drivers: dma: dma_nxp_sof_host_dma: do cache WB after HOST_TO_MEMORY copy

SOF is designed with the idea that the data transfer
between the host memory and local memory is performed via
DMA. This is not true for imx platform in which the DSP
performs this operation.

Because of the aforementioned design, SOF performs a
cache invalidation operation on the destination memory
region before data is copied further down the pipeline.

For some imx platforms, the destination memory region is
cacheable. As such, some of the data transferred from the
host memory region is held entirely in cache, which means
the RAM and the cache have different data for the same
memory region.

In such cases, performing cache invalidation forces
the DSP to fetch data from RAM instead of the cache, which
means the DSP will read stale data and propagate it further
down the pipeline.

Although not optimal and mostly as a workaround to this issue,
perform a cache WB operation on the destination memory region
to make sure that the cache and the RAM hold the same data.
During the data read operation (to copy it further down the
pipeline) after the aforemention cache invalidation, the DSP
will no longer end up reading stale data.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>