coding guidelines: comply with MISRA C:2012 Rule 12.1. (29155bdd) · Commits · Wenxi XU / zephyr

arch/x86/core/acpi.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -62,9 +62,9 @@ static void find_rsdp(void)
		search_length = 1024;
		z_phys_map((uint8_t **)&search, search_phys, search_length, 0);

		for (size_t i = 0; i < 1024/8; i++) {
		for (size_t i = 0; i < (1024/8); i++) {
		if (search[i] == ACPI_RSDP_SIGNATURE) {
		rsdp_phys = search_phys + i * 8;
		rsdp_phys = search_phys + (i * 8);
		rsdp = (void *)&search[i];
		goto found;
		}
		@@ -81,9 +81,9 @@ static void find_rsdp(void)
		z_phys_map((uint8_t **)&search, search_phys, search_length, 0);

		rsdp_phys = 0U;
		for (size_t i = 0; i < 128*1024/8; i++) {
		for (size_t i = 0; i < ((128*1024)/8); i++) {
		if (search[i] == ACPI_RSDP_SIGNATURE) {
		rsdp_phys = search_phys + i * 8;
		rsdp_phys = search_phys + (i * 8);
		rsdp = (void *)&search[i];
		goto found;
		}
		@@ -154,7 +154,7 @@ void *z_acpi_find_table(uint32_t signature)
		z_phys_map(&mapped_tbl, t_phys, sizeof(*t), 0);
		t = (void *)mapped_tbl;

		if (t->signature == signature && check_sum(t)) {
		if ((t->signature == signature) && check_sum(t)) {
		tbl_found = true;
		break;
		}
		@@ -191,7 +191,7 @@ void *z_acpi_find_table(uint32_t signature)
		z_phys_map(&mapped_tbl, t_phys, sizeof(*t), 0);
		t = (void *)mapped_tbl;

		if (t->signature == signature && check_sum(t)) {
		if ((t->signature == signature) && check_sum(t)) {
		tbl_found = true;
		break;
		}

arch/x86/core/early_serial.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -21,8 +21,8 @@
		* together.
		*/
		static mm_reg_t mmio;
		#define IN(reg) (sys_read32(mmio + (reg) * 4U) & 0xffU)
		#define OUT(reg, val) sys_write32((uint32_t)(val) & 0xffU, mmio + (reg) * 4U)
		#define IN(reg) (sys_read32(mmio + ((reg) * 4U)) & 0xffU)
		#define OUT(reg, val) sys_write32((uint32_t)(val) & 0xffU, mmio + ((reg) * 4U))
		#elif defined(X86_SOC_EARLY_SERIAL_MMIO8_ADDR)
		/* Still other devices use a MMIO region containing packed byte
		* registers

arch/x86/core/fatal.c

+12 −12

Original line number	Diff line number	Diff line
		@@ -57,7 +57,7 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs)
		{
		uintptr_t start, end;

		if (_current == NULL \|\| arch_is_in_isr()) {
		if ((_current == NULL) \|\| arch_is_in_isr()) {
		/* We were servicing an interrupt or in early boot environment
		* and are supposed to be on the interrupt stack */
		uint8_t cpu_id;
		@@ -71,8 +71,8 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs)
		z_interrupt_stacks[cpu_id]);
		end = start + CONFIG_ISR_STACK_SIZE;
		#ifdef CONFIG_USERSPACE
		} else if ((cs & 0x3U) == 0U &&
		(_current->base.user_options & K_USER) != 0) {
		} else if (((cs & 0x3U) == 0U) &&
		((_current->base.user_options & K_USER) != 0)) {
		/* The low two bits of the CS register is the privilege
		* level. It will be 0 in supervisor mode and 3 in user mode
		* corresponding to ring 0 / ring 3.
		@@ -90,7 +90,7 @@ bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs)
		_current->stack_info.size);
		}

		return (addr <= start) \|\| (addr + size > end);
		return (addr <= start) \|\| ((addr + size) > end);
		}
		#endif

		@@ -307,8 +307,8 @@ static void dump_page_fault(z_arch_esf_t *esf)
		LOG_ERR("Linear address not present in page tables");
		}
		LOG_ERR("Access violation: %s thread not allowed to %s",
		(err & PF_US) != 0U ? "user" : "supervisor",
		(err & PF_ID) != 0U ? "execute" : ((err & PF_WR) != 0U ?
		((err & PF_US) != 0U) ? "user" : "supervisor",
		((err & PF_ID) != 0U) ? "execute" : (((err & PF_WR) != 0U) ?
		"write" :
		"read"));
		if ((err & PF_PK) != 0) {
		@@ -415,14 +415,14 @@ void z_x86_page_fault_handler(z_arch_esf_t *esf)
		#ifdef CONFIG_USERSPACE
		for (size_t i = 0; i < ARRAY_SIZE(exceptions); i++) {
		#ifdef CONFIG_X86_64
		if ((void *)esf->rip >= exceptions[i].start &&
		(void *)esf->rip < exceptions[i].end) {
		if (((void *)esf->rip >= exceptions[i].start) &&
		((void *)esf->rip < exceptions[i].end)) {
		esf->rip = (uint64_t)(exceptions[i].fixup);
		return;
		}
		#else
		if ((void *)esf->eip >= exceptions[i].start &&
		(void *)esf->eip < exceptions[i].end) {
		if (((void *)esf->eip >= exceptions[i].start) &&
		((void *)esf->eip < exceptions[i].end)) {
		esf->eip = (unsigned int)(exceptions[i].fixup);
		return;
		}
		@@ -458,8 +458,8 @@ void z_x86_do_kernel_oops(const z_arch_esf_t *esf)
		/* User mode is only allowed to induce oopses and stack check
		* failures via this software interrupt
		*/
		if ((esf->cs & 0x3U) != 0 && !(reason == (unsigned int)K_ERR_KERNEL_OOPS \|\|
		reason == (unsigned int)K_ERR_STACK_CHK_FAIL)) {
		if (((esf->cs & 0x3U) != 0) && !((reason == (unsigned int)K_ERR_KERNEL_OOPS) \|\|
		(reason == (unsigned int)K_ERR_STACK_CHK_FAIL))) {
		reason = (unsigned int)K_ERR_KERNEL_OOPS;
		}
		#endif

arch/x86/core/intel64/irq.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -62,7 +62,7 @@ int z_x86_allocate_vector(unsigned int priority, int prev_vector)
		const int end_vector = vector + (int) VECTORS_PER_PRIORITY;

		for (; vector < end_vector; ++vector) {
		if (prev_vector != 1 && vector == prev_vector) {
		if ((prev_vector != 1) && (vector == prev_vector)) {
		continue;
		}

arch/x86/core/pcie.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -39,7 +39,7 @@ static void pcie_mm_init(void)
		if (m != NULL) {
		size_t n = (m->sdt.length - sizeof(*m)) / sizeof(m->pci_segs[0]);

		for (size_t i = 0; i < n && i < MAX_PCI_BUS_SEGMENTS; i++) {
		for (size_t i = 0; (i < n) && (i < MAX_PCI_BUS_SEGMENTS); i++) {
		size_t size;
		uintptr_t phys_addr;

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