diff --git a/ext/hal/CMakeLists.txt b/ext/hal/CMakeLists.txt index 0b92c4c635eb838839af382b66f853798124f477..07eae45d5245c485f30a38fbc233c0e7dd74968d 100644 --- a/ext/hal/CMakeLists.txt +++ b/ext/hal/CMakeLists.txt @@ -1,5 +1,4 @@ add_subdirectory(cmsis) add_subdirectory(nxp) -add_subdirectory(openisa) add_subdirectory_ifdef(CONFIG_HAS_ALTERA_HAL altera) add_subdirectory(microchip) diff --git a/ext/hal/Kconfig b/ext/hal/Kconfig index 24466605b5f7f0e88077f29a7abd3e216956c33c..ee708b98cf254fabfbddca457bd08b1c5a794843 100644 --- a/ext/hal/Kconfig +++ b/ext/hal/Kconfig @@ -20,6 +20,4 @@ source "ext/hal/nxp/mcux/Kconfig" source "ext/hal/nxp/imx/Kconfig" -source "ext/hal/openisa/vega_sdk_riscv/Kconfig" - endmenu diff --git a/ext/hal/openisa/CMakeLists.txt b/ext/hal/openisa/CMakeLists.txt deleted file mode 100644 index f6f7083bdad7e2f0b348aa8d38541c5b84ea16b2..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -add_subdirectory_ifdef( - CONFIG_VEGA_SDK_HAL - vega_sdk_riscv - ) diff --git a/ext/hal/openisa/vega_sdk_riscv/CMakeLists.txt b/ext/hal/openisa/vega_sdk_riscv/CMakeLists.txt deleted file mode 100644 index 29994f2da58ac8027e3d3c3d3875c512f5e0a10f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# This CMakeLists.txt is being kept deliberately simple for now, since -# the HAL is currently only needed to support one SoC. - -zephyr_include_directories(RISCV) -zephyr_include_directories(devices/RV32M1) - -# The HAL uses a CPU name to expose core-specific features. -# See fsl_device_registers.h and $CPU_RV32M1_{ri5cy,zero_riscy}_features.h -# for details. -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) - zephyr_compile_definitions(CPU_RV32M1_ri5cy) -else() - zephyr_compile_definitions(CPU_RV32M1_zero_riscy) -endif() - -add_subdirectory(devices/RV32M1/drivers) diff --git a/ext/hal/openisa/vega_sdk_riscv/README b/ext/hal/openisa/vega_sdk_riscv/README deleted file mode 100644 index a25c539d68de6f69b320cf213ae996b8b3ba5326..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/README +++ /dev/null @@ -1,42 +0,0 @@ -VEGA SDK -######## - -Origin: - OpenISA RV32M1 SDK for RISC-V - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv - -Status: - This includes portions of the initial release of the RV32M1 SDK for - the RISC-V cores. - -Purpose: - Provides device header files and bare metal peripheral drivers for - the RV32M1 SoC. Zephyr shim drivers are built on top of these imported - drivers to adapt the RV32M1 SDK APIs to Zephyr APIs. - -Description: - This package is an extract from the upstream RV32M1 SDK that contains - only the files needed for Zephyr. - -Dependencies: - None - -URL: - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv - -commit: - 365b1060f0947d5250c07b3eebdbc9e54cd0246e - -Maintained-by: - External - -License: - BSD-3-Clause - -License Link: - https://spdx.org/licenses/BSD-3-Clause.html - -Patch List: - No changes were made to any imported source files. - Additional Zephyr-specific build system files were added (Kconfig files, - CMakeLists.txt, etc.) diff --git a/ext/hal/openisa/vega_sdk_riscv/RISCV/core_riscv32.h b/ext/hal/openisa/vega_sdk_riscv/RISCV/core_riscv32.h deleted file mode 100644 index fa0e9eeb28bff2acbb467243f85b045835e6101e..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/RISCV/core_riscv32.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef __CORE_RISCV32_H__ -#define __CORE_RISCV32_H__ - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define RISCV32 - -#if defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -#if defined ( __GNUC__ ) - -#define __BKPT(x) __ASM("ebreak") - -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("nop"); -} - -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("nop"); -} - -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("csrsi mstatus, 8"); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("csrci mstatus, 8"); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - return __builtin_bswap32(value); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - return __builtin_bswap16(value); -} - -#else - #error Unknown compiler -#endif - -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_RISCV32_H__ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h deleted file mode 100644 index 0264b6f3681f2b3da72f84952bf32ed88e88aecc..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h +++ /dev/null @@ -1,24026 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_ri5cy -** RV32M1_ri5cy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** CMSIS Peripheral Access Layer for RV32M1_ri5cy -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_ri5cy.h - * @version 1.0 - * @date 2018-10-02 - * @brief CMSIS Peripheral Access Layer for RV32M1_ri5cy - * - * CMSIS Peripheral Access Layer for RV32M1_ri5cy - */ - -#ifndef _RV32M1_RI5CY_H_ -#define _RV32M1_RI5CY_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 82 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Device specific interrupts */ - DMA0_0_4_8_12_IRQn = 0, /**< DMA0 channel 0/4/8/12 transfer complete */ - DMA0_1_5_9_13_IRQn = 1, /**< DMA0 channel 1/5/9/13 transfer complete */ - DMA0_2_6_10_14_IRQn = 2, /**< DMA0 channel 2/6/10/14 transfer complete */ - DMA0_3_7_11_15_IRQn = 3, /**< DMA0 channel 3/7/11/15 transfer complete */ - DMA0_Error_IRQn = 4, /**< DMA0 channel 0-15 error interrupt */ - CMC0_IRQn = 5, /**< Core Mode Controller 0 */ - MUA_IRQn = 6, /**< MU Side A interrupt */ - USB0_IRQn = 7, /**< USB0 interrupt */ - USDHC0_IRQn = 8, /**< SDHC0 interrupt */ - I2S0_IRQn = 9, /**< I2S0 interrupt */ - FLEXIO0_IRQn = 10, /**< FLEXIO0 */ - EMVSIM0_IRQn = 11, /**< EMVSIM0 interrupt */ - LPIT0_IRQn = 12, /**< LPIT0 interrupt */ - LPSPI0_IRQn = 13, /**< LPSPI0 single interrupt vector for all sources */ - LPSPI1_IRQn = 14, /**< LPSPI1 single interrupt vector for all sources */ - LPI2C0_IRQn = 15, /**< LPI2C0 interrupt */ - LPI2C1_IRQn = 16, /**< LPI2C1 interrupt */ - LPUART0_IRQn = 17, /**< LPUART0 status and error */ - PORTA_IRQn = 18, /**< PORTA Pin detect */ - TPM0_IRQn = 19, /**< TPM0 single interrupt vector for all sources */ - ADC0_IRQn = 21, /**< LPADC0 interrupt */ - LPDAC0_IRQn = 20, /**< DAC0 interrupt */ - LPCMP0_IRQn = 22, /**< LPCMP0 interrupt */ - RTC_IRQn = 23, /**< RTC Alarm interrupt */ - INTMUX0_0_IRQn = 24, /**< INTMUX0 channel0 interrupt */ - INTMUX0_1_IRQn = 25, /**< INTMUX0 channel1 interrupt */ - INTMUX0_2_IRQn = 26, /**< INTMUX0 channel2 interrupt */ - INTMUX0_3_IRQn = 27, /**< INTMUX0 channel3 interrupt */ - INTMUX0_4_IRQn = 28, /**< INTMUX0 channel4 interrupt */ - INTMUX0_5_IRQn = 29, /**< INTMUX0 channel5 interrupt */ - INTMUX0_6_IRQn = 30, /**< INTMUX0 channel6 interrupt */ - INTMUX0_7_IRQn = 31, /**< INTMUX0 channel7 interrupt */ - EWM_IRQn = 32, /**< EWM interrupt */ - FTFE_Command_Complete_IRQn = 33, /**< FTFE interrupt */ - FTFE_Read_Collision_IRQn = 34, /**< FTFE interrupt */ - LLWU0_IRQn = 35, /**< Low leakage wakeup 0 */ - SPM_IRQn = 36, /**< SPM */ - WDOG0_IRQn = 37, /**< WDOG0 interrupt */ - SCG_IRQn = 38, /**< SCG interrupt */ - LPTMR0_IRQn = 39, /**< LPTMR0 interrupt */ - LPTMR1_IRQn = 40, /**< LPTMR1 interrupt */ - TPM1_IRQn = 41, /**< TPM1 single interrupt vector for all sources */ - TPM2_IRQn = 42, /**< TPM2 single interrupt vector for all sources */ - LPI2C2_IRQn = 43, /**< LPI2C2 interrupt */ - LPSPI2_IRQn = 44, /**< LPSPI2 single interrupt vector for all sources */ - LPUART1_IRQn = 45, /**< LPUART1 status and error */ - LPUART2_IRQn = 46, /**< LPUART2 status and error */ - PORTB_IRQn = 47, /**< PORTB Pin detect */ - PORTC_IRQn = 48, /**< PORTC Pin detect */ - PORTD_IRQn = 49, /**< PORTD Pin detect */ - CAU3_Task_Complete_IRQn = 50, /**< Cryptographic Acceleration Unit version 3 Task Complete */ - CAU3_Security_Violation_IRQn = 51, /**< Cryptographic Acceleration Unit version 3 Security Violation */ - TRNG_IRQn = 52, /**< TRNG interrupt */ - LPIT1_IRQn = 53, /**< LPIT1 interrupt */ - LPTMR2_IRQn = 54, /**< LPTMR2 interrupt */ - TPM3_IRQn = 55, /**< TPM3 single interrupt vector for all sources */ - LPI2C3_IRQn = 56, /**< LPI2C3 interrupt */ - LPSPI3_IRQn = 57, /**< LPSPI3 single interrupt vector for all sources */ - LPUART3_IRQn = 58, /**< LPUART3 status and error */ - PORTE_IRQn = 59, /**< PORTE Pin detect */ - LPCMP1_IRQn = 60, /**< LPCMP1 interrupt */ - RF0_0_IRQn = 61, /**< RF0 interrupt 0 */ - RF0_1_IRQn = 62, /**< RF0 interrupt 1 */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_riscv32.h" /* Core Peripheral Access Layer */ -#include "system_RV32M1_ri5cy.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup edma_request - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the DMA hardware request - * - * Defines the enumeration for the DMA hardware request collections. - */ -typedef enum _dma_request_source -{ - kDmaRequestMux0LLWU0 = 0|0x100U, /**< LLWU0 Wakeup */ - kDmaRequestMux0LPTMR0 = 1|0x100U, /**< LPTMR0 Trigger */ - kDmaRequestMux0LPTMR1 = 2|0x100U, /**< LPTMR1 Trigger */ - kDmaRequestMux0TPM0Channel0 = 3|0x100U, /**< TPM0 Channel 0 */ - kDmaRequestMux0TPM0Channel1 = 4|0x100U, /**< TPM0 Channel 1 */ - kDmaRequestMux0TPM0Channel2 = 5|0x100U, /**< TPM0 Channel 2 */ - kDmaRequestMux0TPM0Channel3 = 6|0x100U, /**< TPM0 Channel 3 */ - kDmaRequestMux0TPM0Channel4 = 7|0x100U, /**< TPM0 Channel 4 */ - kDmaRequestMux0TPM0Channel5 = 8|0x100U, /**< TPM0 Channel 5 */ - kDmaRequestMux0TPM0Overflow = 9|0x100U, /**< TPM0 Overflow */ - kDmaRequestMux0TPM1Channel0 = 10|0x100U, /**< TPM1 Channel 0 */ - kDmaRequestMux0TPM1Channel1 = 11|0x100U, /**< TPM1 Channel 1 */ - kDmaRequestMux0TPM1Overflow = 12|0x100U, /**< TPM1 Overflow */ - kDmaRequestMux0TPM2Channel0 = 13|0x100U, /**< TPM2 Channel 0 */ - kDmaRequestMux0TPM2Channel1 = 14|0x100U, /**< TPM2 Channel 1 */ - kDmaRequestMux0TPM2Channel2 = 15|0x100U, /**< TPM2 Channel 2 */ - kDmaRequestMux0TPM2Channel3 = 16|0x100U, /**< TPM2 Channel 3 */ - kDmaRequestMux0TPM2Channel4 = 17|0x100U, /**< TPM2 Channel 4 */ - kDmaRequestMux0TPM2Channel5 = 18|0x100U, /**< TPM2 Channel 5 */ - kDmaRequestMux0TPM2Overflow = 19|0x100U, /**< TPM2 Overflow */ - kDmaRequestMux0EMVSIM0Rx = 20|0x100U, /**< EMVSIM0 Receive */ - kDmaRequestMux0EMVSIM0Tx = 21|0x100U, /**< EMVSIM0 Transmit */ - kDmaRequestMux0FLEXIO0Channel0 = 22|0x100U, /**< FLEXIO0 Channel 0 */ - kDmaRequestMux0FLEXIO0Channel1 = 23|0x100U, /**< FLEXIO0 Channel 1 */ - kDmaRequestMux0FLEXIO0Channel2 = 24|0x100U, /**< FLEXIO0 Channel 2 */ - kDmaRequestMux0FLEXIO0Channel3 = 25|0x100U, /**< FLEXIO0 Channel 3 */ - kDmaRequestMux0FLEXIO0Channel4 = 26|0x100U, /**< FLEXIO0 Channel 4 */ - kDmaRequestMux0FLEXIO0Channel5 = 27|0x100U, /**< FLEXIO0 Channel 5 */ - kDmaRequestMux0FLEXIO0Channel6 = 28|0x100U, /**< FLEXIO0 Channel 6 */ - kDmaRequestMux0FLEXIO0Channel7 = 29|0x100U, /**< FLEXIO0 Channel 7 */ - kDmaRequestMux0LPI2C0Rx = 30|0x100U, /**< LPI2C0 Receive */ - kDmaRequestMux0LPI2C0Tx = 31|0x100U, /**< LPI2C0 Transmit */ - kDmaRequestMux0LPI2C1Rx = 32|0x100U, /**< LPI2C1 Receive */ - kDmaRequestMux0LPI2C1Tx = 33|0x100U, /**< LPI2C1 Transmit */ - kDmaRequestMux0LPI2C2Rx = 34|0x100U, /**< LPI2C2 Receive */ - kDmaRequestMux0LPI2C2Tx = 35|0x100U, /**< LPI2C2 Transmit */ - kDmaRequestMux0I2S0Rx = 36|0x100U, /**< I2S0 Receive */ - kDmaRequestMux0I2S0Tx = 37|0x100U, /**< I2S0 Transmit */ - kDmaRequestMux0LPSPI0Rx = 38|0x100U, /**< LPSPI0 Receive */ - kDmaRequestMux0LPSPI0Tx = 39|0x100U, /**< LPSPI0 Transmit */ - kDmaRequestMux0LPSPI1Rx = 40|0x100U, /**< LPSPI1 Receive */ - kDmaRequestMux0LPSPI1Tx = 41|0x100U, /**< LPSPI1 Transmit */ - kDmaRequestMux0LPSPI2Rx = 42|0x100U, /**< LPSPI2 Receive */ - kDmaRequestMux0LPSPI2Tx = 43|0x100U, /**< LPSPI2 Transmit */ - kDmaRequestMux0LPUART0Rx = 44|0x100U, /**< LPUART0 Receive */ - kDmaRequestMux0LPUART0Tx = 45|0x100U, /**< LPUART0 Transmit */ - kDmaRequestMux0LPUART1Rx = 46|0x100U, /**< LPUART1 Receive */ - kDmaRequestMux0LPUART1Tx = 47|0x100U, /**< LPUART1 Transmit */ - kDmaRequestMux0LPUART2Rx = 48|0x100U, /**< LPUART2 Receive */ - kDmaRequestMux0LPUART2Tx = 49|0x100U, /**< LPUART2 Transmit */ - kDmaRequestMux0PORTA = 50|0x100U, /**< PORTA Pin Request */ - kDmaRequestMux0PORTB = 51|0x100U, /**< PORTB Pin Request */ - kDmaRequestMux0PORTC = 52|0x100U, /**< PORTC Pin Request */ - kDmaRequestMux0PORTD = 53|0x100U, /**< PORTD Pin Request */ - kDmaRequestMux0LPADC0 = 54|0x100U, /**< LPADC0 Conversion Complete */ - kDmaRequestMux0LPCMP0 = 55|0x100U, /**< LPCMP0 Comparator Trigger */ - kDmaRequestMux0DAC0 = 56|0x100U, /**< DAC0 Conversion Complete */ - kDmaRequestMux0CAUv3 = 57|0x100U, /**< CAUv3 Data Request */ - kDmaRequestMux0LPTMR2 = 58|0x100U, /**< LPTMR2 Trigger */ - kDmaRequestMux0LPSPI3Rx = 59|0x100U, /**< LPSPI3 Receive */ - kDmaRequestMux0LPSPI3Tx = 60|0x100U, /**< LPSPI3 Transmit */ - kDmaRequestMux0LPUART3Rx = 61|0x100U, /**< LPUART3 Receive */ - kDmaRequestMux0LPUART3Tx = 62|0x100U, /**< LPUART3 Transmit */ - kDmaRequestMux0PORTE = 63|0x100U, /**< PORTE Pin Request */ -} dma_request_source_t; - -/* @} */ - -/*! - * @addtogroup trgmux_source - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the TRGMUX source - * - * Defines the enumeration for the TRGMUX source collections. - */ -typedef enum _trgmux_source -{ - kTRGMUX_Source0Disabled = 0U, /**< Trigger function is disabled */ - kTRGMUX_Source1Disabled = 0U, /**< Trigger function is disabled */ - kTRGMUX_Source0Llwu0 = 1U, /**< LLWU0 trigger is selected */ - kTRGMUX_Source1Llwu1 = 1U, /**< LLWU1 trigger is selected */ - kTRGMUX_Source0Lpit0Channel0 = 2U, /**< LPIT0 Channel 0 is selected */ - kTRGMUX_Source1Lpit1Channel0 = 2U, /**< LPIT1 Channel 0 is selected */ - kTRGMUX_Source0Lpit0Channel1 = 3U, /**< LPIT0 Channel 1 is selected */ - kTRGMUX_Source1Lpit1Channel1 = 3U, /**< LPIT1 Channel 1 is selected */ - kTRGMUX_Source0Lpit0Channel2 = 4U, /**< LPIT0 Channel 2 is selected */ - kTRGMUX_Source1Lpit1Channel2 = 4U, /**< LPIT1 Channel 2 is selected */ - kTRGMUX_Source0Lpit0Channel3 = 5U, /**< LPIT0 Channel 3 is selected */ - kTRGMUX_Source1Lpit1Channel3 = 5U, /**< LPIT1 Channel 3 is selected */ - kTRGMUX_Source0RtcAlarm = 6U, /**< RTC Alarm is selected */ - kTRGMUX_Source1Lptmr2Trigger = 6U, /**< LPTMR2 Trigger is selected */ - kTRGMUX_Source0RtcSeconds = 7U, /**< RTC Seconds is selected */ - kTRGMUX_Source1Tpm3ChannelEven = 7U, /**< TPM3 Channel Even is selected */ - kTRGMUX_Source0Lptmr0Trigger = 8U, /**< LPTMR0 Trigger is selected */ - kTRGMUX_Source1Tpm3ChannelOdd = 8U, /**< TPM3 Channel Odd is selected */ - kTRGMUX_Source0Lptmr1Trigger = 9U, /**< LPTMR1 Trigger is selected */ - kTRGMUX_Source1Tpm3Overflow = 9U, /**< TPM3 Overflow is selected */ - kTRGMUX_Source0Tpm0ChannelEven = 10U, /**< TPM0 Channel Even is selected */ - kTRGMUX_Source1Lpi2c3MasterStop = 10U, /**< LPI2C3 Master Stop is selected */ - kTRGMUX_Source0Tpm0ChannelOdd = 11U, /**< TPM0 Channel Odd is selected */ - kTRGMUX_Source1Lpi2c3SlaveStop = 11U, /**< LPI2C3 Slave Stop is selected */ - kTRGMUX_Source0Tpm0Overflow = 12U, /**< TPM0 Overflow is selected */ - kTRGMUX_Source1Lpspi3Frame = 12U, /**< LPSPI3 Frame is selected */ - kTRGMUX_Source0Tpm1ChannelEven = 13U, /**< TPM1 Channel Even is selected */ - kTRGMUX_Source1Lpspi3RX = 13U, /**< LPSPI3 Rx is selected */ - kTRGMUX_Source0Tpm1ChannelOdd = 14U, /**< TPM1 Channel Odd is selected */ - kTRGMUX_Source1Lpuart3RxData = 14U, /**< LPUART3 Rx Data is selected */ - kTRGMUX_Source0Tpm1Overflow = 15U, /**< TPM1 Overflow is selected */ - kTRGMUX_Source1Lpuart3RxIdle = 15U, /**< LPUART3 Rx Idle is selected */ - kTRGMUX_Source0Tpm2ChannelEven = 16U, /**< TPM2 Channel Even is selected */ - kTRGMUX_Source1Lpuart3TxData = 16U, /**< LPUART3 Tx Data is selected */ - kTRGMUX_Source0Tpm2ChannelOdd = 17U, /**< TPM2 Channel Odd is selected */ - kTRGMUX_Source1PortEPinTrigger = 17U, /**< PORTE Pin Trigger is selected */ - kTRGMUX_Source0Tpm2Overflow = 18U, /**< TPM2 Overflow is selected */ - kTRGMUX_Source1Lpcmp1Output = 18U, /**< LPCMP1 Output is selected */ - kTRGMUX_Source0FlexIO0Timer0 = 19U, /**< FlexIO0 Timer 0 is selected */ - kTRGMUX_Source1RtcAlarm = 19U, /**< RTC Alarm is selected */ - kTRGMUX_Source0FlexIO0Timer1 = 20U, /**< FlexIO0 Timer 1 is selected */ - kTRGMUX_Source1RtcSeconds = 20U, /**< RTC Seconds is selected */ - kTRGMUX_Source0FlexIO0Timer2 = 21U, /**< FlexIO0 Timer 2 is selected */ - kTRGMUX_Source1Lptmr0Trigger = 21U, /**< LPTMR0 Trigger is selected */ - kTRGMUX_Source0FlexIO0Timer3 = 22U, /**< FlexIO0 Timer 3 is selected */ - kTRGMUX_Source1Lptmr1Trigger = 22U, /**< LPTMR1 Trigger is selected */ - kTRGMUX_Source0FlexIO0Timer4 = 23U, /**< FLexIO0 Timer 4 is selected */ - kTRGMUX_Source1Tpm1ChannelEven = 23U, /**< TPM1 Channel Even is selected */ - kTRGMUX_Source0FlexIO0Timer5 = 24U, /**< FlexIO0 Timer 5 is selected */ - kTRGMUX_Source1Tpm1ChannelOdd = 24U, /**< TPM1 Channel Odd is selected */ - kTRGMUX_Source0FlexIO0Timer6 = 25U, /**< FlexIO0 Timer 6 is selected */ - kTRGMUX_Source1Tpm1Overflow = 25U, /**< TPM1 Overflow is selected */ - kTRGMUX_Source0FlexIO0Timer7 = 26U, /**< FlexIO0 Timer 7 is selected */ - kTRGMUX_Source1Tpm2ChannelEven = 26U, /**< TPM2 Channel Even is selected */ - kTRGMUX_Source0Lpi2c0MasterStop = 27U, /**< LPI2C0 Master Stop is selected */ - kTRGMUX_Source1Tpm2ChannelOdd = 27U, /**< TPM2 Channel Odd is selected */ - kTRGMUX_Source0Lpi2c0SlaveStop = 28U, /**< LPI2C0 Slave Stop is selected */ - kTRGMUX_Source1Tpm2Overflow = 28U, /**< TPM2 Overflow is selected */ - kTRGMUX_Source0Lpi2c1MasterStop = 29U, /**< LPI2C1 Master Stop is selected */ - kTRGMUX_Source1FlexIO0Timer0 = 29U, /**< FlexIO0 Timer 0 is selected */ - kTRGMUX_Source0Lpi2c1SlaveStop = 30U, /**< LPI2C1 Slave Stop is selected */ - kTRGMUX_Source1FlexIO0Timer1 = 30U, /**< FlexIO0 Timer 1 is selected */ - kTRGMUX_Source0Lpi2c2MasterStop = 31U, /**< LPI2C2 Master Stop is selected */ - kTRGMUX_Source1FlexIO0Timer2 = 31U, /**< FlexIO0 Timer 2 is selected */ - kTRGMUX_Source0Lpi2c2SlaveStop = 32U, /**< LPI2C2 Slave Stop is selected */ - kTRGMUX_Source1FlexIO0Timer3 = 32U, /**< FlexIO0 Timer 3 is selected */ - kTRGMUX_Source0Sai0Rx = 33U, /**< SAI0 Rx Frame Sync is selected */ - kTRGMUX_Source1FlexIO0Timer4 = 33U, /**< FLexIO0 Timer 4 is selected */ - kTRGMUX_Source0Sai0Tx = 34U, /**< SAI0 Tx Frame Sync is selected */ - kTRGMUX_Source1FlexIO0Timer5 = 34U, /**< FlexIO0 Timer 5 is selected */ - kTRGMUX_Source0Lpspi0Frame = 35U, /**< LPSPI0 Frame is selected */ - kTRGMUX_Source1FlexIO0Timer6 = 35U, /**< FlexIO0 Timer 6 is selected */ - kTRGMUX_Source0Lpspi0Rx = 36U, /**< LPSPI0 Rx is selected */ - kTRGMUX_Source1FlexIO0Timer7 = 36U, /**< FlexIO0 Timer 7 is selected */ - kTRGMUX_Source0Lpspi1Frame = 37U, /**< LPSPI1 Frame is selected */ - kTRGMUX_Source1Lpi2c0MasterStop = 37U, /**< LPI2C0 Master Stop is selected */ - kTRGMUX_Source0Lpspi1Rx = 38U, /**< LPSPI1 Rx is selected */ - kTRGMUX_Source1Lpi2c0SlaveStop = 38U, /**< LPI2C0 Slave Stop is selected */ - kTRGMUX_Source0Lpspi2Frame = 39U, /**< LPSPI2 Frame is selected */ - kTRGMUX_Source1Lpi2c1MasterStop = 39U, /**< LPI2C1 Master Stop is selected */ - kTRGMUX_Source0Lpspi2RX = 40U, /**< LPSPI2 Rx is selected */ - kTRGMUX_Source1Lpi2c1SlaveStop = 40U, /**< LPI2C1 Slave Stop is selected */ - kTRGMUX_Source0Lpuart0RxData = 41U, /**< LPUART0 Rx Data is selected */ - kTRGMUX_Source1Lpi2c2MasterStop = 41U, /**< LPI2C2 Master Stop is selected */ - kTRGMUX_Source0Lpuart0RxIdle = 42U, /**< LPUART0 Rx Idle is selected */ - kTRGMUX_Source1Lpi2c2SlaveStop = 42U, /**< LPI2C2 Slave Stop is selected */ - kTRGMUX_Source0Lpuart0TxData = 43U, /**< LPUART0 Tx Data is selected */ - kTRGMUX_Source1Sai0Rx = 43U, /**< SAI0 Rx Frame Sync is selected */ - kTRGMUX_Source0Lpuart1RxData = 44U, /**< LPUART1 Rx Data is selected */ - kTRGMUX_Source1Sai0Tx = 44U, /**< SAI0 Tx Frame Sync is selected */ - kTRGMUX_Source0Lpuart1RxIdle = 45U, /**< LPUART1 Rx Idle is selected */ - kTRGMUX_Source1Lpspi0Frame = 45U, /**< LPSPI0 Frame is selected */ - kTRGMUX_Source0Lpuart1TxData = 46U, /**< LPUART1 TX Data is selected */ - kTRGMUX_Source1Lpspi0Rx = 46U, /**< LPSPI0 Rx is selected */ - kTRGMUX_Source0Lpuart2RxData = 47U, /**< LPUART2 RX Data is selected */ - kTRGMUX_Source1Lpspi1Frame = 47U, /**< LPSPI1 Frame is selected */ - kTRGMUX_Source0Lpuart2RxIdle = 48U, /**< LPUART2 RX Idle is selected */ - kTRGMUX_Source1Lpspi1Rx = 48U, /**< LPSPI1 Rx is selected */ - kTRGMUX_Source0Lpuart2TxData = 49U, /**< LPUART2 TX Data is selected */ - kTRGMUX_Source1Lpspi2Frame = 49U, /**< LPSPI2 Frame is selected */ - kTRGMUX_Source0Usb0Frame = 50U, /**< USB0 Start of Frame is selected */ - kTRGMUX_Source1Lpspi2RX = 50U, /**< LPSPI2 Rx is selected */ - kTRGMUX_Source0PortAPinTrigger = 51U, /**< PORTA Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0RxData = 51U, /**< LPUART0 Rx Data is selected */ - kTRGMUX_Source0PortBPinTrigger = 52U, /**< PORTB Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0RxIdle = 52U, /**< LPUART0 Rx Idle is selected */ - kTRGMUX_Source0PortCPinTrigger = 53U, /**< PORTC Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0TxData = 53U, /**< LPUART0 Tx Data is selected */ - kTRGMUX_Source0PortDPinTrigger = 54U, /**< PORTD Pin Trigger is selected */ - kTRGMUX_Source1Lpuart1RxData = 54U, /**< LPUART1 Rx Data is selected */ - kTRGMUX_Source0Lpcmp0Output = 55U, /**< LPCMP0 Output is selected */ - kTRGMUX_Source1Lpuart1RxIdle = 55U, /**< LPUART1 Rx Idle is selected */ - kTRGMUX_Source0Lpi2c3MasterStop = 56U, /**< LPI2C3 Master Stop is selected */ - kTRGMUX_Source1Lpuart1TxData = 56U, /**< LPUART1 TX Data is selected */ - kTRGMUX_Source0Lpi2c3SlaveStop = 57U, /**< LPI2C3 Slave Stop is selected */ - kTRGMUX_Source1Lpuart2RxData = 57U, /**< LPUART2 RX Data is selected */ - kTRGMUX_Source0Lpspi3Frame = 58U, /**< LPSPI3 Frame is selected */ - kTRGMUX_Source1Lpuart2RxIdle = 58U, /**< LPUART2 RX Idle is selected */ - kTRGMUX_Source0Lpspi3Rx = 59U, /**< LPSPI3 Rx Data is selected */ - kTRGMUX_Source1Lpuart2TxData = 59U, /**< LPUART2 TX Data is selected */ - kTRGMUX_Source0Lpuart3RxData = 60U, /**< LPUART3 Rx Data is selected */ - kTRGMUX_Source1PortAPinTrigger = 60U, /**< PORTA Pin Trigger is selected */ - kTRGMUX_Source0Lpuart3RxIdle = 61U, /**< LPUART3 Rx Idle is selected */ - kTRGMUX_Source1PortBPinTrigger = 61U, /**< PORTB Pin Trigger is selected */ - kTRGMUX_Source0Lpuart3TxData = 62U, /**< LPUART3 Tx Data is selected */ - kTRGMUX_Source1PortCPinTrigger = 62U, /**< PORTC Pin Trigger is selected */ - kTRGMUX_Source0PortEPinTrigger = 63U, /**< PORTE Pin Trigger is selected */ - kTRGMUX_Source1PortDPinTrigger = 63U, /**< PORTD Pin Trigger is selected */ -} trgmux_source_t; - -/* @} */ - -/*! - * @brief Enumeration for the TRGMUX device - * - * Defines the enumeration for the TRGMUX device collections. - */ -typedef enum _trgmux_device -{ - kTRGMUX_Trgmux0Dmamux0 = 0U, /**< DMAMUX0 device trigger input */ - kTRGMUX_Trgmux1Dmamux1 = 0U, /**< DMAMUX1 device trigger input */ - kTRGMUX_Trgmux0Lpit0 = 1U, /**< LPIT0 device trigger input */ - kTRGMUX_Trgmux1Lpit1 = 1U, /**< LPIT1 device trigger input */ - kTRGMUX_Trgmux0Tpm0 = 2U, /**< TPM0 device trigger input */ - kTRGMUX_Trgmux1Tpm3 = 2U, /**< TPM3 device trigger input */ - kTRGMUX_Trgmux0Tpm1 = 3U, /**< TPM1 device trigger input */ - kTRGMUX_Trgmux1Lpi2c3 = 3U, /**< LPI2C3 device trigger input */ - kTRGMUX_Trgmux0Tpm2 = 4U, /**< TPM2 device trigger input */ - kTRGMUX_Trgmux1Lpspi3 = 4U, /**< LPSPI3 device trigger input */ - kTRGMUX_Trgmux0Flexio0 = 5U, /**< FLEXIO0 device trigger input */ - kTRGMUX_Trgmux1Lpuart3 = 5U, /**< LPUART3 device trigger input */ - kTRGMUX_Trgmux0Lpi2c0 = 6U, /**< LPI2C0 device trigger input */ - kTRGMUX_Trgmux1Lpcmp1 = 6U, /**< LPCMP1 device trigger input */ - kTRGMUX_Trgmux0Lpi2c1 = 7U, /**< LPI2C1 device trigger input */ - kTRGMUX_Trgmux1Dmamux0 = 7U, /**< DMAMUX0 device trigger input */ - kTRGMUX_Trgmux0Lpi2c2 = 8U, /**< LPI2C2 device trigger input */ - kTRGMUX_Trgmux1Lpit0 = 8U, /**< LPIT0 device trigger input */ - kTRGMUX_Trgmux0Lpspi0 = 9U, /**< LPSPI0 device trigger input */ - kTRGMUX_Trgmux1Tpm0 = 9U, /**< TPM0 device trigger input */ - kTRGMUX_Trgmux0Lpspi1 = 10U, /**< LPSPI1 device trigger input */ - kTRGMUX_Trgmux1Tpm1 = 10U, /**< TPM1 device trigger input */ - kTRGMUX_Trgmux0Lpspi2 = 11U, /**< LPSPI2 device trigger input */ - kTRGMUX_Trgmux1Tpm2 = 11U, /**< TPM2 device trigger input */ - kTRGMUX_Trgmux0Lpuart0 = 12U, /**< LPUART0 device trigger input */ - kTRGMUX_Trgmux1Flexio0 = 12U, /**< FLEXIO0 device trigger input */ - kTRGMUX_Trgmux0Lpuart1 = 13U, /**< LPUART1 device trigger input */ - kTRGMUX_Trgmux1Lpi2c0 = 13U, /**< LPI2C0 device trigger input */ - kTRGMUX_Trgmux0Lpuart2 = 14U, /**< LPUART2 device trigger input */ - kTRGMUX_Trgmux1Lpi2c1 = 14U, /**< LPI2C1 device trigger input */ - kTRGMUX_Trgmux0Adc0 = 15U, /**< ADC0 device trigger input */ - kTRGMUX_Trgmux1Lpi2c2 = 15U, /**< LPI2C2 device trigger input */ - kTRGMUX_Trgmux0Lpcmp0 = 16U, /**< LPCMP0 device trigger input */ - kTRGMUX_Trgmux1Lpspi0 = 16U, /**< LPSPI0 device trigger input */ - kTRGMUX_Trgmux0Dac0 = 17U, /**< DAC0 device trigger input */ - kTRGMUX_Trgmux1Lpspi1 = 17U, /**< LPSPI1 device trigger input */ - kTRGMUX_Trgmux0Dmamux1 = 18U, /**< DMAMUX1 device trigger input */ - kTRGMUX_Trgmux1Lpspi2 = 18U, /**< LPSPI2 device trigger input */ - kTRGMUX_Trgmux0Lpit1 = 19U, /**< LPIT1 device trigger input */ - kTRGMUX_Trgmux1Lpuart0 = 19U, /**< LPUART0 device trigger input */ - kTRGMUX_Trgmux0Tpm3 = 20U, /**< TPM3 device trigger input */ - kTRGMUX_Trgmux1Lpuart1 = 20U, /**< LPUART1 device trigger input */ - kTRGMUX_Trgmux0Lpi2c3 = 21U, /**< LPI2C3 device trigger input */ - kTRGMUX_Trgmux1Lpuart2 = 21U, /**< LPUART2 device trigger input */ - kTRGMUX_Trgmux0Lpspi3 = 22U, /**< LPSPI3 device trigger input */ - kTRGMUX_Trgmux1Adc0 = 22U, /**< ADC0 device trigger input */ - kTRGMUX_Trgmux0Lpuart3 = 23U, /**< LPUART3 device trigger input */ - kTRGMUX_Trgmux1Lpcmp0 = 23U, /**< LPCMP0 device trigger input */ - kTRGMUX_Trgmux0Lpcmp1 = 24U, /**< LPCMP1 device trigger input */ - kTRGMUX_Trgmux1Lpdac0 = 24U, /**< LPDAC0 device trigger input */ -} trgmux_device_t; - -/* @} */ - -/*! - * @addtogroup xrdc_mapping - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the XRDC mapping - * - * Defines the structure for the XRDC resource collections. - */ - -typedef enum _xrdc_master -{ - kXRDC_MasterCM4CodeBus = 0U, /**< CM4 C-BUS */ - kXRDC_MasterCM4SystemBus = 1U, /**< CM4 S-BUS */ - kXRDC_MasterRI5CYCodeBus = 16U, /**< RI5CY C-BUS */ - kXRDC_MasterRI5CYSystemBus = 17U, /**< RI5CY S-BUS */ - kXRDC_MasterEdma0 = 2U, /**< EDMA0 */ - kXRDC_MasterUsdhc = 3U, /**< USDHC */ - kXRDC_MasterUsb = 4U, /**< USB */ - kXRDC_MasterCM0P = 32U, /**< CM0P */ - kXRDC_MasterEdma1 = 33U, /**< EDMA1 */ - kXRDC_MasterCau3 = 34U, /**< CAU3 */ - kXRDC_MasterZERORISCYCodeBus = 35U, /**< ZERO RISCY C-BUS */ - kXRDC_MasterZERORISCYSystemBus = 36U, /**< ZERO RISCY S-BUS */ -} xrdc_master_t; - -/* @} */ - -typedef enum _xrdc_mem -{ - kXRDC_MemMrc0_0 = 0U, /**< MRC0 Memory 0 */ - kXRDC_MemMrc0_1 = 1U, /**< MRC0 Memory 1 */ - kXRDC_MemMrc0_2 = 2U, /**< MRC0 Memory 2 */ - kXRDC_MemMrc0_3 = 3U, /**< MRC0 Memory 3 */ - kXRDC_MemMrc0_4 = 4U, /**< MRC0 Memory 4 */ - kXRDC_MemMrc0_5 = 5U, /**< MRC0 Memory 5 */ - kXRDC_MemMrc0_6 = 6U, /**< MRC0 Memory 6 */ - kXRDC_MemMrc0_7 = 7U, /**< MRC0 Memory 7 */ - kXRDC_MemMrc1_0 = 16U, /**< MRC1 Memory 0 */ - kXRDC_MemMrc1_1 = 17U, /**< MRC1 Memory 1 */ - kXRDC_MemMrc1_2 = 18U, /**< MRC1 Memory 2 */ - kXRDC_MemMrc1_3 = 19U, /**< MRC1 Memory 3 */ - kXRDC_MemMrc1_4 = 20U, /**< MRC1 Memory 4 */ - kXRDC_MemMrc1_5 = 21U, /**< MRC1 Memory 5 */ - kXRDC_MemMrc1_6 = 22U, /**< MRC1 Memory 6 */ - kXRDC_MemMrc1_7 = 23U, /**< MRC1 Memory 7 */ -} xrdc_mem_t; - -typedef enum _xrdc_periph -{ - kXRDC_PeriphMscm = 1U, /**< Miscellaneous System Control Module (MSCM) */ - kXRDC_PeriphDma0 = 8U, /**< Direct Memory Access 0 (DMA0) controller */ - kXRDC_PeriphDma0Tcd = 9U, /**< Direct Memory Access 0 (DMA0) controller transfer control descriptors */ - kXRDC_PeriphFlexBus = 12U, /**< External Bus Interface(FlexBus) */ - kXRDC_PeriphXrdcMgr = 20U, /**< Extended Resource Domain Controller (XRDC) MGR */ - kXRDC_PeriphXrdcMdac = 21U, /**< Extended Resource Domain Controller (XRDC) MDAC */ - kXRDC_PeriphXrdcPac = 22U, /**< Extended Resource Domain Controller (XRDC) PAC */ - kXRDC_PeriphXrdcMrc = 23U, /**< Extended Resource Domain Controller (XRDC) MRC */ - kXRDC_PeriphSema420 = 27U, /**< Semaphore Unit 0 (SEMA420) */ - kXRDC_PeriphCmc0 = 32U, /**< Core Mode Controller (CMC) */ - kXRDC_PeriphDmamux0 = 33U, /**< Direct Memory Access Multiplexer 0 (DMAMUX0) */ - kXRDC_PeriphEwm = 34U, /**< External Watchdog Monitor (EWM) */ - kXRDC_PeriphFtfe = 35U, /**< Flash Memory Module (FTFE) */ - kXRDC_PeriphLlwu0 = 36U, /**< Low Leakage Wake-up Unit 0 (LLWU0) */ - kXRDC_PeriphMua = 37U, /**< Message Unit Side A (MU-A) */ - kXRDC_PeriphSim = 38U, /**< System Integration Module (SIM) */ - kXRDC_PeriphSimdgo = 39U, /**< System Integration Module - DGO (SIM-DGO) */ - kXRDC_PeriphSpm = 40U, /**< System Power Management (SPM) */ - kXRDC_PeriphTrgmux0 = 41U, /**< Tirgger Multiplexer 0 (TRGMUX0) */ - kXRDC_PeriphWdog0 = 42U, /**< Watchdog 0 (WDOG0) */ - kXRDC_PeriphPcc0 = 43U, /**< Peripheral Clock Controller 0 (PCC0) */ - kXRDC_PeriphScg = 44U, /**< System Clock Generator (SCG) */ - kXRDC_PeriphSrf = 45U, /**< System Register File */ - kXRDC_PeriphVbat = 46U, /**< VBAT Register File */ - kXRDC_PeriphCrc0 = 47U, /**< Cyclic Redundancy Check 0 (CRC0) */ - kXRDC_PeriphLpit0 = 48U, /**< Low-Power Periodic Interrupt Timer 0 (LPIT0) */ - kXRDC_PeriphRtc = 49U, /**< Real Time Clock (RTC) */ - kXRDC_PeriphLptmr0 = 50U, /**< Low-Power Timer 0 (LPTMR0) */ - kXRDC_PeriphLptmr1 = 51U, /**< Low-Power Timer 1 (LPTMR1) */ - kXRDC_PeriphTstmr0 = 52U, /**< Time Stamp Timer 0 (TSTMR0) */ - kXRDC_PeriphTpm0 = 53U, /**< Timer / Pulse Width Modulator Module 0 (TPM0) - 6 channel */ - kXRDC_PeriphTpm1 = 54U, /**< Timer / Pulse Width Modulator Module 1 (TPM1) - 2 channel */ - kXRDC_PeriphTpm2 = 55U, /**< Timer / Pulse Width Modulator Module 2 (TPM2) - 6 channel */ - kXRDC_PeriphEmvsim0 = 56U, /**< Euro Mastercard Visa Secure Identity Module 0 (EMVSIM0) */ - kXRDC_PeriphFlexio0 = 57U, /**< Flexible Input / Output 0 (FlexIO0) */ - kXRDC_PeriphLpi2c0 = 58U, /**< Low-Power Inter-Integrated Circuit 0 (LPI2C0) */ - kXRDC_PeriphLpi2c1 = 59U, /**< Low-Power Inter-Integrated Circuit 1 (LPI2C1) */ - kXRDC_PeriphLpi2c2 = 60U, /**< Low-Power Inter-Integrated Circuit 2 (LPI2C2) */ - kXRDC_PeriphSai0 = 61U, /**< Serial Audio Interface 0 (SAI0) */ - kXRDC_PeriphSdhc0 = 62U, /**< Secure Digital Host Controller 0 (SDHC0) */ - kXRDC_PeriphLpspi0 = 63U, /**< Low-Power Serial Peripheral Interface 0 (LPSPI0) */ - kXRDC_PeriphLpspi1 = 64U, /**< Low-Power Serial Peripheral Interface 1 (LPSPI1) */ - kXRDC_PeriphLpspi2 = 65U, /**< Low-Power Serial Peripheral Interface 2 (LPSPI2) */ - kXRDC_PeriphLpuart0 = 66U, /**< Low-Power Universal Asynchronous Receive / Transmit 0 (LPUART0) */ - kXRDC_PeriphLpuart1 = 67U, /**< Low-Power Universal Asynchronous Receive / Transmit 1 (LPUART1) */ - kXRDC_PeriphLpuart2 = 68U, /**< Low-Power Universal Asynchronous Receive / Transmit 2 (LPUART2) */ - kXRDC_PeriphUsb0 = 69U, /**< Universal Serial Bus 0 (USB0) - Full Speed, Device Only */ - kXRDC_PeriphPortA = 70U, /**< PORTA Multiplex Control */ - kXRDC_PeriphPortB = 71U, /**< PORTB Multiplex Control */ - kXRDC_PeriphPortC = 72U, /**< PORTC Multiplex Control */ - kXRDC_PeriphPortD = 73U, /**< PORTD Multiplex Control */ - kXRDC_PeriphLpadc0 = 74U, /**< Low-Power Analog-to-Digital Converter 0 (LPADC0) */ - kXRDC_PeriphLpcmp0 = 75U, /**< Low-Power Comparator 0 (LPCMP0) */ - kXRDC_PeriphDac0 = 76U, /**< Digital-to-Analog Converter 0 (DAC0) */ - kXRDC_PeriphVref = 77U, /**< Voltage Reference (VREF) */ - kXRDC_PeriphDma1 = 136U, /**< Direct Memory Access 1 (DMA1) controller */ - kXRDC_PeriphDma1Tcd = 137U, /**< Direct Memory Access 1 (DMA1) controller trasfer control descriptors */ - kXRDC_PeriphFgpio1 = 143U, /**< IO Port Alias */ - kXRDC_PeriphSema421 = 155U, /**< Semaphore Unit 1 (SEMA421) */ - kXRDC_PeriphCmc1 = 160U, /**< Core Mode Controller (CMC) */ - kXRDC_PeriphDmamux1 = 161U, /**< Direct Memory Access Mutiplexer 1 (DMAMUX1) */ - kXRDC_PeriphIntmux0 = 162U, /**< Interrupt Multiplexer 0 (INTMUX0) */ - kXRDC_Periphllwu1 = 163U, /**< Low Leakage Wake-up Unit 1 (LLWU1) */ - kXRDC_PeriphMub = 164U, /**< Messaging Unit - Side B (MU-B) */ - kXRDC_PeriphTrgmux1 = 165U, /**< Trigger Multiplexer 1 (TRGMUX1) */ - kXRDC_PeriphWdog1 = 166U, /**< Watchdog 1 (WDOG1) */ - kXRDC_PeriphPcc1 = 167U, /**< Peripheral Clock Controller 1 (PCC1) */ - kXRDC_PeriphCau3 = 168U, /**< Cryptographic Acceleration Unit (CAU3) */ - kXRDC_PeriphTrng = 169U, /**< True Random Number Generator (TRNG) */ - kXRDC_PeriphLpit1 = 170U, /**< Low-Power Periodic Interrupt Timer 1 (LPIT1) */ - kXRDC_PeriphLptmr2 = 171U, /**< Low-Power Timer 2 (LPTMR2) */ - kXRDC_PeriphTstmr1 = 172U, /**< Time Stamp Timer 1 (TSTMR1) */ - kXRDC_PeriphTpm3 = 173U, /**< Timer / Pulse Width Modulation Module 3 (TPM3) - 2 channel */ - kXRDC_PeriphLpi2c3 = 174U, /**< Low-Power Inter-Integrated Circuit 3 (LPI2C3) */ - kXRDC_PeriphRsim = 175U, /**< 2.4GHz Radio (RF2.4G) - RSIM */ - kXRDC_PeriphXcvr = 176U, /**< 2.4GHz Radio (RF2.4G) - XCVR */ - kXRDC_PeriphAnt = 177U, /**< 2.4GHz Radio (RF2.4G) - ANT+ Link Layer */ - kXRDC_PeriphBle = 178U, /**< 2.4GHz Radio (RF2.4G) - Bluetooth Link layer */ - kXRDC_PeriphGfsk = 179U, /**< 2.4GHz Radio (RF2.4G) - Generic Link layer */ - kXRDC_PeriphIeee = 180U, /**< 2.4GHz Radio (RF2.4G) - IEEE 802.15.4 Link Layer */ - kXRDC_PeriphLpspi3 = 181U, /**< Low-Power Serial Peripheral Interface 3 (LPSPI3) */ - kXRDC_PeriphLpuart3 = 182U, /**< Low-Power Universal Asynchronous Receive / Transmit 3 (LPUART3) */ - kXRDC_PeriphPortE = 183U, /**< PORTE Multiplex Control */ - kXRDC_PeriphLpcmp1 = 214U, /**< Low-Power Comparator 1 (LPCMP1) */ -} xrdc_periph_t; - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[8]; - __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[124]; - __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[48]; - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Offset Function Implemented - * 0b0..Offset calibration and offset trimming not implemented. - * 0b1..Offset calibration and offset trimming implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) -#define ADC_CTRL_RSTFIFO_MASK (0x100U) -#define ADC_CTRL_RSTFIFO_SHIFT (8U) -/*! RSTFIFO - Reset FIFO - * 0b0..No effect. - * 0b1..FIFO is reset. - */ -#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ -#define ADC_STAT_RDY_MASK (0x1U) -#define ADC_STAT_RDY_SHIFT (0U) -/*! RDY - Result FIFO Ready Flag - * 0b0..Result FIFO data level not above watermark level. - * 0b1..Result FIFO holding data above watermark level. - */ -#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) -#define ADC_STAT_FOF_MASK (0x2U) -#define ADC_STAT_FOF_SHIFT (1U) -/*! FOF - Result FIFO Overflow Flag - * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) -#define ADC_STAT_TRGACT_MASK (0x30000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b00..Command (sequence) associated with Trigger 0 currently being executed. - * 0b01..Command (sequence) associated with Trigger 1 currently being executed. - * 0b10..Command (sequence) associated with Trigger 2 currently being executed. - * 0b11..Command (sequence) associated with Trigger 3 currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ -#define ADC_IE_FWMIE_MASK (0x1U) -#define ADC_IE_FWMIE_SHIFT (0U) -/*! FWMIE - FIFO Watermark Interrupt Enable - * 0b0..FIFO watermark interrupts are not enabled. - * 0b1..FIFO watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) -#define ADC_IE_FOFIE_MASK (0x2U) -#define ADC_IE_FOFIE_SHIFT (1U) -/*! FOFIE - Result FIFO Overflow Interrupt Enable - * 0b0..FIFO overflow interrupts are not enabled. - * 0b1..FIFO overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ -#define ADC_DE_FWMDE_MASK (0x1U) -#define ADC_DE_FWMDE_SHIFT (0U) -/*! FWMDE - FIFO Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ -#define ADC_CFG_TPRICTRL_MASK (0x1U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion. - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Level 1 (Lowest power setting) - * 0b01..Level 2 - * 0b10..Level 3 - * 0b11..Level 4 (Highest power setting) - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) -#define ADC_CFG_CALOFS_MASK (0x8000U) -#define ADC_CFG_CALOFS_SHIFT (15U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Configure for offset calibration function - */ -#define ADC_CFG_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_CALOFS_SHIFT)) & ADC_CFG_CALOFS_MASK) -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -#define ADC_CFG_VREF1RNG_MASK (0x20000000U) -#define ADC_CFG_VREF1RNG_SHIFT (29U) -/*! VREF1RNG - Enable support for low voltage reference on Option 1 Reference - * 0b0..Configuration required when Voltage Reference Option 1 input is in high voltage range - * 0b1..Configuration required when Voltage Reference Option 1 input is in low voltage range - */ -#define ADC_CFG_VREF1RNG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF1RNG_SHIFT)) & ADC_CFG_VREF1RNG_MASK) -#define ADC_CFG_ADCKEN_MASK (0x80000000U) -#define ADC_CFG_ADCKEN_SHIFT (31U) -/*! ADCKEN - ADC asynchronous clock enable - * 0b0..ADC internal clock is disabled - * 0b1..ADC internal clock is enabled - */ -#define ADC_CFG_ADCKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADCKEN_SHIFT)) & ADC_CFG_ADCKEN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name FCTRL - ADC FIFO Control Register */ -/*! @{ */ -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ -#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FU) -#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U) -#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) -#define ADC_TCTRL_TPRI_MASK (0x300U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b00..Set to highest priority, Level 1 - * 0b01-0b10..Set to corresponding priority level - * 0b11..Set to lowest priority, Level 4 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (4U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B - * 0b00001..Select CH1A or CH1B - * 0b00010..Select CH2A or CH2B - * 0b00011..Select CH3A or CH3B - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB - * 0b11110..Select CH30A or CH30B - * 0b11111..Select CH31A or CH31B - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) -#define ADC_CMDL_ABSEL_MASK (0x20U) -#define ADC_CMDL_ABSEL_SHIFT (5U) -/*! ABSEL - A-side vs. B-side Select - * 0b0..The associated A-side channel is converted. - * 0b1..The associated B-side channel is converted. - */ -#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) -#define ADC_RESFIFO_TSRC_MASK (0x30000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b00..Trigger source 0 initiated this conversion. - * 0b01..Trigger source 1 initiated this conversion. - * 0b10..Trigger source 2 initiated this conversion. - * 0b11..Trigger source 3 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x4004A000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AXBS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer - * @{ - */ - -/** AXBS - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x100 */ - __IO uint32_t PRS; /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */ - uint8_t RESERVED_0[12]; - __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ - uint8_t RESERVED_1[236]; - } SLAVE[5]; - uint8_t RESERVED_0[768]; - __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ - uint8_t RESERVED_1[252]; - __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ - uint8_t RESERVED_2[252]; - __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ - uint8_t RESERVED_3[252]; - __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ - uint8_t RESERVED_4[252]; - __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ - uint8_t RESERVED_5[252]; - __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ -} AXBS_Type; - -/* ---------------------------------------------------------------------------- - -- AXBS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Masks AXBS Register Masks - * @{ - */ - -/*! @name PRS - Priority Slave Registers */ -/*! @{ */ -#define AXBS_PRS_M0_MASK (0x7U) -#define AXBS_PRS_M0_SHIFT (0U) -/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) -#define AXBS_PRS_M1_MASK (0x70U) -#define AXBS_PRS_M1_SHIFT (4U) -/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) -#define AXBS_PRS_M2_MASK (0x700U) -#define AXBS_PRS_M2_SHIFT (8U) -/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) -#define AXBS_PRS_M3_MASK (0x7000U) -#define AXBS_PRS_M3_SHIFT (12U) -/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) -#define AXBS_PRS_M4_MASK (0x70000U) -#define AXBS_PRS_M4_SHIFT (16U) -/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) -#define AXBS_PRS_M5_MASK (0x700000U) -#define AXBS_PRS_M5_SHIFT (20U) -/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. - * 0b000..This master has level 1, or highest, priority when accessing the slave port. - * 0b001..This master has level 2 priority when accessing the slave port. - * 0b010..This master has level 3 priority when accessing the slave port. - * 0b011..This master has level 4 priority when accessing the slave port. - * 0b100..This master has level 5 priority when accessing the slave port. - * 0b101..This master has level 6 priority when accessing the slave port. - * 0b110..This master has level 7 priority when accessing the slave port. - * 0b111..This master has level 8, or lowest, priority when accessing the slave port. - */ -#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) -/*! @} */ - -/* The count of AXBS_PRS */ -#define AXBS_PRS_COUNT (5U) - -/*! @name CRS - Control Register */ -/*! @{ */ -#define AXBS_CRS_PARK_MASK (0x7U) -#define AXBS_CRS_PARK_SHIFT (0U) -/*! PARK - Park - * 0b000..Park on master port M0 - * 0b001..Park on master port M1 - * 0b010..Park on master port M2 - * 0b011..Park on master port M3 - * 0b100..Park on master port M4 - * 0b101..Park on master port M5 - * 0b110..Park on master port M6 - * 0b111..Park on master port M7 - */ -#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) -#define AXBS_CRS_PCTL_MASK (0x30U) -#define AXBS_CRS_PCTL_SHIFT (4U) -/*! PCTL - Parking Control - * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field - * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port - * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state - * 0b11..Reserved - */ -#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) -#define AXBS_CRS_ARB_MASK (0x300U) -#define AXBS_CRS_ARB_SHIFT (8U) -/*! ARB - Arbitration Mode - * 0b00..Fixed priority - * 0b01..Round-robin, or rotating, priority - * 0b10..Reserved - * 0b11..Reserved - */ -#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) -#define AXBS_CRS_HLP_MASK (0x40000000U) -#define AXBS_CRS_HLP_SHIFT (30U) -/*! HLP - Halt Low Priority - * 0b0..The low power mode request has the highest priority for arbitration on this slave port - * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port - */ -#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) -#define AXBS_CRS_RO_MASK (0x80000000U) -#define AXBS_CRS_RO_SHIFT (31U) -/*! RO - Read Only - * 0b0..The slave port's registers are writeable - * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. - */ -#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) -/*! @} */ - -/* The count of AXBS_CRS */ -#define AXBS_CRS_COUNT (5U) - -/*! @name MGPCR0 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR0_AULB_MASK (0x7U) -#define AXBS_MGPCR0_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) -/*! @} */ - -/*! @name MGPCR1 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR1_AULB_MASK (0x7U) -#define AXBS_MGPCR1_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) -/*! @} */ - -/*! @name MGPCR2 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR2_AULB_MASK (0x7U) -#define AXBS_MGPCR2_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) -/*! @} */ - -/*! @name MGPCR3 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR3_AULB_MASK (0x7U) -#define AXBS_MGPCR3_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) -/*! @} */ - -/*! @name MGPCR4 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR4_AULB_MASK (0x7U) -#define AXBS_MGPCR4_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) -/*! @} */ - -/*! @name MGPCR5 - Master General Purpose Control Register */ -/*! @{ */ -#define AXBS_MGPCR5_AULB_MASK (0x7U) -#define AXBS_MGPCR5_AULB_SHIFT (0U) -/*! AULB - Arbitrates On Undefined Length Bursts - * 0b000..No arbitration is allowed during an undefined length burst - * 0b001..Arbitration is allowed at any time during an undefined length burst - * 0b010..Arbitration is allowed after four beats of an undefined length burst - * 0b011..Arbitration is allowed after eight beats of an undefined length burst - * 0b100..Arbitration is allowed after 16 beats of an undefined length burst - * 0b101..Reserved - * 0b110..Reserved - * 0b111..Reserved - */ -#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AXBS_Register_Masks */ - - -/* AXBS - Peripheral instance base addresses */ -/** Peripheral AXBS0 base address */ -#define AXBS0_BASE (0x40004000u) -/** Peripheral AXBS0 base pointer */ -#define AXBS0 ((AXBS_Type *)AXBS0_BASE) -/** Array initializer of AXBS peripheral base addresses */ -#define AXBS_BASE_ADDRS { AXBS0_BASE } -/** Array initializer of AXBS peripheral base pointers */ -#define AXBS_BASE_PTRS { AXBS0 } - -/*! - * @} - */ /* end of group AXBS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAU3 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU3_Peripheral_Access_Layer CAU3 Peripheral Access Layer - * @{ - */ - -/** CAU3 - Register Layout Typedef */ -typedef struct { - __I uint32_t PCT; /**< Processor Core Type, offset: 0x0 */ - __I uint32_t MCFG; /**< Memory Configuration, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DBGCSR; /**< Debug Control/Status Register, offset: 0x20 */ - __IO uint32_t DBGPBR; /**< Debug PC Breakpoint Register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t DBGMCMD; /**< Debug Memory Command Register, offset: 0x30 */ - __IO uint32_t DBGMADR; /**< Debug Memory Address Register, offset: 0x34 */ - __IO uint32_t DBGMDR; /**< Debug Memory Data Register, offset: 0x38 */ - uint8_t RESERVED_3[180]; - __IO uint32_t SEMA4; /**< Semaphore Register, offset: 0xF0 */ - __I uint32_t SMOWNR; /**< Semaphore Ownership Register, offset: 0xF4 */ - uint8_t RESERVED_4[4]; - __IO uint32_t ARR; /**< Address Remap Register, offset: 0xFC */ - uint8_t RESERVED_5[128]; - __IO uint32_t CC_R[30]; /**< CryptoCore General Purpose Registers, array offset: 0x180, array step: 0x4 */ - __IO uint32_t CC_R30; /**< General Purpose R30, offset: 0x1F8 */ - __IO uint32_t CC_R31; /**< General Purpose R31, offset: 0x1FC */ - __IO uint32_t CC_PC; /**< Program Counter, offset: 0x200 */ - __O uint32_t CC_CMD; /**< Start Command Register, offset: 0x204 */ - __I uint32_t CC_CF; /**< Condition Flag, offset: 0x208 */ - uint8_t RESERVED_6[500]; - __IO uint32_t MDPK; /**< Mode Register (PublicKey), offset: 0x400 */ - uint8_t RESERVED_7[44]; - __O uint32_t COM; /**< Command Register, offset: 0x430 */ - __IO uint32_t CTL; /**< Control Register, offset: 0x434 */ - uint8_t RESERVED_8[8]; - __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */ - uint8_t RESERVED_9[4]; - __IO uint32_t STA; /**< Status Register, offset: 0x448 */ - __I uint32_t ESTA; /**< Error Status Register, offset: 0x44C */ - uint8_t RESERVED_10[48]; - __IO uint32_t PKASZ; /**< PKHA A Size Register, offset: 0x480 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PKBSZ; /**< PKHA B Size Register, offset: 0x488 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PKNSZ; /**< PKHA N Size Register, offset: 0x490 */ - uint8_t RESERVED_13[4]; - __IO uint32_t PKESZ; /**< PKHA E Size Register, offset: 0x498 */ - uint8_t RESERVED_14[84]; - __I uint32_t PKHA_VID1; /**< PKHA Revision ID 1, offset: 0x4F0 */ - __I uint32_t PKHA_VID2; /**< PKHA Revision ID 2, offset: 0x4F4 */ - __I uint32_t CHA_VID; /**< CHA Revision ID, offset: 0x4F8 */ - uint8_t RESERVED_15[260]; - __IO uint32_t PKHA_CCR; /**< PKHA Clock Control Register, offset: 0x600 */ - __I uint32_t GSR; /**< Global Status Register, offset: 0x604 */ - __IO uint32_t CKLFSR; /**< Clock Linear Feedback Shift Register, offset: 0x608 */ - uint8_t RESERVED_16[500]; - __IO uint32_t PKA0[32]; /**< PKHA A0 Register, array offset: 0x800, array step: 0x4 */ - __IO uint32_t PKA1[32]; /**< PKHA A1 Register, array offset: 0x880, array step: 0x4 */ - __IO uint32_t PKA2[32]; /**< PKHA A2 Register, array offset: 0x900, array step: 0x4 */ - __IO uint32_t PKA3[32]; /**< PKHA A3 Register, array offset: 0x980, array step: 0x4 */ - __IO uint32_t PKB0[32]; /**< PKHA B0 Register, array offset: 0xA00, array step: 0x4 */ - __IO uint32_t PKB1[32]; /**< PKHA B1 Register, array offset: 0xA80, array step: 0x4 */ - __IO uint32_t PKB2[32]; /**< PKHA B2 Register, array offset: 0xB00, array step: 0x4 */ - __IO uint32_t PKB3[32]; /**< PKHA B3 Register, array offset: 0xB80, array step: 0x4 */ - __IO uint32_t PKN0[32]; /**< PKHA N0 Register, array offset: 0xC00, array step: 0x4 */ - __IO uint32_t PKN1[32]; /**< PKHA N1 Register, array offset: 0xC80, array step: 0x4 */ - __IO uint32_t PKN2[32]; /**< PKHA N2 Register, array offset: 0xD00, array step: 0x4 */ - __IO uint32_t PKN3[32]; /**< PKHA N3 Register, array offset: 0xD80, array step: 0x4 */ - __O uint32_t PKE[128]; /**< PKHA E Register, array offset: 0xE00, array step: 0x4 */ -} CAU3_Type; - -/* ---------------------------------------------------------------------------- - -- CAU3 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU3_Register_Masks CAU3 Register Masks - * @{ - */ - -/*! @name PCT - Processor Core Type */ -/*! @{ */ -#define CAU3_PCT_Y_MASK (0xFU) -#define CAU3_PCT_Y_SHIFT (0U) -/*! Y - Minor version number - * 0b0000..Minor version number - */ -#define CAU3_PCT_Y(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_Y_SHIFT)) & CAU3_PCT_Y_MASK) -#define CAU3_PCT_X_MASK (0xF0U) -#define CAU3_PCT_X_SHIFT (4U) -/*! X - Major version number - * 0b0000..Major version number - */ -#define CAU3_PCT_X(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_X_SHIFT)) & CAU3_PCT_X_MASK) -#define CAU3_PCT_ID_MASK (0xFFFFFF00U) -#define CAU3_PCT_ID_SHIFT (8U) -/*! ID - Module ID number - * 0b010010110100000101100000..ID number for basic configuration - * 0b010010110100000101100001..ID number for PKHA configuration - */ -#define CAU3_PCT_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_ID_SHIFT)) & CAU3_PCT_ID_MASK) -/*! @} */ - -/*! @name MCFG - Memory Configuration */ -/*! @{ */ -#define CAU3_MCFG_DRAM_SZ_MASK (0xF00U) -#define CAU3_MCFG_DRAM_SZ_SHIFT (8U) -/*! DRAM_SZ - Data RAM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_DRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_DRAM_SZ_SHIFT)) & CAU3_MCFG_DRAM_SZ_MASK) -#define CAU3_MCFG_IROM_SZ_MASK (0xF0000U) -#define CAU3_MCFG_IROM_SZ_SHIFT (16U) -/*! IROM_SZ - Instruction ROM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_IROM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IROM_SZ_SHIFT)) & CAU3_MCFG_IROM_SZ_MASK) -#define CAU3_MCFG_IRAM_SZ_MASK (0xF000000U) -#define CAU3_MCFG_IRAM_SZ_SHIFT (24U) -/*! IRAM_SZ - Instruction RAM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_IRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IRAM_SZ_SHIFT)) & CAU3_MCFG_IRAM_SZ_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define CAU3_CR_TCSEIE_MASK (0x1U) -#define CAU3_CR_TCSEIE_SHIFT (0U) -/*! TCSEIE - Task completion with software error interrupt enable - * 0b0..Disables task completion with software error to generate an interrupt request - * 0b1..Enables task completion with software error to generate an interrupt request - */ -#define CAU3_CR_TCSEIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCSEIE_SHIFT)) & CAU3_CR_TCSEIE_MASK) -#define CAU3_CR_ILLIE_MASK (0x2U) -#define CAU3_CR_ILLIE_SHIFT (1U) -/*! ILLIE - Illegal Instruction Interrupt Enable - * 0b0..Illegal instruction interrupt requests are disabled - * 0b1..illegal Instruction interrupt requests are enabled - */ -#define CAU3_CR_ILLIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ILLIE_SHIFT)) & CAU3_CR_ILLIE_MASK) -#define CAU3_CR_ASREIE_MASK (0x8U) -#define CAU3_CR_ASREIE_SHIFT (3U) -/*! ASREIE - AHB Slave Response Error Interrupt Enable - * 0b0..AHB slave response error interruption is not enabled - * 0b1..AHB slave response error interruption is enabled - */ -#define CAU3_CR_ASREIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ASREIE_SHIFT)) & CAU3_CR_ASREIE_MASK) -#define CAU3_CR_IIADIE_MASK (0x10U) -#define CAU3_CR_IIADIE_SHIFT (4U) -/*! IIADIE - IMEM Illegal Address Interrupt Enable - * 0b0..IMEM illegal address interruption is not enabled - * 0b1..IMEM illegal address interruption is enabled - */ -#define CAU3_CR_IIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_IIADIE_SHIFT)) & CAU3_CR_IIADIE_MASK) -#define CAU3_CR_DIADIE_MASK (0x20U) -#define CAU3_CR_DIADIE_SHIFT (5U) -/*! DIADIE - DMEM Illegal Address Interrupt Enable - * 0b0..DMEM illegal address interruption is not enabled - * 0b1..DMEM illegal address interruption is enabled - */ -#define CAU3_CR_DIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DIADIE_SHIFT)) & CAU3_CR_DIADIE_MASK) -#define CAU3_CR_SVIE_MASK (0x40U) -#define CAU3_CR_SVIE_SHIFT (6U) -/*! SVIE - Security Violation Interrupt Enable - * 0b0..Security violation interruption is not enabled - * 0b1..Security violation interruption is enabled - */ -#define CAU3_CR_SVIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_SVIE_SHIFT)) & CAU3_CR_SVIE_MASK) -#define CAU3_CR_TCIE_MASK (0x80U) -#define CAU3_CR_TCIE_SHIFT (7U) -/*! TCIE - Task completion with no error interrupt enable - * 0b0..Disables task completion with no error to generate an interrupt request - * 0b1..Enables task completion with no error to generate an interrupt request - */ -#define CAU3_CR_TCIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCIE_SHIFT)) & CAU3_CR_TCIE_MASK) -#define CAU3_CR_RSTSM4_MASK (0x3000U) -#define CAU3_CR_RSTSM4_SHIFT (12U) -/*! RSTSM4 - Reset Semaphore - * 0b00..Idle state - * 0b01..Wait for second write - * 0b10..Clears semaphore if previous state was "01" - * 0b11..Reserved - */ -#define CAU3_CR_RSTSM4(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_RSTSM4_SHIFT)) & CAU3_CR_RSTSM4_MASK) -#define CAU3_CR_MRST_MASK (0x8000U) -#define CAU3_CR_MRST_SHIFT (15U) -/*! MRST - Module Reset - * 0b0..no action - * 0b1..reset - */ -#define CAU3_CR_MRST(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MRST_SHIFT)) & CAU3_CR_MRST_MASK) -#define CAU3_CR_FSV_MASK (0x10000U) -#define CAU3_CR_FSV_SHIFT (16U) -/*! FSV - Force Security Violation Test - * 0b0..no violation is forced - * 0b1..force security violation - */ -#define CAU3_CR_FSV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_FSV_SHIFT)) & CAU3_CR_FSV_MASK) -#define CAU3_CR_DTCCFG_MASK (0x7000000U) -#define CAU3_CR_DTCCFG_SHIFT (24U) -/*! DTCCFG - Default Task Completion Configuration - * 0b100..Issue a DMA request - * 0b010..Assert Event Completion Signal - * 0b001..Issue an Interrupt Request - * 0b000..no explicit action - */ -#define CAU3_CR_DTCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DTCCFG_SHIFT)) & CAU3_CR_DTCCFG_MASK) -#define CAU3_CR_DSHFI_MASK (0x10000000U) -#define CAU3_CR_DSHFI_SHIFT (28U) -/*! DSHFI - Disable Secure Hash Function Instructions - * 0b0..Secure Hash Functions are enabled - * 0b1..Secure Hash Functions are disabled - */ -#define CAU3_CR_DSHFI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DSHFI_SHIFT)) & CAU3_CR_DSHFI_MASK) -#define CAU3_CR_DDESI_MASK (0x20000000U) -#define CAU3_CR_DDESI_SHIFT (29U) -/*! DDESI - Disable DES Instructions - * 0b0..DES instructions are enabled - * 0b1..DES instructions are disabled - */ -#define CAU3_CR_DDESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DDESI_SHIFT)) & CAU3_CR_DDESI_MASK) -#define CAU3_CR_DAESI_MASK (0x40000000U) -#define CAU3_CR_DAESI_SHIFT (30U) -/*! DAESI - Disable AES Instructions - * 0b0..AES instructions are enabled - * 0b1..AES instructions are disabled - */ -#define CAU3_CR_DAESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DAESI_SHIFT)) & CAU3_CR_DAESI_MASK) -#define CAU3_CR_MDIS_MASK (0x80000000U) -#define CAU3_CR_MDIS_SHIFT (31U) -/*! MDIS - Module Disable - * 0b0..CAU3 exits from low power mode - * 0b1..CAU3 enters low power mode - */ -#define CAU3_CR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MDIS_SHIFT)) & CAU3_CR_MDIS_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ -#define CAU3_SR_TCSEIRQ_MASK (0x1U) -#define CAU3_SR_TCSEIRQ_SHIFT (0U) -/*! TCSEIRQ - Task completion with software error interrupt request - * 0b0..Task not finished or finished with no software error - * 0b1..Task execution finished with software error - */ -#define CAU3_SR_TCSEIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCSEIRQ_SHIFT)) & CAU3_SR_TCSEIRQ_MASK) -#define CAU3_SR_ILLIRQ_MASK (0x2U) -#define CAU3_SR_ILLIRQ_SHIFT (1U) -/*! ILLIRQ - Illegal instruction interrupt request - * 0b0..no error - * 0b1..illegal instruction detected - */ -#define CAU3_SR_ILLIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ILLIRQ_SHIFT)) & CAU3_SR_ILLIRQ_MASK) -#define CAU3_SR_ASREIRQ_MASK (0x8U) -#define CAU3_SR_ASREIRQ_SHIFT (3U) -/*! ASREIRQ - AHB slave response error interrupt Request - * 0b0..no error - * 0b1..AHB slave response error detected - */ -#define CAU3_SR_ASREIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ASREIRQ_SHIFT)) & CAU3_SR_ASREIRQ_MASK) -#define CAU3_SR_IIADIRQ_MASK (0x10U) -#define CAU3_SR_IIADIRQ_SHIFT (4U) -/*! IIADIRQ - IMEM Illegal address interrupt request - * 0b0..no error - * 0b1..illegal IMEM address detected - */ -#define CAU3_SR_IIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_IIADIRQ_SHIFT)) & CAU3_SR_IIADIRQ_MASK) -#define CAU3_SR_DIADIRQ_MASK (0x20U) -#define CAU3_SR_DIADIRQ_SHIFT (5U) -/*! DIADIRQ - DMEM illegal access interrupt request - * 0b0..no illegal address - * 0b1..illegal address - */ -#define CAU3_SR_DIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DIADIRQ_SHIFT)) & CAU3_SR_DIADIRQ_MASK) -#define CAU3_SR_SVIRQ_MASK (0x40U) -#define CAU3_SR_SVIRQ_SHIFT (6U) -/*! SVIRQ - Security violation interrupt request - * 0b0..No security violation - * 0b1..Security violation - */ -#define CAU3_SR_SVIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVIRQ_SHIFT)) & CAU3_SR_SVIRQ_MASK) -#define CAU3_SR_TCIRQ_MASK (0x80U) -#define CAU3_SR_TCIRQ_SHIFT (7U) -/*! TCIRQ - Task completion with no error interrupt request - * 0b0..Task not finished or finished with error - * 0b1..Task execution finished with no error - */ -#define CAU3_SR_TCIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCIRQ_SHIFT)) & CAU3_SR_TCIRQ_MASK) -#define CAU3_SR_TKCS_MASK (0xF00U) -#define CAU3_SR_TKCS_SHIFT (8U) -/*! TKCS - Task completion status - * 0b0000..Initialization RUN - * 0b0001..Running - * 0b0010..Debug Halted - * 0b1001..Stop - Error Free - * 0b1010..Stop - Error - * 0b1110..Stop - Security Violation, assert security violation output signal and set SVIRQ - * 0b1111..Stop - Security Violation and set SVIRQ - */ -#define CAU3_SR_TKCS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TKCS_SHIFT)) & CAU3_SR_TKCS_MASK) -#define CAU3_SR_SVF_MASK (0x10000U) -#define CAU3_SR_SVF_SHIFT (16U) -/*! SVF - Security violation flag - * 0b0..SoC security violation is not asserted - * 0b1..SoC security violation was asserted - */ -#define CAU3_SR_SVF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVF_SHIFT)) & CAU3_SR_SVF_MASK) -#define CAU3_SR_DBG_MASK (0x20000U) -#define CAU3_SR_DBG_SHIFT (17U) -/*! DBG - Debug mode - * 0b0..CAU3 is not in debug mode - * 0b1..CAU3 is in debug mode - */ -#define CAU3_SR_DBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DBG_SHIFT)) & CAU3_SR_DBG_MASK) -#define CAU3_SR_TCCFG_MASK (0x7000000U) -#define CAU3_SR_TCCFG_SHIFT (24U) -/*! TCCFG - Task completion configuration - * 0b100..Issue a DMA request - * 0b010..Assert the Event Completion Signal - * 0b001..Assert an interrupt request - * 0b000..No action - */ -#define CAU3_SR_TCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCCFG_SHIFT)) & CAU3_SR_TCCFG_MASK) -#define CAU3_SR_MDISF_MASK (0x80000000U) -#define CAU3_SR_MDISF_SHIFT (31U) -/*! MDISF - Module disable flag - * 0b0..CCore is not in low power mode - * 0b1..CCore is in low power mode - */ -#define CAU3_SR_MDISF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK) -/*! @} */ - -/*! @name DBGCSR - Debug Control/Status Register */ -/*! @{ */ -#define CAU3_DBGCSR_DDBG_MASK (0x1U) -#define CAU3_DBGCSR_DDBG_SHIFT (0U) -/*! DDBG - Debug Disable - * 0b0..debug is enabled - * 0b1..debug is disabled - */ -#define CAU3_DBGCSR_DDBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBG_SHIFT)) & CAU3_DBGCSR_DDBG_MASK) -#define CAU3_DBGCSR_DDBGMC_MASK (0x2U) -#define CAU3_DBGCSR_DDBGMC_SHIFT (1U) -/*! DDBGMC - Disable Debug Memory Commands - * 0b0..IPS access to IMEM and DMEM are enabled - * 0b1..IPS access to IMEM and DMEM are disabled - */ -#define CAU3_DBGCSR_DDBGMC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK) -#define CAU3_DBGCSR_PBREN_MASK (0x10U) -#define CAU3_DBGCSR_PBREN_SHIFT (4U) -/*! PBREN - PC Breakpoint Register Enable - * 0b0..PC breakpoint register (DBGPBR) is disabled - * 0b1..PC breakpoint register (DBGPBR) is enabled - */ -#define CAU3_DBGCSR_PBREN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PBREN_SHIFT)) & CAU3_DBGCSR_PBREN_MASK) -#define CAU3_DBGCSR_SIM_MASK (0x20U) -#define CAU3_DBGCSR_SIM_SHIFT (5U) -/*! SIM - Single Instruction Mode - * 0b0..Single instruction mode is disabled - * 0b1..Single instruction mode is enabled - */ -#define CAU3_DBGCSR_SIM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIM_SHIFT)) & CAU3_DBGCSR_SIM_MASK) -#define CAU3_DBGCSR_FRCH_MASK (0x100U) -#define CAU3_DBGCSR_FRCH_SHIFT (8U) -/*! FRCH - Force Debug Halt - * 0b0..Halt state not forced - * 0b1..Force halt state - */ -#define CAU3_DBGCSR_FRCH(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_FRCH_SHIFT)) & CAU3_DBGCSR_FRCH_MASK) -#define CAU3_DBGCSR_DBGGO_MASK (0x1000U) -#define CAU3_DBGCSR_DBGGO_SHIFT (12U) -/*! DBGGO - Debug Go - * 0b0..No action - * 0b1..Resume program execution - */ -#define CAU3_DBGCSR_DBGGO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DBGGO_SHIFT)) & CAU3_DBGCSR_DBGGO_MASK) -#define CAU3_DBGCSR_PCBHF_MASK (0x10000U) -#define CAU3_DBGCSR_PCBHF_SHIFT (16U) -/*! PCBHF - CryptoCore is Halted due to Hardware Breakpoint - * 0b0..CryptoCore is not halted due to a hardware breakpoint - * 0b1..CryptoCore is halted due to a hardware breakpoint - */ -#define CAU3_DBGCSR_PCBHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PCBHF_SHIFT)) & CAU3_DBGCSR_PCBHF_MASK) -#define CAU3_DBGCSR_SIMHF_MASK (0x20000U) -#define CAU3_DBGCSR_SIMHF_SHIFT (17U) -/*! SIMHF - CryptoCore is Halted due to Single Instruction Step - * 0b0..CryptoCore is not in a single step halt - * 0b1..CryptoCore is in a single step halt - */ -#define CAU3_DBGCSR_SIMHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIMHF_SHIFT)) & CAU3_DBGCSR_SIMHF_MASK) -#define CAU3_DBGCSR_HLTIF_MASK (0x40000U) -#define CAU3_DBGCSR_HLTIF_SHIFT (18U) -/*! HLTIF - CryptoCore is Halted due to HALT Instruction - * 0b0..CryptoCore is not in software breakpoint - * 0b1..CryptoCore is in software breakpoint - */ -#define CAU3_DBGCSR_HLTIF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_HLTIF_SHIFT)) & CAU3_DBGCSR_HLTIF_MASK) -#define CAU3_DBGCSR_CSTPF_MASK (0x40000000U) -#define CAU3_DBGCSR_CSTPF_SHIFT (30U) -/*! CSTPF - CryptoCore is Stopped Status Flag - * 0b0..CryptoCore is not stopped - * 0b1..CryptoCore is stopped - */ -#define CAU3_DBGCSR_CSTPF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CSTPF_SHIFT)) & CAU3_DBGCSR_CSTPF_MASK) -#define CAU3_DBGCSR_CHLTF_MASK (0x80000000U) -#define CAU3_DBGCSR_CHLTF_SHIFT (31U) -/*! CHLTF - CryptoCore is Halted Status Flag - * 0b0..CryptoCore is not halted - * 0b1..CryptoCore is halted - */ -#define CAU3_DBGCSR_CHLTF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CHLTF_SHIFT)) & CAU3_DBGCSR_CHLTF_MASK) -/*! @} */ - -/*! @name DBGPBR - Debug PC Breakpoint Register */ -/*! @{ */ -#define CAU3_DBGPBR_PCBKPT_MASK (0xFFFFCU) -#define CAU3_DBGPBR_PCBKPT_SHIFT (2U) -#define CAU3_DBGPBR_PCBKPT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGPBR_PCBKPT_SHIFT)) & CAU3_DBGPBR_PCBKPT_MASK) -/*! @} */ - -/*! @name DBGMCMD - Debug Memory Command Register */ -/*! @{ */ -#define CAU3_DBGMCMD_DM_MASK (0x1000000U) -#define CAU3_DBGMCMD_DM_SHIFT (24U) -/*! DM - Instruction/Data Memory Selection - * 0b0..IMEM is selected - * 0b1..DMEM is selected - */ -#define CAU3_DBGMCMD_DM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_DM_SHIFT)) & CAU3_DBGMCMD_DM_MASK) -#define CAU3_DBGMCMD_IA_MASK (0x4000000U) -#define CAU3_DBGMCMD_IA_SHIFT (26U) -/*! IA - Increment Address - * 0b0..Address is not incremented - * 0b1..Address is incremented after the access - */ -#define CAU3_DBGMCMD_IA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_IA_SHIFT)) & CAU3_DBGMCMD_IA_MASK) -#define CAU3_DBGMCMD_Rb_1_MASK (0x8000000U) -#define CAU3_DBGMCMD_Rb_1_SHIFT (27U) -#define CAU3_DBGMCMD_Rb_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_Rb_1_SHIFT)) & CAU3_DBGMCMD_Rb_1_MASK) -#define CAU3_DBGMCMD_BV_MASK (0x10000000U) -#define CAU3_DBGMCMD_BV_SHIFT (28U) -/*! BV - Byte Reversal Control - * 0b0..DMEM bytes are not reversed - * 0b1..DMEM bytes are reversed - */ -#define CAU3_DBGMCMD_BV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_BV_SHIFT)) & CAU3_DBGMCMD_BV_MASK) -#define CAU3_DBGMCMD_R_0_MASK (0x40000000U) -#define CAU3_DBGMCMD_R_0_SHIFT (30U) -#define CAU3_DBGMCMD_R_0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_0_SHIFT)) & CAU3_DBGMCMD_R_0_MASK) -#define CAU3_DBGMCMD_R_1_MASK (0x80000000U) -#define CAU3_DBGMCMD_R_1_SHIFT (31U) -#define CAU3_DBGMCMD_R_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_1_SHIFT)) & CAU3_DBGMCMD_R_1_MASK) -/*! @} */ - -/*! @name DBGMADR - Debug Memory Address Register */ -/*! @{ */ -#define CAU3_DBGMADR_DMADDR_MASK (0xFFFFFFFCU) -#define CAU3_DBGMADR_DMADDR_SHIFT (2U) -#define CAU3_DBGMADR_DMADDR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMADR_DMADDR_SHIFT)) & CAU3_DBGMADR_DMADDR_MASK) -/*! @} */ - -/*! @name DBGMDR - Debug Memory Data Register */ -/*! @{ */ -#define CAU3_DBGMDR_DMDATA_MASK (0xFFFFFFFFU) -#define CAU3_DBGMDR_DMDATA_SHIFT (0U) -#define CAU3_DBGMDR_DMDATA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMDR_DMDATA_SHIFT)) & CAU3_DBGMDR_DMDATA_MASK) -/*! @} */ - -/*! @name SEMA4 - Semaphore Register */ -/*! @{ */ -#define CAU3_SEMA4_DID_MASK (0xFU) -#define CAU3_SEMA4_DID_SHIFT (0U) -#define CAU3_SEMA4_DID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_DID_SHIFT)) & CAU3_SEMA4_DID_MASK) -#define CAU3_SEMA4_PR_MASK (0x40U) -#define CAU3_SEMA4_PR_SHIFT (6U) -/*! PR - Privilege Attribute of Locked Semaphore Owner - * 0b0..If semaphore is locked, then owner is operating in user mode - * 0b1..If semaphore is locked, then owner is operating in privileged mode - */ -#define CAU3_SEMA4_PR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_PR_SHIFT)) & CAU3_SEMA4_PR_MASK) -#define CAU3_SEMA4_NS_MASK (0x80U) -#define CAU3_SEMA4_NS_SHIFT (7U) -/*! NS - Non Secure Attribute of the Locked Semaphore Owner - * 0b0..If semaphore is locked, owner is operating in secure mode - * 0b1..If semaphore is locked, owner is operating in nonsecure mode - */ -#define CAU3_SEMA4_NS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK) -#define CAU3_SEMA4_MSTRN_MASK (0x3F00U) -#define CAU3_SEMA4_MSTRN_SHIFT (8U) -#define CAU3_SEMA4_MSTRN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_MSTRN_SHIFT)) & CAU3_SEMA4_MSTRN_MASK) -#define CAU3_SEMA4_LK_MASK (0x80000000U) -#define CAU3_SEMA4_LK_SHIFT (31U) -/*! LK - Semaphore Lock and Release Control - * 0b0..Semaphore release - * 0b1..Semaphore lock - */ -#define CAU3_SEMA4_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_LK_SHIFT)) & CAU3_SEMA4_LK_MASK) -/*! @} */ - -/*! @name SMOWNR - Semaphore Ownership Register */ -/*! @{ */ -#define CAU3_SMOWNR_LOCK_MASK (0x1U) -#define CAU3_SMOWNR_LOCK_SHIFT (0U) -/*! LOCK - Semaphore Locked - * 0b0..Semaphore not locked - * 0b1..Semaphore locked - */ -#define CAU3_SMOWNR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_LOCK_SHIFT)) & CAU3_SMOWNR_LOCK_MASK) -#define CAU3_SMOWNR_NOWNER_MASK (0x80000000U) -#define CAU3_SMOWNR_NOWNER_SHIFT (31U) -/*! NOWNER - Semaphore Ownership - * 0b0..The host making the current read access is the semaphore owner - * 0b1..The host making the current read access is NOT the semaphore owner - */ -#define CAU3_SMOWNR_NOWNER(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_NOWNER_SHIFT)) & CAU3_SMOWNR_NOWNER_MASK) -/*! @} */ - -/*! @name ARR - Address Remap Register */ -/*! @{ */ -#define CAU3_ARR_ARRL_MASK (0xFFFFFFFFU) -#define CAU3_ARR_ARRL_SHIFT (0U) -#define CAU3_ARR_ARRL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ARR_ARRL_SHIFT)) & CAU3_ARR_ARRL_MASK) -/*! @} */ - -/*! @name CC_R - CryptoCore General Purpose Registers */ -/*! @{ */ -#define CAU3_CC_R_R_MASK (0xFFFFFFFFU) -#define CAU3_CC_R_R_SHIFT (0U) -#define CAU3_CC_R_R(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R_R_SHIFT)) & CAU3_CC_R_R_MASK) -/*! @} */ - -/* The count of CAU3_CC_R */ -#define CAU3_CC_R_COUNT (30U) - -/*! @name CC_R30 - General Purpose R30 */ -/*! @{ */ -#define CAU3_CC_R30_SP_MASK (0xFFFFFFFFU) -#define CAU3_CC_R30_SP_SHIFT (0U) -#define CAU3_CC_R30_SP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R30_SP_SHIFT)) & CAU3_CC_R30_SP_MASK) -/*! @} */ - -/*! @name CC_R31 - General Purpose R31 */ -/*! @{ */ -#define CAU3_CC_R31_LR_MASK (0xFFFFFFFFU) -#define CAU3_CC_R31_LR_SHIFT (0U) -#define CAU3_CC_R31_LR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R31_LR_SHIFT)) & CAU3_CC_R31_LR_MASK) -/*! @} */ - -/*! @name CC_PC - Program Counter */ -/*! @{ */ -#define CAU3_CC_PC_PC_MASK (0xFFFFFU) -#define CAU3_CC_PC_PC_SHIFT (0U) -#define CAU3_CC_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_PC_PC_SHIFT)) & CAU3_CC_PC_PC_MASK) -/*! @} */ - -/*! @name CC_CMD - Start Command Register */ -/*! @{ */ -#define CAU3_CC_CMD_CMD_MASK (0x70000U) -#define CAU3_CC_CMD_CMD_SHIFT (16U) -/*! CMD - Command - * 0b000..Use CR[DTCCFG] for task completion configuration - * 0b100..Issue a DMA request - * 0b010..Assert Event Completion Signal - * 0b001..Issue an interrupt request - */ -#define CAU3_CC_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CMD_CMD_SHIFT)) & CAU3_CC_CMD_CMD_MASK) -/*! @} */ - -/*! @name CC_CF - Condition Flag */ -/*! @{ */ -#define CAU3_CC_CF_C_MASK (0x1U) -#define CAU3_CC_CF_C_SHIFT (0U) -#define CAU3_CC_CF_C(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_C_SHIFT)) & CAU3_CC_CF_C_MASK) -#define CAU3_CC_CF_V_MASK (0x2U) -#define CAU3_CC_CF_V_SHIFT (1U) -#define CAU3_CC_CF_V(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK) -#define CAU3_CC_CF_Z_MASK (0x4U) -#define CAU3_CC_CF_Z_SHIFT (2U) -#define CAU3_CC_CF_Z(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_Z_SHIFT)) & CAU3_CC_CF_Z_MASK) -#define CAU3_CC_CF_N_MASK (0x8U) -#define CAU3_CC_CF_N_SHIFT (3U) -#define CAU3_CC_CF_N(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_N_SHIFT)) & CAU3_CC_CF_N_MASK) -/*! @} */ - -/*! @name MDPK - Mode Register (PublicKey) */ -/*! @{ */ -#define CAU3_MDPK_PKHA_MODE_LS_MASK (0xFFFU) -#define CAU3_MDPK_PKHA_MODE_LS_SHIFT (0U) -#define CAU3_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_LS_SHIFT)) & CAU3_MDPK_PKHA_MODE_LS_MASK) -#define CAU3_MDPK_PKHA_MODE_MS_MASK (0xF0000U) -#define CAU3_MDPK_PKHA_MODE_MS_SHIFT (16U) -#define CAU3_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_MS_SHIFT)) & CAU3_MDPK_PKHA_MODE_MS_MASK) -#define CAU3_MDPK_ALG_MASK (0xF00000U) -#define CAU3_MDPK_ALG_SHIFT (20U) -/*! ALG - Algorithm - * 0b1000..PKHA - */ -#define CAU3_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_ALG_SHIFT)) & CAU3_MDPK_ALG_MASK) -/*! @} */ - -/*! @name COM - Command Register */ -/*! @{ */ -#define CAU3_COM_ALL_MASK (0x1U) -#define CAU3_COM_ALL_SHIFT (0U) -/*! ALL - Reset All Internal Logic - * 0b0..Do Not Reset - * 0b1..Reset PKHA engine and registers - */ -#define CAU3_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_ALL_SHIFT)) & CAU3_COM_ALL_MASK) -#define CAU3_COM_PK_MASK (0x40U) -#define CAU3_COM_PK_SHIFT (6U) -/*! PK - Reset PKHA - * 0b0..Do Not Reset - * 0b1..Reset Public Key Hardware Accelerator - */ -#define CAU3_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_PK_SHIFT)) & CAU3_COM_PK_MASK) -/*! @} */ - -/*! @name CTL - Control Register */ -/*! @{ */ -#define CAU3_CTL_IM_MASK (0x1U) -#define CAU3_CTL_IM_SHIFT (0U) -/*! IM - Interrupt Mask - * 0b0..Interrupt not masked. - * 0b1..Interrupt masked - */ -#define CAU3_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_IM_SHIFT)) & CAU3_CTL_IM_MASK) -#define CAU3_CTL_PDE_MASK (0x10U) -#define CAU3_CTL_PDE_SHIFT (4U) -/*! PDE - PKHA Register DMA Enable - * 0b0..DMA Request and Done signals disabled for the PKHA Registers. - * 0b1..DMA Request and Done signals enabled for the PKHA Registers. - */ -#define CAU3_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_PDE_SHIFT)) & CAU3_CTL_PDE_MASK) -/*! @} */ - -/*! @name CW - Clear Written Register */ -/*! @{ */ -#define CAU3_CW_CM_MASK (0x1U) -#define CAU3_CW_CM_SHIFT (0U) -#define CAU3_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CM_SHIFT)) & CAU3_CW_CM_MASK) -#define CAU3_CW_CPKA_MASK (0x1000U) -#define CAU3_CW_CPKA_SHIFT (12U) -#define CAU3_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKA_SHIFT)) & CAU3_CW_CPKA_MASK) -#define CAU3_CW_CPKB_MASK (0x2000U) -#define CAU3_CW_CPKB_SHIFT (13U) -#define CAU3_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKB_SHIFT)) & CAU3_CW_CPKB_MASK) -#define CAU3_CW_CPKN_MASK (0x4000U) -#define CAU3_CW_CPKN_SHIFT (14U) -#define CAU3_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKN_SHIFT)) & CAU3_CW_CPKN_MASK) -#define CAU3_CW_CPKE_MASK (0x8000U) -#define CAU3_CW_CPKE_SHIFT (15U) -#define CAU3_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKE_SHIFT)) & CAU3_CW_CPKE_MASK) -/*! @} */ - -/*! @name STA - Status Register */ -/*! @{ */ -#define CAU3_STA_PB_MASK (0x40U) -#define CAU3_STA_PB_SHIFT (6U) -/*! PB - PKHA Busy - * 0b0..PKHA Idle - * 0b1..PKHA Busy. - */ -#define CAU3_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PB_SHIFT)) & CAU3_STA_PB_MASK) -#define CAU3_STA_DI_MASK (0x10000U) -#define CAU3_STA_DI_SHIFT (16U) -#define CAU3_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_DI_SHIFT)) & CAU3_STA_DI_MASK) -#define CAU3_STA_EI_MASK (0x100000U) -#define CAU3_STA_EI_SHIFT (20U) -/*! EI - Error Interrupt - * 0b0..Not Error. - * 0b1..Error Interrupt. - */ -#define CAU3_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_EI_SHIFT)) & CAU3_STA_EI_MASK) -#define CAU3_STA_PKP_MASK (0x10000000U) -#define CAU3_STA_PKP_SHIFT (28U) -#define CAU3_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKP_SHIFT)) & CAU3_STA_PKP_MASK) -#define CAU3_STA_PKO_MASK (0x20000000U) -#define CAU3_STA_PKO_SHIFT (29U) -#define CAU3_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKO_SHIFT)) & CAU3_STA_PKO_MASK) -#define CAU3_STA_PKZ_MASK (0x40000000U) -#define CAU3_STA_PKZ_SHIFT (30U) -#define CAU3_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKZ_SHIFT)) & CAU3_STA_PKZ_MASK) -/*! @} */ - -/*! @name ESTA - Error Status Register */ -/*! @{ */ -#define CAU3_ESTA_ERRID1_MASK (0xFU) -#define CAU3_ESTA_ERRID1_SHIFT (0U) -/*! ERRID1 - Error ID 1 - * 0b0001..Mode Error - * 0b0010..PKHA N Register Size Error - * 0b0011..PKHA E Register Size Error - * 0b0100..PKHA A Register Size Error - * 0b0101..PKHA B Register Size Error - * 0b0110..PKHA C input (as contained in the PKHA B0 quadrant) is Zero - * 0b0111..PKHA Divide by Zero Error - * 0b1000..PKHA Modulus Even Error - * 0b1111..Invalid Crypto Engine Selected - */ -#define CAU3_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_ERRID1_SHIFT)) & CAU3_ESTA_ERRID1_MASK) -#define CAU3_ESTA_CL1_MASK (0xF00U) -#define CAU3_ESTA_CL1_SHIFT (8U) -/*! CL1 - algorithms - * 0b0000..General Error - * 0b1000..Public Key - */ -#define CAU3_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_CL1_SHIFT)) & CAU3_ESTA_CL1_MASK) -/*! @} */ - -/*! @name PKASZ - PKHA A Size Register */ -/*! @{ */ -#define CAU3_PKASZ_PKASZ_MASK (0x1FFU) -#define CAU3_PKASZ_PKASZ_SHIFT (0U) -#define CAU3_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKASZ_PKASZ_SHIFT)) & CAU3_PKASZ_PKASZ_MASK) -/*! @} */ - -/*! @name PKBSZ - PKHA B Size Register */ -/*! @{ */ -#define CAU3_PKBSZ_PKBSZ_MASK (0x1FFU) -#define CAU3_PKBSZ_PKBSZ_SHIFT (0U) -#define CAU3_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKBSZ_PKBSZ_SHIFT)) & CAU3_PKBSZ_PKBSZ_MASK) -/*! @} */ - -/*! @name PKNSZ - PKHA N Size Register */ -/*! @{ */ -#define CAU3_PKNSZ_PKNSZ_MASK (0x1FFU) -#define CAU3_PKNSZ_PKNSZ_SHIFT (0U) -#define CAU3_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKNSZ_PKNSZ_SHIFT)) & CAU3_PKNSZ_PKNSZ_MASK) -/*! @} */ - -/*! @name PKESZ - PKHA E Size Register */ -/*! @{ */ -#define CAU3_PKESZ_PKESZ_MASK (0x1FFU) -#define CAU3_PKESZ_PKESZ_SHIFT (0U) -#define CAU3_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKESZ_PKESZ_SHIFT)) & CAU3_PKESZ_PKESZ_MASK) -/*! @} */ - -/*! @name PKHA_VID1 - PKHA Revision ID 1 */ -/*! @{ */ -#define CAU3_PKHA_VID1_MIN_REV_MASK (0xFFU) -#define CAU3_PKHA_VID1_MIN_REV_SHIFT (0U) -#define CAU3_PKHA_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MIN_REV_SHIFT)) & CAU3_PKHA_VID1_MIN_REV_MASK) -#define CAU3_PKHA_VID1_MAJ_REV_MASK (0xFF00U) -#define CAU3_PKHA_VID1_MAJ_REV_SHIFT (8U) -#define CAU3_PKHA_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MAJ_REV_SHIFT)) & CAU3_PKHA_VID1_MAJ_REV_MASK) -#define CAU3_PKHA_VID1_IP_ID_MASK (0xFFFF0000U) -#define CAU3_PKHA_VID1_IP_ID_SHIFT (16U) -#define CAU3_PKHA_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_IP_ID_SHIFT)) & CAU3_PKHA_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name PKHA_VID2 - PKHA Revision ID 2 */ -/*! @{ */ -#define CAU3_PKHA_VID2_ECO_REV_MASK (0xFFU) -#define CAU3_PKHA_VID2_ECO_REV_SHIFT (0U) -#define CAU3_PKHA_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ECO_REV_SHIFT)) & CAU3_PKHA_VID2_ECO_REV_MASK) -#define CAU3_PKHA_VID2_ARCH_ERA_MASK (0xFF00U) -#define CAU3_PKHA_VID2_ARCH_ERA_SHIFT (8U) -#define CAU3_PKHA_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ARCH_ERA_SHIFT)) & CAU3_PKHA_VID2_ARCH_ERA_MASK) -/*! @} */ - -/*! @name CHA_VID - CHA Revision ID */ -/*! @{ */ -#define CAU3_CHA_VID_PKHAREV_MASK (0xF0000U) -#define CAU3_CHA_VID_PKHAREV_SHIFT (16U) -#define CAU3_CHA_VID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAREV_SHIFT)) & CAU3_CHA_VID_PKHAREV_MASK) -#define CAU3_CHA_VID_PKHAVID_MASK (0xF00000U) -#define CAU3_CHA_VID_PKHAVID_SHIFT (20U) -#define CAU3_CHA_VID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAVID_SHIFT)) & CAU3_CHA_VID_PKHAVID_MASK) -/*! @} */ - -/*! @name PKHA_CCR - PKHA Clock Control Register */ -/*! @{ */ -#define CAU3_PKHA_CCR_CKTHRT_MASK (0x7U) -#define CAU3_PKHA_CCR_CKTHRT_SHIFT (0U) -/*! CKTHRT - Clock Throttle selection - * 0b000..PKHA clock division rate is 8/8 - full speed - * 0b001..PKHA clock division rate is 1/8 - * 0b010..PKHA clock division rate is 2/8 - * 0b011..PKHA clock division rate is 3/8 - * 0b100..PKHA clock division rate is 4/8 - * 0b101..PKHA clock division rate is 5/8 - * 0b110..PKHA clock division rate is 6/8 - * 0b111..PKHA clock division rate is 7/8 - */ -#define CAU3_PKHA_CCR_CKTHRT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_CKTHRT_SHIFT)) & CAU3_PKHA_CCR_CKTHRT_MASK) -#define CAU3_PKHA_CCR_LK_MASK (0x1000000U) -#define CAU3_PKHA_CCR_LK_SHIFT (24U) -/*! LK - Register Lock - * 0b0..Register is unlocked - * 0b1..Register is locked - */ -#define CAU3_PKHA_CCR_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_LK_SHIFT)) & CAU3_PKHA_CCR_LK_MASK) -#define CAU3_PKHA_CCR_ELFR_MASK (0x20000000U) -#define CAU3_PKHA_CCR_ELFR_SHIFT (29U) -/*! ELFR - Enable Linear Feedback Shift Register - * 0b0..LFSR is only enabled if ECT = 1 and ECJ = 1 - * 0b1..LFSR is enabled independently of ECT and ECJ - */ -#define CAU3_PKHA_CCR_ELFR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ELFR_SHIFT)) & CAU3_PKHA_CCR_ELFR_MASK) -#define CAU3_PKHA_CCR_ECJ_MASK (0x40000000U) -#define CAU3_PKHA_CCR_ECJ_SHIFT (30U) -/*! ECJ - Enable Clock Jitter - * 0b0..Clock Jitter is disabled - * 0b1..Clock jitter is enabled - */ -#define CAU3_PKHA_CCR_ECJ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECJ_SHIFT)) & CAU3_PKHA_CCR_ECJ_MASK) -#define CAU3_PKHA_CCR_ECT_MASK (0x80000000U) -#define CAU3_PKHA_CCR_ECT_SHIFT (31U) -/*! ECT - Enable Clock Throttle - * 0b0..PKHA clock throttle disabled meaning that PKHA is operatiing at full speed - * 0b1..PKHA clock throttle enabled - */ -#define CAU3_PKHA_CCR_ECT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECT_SHIFT)) & CAU3_PKHA_CCR_ECT_MASK) -/*! @} */ - -/*! @name GSR - Global Status Register */ -/*! @{ */ -#define CAU3_GSR_CDI_MASK (0x400U) -#define CAU3_GSR_CDI_SHIFT (10U) -/*! CDI - CAU3 Done Interrupt occurred - * 0b0..CAU3 Done Interrupt did not occur - * 0b1..CAU3 Done Interrupt occurred - */ -#define CAU3_GSR_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CDI_SHIFT)) & CAU3_GSR_CDI_MASK) -#define CAU3_GSR_CEI_MASK (0x4000U) -#define CAU3_GSR_CEI_SHIFT (14U) -/*! CEI - CAU3 Error Interrupt - * 0b0..CAU3 Error Interrupt did not occur - * 0b1..CAU3 Error Interrupt occurred - */ -#define CAU3_GSR_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CEI_SHIFT)) & CAU3_GSR_CEI_MASK) -#define CAU3_GSR_PEI_MASK (0x8000U) -#define CAU3_GSR_PEI_SHIFT (15U) -/*! PEI - PKHA Done or Error Interrupt - * 0b0..PKHA interrupt did not occur - * 0b1..PKHA interrupt had occurred - */ -#define CAU3_GSR_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PEI_SHIFT)) & CAU3_GSR_PEI_MASK) -#define CAU3_GSR_PBSY_MASK (0x80000000U) -#define CAU3_GSR_PBSY_SHIFT (31U) -/*! PBSY - PKHA Busy - * 0b0..PKHA not busy - * 0b1..PKHA busy - */ -#define CAU3_GSR_PBSY(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PBSY_SHIFT)) & CAU3_GSR_PBSY_MASK) -/*! @} */ - -/*! @name CKLFSR - Clock Linear Feedback Shift Register */ -/*! @{ */ -#define CAU3_CKLFSR_LFSR_MASK (0xFFFFFFFFU) -#define CAU3_CKLFSR_LFSR_SHIFT (0U) -#define CAU3_CKLFSR_LFSR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CKLFSR_LFSR_SHIFT)) & CAU3_CKLFSR_LFSR_MASK) -/*! @} */ - -/*! @name PKA0 - PKHA A0 Register */ -/*! @{ */ -#define CAU3_PKA0_PKHA_A0_MASK (0xFFFFFFFFU) -#define CAU3_PKA0_PKHA_A0_SHIFT (0U) -#define CAU3_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA0_PKHA_A0_SHIFT)) & CAU3_PKA0_PKHA_A0_MASK) -/*! @} */ - -/* The count of CAU3_PKA0 */ -#define CAU3_PKA0_COUNT (32U) - -/*! @name PKA1 - PKHA A1 Register */ -/*! @{ */ -#define CAU3_PKA1_PKHA_A1_MASK (0xFFFFFFFFU) -#define CAU3_PKA1_PKHA_A1_SHIFT (0U) -#define CAU3_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA1_PKHA_A1_SHIFT)) & CAU3_PKA1_PKHA_A1_MASK) -/*! @} */ - -/* The count of CAU3_PKA1 */ -#define CAU3_PKA1_COUNT (32U) - -/*! @name PKA2 - PKHA A2 Register */ -/*! @{ */ -#define CAU3_PKA2_PKHA_A2_MASK (0xFFFFFFFFU) -#define CAU3_PKA2_PKHA_A2_SHIFT (0U) -#define CAU3_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA2_PKHA_A2_SHIFT)) & CAU3_PKA2_PKHA_A2_MASK) -/*! @} */ - -/* The count of CAU3_PKA2 */ -#define CAU3_PKA2_COUNT (32U) - -/*! @name PKA3 - PKHA A3 Register */ -/*! @{ */ -#define CAU3_PKA3_PKHA_A3_MASK (0xFFFFFFFFU) -#define CAU3_PKA3_PKHA_A3_SHIFT (0U) -#define CAU3_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA3_PKHA_A3_SHIFT)) & CAU3_PKA3_PKHA_A3_MASK) -/*! @} */ - -/* The count of CAU3_PKA3 */ -#define CAU3_PKA3_COUNT (32U) - -/*! @name PKB0 - PKHA B0 Register */ -/*! @{ */ -#define CAU3_PKB0_PKHA_B0_MASK (0xFFFFFFFFU) -#define CAU3_PKB0_PKHA_B0_SHIFT (0U) -#define CAU3_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB0_PKHA_B0_SHIFT)) & CAU3_PKB0_PKHA_B0_MASK) -/*! @} */ - -/* The count of CAU3_PKB0 */ -#define CAU3_PKB0_COUNT (32U) - -/*! @name PKB1 - PKHA B1 Register */ -/*! @{ */ -#define CAU3_PKB1_PKHA_B1_MASK (0xFFFFFFFFU) -#define CAU3_PKB1_PKHA_B1_SHIFT (0U) -#define CAU3_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB1_PKHA_B1_SHIFT)) & CAU3_PKB1_PKHA_B1_MASK) -/*! @} */ - -/* The count of CAU3_PKB1 */ -#define CAU3_PKB1_COUNT (32U) - -/*! @name PKB2 - PKHA B2 Register */ -/*! @{ */ -#define CAU3_PKB2_PKHA_B2_MASK (0xFFFFFFFFU) -#define CAU3_PKB2_PKHA_B2_SHIFT (0U) -#define CAU3_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB2_PKHA_B2_SHIFT)) & CAU3_PKB2_PKHA_B2_MASK) -/*! @} */ - -/* The count of CAU3_PKB2 */ -#define CAU3_PKB2_COUNT (32U) - -/*! @name PKB3 - PKHA B3 Register */ -/*! @{ */ -#define CAU3_PKB3_PKHA_B3_MASK (0xFFFFFFFFU) -#define CAU3_PKB3_PKHA_B3_SHIFT (0U) -#define CAU3_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB3_PKHA_B3_SHIFT)) & CAU3_PKB3_PKHA_B3_MASK) -/*! @} */ - -/* The count of CAU3_PKB3 */ -#define CAU3_PKB3_COUNT (32U) - -/*! @name PKN0 - PKHA N0 Register */ -/*! @{ */ -#define CAU3_PKN0_PKHA_N0_MASK (0xFFFFFFFFU) -#define CAU3_PKN0_PKHA_N0_SHIFT (0U) -#define CAU3_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN0_PKHA_N0_SHIFT)) & CAU3_PKN0_PKHA_N0_MASK) -/*! @} */ - -/* The count of CAU3_PKN0 */ -#define CAU3_PKN0_COUNT (32U) - -/*! @name PKN1 - PKHA N1 Register */ -/*! @{ */ -#define CAU3_PKN1_PKHA_N1_MASK (0xFFFFFFFFU) -#define CAU3_PKN1_PKHA_N1_SHIFT (0U) -#define CAU3_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN1_PKHA_N1_SHIFT)) & CAU3_PKN1_PKHA_N1_MASK) -/*! @} */ - -/* The count of CAU3_PKN1 */ -#define CAU3_PKN1_COUNT (32U) - -/*! @name PKN2 - PKHA N2 Register */ -/*! @{ */ -#define CAU3_PKN2_PKHA_N2_MASK (0xFFFFFFFFU) -#define CAU3_PKN2_PKHA_N2_SHIFT (0U) -#define CAU3_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN2_PKHA_N2_SHIFT)) & CAU3_PKN2_PKHA_N2_MASK) -/*! @} */ - -/* The count of CAU3_PKN2 */ -#define CAU3_PKN2_COUNT (32U) - -/*! @name PKN3 - PKHA N3 Register */ -/*! @{ */ -#define CAU3_PKN3_PKHA_N3_MASK (0xFFFFFFFFU) -#define CAU3_PKN3_PKHA_N3_SHIFT (0U) -#define CAU3_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN3_PKHA_N3_SHIFT)) & CAU3_PKN3_PKHA_N3_MASK) -/*! @} */ - -/* The count of CAU3_PKN3 */ -#define CAU3_PKN3_COUNT (32U) - -/*! @name PKE - PKHA E Register */ -/*! @{ */ -#define CAU3_PKE_PKHA_E_MASK (0xFFFFFFFFU) -#define CAU3_PKE_PKHA_E_SHIFT (0U) -#define CAU3_PKE_PKHA_E(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKE_PKHA_E_SHIFT)) & CAU3_PKE_PKHA_E_MASK) -/*! @} */ - -/* The count of CAU3_PKE */ -#define CAU3_PKE_COUNT (128U) - - -/*! - * @} - */ /* end of group CAU3_Register_Masks */ - - -/* CAU3 - Peripheral instance base addresses */ -/** Peripheral CAU3 base address */ -#define CAU3_BASE (0x41028000u) -/** Peripheral CAU3 base pointer */ -#define CAU3 ((CAU3_Type *)CAU3_BASE) -/** Array initializer of CAU3 peripheral base addresses */ -#define CAU3_BASE_ADDRS { CAU3_BASE } -/** Array initializer of CAU3 peripheral base pointers */ -#define CAU3_BASE_PTRS { CAU3 } -/** Interrupt vectors for the CAU3 peripheral type */ -#define CAU3_TASK_COMPLETE_IRQS { CAU3_Task_Complete_IRQn } -#define CAU3_SECURITY_VIOLATION_IRQS { CAU3_Security_Violation_IRQn } - -/*! - * @} - */ /* end of group CAU3_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ - __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ - __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ - __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ - } ACCESS8BIT; - struct { /* offset: 0x0 */ - __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ - __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ - } ACCESS16BIT; - }; - union { /* offset: 0x4 */ - __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ - __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ - __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ - __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ - } GPOLY_ACCESS8BIT; - struct { /* offset: 0x4 */ - __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ - __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ - } GPOLY_ACCESS16BIT; - }; - union { /* offset: 0x8 */ - __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ - struct { /* offset: 0x8 */ - uint8_t RESERVED_0[3]; - __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ - } CTRL_ACCESS8BIT; - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name DATA - CRC Data register */ -/*! @{ */ -#define CRC_DATA_LL_MASK (0xFFU) -#define CRC_DATA_LL_SHIFT (0U) -#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) -#define CRC_DATA_LU_MASK (0xFF00U) -#define CRC_DATA_LU_SHIFT (8U) -#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) -#define CRC_DATA_HL_MASK (0xFF0000U) -#define CRC_DATA_HL_SHIFT (16U) -#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) -#define CRC_DATA_HU_MASK (0xFF000000U) -#define CRC_DATA_HU_SHIFT (24U) -#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) -/*! @} */ - -/*! @name DATALL - CRC_DATALL register */ -/*! @{ */ -#define CRC_DATALL_DATALL_MASK (0xFFU) -#define CRC_DATALL_DATALL_SHIFT (0U) -#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) -/*! @} */ - -/*! @name DATALU - CRC_DATALU register */ -/*! @{ */ -#define CRC_DATALU_DATALU_MASK (0xFFU) -#define CRC_DATALU_DATALU_SHIFT (0U) -#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) -/*! @} */ - -/*! @name DATAHL - CRC_DATAHL register */ -/*! @{ */ -#define CRC_DATAHL_DATAHL_MASK (0xFFU) -#define CRC_DATAHL_DATAHL_SHIFT (0U) -#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) -/*! @} */ - -/*! @name DATAHU - CRC_DATAHU register */ -/*! @{ */ -#define CRC_DATAHU_DATAHU_MASK (0xFFU) -#define CRC_DATAHU_DATAHU_SHIFT (0U) -#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) -/*! @} */ - -/*! @name DATAL - CRC_DATAL register */ -/*! @{ */ -#define CRC_DATAL_DATAL_MASK (0xFFFFU) -#define CRC_DATAL_DATAL_SHIFT (0U) -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) -/*! @} */ - -/*! @name DATAH - CRC_DATAH register */ -/*! @{ */ -#define CRC_DATAH_DATAH_MASK (0xFFFFU) -#define CRC_DATAH_DATAH_SHIFT (0U) -#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) -/*! @} */ - -/*! @name GPOLY - CRC Polynomial register */ -/*! @{ */ -#define CRC_GPOLY_LOW_MASK (0xFFFFU) -#define CRC_GPOLY_LOW_SHIFT (0U) -#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) -#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) -#define CRC_GPOLY_HIGH_SHIFT (16U) -#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) -/*! @} */ - -/*! @name GPOLYLL - CRC_GPOLYLL register */ -/*! @{ */ -#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) -#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) -#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) -/*! @} */ - -/*! @name GPOLYLU - CRC_GPOLYLU register */ -/*! @{ */ -#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) -#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) -#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) -/*! @} */ - -/*! @name GPOLYHL - CRC_GPOLYHL register */ -/*! @{ */ -#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) -#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) -#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) -/*! @} */ - -/*! @name GPOLYHU - CRC_GPOLYHU register */ -/*! @{ */ -#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) -#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) -#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) -/*! @} */ - -/*! @name GPOLYL - CRC_GPOLYL register */ -/*! @{ */ -#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) -#define CRC_GPOLYL_GPOLYL_SHIFT (0U) -#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) -/*! @} */ - -/*! @name GPOLYH - CRC_GPOLYH register */ -/*! @{ */ -#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) -#define CRC_GPOLYH_GPOLYH_SHIFT (0U) -#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) -/*! @} */ - -/*! @name CTRL - CRC Control register */ -/*! @{ */ -#define CRC_CTRL_TCRC_MASK (0x1000000U) -#define CRC_CTRL_TCRC_SHIFT (24U) -/*! TCRC - TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) -#define CRC_CTRL_WAS_MASK (0x2000000U) -#define CRC_CTRL_WAS_SHIFT (25U) -/*! WAS - Write CRC Data Register As Seed - * 0b0..Writes to the CRC data register are data values. - * 0b1..Writes to the CRC data register are seed values. - */ -#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) -#define CRC_CTRL_FXOR_MASK (0x4000000U) -#define CRC_CTRL_FXOR_SHIFT (26U) -/*! FXOR - Complement Read Of CRC Data Register - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC Data register. - */ -#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) -#define CRC_CTRL_TOTR_MASK (0x30000000U) -#define CRC_CTRL_TOTR_SHIFT (28U) -/*! TOTR - Type Of Transpose For Read - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) -#define CRC_CTRL_TOT_MASK (0xC0000000U) -#define CRC_CTRL_TOT_SHIFT (30U) -/*! TOT - Type Of Transpose For Writes - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) -/*! @} */ - -/*! @name CTRLHU - CRC_CTRLHU register */ -/*! @{ */ -#define CRC_CTRLHU_TCRC_MASK (0x1U) -#define CRC_CTRLHU_TCRC_SHIFT (0U) -/*! TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) -#define CRC_CTRLHU_WAS_MASK (0x2U) -#define CRC_CTRLHU_WAS_SHIFT (1U) -/*! WAS - * 0b0..Writes to the CRC data register are data values. - * 0b1..Writes to the CRC data register are seed values. - */ -#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) -#define CRC_CTRLHU_FXOR_MASK (0x4U) -#define CRC_CTRLHU_FXOR_SHIFT (2U) -/*! FXOR - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC Data register. - */ -#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) -#define CRC_CTRLHU_TOTR_MASK (0x30U) -#define CRC_CTRLHU_TOTR_SHIFT (4U) -/*! TOTR - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) -#define CRC_CTRLHU_TOT_MASK (0xC0U) -#define CRC_CTRLHU_TOT_SHIFT (6U) -/*! TOT - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC base address */ -#define CRC_BASE (0x4002F000u) -/** Peripheral CRC base pointer */ -#define CRC0 ((CRC_Type *)CRC_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC0 } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[12]; - __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ - uint8_t RESERVED_6[184]; - __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */ - __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */ - __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */ - __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */ - __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */ - __IO uint8_t DCHPRI11; /**< Channel Priority Register, offset: 0x108 */ - __IO uint8_t DCHPRI10; /**< Channel Priority Register, offset: 0x109 */ - __IO uint8_t DCHPRI9; /**< Channel Priority Register, offset: 0x10A */ - __IO uint8_t DCHPRI8; /**< Channel Priority Register, offset: 0x10B */ - __IO uint8_t DCHPRI15; /**< Channel Priority Register, offset: 0x10C */ - __IO uint8_t DCHPRI14; /**< Channel Priority Register, offset: 0x10D */ - __IO uint8_t DCHPRI13; /**< Channel Priority Register, offset: 0x10E */ - __IO uint8_t DCHPRI12; /**< Channel Priority Register, offset: 0x10F */ - uint8_t RESERVED_7[3824]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[16]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -/*! EDBG - Enable Debug - * 0b0..When in debug mode, the DMA continues to operate. - * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. - */ -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -/*! ERCA - Enable Round Robin Channel Arbitration - * 0b0..Fixed priority arbitration is used for channel selection . - * 0b1..Round robin arbitration is used for channel selection . - */ -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -/*! HOE - Halt On Error - * 0b0..Normal operation - * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. - */ -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -/*! HALT - Halt DMA Operations - * 0b0..Normal operation - * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. - */ -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -/*! CLM - Continuous Link Mode - * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. - * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. - */ -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -/*! EMLM - Enable Minor Loop Mapping - * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. - * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. - */ -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -/*! ECX - Error Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. - */ -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -/*! CX - Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. - */ -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) -#define DMA_CR_ACTIVE_MASK (0x80000000U) -#define DMA_CR_ACTIVE_SHIFT (31U) -/*! ACTIVE - DMA Active Status - * 0b0..eDMA is idle. - * 0b1..eDMA is executing a channel. - */ -#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) -/*! @} */ - -/*! @name ES - Error Status Register */ -/*! @{ */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -/*! DBE - Destination Bus Error - * 0b0..No destination bus error - * 0b1..The last recorded error was a bus error on a destination write - */ -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -/*! SBE - Source Bus Error - * 0b0..No source bus error - * 0b1..The last recorded error was a bus error on a source read - */ -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -/*! SGE - Scatter/Gather Configuration Error - * 0b0..No scatter/gather configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. - */ -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -/*! NCE - NBYTES/CITER Configuration Error - * 0b0..No NBYTES/CITER configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] - */ -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -/*! DOE - Destination Offset Error - * 0b0..No destination offset configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. - */ -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -/*! DAE - Destination Address Error - * 0b0..No destination address configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. - */ -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -/*! SOE - Source Offset Error - * 0b0..No source offset configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. - */ -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -/*! SAE - Source Address Error - * 0b0..No source address configuration error. - * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. - */ -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0xF00U) -#define DMA_ES_ERRCHN_SHIFT (8U) -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -/*! CPE - Channel Priority Error - * 0b0..No channel priority error - * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. - */ -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -/*! ECX - Transfer Canceled - * 0b0..No canceled transfers - * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input - */ -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -/*! VLD - VLD - * 0b0..No ERR bits are set. - * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. - */ -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) -/*! @} */ - -/*! @name ERQ - Enable Request Register */ -/*! @{ */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -/*! ERQ0 - Enable DMA Request 0 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -/*! ERQ1 - Enable DMA Request 1 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -/*! ERQ2 - Enable DMA Request 2 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -/*! ERQ3 - Enable DMA Request 3 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) -#define DMA_ERQ_ERQ4_MASK (0x10U) -#define DMA_ERQ_ERQ4_SHIFT (4U) -/*! ERQ4 - Enable DMA Request 4 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) -#define DMA_ERQ_ERQ5_MASK (0x20U) -#define DMA_ERQ_ERQ5_SHIFT (5U) -/*! ERQ5 - Enable DMA Request 5 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) -#define DMA_ERQ_ERQ6_MASK (0x40U) -#define DMA_ERQ_ERQ6_SHIFT (6U) -/*! ERQ6 - Enable DMA Request 6 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) -#define DMA_ERQ_ERQ7_MASK (0x80U) -#define DMA_ERQ_ERQ7_SHIFT (7U) -/*! ERQ7 - Enable DMA Request 7 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) -#define DMA_ERQ_ERQ8_MASK (0x100U) -#define DMA_ERQ_ERQ8_SHIFT (8U) -/*! ERQ8 - Enable DMA Request 8 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) -#define DMA_ERQ_ERQ9_MASK (0x200U) -#define DMA_ERQ_ERQ9_SHIFT (9U) -/*! ERQ9 - Enable DMA Request 9 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) -#define DMA_ERQ_ERQ10_MASK (0x400U) -#define DMA_ERQ_ERQ10_SHIFT (10U) -/*! ERQ10 - Enable DMA Request 10 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) -#define DMA_ERQ_ERQ11_MASK (0x800U) -#define DMA_ERQ_ERQ11_SHIFT (11U) -/*! ERQ11 - Enable DMA Request 11 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) -#define DMA_ERQ_ERQ12_MASK (0x1000U) -#define DMA_ERQ_ERQ12_SHIFT (12U) -/*! ERQ12 - Enable DMA Request 12 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) -#define DMA_ERQ_ERQ13_MASK (0x2000U) -#define DMA_ERQ_ERQ13_SHIFT (13U) -/*! ERQ13 - Enable DMA Request 13 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) -#define DMA_ERQ_ERQ14_MASK (0x4000U) -#define DMA_ERQ_ERQ14_SHIFT (14U) -/*! ERQ14 - Enable DMA Request 14 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) -#define DMA_ERQ_ERQ15_MASK (0x8000U) -#define DMA_ERQ_ERQ15_SHIFT (15U) -/*! ERQ15 - Enable DMA Request 15 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) -/*! @} */ - -/*! @name EEI - Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -/*! EEI0 - Enable Error Interrupt 0 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -/*! EEI1 - Enable Error Interrupt 1 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -/*! EEI2 - Enable Error Interrupt 2 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -/*! EEI3 - Enable Error Interrupt 3 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) -#define DMA_EEI_EEI4_MASK (0x10U) -#define DMA_EEI_EEI4_SHIFT (4U) -/*! EEI4 - Enable Error Interrupt 4 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) -#define DMA_EEI_EEI5_MASK (0x20U) -#define DMA_EEI_EEI5_SHIFT (5U) -/*! EEI5 - Enable Error Interrupt 5 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) -#define DMA_EEI_EEI6_MASK (0x40U) -#define DMA_EEI_EEI6_SHIFT (6U) -/*! EEI6 - Enable Error Interrupt 6 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) -#define DMA_EEI_EEI7_MASK (0x80U) -#define DMA_EEI_EEI7_SHIFT (7U) -/*! EEI7 - Enable Error Interrupt 7 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) -#define DMA_EEI_EEI8_MASK (0x100U) -#define DMA_EEI_EEI8_SHIFT (8U) -/*! EEI8 - Enable Error Interrupt 8 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) -#define DMA_EEI_EEI9_MASK (0x200U) -#define DMA_EEI_EEI9_SHIFT (9U) -/*! EEI9 - Enable Error Interrupt 9 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) -#define DMA_EEI_EEI10_MASK (0x400U) -#define DMA_EEI_EEI10_SHIFT (10U) -/*! EEI10 - Enable Error Interrupt 10 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) -#define DMA_EEI_EEI11_MASK (0x800U) -#define DMA_EEI_EEI11_SHIFT (11U) -/*! EEI11 - Enable Error Interrupt 11 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) -#define DMA_EEI_EEI12_MASK (0x1000U) -#define DMA_EEI_EEI12_SHIFT (12U) -/*! EEI12 - Enable Error Interrupt 12 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) -#define DMA_EEI_EEI13_MASK (0x2000U) -#define DMA_EEI_EEI13_SHIFT (13U) -/*! EEI13 - Enable Error Interrupt 13 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) -#define DMA_EEI_EEI14_MASK (0x4000U) -#define DMA_EEI_EEI14_SHIFT (14U) -/*! EEI14 - Enable Error Interrupt 14 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) -#define DMA_EEI_EEI15_MASK (0x8000U) -#define DMA_EEI_EEI15_SHIFT (15U) -/*! EEI15 - Enable Error Interrupt 15 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) -/*! @} */ - -/*! @name CEEI - Clear Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_CEEI_CEEI_MASK (0xFU) -#define DMA_CEEI_CEEI_SHIFT (0U) -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -/*! CAEE - Clear All Enable Error Interrupts - * 0b0..Clear only the EEI bit specified in the CEEI field - * 0b1..Clear all bits in EEI - */ -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) -/*! @} */ - -/*! @name SEEI - Set Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_SEEI_SEEI_MASK (0xFU) -#define DMA_SEEI_SEEI_SHIFT (0U) -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -/*! SAEE - Sets All Enable Error Interrupts - * 0b0..Set only the EEI bit specified in the SEEI field. - * 0b1..Sets all bits in EEI - */ -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) -/*! @} */ - -/*! @name CERQ - Clear Enable Request Register */ -/*! @{ */ -#define DMA_CERQ_CERQ_MASK (0xFU) -#define DMA_CERQ_CERQ_SHIFT (0U) -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -/*! CAER - Clear All Enable Requests - * 0b0..Clear only the ERQ bit specified in the CERQ field - * 0b1..Clear all bits in ERQ - */ -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) -/*! @} */ - -/*! @name SERQ - Set Enable Request Register */ -/*! @{ */ -#define DMA_SERQ_SERQ_MASK (0xFU) -#define DMA_SERQ_SERQ_SHIFT (0U) -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -/*! SAER - Set All Enable Requests - * 0b0..Set only the ERQ bit specified in the SERQ field - * 0b1..Set all bits in ERQ - */ -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) -/*! @} */ - -/*! @name CDNE - Clear DONE Status Bit Register */ -/*! @{ */ -#define DMA_CDNE_CDNE_MASK (0xFU) -#define DMA_CDNE_CDNE_SHIFT (0U) -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -/*! CADN - Clears All DONE Bits - * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field - * 0b1..Clears all bits in TCDn_CSR[DONE] - */ -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) -/*! @} */ - -/*! @name SSRT - Set START Bit Register */ -/*! @{ */ -#define DMA_SSRT_SSRT_MASK (0xFU) -#define DMA_SSRT_SSRT_SHIFT (0U) -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -/*! SAST - Set All START Bits (activates all channels) - * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field - * 0b1..Set all bits in TCDn_CSR[START] - */ -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) -/*! @} */ - -/*! @name CERR - Clear Error Register */ -/*! @{ */ -#define DMA_CERR_CERR_MASK (0xFU) -#define DMA_CERR_CERR_SHIFT (0U) -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -/*! CAEI - Clear All Error Indicators - * 0b0..Clear only the ERR bit specified in the CERR field - * 0b1..Clear all bits in ERR - */ -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) -/*! @} */ - -/*! @name CINT - Clear Interrupt Request Register */ -/*! @{ */ -#define DMA_CINT_CINT_MASK (0xFU) -#define DMA_CINT_CINT_SHIFT (0U) -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -/*! CAIR - Clear All Interrupt Requests - * 0b0..Clear only the INT bit specified in the CINT field - * 0b1..Clear all bits in INT - */ -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) -/*! @} */ - -/*! @name INT - Interrupt Request Register */ -/*! @{ */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -/*! INT0 - Interrupt Request 0 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -/*! INT1 - Interrupt Request 1 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -/*! INT2 - Interrupt Request 2 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -/*! INT3 - Interrupt Request 3 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) -#define DMA_INT_INT4_MASK (0x10U) -#define DMA_INT_INT4_SHIFT (4U) -/*! INT4 - Interrupt Request 4 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) -#define DMA_INT_INT5_MASK (0x20U) -#define DMA_INT_INT5_SHIFT (5U) -/*! INT5 - Interrupt Request 5 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) -#define DMA_INT_INT6_MASK (0x40U) -#define DMA_INT_INT6_SHIFT (6U) -/*! INT6 - Interrupt Request 6 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) -#define DMA_INT_INT7_MASK (0x80U) -#define DMA_INT_INT7_SHIFT (7U) -/*! INT7 - Interrupt Request 7 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) -#define DMA_INT_INT8_MASK (0x100U) -#define DMA_INT_INT8_SHIFT (8U) -/*! INT8 - Interrupt Request 8 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) -#define DMA_INT_INT9_MASK (0x200U) -#define DMA_INT_INT9_SHIFT (9U) -/*! INT9 - Interrupt Request 9 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) -#define DMA_INT_INT10_MASK (0x400U) -#define DMA_INT_INT10_SHIFT (10U) -/*! INT10 - Interrupt Request 10 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) -#define DMA_INT_INT11_MASK (0x800U) -#define DMA_INT_INT11_SHIFT (11U) -/*! INT11 - Interrupt Request 11 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) -#define DMA_INT_INT12_MASK (0x1000U) -#define DMA_INT_INT12_SHIFT (12U) -/*! INT12 - Interrupt Request 12 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) -#define DMA_INT_INT13_MASK (0x2000U) -#define DMA_INT_INT13_SHIFT (13U) -/*! INT13 - Interrupt Request 13 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) -#define DMA_INT_INT14_MASK (0x4000U) -#define DMA_INT_INT14_SHIFT (14U) -/*! INT14 - Interrupt Request 14 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) -#define DMA_INT_INT15_MASK (0x8000U) -#define DMA_INT_INT15_SHIFT (15U) -/*! INT15 - Interrupt Request 15 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) -/*! @} */ - -/*! @name ERR - Error Register */ -/*! @{ */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -/*! ERR0 - Error In Channel 0 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -/*! ERR1 - Error In Channel 1 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -/*! ERR2 - Error In Channel 2 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -/*! ERR3 - Error In Channel 3 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) -#define DMA_ERR_ERR4_MASK (0x10U) -#define DMA_ERR_ERR4_SHIFT (4U) -/*! ERR4 - Error In Channel 4 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) -#define DMA_ERR_ERR5_MASK (0x20U) -#define DMA_ERR_ERR5_SHIFT (5U) -/*! ERR5 - Error In Channel 5 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) -#define DMA_ERR_ERR6_MASK (0x40U) -#define DMA_ERR_ERR6_SHIFT (6U) -/*! ERR6 - Error In Channel 6 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) -#define DMA_ERR_ERR7_MASK (0x80U) -#define DMA_ERR_ERR7_SHIFT (7U) -/*! ERR7 - Error In Channel 7 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) -#define DMA_ERR_ERR8_MASK (0x100U) -#define DMA_ERR_ERR8_SHIFT (8U) -/*! ERR8 - Error In Channel 8 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) -#define DMA_ERR_ERR9_MASK (0x200U) -#define DMA_ERR_ERR9_SHIFT (9U) -/*! ERR9 - Error In Channel 9 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) -#define DMA_ERR_ERR10_MASK (0x400U) -#define DMA_ERR_ERR10_SHIFT (10U) -/*! ERR10 - Error In Channel 10 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) -#define DMA_ERR_ERR11_MASK (0x800U) -#define DMA_ERR_ERR11_SHIFT (11U) -/*! ERR11 - Error In Channel 11 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) -#define DMA_ERR_ERR12_MASK (0x1000U) -#define DMA_ERR_ERR12_SHIFT (12U) -/*! ERR12 - Error In Channel 12 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) -#define DMA_ERR_ERR13_MASK (0x2000U) -#define DMA_ERR_ERR13_SHIFT (13U) -/*! ERR13 - Error In Channel 13 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) -#define DMA_ERR_ERR14_MASK (0x4000U) -#define DMA_ERR_ERR14_SHIFT (14U) -/*! ERR14 - Error In Channel 14 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) -#define DMA_ERR_ERR15_MASK (0x8000U) -#define DMA_ERR_ERR15_SHIFT (15U) -/*! ERR15 - Error In Channel 15 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) -/*! @} */ - -/*! @name HRS - Hardware Request Status Register */ -/*! @{ */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -/*! HRS0 - Hardware Request Status Channel 0 - * 0b0..A hardware service request for channel 0 is not present - * 0b1..A hardware service request for channel 0 is present - */ -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -/*! HRS1 - Hardware Request Status Channel 1 - * 0b0..A hardware service request for channel 1 is not present - * 0b1..A hardware service request for channel 1 is present - */ -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -/*! HRS2 - Hardware Request Status Channel 2 - * 0b0..A hardware service request for channel 2 is not present - * 0b1..A hardware service request for channel 2 is present - */ -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -/*! HRS3 - Hardware Request Status Channel 3 - * 0b0..A hardware service request for channel 3 is not present - * 0b1..A hardware service request for channel 3 is present - */ -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) -#define DMA_HRS_HRS4_MASK (0x10U) -#define DMA_HRS_HRS4_SHIFT (4U) -/*! HRS4 - Hardware Request Status Channel 4 - * 0b0..A hardware service request for channel 4 is not present - * 0b1..A hardware service request for channel 4 is present - */ -#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) -#define DMA_HRS_HRS5_MASK (0x20U) -#define DMA_HRS_HRS5_SHIFT (5U) -/*! HRS5 - Hardware Request Status Channel 5 - * 0b0..A hardware service request for channel 5 is not present - * 0b1..A hardware service request for channel 5 is present - */ -#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) -#define DMA_HRS_HRS6_MASK (0x40U) -#define DMA_HRS_HRS6_SHIFT (6U) -/*! HRS6 - Hardware Request Status Channel 6 - * 0b0..A hardware service request for channel 6 is not present - * 0b1..A hardware service request for channel 6 is present - */ -#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) -#define DMA_HRS_HRS7_MASK (0x80U) -#define DMA_HRS_HRS7_SHIFT (7U) -/*! HRS7 - Hardware Request Status Channel 7 - * 0b0..A hardware service request for channel 7 is not present - * 0b1..A hardware service request for channel 7 is present - */ -#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) -#define DMA_HRS_HRS8_MASK (0x100U) -#define DMA_HRS_HRS8_SHIFT (8U) -/*! HRS8 - Hardware Request Status Channel 8 - * 0b0..A hardware service request for channel 8 is not present - * 0b1..A hardware service request for channel 8 is present - */ -#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) -#define DMA_HRS_HRS9_MASK (0x200U) -#define DMA_HRS_HRS9_SHIFT (9U) -/*! HRS9 - Hardware Request Status Channel 9 - * 0b0..A hardware service request for channel 9 is not present - * 0b1..A hardware service request for channel 9 is present - */ -#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) -#define DMA_HRS_HRS10_MASK (0x400U) -#define DMA_HRS_HRS10_SHIFT (10U) -/*! HRS10 - Hardware Request Status Channel 10 - * 0b0..A hardware service request for channel 10 is not present - * 0b1..A hardware service request for channel 10 is present - */ -#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) -#define DMA_HRS_HRS11_MASK (0x800U) -#define DMA_HRS_HRS11_SHIFT (11U) -/*! HRS11 - Hardware Request Status Channel 11 - * 0b0..A hardware service request for channel 11 is not present - * 0b1..A hardware service request for channel 11 is present - */ -#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) -#define DMA_HRS_HRS12_MASK (0x1000U) -#define DMA_HRS_HRS12_SHIFT (12U) -/*! HRS12 - Hardware Request Status Channel 12 - * 0b0..A hardware service request for channel 12 is not present - * 0b1..A hardware service request for channel 12 is present - */ -#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) -#define DMA_HRS_HRS13_MASK (0x2000U) -#define DMA_HRS_HRS13_SHIFT (13U) -/*! HRS13 - Hardware Request Status Channel 13 - * 0b0..A hardware service request for channel 13 is not present - * 0b1..A hardware service request for channel 13 is present - */ -#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) -#define DMA_HRS_HRS14_MASK (0x4000U) -#define DMA_HRS_HRS14_SHIFT (14U) -/*! HRS14 - Hardware Request Status Channel 14 - * 0b0..A hardware service request for channel 14 is not present - * 0b1..A hardware service request for channel 14 is present - */ -#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) -#define DMA_HRS_HRS15_MASK (0x8000U) -#define DMA_HRS_HRS15_SHIFT (15U) -/*! HRS15 - Hardware Request Status Channel 15 - * 0b0..A hardware service request for channel 15 is not present - * 0b1..A hardware service request for channel 15 is present - */ -#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) -/*! @} */ - -/*! @name EARS - Enable Asynchronous Request in Stop Register */ -/*! @{ */ -#define DMA_EARS_EDREQ_0_MASK (0x1U) -#define DMA_EARS_EDREQ_0_SHIFT (0U) -/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. - * 0b0..Disable asynchronous DMA request for channel 0. - * 0b1..Enable asynchronous DMA request for channel 0. - */ -#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) -#define DMA_EARS_EDREQ_1_MASK (0x2U) -#define DMA_EARS_EDREQ_1_SHIFT (1U) -/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. - * 0b0..Disable asynchronous DMA request for channel 1 - * 0b1..Enable asynchronous DMA request for channel 1. - */ -#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) -#define DMA_EARS_EDREQ_2_MASK (0x4U) -#define DMA_EARS_EDREQ_2_SHIFT (2U) -/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. - * 0b0..Disable asynchronous DMA request for channel 2. - * 0b1..Enable asynchronous DMA request for channel 2. - */ -#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) -#define DMA_EARS_EDREQ_3_MASK (0x8U) -#define DMA_EARS_EDREQ_3_SHIFT (3U) -/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. - * 0b0..Disable asynchronous DMA request for channel 3. - * 0b1..Enable asynchronous DMA request for channel 3. - */ -#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) -#define DMA_EARS_EDREQ_4_MASK (0x10U) -#define DMA_EARS_EDREQ_4_SHIFT (4U) -/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 - * 0b0..Disable asynchronous DMA request for channel 4. - * 0b1..Enable asynchronous DMA request for channel 4. - */ -#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) -#define DMA_EARS_EDREQ_5_MASK (0x20U) -#define DMA_EARS_EDREQ_5_SHIFT (5U) -/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 - * 0b0..Disable asynchronous DMA request for channel 5. - * 0b1..Enable asynchronous DMA request for channel 5. - */ -#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) -#define DMA_EARS_EDREQ_6_MASK (0x40U) -#define DMA_EARS_EDREQ_6_SHIFT (6U) -/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 - * 0b0..Disable asynchronous DMA request for channel 6. - * 0b1..Enable asynchronous DMA request for channel 6. - */ -#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) -#define DMA_EARS_EDREQ_7_MASK (0x80U) -#define DMA_EARS_EDREQ_7_SHIFT (7U) -/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 - * 0b0..Disable asynchronous DMA request for channel 7. - * 0b1..Enable asynchronous DMA request for channel 7. - */ -#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) -#define DMA_EARS_EDREQ_8_MASK (0x100U) -#define DMA_EARS_EDREQ_8_SHIFT (8U) -/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 - * 0b0..Disable asynchronous DMA request for channel 8. - * 0b1..Enable asynchronous DMA request for channel 8. - */ -#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) -#define DMA_EARS_EDREQ_9_MASK (0x200U) -#define DMA_EARS_EDREQ_9_SHIFT (9U) -/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 - * 0b0..Disable asynchronous DMA request for channel 9. - * 0b1..Enable asynchronous DMA request for channel 9. - */ -#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) -#define DMA_EARS_EDREQ_10_MASK (0x400U) -#define DMA_EARS_EDREQ_10_SHIFT (10U) -/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 - * 0b0..Disable asynchronous DMA request for channel 10. - * 0b1..Enable asynchronous DMA request for channel 10. - */ -#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) -#define DMA_EARS_EDREQ_11_MASK (0x800U) -#define DMA_EARS_EDREQ_11_SHIFT (11U) -/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 - * 0b0..Disable asynchronous DMA request for channel 11. - * 0b1..Enable asynchronous DMA request for channel 11. - */ -#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) -#define DMA_EARS_EDREQ_12_MASK (0x1000U) -#define DMA_EARS_EDREQ_12_SHIFT (12U) -/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 - * 0b0..Disable asynchronous DMA request for channel 12. - * 0b1..Enable asynchronous DMA request for channel 12. - */ -#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) -#define DMA_EARS_EDREQ_13_MASK (0x2000U) -#define DMA_EARS_EDREQ_13_SHIFT (13U) -/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 - * 0b0..Disable asynchronous DMA request for channel 13. - * 0b1..Enable asynchronous DMA request for channel 13. - */ -#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) -#define DMA_EARS_EDREQ_14_MASK (0x4000U) -#define DMA_EARS_EDREQ_14_SHIFT (14U) -/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 - * 0b0..Disable asynchronous DMA request for channel 14. - * 0b1..Enable asynchronous DMA request for channel 14. - */ -#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) -#define DMA_EARS_EDREQ_15_MASK (0x8000U) -#define DMA_EARS_EDREQ_15_SHIFT (15U) -/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 - * 0b0..Disable asynchronous DMA request for channel 15. - * 0b1..Enable asynchronous DMA request for channel 15. - */ -#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) -/*! @} */ - -/*! @name DCHPRI3 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI3_CHPRI_MASK (0xFU) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI2 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI2_CHPRI_MASK (0xFU) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI1 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI1_CHPRI_MASK (0xFU) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI0 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI0_CHPRI_MASK (0xFU) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI7 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI7_CHPRI_MASK (0xFU) -#define DMA_DCHPRI7_CHPRI_SHIFT (0U) -#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) -#define DMA_DCHPRI7_DPA_MASK (0x40U) -#define DMA_DCHPRI7_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) -#define DMA_DCHPRI7_ECP_MASK (0x80U) -#define DMA_DCHPRI7_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI6 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI6_CHPRI_MASK (0xFU) -#define DMA_DCHPRI6_CHPRI_SHIFT (0U) -#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) -#define DMA_DCHPRI6_DPA_MASK (0x40U) -#define DMA_DCHPRI6_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) -#define DMA_DCHPRI6_ECP_MASK (0x80U) -#define DMA_DCHPRI6_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI5 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI5_CHPRI_MASK (0xFU) -#define DMA_DCHPRI5_CHPRI_SHIFT (0U) -#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) -#define DMA_DCHPRI5_DPA_MASK (0x40U) -#define DMA_DCHPRI5_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) -#define DMA_DCHPRI5_ECP_MASK (0x80U) -#define DMA_DCHPRI5_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI4 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI4_CHPRI_MASK (0xFU) -#define DMA_DCHPRI4_CHPRI_SHIFT (0U) -#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) -#define DMA_DCHPRI4_DPA_MASK (0x40U) -#define DMA_DCHPRI4_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) -#define DMA_DCHPRI4_ECP_MASK (0x80U) -#define DMA_DCHPRI4_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI11 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI11_CHPRI_MASK (0xFU) -#define DMA_DCHPRI11_CHPRI_SHIFT (0U) -#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) -#define DMA_DCHPRI11_DPA_MASK (0x40U) -#define DMA_DCHPRI11_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) -#define DMA_DCHPRI11_ECP_MASK (0x80U) -#define DMA_DCHPRI11_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI10 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI10_CHPRI_MASK (0xFU) -#define DMA_DCHPRI10_CHPRI_SHIFT (0U) -#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) -#define DMA_DCHPRI10_DPA_MASK (0x40U) -#define DMA_DCHPRI10_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) -#define DMA_DCHPRI10_ECP_MASK (0x80U) -#define DMA_DCHPRI10_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI9 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI9_CHPRI_MASK (0xFU) -#define DMA_DCHPRI9_CHPRI_SHIFT (0U) -#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) -#define DMA_DCHPRI9_DPA_MASK (0x40U) -#define DMA_DCHPRI9_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) -#define DMA_DCHPRI9_ECP_MASK (0x80U) -#define DMA_DCHPRI9_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI8 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI8_CHPRI_MASK (0xFU) -#define DMA_DCHPRI8_CHPRI_SHIFT (0U) -#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) -#define DMA_DCHPRI8_DPA_MASK (0x40U) -#define DMA_DCHPRI8_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) -#define DMA_DCHPRI8_ECP_MASK (0x80U) -#define DMA_DCHPRI8_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI15 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI15_CHPRI_MASK (0xFU) -#define DMA_DCHPRI15_CHPRI_SHIFT (0U) -#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) -#define DMA_DCHPRI15_DPA_MASK (0x40U) -#define DMA_DCHPRI15_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) -#define DMA_DCHPRI15_ECP_MASK (0x80U) -#define DMA_DCHPRI15_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI14 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI14_CHPRI_MASK (0xFU) -#define DMA_DCHPRI14_CHPRI_SHIFT (0U) -#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) -#define DMA_DCHPRI14_DPA_MASK (0x40U) -#define DMA_DCHPRI14_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) -#define DMA_DCHPRI14_ECP_MASK (0x80U) -#define DMA_DCHPRI14_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI13 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI13_CHPRI_MASK (0xFU) -#define DMA_DCHPRI13_CHPRI_SHIFT (0U) -#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) -#define DMA_DCHPRI13_DPA_MASK (0x40U) -#define DMA_DCHPRI13_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) -#define DMA_DCHPRI13_ECP_MASK (0x80U) -#define DMA_DCHPRI13_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI12 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI12_CHPRI_MASK (0xFU) -#define DMA_DCHPRI12_CHPRI_SHIFT (0U) -#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) -#define DMA_DCHPRI12_DPA_MASK (0x40U) -#define DMA_DCHPRI12_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) -#define DMA_DCHPRI12_ECP_MASK (0x80U) -#define DMA_DCHPRI12_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) -/*! @} */ - -/*! @name SADDR - TCD Source Address */ -/*! @{ */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) -/*! @} */ - -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (16U) - -/*! @name SOFF - TCD Signed Source Address Offset */ -/*! @{ */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) -/*! @} */ - -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (16U) - -/*! @name ATTR - TCD Transfer Attributes */ -/*! @{ */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -/*! SSIZE - Source data transfer size - * 0b000..8-bit - * 0b001..16-bit - * 0b010..32-bit - * 0b011..Reserved - * 0b100..16-byte burst - * 0b101..32-byte burst - * 0b110..Reserved - * 0b111..Reserved - */ -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -/*! SMOD - Source Address Modulo - * 0b00000..Source address modulo feature is disabled - * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. - */ -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) -/*! @} */ - -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (16U) - -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (16U) - -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR - */ -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR - */ -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (16U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR - */ -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR - */ -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (16U) - -/*! @name SLAST - TCD Last Source Address Adjustment */ -/*! @{ */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) -/*! @} */ - -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (16U) - -/*! @name DADDR - TCD Destination Address */ -/*! @{ */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) -/*! @} */ - -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (16U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ -/*! @{ */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) -/*! @} */ - -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (16U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (16U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (16U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ -/*! @{ */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) -/*! @} */ - -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (16U) - -/*! @name CSR - TCD Control and Status */ -/*! @{ */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -/*! START - Channel Start - * 0b0..The channel is not explicitly started. - * 0b1..The channel is explicitly started via a software initiated service request. - */ -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -/*! INTMAJOR - Enable an interrupt when major iteration count completes. - * 0b0..The end-of-major loop interrupt is disabled. - * 0b1..The end-of-major loop interrupt is enabled. - */ -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -/*! INTHALF - Enable an interrupt when major counter is half complete. - * 0b0..The half-point interrupt is disabled. - * 0b1..The half-point interrupt is enabled. - */ -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -/*! DREQ - Disable Request - * 0b0..The channel's ERQ bit is not affected. - * 0b1..The channel's ERQ bit is cleared when the major loop is complete. - */ -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -/*! ESG - Enable Scatter/Gather Processing - * 0b0..The current channel's TCD is normal format. - * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. - */ -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -/*! MAJORELINK - Enable channel-to-channel linking on major loop complete - * 0b0..The channel-to-channel linking is disabled. - * 0b1..The channel-to-channel linking is enabled. - */ -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0xF00U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -/*! BWC - Bandwidth Control - * 0b00..No eDMA engine stalls. - * 0b01..Reserved - * 0b10..eDMA engine stalls for 4 cycles after each R/W. - * 0b11..eDMA engine stalls for 8 cycles after each R/W. - */ -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) -/*! @} */ - -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (16U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (16U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (16U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40008000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { {DMA0_0_4_8_12_IRQn, DMA0_1_5_9_13_IRQn, DMA0_2_6_10_14_IRQn, DMA0_3_7_11_15_IRQn} } -#define DMA_ERROR_IRQS { DMA0_Error_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CHCFG[16]; /**< Channel 0 Configuration Register..Channel 15 Configuration Register, array offset: 0x0, array step: 0x4 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/*! @name CHCFG - Channel 0 Configuration Register..Channel 15 Configuration Register */ -/*! @{ */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) -#define DMAMUX_CHCFG_A_ON_SHIFT (29U) -/*! A_ON - DMA Channel Always Enable - * 0b0..DMA Channel Always ON function is disabled - * 0b1..DMA Channel Always ON function is enabled - */ -#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) -#define DMAMUX_CHCFG_TRIG_SHIFT (30U) -/*! TRIG - DMA Channel Trigger Enable - * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) - * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. - */ -#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) -#define DMAMUX_CHCFG_ENBL_SHIFT (31U) -/*! ENBL - DMA Mux Channel Enable - * 0b0..DMA Mux channel is disabled - * 0b1..DMA Mux channel is enabled - */ -#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) -/*! @} */ - -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (16U) - - -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX0 base address */ -#define DMAMUX0_BASE (0x40021000u) -/** Peripheral DMAMUX0 base pointer */ -#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { DMAMUX0 } - -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EMVSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer - * @{ - */ - -/** EMVSIM - Register Layout Typedef */ -typedef struct { - __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ - __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ - __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ - __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ - __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ - __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ - __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ - __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ - __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ - __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ - __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ - __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ - __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ - __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ - __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ - __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ - __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ -} EMVSIM_Type; - -/* ---------------------------------------------------------------------------- - -- EMVSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks - * @{ - */ - -/*! @name VER_ID - Version ID Register */ -/*! @{ */ -#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) -#define EMVSIM_VER_ID_VER_SHIFT (0U) -#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) -#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) -#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) -#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) -#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) -#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) -/*! @} */ - -/*! @name CLKCFG - Clock Configuration Register */ -/*! @{ */ -#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) -#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) -/*! CLK_PRSC - Clock Prescaler Value - * 0b00000010..Divide by 2 - */ -#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) -/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select - * 0b00..Disabled / Reset (default) - * 0b01..Card Clock - * 0b10..Receive Clock - * 0b11..ETU Clock (transmit clock) - */ -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) -/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select - * 0b00..Disabled / Reset (default) - * 0b01..Card Clock - * 0b10..Receive Clock - * 0b11..ETU Clock (transmit clock) - */ -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) -/*! @} */ - -/*! @name DIVISOR - Baud Rate Divisor Register */ -/*! @{ */ -#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) -#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) -/*! DIVISOR_VALUE - Divisor (F/D) Value - * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 - * 0b101110100..Divisor value for F = 372 and D = 1 (default) - */ -#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) -/*! @} */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define EMVSIM_CTRL_IC_MASK (0x1U) -#define EMVSIM_CTRL_IC_SHIFT (0U) -/*! IC - Inverse Convention - * 0b0..Direction convention transfers enabled (default) - * 0b1..Inverse convention transfers enabled - */ -#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) -#define EMVSIM_CTRL_ICM_MASK (0x2U) -#define EMVSIM_CTRL_ICM_SHIFT (1U) -/*! ICM - Initial Character Mode - * 0b0..Initial Character Mode disabled - * 0b1..Initial Character Mode enabled (default) - */ -#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) -#define EMVSIM_CTRL_ANACK_MASK (0x4U) -#define EMVSIM_CTRL_ANACK_SHIFT (2U) -/*! ANACK - Auto NACK Enable - * 0b0..NACK generation on errors disabled - * 0b1..NACK generation on errors enabled (default) - */ -#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) -#define EMVSIM_CTRL_ONACK_MASK (0x8U) -#define EMVSIM_CTRL_ONACK_SHIFT (3U) -/*! ONACK - Overrun NACK Enable - * 0b0..NACK generation on overrun is disabled (default) - * 0b1..NACK generation on overrun is enabled - */ -#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) -#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) -#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) -/*! FLSH_RX - Flush Receiver Bit - * 0b0..EMV SIM Receiver normal operation (default) - * 0b1..EMV SIM Receiver held in Reset - */ -#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) -#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) -#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) -/*! FLSH_TX - Flush Transmitter Bit - * 0b0..EMV SIM Transmitter normal operation (default) - * 0b1..EMV SIM Transmitter held in Reset - */ -#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) -#define EMVSIM_CTRL_SW_RST_MASK (0x400U) -#define EMVSIM_CTRL_SW_RST_SHIFT (10U) -/*! SW_RST - Software Reset Bit - * 0b0..EMV SIM Normal operation (default) - * 0b1..EMV SIM held in Reset - */ -#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) -#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) -#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) -/*! KILL_CLOCKS - Kill all internal clocks - * 0b0..EMV SIM input clock enabled (default) - * 0b1..EMV SIM input clock is disabled - */ -#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) -#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) -#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) -/*! DOZE_EN - Doze Enable - * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) - * 0b1..DOZE instruction has no effect on EMV SIM module - */ -#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) -#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) -#define EMVSIM_CTRL_STOP_EN_SHIFT (13U) -/*! STOP_EN - STOP Enable - * 0b0..STOP instruction shuts down all EMV SIM clocks (default) - * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) - */ -#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) -#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) -#define EMVSIM_CTRL_RCV_EN_SHIFT (16U) -/*! RCV_EN - Receiver Enable - * 0b0..EMV SIM Receiver disabled (default) - * 0b1..EMV SIM Receiver enabled - */ -#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) -#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) -#define EMVSIM_CTRL_XMT_EN_SHIFT (17U) -/*! XMT_EN - Transmitter Enable - * 0b0..EMV SIM Transmitter disabled (default) - * 0b1..EMV SIM Transmitter enabled - */ -#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) -#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) -#define EMVSIM_CTRL_RCVR_11_SHIFT (18U) -/*! RCVR_11 - Receiver 11 ETU Mode Enable - * 0b0..Receiver configured for 12 ETU operation mode (default) - * 0b1..Receiver configured for 11 ETU operation mode - */ -#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) -#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) -#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) -/*! RX_DMA_EN - Receive DMA Enable - * 0b0..No DMA Read Request asserted for Receiver (default) - * 0b1..DMA Read Request asserted for Receiver - */ -#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) -#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) -#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) -/*! TX_DMA_EN - Transmit DMA Enable - * 0b0..No DMA Write Request asserted for Transmitter (default) - * 0b1..DMA Write Request asserted for Transmitter - */ -#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) -#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) -#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) -/*! INV_CRC_VAL - Invert bits in the CRC Output Value - * 0b0..Bits in CRC Output value will not be inverted. - * 0b1..Bits in CRC Output value will be inverted. (default) - */ -#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) -#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) -#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) -/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip - * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) - * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} - */ -#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) -#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) -#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) -/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control - * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) - * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation - */ -#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) -#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) -#define EMVSIM_CTRL_CWT_EN_SHIFT (27U) -/*! CWT_EN - Character Wait Time Counter Enable - * 0b0..Character Wait time Counter is disabled (default) - * 0b1..Character Wait time counter is enabled - */ -#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) -#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) -#define EMVSIM_CTRL_LRC_EN_SHIFT (28U) -/*! LRC_EN - LRC Enable - * 0b0..8-bit Linear Redundancy Checking disabled (default) - * 0b1..8-bit Linear Redundancy Checking enabled - */ -#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) -#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) -#define EMVSIM_CTRL_CRC_EN_SHIFT (29U) -/*! CRC_EN - CRC Enable - * 0b0..16-bit Cyclic Redundancy Checking disabled (default) - * 0b1..16-bit Cyclic Redundancy Checking enabled - */ -#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) -#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) -#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) -/*! XMT_CRC_LRC - Transmit CRC or LRC Enable - * 0b0..No CRC or LRC value is transmitted (default) - * 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled) - */ -#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) -#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) -#define EMVSIM_CTRL_BWT_EN_SHIFT (31U) -/*! BWT_EN - Block Wait Time Counter Enable - * 0b0..Disable BWT, BGT Counters (default) - * 0b1..Enable BWT, BGT Counters - */ -#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) -/*! @} */ - -/*! @name INT_MASK - Interrupt Mask Register */ -/*! @{ */ -#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) -#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) -/*! RDT_IM - Receive Data Threshold Interrupt Mask - * 0b0..RDTF interrupt enabled - * 0b1..RDTF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) -#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) -#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) -/*! TC_IM - Transmit Complete Interrupt Mask - * 0b0..TCF interrupt enabled - * 0b1..TCF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) -#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) -#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) -/*! RFO_IM - Receive FIFO Overflow Interrupt Mask - * 0b0..RFO interrupt enabled - * 0b1..RFO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) -#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) -#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) -/*! ETC_IM - Early Transmit Complete Interrupt Mask - * 0b0..ETC interrupt enabled - * 0b1..ETC interrupt masked (default) - */ -#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) -#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) -#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) -/*! TFE_IM - Transmit FIFO Empty Interrupt Mask - * 0b0..TFE interrupt enabled - * 0b1..TFE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) -#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) -#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) -/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask - * 0b0..TNTE interrupt enabled - * 0b1..TNTE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) -#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) -#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) -/*! TFF_IM - Transmit FIFO Full Interrupt Mask - * 0b0..TFF interrupt enabled - * 0b1..TFF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) -#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) -#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) -/*! TDT_IM - Transmit Data Threshold Interrupt Mask - * 0b0..TDTF interrupt enabled - * 0b1..TDTF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) -#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) -#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) -/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask - * 0b0..GPCNT0_TO interrupt enabled - * 0b1..GPCNT0_TO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) -#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) -#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) -/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask - * 0b0..CWT_ERR interrupt enabled - * 0b1..CWT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) -#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) -/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask - * 0b0..RTE interrupt enabled - * 0b1..RTE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) -#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) -#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) -/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask - * 0b0..BWT_ERR interrupt enabled - * 0b1..BWT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) -#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) -/*! BGT_ERR_IM - Block Guard Time Error Interrupt - * 0b0..BGT_ERR interrupt enabled - * 0b1..BGT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) -#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) -/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask - * 0b0..GPCNT1_TO interrupt enabled - * 0b1..GPCNT1_TO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) -#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) -#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) -/*! RX_DATA_IM - Receive Data Interrupt Mask - * 0b0..RX_DATA interrupt enabled - * 0b1..RX_DATA interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) -#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) -#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) -/*! PEF_IM - Parity Error Interrupt Mask - * 0b0..PEF interrupt enabled - * 0b1..PEF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) -/*! @} */ - -/*! @name RX_THD - Receiver Threshold Register */ -/*! @{ */ -#define EMVSIM_RX_THD_RDT_MASK (0xFU) -#define EMVSIM_RX_THD_RDT_SHIFT (0U) -#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) -#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) -#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) -/*! RNCK_THD - Receiver NACK Threshold Value - * 0b0000..Zero Threshold. RTE will not be set - */ -#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) -/*! @} */ - -/*! @name TX_THD - Transmitter Threshold Register */ -/*! @{ */ -#define EMVSIM_TX_THD_TDT_MASK (0xFU) -#define EMVSIM_TX_THD_TDT_SHIFT (0U) -#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) -#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) -#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) -/*! TNCK_THD - Transmitter NACK Threshold Value - * 0b0000..TNTE will never be set; retransmission after NACK reception is disabled. - * 0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs. - * 0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs. - * 0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs. - * 0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs. - */ -#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) -/*! @} */ - -/*! @name RX_STATUS - Receive Status Register */ -/*! @{ */ -#define EMVSIM_RX_STATUS_RFO_MASK (0x1U) -#define EMVSIM_RX_STATUS_RFO_SHIFT (0U) -/*! RFO - Receive FIFO Overflow Flag - * 0b0..No overrun error has occurred (default) - * 0b1..A byte was received when the received FIFO was already full - */ -#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) -#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) -#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) -/*! RX_DATA - Receive Data Interrupt Flag - * 0b0..No new byte is received - * 0b1..New byte is received ans stored in Receive FIFO - */ -#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) -#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) -#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) -/*! RDTF - Receive Data Threshold Interrupt Flag - * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). - * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. - */ -#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) -#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) -#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) -/*! LRC_OK - LRC Check OK Flag - * 0b0..Current LRC value does not match remainder. - * 0b1..Current calculated LRC value matches the expected result (i.e. zero). - */ -#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) -#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) -#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) -/*! CRC_OK - CRC Check OK Flag - * 0b0..Current CRC value does not match remainder. - * 0b1..Current calculated CRC value matches the expected result. - */ -#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) -#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) -#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) -/*! CWT_ERR - Character Wait Time Error Flag - * 0b0..No CWT violation has occurred (default). - * 0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT. - */ -#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) -#define EMVSIM_RX_STATUS_RTE_MASK (0x200U) -#define EMVSIM_RX_STATUS_RTE_SHIFT (9U) -/*! RTE - Received NACK Threshold Error Flag - * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] - * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] - */ -#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) -#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) -#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) -/*! BWT_ERR - Block Wait Time Error Flag - * 0b0..Block wait time not exceeded - * 0b1..Block wait time was exceeded - */ -#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) -#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) -#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) -/*! BGT_ERR - Block Guard Time Error Flag - * 0b0..Block guard time was sufficient - * 0b1..Block guard time was too small - */ -#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) -#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) -#define EMVSIM_RX_STATUS_PEF_SHIFT (12U) -/*! PEF - Parity Error Flag - * 0b0..No parity error detected - * 0b1..Parity error detected - */ -#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) -#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) -#define EMVSIM_RX_STATUS_FEF_SHIFT (13U) -/*! FEF - Frame Error Flag - * 0b0..No frame error detected - * 0b1..Frame error detected - */ -#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) -#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) -#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) -#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) -#define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) -#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) -/*! RX_CNT - Receive FIFO Byte Count - * 0b0000..FIFO is emtpy - */ -#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) -/*! @} */ - -/*! @name TX_STATUS - Transmitter Status Register */ -/*! @{ */ -#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) -#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) -/*! TNTE - Transmit NACK Threshold Error Flag - * 0b0..Transmit NACK threshold has not been reached (default) - * 0b1..Transmit NACK threshold reached; transmitter frozen - */ -#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) -#define EMVSIM_TX_STATUS_TFE_MASK (0x8U) -#define EMVSIM_TX_STATUS_TFE_SHIFT (3U) -/*! TFE - Transmit FIFO Empty Flag - * 0b0..Transmit FIFO is not empty - * 0b1..Transmit FIFO is empty (default) - */ -#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) -#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) -#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) -/*! ETCF - Early Transmit Complete Flag - * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) - */ -#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) -#define EMVSIM_TX_STATUS_TCF_MASK (0x20U) -#define EMVSIM_TX_STATUS_TCF_SHIFT (5U) -/*! TCF - Transmit Complete Flag - * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) - */ -#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) -#define EMVSIM_TX_STATUS_TFF_MASK (0x40U) -#define EMVSIM_TX_STATUS_TFF_SHIFT (6U) -/*! TFF - Transmit FIFO Full Flag - * 0b0..Transmit FIFO Full condition has not occurred (default) - * 0b1..A Transmit FIFO Full condition has occurred - */ -#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) -#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) -#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) -/*! TDTF - Transmit Data Threshold Flag - * 0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared - * 0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default) - */ -#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) -#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) -#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) -/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag - * 0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT0_VAL value - */ -#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) -#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) -#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) -/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag - * 0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT1_VAL value - */ -#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) -#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) -#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) -#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) -#define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) -#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) -/*! TX_CNT - Transmit FIFO Byte Count - * 0b0000..FIFO is emtpy - */ -#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) -/*! @} */ - -/*! @name PCSR - Port Control and Status Register */ -/*! @{ */ -#define EMVSIM_PCSR_SAPD_MASK (0x1U) -#define EMVSIM_PCSR_SAPD_SHIFT (0U) -/*! SAPD - Auto Power Down Enable - * 0b0..Auto power down disabled (default) - * 0b1..Auto power down enabled - */ -#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) -#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) -#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) -/*! SVCC_EN - Vcc Enable for Smart Card - * 0b0..Smart Card Voltage disabled (default) - * 0b1..Smart Card Voltage enabled - */ -#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) -#define EMVSIM_PCSR_VCCENP_MASK (0x4U) -#define EMVSIM_PCSR_VCCENP_SHIFT (2U) -/*! VCCENP - VCC Enable Polarity Control - * 0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged. - * 0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted. - */ -#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) -#define EMVSIM_PCSR_SRST_MASK (0x8U) -#define EMVSIM_PCSR_SRST_SHIFT (3U) -/*! SRST - Reset to Smart Card - * 0b0..Smart Card Reset is asserted (default) - * 0b1..Smart Card Reset is de-asserted - */ -#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) -#define EMVSIM_PCSR_SCEN_MASK (0x10U) -#define EMVSIM_PCSR_SCEN_SHIFT (4U) -/*! SCEN - Clock Enable for Smart Card - * 0b0..Smart Card Clock Disabled - * 0b1..Smart Card Clock Enabled - */ -#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) -#define EMVSIM_PCSR_SCSP_MASK (0x20U) -#define EMVSIM_PCSR_SCSP_SHIFT (5U) -/*! SCSP - Smart Card Clock Stop Polarity - * 0b0..Clock is logic 0 when stopped by SCEN - * 0b1..Clock is logic 1 when stopped by SCEN - */ -#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) -#define EMVSIM_PCSR_SPD_MASK (0x80U) -#define EMVSIM_PCSR_SPD_SHIFT (7U) -/*! SPD - Auto Power Down Control - * 0b0..No effect (default) - * 0b1..Start Auto Powerdown or Power Down is in progress - */ -#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) -#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) -#define EMVSIM_PCSR_SPDIM_SHIFT (24U) -/*! SPDIM - Smart Card Presence Detect Interrupt Mask - * 0b0..SIM presence detect interrupt is enabled - * 0b1..SIM presence detect interrupt is masked (default) - */ -#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) -#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) -#define EMVSIM_PCSR_SPDIF_SHIFT (25U) -/*! SPDIF - Smart Card Presence Detect Interrupt Flag - * 0b0..No insertion or removal of Smart Card detected on Port (default) - * 0b1..Insertion or removal of Smart Card detected on Port - */ -#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) -#define EMVSIM_PCSR_SPDP_MASK (0x4000000U) -#define EMVSIM_PCSR_SPDP_SHIFT (26U) -/*! SPDP - Smart Card Presence Detect Pin Status - * 0b0..SIM Presence Detect pin is logic low - * 0b1..SIM Presence Detectpin is logic high - */ -#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) -#define EMVSIM_PCSR_SPDES_MASK (0x8000000U) -#define EMVSIM_PCSR_SPDES_SHIFT (27U) -/*! SPDES - SIM Presence Detect Edge Select - * 0b0..Falling edge on the pin (default) - * 0b1..Rising edge on the pin - */ -#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) -/*! @} */ - -/*! @name RX_BUF - Receive Data Read Buffer */ -/*! @{ */ -#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) -#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) -#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) -/*! @} */ - -/*! @name TX_BUF - Transmit Data Buffer */ -/*! @{ */ -#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) -#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) -#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) -/*! @} */ - -/*! @name TX_GETU - Transmitter Guard ETU Value Register */ -/*! @{ */ -#define EMVSIM_TX_GETU_GETU_MASK (0xFFU) -#define EMVSIM_TX_GETU_GETU_SHIFT (0U) -/*! GETU - Transmitter Guard Time Value in ETU - * 0b00000000..no additional ETUs inserted (default) - * 0b00000001..1 additional ETU inserted - * 0b11111110..254 additional ETUs inserted - * 0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one - */ -#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) -/*! @} */ - -/*! @name CWT_VAL - Character Wait Time Value Register */ -/*! @{ */ -#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) -#define EMVSIM_CWT_VAL_CWT_SHIFT (0U) -#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) -/*! @} */ - -/*! @name BWT_VAL - Block Wait Time Value Register */ -/*! @{ */ -#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) -#define EMVSIM_BWT_VAL_BWT_SHIFT (0U) -#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) -/*! @} */ - -/*! @name BGT_VAL - Block Guard Time Value Register */ -/*! @{ */ -#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) -#define EMVSIM_BGT_VAL_BGT_SHIFT (0U) -#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) -/*! @} */ - -/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ -/*! @{ */ -#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) -#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) -#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) -/*! @} */ - -/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ -/*! @{ */ -#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) -#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) -#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EMVSIM_Register_Masks */ - - -/* EMVSIM - Peripheral instance base addresses */ -/** Peripheral EMVSIM0 base address */ -#define EMVSIM0_BASE (0x40038000u) -/** Peripheral EMVSIM0 base pointer */ -#define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) -/** Array initializer of EMVSIM peripheral base addresses */ -#define EMVSIM_BASE_ADDRS { EMVSIM0_BASE } -/** Array initializer of EMVSIM peripheral base pointers */ -#define EMVSIM_BASE_PTRS { EMVSIM0 } -/** Interrupt vectors for the EMVSIM peripheral type */ -#define EMVSIM_IRQS { EMVSIM0_IRQn } - -/*! - * @} - */ /* end of group EMVSIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EVENT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EVENT_Peripheral_Access_Layer EVENT Peripheral Access Layer - * @{ - */ - -/** EVENT - Register Layout Typedef */ -typedef struct { - __IO uint32_t INTPTEN; /**< Interrupt Enable Register, offset: 0x0 */ - __IO uint32_t INTPTPEND; /**< Interrupt Pengding Register, offset: 0x4 */ - __IO uint32_t INTPTPENDSET; /**< Set Interrupt Pengding Register, offset: 0x8 */ - __IO uint32_t INTPTPENDCLEAR; /**< Clear Interrupt Pengding Register, offset: 0xC */ - __IO uint32_t INTPTSECURE; /**< Interrupt Secure Register, offset: 0x10 */ - __IO uint32_t INTPTPRI[4]; /**< Interrupt Priority 0 Register..Interrupt Priority 3 Register, array offset: 0x14, array step: 0x4 */ - __IO uint32_t INTPRIBASE; /**< Interrupt Priority Base, offset: 0x24 */ - __I uint32_t INTPTENACTIVE; /**< Interrupt Active Register, offset: 0x28 */ - __I uint32_t INTACTPRI[4]; /**< Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register, array offset: 0x2C, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t EVENTEN; /**< Event Enable Register, offset: 0x40 */ - __IO uint32_t EVENTPEND; /**< Event Pengding Register, offset: 0x44 */ - __IO uint32_t EVTPENDSET; /**< Set Event Pengding Register, offset: 0x48 */ - __IO uint32_t EVTPENDCLEAR; /**< Clear Event Pengding Register, offset: 0x4C */ - uint8_t RESERVED_1[48]; - __IO uint32_t SLPCTRL; /**< Sleep Control Register, offset: 0x80 */ - __IO uint32_t SLPSTATUS; /**< Sleep Status Register, offset: 0x84 */ -} EVENT_Type; - -/* ---------------------------------------------------------------------------- - -- EVENT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EVENT_Register_Masks EVENT Register Masks - * @{ - */ - -/*! @name INTPTEN - Interrupt Enable Register */ -/*! @{ */ -#define EVENT_INTPTEN_IEN_MASK (0xFFFFFFFFU) -#define EVENT_INTPTEN_IEN_SHIFT (0U) -/*! IEN - Interrupt n Enable - * 0b00000000000000000000000000000000..Interrupt n is disabled. - * 0b00000000000000000000000000000001..Interrupt n is enabled. - */ -#define EVENT_INTPTEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTEN_IEN_SHIFT)) & EVENT_INTPTEN_IEN_MASK) -/*! @} */ - -/*! @name INTPTPEND - Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPEND_IPEND_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPEND_IPEND_SHIFT (0U) -/*! IPEND - Interrupt n Pending - * 0b00000000000000000000000000000000..Interrupt n is not pending. - * 0b00000000000000000000000000000001..Interrupt n is pending. - */ -#define EVENT_INTPTPEND_IPEND(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPEND_IPEND_SHIFT)) & EVENT_INTPTPEND_IPEND_MASK) -/*! @} */ - -/*! @name INTPTPENDSET - Set Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPENDSET_IPENDSET_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPENDSET_IPENDSET_SHIFT (0U) -/*! IPENDSET - Set Interrupt n Pending - * 0b00000000000000000000000000000000..Not set interrupt n in pending status - * 0b00000000000000000000000000000001..Set interrupt n in pending status. - */ -#define EVENT_INTPTPENDSET_IPENDSET(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDSET_IPENDSET_SHIFT)) & EVENT_INTPTPENDSET_IPENDSET_MASK) -/*! @} */ - -/*! @name INTPTPENDCLEAR - Clear Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT (0U) -/*! IPENDCLEAR - Clear Interrupt n out of Pending - * 0b00000000000000000000000000000000..Not clear interrupt n out of pending status - * 0b00000000000000000000000000000001..Clear interrupt n out of pending status. - */ -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT)) & EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK) -/*! @} */ - -/*! @name INTPTSECURE - Interrupt Secure Register */ -/*! @{ */ -#define EVENT_INTPTSECURE_ISECURE_MASK (0xFFFFFFFFU) -#define EVENT_INTPTSECURE_ISECURE_SHIFT (0U) -/*! ISECURE - Set secure feature of Interrupt n - * 0b00000000000000000000000000000000..Set interrupt n out of security - * 0b00000000000000000000000000000001..Set interrupt n in secruity. - */ -#define EVENT_INTPTSECURE_ISECURE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTSECURE_ISECURE_SHIFT)) & EVENT_INTPTSECURE_ISECURE_MASK) -/*! @} */ - -/*! @name INTPTPRI - Interrupt Priority 0 Register..Interrupt Priority 3 Register */ -/*! @{ */ -#define EVENT_INTPTPRI_IPRI0_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI0_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI0(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI0_SHIFT)) & EVENT_INTPTPRI_IPRI0_MASK) -#define EVENT_INTPTPRI_IPRI8_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI8_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI8(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI8_SHIFT)) & EVENT_INTPTPRI_IPRI8_MASK) -#define EVENT_INTPTPRI_IPRI16_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI16_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI16(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI16_SHIFT)) & EVENT_INTPTPRI_IPRI16_MASK) -#define EVENT_INTPTPRI_IPRI24_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI24_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI24(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI24_SHIFT)) & EVENT_INTPTPRI_IPRI24_MASK) -#define EVENT_INTPTPRI_IPRI1_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI1_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI1(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI1_SHIFT)) & EVENT_INTPTPRI_IPRI1_MASK) -#define EVENT_INTPTPRI_IPRI9_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI9_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI9(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI9_SHIFT)) & EVENT_INTPTPRI_IPRI9_MASK) -#define EVENT_INTPTPRI_IPRI17_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI17_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI17(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI17_SHIFT)) & EVENT_INTPTPRI_IPRI17_MASK) -#define EVENT_INTPTPRI_IPRI25_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI25_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI25(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI25_SHIFT)) & EVENT_INTPTPRI_IPRI25_MASK) -#define EVENT_INTPTPRI_IPRI2_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI2_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI2(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI2_SHIFT)) & EVENT_INTPTPRI_IPRI2_MASK) -#define EVENT_INTPTPRI_IPRI10_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI10_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI10(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI10_SHIFT)) & EVENT_INTPTPRI_IPRI10_MASK) -#define EVENT_INTPTPRI_IPRI18_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI18_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI18(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI18_SHIFT)) & EVENT_INTPTPRI_IPRI18_MASK) -#define EVENT_INTPTPRI_IPRI26_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI26_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI26(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI26_SHIFT)) & EVENT_INTPTPRI_IPRI26_MASK) -#define EVENT_INTPTPRI_IPRI3_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI3_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI3(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI3_SHIFT)) & EVENT_INTPTPRI_IPRI3_MASK) -#define EVENT_INTPTPRI_IPRI11_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI11_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI11(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI11_SHIFT)) & EVENT_INTPTPRI_IPRI11_MASK) -#define EVENT_INTPTPRI_IPRI19_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI19_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI19(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI19_SHIFT)) & EVENT_INTPTPRI_IPRI19_MASK) -#define EVENT_INTPTPRI_IPRI27_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI27_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI27(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI27_SHIFT)) & EVENT_INTPTPRI_IPRI27_MASK) -#define EVENT_INTPTPRI_IPRI4_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI4_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI4(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI4_SHIFT)) & EVENT_INTPTPRI_IPRI4_MASK) -#define EVENT_INTPTPRI_IPRI12_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI12_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI12(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI12_SHIFT)) & EVENT_INTPTPRI_IPRI12_MASK) -#define EVENT_INTPTPRI_IPRI20_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI20_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI20(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI20_SHIFT)) & EVENT_INTPTPRI_IPRI20_MASK) -#define EVENT_INTPTPRI_IPRI28_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI28_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI28(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI28_SHIFT)) & EVENT_INTPTPRI_IPRI28_MASK) -#define EVENT_INTPTPRI_IPRI5_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI5_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI5(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI5_SHIFT)) & EVENT_INTPTPRI_IPRI5_MASK) -#define EVENT_INTPTPRI_IPRI13_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI13_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI13(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI13_SHIFT)) & EVENT_INTPTPRI_IPRI13_MASK) -#define EVENT_INTPTPRI_IPRI21_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI21_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI21(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI21_SHIFT)) & EVENT_INTPTPRI_IPRI21_MASK) -#define EVENT_INTPTPRI_IPRI29_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI29_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI29(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI29_SHIFT)) & EVENT_INTPTPRI_IPRI29_MASK) -#define EVENT_INTPTPRI_IPRI6_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI6_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI6(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI6_SHIFT)) & EVENT_INTPTPRI_IPRI6_MASK) -#define EVENT_INTPTPRI_IPRI14_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI14_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI14(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI14_SHIFT)) & EVENT_INTPTPRI_IPRI14_MASK) -#define EVENT_INTPTPRI_IPRI22_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI22_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI22(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI22_SHIFT)) & EVENT_INTPTPRI_IPRI22_MASK) -#define EVENT_INTPTPRI_IPRI30_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI30_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI30(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI30_SHIFT)) & EVENT_INTPTPRI_IPRI30_MASK) -#define EVENT_INTPTPRI_IPRI7_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI7_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI7(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI7_SHIFT)) & EVENT_INTPTPRI_IPRI7_MASK) -#define EVENT_INTPTPRI_IPRI15_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI15_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI15(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI15_SHIFT)) & EVENT_INTPTPRI_IPRI15_MASK) -#define EVENT_INTPTPRI_IPRI23_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI23_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI23(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI23_SHIFT)) & EVENT_INTPTPRI_IPRI23_MASK) -#define EVENT_INTPTPRI_IPRI31_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI31_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI31(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI31_SHIFT)) & EVENT_INTPTPRI_IPRI31_MASK) -/*! @} */ - -/* The count of EVENT_INTPTPRI */ -#define EVENT_INTPTPRI_COUNT (4U) - -/*! @name INTPRIBASE - Interrupt Priority Base */ -/*! @{ */ -#define EVENT_INTPRIBASE_IPBASE_MASK (0xFU) -#define EVENT_INTPRIBASE_IPBASE_SHIFT (0U) -#define EVENT_INTPRIBASE_IPBASE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPRIBASE_IPBASE_SHIFT)) & EVENT_INTPRIBASE_IPBASE_MASK) -/*! @} */ - -/*! @name INTPTENACTIVE - Interrupt Active Register */ -/*! @{ */ -#define EVENT_INTPTENACTIVE_IACTIVE_MASK (0xFFFFFFFFU) -#define EVENT_INTPTENACTIVE_IACTIVE_SHIFT (0U) -/*! IACTIVE - Interrupt n Enable - * 0b00000000000000000000000000000000..Interrupt n is not active. - * 0b00000000000000000000000000000001..Interrupt n is active.. - */ -#define EVENT_INTPTENACTIVE_IACTIVE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTENACTIVE_IACTIVE_SHIFT)) & EVENT_INTPTENACTIVE_IACTIVE_MASK) -/*! @} */ - -/*! @name INTACTPRI - Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register */ -/*! @{ */ -#define EVENT_INTACTPRI_IAPRI0_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI0_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI0(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI0_SHIFT)) & EVENT_INTACTPRI_IAPRI0_MASK) -#define EVENT_INTACTPRI_IAPRI8_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI8_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI8(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI8_SHIFT)) & EVENT_INTACTPRI_IAPRI8_MASK) -#define EVENT_INTACTPRI_IAPRI16_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI16_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI16(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI16_SHIFT)) & EVENT_INTACTPRI_IAPRI16_MASK) -#define EVENT_INTACTPRI_IAPRI24_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI24_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI24(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI24_SHIFT)) & EVENT_INTACTPRI_IAPRI24_MASK) -#define EVENT_INTACTPRI_IAPRI1_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI1_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI1(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI1_SHIFT)) & EVENT_INTACTPRI_IAPRI1_MASK) -#define EVENT_INTACTPRI_IAPRI9_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI9_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI9(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI9_SHIFT)) & EVENT_INTACTPRI_IAPRI9_MASK) -#define EVENT_INTACTPRI_IAPRI17_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI17_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI17(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI17_SHIFT)) & EVENT_INTACTPRI_IAPRI17_MASK) -#define EVENT_INTACTPRI_IAPRI25_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI25_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI25(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI25_SHIFT)) & EVENT_INTACTPRI_IAPRI25_MASK) -#define EVENT_INTACTPRI_IAPRI2_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI2_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI2(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI2_SHIFT)) & EVENT_INTACTPRI_IAPRI2_MASK) -#define EVENT_INTACTPRI_IAPRI10_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI10_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI10(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI10_SHIFT)) & EVENT_INTACTPRI_IAPRI10_MASK) -#define EVENT_INTACTPRI_IAPRI18_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI18_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI18(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI18_SHIFT)) & EVENT_INTACTPRI_IAPRI18_MASK) -#define EVENT_INTACTPRI_IAPRI26_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI26_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI26(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI26_SHIFT)) & EVENT_INTACTPRI_IAPRI26_MASK) -#define EVENT_INTACTPRI_IAPRI3_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI3_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI3(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI3_SHIFT)) & EVENT_INTACTPRI_IAPRI3_MASK) -#define EVENT_INTACTPRI_IAPRI11_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI11_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI11(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI11_SHIFT)) & EVENT_INTACTPRI_IAPRI11_MASK) -#define EVENT_INTACTPRI_IAPRI19_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI19_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI19(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI19_SHIFT)) & EVENT_INTACTPRI_IAPRI19_MASK) -#define EVENT_INTACTPRI_IAPRI27_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI27_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI27(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI27_SHIFT)) & EVENT_INTACTPRI_IAPRI27_MASK) -#define EVENT_INTACTPRI_IAPRI4_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI4_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI4(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI4_SHIFT)) & EVENT_INTACTPRI_IAPRI4_MASK) -#define EVENT_INTACTPRI_IAPRI12_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI12_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI12(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI12_SHIFT)) & EVENT_INTACTPRI_IAPRI12_MASK) -#define EVENT_INTACTPRI_IAPRI20_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI20_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI20(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI20_SHIFT)) & EVENT_INTACTPRI_IAPRI20_MASK) -#define EVENT_INTACTPRI_IAPRI28_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI28_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI28(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI28_SHIFT)) & EVENT_INTACTPRI_IAPRI28_MASK) -#define EVENT_INTACTPRI_IAPRI5_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI5_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI5(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI5_SHIFT)) & EVENT_INTACTPRI_IAPRI5_MASK) -#define EVENT_INTACTPRI_IAPRI13_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI13_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI13(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI13_SHIFT)) & EVENT_INTACTPRI_IAPRI13_MASK) -#define EVENT_INTACTPRI_IAPRI21_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI21_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI21(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI21_SHIFT)) & EVENT_INTACTPRI_IAPRI21_MASK) -#define EVENT_INTACTPRI_IAPRI29_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI29_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI29(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI29_SHIFT)) & EVENT_INTACTPRI_IAPRI29_MASK) -#define EVENT_INTACTPRI_IAPRI6_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI6_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI6(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI6_SHIFT)) & EVENT_INTACTPRI_IAPRI6_MASK) -#define EVENT_INTACTPRI_IAPRI14_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI14_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI14(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI14_SHIFT)) & EVENT_INTACTPRI_IAPRI14_MASK) -#define EVENT_INTACTPRI_IAPRI22_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI22_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI22(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI22_SHIFT)) & EVENT_INTACTPRI_IAPRI22_MASK) -#define EVENT_INTACTPRI_IAPRI30_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI30_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI30(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI30_SHIFT)) & EVENT_INTACTPRI_IAPRI30_MASK) -#define EVENT_INTACTPRI_IAPRI7_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI7_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI7(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI7_SHIFT)) & EVENT_INTACTPRI_IAPRI7_MASK) -#define EVENT_INTACTPRI_IAPRI15_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI15_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI15(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI15_SHIFT)) & EVENT_INTACTPRI_IAPRI15_MASK) -#define EVENT_INTACTPRI_IAPRI23_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI23_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI23(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI23_SHIFT)) & EVENT_INTACTPRI_IAPRI23_MASK) -#define EVENT_INTACTPRI_IAPRI31_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI31_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI31(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI31_SHIFT)) & EVENT_INTACTPRI_IAPRI31_MASK) -/*! @} */ - -/* The count of EVENT_INTACTPRI */ -#define EVENT_INTACTPRI_COUNT (4U) - -/*! @name EVENTEN - Event Enable Register */ -/*! @{ */ -#define EVENT_EVENTEN_EEN_MASK (0xFFFFFFFFU) -#define EVENT_EVENTEN_EEN_SHIFT (0U) -/*! EEN - Event n Enable - * 0b00000000000000000000000000000000..Event n is disabled. - * 0b00000000000000000000000000000001..Event n is enabled. - */ -#define EVENT_EVENTEN_EEN(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTEN_EEN_SHIFT)) & EVENT_EVENTEN_EEN_MASK) -/*! @} */ - -/*! @name EVENTPEND - Event Pengding Register */ -/*! @{ */ -#define EVENT_EVENTPEND_EPEND_MASK (0xFFFFFFFFU) -#define EVENT_EVENTPEND_EPEND_SHIFT (0U) -/*! EPEND - Event n Pending - * 0b00000000000000000000000000000000..Event n is not pending. - * 0b00000000000000000000000000000001..Event n is pending. - */ -#define EVENT_EVENTPEND_EPEND(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTPEND_EPEND_SHIFT)) & EVENT_EVENTPEND_EPEND_MASK) -/*! @} */ - -/*! @name EVTPENDSET - Set Event Pengding Register */ -/*! @{ */ -#define EVENT_EVTPENDSET_EPENDSET_MASK (0xFFFFFFFFU) -#define EVENT_EVTPENDSET_EPENDSET_SHIFT (0U) -/*! EPENDSET - Set Event n Pending - * 0b00000000000000000000000000000000..Not set event n in pending status - * 0b00000000000000000000000000000001..Set event n in pending status. - */ -#define EVENT_EVTPENDSET_EPENDSET(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDSET_EPENDSET_SHIFT)) & EVENT_EVTPENDSET_EPENDSET_MASK) -/*! @} */ - -/*! @name EVTPENDCLEAR - Clear Event Pengding Register */ -/*! @{ */ -#define EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK (0xFFFFFFFFU) -#define EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT (0U) -/*! EPENDCLEAR - Clear Event n out of Pending - * 0b00000000000000000000000000000000..Not clear event n out of pending status - * 0b00000000000000000000000000000001..Clear event n out of pending status. - */ -#define EVENT_EVTPENDCLEAR_EPENDCLEAR(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT)) & EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK) -/*! @} */ - -/*! @name SLPCTRL - Sleep Control Register */ -/*! @{ */ -#define EVENT_SLPCTRL_SLPCTRL_MASK (0x3U) -#define EVENT_SLPCTRL_SLPCTRL_SHIFT (0U) -/*! SLPCTRL - Sleep Mode Control - * 0b01..Sleep enable - * 0b10..Deep sleep enable - */ -#define EVENT_SLPCTRL_SLPCTRL(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SLPCTRL_SHIFT)) & EVENT_SLPCTRL_SLPCTRL_MASK) -#define EVENT_SLPCTRL_SYSRSTREQST_MASK (0x80000000U) -#define EVENT_SLPCTRL_SYSRSTREQST_SHIFT (31U) -/*! SYSRSTREQST - System Reset Request - * 0b0..Do not send system reset request. - * 0b1..Send system reset request - */ -#define EVENT_SLPCTRL_SYSRSTREQST(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SYSRSTREQST_SHIFT)) & EVENT_SLPCTRL_SYSRSTREQST_MASK) -/*! @} */ - -/*! @name SLPSTATUS - Sleep Status Register */ -/*! @{ */ -#define EVENT_SLPSTATUS_SLPSTAT_MASK (0x3U) -#define EVENT_SLPSTATUS_SLPSTAT_SHIFT (0U) -/*! SLPSTAT - Sleep Status - * 0b01..In sleep mode - * 0b10..In deep sleep mode - */ -#define EVENT_SLPSTATUS_SLPSTAT(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPSTATUS_SLPSTAT_SHIFT)) & EVENT_SLPSTATUS_SLPSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EVENT_Register_Masks */ - - -/* EVENT - Peripheral instance base addresses */ -/** Peripheral EVENT0 base address */ -#define EVENT0_BASE (0xE0041000u) -/** Peripheral EVENT0 base pointer */ -#define EVENT0 ((EVENT_Type *)EVENT0_BASE) -/** Array initializer of EVENT peripheral base addresses */ -#define EVENT_BASE_ADDRS { EVENT0_BASE } -/** Array initializer of EVENT peripheral base pointers */ -#define EVENT_BASE_PTRS { EVENT0 } - -/*! - * @} - */ /* end of group EVENT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer - * @{ - */ - -/** EWM - Register Layout Typedef */ -typedef struct { - __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ - __O uint8_t SERV; /**< Service Register, offset: 0x1 */ - __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ - __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ - uint8_t RESERVED_0[1]; - __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ -} EWM_Type; - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define EWM_CTRL_EWMEN_MASK (0x1U) -#define EWM_CTRL_EWMEN_SHIFT (0U) -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) -#define EWM_CTRL_ASSIN_MASK (0x2U) -#define EWM_CTRL_ASSIN_SHIFT (1U) -#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) -#define EWM_CTRL_INEN_MASK (0x4U) -#define EWM_CTRL_INEN_SHIFT (2U) -#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) -#define EWM_CTRL_INTEN_MASK (0x8U) -#define EWM_CTRL_INTEN_SHIFT (3U) -#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) -/*! @} */ - -/*! @name SERV - Service Register */ -/*! @{ */ -#define EWM_SERV_SERVICE_MASK (0xFFU) -#define EWM_SERV_SERVICE_SHIFT (0U) -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) -/*! @} */ - -/*! @name CMPL - Compare Low Register */ -/*! @{ */ -#define EWM_CMPL_COMPAREL_MASK (0xFFU) -#define EWM_CMPL_COMPAREL_SHIFT (0U) -#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) -/*! @} */ - -/*! @name CMPH - Compare High Register */ -/*! @{ */ -#define EWM_CMPH_COMPAREH_MASK (0xFFU) -#define EWM_CMPH_COMPAREH_SHIFT (0U) -#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) -/*! @} */ - -/*! @name CLKPRESCALER - Clock Prescaler Register */ -/*! @{ */ -#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) -#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) -#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EWM_Register_Masks */ - - -/* EWM - Peripheral instance base addresses */ -/** Peripheral EWM base address */ -#define EWM_BASE (0x40022000u) -/** Peripheral EWM base pointer */ -#define EWM ((EWM_Type *)EWM_BASE) -/** Array initializer of EWM peripheral base addresses */ -#define EWM_BASE_ADDRS { EWM_BASE } -/** Array initializer of EWM peripheral base pointers */ -#define EWM_BASE_PTRS { EWM } -/** Interrupt vectors for the EWM peripheral type */ -#define EWM_IRQS { EWM_IRQn } - -/*! - * @} - */ /* end of group EWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer - * @{ - */ - -/** FB - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0xC */ - __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ - __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ - __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ - } CS[6]; - uint8_t RESERVED_0[24]; - __IO uint32_t CSPMCR; /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */ -} FB_Type; - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/*! @name CSAR - Chip Select Address Register */ -/*! @{ */ -#define FB_CSAR_BA_MASK (0xFFFF0000U) -#define FB_CSAR_BA_SHIFT (16U) -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) -/*! @} */ - -/* The count of FB_CSAR */ -#define FB_CSAR_COUNT (6U) - -/*! @name CSMR - Chip Select Mask Register */ -/*! @{ */ -#define FB_CSMR_V_MASK (0x1U) -#define FB_CSMR_V_SHIFT (0U) -/*! V - Valid - * 0b0..Chip-select is invalid. - * 0b1..Chip-select is valid. - */ -#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) -#define FB_CSMR_WP_MASK (0x100U) -#define FB_CSMR_WP_SHIFT (8U) -/*! WP - Write Protect - * 0b0..Write accesses are allowed. - * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. - */ -#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) -#define FB_CSMR_BAM_MASK (0xFFFF0000U) -#define FB_CSMR_BAM_SHIFT (16U) -/*! BAM - Base Address Mask - * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. - * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode. - */ -#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) -/*! @} */ - -/* The count of FB_CSMR */ -#define FB_CSMR_COUNT (6U) - -/*! @name CSCR - Chip Select Control Register */ -/*! @{ */ -#define FB_CSCR_BSTW_MASK (0x8U) -#define FB_CSCR_BSTW_SHIFT (3U) -/*! BSTW - Burst-Write Enable - * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. - * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. - */ -#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) -#define FB_CSCR_BSTR_MASK (0x10U) -#define FB_CSCR_BSTR_SHIFT (4U) -/*! BSTR - Burst-Read Enable - * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. - * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. - */ -#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) -#define FB_CSCR_BEM_MASK (0x20U) -#define FB_CSCR_BEM_SHIFT (5U) -/*! BEM - Byte-Enable Mode - * 0b0..FB_BE_B is asserted for data write only. - * 0b1..FB_BE_B is asserted for data read and write accesses. - */ -#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) -#define FB_CSCR_PS_MASK (0xC0U) -#define FB_CSCR_PS_SHIFT (6U) -/*! PS - Port Size - * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. - * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. - * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. - */ -#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) -#define FB_CSCR_AA_MASK (0x100U) -#define FB_CSCR_AA_SHIFT (8U) -/*! AA - Auto-Acknowledge Enable - * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. - * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS. - */ -#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) -#define FB_CSCR_BLS_MASK (0x200U) -#define FB_CSCR_BLS_SHIFT (9U) -/*! BLS - Byte-Lane Shift - * 0b0..Not shifted. Data is left-aligned on FB_AD. - * 0b1..Shifted. Data is right-aligned on FB_AD. - */ -#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) -#define FB_CSCR_WS_MASK (0xFC00U) -#define FB_CSCR_WS_SHIFT (10U) -#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) -#define FB_CSCR_WRAH_MASK (0x30000U) -#define FB_CSCR_WRAH_SHIFT (16U) -/*! WRAH - Write Address Hold or Deselect - * 0b00..1 cycle (default for all but FB_CS0_B) - * 0b01..2 cycles - * 0b10..3 cycles - * 0b11..4 cycles (default for FB_CS0_B) - */ -#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) -#define FB_CSCR_RDAH_MASK (0xC0000U) -#define FB_CSCR_RDAH_SHIFT (18U) -/*! RDAH - Read Address Hold or Deselect - * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. - * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. - * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. - * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. - */ -#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) -#define FB_CSCR_ASET_MASK (0x300000U) -#define FB_CSCR_ASET_SHIFT (20U) -/*! ASET - Address Setup - * 0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B). - * 0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted. - * 0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted. - * 0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ). - */ -#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) -#define FB_CSCR_EXTS_MASK (0x400000U) -#define FB_CSCR_EXTS_SHIFT (22U) -/*! EXTS - EXTS - * 0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle. - * 0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts. - */ -#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) -#define FB_CSCR_SWSEN_MASK (0x800000U) -#define FB_CSCR_SWSEN_SHIFT (23U) -/*! SWSEN - Secondary Wait State Enable - * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. - * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. - */ -#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) -#define FB_CSCR_SWS_MASK (0xFC000000U) -#define FB_CSCR_SWS_SHIFT (26U) -#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) -/*! @} */ - -/* The count of FB_CSCR */ -#define FB_CSCR_COUNT (6U) - -/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */ -/*! @{ */ -#define FB_CSPMCR_GROUP5_MASK (0xF000U) -#define FB_CSPMCR_GROUP5_SHIFT (12U) -/*! GROUP5 - FlexBus Signal Group 5 Multiplex control - * 0b0000..FB_TA_B - * 0b0001..FB_CS3_B. You must also write 1b to CSCR[AA]. - * 0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA]. - */ -#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) -#define FB_CSPMCR_GROUP4_MASK (0xF0000U) -#define FB_CSPMCR_GROUP4_SHIFT (16U) -/*! GROUP4 - FlexBus Signal Group 4 Multiplex control - * 0b0000..FB_TBST_B - * 0b0001..FB_CS2_B - * 0b0010..FB_BE_15_8_B - */ -#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) -#define FB_CSPMCR_GROUP3_MASK (0xF00000U) -#define FB_CSPMCR_GROUP3_SHIFT (20U) -/*! GROUP3 - FlexBus Signal Group 3 Multiplex control - * 0b0000..FB_CS5_B - * 0b0001..FB_TSIZ1 - * 0b0010..FB_BE_23_16_B - */ -#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) -#define FB_CSPMCR_GROUP2_MASK (0xF000000U) -#define FB_CSPMCR_GROUP2_SHIFT (24U) -/*! GROUP2 - FlexBus Signal Group 2 Multiplex control - * 0b0000..FB_CS4_B - * 0b0001..FB_TSIZ0 - * 0b0010..FB_BE_31_24_B - */ -#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) -#define FB_CSPMCR_GROUP1_MASK (0xF0000000U) -#define FB_CSPMCR_GROUP1_SHIFT (28U) -/*! GROUP1 - FlexBus Signal Group 1 Multiplex control - * 0b0000..FB_ALE - * 0b0001..FB_CS1_B - * 0b0010..FB_TS_B - */ -#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FB_Register_Masks */ - - -/* FB - Peripheral instance base addresses */ -/** Peripheral FB base address */ -#define FB_BASE (0x4000C000u) -/** Peripheral FB base pointer */ -#define FB ((FB_Type *)FB_BASE) -/** Array initializer of FB peripheral base addresses */ -#define FB_BASE_ADDRS { FB_BASE } -/** Array initializer of FB peripheral base pointers */ -#define FB_BASE_PTRS { FB } - -/*! - * @} - */ /* end of group FB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer - * @{ - */ - -/** FLEXIO - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ - __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ - __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ - __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ - __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ - __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ - __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ - uint8_t RESERVED_2[12]; - __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ - uint8_t RESERVED_3[60]; - __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_4[96]; - __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_5[224]; - __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[96]; - __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ - uint8_t RESERVED_7[96]; - __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_8[96]; - __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ - uint8_t RESERVED_9[96]; - __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_10[96]; - __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ - uint8_t RESERVED_11[96]; - __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_12[352]; - __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_13[96]; - __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ - uint8_t RESERVED_14[96]; - __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ -} FLEXIO_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) -#define FLEXIO_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - * 0b0000000000000001..Supports state, logic and parallel modes. - */ -#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) -#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) -#define FLEXIO_VERID_MINOR_SHIFT (16U) -#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) -#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) -#define FLEXIO_VERID_MAJOR_SHIFT (24U) -#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) -#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) -#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) -#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) -#define FLEXIO_PARAM_TIMER_SHIFT (8U) -#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) -#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) -#define FLEXIO_PARAM_PIN_SHIFT (16U) -#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) -#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) -#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) -#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) -/*! @} */ - -/*! @name CTRL - FlexIO Control Register */ -/*! @{ */ -#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) -#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) -/*! FLEXEN - FlexIO Enable - * 0b0..FlexIO module is disabled. - * 0b1..FlexIO module is enabled. - */ -#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) -#define FLEXIO_CTRL_SWRST_MASK (0x2U) -#define FLEXIO_CTRL_SWRST_SHIFT (1U) -/*! SWRST - Software Reset - * 0b0..Software reset is disabled - * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. - */ -#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) -#define FLEXIO_CTRL_FASTACC_MASK (0x4U) -#define FLEXIO_CTRL_FASTACC_SHIFT (2U) -/*! FASTACC - Fast Access - * 0b0..Configures for normal register accesses to FlexIO - * 0b1..Configures for fast register accesses to FlexIO - */ -#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) -#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) -#define FLEXIO_CTRL_DBGE_SHIFT (30U) -/*! DBGE - Debug Enable - * 0b0..FlexIO is disabled in debug modes. - * 0b1..FlexIO is enabled in debug modes - */ -#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) -#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) -#define FLEXIO_CTRL_DOZEN_SHIFT (31U) -/*! DOZEN - Doze Enable - * 0b0..FlexIO enabled in Doze modes. - * 0b1..FlexIO disabled in Doze modes. - */ -#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) -/*! @} */ - -/*! @name PIN - Pin State Register */ -/*! @{ */ -#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) -#define FLEXIO_PIN_PDI_SHIFT (0U) -#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) -/*! @} */ - -/*! @name SHIFTSTAT - Shifter Status Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) -#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) -#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) -/*! @} */ - -/*! @name SHIFTERR - Shifter Error Register */ -/*! @{ */ -#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) -#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) -#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) -/*! @} */ - -/*! @name TIMSTAT - Timer Status Register */ -/*! @{ */ -#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) -#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) -#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) -/*! @} */ - -/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) -#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) -#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) -/*! @} */ - -/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) -#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) -#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) -/*! @} */ - -/*! @name TIMIEN - Timer Interrupt Enable Register */ -/*! @{ */ -#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) -#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) -#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) -/*! @} */ - -/*! @name SHIFTSDEN - Shifter Status DMA Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) -#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) -#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) -/*! @} */ - -/*! @name SHIFTSTATE - Shifter State Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) -#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) -#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) -/*! @} */ - -/*! @name SHIFTCTL - Shifter Control N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) -#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) -/*! SMOD - Shifter Mode - * 0b000..Disabled. - * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. - * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. - * 0b011..Reserved. - * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. - * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. - * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. - * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. - */ -#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) -#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) -#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) -/*! PINPOL - Shifter Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low - */ -#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) -#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) -#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) -#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) -/*! PINCFG - Shifter Pin Configuration - * 0b00..Shifter pin output disabled - * 0b01..Shifter pin open drain or bidirectional output enable - * 0b10..Shifter pin bidirectional output data - * 0b11..Shifter pin output - */ -#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) -#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) -#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) -/*! TIMPOL - Timer Polarity - * 0b0..Shift on posedge of Shift clock - * 0b1..Shift on negedge of Shift clock - */ -#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) -#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) -#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) -#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCTL */ -#define FLEXIO_SHIFTCTL_COUNT (8U) - -/*! @name SHIFTCFG - Shifter Configuration N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) -#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) -/*! SSTART - Shifter Start bit - * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable - * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift - * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 - * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 - */ -#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) -#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) -#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) -/*! SSTOP - Shifter Stop bit - * 0b00..Stop bit disabled for transmitter/receiver/match store - * 0b01..Reserved for transmitter/receiver/match store - * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 - * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 - */ -#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) -#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) -#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) -/*! INSRC - Input Source - * 0b0..Pin - * 0b1..Shifter N+1 Output - */ -#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) -#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) -#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) -#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCFG */ -#define FLEXIO_SHIFTCFG_COUNT (8U) - -/*! @name SHIFTBUF - Shifter Buffer N Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) -#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUF */ -#define FLEXIO_SHIFTBUF_COUNT (8U) - -/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBIS */ -#define FLEXIO_SHIFTBUFBIS_COUNT (8U) - -/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBYS */ -#define FLEXIO_SHIFTBUFBYS_COUNT (8U) - -/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBBS */ -#define FLEXIO_SHIFTBUFBBS_COUNT (8U) - -/*! @name TIMCTL - Timer Control N Register */ -/*! @{ */ -#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) -#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) -/*! TIMOD - Timer Mode - * 0b00..Timer Disabled. - * 0b01..Dual 8-bit counters baud mode. - * 0b10..Dual 8-bit counters PWM high mode. - * 0b11..Single 16-bit counter mode. - */ -#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) -#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) -#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) -/*! PINPOL - Timer Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low - */ -#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) -#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) -#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) -#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) -/*! PINCFG - Timer Pin Configuration - * 0b00..Timer pin output disabled - * 0b01..Timer pin open drain or bidirectional output enable - * 0b10..Timer pin bidirectional output data - * 0b11..Timer pin output - */ -#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) -#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) -#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) -/*! TRGSRC - Trigger Source - * 0b0..External trigger selected - * 0b1..Internal trigger selected - */ -#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) -#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) -#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) -/*! TRGPOL - Trigger Polarity - * 0b0..Trigger active high - * 0b1..Trigger active low - */ -#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) -#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) -#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) -#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCTL */ -#define FLEXIO_TIMCTL_COUNT (8U) - -/*! @name TIMCFG - Timer Configuration N Register */ -/*! @{ */ -#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) -#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) -/*! TSTART - Timer Start Bit - * 0b0..Start bit disabled - * 0b1..Start bit enabled - */ -#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) -#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) -#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) -/*! TSTOP - Timer Stop Bit - * 0b00..Stop bit disabled - * 0b01..Stop bit is enabled on timer compare - * 0b10..Stop bit is enabled on timer disable - * 0b11..Stop bit is enabled on timer compare and timer disable - */ -#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) -#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) -#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) -/*! TIMENA - Timer Enable - * 0b000..Timer always enabled - * 0b001..Timer enabled on Timer N-1 enable - * 0b010..Timer enabled on Trigger high - * 0b011..Timer enabled on Trigger high and Pin high - * 0b100..Timer enabled on Pin rising edge - * 0b101..Timer enabled on Pin rising edge and Trigger high - * 0b110..Timer enabled on Trigger rising edge - * 0b111..Timer enabled on Trigger rising or falling edge - */ -#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) -#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) -#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) -/*! TIMDIS - Timer Disable - * 0b000..Timer never disabled - * 0b001..Timer disabled on Timer N-1 disable - * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) - * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low - * 0b100..Timer disabled on Pin rising or falling edge - * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high - * 0b110..Timer disabled on Trigger falling edge - * 0b111..Reserved - */ -#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) -#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) -#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) -/*! TIMRST - Timer Reset - * 0b000..Timer never reset - * 0b001..Reserved - * 0b010..Timer reset on Timer Pin equal to Timer Output - * 0b011..Timer reset on Timer Trigger equal to Timer Output - * 0b100..Timer reset on Timer Pin rising edge - * 0b101..Reserved - * 0b110..Timer reset on Trigger rising edge - * 0b111..Timer reset on Trigger rising or falling edge - */ -#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) -#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) -#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) -/*! TIMDEC - Timer Decrement - * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. - * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. - * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. - * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. - */ -#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) -#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) -#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) -/*! TIMOUT - Timer Output - * 0b00..Timer output is logic one when enabled and is not affected by timer reset - * 0b01..Timer output is logic zero when enabled and is not affected by timer reset - * 0b10..Timer output is logic one when enabled and on timer reset - * 0b11..Timer output is logic zero when enabled and on timer reset - */ -#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCFG */ -#define FLEXIO_TIMCFG_COUNT (8U) - -/*! @name TIMCMP - Timer Compare N Register */ -/*! @{ */ -#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) -#define FLEXIO_TIMCMP_CMP_SHIFT (0U) -#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCMP */ -#define FLEXIO_TIMCMP_COUNT (8U) - -/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNBS */ -#define FLEXIO_SHIFTBUFNBS_COUNT (8U) - -/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFHWS */ -#define FLEXIO_SHIFTBUFHWS_COUNT (8U) - -/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNIS */ -#define FLEXIO_SHIFTBUFNIS_COUNT (8U) - - -/*! - * @} - */ /* end of group FLEXIO_Register_Masks */ - - -/* FLEXIO - Peripheral instance base addresses */ -/** Peripheral FLEXIO0 base address */ -#define FLEXIO0_BASE (0x40039000u) -/** Peripheral FLEXIO0 base pointer */ -#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) -/** Array initializer of FLEXIO peripheral base addresses */ -#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } -/** Array initializer of FLEXIO peripheral base pointers */ -#define FLEXIO_BASE_PTRS { FLEXIO0 } -/** Interrupt vectors for the FLEXIO peripheral type */ -#define FLEXIO_IRQS { FLEXIO0_IRQn } - -/*! - * @} - */ /* end of group FLEXIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTFE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer - * @{ - */ - -/** FTFE - Register Layout Typedef */ -typedef struct { - __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ - __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ - __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ - uint8_t RESERVED_0[1]; - __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ - __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ - __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ - __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ - __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ - __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ - __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ - __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ - __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ - __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ - __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ - __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ - __I uint8_t FOPT3; /**< Flash Option Registers, offset: 0x10 */ - __I uint8_t FOPT2; /**< Flash Option Registers, offset: 0x11 */ - __I uint8_t FOPT1; /**< Flash Option Registers, offset: 0x12 */ - __I uint8_t FOPT0; /**< Flash Option Registers, offset: 0x13 */ - uint8_t RESERVED_1[4]; - __IO uint8_t FPROTH3; /**< Primary Program Flash Protection Registers, offset: 0x18 */ - __IO uint8_t FPROTH2; /**< Primary Program Flash Protection Registers, offset: 0x19 */ - __IO uint8_t FPROTH1; /**< Primary Program Flash Protection Registers, offset: 0x1A */ - __IO uint8_t FPROTH0; /**< Primary Program Flash Protection Registers, offset: 0x1B */ - __IO uint8_t FPROTL3; /**< Primary Program Flash Protection Registers, offset: 0x1C */ - __IO uint8_t FPROTL2; /**< Primary Program Flash Protection Registers, offset: 0x1D */ - __IO uint8_t FPROTL1; /**< Primary Program Flash Protection Registers, offset: 0x1E */ - __IO uint8_t FPROTL0; /**< Primary Program Flash Protection Registers, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint8_t FPROTSL; /**< Secondary Program Flash Protection Registers, offset: 0x24 */ - __IO uint8_t FPROTSH; /**< Secondary Program Flash Protection Registers, offset: 0x25 */ - uint8_t RESERVED_3[6]; - __I uint8_t FACSS; /**< Primary Flash Access Segment Size Register, offset: 0x2C */ - __I uint8_t FACSN; /**< Primary Flash Access Segment Number Register, offset: 0x2D */ - __I uint8_t FACSSS; /**< Secondary Flash Access Segment Size Register, offset: 0x2E */ - __I uint8_t FACSNS; /**< Secondary Flash Access Segment Number Register, offset: 0x2F */ - __I uint8_t XACCH3; /**< Primary Execute-only Access Registers, offset: 0x30 */ - __I uint8_t XACCH2; /**< Primary Execute-only Access Registers, offset: 0x31 */ - __I uint8_t XACCH1; /**< Primary Execute-only Access Registers, offset: 0x32 */ - __I uint8_t XACCH0; /**< Primary Execute-only Access Registers, offset: 0x33 */ - __I uint8_t XACCL3; /**< Primary Execute-only Access Registers, offset: 0x34 */ - __I uint8_t XACCL2; /**< Primary Execute-only Access Registers, offset: 0x35 */ - __I uint8_t XACCL1; /**< Primary Execute-only Access Registers, offset: 0x36 */ - __I uint8_t XACCL0; /**< Primary Execute-only Access Registers, offset: 0x37 */ - __I uint8_t SACCH3; /**< Primary Supervisor-only Access Registers, offset: 0x38 */ - __I uint8_t SACCH2; /**< Primary Supervisor-only Access Registers, offset: 0x39 */ - __I uint8_t SACCH1; /**< Primary Supervisor-only Access Registers, offset: 0x3A */ - __I uint8_t SACCH0; /**< Primary Supervisor-only Access Registers, offset: 0x3B */ - __I uint8_t SACCL3; /**< Primary Supervisor-only Access Registers, offset: 0x3C */ - __I uint8_t SACCL2; /**< Primary Supervisor-only Access Registers, offset: 0x3D */ - __I uint8_t SACCL1; /**< Primary Supervisor-only Access Registers, offset: 0x3E */ - __I uint8_t SACCL0; /**< Primary Supervisor-only Access Registers, offset: 0x3F */ - uint8_t RESERVED_4[4]; - __I uint8_t XACCSL; /**< Secondary Execute-only Access Registers, offset: 0x44 */ - __I uint8_t XACCSH; /**< Secondary Execute-only Access Registers, offset: 0x45 */ - uint8_t RESERVED_5[6]; - __I uint8_t SACCSL; /**< Secondary Supervisor-only Access Registers, offset: 0x4C */ - __I uint8_t SACCSH; /**< Secondary Supervisor-only Access Registers, offset: 0x4D */ - uint8_t RESERVED_6[4]; - __I uint8_t FSTDBYCTL; /**< Flash Standby Control Register, offset: 0x52 */ - __IO uint8_t FSTDBY; /**< Flash Standby Register, offset: 0x53 */ -} FTFE_Type; - -/* ---------------------------------------------------------------------------- - -- FTFE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Register_Masks FTFE Register Masks - * @{ - */ - -/*! @name FSTAT - Flash Status Register */ -/*! @{ */ -#define FTFE_FSTAT_MGSTAT0_MASK (0x1U) -#define FTFE_FSTAT_MGSTAT0_SHIFT (0U) -#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) -#define FTFE_FSTAT_FPVIOL_MASK (0x10U) -#define FTFE_FSTAT_FPVIOL_SHIFT (4U) -/*! FPVIOL - Flash Protection Violation Flag - * 0b0..No protection violation detected - * 0b1..Protection violation detected - */ -#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) -#define FTFE_FSTAT_ACCERR_MASK (0x20U) -#define FTFE_FSTAT_ACCERR_SHIFT (5U) -/*! ACCERR - Flash Access Error Flag - * 0b0..No access error detected - * 0b1..Access error detected - */ -#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) -#define FTFE_FSTAT_RDCOLERR_MASK (0x40U) -#define FTFE_FSTAT_RDCOLERR_SHIFT (6U) -/*! RDCOLERR - Flash Read Collision Error Flag - * 0b0..No collision error detected - * 0b1..Collision error detected - */ -#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) -#define FTFE_FSTAT_CCIF_MASK (0x80U) -#define FTFE_FSTAT_CCIF_SHIFT (7U) -/*! CCIF - Command Complete Interrupt Flag - * 0b0..Flash command in progress - * 0b1..Flash command has completed - */ -#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) -/*! @} */ - -/*! @name FCNFG - Flash Configuration Register */ -/*! @{ */ -#define FTFE_FCNFG_RAMRDY_MASK (0x2U) -#define FTFE_FCNFG_RAMRDY_SHIFT (1U) -/*! RAMRDY - RAM Ready - * 0b0..Programming acceleration RAM is not available - * 0b1..Programming acceleration RAM is available - */ -#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) -#define FTFE_FCNFG_CRCRDY_MASK (0x4U) -#define FTFE_FCNFG_CRCRDY_SHIFT (2U) -/*! CRCRDY - CRC Ready - * 0b0..Programming acceleration RAM is not available for CRC operations - * 0b1..Programming acceleration RAM is available for CRC operations - */ -#define FTFE_FCNFG_CRCRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CRCRDY_SHIFT)) & FTFE_FCNFG_CRCRDY_MASK) -#define FTFE_FCNFG_SWAP_MASK (0x8U) -#define FTFE_FCNFG_SWAP_SHIFT (3U) -/*! SWAP - Swap - * 0b0..Program flash 0 block is located at relative address 0x0000 - * 0b1..Program flash 1 block is located at relative address 0x0000 - */ -#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) -#define FTFE_FCNFG_ERSSUSP_MASK (0x10U) -#define FTFE_FCNFG_ERSSUSP_SHIFT (4U) -/*! ERSSUSP - Erase Suspend - * 0b0..No suspend requested - * 0b1..Suspend the current Erase Flash Sector command execution - */ -#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) -#define FTFE_FCNFG_ERSAREQ_MASK (0x20U) -#define FTFE_FCNFG_ERSAREQ_SHIFT (5U) -/*! ERSAREQ - Erase All Request - * 0b0..No request or request complete - * 0b1..Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the FSEC[SEC] field to the unsecure state. - */ -#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) -#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) -#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) -/*! RDCOLLIE - Read Collision Error Interrupt Enable - * 0b0..Read collision error interrupt disabled - * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision error is detected (see the description of FSTAT[RDCOLERR]). - */ -#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) -#define FTFE_FCNFG_CCIE_MASK (0x80U) -#define FTFE_FCNFG_CCIE_SHIFT (7U) -/*! CCIE - Command Complete Interrupt Enable - * 0b0..Command complete interrupt disabled - * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. - */ -#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) -/*! @} */ - -/*! @name FSEC - Flash Security Register */ -/*! @{ */ -#define FTFE_FSEC_SEC_MASK (0x3U) -#define FTFE_FSEC_SEC_SHIFT (0U) -/*! SEC - Flash Security - * 0b00..MCU security status is secure - * 0b01..MCU security status is secure - * 0b10..MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.) - * 0b11..MCU security status is secure - */ -#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) -#define FTFE_FSEC_FSLACC_MASK (0xCU) -#define FTFE_FSEC_FSLACC_SHIFT (2U) -/*! FSLACC - Factory Security Level Access Code - * 0b00..Factory access granted - * 0b01..Factory access denied - * 0b10..Factory access denied - * 0b11..Factory access granted - */ -#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) -#define FTFE_FSEC_MEEN_MASK (0x30U) -#define FTFE_FSEC_MEEN_SHIFT (4U) -/*! MEEN - Mass Erase Enable Bits - * 0b00..Mass erase is enabled - * 0b01..Mass erase is enabled - * 0b10..Mass erase is disabled - * 0b11..Mass erase is enabled - */ -#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) -#define FTFE_FSEC_KEYEN_MASK (0xC0U) -#define FTFE_FSEC_KEYEN_SHIFT (6U) -/*! KEYEN - Backdoor Key Security Enable - * 0b00..Backdoor key access disabled - * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) - * 0b10..Backdoor key access enabled - * 0b11..Backdoor key access disabled - */ -#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) -/*! @} */ - -/*! @name FCCOB3 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB3_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB3_CCOBn_SHIFT (0U) -#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB2 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB2_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB2_CCOBn_SHIFT (0U) -#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB1 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB1_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB1_CCOBn_SHIFT (0U) -#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB0 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB0_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB0_CCOBn_SHIFT (0U) -#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB7 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB7_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB7_CCOBn_SHIFT (0U) -#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB6 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB6_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB6_CCOBn_SHIFT (0U) -#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB5 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB5_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB5_CCOBn_SHIFT (0U) -#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB4 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB4_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB4_CCOBn_SHIFT (0U) -#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOBB - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOBB_CCOBn_MASK (0xFFU) -#define FTFE_FCCOBB_CCOBn_SHIFT (0U) -#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOBA - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOBA_CCOBn_MASK (0xFFU) -#define FTFE_FCCOBA_CCOBn_SHIFT (0U) -#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB9 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB9_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB9_CCOBn_SHIFT (0U) -#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB8 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB8_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB8_CCOBn_SHIFT (0U) -#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) -/*! @} */ - -/*! @name FOPT3 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT3_OPT_MASK (0xFFU) -#define FTFE_FOPT3_OPT_SHIFT (0U) -#define FTFE_FOPT3_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT3_OPT_SHIFT)) & FTFE_FOPT3_OPT_MASK) -/*! @} */ - -/*! @name FOPT2 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT2_OPT_MASK (0xFFU) -#define FTFE_FOPT2_OPT_SHIFT (0U) -#define FTFE_FOPT2_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT2_OPT_SHIFT)) & FTFE_FOPT2_OPT_MASK) -/*! @} */ - -/*! @name FOPT1 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT1_OPT_MASK (0xFFU) -#define FTFE_FOPT1_OPT_SHIFT (0U) -#define FTFE_FOPT1_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT1_OPT_SHIFT)) & FTFE_FOPT1_OPT_MASK) -/*! @} */ - -/*! @name FOPT0 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT0_OPT_MASK (0xFFU) -#define FTFE_FOPT0_OPT_SHIFT (0U) -#define FTFE_FOPT0_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT0_OPT_SHIFT)) & FTFE_FOPT0_OPT_MASK) -/*! @} */ - -/*! @name FPROTH3 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH3_PROT_MASK (0xFFU) -#define FTFE_FPROTH3_PROT_SHIFT (0U) -#define FTFE_FPROTH3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH3_PROT_SHIFT)) & FTFE_FPROTH3_PROT_MASK) -/*! @} */ - -/*! @name FPROTH2 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH2_PROT_MASK (0xFFU) -#define FTFE_FPROTH2_PROT_SHIFT (0U) -#define FTFE_FPROTH2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH2_PROT_SHIFT)) & FTFE_FPROTH2_PROT_MASK) -/*! @} */ - -/*! @name FPROTH1 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH1_PROT_MASK (0xFFU) -#define FTFE_FPROTH1_PROT_SHIFT (0U) -#define FTFE_FPROTH1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH1_PROT_SHIFT)) & FTFE_FPROTH1_PROT_MASK) -/*! @} */ - -/*! @name FPROTH0 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH0_PROT_MASK (0xFFU) -#define FTFE_FPROTH0_PROT_SHIFT (0U) -#define FTFE_FPROTH0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH0_PROT_SHIFT)) & FTFE_FPROTH0_PROT_MASK) -/*! @} */ - -/*! @name FPROTL3 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL3_PROT_MASK (0xFFU) -#define FTFE_FPROTL3_PROT_SHIFT (0U) -#define FTFE_FPROTL3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL3_PROT_SHIFT)) & FTFE_FPROTL3_PROT_MASK) -/*! @} */ - -/*! @name FPROTL2 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL2_PROT_MASK (0xFFU) -#define FTFE_FPROTL2_PROT_SHIFT (0U) -#define FTFE_FPROTL2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL2_PROT_SHIFT)) & FTFE_FPROTL2_PROT_MASK) -/*! @} */ - -/*! @name FPROTL1 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL1_PROT_MASK (0xFFU) -#define FTFE_FPROTL1_PROT_SHIFT (0U) -#define FTFE_FPROTL1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL1_PROT_SHIFT)) & FTFE_FPROTL1_PROT_MASK) -/*! @} */ - -/*! @name FPROTL0 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL0_PROT_MASK (0xFFU) -#define FTFE_FPROTL0_PROT_SHIFT (0U) -#define FTFE_FPROTL0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL0_PROT_SHIFT)) & FTFE_FPROTL0_PROT_MASK) -/*! @} */ - -/*! @name FPROTSL - Secondary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTSL_PROTS_MASK (0xFFU) -#define FTFE_FPROTSL_PROTS_SHIFT (0U) -#define FTFE_FPROTSL_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSL_PROTS_SHIFT)) & FTFE_FPROTSL_PROTS_MASK) -/*! @} */ - -/*! @name FPROTSH - Secondary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTSH_PROTS_MASK (0xFFU) -#define FTFE_FPROTSH_PROTS_SHIFT (0U) -#define FTFE_FPROTSH_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSH_PROTS_SHIFT)) & FTFE_FPROTSH_PROTS_MASK) -/*! @} */ - -/*! @name FACSS - Primary Flash Access Segment Size Register */ -/*! @{ */ -#define FTFE_FACSS_SGSIZE_MASK (0xFFU) -#define FTFE_FACSS_SGSIZE_SHIFT (0U) -#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK) -/*! @} */ - -/*! @name FACSN - Primary Flash Access Segment Number Register */ -/*! @{ */ -#define FTFE_FACSN_NUMSG_MASK (0xFFU) -#define FTFE_FACSN_NUMSG_SHIFT (0U) -/*! NUMSG - Number of Segments Indicator - * 0b00110000..Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) - * 0b01000000..Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes) - */ -#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK) -/*! @} */ - -/*! @name FACSSS - Secondary Flash Access Segment Size Register */ -/*! @{ */ -#define FTFE_FACSSS_SGSIZE_S_MASK (0xFFU) -#define FTFE_FACSSS_SGSIZE_S_SHIFT (0U) -#define FTFE_FACSSS_SGSIZE_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSSS_SGSIZE_S_SHIFT)) & FTFE_FACSSS_SGSIZE_S_MASK) -/*! @} */ - -/*! @name FACSNS - Secondary Flash Access Segment Number Register */ -/*! @{ */ -#define FTFE_FACSNS_NUMSG_S_MASK (0xFFU) -#define FTFE_FACSNS_NUMSG_S_SHIFT (0U) -/*! NUMSG_S - Number of Segments Indicator - * 0b00010000..Secondary Program flash memory is divided into 16 segments - */ -#define FTFE_FACSNS_NUMSG_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSNS_NUMSG_S_SHIFT)) & FTFE_FACSNS_NUMSG_S_MASK) -/*! @} */ - -/*! @name XACCH3 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH3_XA_MASK (0xFFU) -#define FTFE_XACCH3_XA_SHIFT (0U) -#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK) -/*! @} */ - -/*! @name XACCH2 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH2_XA_MASK (0xFFU) -#define FTFE_XACCH2_XA_SHIFT (0U) -#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK) -/*! @} */ - -/*! @name XACCH1 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH1_XA_MASK (0xFFU) -#define FTFE_XACCH1_XA_SHIFT (0U) -#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK) -/*! @} */ - -/*! @name XACCH0 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH0_XA_MASK (0xFFU) -#define FTFE_XACCH0_XA_SHIFT (0U) -#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK) -/*! @} */ - -/*! @name XACCL3 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL3_XA_MASK (0xFFU) -#define FTFE_XACCL3_XA_SHIFT (0U) -#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK) -/*! @} */ - -/*! @name XACCL2 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL2_XA_MASK (0xFFU) -#define FTFE_XACCL2_XA_SHIFT (0U) -#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK) -/*! @} */ - -/*! @name XACCL1 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL1_XA_MASK (0xFFU) -#define FTFE_XACCL1_XA_SHIFT (0U) -#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK) -/*! @} */ - -/*! @name XACCL0 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL0_XA_MASK (0xFFU) -#define FTFE_XACCL0_XA_SHIFT (0U) -#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK) -/*! @} */ - -/*! @name SACCH3 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH3_SA_MASK (0xFFU) -#define FTFE_SACCH3_SA_SHIFT (0U) -#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK) -/*! @} */ - -/*! @name SACCH2 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH2_SA_MASK (0xFFU) -#define FTFE_SACCH2_SA_SHIFT (0U) -#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK) -/*! @} */ - -/*! @name SACCH1 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH1_SA_MASK (0xFFU) -#define FTFE_SACCH1_SA_SHIFT (0U) -#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK) -/*! @} */ - -/*! @name SACCH0 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH0_SA_MASK (0xFFU) -#define FTFE_SACCH0_SA_SHIFT (0U) -#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK) -/*! @} */ - -/*! @name SACCL3 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL3_SA_MASK (0xFFU) -#define FTFE_SACCL3_SA_SHIFT (0U) -#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK) -/*! @} */ - -/*! @name SACCL2 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL2_SA_MASK (0xFFU) -#define FTFE_SACCL2_SA_SHIFT (0U) -#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK) -/*! @} */ - -/*! @name SACCL1 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL1_SA_MASK (0xFFU) -#define FTFE_SACCL1_SA_SHIFT (0U) -#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK) -/*! @} */ - -/*! @name SACCL0 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL0_SA_MASK (0xFFU) -#define FTFE_SACCL0_SA_SHIFT (0U) -#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK) -/*! @} */ - -/*! @name XACCSL - Secondary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCSL_XA_S_MASK (0xFFU) -#define FTFE_XACCSL_XA_S_SHIFT (0U) -#define FTFE_XACCSL_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSL_XA_S_SHIFT)) & FTFE_XACCSL_XA_S_MASK) -/*! @} */ - -/*! @name XACCSH - Secondary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCSH_XA_S_MASK (0xFFU) -#define FTFE_XACCSH_XA_S_SHIFT (0U) -#define FTFE_XACCSH_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSH_XA_S_SHIFT)) & FTFE_XACCSH_XA_S_MASK) -/*! @} */ - -/*! @name SACCSL - Secondary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCSL_SA_S_MASK (0xFFU) -#define FTFE_SACCSL_SA_S_SHIFT (0U) -#define FTFE_SACCSL_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSL_SA_S_SHIFT)) & FTFE_SACCSL_SA_S_MASK) -/*! @} */ - -/*! @name SACCSH - Secondary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCSH_SA_S_MASK (0xFFU) -#define FTFE_SACCSH_SA_S_SHIFT (0U) -#define FTFE_SACCSH_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK) -/*! @} */ - -/*! @name FSTDBYCTL - Flash Standby Control Register */ -/*! @{ */ -#define FTFE_FSTDBYCTL_STDBYDIS_MASK (0x1U) -#define FTFE_FSTDBYCTL_STDBYDIS_SHIFT (0U) -/*! STDBYDIS - Standy Mode Disable - * 0b0..Standby mode enabled for flash blocks selected by STDBYx - * 0b1..Standby mode disabled (STDBYx ignored) - */ -#define FTFE_FSTDBYCTL_STDBYDIS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBYCTL_STDBYDIS_SHIFT)) & FTFE_FSTDBYCTL_STDBYDIS_MASK) -/*! @} */ - -/*! @name FSTDBY - Flash Standby Register */ -/*! @{ */ -#define FTFE_FSTDBY_STDBY0_MASK (0x1U) -#define FTFE_FSTDBY_STDBY0_SHIFT (0U) -/*! STDBY0 - Standy Mode for Flash Block 0 - * 0b0..Standby mode not enabled for flash block 0 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block) - */ -#define FTFE_FSTDBY_STDBY0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY0_SHIFT)) & FTFE_FSTDBY_STDBY0_MASK) -#define FTFE_FSTDBY_STDBY1_MASK (0x2U) -#define FTFE_FSTDBY_STDBY1_SHIFT (1U) -/*! STDBY1 - Standy Mode for Flash Block 1 - * 0b0..Standby mode not enabled for flash block 1 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block) - */ -#define FTFE_FSTDBY_STDBY1(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY1_SHIFT)) & FTFE_FSTDBY_STDBY1_MASK) -#define FTFE_FSTDBY_STDBY2_MASK (0x4U) -#define FTFE_FSTDBY_STDBY2_SHIFT (2U) -/*! STDBY2 - Standy Mode for Flash Block 2 - * 0b0..Standby mode not enabled for flash block 2 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 2 - */ -#define FTFE_FSTDBY_STDBY2(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY2_SHIFT)) & FTFE_FSTDBY_STDBY2_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FTFE_Register_Masks */ - - -/* FTFE - Peripheral instance base addresses */ -/** Peripheral FTFE base address */ -#define FTFE_BASE (0x40023000u) -/** Peripheral FTFE base pointer */ -#define FTFE ((FTFE_Type *)FTFE_BASE) -/** Array initializer of FTFE peripheral base addresses */ -#define FTFE_BASE_ADDRS { FTFE_BASE } -/** Array initializer of FTFE peripheral base pointers */ -#define FTFE_BASE_PTRS { FTFE } -/** Interrupt vectors for the FTFE peripheral type */ -#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_Command_Complete_IRQn } -#define FTFE_READ_COLLISION_IRQS { FTFE_Read_Collision_IRQn } - -/*! - * @} - */ /* end of group FTFE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -/*! @{ */ -#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define GPIO_PDOR_PDO_SHIFT (0U) -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) -/*! @} */ - -/*! @name PSOR - Port Set Output Register */ -/*! @{ */ -#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define GPIO_PSOR_PTSO_SHIFT (0U) -#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) -/*! @} */ - -/*! @name PCOR - Port Clear Output Register */ -/*! @{ */ -#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define GPIO_PCOR_PTCO_SHIFT (0U) -#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) -/*! @} */ - -/*! @name PTOR - Port Toggle Output Register */ -/*! @{ */ -#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define GPIO_PTOR_PTTO_SHIFT (0U) -#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) -/*! @} */ - -/*! @name PDIR - Port Data Input Register */ -/*! @{ */ -#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define GPIO_PDIR_PDI_SHIFT (0U) -#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) -/*! @} */ - -/*! @name PDDR - Port Data Direction Register */ -/*! @{ */ -#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define GPIO_PDDR_PDD_SHIFT (0U) -#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIOA base address */ -#define GPIOA_BASE (0x48020000u) -/** Peripheral GPIOA base pointer */ -#define GPIOA ((GPIO_Type *)GPIOA_BASE) -/** Peripheral GPIOB base address */ -#define GPIOB_BASE (0x48020040u) -/** Peripheral GPIOB base pointer */ -#define GPIOB ((GPIO_Type *)GPIOB_BASE) -/** Peripheral GPIOC base address */ -#define GPIOC_BASE (0x48020080u) -/** Peripheral GPIOC base pointer */ -#define GPIOC ((GPIO_Type *)GPIOC_BASE) -/** Peripheral GPIOD base address */ -#define GPIOD_BASE (0x480200C0u) -/** Peripheral GPIOD base pointer */ -#define GPIOD ((GPIO_Type *)GPIOD_BASE) -/** Peripheral GPIOE base address */ -#define GPIOE_BASE (0x4100F000u) -/** Peripheral GPIOE base pointer */ -#define GPIOE ((GPIO_Type *)GPIOE_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ - __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_0[24]; - __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ - uint8_t RESERVED_2[36]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ - __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_3[24]; - __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[24]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define I2S_VERID_FEATURE_MASK (0xFFFFU) -#define I2S_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard feature set. - */ -#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) -#define I2S_VERID_MINOR_MASK (0xFF0000U) -#define I2S_VERID_MINOR_SHIFT (16U) -#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) -#define I2S_VERID_MAJOR_MASK (0xFF000000U) -#define I2S_VERID_MAJOR_SHIFT (24U) -#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define I2S_PARAM_DATALINE_MASK (0xFU) -#define I2S_PARAM_DATALINE_SHIFT (0U) -#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) -#define I2S_PARAM_FIFO_MASK (0xF00U) -#define I2S_PARAM_FIFO_SHIFT (8U) -#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) -#define I2S_PARAM_FRAME_MASK (0xF0000U) -#define I2S_PARAM_FRAME_SHIFT (16U) -#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) -/*! @} */ - -/*! @name TCSR - SAI Transmit Control Register */ -/*! @{ */ -#define I2S_TCSR_FRDE_MASK (0x1U) -#define I2S_TCSR_FRDE_SHIFT (0U) -/*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) -#define I2S_TCSR_FWDE_MASK (0x2U) -#define I2S_TCSR_FWDE_SHIFT (1U) -/*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) -#define I2S_TCSR_FRIE_MASK (0x100U) -#define I2S_TCSR_FRIE_SHIFT (8U) -/*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) -#define I2S_TCSR_FWIE_MASK (0x200U) -#define I2S_TCSR_FWIE_SHIFT (9U) -/*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) -#define I2S_TCSR_FEIE_MASK (0x400U) -#define I2S_TCSR_FEIE_SHIFT (10U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) -#define I2S_TCSR_SEIE_MASK (0x800U) -#define I2S_TCSR_SEIE_SHIFT (11U) -/*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) -#define I2S_TCSR_WSIE_MASK (0x1000U) -#define I2S_TCSR_WSIE_SHIFT (12U) -/*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) -#define I2S_TCSR_FRF_MASK (0x10000U) -#define I2S_TCSR_FRF_SHIFT (16U) -/*! FRF - FIFO Request Flag - * 0b0..Transmit FIFO watermark has not been reached. - * 0b1..Transmit FIFO watermark has been reached. - */ -#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) -#define I2S_TCSR_FWF_MASK (0x20000U) -#define I2S_TCSR_FWF_SHIFT (17U) -/*! FWF - FIFO Warning Flag - * 0b0..No enabled transmit FIFO is empty. - * 0b1..Enabled transmit FIFO is empty. - */ -#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) -#define I2S_TCSR_FEF_MASK (0x40000U) -#define I2S_TCSR_FEF_SHIFT (18U) -/*! FEF - FIFO Error Flag - * 0b0..Transmit underrun not detected. - * 0b1..Transmit underrun detected. - */ -#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) -#define I2S_TCSR_SEF_MASK (0x80000U) -#define I2S_TCSR_SEF_SHIFT (19U) -/*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. - */ -#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) -#define I2S_TCSR_WSF_MASK (0x100000U) -#define I2S_TCSR_WSF_SHIFT (20U) -/*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. - */ -#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) -#define I2S_TCSR_SR_MASK (0x1000000U) -#define I2S_TCSR_SR_SHIFT (24U) -/*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. - */ -#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) -#define I2S_TCSR_FR_MASK (0x2000000U) -#define I2S_TCSR_FR_SHIFT (25U) -/*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. - */ -#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) -#define I2S_TCSR_BCE_MASK (0x10000000U) -#define I2S_TCSR_BCE_SHIFT (28U) -/*! BCE - Bit Clock Enable - * 0b0..Transmit bit clock is disabled. - * 0b1..Transmit bit clock is enabled. - */ -#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) -#define I2S_TCSR_DBGE_MASK (0x20000000U) -#define I2S_TCSR_DBGE_SHIFT (29U) -/*! DBGE - Debug Enable - * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. - * 0b1..Transmitter is enabled in Debug mode. - */ -#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) -#define I2S_TCSR_STOPE_MASK (0x40000000U) -#define I2S_TCSR_STOPE_SHIFT (30U) -/*! STOPE - Stop Enable - * 0b0..Transmitter disabled in Stop mode. - * 0b1..Transmitter enabled in Stop mode. - */ -#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) -#define I2S_TCSR_TE_MASK (0x80000000U) -#define I2S_TCSR_TE_SHIFT (31U) -/*! TE - Transmitter Enable - * 0b0..Transmitter is disabled. - * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. - */ -#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) -/*! @} */ - -/*! @name TCR1 - SAI Transmit Configuration 1 Register */ -/*! @{ */ -#define I2S_TCR1_TFW_MASK (0x7U) -#define I2S_TCR1_TFW_SHIFT (0U) -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) -/*! @} */ - -/*! @name TCR2 - SAI Transmit Configuration 2 Register */ -/*! @{ */ -#define I2S_TCR2_DIV_MASK (0xFFU) -#define I2S_TCR2_DIV_SHIFT (0U) -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) -#define I2S_TCR2_BCD_MASK (0x1000000U) -#define I2S_TCR2_BCD_SHIFT (24U) -/*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. - */ -#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) -#define I2S_TCR2_BCP_MASK (0x2000000U) -#define I2S_TCR2_BCP_SHIFT (25U) -/*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. - */ -#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) -#define I2S_TCR2_MSEL_MASK (0xC000000U) -#define I2S_TCR2_MSEL_SHIFT (26U) -/*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. - */ -#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) -#define I2S_TCR2_BCI_MASK (0x10000000U) -#define I2S_TCR2_BCI_SHIFT (28U) -/*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. - */ -#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) -#define I2S_TCR2_BCS_MASK (0x20000000U) -#define I2S_TCR2_BCS_SHIFT (29U) -/*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. - */ -#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) -#define I2S_TCR2_SYNC_MASK (0xC0000000U) -#define I2S_TCR2_SYNC_SHIFT (30U) -/*! SYNC - Synchronous Mode - * 0b00..Asynchronous mode. - * 0b01..Synchronous with receiver. - * 0b10..Synchronous with another SAI transmitter. - * 0b11..Synchronous with another SAI receiver. - */ -#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) -/*! @} */ - -/*! @name TCR3 - SAI Transmit Configuration 3 Register */ -/*! @{ */ -#define I2S_TCR3_WDFL_MASK (0x1FU) -#define I2S_TCR3_WDFL_SHIFT (0U) -#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) -#define I2S_TCR3_TCE_MASK (0x30000U) -#define I2S_TCR3_TCE_SHIFT (16U) -#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) -#define I2S_TCR3_CFR_MASK (0x3000000U) -#define I2S_TCR3_CFR_SHIFT (24U) -#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) -/*! @} */ - -/*! @name TCR4 - SAI Transmit Configuration 4 Register */ -/*! @{ */ -#define I2S_TCR4_FSD_MASK (0x1U) -#define I2S_TCR4_FSD_SHIFT (0U) -/*! FSD - Frame Sync Direction - * 0b0..Frame sync is generated externally in Slave mode. - * 0b1..Frame sync is generated internally in Master mode. - */ -#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) -#define I2S_TCR4_FSP_MASK (0x2U) -#define I2S_TCR4_FSP_SHIFT (1U) -/*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. - */ -#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) -#define I2S_TCR4_ONDEM_MASK (0x4U) -#define I2S_TCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. - */ -#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) -#define I2S_TCR4_FSE_MASK (0x8U) -#define I2S_TCR4_FSE_SHIFT (3U) -/*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. - */ -#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) -#define I2S_TCR4_MF_MASK (0x10U) -#define I2S_TCR4_MF_SHIFT (4U) -/*! MF - MSB First - * 0b0..LSB is transmitted first. - * 0b1..MSB is transmitted first. - */ -#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) -#define I2S_TCR4_CHMOD_MASK (0x20U) -#define I2S_TCR4_CHMOD_SHIFT (5U) -/*! CHMOD - Channel Mode - * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. - * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. - */ -#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) -#define I2S_TCR4_SYWD_MASK (0x1F00U) -#define I2S_TCR4_SYWD_SHIFT (8U) -#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) -#define I2S_TCR4_FRSZ_MASK (0x1F0000U) -#define I2S_TCR4_FRSZ_SHIFT (16U) -#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) -#define I2S_TCR4_FPACK_MASK (0x3000000U) -#define I2S_TCR4_FPACK_SHIFT (24U) -/*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled - * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled - */ -#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) -#define I2S_TCR4_FCOMB_MASK (0xC000000U) -#define I2S_TCR4_FCOMB_SHIFT (26U) -/*! FCOMB - FIFO Combine Mode - * 0b00..FIFO combine mode disabled. - * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). - * 0b10..FIFO combine mode enabled on FIFO writes (by software). - * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). - */ -#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) -#define I2S_TCR4_FCONT_MASK (0x10000000U) -#define I2S_TCR4_FCONT_SHIFT (28U) -/*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. - */ -#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) -/*! @} */ - -/*! @name TCR5 - SAI Transmit Configuration 5 Register */ -/*! @{ */ -#define I2S_TCR5_FBT_MASK (0x1F00U) -#define I2S_TCR5_FBT_SHIFT (8U) -#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) -#define I2S_TCR5_W0W_MASK (0x1F0000U) -#define I2S_TCR5_W0W_SHIFT (16U) -#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) -#define I2S_TCR5_WNW_MASK (0x1F000000U) -#define I2S_TCR5_WNW_SHIFT (24U) -#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) -/*! @} */ - -/*! @name TDR - SAI Transmit Data Register */ -/*! @{ */ -#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) -#define I2S_TDR_TDR_SHIFT (0U) -#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) -/*! @} */ - -/* The count of I2S_TDR */ -#define I2S_TDR_COUNT (2U) - -/*! @name TFR - SAI Transmit FIFO Register */ -/*! @{ */ -#define I2S_TFR_RFP_MASK (0xFU) -#define I2S_TFR_RFP_SHIFT (0U) -#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) -#define I2S_TFR_WFP_MASK (0xF0000U) -#define I2S_TFR_WFP_SHIFT (16U) -#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) -#define I2S_TFR_WCP_MASK (0x80000000U) -#define I2S_TFR_WCP_SHIFT (31U) -/*! WCP - Write Channel Pointer - * 0b0..No effect. - * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. - */ -#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) -/*! @} */ - -/* The count of I2S_TFR */ -#define I2S_TFR_COUNT (2U) - -/*! @name TMR - SAI Transmit Mask Register */ -/*! @{ */ -#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) -#define I2S_TMR_TWM_SHIFT (0U) -/*! TWM - Transmit Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. - */ -#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) -/*! @} */ - -/*! @name RCSR - SAI Receive Control Register */ -/*! @{ */ -#define I2S_RCSR_FRDE_MASK (0x1U) -#define I2S_RCSR_FRDE_SHIFT (0U) -/*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) -#define I2S_RCSR_FWDE_MASK (0x2U) -#define I2S_RCSR_FWDE_SHIFT (1U) -/*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) -#define I2S_RCSR_FRIE_MASK (0x100U) -#define I2S_RCSR_FRIE_SHIFT (8U) -/*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) -#define I2S_RCSR_FWIE_MASK (0x200U) -#define I2S_RCSR_FWIE_SHIFT (9U) -/*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) -#define I2S_RCSR_FEIE_MASK (0x400U) -#define I2S_RCSR_FEIE_SHIFT (10U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) -#define I2S_RCSR_SEIE_MASK (0x800U) -#define I2S_RCSR_SEIE_SHIFT (11U) -/*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) -#define I2S_RCSR_WSIE_MASK (0x1000U) -#define I2S_RCSR_WSIE_SHIFT (12U) -/*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) -#define I2S_RCSR_FRF_MASK (0x10000U) -#define I2S_RCSR_FRF_SHIFT (16U) -/*! FRF - FIFO Request Flag - * 0b0..Receive FIFO watermark not reached. - * 0b1..Receive FIFO watermark has been reached. - */ -#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) -#define I2S_RCSR_FWF_MASK (0x20000U) -#define I2S_RCSR_FWF_SHIFT (17U) -/*! FWF - FIFO Warning Flag - * 0b0..No enabled receive FIFO is full. - * 0b1..Enabled receive FIFO is full. - */ -#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) -#define I2S_RCSR_FEF_MASK (0x40000U) -#define I2S_RCSR_FEF_SHIFT (18U) -/*! FEF - FIFO Error Flag - * 0b0..Receive overflow not detected. - * 0b1..Receive overflow detected. - */ -#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) -#define I2S_RCSR_SEF_MASK (0x80000U) -#define I2S_RCSR_SEF_SHIFT (19U) -/*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. - */ -#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) -#define I2S_RCSR_WSF_MASK (0x100000U) -#define I2S_RCSR_WSF_SHIFT (20U) -/*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. - */ -#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) -#define I2S_RCSR_SR_MASK (0x1000000U) -#define I2S_RCSR_SR_SHIFT (24U) -/*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. - */ -#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) -#define I2S_RCSR_FR_MASK (0x2000000U) -#define I2S_RCSR_FR_SHIFT (25U) -/*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. - */ -#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) -#define I2S_RCSR_BCE_MASK (0x10000000U) -#define I2S_RCSR_BCE_SHIFT (28U) -/*! BCE - Bit Clock Enable - * 0b0..Receive bit clock is disabled. - * 0b1..Receive bit clock is enabled. - */ -#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) -#define I2S_RCSR_DBGE_MASK (0x20000000U) -#define I2S_RCSR_DBGE_SHIFT (29U) -/*! DBGE - Debug Enable - * 0b0..Receiver is disabled in Debug mode, after completing the current frame. - * 0b1..Receiver is enabled in Debug mode. - */ -#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) -#define I2S_RCSR_STOPE_MASK (0x40000000U) -#define I2S_RCSR_STOPE_SHIFT (30U) -/*! STOPE - Stop Enable - * 0b0..Receiver disabled in Stop mode. - * 0b1..Receiver enabled in Stop mode. - */ -#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) -#define I2S_RCSR_RE_MASK (0x80000000U) -#define I2S_RCSR_RE_SHIFT (31U) -/*! RE - Receiver Enable - * 0b0..Receiver is disabled. - * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. - */ -#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) -/*! @} */ - -/*! @name RCR1 - SAI Receive Configuration 1 Register */ -/*! @{ */ -#define I2S_RCR1_RFW_MASK (0x7U) -#define I2S_RCR1_RFW_SHIFT (0U) -#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) -/*! @} */ - -/*! @name RCR2 - SAI Receive Configuration 2 Register */ -/*! @{ */ -#define I2S_RCR2_DIV_MASK (0xFFU) -#define I2S_RCR2_DIV_SHIFT (0U) -#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) -#define I2S_RCR2_BCD_MASK (0x1000000U) -#define I2S_RCR2_BCD_SHIFT (24U) -/*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. - */ -#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) -#define I2S_RCR2_BCP_MASK (0x2000000U) -#define I2S_RCR2_BCP_SHIFT (25U) -/*! BCP - Bit Clock Polarity - * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. - */ -#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) -#define I2S_RCR2_MSEL_MASK (0xC000000U) -#define I2S_RCR2_MSEL_SHIFT (26U) -/*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. - */ -#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) -#define I2S_RCR2_BCI_MASK (0x10000000U) -#define I2S_RCR2_BCI_SHIFT (28U) -/*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. - */ -#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) -#define I2S_RCR2_BCS_MASK (0x20000000U) -#define I2S_RCR2_BCS_SHIFT (29U) -/*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. - */ -#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) -#define I2S_RCR2_SYNC_MASK (0xC0000000U) -#define I2S_RCR2_SYNC_SHIFT (30U) -/*! SYNC - Synchronous Mode - * 0b00..Asynchronous mode. - * 0b01..Synchronous with transmitter. - * 0b10..Synchronous with another SAI receiver. - * 0b11..Synchronous with another SAI transmitter. - */ -#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) -/*! @} */ - -/*! @name RCR3 - SAI Receive Configuration 3 Register */ -/*! @{ */ -#define I2S_RCR3_WDFL_MASK (0x1FU) -#define I2S_RCR3_WDFL_SHIFT (0U) -#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) -#define I2S_RCR3_RCE_MASK (0x30000U) -#define I2S_RCR3_RCE_SHIFT (16U) -#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) -#define I2S_RCR3_CFR_MASK (0x3000000U) -#define I2S_RCR3_CFR_SHIFT (24U) -#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) -/*! @} */ - -/*! @name RCR4 - SAI Receive Configuration 4 Register */ -/*! @{ */ -#define I2S_RCR4_FSD_MASK (0x1U) -#define I2S_RCR4_FSD_SHIFT (0U) -/*! FSD - Frame Sync Direction - * 0b0..Frame Sync is generated externally in Slave mode. - * 0b1..Frame Sync is generated internally in Master mode. - */ -#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) -#define I2S_RCR4_FSP_MASK (0x2U) -#define I2S_RCR4_FSP_SHIFT (1U) -/*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. - */ -#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) -#define I2S_RCR4_ONDEM_MASK (0x4U) -#define I2S_RCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. - */ -#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) -#define I2S_RCR4_FSE_MASK (0x8U) -#define I2S_RCR4_FSE_SHIFT (3U) -/*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. - */ -#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) -#define I2S_RCR4_MF_MASK (0x10U) -#define I2S_RCR4_MF_SHIFT (4U) -/*! MF - MSB First - * 0b0..LSB is received first. - * 0b1..MSB is received first. - */ -#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) -#define I2S_RCR4_SYWD_MASK (0x1F00U) -#define I2S_RCR4_SYWD_SHIFT (8U) -#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) -#define I2S_RCR4_FRSZ_MASK (0x1F0000U) -#define I2S_RCR4_FRSZ_SHIFT (16U) -#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) -#define I2S_RCR4_FPACK_MASK (0x3000000U) -#define I2S_RCR4_FPACK_SHIFT (24U) -/*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled - * 0b01..Reserved. - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled - */ -#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) -#define I2S_RCR4_FCOMB_MASK (0xC000000U) -#define I2S_RCR4_FCOMB_SHIFT (26U) -/*! FCOMB - FIFO Combine Mode - * 0b00..FIFO combine mode disabled. - * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). - * 0b10..FIFO combine mode enabled on FIFO reads (by software). - * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). - */ -#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) -#define I2S_RCR4_FCONT_MASK (0x10000000U) -#define I2S_RCR4_FCONT_SHIFT (28U) -/*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. - */ -#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) -/*! @} */ - -/*! @name RCR5 - SAI Receive Configuration 5 Register */ -/*! @{ */ -#define I2S_RCR5_FBT_MASK (0x1F00U) -#define I2S_RCR5_FBT_SHIFT (8U) -#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) -#define I2S_RCR5_W0W_MASK (0x1F0000U) -#define I2S_RCR5_W0W_SHIFT (16U) -#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) -#define I2S_RCR5_WNW_MASK (0x1F000000U) -#define I2S_RCR5_WNW_SHIFT (24U) -#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) -/*! @} */ - -/*! @name RDR - SAI Receive Data Register */ -/*! @{ */ -#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) -#define I2S_RDR_RDR_SHIFT (0U) -#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) -/*! @} */ - -/* The count of I2S_RDR */ -#define I2S_RDR_COUNT (2U) - -/*! @name RFR - SAI Receive FIFO Register */ -/*! @{ */ -#define I2S_RFR_RFP_MASK (0xFU) -#define I2S_RFR_RFP_SHIFT (0U) -#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) -#define I2S_RFR_RCP_MASK (0x8000U) -#define I2S_RFR_RCP_SHIFT (15U) -/*! RCP - Receive Channel Pointer - * 0b0..No effect. - * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. - */ -#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) -#define I2S_RFR_WFP_MASK (0xF0000U) -#define I2S_RFR_WFP_SHIFT (16U) -#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) -/*! @} */ - -/* The count of I2S_RFR */ -#define I2S_RFR_COUNT (2U) - -/*! @name RMR - SAI Receive Mask Register */ -/*! @{ */ -#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) -#define I2S_RMR_RWM_SHIFT (0U) -/*! RWM - Receive Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. - */ -#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x4003D000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { I2S0_IRQn } -#define I2S_TX_IRQS { I2S0_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer - * @{ - */ - -/** INTMUX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x40 */ - __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */ - __I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */ - uint8_t RESERVED_1[12]; - __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */ - uint8_t RESERVED_2[28]; - } CHANNEL[8]; -} INTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INTMUX_Register_Masks INTMUX Register Masks - * @{ - */ - -/*! @name CHn_CSR - Channel n Control Status Register */ -/*! @{ */ -#define INTMUX_CHn_CSR_RST_MASK (0x1U) -#define INTMUX_CHn_CSR_RST_SHIFT (0U) -/*! RST - Software Reset - * 0b0..No operation. - * 0b1..Perform a software reset on this channel. - */ -#define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK) -#define INTMUX_CHn_CSR_AND_MASK (0x2U) -#define INTMUX_CHn_CSR_AND_SHIFT (1U) -/*! AND - Logic AND - * 0b0..Logic OR all enabled interrupt inputs. - * 0b1..Logic AND all enabled interrupt inputs. - */ -#define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK) -#define INTMUX_CHn_CSR_IRQN_MASK (0x30U) -#define INTMUX_CHn_CSR_IRQN_SHIFT (4U) -/*! IRQN - Channel Input Number - * 0b00..32 interrupt inputs - * 0b01..Reserved - * 0b10..Reserved - * 0b11..Reserved - */ -#define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK) -#define INTMUX_CHn_CSR_CHIN_MASK (0xF00U) -#define INTMUX_CHn_CSR_CHIN_SHIFT (8U) -#define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK) -#define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) -#define INTMUX_CHn_CSR_IRQP_SHIFT (31U) -/*! IRQP - Channel Interrupt Request Pending - * 0b0..No interrupt is pending. - * 0b1..The interrupt output of this channel is pending. - */ -#define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_CSR */ -#define INTMUX_CHn_CSR_COUNT (8U) - -/*! @name CHn_VEC - Channel n Vector Number Register */ -/*! @{ */ -#define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU) -#define INTMUX_CHn_VEC_VECN_SHIFT (2U) -#define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_VEC */ -#define INTMUX_CHn_VEC_COUNT (8U) - -/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */ -/*! @{ */ -#define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU) -#define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U) -#define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_IER_31_0 */ -#define INTMUX_CHn_IER_31_0_COUNT (8U) - -/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */ -/*! @{ */ -#define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU) -#define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U) -#define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_IPR_31_0 */ -#define INTMUX_CHn_IPR_31_0_COUNT (8U) - - -/*! - * @} - */ /* end of group INTMUX_Register_Masks */ - - -/* INTMUX - Peripheral instance base addresses */ -/** Peripheral INTMUX0 base address */ -#define INTMUX0_BASE (0x4004F000u) -/** Peripheral INTMUX0 base pointer */ -#define INTMUX0 ((INTMUX_Type *)INTMUX0_BASE) -/** Array initializer of INTMUX peripheral base addresses */ -#define INTMUX_BASE_ADDRS { INTMUX0_BASE } -/** Array initializer of INTMUX peripheral base pointers */ -#define INTMUX_BASE_PTRS { INTMUX0 } -/** Interrupt vectors for the INTMUX peripheral type */ -#define INTMUX_IRQS { { INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn, INTMUX0_4_IRQn, INTMUX0_5_IRQn, INTMUX0_6_IRQn, INTMUX0_7_IRQn }, } - -/*! - * @} - */ /* end of group INTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer - * @{ - */ - -/** LLWU - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t PE1; /**< Pin Enable 1 register, offset: 0x8 */ - __IO uint32_t PE2; /**< Pin Enable 2 register, offset: 0xC */ - uint8_t RESERVED_0[8]; - __IO uint32_t ME; /**< Module Interrupt Enable register, offset: 0x18 */ - __IO uint32_t DE; /**< Module DMA/Trigger Enable register, offset: 0x1C */ - __IO uint32_t PF; /**< Pin Flag register, offset: 0x20 */ - uint8_t RESERVED_1[12]; - __IO uint32_t FILT; /**< Pin Filter register, offset: 0x30 */ - uint8_t RESERVED_2[4]; - __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1 register, offset: 0x38 */ - __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2 register, offset: 0x3C */ - uint8_t RESERVED_3[8]; - __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration register, offset: 0x48 */ - uint8_t RESERVED_4[4]; - __IO uint32_t PMC; /**< Pin Mode Configuration register, offset: 0x50 */ - uint8_t RESERVED_5[4]; - __IO uint32_t FMC; /**< Pin Filter Mode Configuration register, offset: 0x58 */ -} LLWU_Type; - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LLWU_VERID_FEATURE_MASK (0xFFFFU) -#define LLWU_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented - * 0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled. - */ -#define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK) -#define LLWU_VERID_MINOR_MASK (0xFF0000U) -#define LLWU_VERID_MINOR_SHIFT (16U) -#define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK) -#define LLWU_VERID_MAJOR_MASK (0xFF000000U) -#define LLWU_VERID_MAJOR_SHIFT (24U) -#define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LLWU_PARAM_FILTERS_MASK (0xFFU) -#define LLWU_PARAM_FILTERS_SHIFT (0U) -#define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK) -#define LLWU_PARAM_DMAS_MASK (0xFF00U) -#define LLWU_PARAM_DMAS_SHIFT (8U) -#define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK) -#define LLWU_PARAM_MODULES_MASK (0xFF0000U) -#define LLWU_PARAM_MODULES_SHIFT (16U) -#define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK) -#define LLWU_PARAM_PINS_MASK (0xFF000000U) -#define LLWU_PARAM_PINS_SHIFT (24U) -#define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK) -/*! @} */ - -/*! @name PE1 - Pin Enable 1 register */ -/*! @{ */ -#define LLWU_PE1_WUPE0_MASK (0x3U) -#define LLWU_PE1_WUPE0_SHIFT (0U) -/*! WUPE0 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) -#define LLWU_PE1_WUPE1_MASK (0xCU) -#define LLWU_PE1_WUPE1_SHIFT (2U) -/*! WUPE1 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) -#define LLWU_PE1_WUPE2_MASK (0x30U) -#define LLWU_PE1_WUPE2_SHIFT (4U) -/*! WUPE2 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) -#define LLWU_PE1_WUPE3_MASK (0xC0U) -#define LLWU_PE1_WUPE3_SHIFT (6U) -/*! WUPE3 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) -#define LLWU_PE1_WUPE4_MASK (0x300U) -#define LLWU_PE1_WUPE4_SHIFT (8U) -/*! WUPE4 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK) -#define LLWU_PE1_WUPE5_MASK (0xC00U) -#define LLWU_PE1_WUPE5_SHIFT (10U) -/*! WUPE5 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK) -#define LLWU_PE1_WUPE6_MASK (0x3000U) -#define LLWU_PE1_WUPE6_SHIFT (12U) -/*! WUPE6 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK) -#define LLWU_PE1_WUPE7_MASK (0xC000U) -#define LLWU_PE1_WUPE7_SHIFT (14U) -/*! WUPE7 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK) -#define LLWU_PE1_WUPE8_MASK (0x30000U) -#define LLWU_PE1_WUPE8_SHIFT (16U) -/*! WUPE8 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK) -#define LLWU_PE1_WUPE9_MASK (0xC0000U) -#define LLWU_PE1_WUPE9_SHIFT (18U) -/*! WUPE9 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK) -#define LLWU_PE1_WUPE10_MASK (0x300000U) -#define LLWU_PE1_WUPE10_SHIFT (20U) -/*! WUPE10 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK) -#define LLWU_PE1_WUPE11_MASK (0xC00000U) -#define LLWU_PE1_WUPE11_SHIFT (22U) -/*! WUPE11 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK) -#define LLWU_PE1_WUPE12_MASK (0x3000000U) -#define LLWU_PE1_WUPE12_SHIFT (24U) -/*! WUPE12 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK) -#define LLWU_PE1_WUPE13_MASK (0xC000000U) -#define LLWU_PE1_WUPE13_SHIFT (26U) -/*! WUPE13 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK) -#define LLWU_PE1_WUPE14_MASK (0x30000000U) -#define LLWU_PE1_WUPE14_SHIFT (28U) -/*! WUPE14 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK) -#define LLWU_PE1_WUPE15_MASK (0xC0000000U) -#define LLWU_PE1_WUPE15_SHIFT (30U) -/*! WUPE15 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK) -/*! @} */ - -/*! @name PE2 - Pin Enable 2 register */ -/*! @{ */ -#define LLWU_PE2_WUPE16_MASK (0x3U) -#define LLWU_PE2_WUPE16_SHIFT (0U) -/*! WUPE16 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK) -#define LLWU_PE2_WUPE17_MASK (0xCU) -#define LLWU_PE2_WUPE17_SHIFT (2U) -/*! WUPE17 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK) -#define LLWU_PE2_WUPE18_MASK (0x30U) -#define LLWU_PE2_WUPE18_SHIFT (4U) -/*! WUPE18 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK) -#define LLWU_PE2_WUPE19_MASK (0xC0U) -#define LLWU_PE2_WUPE19_SHIFT (6U) -/*! WUPE19 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK) -#define LLWU_PE2_WUPE20_MASK (0x300U) -#define LLWU_PE2_WUPE20_SHIFT (8U) -/*! WUPE20 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK) -#define LLWU_PE2_WUPE21_MASK (0xC00U) -#define LLWU_PE2_WUPE21_SHIFT (10U) -/*! WUPE21 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK) -#define LLWU_PE2_WUPE22_MASK (0x3000U) -#define LLWU_PE2_WUPE22_SHIFT (12U) -/*! WUPE22 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK) -#define LLWU_PE2_WUPE23_MASK (0xC000U) -#define LLWU_PE2_WUPE23_SHIFT (14U) -/*! WUPE23 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK) -#define LLWU_PE2_WUPE24_MASK (0x30000U) -#define LLWU_PE2_WUPE24_SHIFT (16U) -/*! WUPE24 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK) -#define LLWU_PE2_WUPE25_MASK (0xC0000U) -#define LLWU_PE2_WUPE25_SHIFT (18U) -/*! WUPE25 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK) -#define LLWU_PE2_WUPE26_MASK (0x300000U) -#define LLWU_PE2_WUPE26_SHIFT (20U) -/*! WUPE26 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK) -#define LLWU_PE2_Reserved27_MASK (0xC00000U) -#define LLWU_PE2_Reserved27_SHIFT (22U) -/*! Reserved27 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved27_SHIFT)) & LLWU_PE2_Reserved27_MASK) -#define LLWU_PE2_Reserved28_MASK (0x3000000U) -#define LLWU_PE2_Reserved28_SHIFT (24U) -/*! Reserved28 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved28_SHIFT)) & LLWU_PE2_Reserved28_MASK) -#define LLWU_PE2_WUPE29_MASK (0xC000000U) -#define LLWU_PE2_WUPE29_SHIFT (26U) -/*! WUPE29 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK) -#define LLWU_PE2_WUPE30_MASK (0x30000000U) -#define LLWU_PE2_WUPE30_SHIFT (28U) -/*! WUPE30 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK) -#define LLWU_PE2_WUPE31_MASK (0xC0000000U) -#define LLWU_PE2_WUPE31_SHIFT (30U) -/*! WUPE31 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK) -/*! @} */ - -/*! @name ME - Module Interrupt Enable register */ -/*! @{ */ -#define LLWU_ME_WUME0_MASK (0x1U) -#define LLWU_ME_WUME0_SHIFT (0U) -/*! WUME0 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) -#define LLWU_ME_WUME1_MASK (0x2U) -#define LLWU_ME_WUME1_SHIFT (1U) -/*! WUME1 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) -#define LLWU_ME_WUME2_MASK (0x4U) -#define LLWU_ME_WUME2_SHIFT (2U) -/*! WUME2 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) -#define LLWU_ME_Reserved3_MASK (0x8U) -#define LLWU_ME_Reserved3_SHIFT (3U) -/*! Reserved3 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK) -#define LLWU_ME_WUME3_MASK (0x8U) -#define LLWU_ME_WUME3_SHIFT (3U) -/*! WUME3 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) -#define LLWU_ME_Reserved4_MASK (0x10U) -#define LLWU_ME_Reserved4_SHIFT (4U) -/*! Reserved4 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved4_SHIFT)) & LLWU_ME_Reserved4_MASK) -#define LLWU_ME_WUME5_MASK (0x20U) -#define LLWU_ME_WUME5_SHIFT (5U) -/*! WUME5 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) -#define LLWU_ME_WUME6_MASK (0x40U) -#define LLWU_ME_WUME6_SHIFT (6U) -/*! WUME6 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) -#define LLWU_ME_WUME7_MASK (0x80U) -#define LLWU_ME_WUME7_SHIFT (7U) -/*! WUME7 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) -/*! @} */ - -/*! @name DE - Module DMA/Trigger Enable register */ -/*! @{ */ -#define LLWU_DE_WUDE0_MASK (0x1U) -#define LLWU_DE_WUDE0_SHIFT (0U) -/*! WUDE0 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK) -#define LLWU_DE_WUDE1_MASK (0x2U) -#define LLWU_DE_WUDE1_SHIFT (1U) -/*! WUDE1 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK) -#define LLWU_DE_WUDE2_MASK (0x4U) -#define LLWU_DE_WUDE2_SHIFT (2U) -/*! WUDE2 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK) -#define LLWU_DE_Reserved3_MASK (0x8U) -#define LLWU_DE_Reserved3_SHIFT (3U) -/*! Reserved3 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved3_SHIFT)) & LLWU_DE_Reserved3_MASK) -#define LLWU_DE_WUDE4_MASK (0x10U) -#define LLWU_DE_WUDE4_SHIFT (4U) -/*! WUDE4 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK) -#define LLWU_DE_WUDE5_MASK (0x20U) -#define LLWU_DE_WUDE5_SHIFT (5U) -/*! WUDE5 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK) -#define LLWU_DE_WUDE6_MASK (0x40U) -#define LLWU_DE_WUDE6_SHIFT (6U) -/*! WUDE6 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK) -#define LLWU_DE_Reserved7_MASK (0x80U) -#define LLWU_DE_Reserved7_SHIFT (7U) -/*! Reserved7 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_Reserved7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved7_SHIFT)) & LLWU_DE_Reserved7_MASK) -/*! @} */ - -/*! @name PF - Pin Flag register */ -/*! @{ */ -#define LLWU_PF_WUF0_MASK (0x1U) -#define LLWU_PF_WUF0_SHIFT (0U) -/*! WUF0 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK) -#define LLWU_PF_WUF1_MASK (0x2U) -#define LLWU_PF_WUF1_SHIFT (1U) -/*! WUF1 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK) -#define LLWU_PF_WUF2_MASK (0x4U) -#define LLWU_PF_WUF2_SHIFT (2U) -/*! WUF2 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK) -#define LLWU_PF_WUF3_MASK (0x8U) -#define LLWU_PF_WUF3_SHIFT (3U) -/*! WUF3 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK) -#define LLWU_PF_WUF4_MASK (0x10U) -#define LLWU_PF_WUF4_SHIFT (4U) -/*! WUF4 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK) -#define LLWU_PF_WUF5_MASK (0x20U) -#define LLWU_PF_WUF5_SHIFT (5U) -/*! WUF5 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK) -#define LLWU_PF_WUF6_MASK (0x40U) -#define LLWU_PF_WUF6_SHIFT (6U) -/*! WUF6 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK) -#define LLWU_PF_WUF7_MASK (0x80U) -#define LLWU_PF_WUF7_SHIFT (7U) -/*! WUF7 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK) -#define LLWU_PF_WUF8_MASK (0x100U) -#define LLWU_PF_WUF8_SHIFT (8U) -/*! WUF8 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK) -#define LLWU_PF_WUF9_MASK (0x200U) -#define LLWU_PF_WUF9_SHIFT (9U) -/*! WUF9 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK) -#define LLWU_PF_WUF10_MASK (0x400U) -#define LLWU_PF_WUF10_SHIFT (10U) -/*! WUF10 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK) -#define LLWU_PF_WUF11_MASK (0x800U) -#define LLWU_PF_WUF11_SHIFT (11U) -/*! WUF11 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK) -#define LLWU_PF_WUF12_MASK (0x1000U) -#define LLWU_PF_WUF12_SHIFT (12U) -/*! WUF12 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK) -#define LLWU_PF_WUF13_MASK (0x2000U) -#define LLWU_PF_WUF13_SHIFT (13U) -/*! WUF13 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK) -#define LLWU_PF_WUF14_MASK (0x4000U) -#define LLWU_PF_WUF14_SHIFT (14U) -/*! WUF14 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK) -#define LLWU_PF_WUF15_MASK (0x8000U) -#define LLWU_PF_WUF15_SHIFT (15U) -/*! WUF15 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK) -#define LLWU_PF_WUF16_MASK (0x10000U) -#define LLWU_PF_WUF16_SHIFT (16U) -/*! WUF16 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK) -#define LLWU_PF_WUF17_MASK (0x20000U) -#define LLWU_PF_WUF17_SHIFT (17U) -/*! WUF17 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK) -#define LLWU_PF_WUF18_MASK (0x40000U) -#define LLWU_PF_WUF18_SHIFT (18U) -/*! WUF18 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK) -#define LLWU_PF_WUF19_MASK (0x80000U) -#define LLWU_PF_WUF19_SHIFT (19U) -/*! WUF19 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK) -#define LLWU_PF_WUF20_MASK (0x100000U) -#define LLWU_PF_WUF20_SHIFT (20U) -/*! WUF20 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK) -#define LLWU_PF_WUF21_MASK (0x200000U) -#define LLWU_PF_WUF21_SHIFT (21U) -/*! WUF21 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK) -#define LLWU_PF_WUF22_MASK (0x400000U) -#define LLWU_PF_WUF22_SHIFT (22U) -/*! WUF22 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK) -#define LLWU_PF_WUF23_MASK (0x800000U) -#define LLWU_PF_WUF23_SHIFT (23U) -/*! WUF23 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK) -#define LLWU_PF_WUF24_MASK (0x1000000U) -#define LLWU_PF_WUF24_SHIFT (24U) -/*! WUF24 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK) -#define LLWU_PF_WUF25_MASK (0x2000000U) -#define LLWU_PF_WUF25_SHIFT (25U) -/*! WUF25 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK) -#define LLWU_PF_WUF26_MASK (0x4000000U) -#define LLWU_PF_WUF26_SHIFT (26U) -/*! WUF26 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK) -#define LLWU_PF_Reserved27_MASK (0x8000000U) -#define LLWU_PF_Reserved27_SHIFT (27U) -/*! Reserved27 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved27_SHIFT)) & LLWU_PF_Reserved27_MASK) -#define LLWU_PF_Reserved28_MASK (0x10000000U) -#define LLWU_PF_Reserved28_SHIFT (28U) -/*! Reserved28 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved28_SHIFT)) & LLWU_PF_Reserved28_MASK) -#define LLWU_PF_WUF29_MASK (0x20000000U) -#define LLWU_PF_WUF29_SHIFT (29U) -/*! WUF29 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK) -#define LLWU_PF_WUF30_MASK (0x40000000U) -#define LLWU_PF_WUF30_SHIFT (30U) -/*! WUF30 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK) -#define LLWU_PF_WUF31_MASK (0x80000000U) -#define LLWU_PF_WUF31_SHIFT (31U) -/*! WUF31 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK) -/*! @} */ - -/*! @name FILT - Pin Filter register */ -/*! @{ */ -#define LLWU_FILT_FILTSEL1_MASK (0x1FU) -#define LLWU_FILT_FILTSEL1_SHIFT (0U) -/*! FILTSEL1 - Filter 1 Pin Select - * 0b00000..Select LLWU_P0 for filter - * 0b11111..Select LLWU_P31 for filter - */ -#define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK) -#define LLWU_FILT_FILTE1_MASK (0x60U) -#define LLWU_FILT_FILTE1_SHIFT (5U) -/*! FILTE1 - Filter 1 Enable - * 0b00..Filter disabled - * 0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..Filter any edge detect enabled when configured as interrupt/DMA request - */ -#define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK) -#define LLWU_FILT_FILTF1_MASK (0x80U) -#define LLWU_FILT_FILTF1_SHIFT (7U) -/*! FILTF1 - Filter 1 Flag - * 0b0..Pin Filter 1 was not a wakeup source - * 0b1..Pin Filter 1 was a wakeup source - */ -#define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK) -#define LLWU_FILT_FILTSEL2_MASK (0x1F00U) -#define LLWU_FILT_FILTSEL2_SHIFT (8U) -/*! FILTSEL2 - Filter 2 Pin Select - * 0b00000..Select LLWU_P0 for filter - * 0b11111..Select LLWU_P31 for filter - */ -#define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK) -#define LLWU_FILT_FILTE2_MASK (0x6000U) -#define LLWU_FILT_FILTE2_SHIFT (13U) -/*! FILTE2 - Filter 2 Enable - * 0b00..Filter disabled - * 0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..Filter any edge detect enabled when configured as interrupt/DMA request - */ -#define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK) -#define LLWU_FILT_FILTF2_MASK (0x8000U) -#define LLWU_FILT_FILTF2_SHIFT (15U) -/*! FILTF2 - Filter 2 Flag - * 0b0..Pin Filter 2 was not a wakeup source - * 0b1..Pin Filter 2 was a wakeup source - */ -#define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK) -/*! @} */ - -/*! @name PDC1 - Pin DMA/Trigger Configuration 1 register */ -/*! @{ */ -#define LLWU_PDC1_WUPDC0_MASK (0x3U) -#define LLWU_PDC1_WUPDC0_SHIFT (0U) -/*! WUPDC0 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC0_SHIFT)) & LLWU_PDC1_WUPDC0_MASK) -#define LLWU_PDC1_WUPDC1_MASK (0xCU) -#define LLWU_PDC1_WUPDC1_SHIFT (2U) -/*! WUPDC1 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC1_SHIFT)) & LLWU_PDC1_WUPDC1_MASK) -#define LLWU_PDC1_WUPDC2_MASK (0x30U) -#define LLWU_PDC1_WUPDC2_SHIFT (4U) -/*! WUPDC2 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC2_SHIFT)) & LLWU_PDC1_WUPDC2_MASK) -#define LLWU_PDC1_WUPDC3_MASK (0xC0U) -#define LLWU_PDC1_WUPDC3_SHIFT (6U) -/*! WUPDC3 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC3_SHIFT)) & LLWU_PDC1_WUPDC3_MASK) -#define LLWU_PDC1_WUPDC4_MASK (0x300U) -#define LLWU_PDC1_WUPDC4_SHIFT (8U) -/*! WUPDC4 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC4_SHIFT)) & LLWU_PDC1_WUPDC4_MASK) -#define LLWU_PDC1_WUPDC5_MASK (0xC00U) -#define LLWU_PDC1_WUPDC5_SHIFT (10U) -/*! WUPDC5 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC5_SHIFT)) & LLWU_PDC1_WUPDC5_MASK) -#define LLWU_PDC1_WUPDC6_MASK (0x3000U) -#define LLWU_PDC1_WUPDC6_SHIFT (12U) -/*! WUPDC6 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC6_SHIFT)) & LLWU_PDC1_WUPDC6_MASK) -#define LLWU_PDC1_WUPDC7_MASK (0xC000U) -#define LLWU_PDC1_WUPDC7_SHIFT (14U) -/*! WUPDC7 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC7_SHIFT)) & LLWU_PDC1_WUPDC7_MASK) -#define LLWU_PDC1_WUPDC8_MASK (0x30000U) -#define LLWU_PDC1_WUPDC8_SHIFT (16U) -/*! WUPDC8 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC8_SHIFT)) & LLWU_PDC1_WUPDC8_MASK) -#define LLWU_PDC1_WUPDC9_MASK (0xC0000U) -#define LLWU_PDC1_WUPDC9_SHIFT (18U) -/*! WUPDC9 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC9_SHIFT)) & LLWU_PDC1_WUPDC9_MASK) -#define LLWU_PDC1_WUPDC10_MASK (0x300000U) -#define LLWU_PDC1_WUPDC10_SHIFT (20U) -/*! WUPDC10 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC10_SHIFT)) & LLWU_PDC1_WUPDC10_MASK) -#define LLWU_PDC1_WUPDC11_MASK (0xC00000U) -#define LLWU_PDC1_WUPDC11_SHIFT (22U) -/*! WUPDC11 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC11_SHIFT)) & LLWU_PDC1_WUPDC11_MASK) -#define LLWU_PDC1_WUPDC12_MASK (0x3000000U) -#define LLWU_PDC1_WUPDC12_SHIFT (24U) -/*! WUPDC12 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC12_SHIFT)) & LLWU_PDC1_WUPDC12_MASK) -#define LLWU_PDC1_WUPDC13_MASK (0xC000000U) -#define LLWU_PDC1_WUPDC13_SHIFT (26U) -/*! WUPDC13 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC13_SHIFT)) & LLWU_PDC1_WUPDC13_MASK) -#define LLWU_PDC1_WUPDC14_MASK (0x30000000U) -#define LLWU_PDC1_WUPDC14_SHIFT (28U) -/*! WUPDC14 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC14_SHIFT)) & LLWU_PDC1_WUPDC14_MASK) -#define LLWU_PDC1_WUPDC15_MASK (0xC0000000U) -#define LLWU_PDC1_WUPDC15_SHIFT (30U) -/*! WUPDC15 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC15_SHIFT)) & LLWU_PDC1_WUPDC15_MASK) -/*! @} */ - -/*! @name PDC2 - Pin DMA/Trigger Configuration 2 register */ -/*! @{ */ -#define LLWU_PDC2_WUPDC16_MASK (0x3U) -#define LLWU_PDC2_WUPDC16_SHIFT (0U) -/*! WUPDC16 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC16_SHIFT)) & LLWU_PDC2_WUPDC16_MASK) -#define LLWU_PDC2_WUPDC17_MASK (0xCU) -#define LLWU_PDC2_WUPDC17_SHIFT (2U) -/*! WUPDC17 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC17_SHIFT)) & LLWU_PDC2_WUPDC17_MASK) -#define LLWU_PDC2_WUPDC18_MASK (0x30U) -#define LLWU_PDC2_WUPDC18_SHIFT (4U) -/*! WUPDC18 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC18_SHIFT)) & LLWU_PDC2_WUPDC18_MASK) -#define LLWU_PDC2_WUPDC19_MASK (0xC0U) -#define LLWU_PDC2_WUPDC19_SHIFT (6U) -/*! WUPDC19 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC19_SHIFT)) & LLWU_PDC2_WUPDC19_MASK) -#define LLWU_PDC2_WUPDC20_MASK (0x300U) -#define LLWU_PDC2_WUPDC20_SHIFT (8U) -/*! WUPDC20 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC20_SHIFT)) & LLWU_PDC2_WUPDC20_MASK) -#define LLWU_PDC2_WUPDC21_MASK (0xC00U) -#define LLWU_PDC2_WUPDC21_SHIFT (10U) -/*! WUPDC21 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC21_SHIFT)) & LLWU_PDC2_WUPDC21_MASK) -#define LLWU_PDC2_WUPDC22_MASK (0x3000U) -#define LLWU_PDC2_WUPDC22_SHIFT (12U) -/*! WUPDC22 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC22_SHIFT)) & LLWU_PDC2_WUPDC22_MASK) -#define LLWU_PDC2_WUPDC23_MASK (0xC000U) -#define LLWU_PDC2_WUPDC23_SHIFT (14U) -/*! WUPDC23 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC23_SHIFT)) & LLWU_PDC2_WUPDC23_MASK) -#define LLWU_PDC2_WUPDC24_MASK (0x30000U) -#define LLWU_PDC2_WUPDC24_SHIFT (16U) -/*! WUPDC24 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC24_SHIFT)) & LLWU_PDC2_WUPDC24_MASK) -#define LLWU_PDC2_WUPDC25_MASK (0xC0000U) -#define LLWU_PDC2_WUPDC25_SHIFT (18U) -/*! WUPDC25 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC25_SHIFT)) & LLWU_PDC2_WUPDC25_MASK) -#define LLWU_PDC2_WUPDC26_MASK (0x300000U) -#define LLWU_PDC2_WUPDC26_SHIFT (20U) -/*! WUPDC26 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC26_SHIFT)) & LLWU_PDC2_WUPDC26_MASK) -#define LLWU_PDC2_Reserved27_MASK (0xC00000U) -#define LLWU_PDC2_Reserved27_SHIFT (22U) -/*! Reserved27 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved27_SHIFT)) & LLWU_PDC2_Reserved27_MASK) -#define LLWU_PDC2_Reserved28_MASK (0x3000000U) -#define LLWU_PDC2_Reserved28_SHIFT (24U) -/*! Reserved28 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved28_SHIFT)) & LLWU_PDC2_Reserved28_MASK) -#define LLWU_PDC2_WUPDC29_MASK (0xC000000U) -#define LLWU_PDC2_WUPDC29_SHIFT (26U) -/*! WUPDC29 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC29_SHIFT)) & LLWU_PDC2_WUPDC29_MASK) -#define LLWU_PDC2_WUPDC30_MASK (0x30000000U) -#define LLWU_PDC2_WUPDC30_SHIFT (28U) -/*! WUPDC30 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC30_SHIFT)) & LLWU_PDC2_WUPDC30_MASK) -#define LLWU_PDC2_WUPDC31_MASK (0xC0000000U) -#define LLWU_PDC2_WUPDC31_SHIFT (30U) -/*! WUPDC31 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC31_SHIFT)) & LLWU_PDC2_WUPDC31_MASK) -/*! @} */ - -/*! @name FDC - Pin Filter DMA/Trigger Configuration register */ -/*! @{ */ -#define LLWU_FDC_FILTC1_MASK (0x3U) -#define LLWU_FDC_FILTC1_SHIFT (0U) -/*! FILTC1 - Filter configuration for FILT1 - * 0b00..Filter output configured as interrupt - * 0b01..Filter output configured as DMA request - * 0b10..Filter output configured as trigger event - * 0b11..Reserved - */ -#define LLWU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC1_SHIFT)) & LLWU_FDC_FILTC1_MASK) -#define LLWU_FDC_FILTC2_MASK (0xCU) -#define LLWU_FDC_FILTC2_SHIFT (2U) -/*! FILTC2 - Filter configuration for FILT2 - * 0b00..Filter output configured as interrupt - * 0b01..Filter output configured as DMA request - * 0b10..Filter output configured as trigger event - * 0b11..Reserved - */ -#define LLWU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC2_SHIFT)) & LLWU_FDC_FILTC2_MASK) -/*! @} */ - -/*! @name PMC - Pin Mode Configuration register */ -/*! @{ */ -#define LLWU_PMC_WUPMC0_MASK (0x1U) -#define LLWU_PMC_WUPMC0_SHIFT (0U) -/*! WUPMC0 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC0_SHIFT)) & LLWU_PMC_WUPMC0_MASK) -#define LLWU_PMC_WUPMC1_MASK (0x2U) -#define LLWU_PMC_WUPMC1_SHIFT (1U) -/*! WUPMC1 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC1_SHIFT)) & LLWU_PMC_WUPMC1_MASK) -#define LLWU_PMC_WUPMC2_MASK (0x4U) -#define LLWU_PMC_WUPMC2_SHIFT (2U) -/*! WUPMC2 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC2_SHIFT)) & LLWU_PMC_WUPMC2_MASK) -#define LLWU_PMC_WUPMC3_MASK (0x8U) -#define LLWU_PMC_WUPMC3_SHIFT (3U) -/*! WUPMC3 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC3_SHIFT)) & LLWU_PMC_WUPMC3_MASK) -#define LLWU_PMC_WUPMC4_MASK (0x10U) -#define LLWU_PMC_WUPMC4_SHIFT (4U) -/*! WUPMC4 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC4_SHIFT)) & LLWU_PMC_WUPMC4_MASK) -#define LLWU_PMC_WUPMC5_MASK (0x20U) -#define LLWU_PMC_WUPMC5_SHIFT (5U) -/*! WUPMC5 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC5_SHIFT)) & LLWU_PMC_WUPMC5_MASK) -#define LLWU_PMC_WUPMC6_MASK (0x40U) -#define LLWU_PMC_WUPMC6_SHIFT (6U) -/*! WUPMC6 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC6_SHIFT)) & LLWU_PMC_WUPMC6_MASK) -#define LLWU_PMC_WUPMC7_MASK (0x80U) -#define LLWU_PMC_WUPMC7_SHIFT (7U) -/*! WUPMC7 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC7_SHIFT)) & LLWU_PMC_WUPMC7_MASK) -#define LLWU_PMC_WUPMC8_MASK (0x100U) -#define LLWU_PMC_WUPMC8_SHIFT (8U) -/*! WUPMC8 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC8_SHIFT)) & LLWU_PMC_WUPMC8_MASK) -#define LLWU_PMC_WUPMC9_MASK (0x200U) -#define LLWU_PMC_WUPMC9_SHIFT (9U) -/*! WUPMC9 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC9_SHIFT)) & LLWU_PMC_WUPMC9_MASK) -#define LLWU_PMC_WUPMC10_MASK (0x400U) -#define LLWU_PMC_WUPMC10_SHIFT (10U) -/*! WUPMC10 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC10_SHIFT)) & LLWU_PMC_WUPMC10_MASK) -#define LLWU_PMC_WUPMC11_MASK (0x800U) -#define LLWU_PMC_WUPMC11_SHIFT (11U) -/*! WUPMC11 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC11_SHIFT)) & LLWU_PMC_WUPMC11_MASK) -#define LLWU_PMC_WUPMC12_MASK (0x1000U) -#define LLWU_PMC_WUPMC12_SHIFT (12U) -/*! WUPMC12 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC12_SHIFT)) & LLWU_PMC_WUPMC12_MASK) -#define LLWU_PMC_WUPMC13_MASK (0x2000U) -#define LLWU_PMC_WUPMC13_SHIFT (13U) -/*! WUPMC13 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC13_SHIFT)) & LLWU_PMC_WUPMC13_MASK) -#define LLWU_PMC_WUPMC14_MASK (0x4000U) -#define LLWU_PMC_WUPMC14_SHIFT (14U) -/*! WUPMC14 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC14_SHIFT)) & LLWU_PMC_WUPMC14_MASK) -#define LLWU_PMC_WUPMC15_MASK (0x8000U) -#define LLWU_PMC_WUPMC15_SHIFT (15U) -/*! WUPMC15 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC15_SHIFT)) & LLWU_PMC_WUPMC15_MASK) -#define LLWU_PMC_WUPMC16_MASK (0x10000U) -#define LLWU_PMC_WUPMC16_SHIFT (16U) -/*! WUPMC16 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC16_SHIFT)) & LLWU_PMC_WUPMC16_MASK) -#define LLWU_PMC_WUPMC17_MASK (0x20000U) -#define LLWU_PMC_WUPMC17_SHIFT (17U) -/*! WUPMC17 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC17_SHIFT)) & LLWU_PMC_WUPMC17_MASK) -#define LLWU_PMC_WUPMC18_MASK (0x40000U) -#define LLWU_PMC_WUPMC18_SHIFT (18U) -/*! WUPMC18 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC18_SHIFT)) & LLWU_PMC_WUPMC18_MASK) -#define LLWU_PMC_WUPMC19_MASK (0x80000U) -#define LLWU_PMC_WUPMC19_SHIFT (19U) -/*! WUPMC19 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC19_SHIFT)) & LLWU_PMC_WUPMC19_MASK) -#define LLWU_PMC_WUPMC20_MASK (0x100000U) -#define LLWU_PMC_WUPMC20_SHIFT (20U) -/*! WUPMC20 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC20_SHIFT)) & LLWU_PMC_WUPMC20_MASK) -#define LLWU_PMC_WUPMC21_MASK (0x200000U) -#define LLWU_PMC_WUPMC21_SHIFT (21U) -/*! WUPMC21 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC21_SHIFT)) & LLWU_PMC_WUPMC21_MASK) -#define LLWU_PMC_WUPMC22_MASK (0x400000U) -#define LLWU_PMC_WUPMC22_SHIFT (22U) -/*! WUPMC22 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC22_SHIFT)) & LLWU_PMC_WUPMC22_MASK) -#define LLWU_PMC_WUPMC23_MASK (0x800000U) -#define LLWU_PMC_WUPMC23_SHIFT (23U) -/*! WUPMC23 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC23_SHIFT)) & LLWU_PMC_WUPMC23_MASK) -#define LLWU_PMC_WUPMC24_MASK (0x1000000U) -#define LLWU_PMC_WUPMC24_SHIFT (24U) -/*! WUPMC24 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC24_SHIFT)) & LLWU_PMC_WUPMC24_MASK) -#define LLWU_PMC_WUPMC25_MASK (0x2000000U) -#define LLWU_PMC_WUPMC25_SHIFT (25U) -/*! WUPMC25 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC25_SHIFT)) & LLWU_PMC_WUPMC25_MASK) -#define LLWU_PMC_WUPMC26_MASK (0x4000000U) -#define LLWU_PMC_WUPMC26_SHIFT (26U) -/*! WUPMC26 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC26_SHIFT)) & LLWU_PMC_WUPMC26_MASK) -#define LLWU_PMC_Reserved27_MASK (0x8000000U) -#define LLWU_PMC_Reserved27_SHIFT (27U) -/*! Reserved27 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved27_SHIFT)) & LLWU_PMC_Reserved27_MASK) -#define LLWU_PMC_Reserved28_MASK (0x10000000U) -#define LLWU_PMC_Reserved28_SHIFT (28U) -/*! Reserved28 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved28_SHIFT)) & LLWU_PMC_Reserved28_MASK) -#define LLWU_PMC_WUPMC29_MASK (0x20000000U) -#define LLWU_PMC_WUPMC29_SHIFT (29U) -/*! WUPMC29 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC29_SHIFT)) & LLWU_PMC_WUPMC29_MASK) -#define LLWU_PMC_WUPMC30_MASK (0x40000000U) -#define LLWU_PMC_WUPMC30_SHIFT (30U) -/*! WUPMC30 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC30_SHIFT)) & LLWU_PMC_WUPMC30_MASK) -#define LLWU_PMC_WUPMC31_MASK (0x80000000U) -#define LLWU_PMC_WUPMC31_SHIFT (31U) -/*! WUPMC31 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC31_SHIFT)) & LLWU_PMC_WUPMC31_MASK) -/*! @} */ - -/*! @name FMC - Pin Filter Mode Configuration register */ -/*! @{ */ -#define LLWU_FMC_FILTM1_MASK (0x1U) -#define LLWU_FMC_FILTM1_SHIFT (0U) -/*! FILTM1 - Filter Mode for FILT1 - * 0b0..External input pin filter detection active only during LLS/VLLS mode - * 0b1..External input pin filter detection active during all power modes - */ -#define LLWU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM1_SHIFT)) & LLWU_FMC_FILTM1_MASK) -#define LLWU_FMC_FILTM2_MASK (0x2U) -#define LLWU_FMC_FILTM2_SHIFT (1U) -/*! FILTM2 - Filter Mode for FILT2 - * 0b0..External input pin filter detection active only during LLS/VLLS mode - * 0b1..External input pin filter detection active during all power modes - */ -#define LLWU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM2_SHIFT)) & LLWU_FMC_FILTM2_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LLWU_Register_Masks */ - - -/* LLWU - Peripheral instance base addresses */ -/** Peripheral LLWU0 base address */ -#define LLWU0_BASE (0x40024000u) -/** Peripheral LLWU0 base pointer */ -#define LLWU0 ((LLWU_Type *)LLWU0_BASE) -/** Peripheral LLWU1 base address */ -#define LLWU1_BASE (0x41023000u) -/** Peripheral LLWU1 base pointer */ -#define LLWU1 ((LLWU_Type *)LLWU1_BASE) -/** Array initializer of LLWU peripheral base addresses */ -#define LLWU_BASE_ADDRS { LLWU0_BASE, LLWU1_BASE } -/** Array initializer of LLWU peripheral base pointers */ -#define LLWU_BASE_PTRS { LLWU0, LLWU1 } -/** Interrupt vectors for the LLWU peripheral type */ -#define LLWU_IRQS { LLWU0_IRQn, NotAvail_IRQn } - -/*! - * @} - */ /* end of group LLWU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPCMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer - * @{ - */ - -/** LPCMP - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ - __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ - __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DCR; /**< DAC Control Register, offset: 0x18 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ -} LPCMP_Type; - -/* ---------------------------------------------------------------------------- - -- LPCMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPCMP_Register_Masks LPCMP Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) -#define LPCMP_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000001..Round robin feature - */ -#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) -#define LPCMP_VERID_MINOR_MASK (0xFF0000U) -#define LPCMP_VERID_MINOR_SHIFT (16U) -#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) -#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) -#define LPCMP_VERID_MAJOR_SHIFT (24U) -#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPCMP_PARAM_DAC_RES_MASK (0xFU) -#define LPCMP_PARAM_DAC_RES_SHIFT (0U) -/*! DAC_RES - DAC resolution - * 0b0000..4 bit DAC - * 0b0001..6 bit DAC - * 0b0010..8 bit DAC - * 0b0011..10 bit DAC - * 0b0100..12 bit DAC - * 0b0101..14 bit DAC - * 0b0110..16 bit DAC - */ -#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) -/*! @} */ - -/*! @name CCR0 - Comparator Control Register 0 */ -/*! @{ */ -#define LPCMP_CCR0_CMP_EN_MASK (0x1U) -#define LPCMP_CCR0_CMP_EN_SHIFT (0U) -/*! CMP_EN - Comparator Module Enable - * 0b0..Analog Comparator is disabled. - * 0b1..Analog Comparator is enabled. - */ -#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) -#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) -#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) -/*! CMP_STOP_EN - Comparator Module STOP Mode Enable - * 0b0..Comparator is disabled in STOP modes regardless of CMP_EN. - * 0b1..Comparator is enabled in STOP mode if CMP_EN is active - */ -#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) -/*! @} */ - -/*! @name CCR1 - Comparator Control Register 1 */ -/*! @{ */ -#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) -#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) -/*! WINDOW_EN - Windowing Enable - * 0b0..Windowing mode is not selected. - * 0b1..Windowing mode is selected. - */ -#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) -#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) -#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) -/*! SAMPLE_EN - Sample Enable - * 0b0..Sampling mode is not selected. - * 0b1..Sampling mode is selected. - */ -#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) -#define LPCMP_CCR1_DMA_EN_MASK (0x4U) -#define LPCMP_CCR1_DMA_EN_SHIFT (2U) -/*! DMA_EN - DMA Enable - * 0b0..DMA is disabled. - * 0b1..DMA is enabled. - */ -#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) -#define LPCMP_CCR1_COUT_INV_MASK (0x8U) -#define LPCMP_CCR1_COUT_INV_SHIFT (3U) -/*! COUT_INV - Comparator invert - * 0b0..Does not invert the comparator output. - * 0b1..Inverts the comparator output. - */ -#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) -#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) -#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) -/*! COUT_SEL - Comparator Output Select - * 0b0..Set CMPO to equal COUT (filtered comparator output). - * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). - */ -#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) -#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) -#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) -/*! COUT_PEN - Comparator Output Pin Enable - * 0b0..When COUT_PEN is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. - * 0b1..When COUT_PEN is 1, and if the software has configured the comparator to own a packaged pin, the comparator output is available in a packaged pin. - */ -#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) -#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) -#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) -/*! FILT_CNT - Filter Sample Count - * 0b000..Filter is disabled. If SAMPLE_EN = 1, then COUT is a logic zero (this is not a legal state in , and is not recommended). If SAMPLE_EN = 0, COUT = COUTA. - * 0b001..1 consecutive sample must agree (comparator output is simply sampled). - * 0b010..2 consecutive samples must agree. - * 0b011..3 consecutive samples must agree. - * 0b100..4 consecutive samples must agree. - * 0b101..5 consecutive samples must agree. - * 0b110..6 consecutive samples must agree. - * 0b111..7 consecutive samples must agree. - */ -#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) -#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) -#define LPCMP_CCR1_FILT_PER_SHIFT (24U) -#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) -/*! @} */ - -/*! @name CCR2 - Comparator Control Register 2 */ -/*! @{ */ -#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) -#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) -/*! CMP_HPMD - CMP High Power Mode Select - * 0b0..Low speed comparison mode is selected.(when CMP_NPMD is 0) - * 0b1..High speed comparison mode is selected.(when CMP_NPMD is 0) - */ -#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) -#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) -#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) -/*! CMP_NPMD - CMP Nano Power Mode Select - * 0b0..Nano Power Comparator is not enabled (mode is determined by CMP_HPMD) - * 0b1..Nano Power Comparator is enabled - */ -#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) -#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) -#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) -/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level - * 0b00..The hard block output has level 0 hysteresis internally. - * 0b01..The hard block output has level 1 hysteresis internally. - * 0b10..The hard block output has level 2 hysteresis internally. - * 0b11..The hard block output has level 3 hysteresis internally. - */ -#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) -#define LPCMP_CCR2_PSEL_MASK (0x70000U) -#define LPCMP_CCR2_PSEL_SHIFT (16U) -/*! PSEL - Plus Input MUX Control - * 0b000..Input 0 - * 0b001..Input 1 - * 0b010..Input 2 - * 0b011..Input 3 - * 0b100..Input 4 - * 0b101..Input 5 - * 0b110..Input 6 - * 0b111..Internal DAC output - */ -#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) -#define LPCMP_CCR2_MSEL_MASK (0x700000U) -#define LPCMP_CCR2_MSEL_SHIFT (20U) -/*! MSEL - Minus Input MUX Control - * 0b000..Input 0 - * 0b001..Input 1 - * 0b010..Input 2 - * 0b011..Input 3 - * 0b100..Input 4 - * 0b101..Input 5 - * 0b110..Input 6 - * 0b111..Internal DAC output - */ -#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) -/*! @} */ - -/*! @name DCR - DAC Control Register */ -/*! @{ */ -#define LPCMP_DCR_DAC_EN_MASK (0x1U) -#define LPCMP_DCR_DAC_EN_SHIFT (0U) -/*! DAC_EN - DAC Enable - * 0b0..DAC is disabled. - * 0b1..DAC is enabled. - */ -#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) -#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) -#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) -/*! DAC_HPMD - DAC High Power Mode Select - * 0b0..DAC high power mode is not enabled. - * 0b1..DAC high power mode is enabled. - */ -#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) -#define LPCMP_DCR_VRSEL_MASK (0x100U) -#define LPCMP_DCR_VRSEL_SHIFT (8U) -/*! VRSEL - Supply Voltage Reference Source Select - * 0b0..vrefh_int is selected as resistor ladder network supply reference Vin. - * 0b1..vrefh_ext is selected as resistor ladder network supply reference Vin. - */ -#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) -#define LPCMP_DCR_DAC_DATA_MASK (0x3F0000U) -#define LPCMP_DCR_DAC_DATA_SHIFT (16U) -#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ -#define LPCMP_IER_CFR_IE_MASK (0x1U) -#define LPCMP_IER_CFR_IE_SHIFT (0U) -/*! CFR_IE - Comparator Flag Rising Interrupt Enable - * 0b0..CFR interrupt is disabled. - * 0b1..CFR interrupt is enabled. - */ -#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) -#define LPCMP_IER_CFF_IE_MASK (0x2U) -#define LPCMP_IER_CFF_IE_SHIFT (1U) -/*! CFF_IE - Comparator Flag Falling Interrupt Enable - * 0b0..CFF interrupt is disabled. - * 0b1..CFF interrupt is enabled. - */ -#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) -/*! @} */ - -/*! @name CSR - Comparator Status Register */ -/*! @{ */ -#define LPCMP_CSR_CFR_MASK (0x1U) -#define LPCMP_CSR_CFR_SHIFT (0U) -/*! CFR - Analog Comparator Flag Rising - * 0b0..A rising edge has not been detected on COUT. - * 0b1..A rising edge on COUT has occurred. - */ -#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) -#define LPCMP_CSR_CFF_MASK (0x2U) -#define LPCMP_CSR_CFF_SHIFT (1U) -/*! CFF - Analog Comparator Flag Falling - * 0b0..A falling edge has not been detected on COUT. - * 0b1..A falling edge on COUT has occurred. - */ -#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) -#define LPCMP_CSR_COUT_MASK (0x100U) -#define LPCMP_CSR_COUT_SHIFT (8U) -#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPCMP_Register_Masks */ - - -/* LPCMP - Peripheral instance base addresses */ -/** Peripheral LPCMP0 base address */ -#define LPCMP0_BASE (0x4004B000u) -/** Peripheral LPCMP0 base pointer */ -#define LPCMP0 ((LPCMP_Type *)LPCMP0_BASE) -/** Peripheral LPCMP1 base address */ -#define LPCMP1_BASE (0x41038000u) -/** Peripheral LPCMP1 base pointer */ -#define LPCMP1 ((LPCMP_Type *)LPCMP1_BASE) -/** Array initializer of LPCMP peripheral base addresses */ -#define LPCMP_BASE_ADDRS { LPCMP0_BASE, LPCMP1_BASE } -/** Array initializer of LPCMP peripheral base pointers */ -#define LPCMP_BASE_PTRS { LPCMP0, LPCMP1 } -/** Interrupt vectors for the LPCMP peripheral type */ -#define LPCMP_IRQS { LPCMP0_IRQn, LPCMP1_IRQn } - -/*! - * @} - */ /* end of group LPCMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPDAC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer - * @{ - */ - -/** LPDAC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */ - __IO uint32_t GCR; /**< DAC Global Control Register, offset: 0xC */ - __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ - __I uint32_t FPR; /**< DAC FIFO Pointer Register, offset: 0x14 */ - __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x18 */ - __IO uint32_t IER; /**< DAC Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t DER; /**< DAC DMA Enable Register, offset: 0x20 */ - __IO uint32_t RCR; /**< DAC Reset Control Register, offset: 0x24 */ - __O uint32_t TCR; /**< DAC Trigger Control Register, offset: 0x28 */ -} LPDAC_Type; - -/* ---------------------------------------------------------------------------- - -- LPDAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Register_Masks LPDAC Register Masks - * @{ - */ - -/*! @name VERID - Version Identifier Register */ -/*! @{ */ -#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) -#define LPDAC_VERID_FEATURE_SHIFT (0U) -#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) -#define LPDAC_VERID_MINOR_MASK (0xFF0000U) -#define LPDAC_VERID_MINOR_SHIFT (16U) -#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) -#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) -#define LPDAC_VERID_MAJOR_SHIFT (24U) -#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) -#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) -/*! FIFOSZ - FIFO size - * 0b000..Reserved - * 0b001..FIFO depth is 4 - * 0b010..FIFO depth is 8 - * 0b011..FIFO depth is 16 - * 0b100..FIFO depth is 32 - * 0b101..FIFO depth is 64 - * 0b110..FIFO depth is 128 - * 0b111..FIFO depth is 256 - */ -#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) -/*! @} */ - -/*! @name DATA - DAC Data Register */ -/*! @{ */ -#define LPDAC_DATA_DATA_MASK (0xFFFU) -#define LPDAC_DATA_DATA_SHIFT (0U) -#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) -/*! @} */ - -/*! @name GCR - DAC Global Control Register */ -/*! @{ */ -#define LPDAC_GCR_DACEN_MASK (0x1U) -#define LPDAC_GCR_DACEN_SHIFT (0U) -/*! DACEN - DAC Enable - * 0b0..The DAC system is disabled. - * 0b1..The DAC system is enabled. - */ -#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) -#define LPDAC_GCR_DACRFS_MASK (0x2U) -#define LPDAC_GCR_DACRFS_SHIFT (1U) -/*! DACRFS - DAC Reference Select - * 0b0..The DAC selects VREFH_INT as the reference voltage. - * 0b1..The DAC selects VREFH_EXT as the reference voltage. - */ -#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) -#define LPDAC_GCR_LPEN_MASK (0x4U) -#define LPDAC_GCR_LPEN_SHIFT (2U) -/*! LPEN - Low Power Enable - * 0b0..High-Power mode - * 0b1..Low-Power mode - */ -#define LPDAC_GCR_LPEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LPEN_SHIFT)) & LPDAC_GCR_LPEN_MASK) -#define LPDAC_GCR_FIFOEN_MASK (0x8U) -#define LPDAC_GCR_FIFOEN_SHIFT (3U) -/*! FIFOEN - FIFO Enable - * 0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion. - * 0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion - */ -#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) -#define LPDAC_GCR_SWMD_MASK (0x10U) -#define LPDAC_GCR_SWMD_SHIFT (4U) -/*! SWMD - Swing Back Mode - * 0b0..Swing back mode disable - * 0b1..Swing back mode enable - */ -#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) -#define LPDAC_GCR_TRGSEL_MASK (0x20U) -#define LPDAC_GCR_TRGSEL_SHIFT (5U) -/*! TRGSEL - DAC Trigger Select - * 0b0..The DAC hardware trigger is selected. - * 0b1..The DAC software trigger is selected. - */ -#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) -/*! @} */ - -/*! @name FCR - DAC FIFO Control Register */ -/*! @{ */ -#define LPDAC_FCR_WML_MASK (0xFU) -#define LPDAC_FCR_WML_SHIFT (0U) -#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) -/*! @} */ - -/*! @name FPR - DAC FIFO Pointer Register */ -/*! @{ */ -#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) -#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) -#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) -#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) -#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) -#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ -#define LPDAC_FSR_FULL_MASK (0x1U) -#define LPDAC_FSR_FULL_SHIFT (0U) -/*! FULL - FIFO Full Flag - * 0b0..FIFO is not full - * 0b1..FIFO is full - */ -#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) -#define LPDAC_FSR_EMPTY_MASK (0x2U) -#define LPDAC_FSR_EMPTY_SHIFT (1U) -/*! EMPTY - FIFO Empty Flag - * 0b0..FIFO is not empty - * 0b1..FIFO is empty - */ -#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) -#define LPDAC_FSR_WM_MASK (0x4U) -#define LPDAC_FSR_WM_SHIFT (2U) -/*! WM - FIFO Watermark Status Flag - * 0b0..Data in FIFO is more than watermark level - * 0b1..Data in FIFO is less than or equal to watermark level - */ -#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) -#define LPDAC_FSR_SWBK_MASK (0x8U) -#define LPDAC_FSR_SWBK_SHIFT (3U) -/*! SWBK - Swing Back One Cycle Complete Flag - * 0b0..No swing back cycle has completed since the last time the flag was cleared. - * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) -#define LPDAC_FSR_OF_MASK (0x40U) -#define LPDAC_FSR_OF_SHIFT (6U) -/*! OF - FIFO Overflow Flag - * 0b0..No overflow has occurred since the last time the flag was cleared. - * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) -#define LPDAC_FSR_UF_MASK (0x80U) -#define LPDAC_FSR_UF_SHIFT (7U) -/*! UF - FIFO Underflow Flag - * 0b0..No underflow has occurred since the last time the flag was cleared. - * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) -/*! @} */ - -/*! @name IER - DAC Interrupt Enable Register */ -/*! @{ */ -#define LPDAC_IER_FULL_IE_MASK (0x1U) -#define LPDAC_IER_FULL_IE_SHIFT (0U) -/*! FULL_IE - FIFO Full Interrupt Enable - * 0b0..FIFO Full interrupt is disabled. - * 0b1..FIFO Full interrupt is enabled. - */ -#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) -#define LPDAC_IER_EMPTY_IE_MASK (0x2U) -#define LPDAC_IER_EMPTY_IE_SHIFT (1U) -/*! EMPTY_IE - FIFO Empty Interrupt Enable - * 0b0..FIFO Empty interrupt is disabled. - * 0b1..FIFO Empty interrupt is enabled. - */ -#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) -#define LPDAC_IER_WM_IE_MASK (0x4U) -#define LPDAC_IER_WM_IE_SHIFT (2U) -/*! WM_IE - FIFO Watermark Interrupt Enable - * 0b0..Watermark interrupt is disabled. - * 0b1..Watermark interrupt is enabled. - */ -#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) -#define LPDAC_IER_SWBK_IE_MASK (0x8U) -#define LPDAC_IER_SWBK_IE_SHIFT (3U) -/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable - * 0b0..Swing back one time complete interrupt is disabled. - * 0b1..Swing back one time complete interrupt is enabled. - */ -#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) -#define LPDAC_IER_OF_IE_MASK (0x40U) -#define LPDAC_IER_OF_IE_SHIFT (6U) -/*! OF_IE - FIFO Overflow Interrupt Enable - * 0b0..Overflow interrupt is disabled - * 0b1..Overflow interrupt is enabled. - */ -#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) -#define LPDAC_IER_UF_IE_MASK (0x80U) -#define LPDAC_IER_UF_IE_SHIFT (7U) -/*! UF_IE - FIFO Underflow Interrupt Enable - * 0b0..Underflow interrupt is disabled. - * 0b1..Underflow interrupt is enabled. - */ -#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) -/*! @} */ - -/*! @name DER - DAC DMA Enable Register */ -/*! @{ */ -#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) -#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) -/*! EMPTY_DMAEN - FIFO Empty DMA Enable - * 0b0..FIFO Empty DMA request is disabled. - * 0b1..FIFO Empty DMA request is enabled. - */ -#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) -#define LPDAC_DER_WM_DMAEN_MASK (0x4U) -#define LPDAC_DER_WM_DMAEN_SHIFT (2U) -/*! WM_DMAEN - FIFO Watermark DMA Enable - * 0b0..Watermark DMA request is disabled. - * 0b1..Watermark DMA request is enabled. - */ -#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) -/*! @} */ - -/*! @name RCR - DAC Reset Control Register */ -/*! @{ */ -#define LPDAC_RCR_SWRST_MASK (0x1U) -#define LPDAC_RCR_SWRST_SHIFT (0U) -/*! SWRST - Software Reset - * 0b0..No effect - * 0b1..Software reset - */ -#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) -#define LPDAC_RCR_FIFORST_MASK (0x2U) -#define LPDAC_RCR_FIFORST_SHIFT (1U) -/*! FIFORST - FIFO Reset - * 0b0..No effect - * 0b1..FIFO reset - */ -#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) -/*! @} */ - -/*! @name TCR - DAC Trigger Control Register */ -/*! @{ */ -#define LPDAC_TCR_SWTRG_MASK (0x1U) -#define LPDAC_TCR_SWTRG_SHIFT (0U) -/*! SWTRG - Software Trigger - * 0b0..The DAC soft trigger is not valid. - * 0b1..The DAC soft trigger is valid. - */ -#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPDAC_Register_Masks */ - - -/* LPDAC - Peripheral instance base addresses */ -/** Peripheral LPDAC0 base address */ -#define LPDAC0_BASE (0x4004C000u) -/** Peripheral LPDAC0 base pointer */ -#define LPDAC0 ((LPDAC_Type *)LPDAC0_BASE) -/** Array initializer of LPDAC peripheral base addresses */ -#define LPDAC_BASE_ADDRS { LPDAC0_BASE } -/** Array initializer of LPDAC peripheral base pointers */ -#define LPDAC_BASE_PTRS { LPDAC0 } -/** Interrupt vectors for the LPDAC peripheral type */ -#define LPDAC_IRQS { LPDAC0_IRQn } - -/*! - * @} - */ /* end of group LPDAC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPI2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer - * @{ - */ - -/** LPI2C - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ - __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ - __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ - __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ - __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ - __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ - __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ - uint8_t RESERVED_1[16]; - __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ - __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ - __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ - uint8_t RESERVED_5[12]; - __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ - uint8_t RESERVED_6[156]; - __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ - __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ - __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ - __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ - uint8_t RESERVED_7[4]; - __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ - __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ - uint8_t RESERVED_8[20]; - __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ - uint8_t RESERVED_9[12]; - __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ - __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ - uint8_t RESERVED_10[8]; - __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ - uint8_t RESERVED_11[12]; - __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ -} LPI2C_Type; - -/* ---------------------------------------------------------------------------- - -- LPI2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Register_Masks LPI2C Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) -#define LPI2C_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000010..Master only, with standard feature set - * 0b0000000000000011..Master and slave, with standard feature set - */ -#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) -#define LPI2C_VERID_MINOR_MASK (0xFF0000U) -#define LPI2C_VERID_MINOR_SHIFT (16U) -#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) -#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) -#define LPI2C_VERID_MAJOR_SHIFT (24U) -#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) -#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) -#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) -#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) -#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) -#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) -/*! @} */ - -/*! @name MCR - Master Control Register */ -/*! @{ */ -#define LPI2C_MCR_MEN_MASK (0x1U) -#define LPI2C_MCR_MEN_SHIFT (0U) -/*! MEN - Master Enable - * 0b0..Master logic is disabled - * 0b1..Master logic is enabled - */ -#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) -#define LPI2C_MCR_RST_MASK (0x2U) -#define LPI2C_MCR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Master logic is not reset - * 0b1..Master logic is reset - */ -#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) -#define LPI2C_MCR_DOZEN_MASK (0x4U) -#define LPI2C_MCR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Master is enabled in Doze mode - * 0b1..Master is disabled in Doze mode - */ -#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) -#define LPI2C_MCR_DBGEN_MASK (0x8U) -#define LPI2C_MCR_DBGEN_SHIFT (3U) -/*! DBGEN - Debug Enable - * 0b0..Master is disabled in debug mode - * 0b1..Master is enabled in debug mode - */ -#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) -#define LPI2C_MCR_RTF_MASK (0x100U) -#define LPI2C_MCR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit FIFO is reset - */ -#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) -#define LPI2C_MCR_RRF_MASK (0x200U) -#define LPI2C_MCR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive FIFO is reset - */ -#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) -/*! @} */ - -/*! @name MSR - Master Status Register */ -/*! @{ */ -#define LPI2C_MSR_TDF_MASK (0x1U) -#define LPI2C_MSR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data is not requested - * 0b1..Transmit data is requested - */ -#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) -#define LPI2C_MSR_RDF_MASK (0x2U) -#define LPI2C_MSR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive Data is not ready - * 0b1..Receive data is ready - */ -#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) -#define LPI2C_MSR_EPF_MASK (0x100U) -#define LPI2C_MSR_EPF_SHIFT (8U) -/*! EPF - End Packet Flag - * 0b0..Master has not generated a STOP or Repeated START condition - * 0b1..Master has generated a STOP or Repeated START condition - */ -#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) -#define LPI2C_MSR_SDF_MASK (0x200U) -#define LPI2C_MSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Master has not generated a STOP condition - * 0b1..Master has generated a STOP condition - */ -#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) -#define LPI2C_MSR_NDF_MASK (0x400U) -#define LPI2C_MSR_NDF_SHIFT (10U) -/*! NDF - NACK Detect Flag - * 0b0..Unexpected NACK was not detected - * 0b1..Unexpected NACK was detected - */ -#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) -#define LPI2C_MSR_ALF_MASK (0x800U) -#define LPI2C_MSR_ALF_SHIFT (11U) -/*! ALF - Arbitration Lost Flag - * 0b0..Master has not lost arbitration - * 0b1..Master has lost arbitration - */ -#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) -#define LPI2C_MSR_FEF_MASK (0x1000U) -#define LPI2C_MSR_FEF_SHIFT (12U) -/*! FEF - FIFO Error Flag - * 0b0..No error - * 0b1..Master sending or receiving data without a START condition - */ -#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) -#define LPI2C_MSR_PLTF_MASK (0x2000U) -#define LPI2C_MSR_PLTF_SHIFT (13U) -/*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout has not occurred or is disabled - * 0b1..Pin low timeout has occurred - */ -#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) -#define LPI2C_MSR_DMF_MASK (0x4000U) -#define LPI2C_MSR_DMF_SHIFT (14U) -/*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data - */ -#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) -#define LPI2C_MSR_MBF_MASK (0x1000000U) -#define LPI2C_MSR_MBF_SHIFT (24U) -/*! MBF - Master Busy Flag - * 0b0..I2C Master is idle - * 0b1..I2C Master is busy - */ -#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) -#define LPI2C_MSR_BBF_MASK (0x2000000U) -#define LPI2C_MSR_BBF_SHIFT (25U) -/*! BBF - Bus Busy Flag - * 0b0..I2C Bus is idle - * 0b1..I2C Bus is busy - */ -#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) -/*! @} */ - -/*! @name MIER - Master Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_MIER_TDIE_MASK (0x1U) -#define LPI2C_MIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) -#define LPI2C_MIER_RDIE_MASK (0x2U) -#define LPI2C_MIER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) -#define LPI2C_MIER_EPIE_MASK (0x100U) -#define LPI2C_MIER_EPIE_SHIFT (8U) -/*! EPIE - End Packet Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) -#define LPI2C_MIER_SDIE_MASK (0x200U) -#define LPI2C_MIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) -#define LPI2C_MIER_NDIE_MASK (0x400U) -#define LPI2C_MIER_NDIE_SHIFT (10U) -/*! NDIE - NACK Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) -#define LPI2C_MIER_ALIE_MASK (0x800U) -#define LPI2C_MIER_ALIE_SHIFT (11U) -/*! ALIE - Arbitration Lost Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) -#define LPI2C_MIER_FEIE_MASK (0x1000U) -#define LPI2C_MIER_FEIE_SHIFT (12U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled - */ -#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) -#define LPI2C_MIER_PLTIE_MASK (0x2000U) -#define LPI2C_MIER_PLTIE_SHIFT (13U) -/*! PLTIE - Pin Low Timeout Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) -#define LPI2C_MIER_DMIE_MASK (0x4000U) -#define LPI2C_MIER_DMIE_SHIFT (14U) -/*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) -/*! @} */ - -/*! @name MDER - Master DMA Enable Register */ -/*! @{ */ -#define LPI2C_MDER_TDDE_MASK (0x1U) -#define LPI2C_MDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) -#define LPI2C_MDER_RDDE_MASK (0x2U) -#define LPI2C_MDER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) -/*! @} */ - -/*! @name MCFGR0 - Master Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCFGR0_HREN_MASK (0x1U) -#define LPI2C_MCFGR0_HREN_SHIFT (0U) -/*! HREN - Host Request Enable - * 0b0..Host request input is disabled - * 0b1..Host request input is enabled - */ -#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) -#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) -#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host Request Polarity - * 0b0..Active low - * 0b1..Active high - */ -#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) -#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) -#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host Request Select - * 0b0..Host request input is pin HREQ - * 0b1..Host request input is input trigger - */ -#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) -#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) -#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO Enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled - */ -#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) -#define LPI2C_MCFGR0_RDMO_MASK (0x200U) -#define LPI2C_MCFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive Data Match Only - * 0b0..Received data is stored in the receive FIFO - * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set - */ -#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) -/*! @} */ - -/*! @name MCFGR1 - Master Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) -#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) -/*! PRESCALE - Prescaler - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) -#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) -#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) -/*! AUTOSTOP - Automatic STOP Generation - * 0b0..No effect - * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy - */ -#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) -#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) -#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) -/*! IGNACK - IGNACK - * 0b0..LPI2C Master will receive ACK and NACK normally - * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK - */ -#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) -#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) -#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) -/*! TIMECFG - Timeout Configuration - * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout - * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout - */ -#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) -#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) -#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) -/*! MATCFG - Match Configuration - * 0b000..Match is disabled - * 0b001..Reserved - * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) - * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) - * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) - * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) - * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) - * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) - */ -#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) -#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) -#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) -/*! PINCFG - Pin Configuration - * 0b000..2-pin open drain mode - * 0b001..2-pin output only mode (ultra-fast mode) - * 0b010..2-pin push-pull mode - * 0b011..4-pin push-pull mode - * 0b100..2-pin open drain mode with separate LPI2C slave - * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave - * 0b110..2-pin push-pull mode with separate LPI2C slave - * 0b111..4-pin push-pull mode (inverted outputs) - */ -#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) -/*! @} */ - -/*! @name MCFGR2 - Master Configuration Register 2 */ -/*! @{ */ -#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) -#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) -#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) -#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) -#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name MCFGR3 - Master Configuration Register 3 */ -/*! @{ */ -#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) -#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) -#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) -/*! @} */ - -/*! @name MDMR - Master Data Match Register */ -/*! @{ */ -#define LPI2C_MDMR_MATCH0_MASK (0xFFU) -#define LPI2C_MDMR_MATCH0_SHIFT (0U) -#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) -#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) -#define LPI2C_MDMR_MATCH1_SHIFT (16U) -#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) -/*! @} */ - -/*! @name MCCR0 - Master Clock Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR0_CLKLO_SHIFT (0U) -#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) -#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR0_CLKHI_SHIFT (8U) -#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) -#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) -#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR0_DATAVD_SHIFT (24U) -#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) -/*! @} */ - -/*! @name MCCR1 - Master Clock Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR1_CLKLO_SHIFT (0U) -#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) -#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR1_CLKHI_SHIFT (8U) -#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) -#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) -#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR1_DATAVD_SHIFT (24U) -#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) -/*! @} */ - -/*! @name MFCR - Master FIFO Control Register */ -/*! @{ */ -#define LPI2C_MFCR_TXWATER_MASK (0x3U) -#define LPI2C_MFCR_TXWATER_SHIFT (0U) -#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) -#define LPI2C_MFCR_RXWATER_MASK (0x30000U) -#define LPI2C_MFCR_RXWATER_SHIFT (16U) -#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) -/*! @} */ - -/*! @name MFSR - Master FIFO Status Register */ -/*! @{ */ -#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) -#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) -#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) -#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) -#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) -#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name MTDR - Master Transmit Data Register */ -/*! @{ */ -#define LPI2C_MTDR_DATA_MASK (0xFFU) -#define LPI2C_MTDR_DATA_SHIFT (0U) -#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) -#define LPI2C_MTDR_CMD_MASK (0x700U) -#define LPI2C_MTDR_CMD_SHIFT (8U) -/*! CMD - Command Data - * 0b000..Transmit DATA[7:0] - * 0b001..Receive (DATA[7:0] + 1) bytes - * 0b010..Generate STOP condition - * 0b011..Receive and discard (DATA[7:0] + 1) bytes - * 0b100..Generate (repeated) START and transmit address in DATA[7:0] - * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. - * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode - * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. - */ -#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) -/*! @} */ - -/*! @name MRDR - Master Receive Data Register */ -/*! @{ */ -#define LPI2C_MRDR_DATA_MASK (0xFFU) -#define LPI2C_MRDR_DATA_SHIFT (0U) -#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) -#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty - */ -#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) -/*! @} */ - -/*! @name SCR - Slave Control Register */ -/*! @{ */ -#define LPI2C_SCR_SEN_MASK (0x1U) -#define LPI2C_SCR_SEN_SHIFT (0U) -/*! SEN - Slave Enable - * 0b0..I2C Slave mode is disabled - * 0b1..I2C Slave mode is enabled - */ -#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) -#define LPI2C_SCR_RST_MASK (0x2U) -#define LPI2C_SCR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Slave mode logic is not reset - * 0b1..Slave mode logic is reset - */ -#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) -#define LPI2C_SCR_FILTEN_MASK (0x10U) -#define LPI2C_SCR_FILTEN_SHIFT (4U) -/*! FILTEN - Filter Enable - * 0b0..Disable digital filter and output delay counter for slave mode - * 0b1..Enable digital filter and output delay counter for slave mode - */ -#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) -#define LPI2C_SCR_FILTDZ_MASK (0x20U) -#define LPI2C_SCR_FILTDZ_SHIFT (5U) -/*! FILTDZ - Filter Doze Enable - * 0b0..Filter remains enabled in Doze mode - * 0b1..Filter is disabled in Doze mode - */ -#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) -#define LPI2C_SCR_RTF_MASK (0x100U) -#define LPI2C_SCR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit Data Register is now empty - */ -#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) -#define LPI2C_SCR_RRF_MASK (0x200U) -#define LPI2C_SCR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive Data Register is now empty - */ -#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) -/*! @} */ - -/*! @name SSR - Slave Status Register */ -/*! @{ */ -#define LPI2C_SSR_TDF_MASK (0x1U) -#define LPI2C_SSR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data not requested - * 0b1..Transmit data is requested - */ -#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) -#define LPI2C_SSR_RDF_MASK (0x2U) -#define LPI2C_SSR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready - */ -#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) -#define LPI2C_SSR_AVF_MASK (0x4U) -#define LPI2C_SSR_AVF_SHIFT (2U) -/*! AVF - Address Valid Flag - * 0b0..Address Status Register is not valid - * 0b1..Address Status Register is valid - */ -#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) -#define LPI2C_SSR_TAF_MASK (0x8U) -#define LPI2C_SSR_TAF_SHIFT (3U) -/*! TAF - Transmit ACK Flag - * 0b0..Transmit ACK/NACK is not required - * 0b1..Transmit ACK/NACK is required - */ -#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) -#define LPI2C_SSR_RSF_MASK (0x100U) -#define LPI2C_SSR_RSF_SHIFT (8U) -/*! RSF - Repeated Start Flag - * 0b0..Slave has not detected a Repeated START condition - * 0b1..Slave has detected a Repeated START condition - */ -#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) -#define LPI2C_SSR_SDF_MASK (0x200U) -#define LPI2C_SSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Slave has not detected a STOP condition - * 0b1..Slave has detected a STOP condition - */ -#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) -#define LPI2C_SSR_BEF_MASK (0x400U) -#define LPI2C_SSR_BEF_SHIFT (10U) -/*! BEF - Bit Error Flag - * 0b0..Slave has not detected a bit error - * 0b1..Slave has detected a bit error - */ -#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) -#define LPI2C_SSR_FEF_MASK (0x800U) -#define LPI2C_SSR_FEF_SHIFT (11U) -/*! FEF - FIFO Error Flag - * 0b0..FIFO underflow or overflow was not detected - * 0b1..FIFO underflow or overflow was detected - */ -#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) -#define LPI2C_SSR_AM0F_MASK (0x1000U) -#define LPI2C_SSR_AM0F_SHIFT (12U) -/*! AM0F - Address Match 0 Flag - * 0b0..Have not received an ADDR0 matching address - * 0b1..Have received an ADDR0 matching address - */ -#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) -#define LPI2C_SSR_AM1F_MASK (0x2000U) -#define LPI2C_SSR_AM1F_SHIFT (13U) -/*! AM1F - Address Match 1 Flag - * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address - * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address - */ -#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) -#define LPI2C_SSR_GCF_MASK (0x4000U) -#define LPI2C_SSR_GCF_SHIFT (14U) -/*! GCF - General Call Flag - * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled - * 0b1..Slave has detected the General Call Address - */ -#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) -#define LPI2C_SSR_SARF_MASK (0x8000U) -#define LPI2C_SSR_SARF_SHIFT (15U) -/*! SARF - SMBus Alert Response Flag - * 0b0..SMBus Alert Response is disabled or not detected - * 0b1..SMBus Alert Response is enabled and detected - */ -#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) -#define LPI2C_SSR_SBF_MASK (0x1000000U) -#define LPI2C_SSR_SBF_SHIFT (24U) -/*! SBF - Slave Busy Flag - * 0b0..I2C Slave is idle - * 0b1..I2C Slave is busy - */ -#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) -#define LPI2C_SSR_BBF_MASK (0x2000000U) -#define LPI2C_SSR_BBF_SHIFT (25U) -/*! BBF - Bus Busy Flag - * 0b0..I2C Bus is idle - * 0b1..I2C Bus is busy - */ -#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) -/*! @} */ - -/*! @name SIER - Slave Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_SIER_TDIE_MASK (0x1U) -#define LPI2C_SIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) -#define LPI2C_SIER_RDIE_MASK (0x2U) -#define LPI2C_SIER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) -#define LPI2C_SIER_AVIE_MASK (0x4U) -#define LPI2C_SIER_AVIE_SHIFT (2U) -/*! AVIE - Address Valid Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) -#define LPI2C_SIER_TAIE_MASK (0x8U) -#define LPI2C_SIER_TAIE_SHIFT (3U) -/*! TAIE - Transmit ACK Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) -#define LPI2C_SIER_RSIE_MASK (0x100U) -#define LPI2C_SIER_RSIE_SHIFT (8U) -/*! RSIE - Repeated Start Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) -#define LPI2C_SIER_SDIE_MASK (0x200U) -#define LPI2C_SIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) -#define LPI2C_SIER_BEIE_MASK (0x400U) -#define LPI2C_SIER_BEIE_SHIFT (10U) -/*! BEIE - Bit Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) -#define LPI2C_SIER_FEIE_MASK (0x800U) -#define LPI2C_SIER_FEIE_SHIFT (11U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) -#define LPI2C_SIER_AM0IE_MASK (0x1000U) -#define LPI2C_SIER_AM0IE_SHIFT (12U) -/*! AM0IE - Address Match 0 Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled - */ -#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) -#define LPI2C_SIER_AM1F_MASK (0x2000U) -#define LPI2C_SIER_AM1F_SHIFT (13U) -/*! AM1F - Address Match 1 Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) -#define LPI2C_SIER_GCIE_MASK (0x4000U) -#define LPI2C_SIER_GCIE_SHIFT (14U) -/*! GCIE - General Call Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) -#define LPI2C_SIER_SARIE_MASK (0x8000U) -#define LPI2C_SIER_SARIE_SHIFT (15U) -/*! SARIE - SMBus Alert Response Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) -/*! @} */ - -/*! @name SDER - Slave DMA Enable Register */ -/*! @{ */ -#define LPI2C_SDER_TDDE_MASK (0x1U) -#define LPI2C_SDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) -#define LPI2C_SDER_RDDE_MASK (0x2U) -#define LPI2C_SDER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) -#define LPI2C_SDER_AVDE_MASK (0x4U) -#define LPI2C_SDER_AVDE_SHIFT (2U) -/*! AVDE - Address Valid DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) -/*! @} */ - -/*! @name SCFGR1 - Slave Configuration Register 1 */ -/*! @{ */ -#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) -#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) -/*! ADRSTALL - Address SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) -#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) -#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) -/*! RXSTALL - RX SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) -#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) -#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) -/*! TXDSTALL - TX Data SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) -#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) -#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) -/*! ACKSTALL - ACK SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) -#define LPI2C_SCFGR1_GCEN_MASK (0x100U) -#define LPI2C_SCFGR1_GCEN_SHIFT (8U) -/*! GCEN - General Call Enable - * 0b0..General Call address is disabled - * 0b1..General Call address is enabled - */ -#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) -#define LPI2C_SCFGR1_SAEN_MASK (0x200U) -#define LPI2C_SCFGR1_SAEN_SHIFT (9U) -/*! SAEN - SMBus Alert Enable - * 0b0..Disables match on SMBus Alert - * 0b1..Enables match on SMBus Alert - */ -#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) -#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) -#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) -/*! TXCFG - Transmit Flag Configuration - * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty - * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty - */ -#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) -#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) -#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) -/*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). - */ -#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) -#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) -#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) -/*! IGNACK - Ignore NACK - * 0b0..Slave will end transfer when NACK is detected - * 0b1..Slave will not end transfer when NACK detected - */ -#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) -#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) -#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) -/*! HSMEN - High Speed Mode Enable - * 0b0..Disables detection of HS-mode master code - * 0b1..Enables detection of HS-mode master code - */ -#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) -#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) -#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) -/*! ADDRCFG - Address Configuration - * 0b000..Address match 0 (7-bit) - * 0b001..Address match 0 (10-bit) - * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) - * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) - * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) - * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) - * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) - * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) - */ -#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) -/*! @} */ - -/*! @name SCFGR2 - Slave Configuration Register 2 */ -/*! @{ */ -#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) -#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) -#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) -#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) -#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) -#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) -#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) -#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name SAMR - Slave Address Match Register */ -/*! @{ */ -#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) -#define LPI2C_SAMR_ADDR0_SHIFT (1U) -#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) -#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) -#define LPI2C_SAMR_ADDR1_SHIFT (17U) -#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) -/*! @} */ - -/*! @name SASR - Slave Address Status Register */ -/*! @{ */ -#define LPI2C_SASR_RADDR_MASK (0x7FFU) -#define LPI2C_SASR_RADDR_SHIFT (0U) -#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) -#define LPI2C_SASR_ANV_MASK (0x4000U) -#define LPI2C_SASR_ANV_SHIFT (14U) -/*! ANV - Address Not Valid - * 0b0..Received Address (RADDR) is valid - * 0b1..Received Address (RADDR) is not valid - */ -#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) -/*! @} */ - -/*! @name STAR - Slave Transmit ACK Register */ -/*! @{ */ -#define LPI2C_STAR_TXNACK_MASK (0x1U) -#define LPI2C_STAR_TXNACK_SHIFT (0U) -/*! TXNACK - Transmit NACK - * 0b0..Write a Transmit ACK for each received word - * 0b1..Write a Transmit NACK for each received word - */ -#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) -/*! @} */ - -/*! @name STDR - Slave Transmit Data Register */ -/*! @{ */ -#define LPI2C_STDR_DATA_MASK (0xFFU) -#define LPI2C_STDR_DATA_SHIFT (0U) -#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) -/*! @} */ - -/*! @name SRDR - Slave Receive Data Register */ -/*! @{ */ -#define LPI2C_SRDR_DATA_MASK (0xFFU) -#define LPI2C_SRDR_DATA_SHIFT (0U) -#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) -#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty - */ -#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) -#define LPI2C_SRDR_SOF_MASK (0x8000U) -#define LPI2C_SRDR_SOF_SHIFT (15U) -/*! SOF - Start Of Frame - * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition - * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition - */ -#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPI2C_Register_Masks */ - - -/* LPI2C - Peripheral instance base addresses */ -/** Peripheral LPI2C0 base address */ -#define LPI2C0_BASE (0x4003A000u) -/** Peripheral LPI2C0 base pointer */ -#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) -/** Peripheral LPI2C1 base address */ -#define LPI2C1_BASE (0x4003B000u) -/** Peripheral LPI2C1 base pointer */ -#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) -/** Peripheral LPI2C2 base address */ -#define LPI2C2_BASE (0x4003C000u) -/** Peripheral LPI2C2 base pointer */ -#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) -/** Peripheral LPI2C3 base address */ -#define LPI2C3_BASE (0x4102E000u) -/** Peripheral LPI2C3 base pointer */ -#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) -/** Array initializer of LPI2C peripheral base addresses */ -#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } -/** Array initializer of LPI2C peripheral base pointers */ -#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } -/** Interrupt vectors for the LPI2C peripheral type */ -#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } - -/*! - * @} - */ /* end of group LPI2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer - * @{ - */ - -/** LPIT - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ - __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ - __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ - __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ - __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - struct { /* offset: 0x20, array step: 0x10 */ - __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[4]; -} LPIT_Type; - -/* ---------------------------------------------------------------------------- - -- LPIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPIT_Register_Masks LPIT Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPIT_VERID_FEATURE_MASK (0xFFFFU) -#define LPIT_VERID_FEATURE_SHIFT (0U) -#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) -#define LPIT_VERID_MINOR_MASK (0xFF0000U) -#define LPIT_VERID_MINOR_SHIFT (16U) -#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) -#define LPIT_VERID_MAJOR_MASK (0xFF000000U) -#define LPIT_VERID_MAJOR_SHIFT (24U) -#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPIT_PARAM_CHANNEL_MASK (0xFFU) -#define LPIT_PARAM_CHANNEL_SHIFT (0U) -#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) -#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) -#define LPIT_PARAM_EXT_TRIG_SHIFT (8U) -#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) -/*! @} */ - -/*! @name MCR - Module Control Register */ -/*! @{ */ -#define LPIT_MCR_M_CEN_MASK (0x1U) -#define LPIT_MCR_M_CEN_SHIFT (0U) -/*! M_CEN - Module Clock Enable - * 0b0..Disable peripheral clock to timers - * 0b1..Enable peripheral clock to timers - */ -#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) -#define LPIT_MCR_SW_RST_MASK (0x2U) -#define LPIT_MCR_SW_RST_SHIFT (1U) -/*! SW_RST - Software Reset Bit - * 0b0..Timer channels and registers are not reset - * 0b1..Reset timer channels and registers - */ -#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) -#define LPIT_MCR_DOZE_EN_MASK (0x4U) -#define LPIT_MCR_DOZE_EN_SHIFT (2U) -/*! DOZE_EN - DOZE Mode Enable Bit - * 0b0..Stop timer channels in DOZE mode - * 0b1..Allow timer channels to continue to run in DOZE mode - */ -#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) -#define LPIT_MCR_DBG_EN_MASK (0x8U) -#define LPIT_MCR_DBG_EN_SHIFT (3U) -/*! DBG_EN - Debug Enable Bit - * 0b0..Stop timer channels in Debug mode - * 0b1..Allow timer channels to continue to run in Debug mode - */ -#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) -/*! @} */ - -/*! @name MSR - Module Status Register */ -/*! @{ */ -#define LPIT_MSR_TIF0_MASK (0x1U) -#define LPIT_MSR_TIF0_SHIFT (0U) -/*! TIF0 - Channel 0 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) -#define LPIT_MSR_TIF1_MASK (0x2U) -#define LPIT_MSR_TIF1_SHIFT (1U) -/*! TIF1 - Channel 1 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) -#define LPIT_MSR_TIF2_MASK (0x4U) -#define LPIT_MSR_TIF2_SHIFT (2U) -/*! TIF2 - Channel 2 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) -#define LPIT_MSR_TIF3_MASK (0x8U) -#define LPIT_MSR_TIF3_SHIFT (3U) -/*! TIF3 - Channel 3 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) -/*! @} */ - -/*! @name MIER - Module Interrupt Enable Register */ -/*! @{ */ -#define LPIT_MIER_TIE0_MASK (0x1U) -#define LPIT_MIER_TIE0_SHIFT (0U) -/*! TIE0 - Channel 0 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) -#define LPIT_MIER_TIE1_MASK (0x2U) -#define LPIT_MIER_TIE1_SHIFT (1U) -/*! TIE1 - Channel 1 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) -#define LPIT_MIER_TIE2_MASK (0x4U) -#define LPIT_MIER_TIE2_SHIFT (2U) -/*! TIE2 - Channel 2 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) -#define LPIT_MIER_TIE3_MASK (0x8U) -#define LPIT_MIER_TIE3_SHIFT (3U) -/*! TIE3 - Channel 3 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) -/*! @} */ - -/*! @name SETTEN - Set Timer Enable Register */ -/*! @{ */ -#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) -#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) -/*! SET_T_EN_0 - Set Timer 0 Enable - * 0b0..No effect - * 0b1..Enables Timer Channel 0 - */ -#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) -#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) -#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) -/*! SET_T_EN_1 - Set Timer 1 Enable - * 0b0..No Effect - * 0b1..Enables Timer Channel 1 - */ -#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) -#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) -#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) -/*! SET_T_EN_2 - Set Timer 2 Enable - * 0b0..No Effect - * 0b1..Enables Timer Channel 2 - */ -#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) -#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) -#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) -/*! SET_T_EN_3 - Set Timer 3 Enable - * 0b0..No effect - * 0b1..Enables Timer Channel 3 - */ -#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) -/*! @} */ - -/*! @name CLRTEN - Clear Timer Enable Register */ -/*! @{ */ -#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) -#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) -/*! CLR_T_EN_0 - Clear Timer 0 Enable - * 0b0..No action - * 0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 - */ -#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) -#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) -#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) -/*! CLR_T_EN_1 - Clear Timer 1 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 - */ -#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) -#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) -#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) -/*! CLR_T_EN_2 - Clear Timer 2 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 - */ -#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) -#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) -#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) -/*! CLR_T_EN_3 - Clear Timer 3 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 - */ -#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) -/*! @} */ - -/*! @name TVAL - Timer Value Register */ -/*! @{ */ -#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) -#define LPIT_TVAL_TMR_VAL_SHIFT (0U) -/*! TMR_VAL - Timer Value - * 0b00000000000000000000000000000000..Invalid load value in compare mode - * 0b00000000000000000000000000000001..Invalid load value in compare mode - * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer - */ -#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) -/*! @} */ - -/* The count of LPIT_TVAL */ -#define LPIT_TVAL_COUNT (4U) - -/*! @name CVAL - Current Timer Value */ -/*! @{ */ -#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) -#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) -#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) -/*! @} */ - -/* The count of LPIT_CVAL */ -#define LPIT_CVAL_COUNT (4U) - -/*! @name TCTRL - Timer Control Register */ -/*! @{ */ -#define LPIT_TCTRL_T_EN_MASK (0x1U) -#define LPIT_TCTRL_T_EN_SHIFT (0U) -/*! T_EN - Timer Enable - * 0b0..Timer Channel is disabled - * 0b1..Timer Channel is enabled - */ -#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) -#define LPIT_TCTRL_CHAIN_MASK (0x2U) -#define LPIT_TCTRL_CHAIN_SHIFT (1U) -/*! CHAIN - Chain Channel - * 0b0..Channel Chaining is disabled. The channel timer runs independently. - * 0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout. - */ -#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) -#define LPIT_TCTRL_MODE_MASK (0xCU) -#define LPIT_TCTRL_MODE_SHIFT (2U) -/*! MODE - Timer Operation Mode - * 0b00..32-bit Periodic Counter - * 0b01..Dual 16-bit Periodic Counter - * 0b10..32-bit Trigger Accumulator - * 0b11..32-bit Trigger Input Capture - */ -#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) -#define LPIT_TCTRL_TSOT_MASK (0x10000U) -#define LPIT_TCTRL_TSOT_SHIFT (16U) -/*! TSOT - Timer Start On Trigger - * 0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) - * 0b1..Timer starts to decrement when a rising edge on a selected trigger is detected - */ -#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) -#define LPIT_TCTRL_TSOI_MASK (0x20000U) -#define LPIT_TCTRL_TSOI_SHIFT (17U) -/*! TSOI - Timer Stop On Interrupt - * 0b0..The channel timer does not stop after timeout - * 0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. - */ -#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) -#define LPIT_TCTRL_TROT_MASK (0x40000U) -#define LPIT_TCTRL_TROT_SHIFT (18U) -/*! TROT - Timer Reload On Trigger - * 0b0..Timer will not reload on the selected trigger - * 0b1..Timer will reload on the selected trigger - */ -#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) -#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) -#define LPIT_TCTRL_TRG_SRC_SHIFT (23U) -/*! TRG_SRC - Trigger Source - * 0b0..Selects external triggers - * 0b1..Selects internal triggers - */ -#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) -#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) -#define LPIT_TCTRL_TRG_SEL_SHIFT (24U) -/*! TRG_SEL - Trigger Select - * 0b0000-0b0011..Timer channel 0 - 3 trigger source is selected - * 0b0100-0b1111..Reserved - */ -#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) -/*! @} */ - -/* The count of LPIT_TCTRL */ -#define LPIT_TCTRL_COUNT (4U) - - -/*! - * @} - */ /* end of group LPIT_Register_Masks */ - - -/* LPIT - Peripheral instance base addresses */ -/** Peripheral LPIT0 base address */ -#define LPIT0_BASE (0x40030000u) -/** Peripheral LPIT0 base pointer */ -#define LPIT0 ((LPIT_Type *)LPIT0_BASE) -/** Peripheral LPIT1 base address */ -#define LPIT1_BASE (0x4102A000u) -/** Peripheral LPIT1 base pointer */ -#define LPIT1 ((LPIT_Type *)LPIT1_BASE) -/** Array initializer of LPIT peripheral base addresses */ -#define LPIT_BASE_ADDRS { LPIT0_BASE, LPIT1_BASE } -/** Array initializer of LPIT peripheral base pointers */ -#define LPIT_BASE_PTRS { LPIT0, LPIT1 } -/** Interrupt vectors for the LPIT peripheral type */ -#define LPIT_IRQS { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }, { LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn } } - -/*! - * @} - */ /* end of group LPIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPSPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer - * @{ - */ - -/** LPSPI - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ - __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ - __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ - uint8_t RESERVED_3[20]; - __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ - __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ - __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ - __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ - uint8_t RESERVED_4[8]; - __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ - __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ -} LPSPI_Type; - -/* ---------------------------------------------------------------------------- - -- LPSPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Register_Masks LPSPI Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) -#define LPSPI_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Module Identification Number - * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. - */ -#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) -#define LPSPI_VERID_MINOR_MASK (0xFF0000U) -#define LPSPI_VERID_MINOR_SHIFT (16U) -#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) -#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) -#define LPSPI_VERID_MAJOR_SHIFT (24U) -#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) -#define LPSPI_PARAM_TXFIFO_SHIFT (0U) -#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) -#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) -#define LPSPI_PARAM_RXFIFO_SHIFT (8U) -#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define LPSPI_CR_MEN_MASK (0x1U) -#define LPSPI_CR_MEN_SHIFT (0U) -/*! MEN - Module Enable - * 0b0..Module is disabled - * 0b1..Module is enabled - */ -#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) -#define LPSPI_CR_RST_MASK (0x2U) -#define LPSPI_CR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Master logic is not reset - * 0b1..Master logic is reset - */ -#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) -#define LPSPI_CR_DOZEN_MASK (0x4U) -#define LPSPI_CR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Module is enabled in Doze mode - * 0b1..Module is disabled in Doze mode - */ -#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) -#define LPSPI_CR_DBGEN_MASK (0x8U) -#define LPSPI_CR_DBGEN_SHIFT (3U) -/*! DBGEN - Debug Enable - * 0b0..Module is disabled in debug mode - * 0b1..Module is enabled in debug mode - */ -#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) -#define LPSPI_CR_RTF_MASK (0x100U) -#define LPSPI_CR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit FIFO is reset - */ -#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) -#define LPSPI_CR_RRF_MASK (0x200U) -#define LPSPI_CR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive FIFO is reset - */ -#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ -#define LPSPI_SR_TDF_MASK (0x1U) -#define LPSPI_SR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data not requested - * 0b1..Transmit data is requested - */ -#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) -#define LPSPI_SR_RDF_MASK (0x2U) -#define LPSPI_SR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive Data is not ready - * 0b1..Receive data is ready - */ -#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) -#define LPSPI_SR_WCF_MASK (0x100U) -#define LPSPI_SR_WCF_SHIFT (8U) -/*! WCF - Word Complete Flag - * 0b0..Transfer of a received word has not yet completed - * 0b1..Transfer of a received word has completed - */ -#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) -#define LPSPI_SR_FCF_MASK (0x200U) -#define LPSPI_SR_FCF_SHIFT (9U) -/*! FCF - Frame Complete Flag - * 0b0..Frame transfer has not completed - * 0b1..Frame transfer has completed - */ -#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) -#define LPSPI_SR_TCF_MASK (0x400U) -#define LPSPI_SR_TCF_SHIFT (10U) -/*! TCF - Transfer Complete Flag - * 0b0..All transfers have not completed - * 0b1..All transfers have completed - */ -#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) -#define LPSPI_SR_TEF_MASK (0x800U) -#define LPSPI_SR_TEF_SHIFT (11U) -/*! TEF - Transmit Error Flag - * 0b0..Transmit FIFO underrun has not occurred - * 0b1..Transmit FIFO underrun has occurred - */ -#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) -#define LPSPI_SR_REF_MASK (0x1000U) -#define LPSPI_SR_REF_SHIFT (12U) -/*! REF - Receive Error Flag - * 0b0..Receive FIFO has not overflowed - * 0b1..Receive FIFO has overflowed - */ -#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) -#define LPSPI_SR_DMF_MASK (0x2000U) -#define LPSPI_SR_DMF_SHIFT (13U) -/*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data - */ -#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) -#define LPSPI_SR_MBF_MASK (0x1000000U) -#define LPSPI_SR_MBF_SHIFT (24U) -/*! MBF - Module Busy Flag - * 0b0..LPSPI is idle - * 0b1..LPSPI is busy - */ -#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ -#define LPSPI_IER_TDIE_MASK (0x1U) -#define LPSPI_IER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) -#define LPSPI_IER_RDIE_MASK (0x2U) -#define LPSPI_IER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) -#define LPSPI_IER_WCIE_MASK (0x100U) -#define LPSPI_IER_WCIE_SHIFT (8U) -/*! WCIE - Word Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) -#define LPSPI_IER_FCIE_MASK (0x200U) -#define LPSPI_IER_FCIE_SHIFT (9U) -/*! FCIE - Frame Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) -#define LPSPI_IER_TCIE_MASK (0x400U) -#define LPSPI_IER_TCIE_SHIFT (10U) -/*! TCIE - Transfer Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) -#define LPSPI_IER_TEIE_MASK (0x800U) -#define LPSPI_IER_TEIE_SHIFT (11U) -/*! TEIE - Transmit Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) -#define LPSPI_IER_REIE_MASK (0x1000U) -#define LPSPI_IER_REIE_SHIFT (12U) -/*! REIE - Receive Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) -#define LPSPI_IER_DMIE_MASK (0x2000U) -#define LPSPI_IER_DMIE_SHIFT (13U) -/*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) -/*! @} */ - -/*! @name DER - DMA Enable Register */ -/*! @{ */ -#define LPSPI_DER_TDDE_MASK (0x1U) -#define LPSPI_DER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) -#define LPSPI_DER_RDDE_MASK (0x2U) -#define LPSPI_DER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) -/*! @} */ - -/*! @name CFGR0 - Configuration Register 0 */ -/*! @{ */ -#define LPSPI_CFGR0_HREN_MASK (0x1U) -#define LPSPI_CFGR0_HREN_SHIFT (0U) -/*! HREN - Host Request Enable - * 0b0..Host request is disabled - * 0b1..Host request is enabled - */ -#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) -#define LPSPI_CFGR0_HRPOL_MASK (0x2U) -#define LPSPI_CFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host Request Polarity - * 0b0..Active low - * 0b1..Active high - */ -#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) -#define LPSPI_CFGR0_HRSEL_MASK (0x4U) -#define LPSPI_CFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host Request Select - * 0b0..Host request input is the LPSPI_HREQ pin - * 0b1..Host request input is the input trigger - */ -#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) -#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) -#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO Enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled - */ -#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) -#define LPSPI_CFGR0_RDMO_MASK (0x200U) -#define LPSPI_CFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive Data Match Only - * 0b0..Received data is stored in the receive FIFO as in normal operations - * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set - */ -#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) -/*! @} */ - -/*! @name CFGR1 - Configuration Register 1 */ -/*! @{ */ -#define LPSPI_CFGR1_MASTER_MASK (0x1U) -#define LPSPI_CFGR1_MASTER_SHIFT (0U) -/*! MASTER - Master Mode - * 0b0..Slave mode - * 0b1..Master mode - */ -#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) -#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) -#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) -/*! SAMPLE - Sample Point - * 0b0..Input data is sampled on SCK edge - * 0b1..Input data is sampled on delayed SCK edge - */ -#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) -#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) -#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) -/*! AUTOPCS - Automatic PCS - * 0b0..Automatic PCS generation is disabled - * 0b1..Automatic PCS generation is enabled - */ -#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) -#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) -#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) -/*! NOSTALL - No Stall - * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full - * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur - */ -#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) -#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) -#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) -/*! PCSPOL - Peripheral Chip Select Polarity - * 0b0000..The Peripheral Chip Select pin PCSx is active low - * 0b0001..The Peripheral Chip Select pin PCSx is active high - */ -#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) -#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) -#define LPSPI_CFGR1_MATCFG_SHIFT (16U) -/*! MATCFG - Match Configuration - * 0b000..Match is disabled - * 0b001..Reserved - * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) - * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) - * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] - * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] - * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] - * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] - */ -#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) -#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) -#define LPSPI_CFGR1_PINCFG_SHIFT (24U) -/*! PINCFG - Pin Configuration - * 0b00..SIN is used for input data and SOUT is used for output data - * 0b01..SIN is used for both input and output data - * 0b10..SOUT is used for both input and output data - * 0b11..SOUT is used for input data and SIN is used for output data - */ -#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) -#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) -#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) -/*! OUTCFG - Output Config - * 0b0..Output data retains last value when chip select is negated - * 0b1..Output data is tristated when chip select is negated - */ -#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) -#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) -#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) -/*! PCSCFG - Peripheral Chip Select Configuration - * 0b0..PCS[3:2] are enabled - * 0b1..PCS[3:2] are disabled - */ -#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) -/*! @} */ - -/*! @name DMR0 - Data Match Register 0 */ -/*! @{ */ -#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) -#define LPSPI_DMR0_MATCH0_SHIFT (0U) -#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) -/*! @} */ - -/*! @name DMR1 - Data Match Register 1 */ -/*! @{ */ -#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) -#define LPSPI_DMR1_MATCH1_SHIFT (0U) -#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) -/*! @} */ - -/*! @name CCR - Clock Configuration Register */ -/*! @{ */ -#define LPSPI_CCR_SCKDIV_MASK (0xFFU) -#define LPSPI_CCR_SCKDIV_SHIFT (0U) -#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) -#define LPSPI_CCR_DBT_MASK (0xFF00U) -#define LPSPI_CCR_DBT_SHIFT (8U) -#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) -#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) -#define LPSPI_CCR_PCSSCK_SHIFT (16U) -#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) -#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) -#define LPSPI_CCR_SCKPCS_SHIFT (24U) -#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) -/*! @} */ - -/*! @name FCR - FIFO Control Register */ -/*! @{ */ -#define LPSPI_FCR_TXWATER_MASK (0x3U) -#define LPSPI_FCR_TXWATER_SHIFT (0U) -#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) -#define LPSPI_FCR_RXWATER_MASK (0x30000U) -#define LPSPI_FCR_RXWATER_SHIFT (16U) -#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ -#define LPSPI_FSR_TXCOUNT_MASK (0x7U) -#define LPSPI_FSR_TXCOUNT_SHIFT (0U) -#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) -#define LPSPI_FSR_RXCOUNT_MASK (0x70000U) -#define LPSPI_FSR_RXCOUNT_SHIFT (16U) -#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name TCR - Transmit Command Register */ -/*! @{ */ -#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) -#define LPSPI_TCR_FRAMESZ_SHIFT (0U) -#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) -#define LPSPI_TCR_WIDTH_MASK (0x30000U) -#define LPSPI_TCR_WIDTH_SHIFT (16U) -/*! WIDTH - Transfer Width - * 0b00..1 bit transfer - * 0b01..2 bit transfer - * 0b10..4 bit transfer - * 0b11..Reserved - */ -#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) -#define LPSPI_TCR_TXMSK_MASK (0x40000U) -#define LPSPI_TCR_TXMSK_SHIFT (18U) -/*! TXMSK - Transmit Data Mask - * 0b0..Normal transfer - * 0b1..Mask transmit data - */ -#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) -#define LPSPI_TCR_RXMSK_MASK (0x80000U) -#define LPSPI_TCR_RXMSK_SHIFT (19U) -/*! RXMSK - Receive Data Mask - * 0b0..Normal transfer - * 0b1..Receive data is masked - */ -#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) -#define LPSPI_TCR_CONTC_MASK (0x100000U) -#define LPSPI_TCR_CONTC_SHIFT (20U) -/*! CONTC - Continuing Command - * 0b0..Command word for start of new transfer - * 0b1..Command word for continuing transfer - */ -#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) -#define LPSPI_TCR_CONT_MASK (0x200000U) -#define LPSPI_TCR_CONT_SHIFT (21U) -/*! CONT - Continuous Transfer - * 0b0..Continuous transfer is disabled - * 0b1..Continuous transfer is enabled - */ -#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) -#define LPSPI_TCR_BYSW_MASK (0x400000U) -#define LPSPI_TCR_BYSW_SHIFT (22U) -/*! BYSW - Byte Swap - * 0b0..Byte swap is disabled - * 0b1..Byte swap is enabled - */ -#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) -#define LPSPI_TCR_LSBF_MASK (0x800000U) -#define LPSPI_TCR_LSBF_SHIFT (23U) -/*! LSBF - LSB First - * 0b0..Data is transferred MSB first - * 0b1..Data is transferred LSB first - */ -#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) -#define LPSPI_TCR_PCS_MASK (0x3000000U) -#define LPSPI_TCR_PCS_SHIFT (24U) -/*! PCS - Peripheral Chip Select - * 0b00..Transfer using LPSPI_PCS[0] - * 0b01..Transfer using LPSPI_PCS[1] - * 0b10..Transfer using LPSPI_PCS[2] - * 0b11..Transfer using LPSPI_PCS[3] - */ -#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) -#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) -#define LPSPI_TCR_PRESCALE_SHIFT (27U) -/*! PRESCALE - Prescaler Value - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) -#define LPSPI_TCR_CPHA_MASK (0x40000000U) -#define LPSPI_TCR_CPHA_SHIFT (30U) -/*! CPHA - Clock Phase - * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK - * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK - */ -#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) -#define LPSPI_TCR_CPOL_MASK (0x80000000U) -#define LPSPI_TCR_CPOL_SHIFT (31U) -/*! CPOL - Clock Polarity - * 0b0..The inactive state value of SCK is low - * 0b1..The inactive state value of SCK is high - */ -#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) -/*! @} */ - -/*! @name TDR - Transmit Data Register */ -/*! @{ */ -#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_TDR_DATA_SHIFT (0U) -#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) -/*! @} */ - -/*! @name RSR - Receive Status Register */ -/*! @{ */ -#define LPSPI_RSR_SOF_MASK (0x1U) -#define LPSPI_RSR_SOF_SHIFT (0U) -/*! SOF - Start Of Frame - * 0b0..Subsequent data word received after LPSPI_PCS assertion - * 0b1..First data word received after LPSPI_PCS assertion - */ -#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) -#define LPSPI_RSR_RXEMPTY_MASK (0x2U) -#define LPSPI_RSR_RXEMPTY_SHIFT (1U) -/*! RXEMPTY - RX FIFO Empty - * 0b0..RX FIFO is not empty - * 0b1..RX FIFO is empty - */ -#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) -/*! @} */ - -/*! @name RDR - Receive Data Register */ -/*! @{ */ -#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_RDR_DATA_SHIFT (0U) -#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPSPI_Register_Masks */ - - -/* LPSPI - Peripheral instance base addresses */ -/** Peripheral LPSPI0 base address */ -#define LPSPI0_BASE (0x4003F000u) -/** Peripheral LPSPI0 base pointer */ -#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) -/** Peripheral LPSPI1 base address */ -#define LPSPI1_BASE (0x40040000u) -/** Peripheral LPSPI1 base pointer */ -#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) -/** Peripheral LPSPI2 base address */ -#define LPSPI2_BASE (0x40041000u) -/** Peripheral LPSPI2 base pointer */ -#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) -/** Peripheral LPSPI3 base address */ -#define LPSPI3_BASE (0x41035000u) -/** Peripheral LPSPI3 base pointer */ -#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) -/** Array initializer of LPSPI peripheral base addresses */ -#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE } -/** Array initializer of LPSPI peripheral base pointers */ -#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3 } -/** Interrupt vectors for the LPSPI peripheral type */ -#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn } - -/*! - * @} - */ /* end of group LPSPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer - * @{ - */ - -/** LPTMR - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ - __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ - __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ - __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ -} LPTMR_Type; - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/*! @name CSR - Low Power Timer Control Status Register */ -/*! @{ */ -#define LPTMR_CSR_TEN_MASK (0x1U) -#define LPTMR_CSR_TEN_SHIFT (0U) -/*! TEN - Timer Enable - * 0b0..LPTMR is disabled and internal logic is reset. - * 0b1..LPTMR is enabled. - */ -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) -#define LPTMR_CSR_TMS_MASK (0x2U) -#define LPTMR_CSR_TMS_SHIFT (1U) -/*! TMS - Timer Mode Select - * 0b0..Time Counter mode. - * 0b1..Pulse Counter mode. - */ -#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) -#define LPTMR_CSR_TFC_MASK (0x4U) -#define LPTMR_CSR_TFC_SHIFT (2U) -/*! TFC - Timer Free-Running Counter - * 0b0..CNR is reset whenever TCF is set. - * 0b1..CNR is reset on overflow. - */ -#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) -#define LPTMR_CSR_TPP_MASK (0x8U) -#define LPTMR_CSR_TPP_SHIFT (3U) -/*! TPP - Timer Pin Polarity - * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. - * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. - */ -#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) -#define LPTMR_CSR_TPS_MASK (0x30U) -#define LPTMR_CSR_TPS_SHIFT (4U) -/*! TPS - Timer Pin Select - * 0b00..Pulse counter input 0 is selected. - * 0b01..Pulse counter input 1 is selected. - * 0b10..Pulse counter input 2 is selected. - * 0b11..Pulse counter input 3 is selected. - */ -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) -#define LPTMR_CSR_TIE_MASK (0x40U) -#define LPTMR_CSR_TIE_SHIFT (6U) -/*! TIE - Timer Interrupt Enable - * 0b0..Timer interrupt disabled. - * 0b1..Timer interrupt enabled. - */ -#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) -#define LPTMR_CSR_TCF_MASK (0x80U) -#define LPTMR_CSR_TCF_SHIFT (7U) -/*! TCF - Timer Compare Flag - * 0b0..The value of CNR is not equal to CMR and increments. - * 0b1..The value of CNR is equal to CMR and increments. - */ -#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) -#define LPTMR_CSR_TDRE_MASK (0x100U) -#define LPTMR_CSR_TDRE_SHIFT (8U) -/*! TDRE - Timer DMA Request Enable - * 0b0..Timer DMA Request disabled. - * 0b1..Timer DMA Request enabled. - */ -#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) -/*! @} */ - -/*! @name PSR - Low Power Timer Prescale Register */ -/*! @{ */ -#define LPTMR_PSR_PCS_MASK (0x3U) -#define LPTMR_PSR_PCS_SHIFT (0U) -/*! PCS - Prescaler Clock Select - * 0b00..Prescaler/glitch filter clock 0 selected. - * 0b01..Prescaler/glitch filter clock 1 selected. - * 0b10..Prescaler/glitch filter clock 2 selected. - * 0b11..Prescaler/glitch filter clock 3 selected. - */ -#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) -#define LPTMR_PSR_PBYP_MASK (0x4U) -#define LPTMR_PSR_PBYP_SHIFT (2U) -/*! PBYP - Prescaler Bypass - * 0b0..Prescaler/glitch filter is enabled. - * 0b1..Prescaler/glitch filter is bypassed. - */ -#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) -#define LPTMR_PSR_PRESCALE_MASK (0x78U) -#define LPTMR_PSR_PRESCALE_SHIFT (3U) -/*! PRESCALE - Prescale Value - * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. - * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. - * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. - * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. - * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. - * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. - * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. - * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. - * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. - * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. - * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. - * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. - * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. - * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. - * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. - * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. - */ -#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) -/*! @} */ - -/*! @name CMR - Low Power Timer Compare Register */ -/*! @{ */ -#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) -#define LPTMR_CMR_COMPARE_SHIFT (0U) -#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) -/*! @} */ - -/*! @name CNR - Low Power Timer Counter Register */ -/*! @{ */ -#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) -#define LPTMR_CNR_COUNTER_SHIFT (0U) -#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPTMR_Register_Masks */ - - -/* LPTMR - Peripheral instance base addresses */ -/** Peripheral LPTMR0 base address */ -#define LPTMR0_BASE (0x40032000u) -/** Peripheral LPTMR0 base pointer */ -#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) -/** Peripheral LPTMR1 base address */ -#define LPTMR1_BASE (0x40033000u) -/** Peripheral LPTMR1 base pointer */ -#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) -/** Peripheral LPTMR2 base address */ -#define LPTMR2_BASE (0x4102B000u) -/** Peripheral LPTMR2 base pointer */ -#define LPTMR2 ((LPTMR_Type *)LPTMR2_BASE) -/** Array initializer of LPTMR peripheral base addresses */ -#define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE, LPTMR2_BASE } -/** Array initializer of LPTMR peripheral base pointers */ -#define LPTMR_BASE_PTRS { LPTMR0, LPTMR1, LPTMR2 } -/** Interrupt vectors for the LPTMR peripheral type */ -#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn } - -/*! - * @} - */ /* end of group LPTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer - * @{ - */ - -/** LPUART - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ - __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ - __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ - __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ - __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ - __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ - __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ - __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ - __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ - __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ -} LPUART_Type; - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPUART_VERID_FEATURE_MASK (0xFFFFU) -#define LPUART_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - * 0b0000000000000001..Standard feature set. - * 0b0000000000000011..Standard feature set with MODEM/IrDA support. - */ -#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) -#define LPUART_VERID_MINOR_MASK (0xFF0000U) -#define LPUART_VERID_MINOR_SHIFT (16U) -#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) -#define LPUART_VERID_MAJOR_MASK (0xFF000000U) -#define LPUART_VERID_MAJOR_SHIFT (24U) -#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPUART_PARAM_TXFIFO_MASK (0xFFU) -#define LPUART_PARAM_TXFIFO_SHIFT (0U) -#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) -#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) -#define LPUART_PARAM_RXFIFO_SHIFT (8U) -#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) -/*! @} */ - -/*! @name GLOBAL - LPUART Global Register */ -/*! @{ */ -#define LPUART_GLOBAL_RST_MASK (0x2U) -#define LPUART_GLOBAL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Module is not reset. - * 0b1..Module is reset. - */ -#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) -/*! @} */ - -/*! @name PINCFG - LPUART Pin Configuration Register */ -/*! @{ */ -#define LPUART_PINCFG_TRGSEL_MASK (0x3U) -#define LPUART_PINCFG_TRGSEL_SHIFT (0U) -/*! TRGSEL - Trigger Select - * 0b00..Input trigger is disabled. - * 0b01..Input trigger is used instead of RXD pin input. - * 0b10..Input trigger is used instead of CTS_B pin input. - * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. - */ -#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) -/*! @} */ - -/*! @name BAUD - LPUART Baud Rate Register */ -/*! @{ */ -#define LPUART_BAUD_SBR_MASK (0x1FFFU) -#define LPUART_BAUD_SBR_SHIFT (0U) -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) -#define LPUART_BAUD_SBNS_MASK (0x2000U) -#define LPUART_BAUD_SBNS_SHIFT (13U) -/*! SBNS - Stop Bit Number Select - * 0b0..One stop bit. - * 0b1..Two stop bits. - */ -#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) -#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) -#define LPUART_BAUD_RXEDGIE_SHIFT (14U) -/*! RXEDGIE - RX Input Active Edge Interrupt Enable - * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. - * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. - */ -#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) -#define LPUART_BAUD_LBKDIE_MASK (0x8000U) -#define LPUART_BAUD_LBKDIE_SHIFT (15U) -/*! LBKDIE - LIN Break Detect Interrupt Enable - * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). - * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. - */ -#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) -#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) -#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) -/*! RESYNCDIS - Resynchronization Disable - * 0b0..Resynchronization during received data word is supported - * 0b1..Resynchronization during received data word is disabled - */ -#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) -#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) -#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) -/*! BOTHEDGE - Both Edge Sampling - * 0b0..Receiver samples input data using the rising edge of the baud rate clock. - * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. - */ -#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) -#define LPUART_BAUD_MATCFG_MASK (0xC0000U) -#define LPUART_BAUD_MATCFG_SHIFT (18U) -/*! MATCFG - Match Configuration - * 0b00..Address Match Wakeup - * 0b01..Idle Match Wakeup - * 0b10..Match On and Match Off - * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input - */ -#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) -#define LPUART_BAUD_RIDMAE_MASK (0x100000U) -#define LPUART_BAUD_RIDMAE_SHIFT (20U) -/*! RIDMAE - Receiver Idle DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) -#define LPUART_BAUD_RDMAE_MASK (0x200000U) -#define LPUART_BAUD_RDMAE_SHIFT (21U) -/*! RDMAE - Receiver Full DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) -#define LPUART_BAUD_TDMAE_MASK (0x800000U) -#define LPUART_BAUD_TDMAE_SHIFT (23U) -/*! TDMAE - Transmitter DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) -#define LPUART_BAUD_OSR_MASK (0x1F000000U) -#define LPUART_BAUD_OSR_SHIFT (24U) -/*! OSR - Oversampling Ratio - * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 - * 0b00001..Reserved - * 0b00010..Reserved - * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. - * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. - * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. - * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. - * 0b00111..Oversampling ratio of 8. - * 0b01000..Oversampling ratio of 9. - * 0b01001..Oversampling ratio of 10. - * 0b01010..Oversampling ratio of 11. - * 0b01011..Oversampling ratio of 12. - * 0b01100..Oversampling ratio of 13. - * 0b01101..Oversampling ratio of 14. - * 0b01110..Oversampling ratio of 15. - * 0b01111..Oversampling ratio of 16. - * 0b10000..Oversampling ratio of 17. - * 0b10001..Oversampling ratio of 18. - * 0b10010..Oversampling ratio of 19. - * 0b10011..Oversampling ratio of 20. - * 0b10100..Oversampling ratio of 21. - * 0b10101..Oversampling ratio of 22. - * 0b10110..Oversampling ratio of 23. - * 0b10111..Oversampling ratio of 24. - * 0b11000..Oversampling ratio of 25. - * 0b11001..Oversampling ratio of 26. - * 0b11010..Oversampling ratio of 27. - * 0b11011..Oversampling ratio of 28. - * 0b11100..Oversampling ratio of 29. - * 0b11101..Oversampling ratio of 30. - * 0b11110..Oversampling ratio of 31. - * 0b11111..Oversampling ratio of 32. - */ -#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) -#define LPUART_BAUD_M10_MASK (0x20000000U) -#define LPUART_BAUD_M10_SHIFT (29U) -/*! M10 - 10-bit Mode select - * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. - * 0b1..Receiver and transmitter use 10-bit data characters. - */ -#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) -#define LPUART_BAUD_MAEN2_MASK (0x40000000U) -#define LPUART_BAUD_MAEN2_SHIFT (30U) -/*! MAEN2 - Match Address Mode Enable 2 - * 0b0..Normal operation. - * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. - */ -#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) -#define LPUART_BAUD_MAEN1_MASK (0x80000000U) -#define LPUART_BAUD_MAEN1_SHIFT (31U) -/*! MAEN1 - Match Address Mode Enable 1 - * 0b0..Normal operation. - * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. - */ -#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) -/*! @} */ - -/*! @name STAT - LPUART Status Register */ -/*! @{ */ -#define LPUART_STAT_MA2F_MASK (0x4000U) -#define LPUART_STAT_MA2F_SHIFT (14U) -/*! MA2F - Match 2 Flag - * 0b0..Received data is not equal to MA2 - * 0b1..Received data is equal to MA2 - */ -#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) -#define LPUART_STAT_MA1F_MASK (0x8000U) -#define LPUART_STAT_MA1F_SHIFT (15U) -/*! MA1F - Match 1 Flag - * 0b0..Received data is not equal to MA1 - * 0b1..Received data is equal to MA1 - */ -#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) -#define LPUART_STAT_PF_MASK (0x10000U) -#define LPUART_STAT_PF_SHIFT (16U) -/*! PF - Parity Error Flag - * 0b0..No parity error. - * 0b1..Parity error. - */ -#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) -#define LPUART_STAT_FE_MASK (0x20000U) -#define LPUART_STAT_FE_SHIFT (17U) -/*! FE - Framing Error Flag - * 0b0..No framing error detected. This does not guarantee the framing is correct. - * 0b1..Framing error. - */ -#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) -#define LPUART_STAT_NF_MASK (0x40000U) -#define LPUART_STAT_NF_SHIFT (18U) -/*! NF - Noise Flag - * 0b0..No noise detected. - * 0b1..Noise detected in the received character in LPUART_DATA. - */ -#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) -#define LPUART_STAT_OR_MASK (0x80000U) -#define LPUART_STAT_OR_SHIFT (19U) -/*! OR - Receiver Overrun Flag - * 0b0..No overrun. - * 0b1..Receive overrun (new LPUART data lost). - */ -#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) -#define LPUART_STAT_IDLE_MASK (0x100000U) -#define LPUART_STAT_IDLE_SHIFT (20U) -/*! IDLE - Idle Line Flag - * 0b0..No idle line detected. - * 0b1..Idle line was detected. - */ -#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) -#define LPUART_STAT_RDRF_MASK (0x200000U) -#define LPUART_STAT_RDRF_SHIFT (21U) -/*! RDRF - Receive Data Register Full Flag - * 0b0..Receive data buffer empty. - * 0b1..Receive data buffer full. - */ -#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) -#define LPUART_STAT_TC_MASK (0x400000U) -#define LPUART_STAT_TC_SHIFT (22U) -/*! TC - Transmission Complete Flag - * 0b0..Transmitter active (sending data, a preamble, or a break). - * 0b1..Transmitter idle (transmission activity complete). - */ -#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) -#define LPUART_STAT_TDRE_MASK (0x800000U) -#define LPUART_STAT_TDRE_SHIFT (23U) -/*! TDRE - Transmit Data Register Empty Flag - * 0b0..Transmit data buffer full. - * 0b1..Transmit data buffer empty. - */ -#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) -#define LPUART_STAT_RAF_MASK (0x1000000U) -#define LPUART_STAT_RAF_SHIFT (24U) -/*! RAF - Receiver Active Flag - * 0b0..LPUART receiver idle waiting for a start bit. - * 0b1..LPUART receiver active (RXD input not idle). - */ -#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) -#define LPUART_STAT_LBKDE_MASK (0x2000000U) -#define LPUART_STAT_LBKDE_SHIFT (25U) -/*! LBKDE - LIN Break Detection Enable - * 0b0..LIN break detect is disabled, normal break character can be detected. - * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). - */ -#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) -#define LPUART_STAT_BRK13_MASK (0x4000000U) -#define LPUART_STAT_BRK13_SHIFT (26U) -/*! BRK13 - Break Character Generation Length - * 0b0..Break character is transmitted with length of 9 to 13 bit times. - * 0b1..Break character is transmitted with length of 12 to 15 bit times. - */ -#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) -#define LPUART_STAT_RWUID_MASK (0x8000000U) -#define LPUART_STAT_RWUID_SHIFT (27U) -/*! RWUID - Receive Wake Up Idle Detect - * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. - * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. - */ -#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) -#define LPUART_STAT_RXINV_MASK (0x10000000U) -#define LPUART_STAT_RXINV_SHIFT (28U) -/*! RXINV - Receive Data Inversion - * 0b0..Receive data not inverted. - * 0b1..Receive data inverted. - */ -#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) -#define LPUART_STAT_MSBF_MASK (0x20000000U) -#define LPUART_STAT_MSBF_SHIFT (29U) -/*! MSBF - MSB First - * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. - * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. - */ -#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) -#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) -#define LPUART_STAT_RXEDGIF_SHIFT (30U) -/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag - * 0b0..No active edge on the receive pin has occurred. - * 0b1..An active edge on the receive pin has occurred. - */ -#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) -#define LPUART_STAT_LBKDIF_MASK (0x80000000U) -#define LPUART_STAT_LBKDIF_SHIFT (31U) -/*! LBKDIF - LIN Break Detect Interrupt Flag - * 0b0..No LIN break character has been detected. - * 0b1..LIN break character has been detected. - */ -#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) -/*! @} */ - -/*! @name CTRL - LPUART Control Register */ -/*! @{ */ -#define LPUART_CTRL_PT_MASK (0x1U) -#define LPUART_CTRL_PT_SHIFT (0U) -/*! PT - Parity Type - * 0b0..Even parity. - * 0b1..Odd parity. - */ -#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) -#define LPUART_CTRL_PE_MASK (0x2U) -#define LPUART_CTRL_PE_SHIFT (1U) -/*! PE - Parity Enable - * 0b0..No hardware parity generation or checking. - * 0b1..Parity enabled. - */ -#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) -#define LPUART_CTRL_ILT_MASK (0x4U) -#define LPUART_CTRL_ILT_SHIFT (2U) -/*! ILT - Idle Line Type Select - * 0b0..Idle character bit count starts after start bit. - * 0b1..Idle character bit count starts after stop bit. - */ -#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) -#define LPUART_CTRL_WAKE_MASK (0x8U) -#define LPUART_CTRL_WAKE_SHIFT (3U) -/*! WAKE - Receiver Wakeup Method Select - * 0b0..Configures RWU for idle-line wakeup. - * 0b1..Configures RWU with address-mark wakeup. - */ -#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) -#define LPUART_CTRL_M_MASK (0x10U) -#define LPUART_CTRL_M_SHIFT (4U) -/*! M - 9-Bit or 8-Bit Mode Select - * 0b0..Receiver and transmitter use 8-bit data characters. - * 0b1..Receiver and transmitter use 9-bit data characters. - */ -#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) -#define LPUART_CTRL_RSRC_MASK (0x20U) -#define LPUART_CTRL_RSRC_SHIFT (5U) -/*! RSRC - Receiver Source Select - * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. - * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. - */ -#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) -#define LPUART_CTRL_DOZEEN_MASK (0x40U) -#define LPUART_CTRL_DOZEEN_SHIFT (6U) -/*! DOZEEN - Doze Enable - * 0b0..LPUART is enabled in Doze mode. - * 0b1..LPUART is disabled in Doze mode. - */ -#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) -#define LPUART_CTRL_LOOPS_MASK (0x80U) -#define LPUART_CTRL_LOOPS_SHIFT (7U) -/*! LOOPS - Loop Mode Select - * 0b0..Normal operation - RXD and TXD use separate pins. - * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). - */ -#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) -#define LPUART_CTRL_IDLECFG_MASK (0x700U) -#define LPUART_CTRL_IDLECFG_SHIFT (8U) -/*! IDLECFG - Idle Configuration - * 0b000..1 idle character - * 0b001..2 idle characters - * 0b010..4 idle characters - * 0b011..8 idle characters - * 0b100..16 idle characters - * 0b101..32 idle characters - * 0b110..64 idle characters - * 0b111..128 idle characters - */ -#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) -#define LPUART_CTRL_M7_MASK (0x800U) -#define LPUART_CTRL_M7_SHIFT (11U) -/*! M7 - 7-Bit Mode Select - * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. - * 0b1..Receiver and transmitter use 7-bit data characters. - */ -#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) -#define LPUART_CTRL_MA2IE_MASK (0x4000U) -#define LPUART_CTRL_MA2IE_SHIFT (14U) -/*! MA2IE - Match 2 Interrupt Enable - * 0b0..MA2F interrupt disabled - * 0b1..MA2F interrupt enabled - */ -#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) -#define LPUART_CTRL_MA1IE_MASK (0x8000U) -#define LPUART_CTRL_MA1IE_SHIFT (15U) -/*! MA1IE - Match 1 Interrupt Enable - * 0b0..MA1F interrupt disabled - * 0b1..MA1F interrupt enabled - */ -#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) -#define LPUART_CTRL_SBK_MASK (0x10000U) -#define LPUART_CTRL_SBK_SHIFT (16U) -/*! SBK - Send Break - * 0b0..Normal transmitter operation. - * 0b1..Queue break character(s) to be sent. - */ -#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) -#define LPUART_CTRL_RWU_MASK (0x20000U) -#define LPUART_CTRL_RWU_SHIFT (17U) -/*! RWU - Receiver Wakeup Control - * 0b0..Normal receiver operation. - * 0b1..LPUART receiver in standby waiting for wakeup condition. - */ -#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) -#define LPUART_CTRL_RE_MASK (0x40000U) -#define LPUART_CTRL_RE_SHIFT (18U) -/*! RE - Receiver Enable - * 0b0..Receiver disabled. - * 0b1..Receiver enabled. - */ -#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) -#define LPUART_CTRL_TE_MASK (0x80000U) -#define LPUART_CTRL_TE_SHIFT (19U) -/*! TE - Transmitter Enable - * 0b0..Transmitter disabled. - * 0b1..Transmitter enabled. - */ -#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) -#define LPUART_CTRL_ILIE_MASK (0x100000U) -#define LPUART_CTRL_ILIE_SHIFT (20U) -/*! ILIE - Idle Line Interrupt Enable - * 0b0..Hardware interrupts from IDLE disabled; use polling. - * 0b1..Hardware interrupt requested when IDLE flag is 1. - */ -#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) -#define LPUART_CTRL_RIE_MASK (0x200000U) -#define LPUART_CTRL_RIE_SHIFT (21U) -/*! RIE - Receiver Interrupt Enable - * 0b0..Hardware interrupts from RDRF disabled; use polling. - * 0b1..Hardware interrupt requested when RDRF flag is 1. - */ -#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) -#define LPUART_CTRL_TCIE_MASK (0x400000U) -#define LPUART_CTRL_TCIE_SHIFT (22U) -/*! TCIE - Transmission Complete Interrupt Enable for - * 0b0..Hardware interrupts from TC disabled; use polling. - * 0b1..Hardware interrupt requested when TC flag is 1. - */ -#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) -#define LPUART_CTRL_TIE_MASK (0x800000U) -#define LPUART_CTRL_TIE_SHIFT (23U) -/*! TIE - Transmit Interrupt Enable - * 0b0..Hardware interrupts from TDRE disabled; use polling. - * 0b1..Hardware interrupt requested when TDRE flag is 1. - */ -#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) -#define LPUART_CTRL_PEIE_MASK (0x1000000U) -#define LPUART_CTRL_PEIE_SHIFT (24U) -/*! PEIE - Parity Error Interrupt Enable - * 0b0..PF interrupts disabled; use polling). - * 0b1..Hardware interrupt requested when PF is set. - */ -#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) -#define LPUART_CTRL_FEIE_MASK (0x2000000U) -#define LPUART_CTRL_FEIE_SHIFT (25U) -/*! FEIE - Framing Error Interrupt Enable - * 0b0..FE interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when FE is set. - */ -#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) -#define LPUART_CTRL_NEIE_MASK (0x4000000U) -#define LPUART_CTRL_NEIE_SHIFT (26U) -/*! NEIE - Noise Error Interrupt Enable - * 0b0..NF interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when NF is set. - */ -#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) -#define LPUART_CTRL_ORIE_MASK (0x8000000U) -#define LPUART_CTRL_ORIE_SHIFT (27U) -/*! ORIE - Overrun Interrupt Enable - * 0b0..OR interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when OR is set. - */ -#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) -#define LPUART_CTRL_TXINV_MASK (0x10000000U) -#define LPUART_CTRL_TXINV_SHIFT (28U) -/*! TXINV - Transmit Data Inversion - * 0b0..Transmit data not inverted. - * 0b1..Transmit data inverted. - */ -#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) -#define LPUART_CTRL_TXDIR_MASK (0x20000000U) -#define LPUART_CTRL_TXDIR_SHIFT (29U) -/*! TXDIR - TXD Pin Direction in Single-Wire Mode - * 0b0..TXD pin is an input in single-wire mode. - * 0b1..TXD pin is an output in single-wire mode. - */ -#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) -#define LPUART_CTRL_R9T8_MASK (0x40000000U) -#define LPUART_CTRL_R9T8_SHIFT (30U) -#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) -#define LPUART_CTRL_R8T9_MASK (0x80000000U) -#define LPUART_CTRL_R8T9_SHIFT (31U) -#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) -/*! @} */ - -/*! @name DATA - LPUART Data Register */ -/*! @{ */ -#define LPUART_DATA_R0T0_MASK (0x1U) -#define LPUART_DATA_R0T0_SHIFT (0U) -#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) -#define LPUART_DATA_R1T1_MASK (0x2U) -#define LPUART_DATA_R1T1_SHIFT (1U) -#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) -#define LPUART_DATA_R2T2_MASK (0x4U) -#define LPUART_DATA_R2T2_SHIFT (2U) -#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) -#define LPUART_DATA_R3T3_MASK (0x8U) -#define LPUART_DATA_R3T3_SHIFT (3U) -#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) -#define LPUART_DATA_R4T4_MASK (0x10U) -#define LPUART_DATA_R4T4_SHIFT (4U) -#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) -#define LPUART_DATA_R5T5_MASK (0x20U) -#define LPUART_DATA_R5T5_SHIFT (5U) -#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) -#define LPUART_DATA_R6T6_MASK (0x40U) -#define LPUART_DATA_R6T6_SHIFT (6U) -#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) -#define LPUART_DATA_R7T7_MASK (0x80U) -#define LPUART_DATA_R7T7_SHIFT (7U) -#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) -#define LPUART_DATA_R8T8_MASK (0x100U) -#define LPUART_DATA_R8T8_SHIFT (8U) -#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) -#define LPUART_DATA_R9T9_MASK (0x200U) -#define LPUART_DATA_R9T9_SHIFT (9U) -#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) -#define LPUART_DATA_IDLINE_MASK (0x800U) -#define LPUART_DATA_IDLINE_SHIFT (11U) -/*! IDLINE - Idle Line - * 0b0..Receiver was not idle before receiving this character. - * 0b1..Receiver was idle before receiving this character. - */ -#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) -#define LPUART_DATA_RXEMPT_MASK (0x1000U) -#define LPUART_DATA_RXEMPT_SHIFT (12U) -/*! RXEMPT - Receive Buffer Empty - * 0b0..Receive buffer contains valid data. - * 0b1..Receive buffer is empty, data returned on read is not valid. - */ -#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) -#define LPUART_DATA_FRETSC_MASK (0x2000U) -#define LPUART_DATA_FRETSC_SHIFT (13U) -/*! FRETSC - Frame Error / Transmit Special Character - * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. - * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. - */ -#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) -#define LPUART_DATA_PARITYE_MASK (0x4000U) -#define LPUART_DATA_PARITYE_SHIFT (14U) -/*! PARITYE - PARITYE - * 0b0..The dataword was received without a parity error. - * 0b1..The dataword was received with a parity error. - */ -#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) -#define LPUART_DATA_NOISY_MASK (0x8000U) -#define LPUART_DATA_NOISY_SHIFT (15U) -/*! NOISY - NOISY - * 0b0..The dataword was received without noise. - * 0b1..The data was received with noise. - */ -#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) -/*! @} */ - -/*! @name MATCH - LPUART Match Address Register */ -/*! @{ */ -#define LPUART_MATCH_MA1_MASK (0x3FFU) -#define LPUART_MATCH_MA1_SHIFT (0U) -#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) -#define LPUART_MATCH_MA2_MASK (0x3FF0000U) -#define LPUART_MATCH_MA2_SHIFT (16U) -#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) -/*! @} */ - -/*! @name MODIR - LPUART Modem IrDA Register */ -/*! @{ */ -#define LPUART_MODIR_TXCTSE_MASK (0x1U) -#define LPUART_MODIR_TXCTSE_SHIFT (0U) -/*! TXCTSE - Transmitter clear-to-send enable - * 0b0..CTS has no effect on the transmitter. - * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. - */ -#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) -#define LPUART_MODIR_TXRTSE_MASK (0x2U) -#define LPUART_MODIR_TXRTSE_SHIFT (1U) -/*! TXRTSE - Transmitter request-to-send enable - * 0b0..The transmitter has no effect on RTS. - * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. - */ -#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) -#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) -#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) -/*! TXRTSPOL - Transmitter request-to-send polarity - * 0b0..Transmitter RTS is active low. - * 0b1..Transmitter RTS is active high. - */ -#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) -#define LPUART_MODIR_RXRTSE_MASK (0x8U) -#define LPUART_MODIR_RXRTSE_SHIFT (3U) -/*! RXRTSE - Receiver request-to-send enable - * 0b0..The receiver has no effect on RTS. - * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. - */ -#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) -#define LPUART_MODIR_TXCTSC_MASK (0x10U) -#define LPUART_MODIR_TXCTSC_SHIFT (4U) -/*! TXCTSC - Transmit CTS Configuration - * 0b0..CTS input is sampled at the start of each character. - * 0b1..CTS input is sampled when the transmitter is idle. - */ -#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) -#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) -#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) -/*! TXCTSSRC - Transmit CTS Source - * 0b0..CTS input is the CTS_B pin. - * 0b1..CTS input is the inverted Receiver Match result. - */ -#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) -#define LPUART_MODIR_RTSWATER_MASK (0x700U) -#define LPUART_MODIR_RTSWATER_SHIFT (8U) -#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) -#define LPUART_MODIR_TNP_MASK (0x30000U) -#define LPUART_MODIR_TNP_SHIFT (16U) -/*! TNP - Transmitter narrow pulse - * 0b00..1/OSR. - * 0b01..2/OSR. - * 0b10..3/OSR. - * 0b11..4/OSR. - */ -#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) -#define LPUART_MODIR_IREN_MASK (0x40000U) -#define LPUART_MODIR_IREN_SHIFT (18U) -/*! IREN - Infrared enable - * 0b0..IR disabled. - * 0b1..IR enabled. - */ -#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) -/*! @} */ - -/*! @name FIFO - LPUART FIFO Register */ -/*! @{ */ -#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) -#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) -/*! RXFIFOSIZE - Receive FIFO. Buffer Depth - * 0b000..Receive FIFO/Buffer depth = 1 dataword. - * 0b001..Receive FIFO/Buffer depth = 4 datawords. - * 0b010..Receive FIFO/Buffer depth = 8 datawords. - * 0b011..Receive FIFO/Buffer depth = 16 datawords. - * 0b100..Receive FIFO/Buffer depth = 32 datawords. - * 0b101..Receive FIFO/Buffer depth = 64 datawords. - * 0b110..Receive FIFO/Buffer depth = 128 datawords. - * 0b111..Receive FIFO/Buffer depth = 256 datawords. - */ -#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) -#define LPUART_FIFO_RXFE_MASK (0x8U) -#define LPUART_FIFO_RXFE_SHIFT (3U) -/*! RXFE - Receive FIFO Enable - * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) - * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. - */ -#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) -#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) -#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) -/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth - * 0b000..Transmit FIFO/Buffer depth = 1 dataword. - * 0b001..Transmit FIFO/Buffer depth = 4 datawords. - * 0b010..Transmit FIFO/Buffer depth = 8 datawords. - * 0b011..Transmit FIFO/Buffer depth = 16 datawords. - * 0b100..Transmit FIFO/Buffer depth = 32 datawords. - * 0b101..Transmit FIFO/Buffer depth = 64 datawords. - * 0b110..Transmit FIFO/Buffer depth = 128 datawords. - * 0b111..Transmit FIFO/Buffer depth = 256 datawords - */ -#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) -#define LPUART_FIFO_TXFE_MASK (0x80U) -#define LPUART_FIFO_TXFE_SHIFT (7U) -/*! TXFE - Transmit FIFO Enable - * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). - * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. - */ -#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) -#define LPUART_FIFO_RXUFE_MASK (0x100U) -#define LPUART_FIFO_RXUFE_SHIFT (8U) -/*! RXUFE - Receive FIFO Underflow Interrupt Enable - * 0b0..RXUF flag does not generate an interrupt to the host. - * 0b1..RXUF flag generates an interrupt to the host. - */ -#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) -#define LPUART_FIFO_TXOFE_MASK (0x200U) -#define LPUART_FIFO_TXOFE_SHIFT (9U) -/*! TXOFE - Transmit FIFO Overflow Interrupt Enable - * 0b0..TXOF flag does not generate an interrupt to the host. - * 0b1..TXOF flag generates an interrupt to the host. - */ -#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) -#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) -#define LPUART_FIFO_RXIDEN_SHIFT (10U) -/*! RXIDEN - Receiver Idle Empty Enable - * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. - * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. - * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. - * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. - * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. - * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. - * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. - * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. - */ -#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) -#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) -#define LPUART_FIFO_RXFLUSH_SHIFT (14U) -/*! RXFLUSH - Receive FIFO/Buffer Flush - * 0b0..No flush operation occurs. - * 0b1..All data in the receive FIFO/buffer is cleared out. - */ -#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) -#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) -#define LPUART_FIFO_TXFLUSH_SHIFT (15U) -/*! TXFLUSH - Transmit FIFO/Buffer Flush - * 0b0..No flush operation occurs. - * 0b1..All data in the transmit FIFO/Buffer is cleared out. - */ -#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) -#define LPUART_FIFO_RXUF_MASK (0x10000U) -#define LPUART_FIFO_RXUF_SHIFT (16U) -/*! RXUF - Receiver Buffer Underflow Flag - * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. - * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. - */ -#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) -#define LPUART_FIFO_TXOF_MASK (0x20000U) -#define LPUART_FIFO_TXOF_SHIFT (17U) -/*! TXOF - Transmitter Buffer Overflow Flag - * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. - * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. - */ -#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) -#define LPUART_FIFO_RXEMPT_MASK (0x400000U) -#define LPUART_FIFO_RXEMPT_SHIFT (22U) -/*! RXEMPT - Receive Buffer/FIFO Empty - * 0b0..Receive buffer is not empty. - * 0b1..Receive buffer is empty. - */ -#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) -#define LPUART_FIFO_TXEMPT_MASK (0x800000U) -#define LPUART_FIFO_TXEMPT_SHIFT (23U) -/*! TXEMPT - Transmit Buffer/FIFO Empty - * 0b0..Transmit buffer is not empty. - * 0b1..Transmit buffer is empty. - */ -#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) -/*! @} */ - -/*! @name WATER - LPUART Watermark Register */ -/*! @{ */ -#define LPUART_WATER_TXWATER_MASK (0x7U) -#define LPUART_WATER_TXWATER_SHIFT (0U) -#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) -#define LPUART_WATER_TXCOUNT_MASK (0xF00U) -#define LPUART_WATER_TXCOUNT_SHIFT (8U) -#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) -#define LPUART_WATER_RXWATER_MASK (0x70000U) -#define LPUART_WATER_RXWATER_SHIFT (16U) -#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) -#define LPUART_WATER_RXCOUNT_MASK (0xF000000U) -#define LPUART_WATER_RXCOUNT_SHIFT (24U) -#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPUART_Register_Masks */ - - -/* LPUART - Peripheral instance base addresses */ -/** Peripheral LPUART0 base address */ -#define LPUART0_BASE (0x40042000u) -/** Peripheral LPUART0 base pointer */ -#define LPUART0 ((LPUART_Type *)LPUART0_BASE) -/** Peripheral LPUART1 base address */ -#define LPUART1_BASE (0x40043000u) -/** Peripheral LPUART1 base pointer */ -#define LPUART1 ((LPUART_Type *)LPUART1_BASE) -/** Peripheral LPUART2 base address */ -#define LPUART2_BASE (0x40044000u) -/** Peripheral LPUART2 base pointer */ -#define LPUART2 ((LPUART_Type *)LPUART2_BASE) -/** Peripheral LPUART3 base address */ -#define LPUART3_BASE (0x41036000u) -/** Peripheral LPUART3 base pointer */ -#define LPUART3 ((LPUART_Type *)LPUART3_BASE) -/** Array initializer of LPUART peripheral base addresses */ -#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE } -/** Array initializer of LPUART peripheral base pointers */ -#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3 } -/** Interrupt vectors for the LPUART peripheral type */ -#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } -#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } - -/*! - * @} - */ /* end of group LPUART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer - * @{ - */ - -/** MCM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ - __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ - __IO uint32_t CPCR; /**< Core Platform Control Register, offset: 0xC */ - __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ - uint8_t RESERVED_1[32]; - __IO uint32_t CPCR2; /**< Core Platform Control Register 2, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ -} MCM_Type; - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ -/*! @{ */ -#define MCM_PLASC_ASC_MASK (0xFFU) -#define MCM_PLASC_ASC_SHIFT (0U) -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) -/*! @} */ - -/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ -/*! @{ */ -#define MCM_PLAMC_AMC_MASK (0xFFU) -#define MCM_PLAMC_AMC_SHIFT (0U) -#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) -/*! @} */ - -/*! @name CPCR - Core Platform Control Register */ -/*! @{ */ -#define MCM_CPCR_CBRR_MASK (0x200U) -#define MCM_CPCR_CBRR_SHIFT (9U) -/*! CBRR - Crossbar round-robin arbitration enable - * 0b0..Fixed-priority arbitration - * 0b1..Round-robin arbitration - */ -#define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK) -/*! @} */ - -/*! @name ISCR - Interrupt Status and Control Register */ -/*! @{ */ -#define MCM_ISCR_FIOC_MASK (0x100U) -#define MCM_ISCR_FIOC_SHIFT (8U) -/*! FIOC - FPU invalid operation interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) -#define MCM_ISCR_FDZC_MASK (0x200U) -#define MCM_ISCR_FDZC_SHIFT (9U) -/*! FDZC - FPU divide-by-zero interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) -#define MCM_ISCR_FOFC_MASK (0x400U) -#define MCM_ISCR_FOFC_SHIFT (10U) -/*! FOFC - FPU overflow interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) -#define MCM_ISCR_FUFC_MASK (0x800U) -#define MCM_ISCR_FUFC_SHIFT (11U) -/*! FUFC - FPU underflow interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) -#define MCM_ISCR_FIXC_MASK (0x1000U) -#define MCM_ISCR_FIXC_SHIFT (12U) -/*! FIXC - FPU inexact interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) -#define MCM_ISCR_FIDC_MASK (0x8000U) -#define MCM_ISCR_FIDC_SHIFT (15U) -/*! FIDC - FPU input denormal interrupt status - * 0b0..No interrupt - * 0b1..Interrupt occurred - */ -#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) -#define MCM_ISCR_FIOCE_MASK (0x1000000U) -#define MCM_ISCR_FIOCE_SHIFT (24U) -/*! FIOCE - FPU invalid operation interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) -#define MCM_ISCR_FDZCE_MASK (0x2000000U) -#define MCM_ISCR_FDZCE_SHIFT (25U) -/*! FDZCE - FPU divide-by-zero interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) -#define MCM_ISCR_FOFCE_MASK (0x4000000U) -#define MCM_ISCR_FOFCE_SHIFT (26U) -/*! FOFCE - FPU overflow interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) -#define MCM_ISCR_FUFCE_MASK (0x8000000U) -#define MCM_ISCR_FUFCE_SHIFT (27U) -/*! FUFCE - FPU underflow interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) -#define MCM_ISCR_FIXCE_MASK (0x10000000U) -#define MCM_ISCR_FIXCE_SHIFT (28U) -/*! FIXCE - FPU inexact interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) -#define MCM_ISCR_FIDCE_MASK (0x80000000U) -#define MCM_ISCR_FIDCE_SHIFT (31U) -/*! FIDCE - FPU input denormal interrupt enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt - */ -#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) -/*! @} */ - -/*! @name CPCR2 - Core Platform Control Register 2 */ -/*! @{ */ -#define MCM_CPCR2_CCBC_MASK (0x1U) -#define MCM_CPCR2_CCBC_SHIFT (0U) -/*! CCBC - Clear code bus cache, this field always reads as 0. - * 0b0..No effect - * 0b1..Clear code bus cache - */ -#define MCM_CPCR2_CCBC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCBC_SHIFT)) & MCM_CPCR2_CCBC_MASK) -#define MCM_CPCR2_DCBC_MASK (0x8U) -#define MCM_CPCR2_DCBC_SHIFT (3U) -/*! DCBC - Disable code bus cache - * 0b0..Enable code bus cache - * 0b1..Disable code bus cache - */ -#define MCM_CPCR2_DCBC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCBC_SHIFT)) & MCM_CPCR2_DCBC_MASK) -#define MCM_CPCR2_CBCS_MASK (0xF0U) -#define MCM_CPCR2_CBCS_SHIFT (4U) -/*! CBCS - Code Bus Cache Size - * 0b0000..0 KB - * 0b0001..1 KB - * 0b0010..2 KB - * 0b0011..4 KB - * 0b0100..8 KB - * 0b0101..16 KB - * 0b0110..32 KB - */ -#define MCM_CPCR2_CBCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CBCS_SHIFT)) & MCM_CPCR2_CBCS_MASK) -#define MCM_CPCR2_PCCMCTRL_MASK (0x10000U) -#define MCM_CPCR2_PCCMCTRL_SHIFT (16U) -/*! PCCMCTRL - Bypass fixed code cache map - * 0b0..The fixed code cache map is not bypassed - * 0b1..The fixed code cache map is bypassed - */ -#define MCM_CPCR2_PCCMCTRL(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_PCCMCTRL_SHIFT)) & MCM_CPCR2_PCCMCTRL_MASK) -#define MCM_CPCR2_LCCPWB_MASK (0x20000U) -#define MCM_CPCR2_LCCPWB_SHIFT (17U) -/*! LCCPWB - Limit code cache peripheral write buffering - * 0b0..Code cache peripheral write buffering is not limited - * 0b1..Code cache peripheral write buffering is limited - */ -#define MCM_CPCR2_LCCPWB(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_LCCPWB_SHIFT)) & MCM_CPCR2_LCCPWB_MASK) -/*! @} */ - -/*! @name CPO - Compute Operation Control Register */ -/*! @{ */ -#define MCM_CPO_CPOREQ_MASK (0x1U) -#define MCM_CPO_CPOREQ_SHIFT (0U) -/*! CPOREQ - Compute Operation request - * 0b0..Request is cleared. - * 0b1..Request Compute Operation. - */ -#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) -#define MCM_CPO_CPOACK_MASK (0x2U) -#define MCM_CPO_CPOACK_SHIFT (1U) -/*! CPOACK - Compute Operation acknowledge - * 0b0..Compute operation entry has not completed or compute operation exit has completed. - * 0b1..Compute operation entry has completed or compute operation exit has not completed. - */ -#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) -#define MCM_CPO_CPOWOI_MASK (0x4U) -#define MCM_CPO_CPOWOI_SHIFT (2U) -/*! CPOWOI - Compute Operation wakeup on interrupt - * 0b0..No effect. - * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. - */ -#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MCM_Register_Masks */ - - -/* MCM - Peripheral instance base addresses */ -/** Peripheral MCM0 base address */ -#define MCM0_BASE (0xE0080000u) -/** Peripheral MCM0 base pointer */ -#define MCM0 ((MCM_Type *)MCM0_BASE) -/** Array initializer of MCM peripheral base addresses */ -#define MCM_BASE_ADDRS { MCM0_BASE } -/** Array initializer of MCM peripheral base pointers */ -#define MCM_BASE_PTRS { MCM0 } -/** Interrupt vectors for the MCM peripheral type */ -#define MCM_IRQS { CTI0_MCM0_IRQn } -/* MCM compatibility definitions */ -#define MCM_BASE MCM0_BASE -#define MCM MCM0 - - -/*! - * @} - */ /* end of group MCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MSCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer - * @{ - */ - -/** MSCM - Register Layout Typedef */ -typedef struct { - __I uint32_t CPXTYPE; /**< Processor X Type Register, offset: 0x0 */ - __I uint32_t CPXNUM; /**< Processor X Number Register, offset: 0x4 */ - __I uint32_t CPXMASTER; /**< Processor X Master Register, offset: 0x8 */ - __I uint32_t CPXCOUNT; /**< Processor X Count Register, offset: 0xC */ - __I uint32_t CPXCFG0; /**< Processor X Configuration Register 0, offset: 0x10 */ - __I uint32_t CPXCFG1; /**< Processor X Configuration Register 1, offset: 0x14 */ - __I uint32_t CPXCFG2; /**< Processor X Configuration Register 2, offset: 0x18 */ - __I uint32_t CPXCFG3; /**< Processor X Configuration Register 3, offset: 0x1C */ - struct { /* offset: 0x20, array step: 0x20 */ - __I uint32_t TYPE; /**< Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20 */ - __I uint32_t NUM; /**< Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20 */ - __I uint32_t MASTER; /**< Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20 */ - __I uint32_t COUNT; /**< Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20 */ - __I uint32_t CFG0; /**< Processor 0 Configuration Register 0..Processor 1 Configuration Register 0, array offset: 0x30, array step: 0x20 */ - __I uint32_t CFG1; /**< Processor 0 Configuration Register 1..Processor 1 Configuration Register 1, array offset: 0x34, array step: 0x20 */ - __I uint32_t CFG2; /**< Processor 0 Configuration Register 2..Processor 1 Configuration Register 2, array offset: 0x38, array step: 0x20 */ - __I uint32_t CFG3; /**< Processor 0 Configuration Register 3..Processor 1 Configuration Register 3, array offset: 0x3C, array step: 0x20 */ - } CP[2]; - uint8_t RESERVED_0[928]; - __IO uint32_t OCMDR0; /**< On-Chip Memory Descriptor Register, offset: 0x400 */ - __IO uint32_t OCMDR1; /**< On-Chip Memory Descriptor Register, offset: 0x404 */ - __IO uint32_t OCMDR2; /**< On-Chip Memory Descriptor Register, offset: 0x408 */ - __IO uint32_t OCMDR3; /**< On-Chip Memory Descriptor Register, offset: 0x40C */ -} MSCM_Type; - -/* ---------------------------------------------------------------------------- - -- MSCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MSCM_Register_Masks MSCM Register Masks - * @{ - */ - -/*! @name CPXTYPE - Processor X Type Register */ -/*! @{ */ -#define MSCM_CPXTYPE_RYPZ_MASK (0xFFU) -#define MSCM_CPXTYPE_RYPZ_SHIFT (0U) -#define MSCM_CPXTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_RYPZ_SHIFT)) & MSCM_CPXTYPE_RYPZ_MASK) -#define MSCM_CPXTYPE_PERSONALITY_MASK (0xFFFFFF00U) -#define MSCM_CPXTYPE_PERSONALITY_SHIFT (8U) -#define MSCM_CPXTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK) -/*! @} */ - -/*! @name CPXNUM - Processor X Number Register */ -/*! @{ */ -#define MSCM_CPXNUM_CPN_MASK (0x1U) -#define MSCM_CPXNUM_CPN_SHIFT (0U) -#define MSCM_CPXNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK) -/*! @} */ - -/*! @name CPXMASTER - Processor X Master Register */ -/*! @{ */ -#define MSCM_CPXMASTER_PPMN_MASK (0x3FU) -#define MSCM_CPXMASTER_PPMN_SHIFT (0U) -#define MSCM_CPXMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXMASTER_PPMN_SHIFT)) & MSCM_CPXMASTER_PPMN_MASK) -/*! @} */ - -/*! @name CPXCOUNT - Processor X Count Register */ -/*! @{ */ -#define MSCM_CPXCOUNT_PCNT_MASK (0x3U) -#define MSCM_CPXCOUNT_PCNT_SHIFT (0U) -#define MSCM_CPXCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCOUNT_PCNT_SHIFT)) & MSCM_CPXCOUNT_PCNT_MASK) -/*! @} */ - -/*! @name CPXCFG0 - Processor X Configuration Register 0 */ -/*! @{ */ -#define MSCM_CPXCFG0_DCWY_MASK (0xFFU) -#define MSCM_CPXCFG0_DCWY_SHIFT (0U) -#define MSCM_CPXCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK) -#define MSCM_CPXCFG0_DCSZ_MASK (0xFF00U) -#define MSCM_CPXCFG0_DCSZ_SHIFT (8U) -#define MSCM_CPXCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK) -#define MSCM_CPXCFG0_ICWY_MASK (0xFF0000U) -#define MSCM_CPXCFG0_ICWY_SHIFT (16U) -#define MSCM_CPXCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK) -#define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) -#define MSCM_CPXCFG0_ICSZ_SHIFT (24U) -#define MSCM_CPXCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK) -/*! @} */ - -/*! @name CPXCFG1 - Processor X Configuration Register 1 */ -/*! @{ */ -#define MSCM_CPXCFG1_L2WY_MASK (0xFF0000U) -#define MSCM_CPXCFG1_L2WY_SHIFT (16U) -#define MSCM_CPXCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK) -#define MSCM_CPXCFG1_L2SZ_MASK (0xFF000000U) -#define MSCM_CPXCFG1_L2SZ_SHIFT (24U) -#define MSCM_CPXCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK) -/*! @} */ - -/*! @name CPXCFG2 - Processor X Configuration Register 2 */ -/*! @{ */ -#define MSCM_CPXCFG2_TMUSZ_MASK (0xFF00U) -#define MSCM_CPXCFG2_TMUSZ_SHIFT (8U) -#define MSCM_CPXCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMUSZ_SHIFT)) & MSCM_CPXCFG2_TMUSZ_MASK) -#define MSCM_CPXCFG2_TMLSZ_MASK (0xFF000000U) -#define MSCM_CPXCFG2_TMLSZ_SHIFT (24U) -#define MSCM_CPXCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMLSZ_SHIFT)) & MSCM_CPXCFG2_TMLSZ_MASK) -/*! @} */ - -/*! @name CPXCFG3 - Processor X Configuration Register 3 */ -/*! @{ */ -#define MSCM_CPXCFG3_FPU_MASK (0x1U) -#define MSCM_CPXCFG3_FPU_SHIFT (0U) -/*! FPU - Floating Point Unit - * 0b0..FPU support is not included. - * 0b1..FPU support is included. - */ -#define MSCM_CPXCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK) -#define MSCM_CPXCFG3_SIMD_MASK (0x2U) -#define MSCM_CPXCFG3_SIMD_SHIFT (1U) -/*! SIMD - SIMD/NEON instruction support - * 0b0..SIMD/NEON support is not included. - * 0b1..SIMD/NEON support is included. - */ -#define MSCM_CPXCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK) -#define MSCM_CPXCFG3_JAZ_MASK (0x4U) -#define MSCM_CPXCFG3_JAZ_SHIFT (2U) -/*! JAZ - Jazelle support - * 0b0..Jazelle support is not included. - * 0b1..Jazelle support is included. - */ -#define MSCM_CPXCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_JAZ_SHIFT)) & MSCM_CPXCFG3_JAZ_MASK) -#define MSCM_CPXCFG3_MMU_MASK (0x8U) -#define MSCM_CPXCFG3_MMU_SHIFT (3U) -/*! MMU - Memory Management Unit - * 0b0..MMU support is not included. - * 0b1..MMU support is included. - */ -#define MSCM_CPXCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK) -#define MSCM_CPXCFG3_TZ_MASK (0x10U) -#define MSCM_CPXCFG3_TZ_SHIFT (4U) -/*! TZ - Trust Zone - * 0b0..Trust Zone support is not included. - * 0b1..Trust Zone support is included. - */ -#define MSCM_CPXCFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_TZ_SHIFT)) & MSCM_CPXCFG3_TZ_MASK) -#define MSCM_CPXCFG3_CMP_MASK (0x20U) -#define MSCM_CPXCFG3_CMP_SHIFT (5U) -/*! CMP - Core Memory Protection unit - * 0b0..Core Memory Protection is not included. - * 0b1..Core Memory Protection is included. - */ -#define MSCM_CPXCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK) -#define MSCM_CPXCFG3_BB_MASK (0x40U) -#define MSCM_CPXCFG3_BB_SHIFT (6U) -/*! BB - Bit Banding - * 0b0..Bit Banding is not supported. - * 0b1..Bit Banding is supported. - */ -#define MSCM_CPXCFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_BB_SHIFT)) & MSCM_CPXCFG3_BB_MASK) -#define MSCM_CPXCFG3_SBP_MASK (0x300U) -#define MSCM_CPXCFG3_SBP_SHIFT (8U) -#define MSCM_CPXCFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SBP_SHIFT)) & MSCM_CPXCFG3_SBP_MASK) -/*! @} */ - -/*! @name TYPE - Processor 0 Type Register..Processor 1 Type Register */ -/*! @{ */ -#define MSCM_TYPE_RYPZ_MASK (0xFFU) -#define MSCM_TYPE_RYPZ_SHIFT (0U) -#define MSCM_TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK) -#define MSCM_TYPE_PERSONALITY_MASK (0xFFFFFF00U) -#define MSCM_TYPE_PERSONALITY_SHIFT (8U) -#define MSCM_TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK) -/*! @} */ - -/* The count of MSCM_TYPE */ -#define MSCM_TYPE_COUNT (2U) - -/*! @name NUM - Processor 0 Number Register..Processor 1 Number Register */ -/*! @{ */ -#define MSCM_NUM_CPN_MASK (0x1U) -#define MSCM_NUM_CPN_SHIFT (0U) -#define MSCM_NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK) -/*! @} */ - -/* The count of MSCM_NUM */ -#define MSCM_NUM_COUNT (2U) - -/*! @name MASTER - Processor 0 Master Register..Processor 1 Master Register */ -/*! @{ */ -#define MSCM_MASTER_PPMN_MASK (0x3FU) -#define MSCM_MASTER_PPMN_SHIFT (0U) -#define MSCM_MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPMN_SHIFT)) & MSCM_MASTER_PPMN_MASK) -/*! @} */ - -/* The count of MSCM_MASTER */ -#define MSCM_MASTER_COUNT (2U) - -/*! @name COUNT - Processor 0 Count Register..Processor 1 Count Register */ -/*! @{ */ -#define MSCM_COUNT_PCNT_MASK (0x3U) -#define MSCM_COUNT_PCNT_SHIFT (0U) -#define MSCM_COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK) -/*! @} */ - -/* The count of MSCM_COUNT */ -#define MSCM_COUNT_COUNT (2U) - -/*! @name CFG0 - Processor 0 Configuration Register 0..Processor 1 Configuration Register 0 */ -/*! @{ */ -#define MSCM_CFG0_DCWY_MASK (0xFFU) -#define MSCM_CFG0_DCWY_SHIFT (0U) -#define MSCM_CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCWY_SHIFT)) & MSCM_CFG0_DCWY_MASK) -#define MSCM_CFG0_DCSZ_MASK (0xFF00U) -#define MSCM_CFG0_DCSZ_SHIFT (8U) -#define MSCM_CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCSZ_SHIFT)) & MSCM_CFG0_DCSZ_MASK) -#define MSCM_CFG0_ICWY_MASK (0xFF0000U) -#define MSCM_CFG0_ICWY_SHIFT (16U) -#define MSCM_CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICWY_SHIFT)) & MSCM_CFG0_ICWY_MASK) -#define MSCM_CFG0_ICSZ_MASK (0xFF000000U) -#define MSCM_CFG0_ICSZ_SHIFT (24U) -#define MSCM_CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICSZ_SHIFT)) & MSCM_CFG0_ICSZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG0 */ -#define MSCM_CFG0_COUNT (2U) - -/*! @name CFG1 - Processor 0 Configuration Register 1..Processor 1 Configuration Register 1 */ -/*! @{ */ -#define MSCM_CFG1_L2WY_MASK (0xFF0000U) -#define MSCM_CFG1_L2WY_SHIFT (16U) -#define MSCM_CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2WY_SHIFT)) & MSCM_CFG1_L2WY_MASK) -#define MSCM_CFG1_L2SZ_MASK (0xFF000000U) -#define MSCM_CFG1_L2SZ_SHIFT (24U) -#define MSCM_CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2SZ_SHIFT)) & MSCM_CFG1_L2SZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG1 */ -#define MSCM_CFG1_COUNT (2U) - -/*! @name CFG2 - Processor 0 Configuration Register 2..Processor 1 Configuration Register 2 */ -/*! @{ */ -#define MSCM_CFG2_TMUSZ_MASK (0xFF00U) -#define MSCM_CFG2_TMUSZ_SHIFT (8U) -#define MSCM_CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMUSZ_SHIFT)) & MSCM_CFG2_TMUSZ_MASK) -#define MSCM_CFG2_TMLSZ_MASK (0xFF000000U) -#define MSCM_CFG2_TMLSZ_SHIFT (24U) -#define MSCM_CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMLSZ_SHIFT)) & MSCM_CFG2_TMLSZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG2 */ -#define MSCM_CFG2_COUNT (2U) - -/*! @name CFG3 - Processor 0 Configuration Register 3..Processor 1 Configuration Register 3 */ -/*! @{ */ -#define MSCM_CFG3_FPU_MASK (0x1U) -#define MSCM_CFG3_FPU_SHIFT (0U) -/*! FPU - Floating Point Unit - * 0b0..FPU support is not included. - * 0b1..FPU support is included. - */ -#define MSCM_CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK) -#define MSCM_CFG3_SIMD_MASK (0x2U) -#define MSCM_CFG3_SIMD_SHIFT (1U) -/*! SIMD - SIMD/NEON instruction support - * 0b0..SIMD/NEON support is not included. - * 0b1..SIMD/NEON support is included. - */ -#define MSCM_CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SIMD_SHIFT)) & MSCM_CFG3_SIMD_MASK) -#define MSCM_CFG3_JAZ_MASK (0x4U) -#define MSCM_CFG3_JAZ_SHIFT (2U) -/*! JAZ - Jazelle support - * 0b0..Jazelle support is not included. - * 0b1..Jazelle support is included. - */ -#define MSCM_CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_JAZ_SHIFT)) & MSCM_CFG3_JAZ_MASK) -#define MSCM_CFG3_MMU_MASK (0x8U) -#define MSCM_CFG3_MMU_SHIFT (3U) -/*! MMU - Memory Management Unit - * 0b0..MMU support is not included. - * 0b1..MMU support is included. - */ -#define MSCM_CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_MMU_SHIFT)) & MSCM_CFG3_MMU_MASK) -#define MSCM_CFG3_TZ_MASK (0x10U) -#define MSCM_CFG3_TZ_SHIFT (4U) -/*! TZ - Trust Zone - * 0b0..Trust Zone support is not included. - * 0b1..Trust Zone support is included. - */ -#define MSCM_CFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_TZ_SHIFT)) & MSCM_CFG3_TZ_MASK) -#define MSCM_CFG3_CMP_MASK (0x20U) -#define MSCM_CFG3_CMP_SHIFT (5U) -/*! CMP - Core Memory Protection unit - * 0b0..Core Memory Protection is not included. - * 0b1..Core Memory Protection is included. - */ -#define MSCM_CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_CMP_SHIFT)) & MSCM_CFG3_CMP_MASK) -#define MSCM_CFG3_BB_MASK (0x40U) -#define MSCM_CFG3_BB_SHIFT (6U) -/*! BB - Bit Banding - * 0b0..Bit Banding is not supported. - * 0b1..Bit Banding is supported. - */ -#define MSCM_CFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_BB_SHIFT)) & MSCM_CFG3_BB_MASK) -#define MSCM_CFG3_SBP_MASK (0x300U) -#define MSCM_CFG3_SBP_SHIFT (8U) -#define MSCM_CFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SBP_SHIFT)) & MSCM_CFG3_SBP_MASK) -/*! @} */ - -/* The count of MSCM_CFG3 */ -#define MSCM_CFG3_COUNT (2U) - -/*! @name OCMDR0 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR0_OCM1_MASK (0x30U) -#define MSCM_OCMDR0_OCM1_SHIFT (4U) -#define MSCM_OCMDR0_OCM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCM1_SHIFT)) & MSCM_OCMDR0_OCM1_MASK) -#define MSCM_OCMDR0_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR0_OCMPU_SHIFT (12U) -#define MSCM_OCMDR0_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMPU_SHIFT)) & MSCM_OCMDR0_OCMPU_MASK) -#define MSCM_OCMDR0_OCMT_MASK (0xE000U) -#define MSCM_OCMDR0_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR0_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMT_SHIFT)) & MSCM_OCMDR0_OCMT_MASK) -#define MSCM_OCMDR0_RO_MASK (0x10000U) -#define MSCM_OCMDR0_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR0_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_RO_SHIFT)) & MSCM_OCMDR0_RO_MASK) -#define MSCM_OCMDR0_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR0_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR0_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMW_SHIFT)) & MSCM_OCMDR0_OCMW_MASK) -#define MSCM_OCMDR0_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR0_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR0_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZ_SHIFT)) & MSCM_OCMDR0_OCMSZ_MASK) -#define MSCM_OCMDR0_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR0_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR0_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZH_SHIFT)) & MSCM_OCMDR0_OCMSZH_MASK) -#define MSCM_OCMDR0_V_MASK (0x80000000U) -#define MSCM_OCMDR0_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR0_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_V_SHIFT)) & MSCM_OCMDR0_V_MASK) -/*! @} */ - -/*! @name OCMDR1 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR1_OCM1_MASK (0x30U) -#define MSCM_OCMDR1_OCM1_SHIFT (4U) -#define MSCM_OCMDR1_OCM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCM1_SHIFT)) & MSCM_OCMDR1_OCM1_MASK) -#define MSCM_OCMDR1_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR1_OCMPU_SHIFT (12U) -#define MSCM_OCMDR1_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMPU_SHIFT)) & MSCM_OCMDR1_OCMPU_MASK) -#define MSCM_OCMDR1_OCMT_MASK (0xE000U) -#define MSCM_OCMDR1_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR1_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMT_SHIFT)) & MSCM_OCMDR1_OCMT_MASK) -#define MSCM_OCMDR1_RO_MASK (0x10000U) -#define MSCM_OCMDR1_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR1_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_RO_SHIFT)) & MSCM_OCMDR1_RO_MASK) -#define MSCM_OCMDR1_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR1_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR1_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMW_SHIFT)) & MSCM_OCMDR1_OCMW_MASK) -#define MSCM_OCMDR1_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR1_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR1_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZ_SHIFT)) & MSCM_OCMDR1_OCMSZ_MASK) -#define MSCM_OCMDR1_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR1_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR1_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZH_SHIFT)) & MSCM_OCMDR1_OCMSZH_MASK) -#define MSCM_OCMDR1_V_MASK (0x80000000U) -#define MSCM_OCMDR1_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR1_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_V_SHIFT)) & MSCM_OCMDR1_V_MASK) -/*! @} */ - -/*! @name OCMDR2 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR2_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR2_OCMPU_SHIFT (12U) -#define MSCM_OCMDR2_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMPU_SHIFT)) & MSCM_OCMDR2_OCMPU_MASK) -#define MSCM_OCMDR2_OCMT_MASK (0xE000U) -#define MSCM_OCMDR2_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR2_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMT_SHIFT)) & MSCM_OCMDR2_OCMT_MASK) -#define MSCM_OCMDR2_RO_MASK (0x10000U) -#define MSCM_OCMDR2_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR2_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_RO_SHIFT)) & MSCM_OCMDR2_RO_MASK) -#define MSCM_OCMDR2_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR2_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR2_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMW_SHIFT)) & MSCM_OCMDR2_OCMW_MASK) -#define MSCM_OCMDR2_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR2_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR2_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZ_SHIFT)) & MSCM_OCMDR2_OCMSZ_MASK) -#define MSCM_OCMDR2_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR2_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR2_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZH_SHIFT)) & MSCM_OCMDR2_OCMSZH_MASK) -#define MSCM_OCMDR2_V_MASK (0x80000000U) -#define MSCM_OCMDR2_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR2_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_V_SHIFT)) & MSCM_OCMDR2_V_MASK) -/*! @} */ - -/*! @name OCMDR3 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR3_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR3_OCMPU_SHIFT (12U) -#define MSCM_OCMDR3_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMPU_SHIFT)) & MSCM_OCMDR3_OCMPU_MASK) -#define MSCM_OCMDR3_OCMT_MASK (0xE000U) -#define MSCM_OCMDR3_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR3_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMT_SHIFT)) & MSCM_OCMDR3_OCMT_MASK) -#define MSCM_OCMDR3_RO_MASK (0x10000U) -#define MSCM_OCMDR3_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR3_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_RO_SHIFT)) & MSCM_OCMDR3_RO_MASK) -#define MSCM_OCMDR3_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR3_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR3_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMW_SHIFT)) & MSCM_OCMDR3_OCMW_MASK) -#define MSCM_OCMDR3_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR3_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR3_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZ_SHIFT)) & MSCM_OCMDR3_OCMSZ_MASK) -#define MSCM_OCMDR3_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR3_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR3_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZH_SHIFT)) & MSCM_OCMDR3_OCMSZH_MASK) -#define MSCM_OCMDR3_V_MASK (0x80000000U) -#define MSCM_OCMDR3_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR3_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_V_SHIFT)) & MSCM_OCMDR3_V_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MSCM_Register_Masks */ - - -/* MSCM - Peripheral instance base addresses */ -/** Peripheral MSCM base address */ -#define MSCM_BASE (0x40001000u) -/** Peripheral MSCM base pointer */ -#define MSCM ((MSCM_Type *)MSCM_BASE) -/** Array initializer of MSCM peripheral base addresses */ -#define MSCM_BASE_ADDRS { MSCM_BASE } -/** Array initializer of MSCM peripheral base pointers */ -#define MSCM_BASE_PTRS { MSCM } - -/*! - * @} - */ /* end of group MSCM_Peripheral_Access_Layer */ - -/*! - * @brief Core boot mode. - */ -typedef enum _mu_core_boot_mode -{ - kMU_CoreBootFromDflashBase = 0x00U, /*!< Boot from Dflash base. */ - kMU_CoreBootFromCore1RamBase = 0x02U, /*!< Boot from ZERO RISCY RAM base. */ -} mu_core_boot_mode_t; -/*! - * @brief Power mode on the other side definition. - */ -typedef enum _mu_power_mode -{ - kMU_PowerModeRun = 0x00U, /*!< Run mode. */ - kMU_PowerModeCoo = 0x01U, /*!< COO mode. */ - kMU_PowerModeWait = 0x02U, /*!< WAIT mode. */ - kMU_PowerModeStop = 0x03U, /*!< STOP/VLPS mode. */ - kMU_PowerModeDsm = 0x04U /*!< DSM: LLS/VLLS mode. */ -} mu_power_mode_t; - - -/* ---------------------------------------------------------------------------- - -- MU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer - * @{ - */ - -/** MU - Register Layout Typedef */ -typedef struct { - __I uint32_t VER; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[24]; - __IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t SR; /**< Status Register, offset: 0x60 */ - __IO uint32_t CR; /**< Control Register, offset: 0x64 */ - __IO uint32_t CCR; /**< Core Control Register, offset: 0x68 */ -} MU_Type; - -/* ---------------------------------------------------------------------------- - -- MU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MU_Register_Masks MU Register Masks - * @{ - */ - -/*! @name VER - Version ID Register */ -/*! @{ */ -#define MU_VER_FEATURE_MASK (0xFFFFU) -#define MU_VER_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB. - * 0b000000000000xx1x..RAIP/RAIE register bits are implemented. - * 0b000000000000xxx0..Standard features implemented - */ -#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) -#define MU_VER_MINOR_MASK (0xFF0000U) -#define MU_VER_MINOR_SHIFT (16U) -#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) -#define MU_VER_MAJOR_MASK (0xFF000000U) -#define MU_VER_MAJOR_SHIFT (24U) -#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) -/*! @} */ - -/*! @name PAR - Parameter Register */ -/*! @{ */ -#define MU_PAR_PARAMETER_MASK (0xFFFFFFFFU) -#define MU_PAR_PARAMETER_SHIFT (0U) -#define MU_PAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK) -/*! @} */ - -/*! @name TR - Transmit Register */ -/*! @{ */ -#define MU_TR_DATA_MASK (0xFFFFFFFFU) -#define MU_TR_DATA_SHIFT (0U) -#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK) -/*! @} */ - -/* The count of MU_TR */ -#define MU_TR_COUNT (4U) - -/*! @name RR - Receive Register */ -/*! @{ */ -#define MU_RR_DATA_MASK (0xFFFFFFFFU) -#define MU_RR_DATA_SHIFT (0U) -#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK) -/*! @} */ - -/* The count of MU_RR */ -#define MU_RR_COUNT (4U) - -/*! @name SR - Status Register */ -/*! @{ */ -#define MU_SR_Fn_MASK (0x7U) -#define MU_SR_Fn_SHIFT (0U) -/*! Fn - Fn - * 0b000..Fn bit in the MUB CR register is written 0 (default). - * 0b001..Fn bit in the MUB CR register is written 1. - */ -#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) -#define MU_SR_NMIC_MASK (0x8U) -#define MU_SR_NMIC_SHIFT (3U) -/*! NMIC - NMIC - * 0b0..Default - * 0b1..Writing "1" clears the NMI bit in the MUB CR register. - */ -#define MU_SR_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK) -#define MU_SR_EP_MASK (0x10U) -#define MU_SR_EP_SHIFT (4U) -/*! EP - EP - * 0b0..The MUA side event is not pending (default). - * 0b1..The MUA side event is pending. - */ -#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) -#define MU_SR_HRIP_MASK (0x80U) -#define MU_SR_HRIP_SHIFT (7U) -/*! HRIP - HRIP - * 0b0..MUB didn't issue hardware reset to Processor A - * 0b1..MUB had initiated a hardware reset to Processor A through HR bit. - */ -#define MU_SR_HRIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_HRIP_SHIFT)) & MU_SR_HRIP_MASK) -#define MU_SR_FUP_MASK (0x100U) -#define MU_SR_FUP_SHIFT (8U) -/*! FUP - FUP - * 0b0..No flags updated, initiated by the MUA, in progress (default) - * 0b1..MUA initiated flags update, processing - */ -#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) -#define MU_SR_RDIP_MASK (0x200U) -#define MU_SR_RDIP_SHIFT (9U) -/*! RDIP - RDIP - * 0b0..Processor B did not exit reset - * 0b1..Processor B exited from reset - */ -#define MU_SR_RDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK) -#define MU_SR_RAIP_MASK (0x400U) -#define MU_SR_RAIP_SHIFT (10U) -/*! RAIP - RAIP - * 0b0..Processor B did not enter reset - * 0b1..Processor B entered reset - */ -#define MU_SR_RAIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK) -#define MU_SR_MURIP_MASK (0x800U) -#define MU_SR_MURIP_SHIFT (11U) -/*! MURIP - MURIP - * 0b0..Processor B did not issue MU reset - * 0b1..Processor B issued MU reset - */ -#define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) -#define MU_SR_PM_MASK (0x7000U) -#define MU_SR_PM_SHIFT (12U) -/*! PM - PM - * 0b000..The MUB processor is in Run Mode. - * 0b001..The MUB processor is in COO Mode. - * 0b010..The MUB processor is in WAIT Mode. - * 0b011..The MUB processor is in STOP/VLPS Mode. - * 0b100..The MUB processor is in LLS/VLLS Mode. - */ -#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK) -#define MU_SR_TEn_MASK (0xF00000U) -#define MU_SR_TEn_SHIFT (20U) -/*! TEn - TEn - * 0b0000..MUA TRn register is not empty. - * 0b0001..MUA TRn register is empty (default). - */ -#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) -#define MU_SR_RFn_MASK (0xF000000U) -#define MU_SR_RFn_SHIFT (24U) -/*! RFn - RFn - * 0b0000..MUA RRn register is not full (default). - * 0b0001..MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA. - */ -#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) -#define MU_SR_GIPn_MASK (0xF0000000U) -#define MU_SR_GIPn_SHIFT (28U) -/*! GIPn - GIPn - * 0b0000..MUA general purpose interrupt n is not pending. (default) - * 0b0001..MUA general purpose interrupt n is pending. - */ -#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define MU_CR_Fn_MASK (0x7U) -#define MU_CR_Fn_SHIFT (0U) -/*! Fn - Fn - * 0b000..Clears the Fn bit in the SR register. - * 0b001..Sets the Fn bit in the SR register. - */ -#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) -#define MU_CR_NMI_MASK (0x8U) -#define MU_CR_NMI_SHIFT (3U) -/*! NMI - NMI - * 0b0..Non-maskable interrupt is not issued to the Processor B by the Processor A (default). - * 0b1..Non-maskable interrupt is issued to the Processor B by the Processor A. - */ -#define MU_CR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK) -#define MU_CR_MUR_MASK (0x20U) -#define MU_CR_MUR_SHIFT (5U) -/*! MUR - MUR - * 0b0..N/A. Self clearing bit (default). - * 0b1..Asserts the MU reset. - */ -#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) -#define MU_CR_RDIE_MASK (0x40U) -#define MU_CR_RDIE_SHIFT (6U) -/*! RDIE - RDIE - * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. - * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. - */ -#define MU_CR_RDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK) -#define MU_CR_HRIE_MASK (0x80U) -#define MU_CR_HRIE_SHIFT (7U) -/*! HRIE - Processor A hardware reset interrupt enable - * 0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A. - * 0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A. - */ -#define MU_CR_HRIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRIE_SHIFT)) & MU_CR_HRIE_MASK) -#define MU_CR_MURIE_MASK (0x800U) -#define MU_CR_MURIE_SHIFT (11U) -/*! MURIE - MURIE - * 0b0..Disables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB. - * 0b1..Enables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB. - */ -#define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) -#define MU_CR_RAIE_MASK (0x1000U) -#define MU_CR_RAIE_SHIFT (12U) -/*! RAIE - RAIE - * 0b0..Disables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion. - * 0b1..Enables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion. - */ -#define MU_CR_RAIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK) -#define MU_CR_GIRn_MASK (0xF0000U) -#define MU_CR_GIRn_SHIFT (16U) -/*! GIRn - GIRn - * 0b0000..MUA General Interrupt n is not requested to the MUB (default). - * 0b0001..MUA General Interrupt n is requested to the MUB. - */ -#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) -#define MU_CR_TIEn_MASK (0xF00000U) -#define MU_CR_TIEn_SHIFT (20U) -/*! TIEn - TIEn - * 0b0000..Disables MUA Transmit Interrupt n. (default) - * 0b0001..Enables MUA Transmit Interrupt n. - */ -#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) -#define MU_CR_RIEn_MASK (0xF000000U) -#define MU_CR_RIEn_SHIFT (24U) -/*! RIEn - RIEn - * 0b0000..Disables MUA Receive Interrupt n. (default) - * 0b0001..Enables MUA Receive Interrupt n. - */ -#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) -#define MU_CR_GIEn_MASK (0xF0000000U) -#define MU_CR_GIEn_SHIFT (28U) -/*! GIEn - GIEn - * 0b0000..Disables MUA General Interrupt n. (default) - * 0b0001..Enables MUA General Interrupt n. - */ -#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) -/*! @} */ - -/*! @name CCR - Core Control Register */ -/*! @{ */ -#define MU_CCR_HR_MASK (0x1U) -#define MU_CCR_HR_SHIFT (0U) -/*! HR - HR - * 0b0..De-assert Hardware reset to the Processor B. (default) - * 0b1..Assert Hardware reset to the Processor B. - */ -#define MU_CCR_HR(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_HR_SHIFT)) & MU_CCR_HR_MASK) -#define MU_CCR_HRM_MASK (0x2U) -#define MU_CCR_HRM_SHIFT (1U) -/*! HRM - When set, HR bit in MUB CCR has no effect - * 0b0..HR bit in MUB CCR is not masked, enables the hardware reset to the Processor A (default after hardware reset). - * 0b1..HR bit in MUB CCR is masked, disables the hardware reset request to the Processor A. - */ -#define MU_CCR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_HRM_SHIFT)) & MU_CCR_HRM_MASK) -#define MU_CCR_RSTH_MASK (0x4U) -#define MU_CCR_RSTH_SHIFT (2U) -/*! RSTH - Processor B Reset Hold - * 0b0..Release Processor B from reset - * 0b1..Hold Processor B in reset - */ -#define MU_CCR_RSTH(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_RSTH_SHIFT)) & MU_CCR_RSTH_MASK) -#define MU_CCR_CLKE_MASK (0x8U) -#define MU_CCR_CLKE_SHIFT (3U) -/*! CLKE - MUB clock enable - * 0b0..MUB platform clock gated when MUB-side enters a stop mode. - * 0b1..MUB platform clock kept running after MUB-side enters a stop mode, until MUA also enters a stop mode. - */ -#define MU_CCR_CLKE(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_CLKE_SHIFT)) & MU_CCR_CLKE_MASK) -#define MU_CCR_BOOT_MASK (0x30U) -#define MU_CCR_BOOT_SHIFT (4U) -/*! BOOT - Slave Processor B Boot Config. - * 0b00..Boot from Dflash base - * 0b01..Reserved - * 0b10..Boot from CM0+ RAM base - * 0b11..Reserved - */ -#define MU_CCR_BOOT(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_BOOT_SHIFT)) & MU_CCR_BOOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MU_Register_Masks */ - - -/* MU - Peripheral instance base addresses */ -/** Peripheral MUA base address */ -#define MUA_BASE (0x40025000u) -/** Peripheral MUA base pointer */ -#define MUA ((MU_Type *)MUA_BASE) -/** Array initializer of MU peripheral base addresses */ -#define MU_BASE_ADDRS { MUA_BASE } -/** Array initializer of MU peripheral base pointers */ -#define MU_BASE_PTRS { MUA } -/** Interrupt vectors for the MU peripheral type */ -#define MU_IRQS { MUA_IRQn } - -/*! - * @} - */ /* end of group MU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PCC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer - * @{ - */ - -/** PCC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CLKCFG[130]; /**< PCC MSCM Register..PCC EXT_CLK Register, array offset: 0x0, array step: 0x4 */ -} PCC_Type; - -/* ---------------------------------------------------------------------------- - -- PCC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PCC_Register_Masks PCC Register Masks - * @{ - */ - -/*! @name CLKCFG - PCC MSCM Register..PCC EXT_CLK Register */ -/*! @{ */ -#define PCC_CLKCFG_PCD_MASK (0x7U) -#define PCC_CLKCFG_PCD_SHIFT (0U) -/*! PCD - Peripheral Clock Divider Select - * 0b000..Divide by 1. - * 0b001..Divide by 2. - * 0b010..Divide by 3. - * 0b011..Divide by 4. - * 0b100..Divide by 5. - * 0b101..Divide by 6. - * 0b110..Divide by 7. - * 0b111..Divide by 8. - */ -#define PCC_CLKCFG_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK) -#define PCC_CLKCFG_FRAC_MASK (0x8U) -#define PCC_CLKCFG_FRAC_SHIFT (3U) -/*! FRAC - Peripheral Clock Divider Fraction - * 0b0..Fractional value is 0. - * 0b1..Fractional value is 1. - */ -#define PCC_CLKCFG_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK) -#define PCC_CLKCFG_PCS_MASK (0x7000000U) -#define PCC_CLKCFG_PCS_SHIFT (24U) -/*! PCS - Peripheral Clock Source Select - * 0b000..Clock is off. An external clock can be enabled for this peripheral. - * 0b001..Clock option 1 - * 0b010..Clock option 2 - * 0b011..Clock option 3 - * 0b100..Clock option 4 - * 0b101..Clock option 5 - * 0b110..Clock option 6 - * 0b111..Clock option 7 - */ -#define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK) -#define PCC_CLKCFG_INUSE_MASK (0x20000000U) -#define PCC_CLKCFG_INUSE_SHIFT (29U) -/*! INUSE - In use flag - * 0b0..Peripheral is not being used. - * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. - */ -#define PCC_CLKCFG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK) -#define PCC_CLKCFG_CGC_MASK (0x40000000U) -#define PCC_CLKCFG_CGC_SHIFT (30U) -/*! CGC - Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled. The current clock selection and divider options are locked. - */ -#define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK) -#define PCC_CLKCFG_PR_MASK (0x80000000U) -#define PCC_CLKCFG_PR_SHIFT (31U) -/*! PR - Present - * 0b0..Peripheral is not present. - * 0b1..Peripheral is present. - */ -#define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK) -/*! @} */ - -/* The count of PCC_CLKCFG */ -#define PCC_CLKCFG_COUNT (130U) - - -/*! - * @} - */ /* end of group PCC_Register_Masks */ - - -/* PCC - Peripheral instance base addresses */ -/** Peripheral PCC0 base address */ -#define PCC0_BASE (0x4002B000u) -/** Peripheral PCC0 base pointer */ -#define PCC0 ((PCC_Type *)PCC0_BASE) -/** Peripheral PCC1 base address */ -#define PCC1_BASE (0x41027000u) -/** Peripheral PCC1 base pointer */ -#define PCC1 ((PCC_Type *)PCC1_BASE) -/** Array initializer of PCC peripheral base addresses */ -#define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE } -/** Array initializer of PCC peripheral base pointers */ -#define PCC_BASE_PTRS { PCC0, PCC1 } -#define PCC_INSTANCE_MASK (0xFu) -#define PCC_INSTANCE_SHIFT (12u) -#define PCC_PERIPHERAL_MASK (0xFFFu) -#define PCC_PERIPHERAL_SHIFT (0u) -#define PCC_INSTANCE_0 (0u) -#define PCC_INSTANCE_1 (1u) - -#define PCC_MSCM_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 1U) -#define PCC_AXBS0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 4U) -#define PCC_DMA0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U) -#define PCC_FLEXBUS_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 12U) -#define PCC_XRDC_MGR_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 20U) -#define PCC0_XRDC_PAC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U) -#define PCC0_XRDC_MRC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U) -#define PCC_SEMA42_0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U) -#define PCC_DMAMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U) -#define PCC_EWM_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U) -#define PCC_MUA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37U) -#define PCC_CRC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 47U) -#define PCC_LPIT0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48U) -#define PCC_TPM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U) -#define PCC_TPM1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U) -#define PCC_TPM2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U) -#define PCC_EMVSIM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56U) -#define PCC_FLEXIO0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 57U) -#define PCC_LPI2C0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 58U) -#define PCC_LPI2C1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 59U) -#define PCC_LPI2C2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60U) -#define PCC_I2S0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61U) -#define PCC_USDHC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62U) -#define PCC_LPSPI0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 63U) -#define PCC_LPSPI1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64U) -#define PCC_LPSPI2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65U) -#define PCC_LPUART0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66U) -#define PCC_LPUART1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 67U) -#define PCC_LPUART2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68U) -#define PCC_USB0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69U) -#define PCC_PORTA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70U) -#define PCC_PORTB_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 71U) -#define PCC_PORTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 72U) -#define PCC_PORTD_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 73U) -#define PCC_ADC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74U) -#define PCC_LPDAC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 76U) -#define PCC_VREF_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 77U) -#define PCC_TRACE_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U) -#define PCC_DMA1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U) -#define PCC_GPIOE_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 15U) -#define PCC1_XRDC_PAC_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U) -#define PCC1_XRDC_MRC_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U) -#define PCC_SEMA42_1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U) -#define PCC_DMAMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U) -#define PCC_INTMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U) -#define PCC_MUB_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36U) -#define PCC_CAU3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 40U) -#define PCC_TRNG_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 41U) -#define PCC_LPIT1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 42U) -#define PCC_TPM3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45U) -#define PCC_LPI2C3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46U) -#define PCC_LPSPI3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U) -#define PCC_LPUART3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U) -#define PCC_PORTE_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U) -#define PCC_MTB_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U) -#define PCC_EXT_CLK_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 129U) -#define PCC_MSCM (PCC0->CLKCFG[1]) -#define PCC_AXBS0 (PCC0->CLKCFG[4]) -#define PCC_DMA0 (PCC0->CLKCFG[8]) -#define PCC_FLEXBUS (PCC0->CLKCFG[12]) -#define PCC_XRDC_MGR (PCC0->CLKCFG[20]) -#define PCC0_XRDC_PAC (PCC0->CLKCFG[22]) -#define PCC0_XRDC_MRC (PCC0->CLKCFG[23]) -#define PCC_SEMA42_0 (PCC0->CLKCFG[27]) -#define PCC_DMAMUX0 (PCC0->CLKCFG[33]) -#define PCC_EWM (PCC0->CLKCFG[34]) -#define PCC_MUA (PCC0->CLKCFG[37]) -#define PCC_CRC0 (PCC0->CLKCFG[47]) -#define PCC_LPIT0 (PCC0->CLKCFG[48]) -#define PCC_TPM0 (PCC0->CLKCFG[53]) -#define PCC_TPM1 (PCC0->CLKCFG[54]) -#define PCC_TPM2 (PCC0->CLKCFG[55]) -#define PCC_EMVSIM0 (PCC0->CLKCFG[56]) -#define PCC_FLEXIO0 (PCC0->CLKCFG[57]) -#define PCC_LPI2C0 (PCC0->CLKCFG[58]) -#define PCC_LPI2C1 (PCC0->CLKCFG[59]) -#define PCC_LPI2C2 (PCC0->CLKCFG[60]) -#define PCC_I2S0 (PCC0->CLKCFG[61]) -#define PCC_USDHC0 (PCC0->CLKCFG[62]) -#define PCC_LPSPI0 (PCC0->CLKCFG[63]) -#define PCC_LPSPI1 (PCC0->CLKCFG[64]) -#define PCC_LPSPI2 (PCC0->CLKCFG[65]) -#define PCC_LPUART0 (PCC0->CLKCFG[66]) -#define PCC_LPUART1 (PCC0->CLKCFG[67]) -#define PCC_LPUART2 (PCC0->CLKCFG[68]) -#define PCC_USB0 (PCC0->CLKCFG[69]) -#define PCC_PORTA (PCC0->CLKCFG[70]) -#define PCC_PORTB (PCC0->CLKCFG[71]) -#define PCC_PORTC (PCC0->CLKCFG[72]) -#define PCC_PORTD (PCC0->CLKCFG[73]) -#define PCC_ADC0 (PCC0->CLKCFG[74]) -#define PCC_LPDAC0 (PCC0->CLKCFG[76]) -#define PCC_VREF (PCC0->CLKCFG[77]) -#define PCC_TRACE (PCC0->CLKCFG[128]) -#define PCC_DMA1 (PCC1->CLKCFG[8]) -#define PCC_GPIOE (PCC1->CLKCFG[15]) -#define PCC1_XRDC_PAC (PCC1->CLKCFG[22]) -#define PCC1_XRDC_MRC (PCC1->CLKCFG[23]) -#define PCC_SEMA42_1 (PCC1->CLKCFG[27]) -#define PCC_DMAMUX1 (PCC1->CLKCFG[33]) -#define PCC_INTMUX1 (PCC1->CLKCFG[34]) -#define PCC_MUB (PCC1->CLKCFG[36]) -#define PCC_CAU3 (PCC1->CLKCFG[40]) -#define PCC_TRNG (PCC1->CLKCFG[41]) -#define PCC_LPIT1 (PCC1->CLKCFG[42]) -#define PCC_TPM3 (PCC1->CLKCFG[45]) -#define PCC_LPI2C3 (PCC1->CLKCFG[46]) -#define PCC_LPSPI3 (PCC1->CLKCFG[53]) -#define PCC_LPUART3 (PCC1->CLKCFG[54]) -#define PCC_PORTE (PCC1->CLKCFG[55]) -#define PCC_MTB (PCC1->CLKCFG[128]) -#define PCC_EXT_CLK (PCC1->CLKCFG[129]) - - -/*! - * @} - */ /* end of group PCC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PORT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer - * @{ - */ - -/** PORT - Register Layout Typedef */ -typedef struct { - __IO uint32_t PCR[32]; /**< Pin Control Register 0..Pin Control Register 30, array offset: 0x0, array step: 0x4 */ - __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ - __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ - __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ - __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ - uint8_t RESERVED_0[16]; - __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ - uint8_t RESERVED_1[28]; - __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ - __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ - __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ -} PORT_Type; - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/*! @name PCR - Pin Control Register 0..Pin Control Register 30 */ -/*! @{ */ -#define PORT_PCR_PS_MASK (0x1U) -#define PORT_PCR_PS_SHIFT (0U) -/*! PS - Pull Select - * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. - * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. - */ -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) -#define PORT_PCR_PE_MASK (0x2U) -#define PORT_PCR_PE_SHIFT (1U) -/*! PE - Pull Enable - * 0b0..Internal pull resistor is not enabled on the corresponding pin. - * 0b1..Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input. - */ -#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) -#define PORT_PCR_SRE_MASK (0x4U) -#define PORT_PCR_SRE_SHIFT (2U) -/*! SRE - Slew Rate Enable - * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. - * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. - */ -#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) -#define PORT_PCR_PFE_MASK (0x10U) -#define PORT_PCR_PFE_SHIFT (4U) -/*! PFE - Passive Filter Enable - * 0b0..Passive input filter is disabled on the corresponding pin. - * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. - */ -#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) -#define PORT_PCR_ODE_MASK (0x20U) -#define PORT_PCR_ODE_SHIFT (5U) -/*! ODE - Open Drain Enable - * 0b0..Open drain output is disabled on the corresponding pin. - * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. - */ -#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) -#define PORT_PCR_DSE_MASK (0x40U) -#define PORT_PCR_DSE_SHIFT (6U) -/*! DSE - Drive Strength Enable - * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. - * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. - */ -#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0x700U) -#define PORT_PCR_MUX_SHIFT (8U) -/*! MUX - Pin Mux Control - * 0b000..Pin disabled (Alternative 0) (analog). - * 0b001..Alternative 1 (GPIO). - * 0b010..Alternative 2 (chip-specific). - * 0b011..Alternative 3 (chip-specific). - * 0b100..Alternative 4 (chip-specific). - * 0b101..Alternative 5 (chip-specific). - * 0b110..Alternative 6 (chip-specific). - * 0b111..Alternative 7 (chip-specific). - */ -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) -#define PORT_PCR_LK_MASK (0x8000U) -#define PORT_PCR_LK_SHIFT (15U) -/*! LK - Lock Register - * 0b0..Pin Control Register is not locked. - * 0b1..Pin Control Register is locked and cannot be updated until the next system reset. - */ -#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) -#define PORT_PCR_IRQC_MASK (0xF0000U) -#define PORT_PCR_IRQC_SHIFT (16U) -/*! IRQC - Interrupt Configuration - * 0b0000..Interrupt Status Flag (ISF) is disabled. - * 0b0001..ISF flag and DMA request on rising edge. - * 0b0010..ISF flag and DMA request on falling edge. - * 0b0011..ISF flag and DMA request on either edge. - * 0b0100..Reserved. - * 0b0101..Flag sets on rising edge. - * 0b0110..Flag sets on falling edge. - * 0b0111..Flag sets on either edge. - * 0b1000..ISF flag and Interrupt when logic 0. - * 0b1001..ISF flag and Interrupt on rising-edge. - * 0b1010..ISF flag and Interrupt on falling-edge. - * 0b1011..ISF flag and Interrupt on either edge. - * 0b1100..ISF flag and Interrupt when logic 1. - * 0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] - * 0b1110..Enable active low trigger output, flag is disabled. - * 0b1111..Reserved. - */ -#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) -#define PORT_PCR_ISF_MASK (0x1000000U) -#define PORT_PCR_ISF_SHIFT (24U) -/*! ISF - Interrupt Status Flag - * 0b0..Configured interrupt is not detected. - * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. - */ -#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) -/*! @} */ - -/* The count of PORT_PCR */ -#define PORT_PCR_COUNT (32U) - -/*! @name GPCLR - Global Pin Control Low Register */ -/*! @{ */ -#define PORT_GPCLR_GPWD_MASK (0xFFFFU) -#define PORT_GPCLR_GPWD_SHIFT (0U) -#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) -#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCLR_GPWE_SHIFT (16U) -#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) -/*! @} */ - -/*! @name GPCHR - Global Pin Control High Register */ -/*! @{ */ -#define PORT_GPCHR_GPWD_MASK (0xFFFFU) -#define PORT_GPCHR_GPWD_SHIFT (0U) -#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) -#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCHR_GPWE_SHIFT (16U) -#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) -/*! @} */ - -/*! @name GICLR - Global Interrupt Control Low Register */ -/*! @{ */ -#define PORT_GICLR_GIWE_MASK (0xFFFFU) -#define PORT_GICLR_GIWE_SHIFT (0U) -#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) -#define PORT_GICLR_GIWD_MASK (0xFFFF0000U) -#define PORT_GICLR_GIWD_SHIFT (16U) -#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) -/*! @} */ - -/*! @name GICHR - Global Interrupt Control High Register */ -/*! @{ */ -#define PORT_GICHR_GIWE_MASK (0xFFFFU) -#define PORT_GICHR_GIWE_SHIFT (0U) -#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) -#define PORT_GICHR_GIWD_MASK (0xFFFF0000U) -#define PORT_GICHR_GIWD_SHIFT (16U) -#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) -/*! @} */ - -/*! @name ISFR - Interrupt Status Flag Register */ -/*! @{ */ -#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) -#define PORT_ISFR_ISF_SHIFT (0U) -#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) -/*! @} */ - -/*! @name DFER - Digital Filter Enable Register */ -/*! @{ */ -#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) -#define PORT_DFER_DFE_SHIFT (0U) -#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) -/*! @} */ - -/*! @name DFCR - Digital Filter Clock Register */ -/*! @{ */ -#define PORT_DFCR_CS_MASK (0x1U) -#define PORT_DFCR_CS_SHIFT (0U) -/*! CS - Clock Source - * 0b0..Digital filters are clocked by the bus clock. - * 0b1..Digital filters are clocked by the 8 clock. - */ -#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) -/*! @} */ - -/*! @name DFWR - Digital Filter Width Register */ -/*! @{ */ -#define PORT_DFWR_FILT_MASK (0x1FU) -#define PORT_DFWR_FILT_SHIFT (0U) -#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PORT_Register_Masks */ - - -/* PORT - Peripheral instance base addresses */ -/** Peripheral PORTA base address */ -#define PORTA_BASE (0x40046000u) -/** Peripheral PORTA base pointer */ -#define PORTA ((PORT_Type *)PORTA_BASE) -/** Peripheral PORTB base address */ -#define PORTB_BASE (0x40047000u) -/** Peripheral PORTB base pointer */ -#define PORTB ((PORT_Type *)PORTB_BASE) -/** Peripheral PORTC base address */ -#define PORTC_BASE (0x40048000u) -/** Peripheral PORTC base pointer */ -#define PORTC ((PORT_Type *)PORTC_BASE) -/** Peripheral PORTD base address */ -#define PORTD_BASE (0x40049000u) -/** Peripheral PORTD base pointer */ -#define PORTD ((PORT_Type *)PORTD_BASE) -/** Peripheral PORTE base address */ -#define PORTE_BASE (0x41037000u) -/** Peripheral PORTE base pointer */ -#define PORTE ((PORT_Type *)PORTE_BASE) -/** Array initializer of PORT peripheral base addresses */ -#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } -/** Array initializer of PORT peripheral base pointers */ -#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } -/** Interrupt vectors for the PORT peripheral type */ -#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } - -/*! - * @} - */ /* end of group PORT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer - * @{ - */ - -/** RSIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Radio System Control, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MISC; /**< Radio Miscellaneous, offset: 0x10 */ - __IO uint32_t POWER; /**< RSIM Power Control, offset: 0x14 */ - __IO uint32_t SW_CONFIG; /**< Radio Software Configuration, offset: 0x18 */ - uint8_t RESERVED_1[228]; - __I uint32_t DSM_TIMER; /**< Deep Sleep Timer, offset: 0x100 */ - __IO uint32_t DSM_CONTROL; /**< Deep Sleep Timer Control, offset: 0x104 */ - __IO uint32_t DSM_WAKEUP; /**< Deep Sleep Wakeup Sequence, offset: 0x108 */ - __I uint32_t WOR_DURATION; /**< WOR Deep Sleep Duration, offset: 0x10C */ - __IO uint32_t WOR_WAKE; /**< WOR Deep Sleep Wake Time, offset: 0x110 */ - uint8_t RESERVED_2[8]; - __IO uint32_t MAN_SLEEP; /**< MAN Deep Sleep Time, offset: 0x11C */ - __IO uint32_t MAN_WAKE; /**< MAN Deep Sleep Wake Time, offset: 0x120 */ - __IO uint32_t RF_OSC_CTRL; /**< Radio Oscillator Control, offset: 0x124 */ - __IO uint32_t ANA_TEST; /**< Radio Analog Test Registers, offset: 0x128 */ - __IO uint32_t ANA_TRIM; /**< Radio Analog Trim Registers, offset: 0x12C */ -} RSIM_Type; - -/* ---------------------------------------------------------------------------- - -- RSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Register_Masks RSIM Register Masks - * @{ - */ - -/*! @name CONTROL - Radio System Control */ -/*! @{ */ -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK (0x1U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT (0U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK (0x2U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT (1U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK (0x10U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT (4U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK (0x20U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT (5U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK) -#define RSIM_CONTROL_RF_OSC_EN_MASK (0x100U) -#define RSIM_CONTROL_RF_OSC_EN_SHIFT (8U) -#define RSIM_CONTROL_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U) -/*! RADIO_GASKET_BYPASS_OVRD - Radio Gasket Bypass Override - * 0b0..XCVR and Link Layer Register Clock is the RF Ref Osc Clock - * 0b1..XCVR and Link Layer Register Clock is the SoC IPG Clock - */ -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK (0x4000U) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT (14U) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT)) & RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK (0x8000U) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT (15U) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK (0x10000U) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT (16U) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK (0x40000U) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT (18U) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK (0x80000U) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT (19U) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK) -#define RSIM_CONTROL_BLE_DSM_EXIT_MASK (0x100000U) -#define RSIM_CONTROL_BLE_DSM_EXIT_SHIFT (20U) -#define RSIM_CONTROL_BLE_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_DSM_EXIT_SHIFT)) & RSIM_CONTROL_BLE_DSM_EXIT_MASK) -#define RSIM_CONTROL_WOR_DSM_EXIT_MASK (0x200000U) -#define RSIM_CONTROL_WOR_DSM_EXIT_SHIFT (21U) -#define RSIM_CONTROL_WOR_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_WOR_DSM_EXIT_SHIFT)) & RSIM_CONTROL_WOR_DSM_EXIT_MASK) -#define RSIM_CONTROL_RF_OSC_READY_MASK (0x1000000U) -#define RSIM_CONTROL_RF_OSC_READY_SHIFT (24U) -#define RSIM_CONTROL_RF_OSC_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK (0x2000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT (25U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK (0x4000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT (26U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK) -#define RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK (0x8000000U) -#define RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT (27U) -/*! RSIM_CGC_BLE_EN - BLE Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_BLE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK (0x10000000U) -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT (28U) -/*! RSIM_CGC_XCVR_EN - XCVR Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK (0x20000000U) -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT (29U) -/*! RSIM_CGC_ZIG_EN - ZIG Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK (0x80000000U) -#define RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT (31U) -/*! RSIM_CGC_GEN_EN - GEN Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK) -/*! @} */ - -/*! @name MISC - Radio Miscellaneous */ -/*! @{ */ -#define RSIM_MISC_RADIO_VERSION_MASK (0xFF000000U) -#define RSIM_MISC_RADIO_VERSION_SHIFT (24U) -#define RSIM_MISC_RADIO_VERSION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK) -/*! @} */ - -/*! @name POWER - RSIM Power Control */ -/*! @{ */ -#define RSIM_POWER_RADIO_STOP_MODE_STAT_MASK (0x7U) -#define RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT (0U) -#define RSIM_POWER_RADIO_STOP_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_STAT_MASK) -#define RSIM_POWER_SPM_STOP_ACK_STAT_MASK (0x8U) -#define RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT (3U) -#define RSIM_POWER_SPM_STOP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_STOP_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK (0x70U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT (4U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK (0x80U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT (7U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK) -#define RSIM_POWER_RADIO_STOP_ACK_STAT_MASK (0x100U) -#define RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT (8U) -#define RSIM_POWER_RADIO_STOP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_STOP_REQ_STAT_MASK (0x200U) -#define RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT (9U) -#define RSIM_POWER_RADIO_STOP_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_REQ_STAT_MASK) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK (0x400U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT (10U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK (0x800U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT (11U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK) -#define RSIM_POWER_RF_OSC_EN_OVRD_MASK (0x1000U) -#define RSIM_POWER_RF_OSC_EN_OVRD_SHIFT (12U) -#define RSIM_POWER_RF_OSC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_MASK) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK (0x2000U) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT (13U) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK) -#define RSIM_POWER_RF_POWER_EN_OVRD_MASK (0x4000U) -#define RSIM_POWER_RF_POWER_EN_OVRD_SHIFT (14U) -#define RSIM_POWER_RF_POWER_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_MASK) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK (0x8000U) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT (15U) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK) -#define RSIM_POWER_SPM_ISO_STAT_MASK (0x10000U) -#define RSIM_POWER_SPM_ISO_STAT_SHIFT (16U) -#define RSIM_POWER_SPM_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_ISO_STAT_SHIFT)) & RSIM_POWER_SPM_ISO_STAT_MASK) -#define RSIM_POWER_RADIO_ISO_STAT_MASK (0x20000U) -#define RSIM_POWER_RADIO_ISO_STAT_SHIFT (17U) -#define RSIM_POWER_RADIO_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_ISO_STAT_SHIFT)) & RSIM_POWER_RADIO_ISO_STAT_MASK) -#define RSIM_POWER_RSIM_ISO_OVRD_MASK (0x40000U) -#define RSIM_POWER_RSIM_ISO_OVRD_SHIFT (18U) -#define RSIM_POWER_RSIM_ISO_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_MASK) -#define RSIM_POWER_RSIM_ISO_OVRD_EN_MASK (0x80000U) -#define RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT (19U) -#define RSIM_POWER_RSIM_ISO_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_EN_MASK) -#define RSIM_POWER_SPM_RUN_ACK_STAT_MASK (0x100000U) -#define RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT (20U) -#define RSIM_POWER_SPM_RUN_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_RUN_REQ_STAT_MASK (0x200000U) -#define RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT (21U) -#define RSIM_POWER_RADIO_RUN_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_RUN_REQ_STAT_MASK) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK (0x400000U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT (22U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK (0x800000U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT (23U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK (0x1000000U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT (24U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK (0x2000000U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT (25U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK (0x4000000U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT (26U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK (0x8000000U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT (27U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK) -#define RSIM_POWER_RSIM_STOP_MODE_MASK (0x70000000U) -#define RSIM_POWER_RSIM_STOP_MODE_SHIFT (28U) -/*! RSIM_STOP_MODE - RSIM lowest allowed Stop Mode - * 0b000..Reserved - * 0b001..Reserved - * 0b011..RLLS mode (Radio State Retention mode) - * 0b111..RVLLS mode (This is the POR setting) - */ -#define RSIM_POWER_RSIM_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_MODE_SHIFT)) & RSIM_POWER_RSIM_STOP_MODE_MASK) -#define RSIM_POWER_RSIM_RUN_REQUEST_MASK (0x80000000U) -#define RSIM_POWER_RSIM_RUN_REQUEST_SHIFT (31U) -#define RSIM_POWER_RSIM_RUN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQUEST_SHIFT)) & RSIM_POWER_RSIM_RUN_REQUEST_MASK) -/*! @} */ - -/*! @name SW_CONFIG - Radio Software Configuration */ -/*! @{ */ -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK (0x1U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT (0U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK (0x2U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT (1U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK (0x10U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT (4U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK (0x20U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT (5U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK) -#define RSIM_SW_CONFIG_RADIO_POR_BIT_MASK (0x100U) -#define RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT (8U) -#define RSIM_SW_CONFIG_RADIO_POR_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_POR_BIT_MASK) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK (0x1000U) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT (12U) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK (0x10000U) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT (16U) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK) -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK (0x300000U) -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT (20U) -/*! WAKEUP_INTERRUPT_SOURCE - RSIM Wakeup Interrupt Source Selector - * 0b00..No Radio Power-On Sequence interrupt will be generated. - * 0b01..A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC. - * 0b10..A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source. - * 0b11..A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs - */ -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT)) & RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK (0x1000000U) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT (24U) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK (0x2000000U) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT (25U) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK (0x10000000U) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT (28U) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK (0x20000000U) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT (29U) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK (0x40000000U) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT (30U) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT)) & RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK (0x80000000U) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT (31U) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT)) & RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK) -/*! @} */ - -/*! @name DSM_TIMER - Deep Sleep Timer */ -/*! @{ */ -#define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU) -#define RSIM_DSM_TIMER_DSM_TIMER_SHIFT (0U) -#define RSIM_DSM_TIMER_DSM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK) -/*! @} */ - -/*! @name DSM_CONTROL - Deep Sleep Timer Control */ -/*! @{ */ -#define RSIM_DSM_CONTROL_DSM_WOR_READY_MASK (0x1U) -#define RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT (0U) -#define RSIM_DSM_CONTROL_DSM_WOR_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_READY_MASK) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK (0x2U) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT (1U) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK (0x4U) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT (2U) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK (0x8U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT (3U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK (0x10U) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT (4U) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK (0x20U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT (5U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK (0x40U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT (6U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK (0x80U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT (7U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_DSM_MAN_READY_MASK (0x100U) -#define RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT (8U) -#define RSIM_DSM_CONTROL_DSM_MAN_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_READY_MASK) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK (0x200U) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT (9U) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK (0x400U) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT (10U) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK (0x800U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT (11U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK (0x1000U) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT (12U) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK (0x2000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT (13U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK (0x4000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT (14U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK (0x8000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT (15U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK (0x10000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT (16U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK (0x20000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT (17U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK (0x40000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT (18U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x100000U) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (20U) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x200000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (21U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK (0x400000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT (22U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK (0x800000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT (23U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT (27U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK (0x80000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT (31U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK) -/*! @} */ - -/*! @name DSM_WAKEUP - Deep Sleep Wakeup Sequence */ -/*! @{ */ -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK (0x3FFU) -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT (0U) -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT)) & RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK (0x3F000U) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT (12U) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT)) & RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK) -#define RSIM_DSM_WAKEUP_FINE_DELAY_MASK (0x3F00000U) -#define RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT (20U) -#define RSIM_DSM_WAKEUP_FINE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_FINE_DELAY_MASK) -#define RSIM_DSM_WAKEUP_COARSE_DELAY_MASK (0xF0000000U) -#define RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT (28U) -#define RSIM_DSM_WAKEUP_COARSE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_COARSE_DELAY_MASK) -/*! @} */ - -/*! @name WOR_DURATION - WOR Deep Sleep Duration */ -/*! @{ */ -#define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK (0xFFFFFFU) -#define RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT (0U) -#define RSIM_WOR_DURATION_WOR_DSM_DURATION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK) -/*! @} */ - -/*! @name WOR_WAKE - WOR Deep Sleep Wake Time */ -/*! @{ */ -#define RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT (0U) -#define RSIM_WOR_WAKE_WOR_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT)) & RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK) -#define RSIM_WOR_WAKE_WOR_FSM_STATE_MASK (0x70000000U) -#define RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT (28U) -#define RSIM_WOR_WAKE_WOR_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT)) & RSIM_WOR_WAKE_WOR_FSM_STATE_MASK) -/*! @} */ - -/*! @name MAN_SLEEP - MAN Deep Sleep Time */ -/*! @{ */ -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK (0xFFFFFFU) -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT (0U) -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT)) & RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK) -/*! @} */ - -/*! @name MAN_WAKE - MAN Deep Sleep Wake Time */ -/*! @{ */ -#define RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT (0U) -#define RSIM_MAN_WAKE_MAN_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT)) & RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK) -#define RSIM_MAN_WAKE_MAN_FSM_STATE_MASK (0x70000000U) -#define RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT (28U) -#define RSIM_MAN_WAKE_MAN_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT)) & RSIM_MAN_WAKE_MAN_FSM_STATE_MASK) -/*! @} */ - -/*! @name RF_OSC_CTRL - Radio Oscillator Control */ -/*! @{ */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U) -/*! BB_XTAL_ALC_COUNT_SEL - rmap_bb_xtal_alc_count_sel_hv[1:0] - * 0b00..2048 (64 us @ 32 MHz) - * 0b01..4096 (128 us @ 32 MHz) - * 0b10..8192 (256 us @ 32 MHz) - * 0b11..16384 (512 us @ 32 MHz) - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK (0x4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT (2U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK (0x8U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT (3U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK (0x1F0U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK (0x400U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT (10U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK (0x1F000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT (12U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK (0x20000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT (17U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U) -/*! BB_XTAL_ON_OVRD_ON - rmap_bb_xtal_on_ovrd_on_hv - * 0b0..rfctrl_bb_xtal_on_hv is asserted - * 0b1..rfctrl_bb_xtal_on_ovrd_hv is asserted - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U) -/*! BB_XTAL_READY_COUNT_SEL - rmap_bb_xtal_ready_count_sel_hv[1:0] - * 0b00..1024 counts (32 us @ 32 MHz) - * 0b01..2048 (64 us @ 32 MHz) - * 0b10..4096 (128 us @ 32 MHz) - * 0b11..8192 (256 us @ 32 MHz) - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK (0x40000000U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT (30U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK (0x80000000U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT (31U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK) -/*! @} */ - -/*! @name ANA_TEST - Radio Analog Test Registers */ -/*! @{ */ -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK (0x10U) -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT (4U) -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT)) & RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK) -/*! @} */ - -/*! @name ANA_TRIM - Radio Analog Trim Registers */ -/*! @{ */ -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK (0x3U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT (0U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK (0x38U) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT (3U) -/*! BB_LDO_LS_TRIM - rmap_bb_ldo_ls_trim_hv[2:0] - * 0b000..1.20 V (Default) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK (0xC0U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT (6U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK (0x700U) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT (8U) -/*! BB_LDO_XO_TRIM - rmap_bb_ldo_xo_trim_hv[2:0] - * 0b000..1.20 V (Default) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK (0xF800U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT (11U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK (0xFF0000U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT (16U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_1V_TRIM_MASK (0xF000000U) -#define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT (24U) -/*! BG_1V_TRIM - rmap_bg_1v_trim_hv[3:0] - * 0b0000..954.14 mV - * 0b0001..959.26 mV - * 0b0010..964.38 mV - * 0b0011..969.5 mV - * 0b0100..974.6 mV - * 0b0101..979.7 mV - * 0b0110..984.8 mV - * 0b0111..989.9 mV - * 0b1000..995 mV (Default) - * 0b1001..1 V - * 0b1010..1.005 V - * 0b1011..1.01 V - * 0b1100..1.015 V - * 0b1101..1.02 V - * 0b1110..1.025 V - * 0b1111..1.031 V - */ -#define RSIM_ANA_TRIM_BG_1V_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK (0xF0000000U) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT (28U) -/*! BG_IBIAS_5U_TRIM - rmap_bg_ibias_5u_trim_hv[3:0] - * 0b0000..3.55 uA - * 0b0001..3.73 uA - * 0b0010..4.04 uA - * 0b0011..4.22 uA - * 0b0100..4.39 uA - * 0b0101..4.57 uA - * 0b0110..4.89 uA - * 0b0111..5.06 (Default) - * 0b1000..5.23 uA - * 0b1001..5.41 uA - * 0b1010..5.72 uA - * 0b1011..5.9 uA - * 0b1100..6.07 uA - * 0b1101..6.25 uA - * 0b1110..6.56 uA - * 0b1111..6.74 uA - */ -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RSIM_Register_Masks */ - - -/* RSIM - Peripheral instance base addresses */ -/** Peripheral RSIM base address */ -#define RSIM_BASE (0x4102F000u) -/** Peripheral RSIM base pointer */ -#define RSIM ((RSIM_Type *)RSIM_BASE) -/** Array initializer of RSIM peripheral base addresses */ -#define RSIM_BASE_ADDRS { RSIM_BASE } -/** Array initializer of RSIM peripheral base pointers */ -#define RSIM_BASE_PTRS { RSIM } - -/*! - * @} - */ /* end of group RSIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ - __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ - __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ - __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ - __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ - __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ - __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ - __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */ - __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */ - __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */ - __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */ - uint8_t RESERVED_0[4]; - __IO uint32_t TDR; /**< RTC Tamper Detect Register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TIR; /**< RTC Tamper Interrupt Register, offset: 0x3C */ - __IO uint32_t PCR[4]; /**< RTC Pin Configuration Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[1968]; - __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ - __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name TSR - RTC Time Seconds Register */ -/*! @{ */ -#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) -#define RTC_TSR_TSR_SHIFT (0U) -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) -/*! @} */ - -/*! @name TPR - RTC Time Prescaler Register */ -/*! @{ */ -#define RTC_TPR_TPR_MASK (0xFFFFU) -#define RTC_TPR_TPR_SHIFT (0U) -#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) -/*! @} */ - -/*! @name TAR - RTC Time Alarm Register */ -/*! @{ */ -#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) -#define RTC_TAR_TAR_SHIFT (0U) -#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) -/*! @} */ - -/*! @name TCR - RTC Time Compensation Register */ -/*! @{ */ -#define RTC_TCR_TCR_MASK (0xFFU) -#define RTC_TCR_TCR_SHIFT (0U) -/*! TCR - Time Compensation Register - * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. - * 0b10000001..Time Prescaler Register overflows every 32895 clock cycles. - * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. - * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. - * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. - * 0b01111110..Time Prescaler Register overflows every 32642 clock cycles. - * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. - */ -#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) -#define RTC_TCR_CIR_MASK (0xFF00U) -#define RTC_TCR_CIR_SHIFT (8U) -#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) -#define RTC_TCR_TCV_MASK (0xFF0000U) -#define RTC_TCR_TCV_SHIFT (16U) -#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) -#define RTC_TCR_CIC_MASK (0xFF000000U) -#define RTC_TCR_CIC_SHIFT (24U) -#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) -/*! @} */ - -/*! @name CR - RTC Control Register */ -/*! @{ */ -#define RTC_CR_SWR_MASK (0x1U) -#define RTC_CR_SWR_SHIFT (0U) -/*! SWR - Software Reset - * 0b0..No effect. - * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. - */ -#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) -#define RTC_CR_WPE_MASK (0x2U) -#define RTC_CR_WPE_SHIFT (1U) -/*! WPE - Wakeup Pin Enable - * 0b0..RTC_WAKEUP pin is disabled. - * 0b1..RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on. - */ -#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) -#define RTC_CR_SUP_MASK (0x4U) -#define RTC_CR_SUP_SHIFT (2U) -/*! SUP - Supervisor Access - * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. - * 0b1..Non-supervisor mode write accesses are supported. - */ -#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) -#define RTC_CR_UM_MASK (0x8U) -#define RTC_CR_UM_SHIFT (3U) -/*! UM - Update Mode - * 0b0..Registers cannot be written when locked. - * 0b1..Registers can be written when locked under limited conditions. - */ -#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) -#define RTC_CR_WPS_MASK (0x10U) -#define RTC_CR_WPS_SHIFT (4U) -/*! WPS - Wakeup Pin Select - * 0b0..RTC_WAKEUP pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. - * 0b1..RTC_WAKEUP pin outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. - */ -#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) -#define RTC_CR_CPS_MASK (0x20U) -#define RTC_CR_CPS_SHIFT (5U) -/*! CPS - Clock Pin Select - * 0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. - * 0b1..The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. - */ -#define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK) -#define RTC_CR_LPOS_MASK (0x80U) -#define RTC_CR_LPOS_SHIFT (7U) -/*! LPOS - LPO Select - * 0b0..RTC prescaler increments using 32.768 kHz clock. - * 0b1..RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. - */ -#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) -#define RTC_CR_OSCE_MASK (0x100U) -#define RTC_CR_OSCE_SHIFT (8U) -/*! OSCE - Oscillator Enable - * 0b0..32.768 kHz oscillator is disabled. - * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. - */ -#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) -#define RTC_CR_CLKO_MASK (0x200U) -#define RTC_CR_CLKO_SHIFT (9U) -/*! CLKO - Clock Output - * 0b0..The 32 kHz clock is output to other peripherals. - * 0b1..The 32 kHz clock is not output to other peripherals. - */ -#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) -#define RTC_CR_SC16P_MASK (0x400U) -#define RTC_CR_SC16P_SHIFT (10U) -/*! SC16P - Oscillator 16pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) -#define RTC_CR_SC8P_MASK (0x800U) -#define RTC_CR_SC8P_SHIFT (11U) -/*! SC8P - Oscillator 8pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) -#define RTC_CR_SC4P_MASK (0x1000U) -#define RTC_CR_SC4P_SHIFT (12U) -/*! SC4P - Oscillator 4pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) -#define RTC_CR_SC2P_MASK (0x2000U) -#define RTC_CR_SC2P_SHIFT (13U) -/*! SC2P - Oscillator 2pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) -#define RTC_CR_OSCM_MASK (0x8000U) -#define RTC_CR_OSCM_SHIFT (15U) -/*! OSCM - Oscillator Mode Select - * 0b0..Configures the 32.768kHz crystal oscillator for robust operation supporting a wide range of crystals. - * 0b1..Configures the 32.768kHz crystal oscillator for low power operation supporting a more limited range of crystals. - */ -#define RTC_CR_OSCM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCM_SHIFT)) & RTC_CR_OSCM_MASK) -#define RTC_CR_PORS_MASK (0x30000U) -#define RTC_CR_PORS_SHIFT (16U) -/*! PORS - POR Select - * 0b00..POR brownout enabled for 120us every 128ms. - * 0b01..POR brownout enabled for 120us every 64ms. - * 0b10..POR brownout enabled for 120us every 32ms. - * 0b11..POR brownout always enabled. - */ -#define RTC_CR_PORS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_PORS_SHIFT)) & RTC_CR_PORS_MASK) -#define RTC_CR_CPE_MASK (0x3000000U) -#define RTC_CR_CPE_SHIFT (24U) -/*! CPE - Clock Pin Enable - * 0b00..The RTC_CLKOUT function is disabled. - * 0b01..Enable RTC_CLKOUT pin on pin 1. - * 0b10..Enable RTC_CLKOUT pin on pin 2. - * 0b11..Enable RTC_CLKOUT pin on pin 3. - */ -#define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK) -/*! @} */ - -/*! @name SR - RTC Status Register */ -/*! @{ */ -#define RTC_SR_TIF_MASK (0x1U) -#define RTC_SR_TIF_SHIFT (0U) -/*! TIF - Time Invalid Flag - * 0b0..Time is valid. - * 0b1..Time is invalid and time counter is read as zero. - */ -#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) -#define RTC_SR_TOF_MASK (0x2U) -#define RTC_SR_TOF_SHIFT (1U) -/*! TOF - Time Overflow Flag - * 0b0..Time overflow has not occurred. - * 0b1..Time overflow has occurred and time counter is read as zero. - */ -#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) -#define RTC_SR_TAF_MASK (0x4U) -#define RTC_SR_TAF_SHIFT (2U) -/*! TAF - Time Alarm Flag - * 0b0..Time alarm has not occurred. - * 0b1..Time alarm has occurred. - */ -#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) -#define RTC_SR_MOF_MASK (0x8U) -#define RTC_SR_MOF_SHIFT (3U) -/*! MOF - Monotonic Overflow Flag - * 0b0..Monotonic counter overflow has not occurred. - * 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero. - */ -#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK) -#define RTC_SR_TCE_MASK (0x10U) -#define RTC_SR_TCE_SHIFT (4U) -/*! TCE - Time Counter Enable - * 0b0..Time counter is disabled. - * 0b1..Time counter is enabled. - */ -#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) -#define RTC_SR_TIDF_MASK (0x80U) -#define RTC_SR_TIDF_SHIFT (7U) -/*! TIDF - Tamper Interrupt Detect Flag - * 0b0..Tamper interrupt has not asserted. - * 0b1..Tamper interrupt has asserted. - */ -#define RTC_SR_TIDF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIDF_SHIFT)) & RTC_SR_TIDF_MASK) -/*! @} */ - -/*! @name LR - RTC Lock Register */ -/*! @{ */ -#define RTC_LR_TCL_MASK (0x8U) -#define RTC_LR_TCL_SHIFT (3U) -/*! TCL - Time Compensation Lock - * 0b0..Time Compensation Register is locked and writes are ignored. - * 0b1..Time Compensation Register is not locked and writes complete as normal. - */ -#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) -#define RTC_LR_CRL_MASK (0x10U) -#define RTC_LR_CRL_SHIFT (4U) -/*! CRL - Control Register Lock - * 0b0..Control Register is locked and writes are ignored. - * 0b1..Control Register is not locked and writes complete as normal. - */ -#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) -#define RTC_LR_SRL_MASK (0x20U) -#define RTC_LR_SRL_SHIFT (5U) -/*! SRL - Status Register Lock - * 0b0..Status Register is locked and writes are ignored. - * 0b1..Status Register is not locked and writes complete as normal. - */ -#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) -#define RTC_LR_LRL_MASK (0x40U) -#define RTC_LR_LRL_SHIFT (6U) -/*! LRL - Lock Register Lock - * 0b0..Lock Register is locked and writes are ignored. - * 0b1..Lock Register is not locked and writes complete as normal. - */ -#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) -#define RTC_LR_TTSL_MASK (0x100U) -#define RTC_LR_TTSL_SHIFT (8U) -/*! TTSL - Tamper Time Seconds Lock - * 0b0..Tamper Time Seconds Register is locked and writes are ignored. - * 0b1..Tamper Time Seconds Register is not locked and writes complete as normal. - */ -#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK) -#define RTC_LR_MEL_MASK (0x200U) -#define RTC_LR_MEL_SHIFT (9U) -/*! MEL - Monotonic Enable Lock - * 0b0..Monotonic Enable Register is locked and writes are ignored. - * 0b1..Monotonic Enable Register is not locked and writes complete as normal. - */ -#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK) -#define RTC_LR_MCLL_MASK (0x400U) -#define RTC_LR_MCLL_SHIFT (10U) -/*! MCLL - Monotonic Counter Low Lock - * 0b0..Monotonic Counter Low Register is locked and writes are ignored. - * 0b1..Monotonic Counter Low Register is not locked and writes complete as normal. - */ -#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK) -#define RTC_LR_MCHL_MASK (0x800U) -#define RTC_LR_MCHL_SHIFT (11U) -/*! MCHL - Monotonic Counter High Lock - * 0b0..Monotonic Counter High Register is locked and writes are ignored. - * 0b1..Monotonic Counter High Register is not locked and writes complete as normal. - */ -#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK) -#define RTC_LR_TDL_MASK (0x2000U) -#define RTC_LR_TDL_SHIFT (13U) -/*! TDL - Tamper Detect Lock - * 0b0..Tamper Detect Register is locked and writes are ignored. - * 0b1..Tamper Detect Register is not locked and writes complete as normal. - */ -#define RTC_LR_TDL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TDL_SHIFT)) & RTC_LR_TDL_MASK) -#define RTC_LR_TIL_MASK (0x8000U) -#define RTC_LR_TIL_SHIFT (15U) -/*! TIL - Tamper Interrupt Lock - * 0b0..Tamper Interrupt Register is locked and writes are ignored. - * 0b1..Tamper Interrupt Register is not locked and writes complete as normal. - */ -#define RTC_LR_TIL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TIL_SHIFT)) & RTC_LR_TIL_MASK) -#define RTC_LR_PCL_MASK (0xF0000U) -#define RTC_LR_PCL_SHIFT (16U) -#define RTC_LR_PCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK) -/*! @} */ - -/*! @name IER - RTC Interrupt Enable Register */ -/*! @{ */ -#define RTC_IER_TIIE_MASK (0x1U) -#define RTC_IER_TIIE_SHIFT (0U) -/*! TIIE - Time Invalid Interrupt Enable - * 0b0..Time invalid flag does not generate an interrupt. - * 0b1..Time invalid flag does generate an interrupt. - */ -#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) -#define RTC_IER_TOIE_MASK (0x2U) -#define RTC_IER_TOIE_SHIFT (1U) -/*! TOIE - Time Overflow Interrupt Enable - * 0b0..Time overflow flag does not generate an interrupt. - * 0b1..Time overflow flag does generate an interrupt. - */ -#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) -#define RTC_IER_TAIE_MASK (0x4U) -#define RTC_IER_TAIE_SHIFT (2U) -/*! TAIE - Time Alarm Interrupt Enable - * 0b0..Time alarm flag does not generate an interrupt. - * 0b1..Time alarm flag does generate an interrupt. - */ -#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) -#define RTC_IER_MOIE_MASK (0x8U) -#define RTC_IER_MOIE_SHIFT (3U) -/*! MOIE - Monotonic Overflow Interrupt Enable - * 0b0..Monotonic overflow flag does not generate an interrupt. - * 0b1..Monotonic overflow flag does generate an interrupt. - */ -#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK) -#define RTC_IER_TSIE_MASK (0x10U) -#define RTC_IER_TSIE_SHIFT (4U) -/*! TSIE - Time Seconds Interrupt Enable - * 0b0..Seconds interrupt is disabled. - * 0b1..Seconds interrupt is enabled. - */ -#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) -#define RTC_IER_WPON_MASK (0x80U) -#define RTC_IER_WPON_SHIFT (7U) -/*! WPON - Wakeup Pin On - * 0b0..No effect. - * 0b1..If the RTC_WAKEUP pin is enabled, then the pin will assert. - */ -#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) -#define RTC_IER_TSIC_MASK (0x70000U) -#define RTC_IER_TSIC_SHIFT (16U) -/*! TSIC - Timer Seconds Interrupt Configuration - * 0b000..1 Hz. - * 0b001..2 Hz. - * 0b010..4 Hz. - * 0b011..8 Hz. - * 0b100..16 Hz. - * 0b101..32 Hz. - * 0b110..64 Hz. - * 0b111..128 Hz. - */ -#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) -/*! @} */ - -/*! @name TTSR - RTC Tamper Time Seconds Register */ -/*! @{ */ -#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU) -#define RTC_TTSR_TTS_SHIFT (0U) -#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK) -/*! @} */ - -/*! @name MER - RTC Monotonic Enable Register */ -/*! @{ */ -#define RTC_MER_MCE_MASK (0x10U) -#define RTC_MER_MCE_SHIFT (4U) -/*! MCE - Monotonic Counter Enable - * 0b0..Writes to the monotonic counter load the counter with the value written. - * 0b1..Writes to the monotonic counter increment the counter. - */ -#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK) -/*! @} */ - -/*! @name MCLR - RTC Monotonic Counter Low Register */ -/*! @{ */ -#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU) -#define RTC_MCLR_MCL_SHIFT (0U) -#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK) -/*! @} */ - -/*! @name MCHR - RTC Monotonic Counter High Register */ -/*! @{ */ -#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU) -#define RTC_MCHR_MCH_SHIFT (0U) -#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK) -/*! @} */ - -/*! @name TDR - RTC Tamper Detect Register */ -/*! @{ */ -#define RTC_TDR_LCTF_MASK (0x10U) -#define RTC_TDR_LCTF_SHIFT (4U) -/*! LCTF - Loss of Clock Tamper Flag - * 0b0..Tamper not detected. - * 0b1..Loss of Clock tamper detected. - */ -#define RTC_TDR_LCTF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_LCTF_SHIFT)) & RTC_TDR_LCTF_MASK) -#define RTC_TDR_STF_MASK (0x20U) -#define RTC_TDR_STF_SHIFT (5U) -/*! STF - Security Tamper Flag - * 0b0..Tamper not detected. - * 0b1..Security module tamper detected. - */ -#define RTC_TDR_STF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_STF_SHIFT)) & RTC_TDR_STF_MASK) -#define RTC_TDR_FSF_MASK (0x40U) -#define RTC_TDR_FSF_SHIFT (6U) -/*! FSF - Flash Security Flag - * 0b0..Tamper not detected. - * 0b1..Flash security tamper detected. - */ -#define RTC_TDR_FSF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_FSF_SHIFT)) & RTC_TDR_FSF_MASK) -#define RTC_TDR_TMF_MASK (0x80U) -#define RTC_TDR_TMF_SHIFT (7U) -/*! TMF - Test Mode Flag - * 0b0..Tamper not detected. - * 0b1..Test mode tamper detected. - */ -#define RTC_TDR_TMF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TMF_SHIFT)) & RTC_TDR_TMF_MASK) -#define RTC_TDR_TPF_MASK (0xF0000U) -#define RTC_TDR_TPF_SHIFT (16U) -#define RTC_TDR_TPF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TPF_SHIFT)) & RTC_TDR_TPF_MASK) -/*! @} */ - -/*! @name TIR - RTC Tamper Interrupt Register */ -/*! @{ */ -#define RTC_TIR_LCIE_MASK (0x10U) -#define RTC_TIR_LCIE_SHIFT (4U) -/*! LCIE - Loss of Clock Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the loss of clock flag is set. - */ -#define RTC_TIR_LCIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_LCIE_SHIFT)) & RTC_TIR_LCIE_MASK) -#define RTC_TIR_SIE_MASK (0x20U) -#define RTC_TIR_SIE_SHIFT (5U) -/*! SIE - Security Module Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the security module flag is set. - */ -#define RTC_TIR_SIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_SIE_SHIFT)) & RTC_TIR_SIE_MASK) -#define RTC_TIR_FSIE_MASK (0x40U) -#define RTC_TIR_FSIE_SHIFT (6U) -/*! FSIE - Flash Security Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the flash security flag is set. - */ -#define RTC_TIR_FSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_FSIE_SHIFT)) & RTC_TIR_FSIE_MASK) -#define RTC_TIR_TMIE_MASK (0x80U) -#define RTC_TIR_TMIE_SHIFT (7U) -/*! TMIE - Test Mode Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the test mode flag is set. - */ -#define RTC_TIR_TMIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TMIE_SHIFT)) & RTC_TIR_TMIE_MASK) -#define RTC_TIR_TPIE_MASK (0xF0000U) -#define RTC_TIR_TPIE_SHIFT (16U) -#define RTC_TIR_TPIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TPIE_SHIFT)) & RTC_TIR_TPIE_MASK) -/*! @} */ - -/*! @name PCR - RTC Pin Configuration Register */ -/*! @{ */ -#define RTC_PCR_TPE_MASK (0x1000000U) -#define RTC_PCR_TPE_SHIFT (24U) -/*! TPE - Tamper Pull Enable - * 0b0..Pull resistor is disabled on tamper pin. - * 0b1..Pull resistor is enabled on tamper pin. - */ -#define RTC_PCR_TPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPE_SHIFT)) & RTC_PCR_TPE_MASK) -#define RTC_PCR_TPS_MASK (0x2000000U) -#define RTC_PCR_TPS_SHIFT (25U) -/*! TPS - Tamper Pull Select - * 0b0..Tamper pin pull resistor direction will assert the tamper pin. - * 0b1..Tamper pin pull resistor direction will negate the tamper pin. - */ -#define RTC_PCR_TPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPS_SHIFT)) & RTC_PCR_TPS_MASK) -#define RTC_PCR_TFE_MASK (0x4000000U) -#define RTC_PCR_TFE_SHIFT (26U) -/*! TFE - Tamper Filter Enable - * 0b0..Input filter is disabled on the tamper pin. - * 0b1..Input filter is enabled on the tamper pin. - */ -#define RTC_PCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TFE_SHIFT)) & RTC_PCR_TFE_MASK) -#define RTC_PCR_TPP_MASK (0x8000000U) -#define RTC_PCR_TPP_SHIFT (27U) -/*! TPP - Tamper Pin Polarity - * 0b0..Tamper pin is active high. - * 0b1..Tamper pin is active low. - */ -#define RTC_PCR_TPP(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPP_SHIFT)) & RTC_PCR_TPP_MASK) -#define RTC_PCR_TPID_MASK (0x80000000U) -#define RTC_PCR_TPID_SHIFT (31U) -/*! TPID - Tamper Pin Input Data - * 0b0..Tamper pin input data is logic zero. - * 0b1..Tamper pin input data is logic one. - */ -#define RTC_PCR_TPID(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPID_SHIFT)) & RTC_PCR_TPID_MASK) -/*! @} */ - -/* The count of RTC_PCR */ -#define RTC_PCR_COUNT (4U) - -/*! @name WAR - RTC Write Access Register */ -/*! @{ */ -#define RTC_WAR_TSRW_MASK (0x1U) -#define RTC_WAR_TSRW_SHIFT (0U) -/*! TSRW - Time Seconds Register Write - * 0b0..Writes to the Time Seconds Register are ignored. - * 0b1..Writes to the Time Seconds Register complete as normal. - */ -#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) -#define RTC_WAR_TPRW_MASK (0x2U) -#define RTC_WAR_TPRW_SHIFT (1U) -/*! TPRW - Time Prescaler Register Write - * 0b0..Writes to the Time Prescaler Register are ignored. - * 0b1..Writes to the Time Prescaler Register complete as normal. - */ -#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) -#define RTC_WAR_TARW_MASK (0x4U) -#define RTC_WAR_TARW_SHIFT (2U) -/*! TARW - Time Alarm Register Write - * 0b0..Writes to the Time Alarm Register are ignored. - * 0b1..Writes to the Time Alarm Register complete as normal. - */ -#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) -#define RTC_WAR_TCRW_MASK (0x8U) -#define RTC_WAR_TCRW_SHIFT (3U) -/*! TCRW - Time Compensation Register Write - * 0b0..Writes to the Time Compensation Register are ignored. - * 0b1..Writes to the Time Compensation Register complete as normal. - */ -#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) -#define RTC_WAR_CRW_MASK (0x10U) -#define RTC_WAR_CRW_SHIFT (4U) -/*! CRW - Control Register Write - * 0b0..Writes to the Control Register are ignored. - * 0b1..Writes to the Control Register complete as normal. - */ -#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) -#define RTC_WAR_SRW_MASK (0x20U) -#define RTC_WAR_SRW_SHIFT (5U) -/*! SRW - Status Register Write - * 0b0..Writes to the Status Register are ignored. - * 0b1..Writes to the Status Register complete as normal. - */ -#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) -#define RTC_WAR_LRW_MASK (0x40U) -#define RTC_WAR_LRW_SHIFT (6U) -/*! LRW - Lock Register Write - * 0b0..Writes to the Lock Register are ignored. - * 0b1..Writes to the Lock Register complete as normal. - */ -#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) -#define RTC_WAR_IERW_MASK (0x80U) -#define RTC_WAR_IERW_SHIFT (7U) -/*! IERW - Interrupt Enable Register Write - * 0b0..Writes to the Interupt Enable Register are ignored. - * 0b1..Writes to the Interrupt Enable Register complete as normal. - */ -#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) -#define RTC_WAR_TTSW_MASK (0x100U) -#define RTC_WAR_TTSW_SHIFT (8U) -/*! TTSW - Tamper Time Seconds Write - * 0b0..Writes to the Tamper Time Seconds Register are ignored. - * 0b1..Writes to the Tamper Time Seconds Register complete as normal. - */ -#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK) -#define RTC_WAR_MERW_MASK (0x200U) -#define RTC_WAR_MERW_SHIFT (9U) -/*! MERW - Monotonic Enable Register Write - * 0b0..Writes to the Monotonic Enable Register are ignored. - * 0b1..Writes to the Monotonic Enable Register complete as normal. - */ -#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK) -#define RTC_WAR_MCLW_MASK (0x400U) -#define RTC_WAR_MCLW_SHIFT (10U) -/*! MCLW - Monotonic Counter Low Write - * 0b0..Writes to the Monotonic Counter Low Register are ignored. - * 0b1..Writes to the Monotonic Counter Low Register complete as normal. - */ -#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK) -#define RTC_WAR_MCHW_MASK (0x800U) -#define RTC_WAR_MCHW_SHIFT (11U) -/*! MCHW - Monotonic Counter High Write - * 0b0..Writes to the Monotonic Counter High Register are ignored. - * 0b1..Writes to the Monotonic Counter High Register complete as normal. - */ -#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK) -#define RTC_WAR_TDRW_MASK (0x2000U) -#define RTC_WAR_TDRW_SHIFT (13U) -/*! TDRW - Tamper Detect Register Write - * 0b0..Writes to the Tamper Detect Register are ignored. - * 0b1..Writes to the Tamper Detect Register complete as normal. - */ -#define RTC_WAR_TDRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TDRW_SHIFT)) & RTC_WAR_TDRW_MASK) -#define RTC_WAR_TIRW_MASK (0x8000U) -#define RTC_WAR_TIRW_SHIFT (15U) -/*! TIRW - Tamper Interrupt Register Write - * 0b0..Writes to the Tamper Interrupt Register are ignored. - * 0b1..Writes to the Tamper Interrupt Register complete as normal. - */ -#define RTC_WAR_TIRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TIRW_SHIFT)) & RTC_WAR_TIRW_MASK) -#define RTC_WAR_PCRW_MASK (0xF0000U) -#define RTC_WAR_PCRW_SHIFT (16U) -#define RTC_WAR_PCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_PCRW_SHIFT)) & RTC_WAR_PCRW_MASK) -/*! @} */ - -/*! @name RAR - RTC Read Access Register */ -/*! @{ */ -#define RTC_RAR_TSRR_MASK (0x1U) -#define RTC_RAR_TSRR_SHIFT (0U) -/*! TSRR - Time Seconds Register Read - * 0b0..Reads to the Time Seconds Register are ignored. - * 0b1..Reads to the Time Seconds Register complete as normal. - */ -#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) -#define RTC_RAR_TPRR_MASK (0x2U) -#define RTC_RAR_TPRR_SHIFT (1U) -/*! TPRR - Time Prescaler Register Read - * 0b0..Reads to the Time Pprescaler Register are ignored. - * 0b1..Reads to the Time Prescaler Register complete as normal. - */ -#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) -#define RTC_RAR_TARR_MASK (0x4U) -#define RTC_RAR_TARR_SHIFT (2U) -/*! TARR - Time Alarm Register Read - * 0b0..Reads to the Time Alarm Register are ignored. - * 0b1..Reads to the Time Alarm Register complete as normal. - */ -#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) -#define RTC_RAR_TCRR_MASK (0x8U) -#define RTC_RAR_TCRR_SHIFT (3U) -/*! TCRR - Time Compensation Register Read - * 0b0..Reads to the Time Compensation Register are ignored. - * 0b1..Reads to the Time Compensation Register complete as normal. - */ -#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) -#define RTC_RAR_CRR_MASK (0x10U) -#define RTC_RAR_CRR_SHIFT (4U) -/*! CRR - Control Register Read - * 0b0..Reads to the Control Register are ignored. - * 0b1..Reads to the Control Register complete as normal. - */ -#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) -#define RTC_RAR_SRR_MASK (0x20U) -#define RTC_RAR_SRR_SHIFT (5U) -/*! SRR - Status Register Read - * 0b0..Reads to the Status Register are ignored. - * 0b1..Reads to the Status Register complete as normal. - */ -#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) -#define RTC_RAR_LRR_MASK (0x40U) -#define RTC_RAR_LRR_SHIFT (6U) -/*! LRR - Lock Register Read - * 0b0..Reads to the Lock Register are ignored. - * 0b1..Reads to the Lock Register complete as normal. - */ -#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) -#define RTC_RAR_IERR_MASK (0x80U) -#define RTC_RAR_IERR_SHIFT (7U) -/*! IERR - Interrupt Enable Register Read - * 0b0..Reads to the Interrupt Enable Register are ignored. - * 0b1..Reads to the Interrupt Enable Register complete as normal. - */ -#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) -#define RTC_RAR_TTSR_MASK (0x100U) -#define RTC_RAR_TTSR_SHIFT (8U) -/*! TTSR - Tamper Time Seconds Read - * 0b0..Reads to the Tamper Time Seconds Register are ignored. - * 0b1..Reads to the Tamper Time Seconds Register complete as normal. - */ -#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK) -#define RTC_RAR_MERR_MASK (0x200U) -#define RTC_RAR_MERR_SHIFT (9U) -/*! MERR - Monotonic Enable Register Read - * 0b0..Reads to the Monotonic Enable Register are ignored. - * 0b1..Reads to the Monotonic Enable Register complete as normal. - */ -#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK) -#define RTC_RAR_MCLR_MASK (0x400U) -#define RTC_RAR_MCLR_SHIFT (10U) -/*! MCLR - Monotonic Counter Low Read - * 0b0..Reads to the Monotonic Counter Low Register are ignored. - * 0b1..Reads to the Monotonic Counter Low Register complete as normal. - */ -#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK) -#define RTC_RAR_MCHR_MASK (0x800U) -#define RTC_RAR_MCHR_SHIFT (11U) -/*! MCHR - Monotonic Counter High Read - * 0b0..Reads to the Monotonic Counter High Register are ignored. - * 0b1..Reads to the Monotonic Counter High Register complete as normal. - */ -#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK) -#define RTC_RAR_TDRR_MASK (0x2000U) -#define RTC_RAR_TDRR_SHIFT (13U) -/*! TDRR - Tamper Detect Register Read - * 0b0..Reads to the Tamper Detect Register are ignored. - * 0b1..Reads to the Tamper Detect Register complete as normal. - */ -#define RTC_RAR_TDRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TDRR_SHIFT)) & RTC_RAR_TDRR_MASK) -#define RTC_RAR_TIRR_MASK (0x8000U) -#define RTC_RAR_TIRR_SHIFT (15U) -/*! TIRR - Tamper Interrupt Register Read - * 0b0..Reads to the Tamper Interrupt Register are ignored. - * 0b1..Reads to the Tamper Interrupt Register complete as normal. - */ -#define RTC_RAR_TIRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TIRR_SHIFT)) & RTC_RAR_TIRR_MASK) -#define RTC_RAR_PCRR_MASK (0xF0000U) -#define RTC_RAR_PCRR_SHIFT (16U) -#define RTC_RAR_PCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_PCRR_SHIFT)) & RTC_RAR_PCRR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x40031000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer - * @{ - */ - -/** SCG - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ - __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ - __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ - __IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ - __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ - uint8_t RESERVED_1[220]; - __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ - __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ - uint8_t RESERVED_2[248]; - __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ - __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ - __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ - uint8_t RESERVED_3[244]; - __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ - __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ - __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ - __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */ - uint8_t RESERVED_4[8]; - __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */ - uint8_t RESERVED_5[228]; - __IO uint32_t ROSCCSR; /**< RTC OSC Control Status Register, offset: 0x400 */ - uint8_t RESERVED_6[252]; - __IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offset: 0x500 */ - __IO uint32_t LPFLLDIV; /**< Low Power FLL Divide Register, offset: 0x504 */ - __IO uint32_t LPFLLCFG; /**< Low Power FLL Configuration Register, offset: 0x508 */ - __IO uint32_t LPFLLTCFG; /**< Low Power FLL Trim Configuration Register, offset: 0x50C */ - uint8_t RESERVED_7[4]; - __IO uint32_t LPFLLSTAT; /**< Low Power FLL Status Register, offset: 0x514 */ -} SCG_Type; - -/* ---------------------------------------------------------------------------- - -- SCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCG_Register_Masks SCG Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) -#define SCG_VERID_VERSION_SHIFT (0U) -#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define SCG_PARAM_CLKPRES_MASK (0xFFU) -#define SCG_PARAM_CLKPRES_SHIFT (0U) -/*! CLKPRES - Clock Present - * 0b00000000-0b00000001..Reserved. - * 0bxxxxxx1x..System OSC (SOSC) is present. - * 0bxxxxx1xx..Slow IRC (SIRC) is present. - * 0bxxxx1xxx..Fast IRC (FIRC) is present. - * 0bxxx1xxxx..RTC OSC (ROSC) is present. - * 0bxx1xxxxx..Low Power FLL (LPFLL) is present. - */ -#define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) -#define SCG_PARAM_DIVPRES_MASK (0xF8000000U) -#define SCG_PARAM_DIVPRES_SHIFT (27U) -/*! DIVPRES - Divider Present - * 0bxxxx1..System DIVSLOW is present. - * 0bxxx1x..System DIVBUS is present. - * 0bxx1xx..System DIVEXT is present. - * 0b1xxxx..System DIVCORE is present. - */ -#define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) -/*! @} */ - -/*! @name CSR - Clock Status Register */ -/*! @{ */ -#define SCG_CSR_DIVSLOW_MASK (0xFU) -#define SCG_CSR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) -#define SCG_CSR_DIVBUS_MASK (0xF0U) -#define SCG_CSR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK) -#define SCG_CSR_DIVEXT_MASK (0xF00U) -#define SCG_CSR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVEXT_SHIFT)) & SCG_CSR_DIVEXT_MASK) -#define SCG_CSR_DIVCORE_MASK (0xF0000U) -#define SCG_CSR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) -#define SCG_CSR_SCS_MASK (0xF000000U) -#define SCG_CSR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) -/*! @} */ - -/*! @name RCCR - Run Clock Control Register */ -/*! @{ */ -#define SCG_RCCR_DIVSLOW_MASK (0xFU) -#define SCG_RCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) -#define SCG_RCCR_DIVBUS_MASK (0xF0U) -#define SCG_RCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK) -#define SCG_RCCR_DIVEXT_MASK (0xF00U) -#define SCG_RCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVEXT_SHIFT)) & SCG_RCCR_DIVEXT_MASK) -#define SCG_RCCR_DIVCORE_MASK (0xF0000U) -#define SCG_RCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) -#define SCG_RCCR_SCS_MASK (0x7000000U) -#define SCG_RCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b000..Reserved - * 0b001..System OSC (SOSC_CLK) - * 0b010..Slow IRC (SIRC_CLK) - * 0b011..Fast IRC (FIRC_CLK) - * 0b100..RTC OSC (ROSC_CLK) - * 0b101..Low Power FLL (LPFLL_CLK) - * 0b110..Reserved - * 0b111..Reserved - */ -#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) -/*! @} */ - -/*! @name VCCR - VLPR Clock Control Register */ -/*! @{ */ -#define SCG_VCCR_DIVSLOW_MASK (0xFU) -#define SCG_VCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) -#define SCG_VCCR_DIVBUS_MASK (0xF0U) -#define SCG_VCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK) -#define SCG_VCCR_DIVEXT_MASK (0xF00U) -#define SCG_VCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVEXT_SHIFT)) & SCG_VCCR_DIVEXT_MASK) -#define SCG_VCCR_DIVCORE_MASK (0xF0000U) -#define SCG_VCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) -#define SCG_VCCR_SCS_MASK (0xF000000U) -#define SCG_VCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Reserved - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Reserved - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) -/*! @} */ - -/*! @name HCCR - HSRUN Clock Control Register */ -/*! @{ */ -#define SCG_HCCR_DIVSLOW_MASK (0xFU) -#define SCG_HCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK) -#define SCG_HCCR_DIVBUS_MASK (0xF0U) -#define SCG_HCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK) -#define SCG_HCCR_DIVEXT_MASK (0xF00U) -#define SCG_HCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVEXT_SHIFT)) & SCG_HCCR_DIVEXT_MASK) -#define SCG_HCCR_DIVCORE_MASK (0xF0000U) -#define SCG_HCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK) -#define SCG_HCCR_SCS_MASK (0xF000000U) -#define SCG_HCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK) -/*! @} */ - -/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ -/*! @{ */ -#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) -#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) -/*! CLKOUTSEL - SCG Clkout Select - * 0b0000..SCG EXTERNAL Clock - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - * 0b1111..Reserved - */ -#define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) -/*! @} */ - -/*! @name SOSCCSR - System OSC Control Status Register */ -/*! @{ */ -#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) -#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) -/*! SOSCEN - System OSC Enable - * 0b0..System OSC is disabled - * 0b1..System OSC is enabled - */ -#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) -#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) -#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) -/*! SOSCSTEN - System OSC Stop Enable - * 0b0..System OSC is disabled in Stop modes - * 0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1. - */ -#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) -#define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U) -#define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U) -/*! SOSCLPEN - System OSC Low Power Enable - * 0b0..System OSC is disabled in VLP modes - * 0b1..System OSC is enabled in VLP modes - */ -#define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK) -#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) -#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) -/*! SOSCCM - System OSC Clock Monitor - * 0b0..System OSC Clock Monitor is disabled - * 0b1..System OSC Clock Monitor is enabled - */ -#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) -#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) -#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) -/*! SOSCCMRE - System OSC Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) -#define SCG_SOSCCSR_LK_MASK (0x800000U) -#define SCG_SOSCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..This Control Status Register can be written. - * 0b1..This Control Status Register cannot be written. - */ -#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) -#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) -#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) -/*! SOSCVLD - System OSC Valid - * 0b0..System OSC is not enabled or clock is not valid - * 0b1..System OSC is enabled and output clock is valid - */ -#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) -#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) -#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) -/*! SOSCSEL - System OSC Selected - * 0b0..System OSC is not the system clock source - * 0b1..System OSC is the system clock source - */ -#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) -#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) -#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) -/*! SOSCERR - System OSC Clock Error - * 0b0..System OSC Clock Monitor is disabled or has not detected an error - * 0b1..System OSC Clock Monitor is enabled and detected an error - */ -#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) -/*! @} */ - -/*! @name SOSCDIV - System OSC Divide Register */ -/*! @{ */ -#define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) -#define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U) -/*! SOSCDIV1 - System OSC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK) -#define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) -#define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) -/*! SOSCDIV2 - System OSC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) -#define SCG_SOSCDIV_SOSCDIV3_MASK (0x70000U) -#define SCG_SOSCDIV_SOSCDIV3_SHIFT (16U) -/*! SOSCDIV3 - System OSC Clock Divide 3 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK) -/*! @} */ - -/*! @name SIRCCSR - Slow IRC Control Status Register */ -/*! @{ */ -#define SCG_SIRCCSR_SIRCEN_MASK (0x1U) -#define SCG_SIRCCSR_SIRCEN_SHIFT (0U) -/*! SIRCEN - Slow IRC Enable - * 0b0..Slow IRC is disabled - * 0b1..Slow IRC is enabled - */ -#define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) -#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) -#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) -/*! SIRCSTEN - Slow IRC Stop Enable - * 0b0..Slow IRC is disabled in Stop modes - * 0b1..Slow IRC is enabled in Stop modes - */ -#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) -#define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) -#define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) -/*! SIRCLPEN - Slow IRC Low Power Enable - * 0b0..Slow IRC is disabled in VLP modes - * 0b1..Slow IRC is enabled in VLP modes - */ -#define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) -#define SCG_SIRCCSR_LK_MASK (0x800000U) -#define SCG_SIRCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) -#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) -#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) -/*! SIRCVLD - Slow IRC Valid - * 0b0..Slow IRC is not enabled or clock is not valid - * 0b1..Slow IRC is enabled and output clock is valid - */ -#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) -#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) -#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) -/*! SIRCSEL - Slow IRC Selected - * 0b0..Slow IRC is not the system clock source - * 0b1..Slow IRC is the system clock source - */ -#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) -/*! @} */ - -/*! @name SIRCDIV - Slow IRC Divide Register */ -/*! @{ */ -#define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U) -#define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U) -/*! SIRCDIV1 - Slow IRC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK) -#define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) -#define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) -/*! SIRCDIV2 - Slow IRC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) -#define SCG_SIRCDIV_SIRCDIV3_MASK (0x70000U) -#define SCG_SIRCDIV_SIRCDIV3_SHIFT (16U) -/*! SIRCDIV3 - Slow IRC Clock Divider 3 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK) -/*! @} */ - -/*! @name SIRCCFG - Slow IRC Configuration Register */ -/*! @{ */ -#define SCG_SIRCCFG_RANGE_MASK (0x1U) -#define SCG_SIRCCFG_RANGE_SHIFT (0U) -/*! RANGE - Frequency Range - * 0b0..Slow IRC low range clock (2MHz) - * 0b1..Slow IRC high range clock (8 MHz) - */ -#define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) -/*! @} */ - -/*! @name FIRCCSR - Fast IRC Control Status Register */ -/*! @{ */ -#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) -#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) -/*! FIRCEN - Fast IRC Enable - * 0b0..Fast IRC is disabled - * 0b1..Fast IRC is enabled - */ -#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) -#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) -#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) -/*! FIRCSTEN - Fast IRC Stop Enable - * 0b0..Fast IRC is disabled in Stop modes. - * 0b1..Fast IRC is enabled in Stop modes - */ -#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) -#define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U) -#define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U) -/*! FIRCLPEN - Fast IRC Low Power Enable - * 0b0..Fast IRC is disabled in VLP modes - * 0b1..Fast IRC is enabled in VLP modes - */ -#define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK) -#define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) -#define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) -/*! FIRCREGOFF - Fast IRC Regulator Enable - * 0b0..Fast IRC Regulator is enabled. - * 0b1..Fast IRC Regulator is disabled. - */ -#define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) -#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) -#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) -/*! FIRCTREN - Fast IRC Trim Enable - * 0b0..Disable trimming Fast IRC to an external clock source - * 0b1..Enable trimming Fast IRC to an external clock source - */ -#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) -#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) -#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) -/*! FIRCTRUP - Fast IRC Trim Update - * 0b0..Disable Fast IRC trimming updates - * 0b1..Enable Fast IRC trimming updates - */ -#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) -#define SCG_FIRCCSR_LK_MASK (0x800000U) -#define SCG_FIRCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) -#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) -#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) -/*! FIRCVLD - Fast IRC Valid status - * 0b0..Fast IRC is not enabled or clock is not valid. - * 0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. - */ -#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) -#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) -#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) -/*! FIRCSEL - Fast IRC Selected status - * 0b0..Fast IRC is not the system clock source - * 0b1..Fast IRC is the system clock source - */ -#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) -#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) -#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) -/*! FIRCERR - Fast IRC Clock Error - * 0b0..Error not detected with the Fast IRC trimming. - * 0b1..Error detected with the Fast IRC trimming. - */ -#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) -/*! @} */ - -/*! @name FIRCDIV - Fast IRC Divide Register */ -/*! @{ */ -#define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U) -#define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U) -/*! FIRCDIV1 - Fast IRC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK) -#define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) -#define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) -/*! FIRCDIV2 - Fast IRC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) -#define SCG_FIRCDIV_FIRCDIV3_MASK (0x70000U) -#define SCG_FIRCDIV_FIRCDIV3_SHIFT (16U) -/*! FIRCDIV3 - Fast IRC Clock Divider 3 - * 0b000..Clock disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK) -/*! @} */ - -/*! @name FIRCCFG - Fast IRC Configuration Register */ -/*! @{ */ -#define SCG_FIRCCFG_RANGE_MASK (0x3U) -#define SCG_FIRCCFG_RANGE_SHIFT (0U) -/*! RANGE - Frequency Range - * 0b00..Fast IRC is trimmed to 48 MHz - * 0b01..Fast IRC is trimmed to 52 MHz - * 0b10..Fast IRC is trimmed to 56 MHz - * 0b11..Fast IRC is trimmed to 60 MHz - */ -#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) -/*! @} */ - -/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */ -/*! @{ */ -#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) -#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) -/*! TRIMSRC - Trim Source - * 0b00..Reserved - * 0b01..Reserved - * 0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency slower than 32kHz. - * 0b11..RTC OSC (32.768 kHz) - */ -#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) -#define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U) -#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U) -/*! TRIMDIV - Fast IRC Trim Predivide - * 0b000..Divide by 1 - * 0b001..Divide by 128 - * 0b010..Divide by 256 - * 0b011..Divide by 512 - * 0b100..Divide by 1024 - * 0b101..Divide by 2048 - * 0b110..Reserved. Writing this value will result in Divide by 1. - * 0b111..Reserved. Writing this value will result in a Divide by 1. - */ -#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) -/*! @} */ - -/*! @name FIRCSTAT - Fast IRC Status Register */ -/*! @{ */ -#define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU) -#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) -#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) -#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) -#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) -#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) -/*! @} */ - -/*! @name ROSCCSR - RTC OSC Control Status Register */ -/*! @{ */ -#define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) -#define SCG_ROSCCSR_ROSCCM_SHIFT (16U) -/*! ROSCCM - RTC OSC Clock Monitor - * 0b0..RTC OSC Clock Monitor is disabled - * 0b1..RTC OSC Clock Monitor is enabled - */ -#define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) -#define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) -#define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) -/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) -#define SCG_ROSCCSR_LK_MASK (0x800000U) -#define SCG_ROSCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) -#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) -#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) -/*! ROSCVLD - RTC OSC Valid - * 0b0..RTC OSC is not enabled or clock is not valid - * 0b1..RTC OSC is enabled and output clock is valid - */ -#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) -#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) -#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) -/*! ROSCSEL - RTC OSC Selected - * 0b0..RTC OSC is not the system clock source - * 0b1..RTC OSC is the system clock source - */ -#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) -#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) -#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) -/*! ROSCERR - RTC OSC Clock Error - * 0b0..RTC OSC Clock Monitor is disabled or has not detected an error - * 0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error - */ -#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) -/*! @} */ - -/*! @name LPFLLCSR - Low Power FLL Control Status Register */ -/*! @{ */ -#define SCG_LPFLLCSR_LPFLLEN_MASK (0x1U) -#define SCG_LPFLLCSR_LPFLLEN_SHIFT (0U) -/*! LPFLLEN - LPFLL Enable - * 0b0..LPFLL is disabled - * 0b1..LPFLL is enabled - */ -#define SCG_LPFLLCSR_LPFLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK) -#define SCG_LPFLLCSR_LPFLLSTEN_MASK (0x2U) -#define SCG_LPFLLCSR_LPFLLSTEN_SHIFT (1U) -/*! LPFLLSTEN - LPFLL Stop Enable - * 0b0..LPFLL is disabled in Stop modes. - * 0b1..LPFLL is enabled in Stop modes - */ -#define SCG_LPFLLCSR_LPFLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSTEN_SHIFT)) & SCG_LPFLLCSR_LPFLLSTEN_MASK) -#define SCG_LPFLLCSR_LPFLLTREN_MASK (0x100U) -#define SCG_LPFLLCSR_LPFLLTREN_SHIFT (8U) -/*! LPFLLTREN - LPFLL Trim Enable - * 0b0..Disable trimming LPFLL to an reference clock source - * 0b1..Enable trimming LPFLL to an reference clock source - */ -#define SCG_LPFLLCSR_LPFLLTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK) -#define SCG_LPFLLCSR_LPFLLTRUP_MASK (0x200U) -#define SCG_LPFLLCSR_LPFLLTRUP_SHIFT (9U) -/*! LPFLLTRUP - LPFLL Trim Update - * 0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. - * 0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication - */ -#define SCG_LPFLLCSR_LPFLLTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK) -#define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) -#define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT (10U) -/*! LPFLLTRMLOCK - LPFLL Trim LOCK - * 0b0..LPFLL not Locked - * 0b1..LPFLL trimmed and Locked - */ -#define SCG_LPFLLCSR_LPFLLTRMLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK) -#define SCG_LPFLLCSR_LPFLLCM_MASK (0x10000U) -#define SCG_LPFLLCSR_LPFLLCM_SHIFT (16U) -/*! LPFLLCM - LPFLL Clock Monitor - * 0b0..LPFLL Clock Monitor is disabled - * 0b1..LPFLL Clock Monitor is enabled - */ -#define SCG_LPFLLCSR_LPFLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK) -#define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) -#define SCG_LPFLLCSR_LPFLLCMRE_SHIFT (17U) -/*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_LPFLLCSR_LPFLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK) -#define SCG_LPFLLCSR_LK_MASK (0x800000U) -#define SCG_LPFLLCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_LPFLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK) -#define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) -#define SCG_LPFLLCSR_LPFLLVLD_SHIFT (24U) -/*! LPFLLVLD - LPFLL Valid - * 0b0..LPFLL is not enabled or clock is not valid. - * 0b1..LPFLL is enabled and output clock is valid. - */ -#define SCG_LPFLLCSR_LPFLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK) -#define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) -#define SCG_LPFLLCSR_LPFLLSEL_SHIFT (25U) -/*! LPFLLSEL - LPFLL Selected - * 0b0..LPFLL is not the system clock source - * 0b1..LPFLL is the system clock source - */ -#define SCG_LPFLLCSR_LPFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK) -#define SCG_LPFLLCSR_LPFLLERR_MASK (0x4000000U) -#define SCG_LPFLLCSR_LPFLLERR_SHIFT (26U) -/*! LPFLLERR - LPFLL Clock Error - * 0b0..Error not detected with the LPFLL trimming. - * 0b1..Error detected with the LPFLL trimming. - */ -#define SCG_LPFLLCSR_LPFLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK) -/*! @} */ - -/*! @name LPFLLDIV - Low Power FLL Divide Register */ -/*! @{ */ -#define SCG_LPFLLDIV_LPFLLDIV1_MASK (0x7U) -#define SCG_LPFLLDIV_LPFLLDIV1_SHIFT (0U) -/*! LPFLLDIV1 - LPFLL Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV1_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV1_MASK) -#define SCG_LPFLLDIV_LPFLLDIV2_MASK (0x700U) -#define SCG_LPFLLDIV_LPFLLDIV2_SHIFT (8U) -/*! LPFLLDIV2 - LPFLL Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK) -#define SCG_LPFLLDIV_LPFLLDIV3_MASK (0x70000U) -#define SCG_LPFLLDIV_LPFLLDIV3_SHIFT (16U) -/*! LPFLLDIV3 - LPFLL Clock Divide 3 - * 0b000..Clock disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK) -/*! @} */ - -/*! @name LPFLLCFG - Low Power FLL Configuration Register */ -/*! @{ */ -#define SCG_LPFLLCFG_FSEL_MASK (0x3U) -#define SCG_LPFLLCFG_FSEL_SHIFT (0U) -/*! FSEL - Frequency Select - * 0b00..LPFLL is trimmed to 48 MHz. - * 0b01..LPFLL is trimmed to 72 MHz. - * 0b10..Reserved - * 0b11..Reserved - */ -#define SCG_LPFLLCFG_FSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK) -/*! @} */ - -/*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */ -/*! @{ */ -#define SCG_LPFLLTCFG_TRIMSRC_MASK (0x3U) -#define SCG_LPFLLTCFG_TRIMSRC_SHIFT (0U) -/*! TRIMSRC - Trim Source - * 0b00..SIRC - * 0b01..FIRC - * 0b10..System OSC - * 0b11..RTC OSC - */ -#define SCG_LPFLLTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK) -#define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) -#define SCG_LPFLLTCFG_TRIMDIV_SHIFT (8U) -#define SCG_LPFLLTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK) -#define SCG_LPFLLTCFG_LOCKW2LSB_MASK (0x10000U) -#define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT (16U) -/*! LOCKW2LSB - Lock LPFLL with 2 LSBS - * 0b0..LPFLL locks within 1LSB (0.4%) - * 0b1..LPFLL locks within 2LSB (0.8%) - */ -#define SCG_LPFLLTCFG_LOCKW2LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK) -/*! @} */ - -/*! @name LPFLLSTAT - Low Power FLL Status Register */ -/*! @{ */ -#define SCG_LPFLLSTAT_AUTOTRIM_MASK (0xFFU) -#define SCG_LPFLLSTAT_AUTOTRIM_SHIFT (0U) -#define SCG_LPFLLSTAT_AUTOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SCG_Register_Masks */ - - -/* SCG - Peripheral instance base addresses */ -/** Peripheral SCG base address */ -#define SCG_BASE (0x4002C000u) -/** Peripheral SCG base pointer */ -#define SCG ((SCG_Type *)SCG_BASE) -/** Array initializer of SCG peripheral base addresses */ -#define SCG_BASE_ADDRS { SCG_BASE } -/** Array initializer of SCG peripheral base pointers */ -#define SCG_BASE_PTRS { SCG } -/** Interrupt vectors for the SCG peripheral type */ -#define SCG_IRQS { SCG_IRQn } - -/*! - * @} - */ /* end of group SCG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SEMA42 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer - * @{ - */ - -/** SEMA42 - Register Layout Typedef */ -typedef struct { - __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ - __IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */ - __IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */ - __IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */ - __IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */ - __IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */ - __IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */ - __IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */ - __IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */ - __IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */ - __IO uint8_t GATE9; /**< Gate Register, offset: 0xA */ - __IO uint8_t GATE8; /**< Gate Register, offset: 0xB */ - __IO uint8_t GATE15; /**< Gate Register, offset: 0xC */ - __IO uint8_t GATE14; /**< Gate Register, offset: 0xD */ - __IO uint8_t GATE13; /**< Gate Register, offset: 0xE */ - __IO uint8_t GATE12; /**< Gate Register, offset: 0xF */ - uint8_t RESERVED_0[50]; - union { /* offset: 0x42 */ - __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ - __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ - }; -} SEMA42_Type; - -/* ---------------------------------------------------------------------------- - -- SEMA42 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks - * @{ - */ - -/*! @name GATE3 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE3_GTFSM_MASK (0xFU) -#define SEMA42_GATE3_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) -/*! @} */ - -/*! @name GATE2 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE2_GTFSM_MASK (0xFU) -#define SEMA42_GATE2_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) -/*! @} */ - -/*! @name GATE1 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE1_GTFSM_MASK (0xFU) -#define SEMA42_GATE1_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) -/*! @} */ - -/*! @name GATE0 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE0_GTFSM_MASK (0xFU) -#define SEMA42_GATE0_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) -/*! @} */ - -/*! @name GATE7 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE7_GTFSM_MASK (0xFU) -#define SEMA42_GATE7_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) -/*! @} */ - -/*! @name GATE6 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE6_GTFSM_MASK (0xFU) -#define SEMA42_GATE6_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) -/*! @} */ - -/*! @name GATE5 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE5_GTFSM_MASK (0xFU) -#define SEMA42_GATE5_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) -/*! @} */ - -/*! @name GATE4 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE4_GTFSM_MASK (0xFU) -#define SEMA42_GATE4_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) -/*! @} */ - -/*! @name GATE11 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE11_GTFSM_MASK (0xFU) -#define SEMA42_GATE11_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) -/*! @} */ - -/*! @name GATE10 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE10_GTFSM_MASK (0xFU) -#define SEMA42_GATE10_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) -/*! @} */ - -/*! @name GATE9 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE9_GTFSM_MASK (0xFU) -#define SEMA42_GATE9_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) -/*! @} */ - -/*! @name GATE8 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE8_GTFSM_MASK (0xFU) -#define SEMA42_GATE8_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) -/*! @} */ - -/*! @name GATE15 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE15_GTFSM_MASK (0xFU) -#define SEMA42_GATE15_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) -/*! @} */ - -/*! @name GATE14 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE14_GTFSM_MASK (0xFU) -#define SEMA42_GATE14_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) -/*! @} */ - -/*! @name GATE13 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE13_GTFSM_MASK (0xFU) -#define SEMA42_GATE13_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) -/*! @} */ - -/*! @name GATE12 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE12_GTFSM_MASK (0xFU) -#define SEMA42_GATE12_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) -/*! @} */ - -/*! @name RSTGT_R - Reset Gate Read */ -/*! @{ */ -#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) -#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) -#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) -#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) -#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) -#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) -#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) -#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) -/*! RSTGSM - RSTGSM - * 0b00..Idle, waiting for the first data pattern write. - * 0b01..Waiting for the second data pattern write. - * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state. - * 0b11..This state encoding is never used and therefore reserved. - */ -#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) -#define SEMA42_RSTGT_R_ROZ_MASK (0xC000U) -#define SEMA42_RSTGT_R_ROZ_SHIFT (14U) -#define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK) -/*! @} */ - -/*! @name RSTGT_W - Reset Gate Write */ -/*! @{ */ -#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) -#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) -#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) -#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) -#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) -#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SEMA42_Register_Masks */ - - -/* SEMA42 - Peripheral instance base addresses */ -/** Peripheral SEMA420 base address */ -#define SEMA420_BASE (0x4001B000u) -/** Peripheral SEMA420 base pointer */ -#define SEMA420 ((SEMA42_Type *)SEMA420_BASE) -/** Peripheral SEMA421 base address */ -#define SEMA421_BASE (0x4101B000u) -/** Peripheral SEMA421 base pointer */ -#define SEMA421 ((SEMA42_Type *)SEMA421_BASE) -/** Array initializer of SEMA42 peripheral base addresses */ -#define SEMA42_BASE_ADDRS { SEMA420_BASE, SEMA421_BASE } -/** Array initializer of SEMA42 peripheral base pointers */ -#define SEMA42_BASE_PTRS { SEMA420, SEMA421 } - -/*! - * @} - */ /* end of group SEMA42_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer - * @{ - */ - -/** SIM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __IO uint32_t CHIPCTRL; /**< Chip Control Register, offset: 0x4 */ - uint8_t RESERVED_1[28]; - __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ - uint8_t RESERVED_2[36]; - __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ - __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x50 */ - uint8_t RESERVED_3[4]; - __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x58 */ - __I uint32_t UIDM; /**< Unique Identification Register Mid Middle, offset: 0x5C */ - __I uint32_t UIDL; /**< Unique Identification Register Mid Low, offset: 0x60 */ - __I uint32_t RFADDRL; /**< RF Mac Address Low, offset: 0x64 */ - __I uint32_t RFADDRH; /**< RF MAC Address High, offset: 0x68 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MISC2; /**< MISC2 Register, offset: 0x70 */ -} SIM_Type; - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/*! @name CHIPCTRL - Chip Control Register */ -/*! @{ */ -#define SIM_CHIPCTRL_FBSL_MASK (0x300U) -#define SIM_CHIPCTRL_FBSL_SHIFT (8U) -/*! FBSL - FLEXBUS security level - * 0b00..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed - * 0b01..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed - * 0b10..off-chip instruction access are disallowed, data access are allowed - * 0b11..off-chip instruction access and data access are allowed - */ -#define SIM_CHIPCTRL_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTRL_FBSL_SHIFT)) & SIM_CHIPCTRL_FBSL_MASK) -/*! @} */ - -/*! @name SDID - System Device Identification Register */ -/*! @{ */ -#define SIM_SDID_PINID_MASK (0xFU) -#define SIM_SDID_PINID_SHIFT (0U) -/*! PINID - PINID - * 0b1000..176-pin - * 0b1101..191-pin - */ -#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) -#define SIM_SDID_DIEID_MASK (0xF80U) -#define SIM_SDID_DIEID_SHIFT (7U) -#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) -#define SIM_SDID_REVID_MASK (0xF000U) -#define SIM_SDID_REVID_SHIFT (12U) -#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) -#define SIM_SDID_SERIESID_MASK (0xF00000U) -#define SIM_SDID_SERIESID_SHIFT (20U) -#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) -#define SIM_SDID_SUBFAMID_MASK (0xF000000U) -#define SIM_SDID_SUBFAMID_SHIFT (24U) -/*! SUBFAMID - SUBFAMID - * 0b0010..02 - * 0b0011..03 - * 0b0100..04 - */ -#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) -#define SIM_SDID_FAMID_MASK (0xF0000000U) -#define SIM_SDID_FAMID_SHIFT (28U) -/*! FAMID - FAMID - * 0b0000..RV32M1 - */ -#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) -/*! @} */ - -/*! @name FCFG1 - Flash Configuration Register 1 */ -/*! @{ */ -#define SIM_FCFG1_FLASHDIS_MASK (0x1U) -#define SIM_FCFG1_FLASHDIS_SHIFT (0U) -/*! FLASHDIS - Flash disable - * 0b0..Flash is enabled - * 0b1..Flash is disabled - */ -#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) -#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) -#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) -/*! FLASHDOZE - Flash Doze - * 0b0..Flash remains enabled during Doze mode - * 0b1..Flash is disabled for the duration of Doze mode - */ -#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) -#define SIM_FCFG1_FLSAUTODISEN_MASK (0x4U) -#define SIM_FCFG1_FLSAUTODISEN_SHIFT (2U) -/*! FLSAUTODISEN - Flash auto disable enabled. - * 0b0..Disable flash auto disable function - * 0b1..Enable flash auto disable function - */ -#define SIM_FCFG1_FLSAUTODISEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK) -#define SIM_FCFG1_FLSAUTODISWD_MASK (0x3FF8U) -#define SIM_FCFG1_FLSAUTODISWD_SHIFT (3U) -#define SIM_FCFG1_FLSAUTODISWD(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK) -#define SIM_FCFG1_CORE1_SRAMSIZE_MASK (0xF0000U) -#define SIM_FCFG1_CORE1_SRAMSIZE_SHIFT (16U) -/*! CORE1_SRAMSIZE - * 0b1001..CM0+ has 128 KB SRAM - */ -#define SIM_FCFG1_CORE1_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE1_SRAMSIZE_MASK) -#define SIM_FCFG1_CORE0_SRAMSIZE_MASK (0xF00000U) -#define SIM_FCFG1_CORE0_SRAMSIZE_SHIFT (20U) -/*! CORE0_SRAMSIZE - * 0b1010..CM4 has 256 KB SRAM - */ -#define SIM_FCFG1_CORE0_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE0_SRAMSIZE_MASK) -#define SIM_FCFG1_CORE1_PFSIZE_MASK (0xF000000U) -#define SIM_FCFG1_CORE1_PFSIZE_SHIFT (24U) -/*! CORE1_PFSIZE - * 0b1010..CM0+ has 256 KB flash size. - */ -#define SIM_FCFG1_CORE1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_PFSIZE_SHIFT)) & SIM_FCFG1_CORE1_PFSIZE_MASK) -#define SIM_FCFG1_CORE0_PFSIZE_MASK (0xF0000000U) -#define SIM_FCFG1_CORE0_PFSIZE_SHIFT (28U) -/*! CORE0_PFSIZE - * 0b1100..CM4 has 1 MB flash size. - */ -#define SIM_FCFG1_CORE0_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_PFSIZE_SHIFT)) & SIM_FCFG1_CORE0_PFSIZE_MASK) -/*! @} */ - -/*! @name FCFG2 - Flash Configuration Register 2 */ -/*! @{ */ -#define SIM_FCFG2_MAXADDR2_MASK (0x3F0000U) -#define SIM_FCFG2_MAXADDR2_SHIFT (16U) -#define SIM_FCFG2_MAXADDR2(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK) -#define SIM_FCFG2_MAXADDR01_MASK (0x7F000000U) -#define SIM_FCFG2_MAXADDR01_SHIFT (24U) -#define SIM_FCFG2_MAXADDR01(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR01_SHIFT)) & SIM_FCFG2_MAXADDR01_MASK) -#define SIM_FCFG2_SWAP_MASK (0x80000000U) -#define SIM_FCFG2_SWAP_SHIFT (31U) -/*! SWAP - SWAP - * 0b0..Logical P-flash Block 0 is located at relative address 0x0000 - * 0b1..Logical P-flash Block 1 is located at relative address 0x0000 - */ -#define SIM_FCFG2_SWAP(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAP_SHIFT)) & SIM_FCFG2_SWAP_MASK) -/*! @} */ - -/*! @name UIDH - Unique Identification Register High */ -/*! @{ */ -#define SIM_UIDH_UID_MASK (0xFFFFU) -#define SIM_UIDH_UID_SHIFT (0U) -#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) -/*! @} */ - -/*! @name UIDM - Unique Identification Register Mid Middle */ -/*! @{ */ -#define SIM_UIDM_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDM_UID_SHIFT (0U) -#define SIM_UIDM_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDM_UID_SHIFT)) & SIM_UIDM_UID_MASK) -/*! @} */ - -/*! @name UIDL - Unique Identification Register Mid Low */ -/*! @{ */ -#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDL_UID_SHIFT (0U) -#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) -/*! @} */ - -/*! @name RFADDRL - RF Mac Address Low */ -/*! @{ */ -#define SIM_RFADDRL_MACADDR0_MASK (0xFFU) -#define SIM_RFADDRL_MACADDR0_SHIFT (0U) -#define SIM_RFADDRL_MACADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR0_SHIFT)) & SIM_RFADDRL_MACADDR0_MASK) -#define SIM_RFADDRL_MACADDR1_MASK (0xFF00U) -#define SIM_RFADDRL_MACADDR1_SHIFT (8U) -#define SIM_RFADDRL_MACADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR1_SHIFT)) & SIM_RFADDRL_MACADDR1_MASK) -#define SIM_RFADDRL_MACADDR2_MASK (0xFF0000U) -#define SIM_RFADDRL_MACADDR2_SHIFT (16U) -#define SIM_RFADDRL_MACADDR2(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR2_SHIFT)) & SIM_RFADDRL_MACADDR2_MASK) -#define SIM_RFADDRL_MACADDR3_MASK (0xFF000000U) -#define SIM_RFADDRL_MACADDR3_SHIFT (24U) -#define SIM_RFADDRL_MACADDR3(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR3_SHIFT)) & SIM_RFADDRL_MACADDR3_MASK) -/*! @} */ - -/*! @name RFADDRH - RF MAC Address High */ -/*! @{ */ -#define SIM_RFADDRH_MACADDR4_MASK (0xFFU) -#define SIM_RFADDRH_MACADDR4_SHIFT (0U) -#define SIM_RFADDRH_MACADDR4(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRH_MACADDR4_SHIFT)) & SIM_RFADDRH_MACADDR4_MASK) -/*! @} */ - -/*! @name MISC2 - MISC2 Register */ -/*! @{ */ -#define SIM_MISC2_SYSTICK_CLK_EN_MASK (0x1U) -#define SIM_MISC2_SYSTICK_CLK_EN_SHIFT (0U) -/*! systick_clk_en - Systick clock enable - * 0b0..Systick clock is disabled - * 0b1..Systick clock is enabled - */ -#define SIM_MISC2_SYSTICK_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC2_SYSTICK_CLK_EN_SHIFT)) & SIM_MISC2_SYSTICK_CLK_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SIM_Register_Masks */ - - -/* SIM - Peripheral instance base addresses */ -/** Peripheral SIM base address */ -#define SIM_BASE (0x40026000u) -/** Peripheral SIM base pointer */ -#define SIM ((SIM_Type *)SIM_BASE) -/** Array initializer of SIM peripheral base addresses */ -#define SIM_BASE_ADDRS { SIM_BASE } -/** Array initializer of SIM peripheral base pointers */ -#define SIM_BASE_PTRS { SIM } - -/*! - * @} - */ /* end of group SIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer - * @{ - */ - -/** SMC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x18 */ - uint8_t RESERVED_2[4]; - __I uint32_t SRS; /**< System Reset Status, offset: 0x20 */ - __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x24 */ - __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x28 */ - __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x2C */ - __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x30 */ - uint8_t RESERVED_3[12]; - __IO uint32_t MR; /**< Mode Register, offset: 0x40 */ - uint8_t RESERVED_4[12]; - __IO uint32_t FM; /**< Force Mode Register, offset: 0x50 */ - uint8_t RESERVED_5[12]; - __IO uint32_t SRAMLPR; /**< SRAM Low Power Register, offset: 0x60 */ - __IO uint32_t SRAMDSR; /**< SRAM Deep Sleep Register, offset: 0x64 */ -} SMC_Type; - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SMC_VERID_FEATURE_MASK (0xFFFFU) -#define SMC_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000010101011..Default features supported - */ -#define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) -#define SMC_VERID_MINOR_MASK (0xFF0000U) -#define SMC_VERID_MINOR_SHIFT (16U) -#define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) -#define SMC_VERID_MAJOR_MASK (0xFF000000U) -#define SMC_VERID_MAJOR_SHIFT (24U) -#define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define SMC_PARAM_PWRD_INDPT_MASK (0x1U) -#define SMC_PARAM_PWRD_INDPT_SHIFT (0U) -#define SMC_PARAM_PWRD_INDPT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_PWRD_INDPT_SHIFT)) & SMC_PARAM_PWRD_INDPT_MASK) -/*! @} */ - -/*! @name PMPROT - Power Mode Protection register */ -/*! @{ */ -#define SMC_PMPROT_AVLLS_MASK (0x3U) -#define SMC_PMPROT_AVLLS_SHIFT (0U) -/*! AVLLS - Allow Very-Low-Leakage Stop Mode - * 0b00..VLLS mode is not allowed - * 0b01..VLLS0/1 mode is allowed - * 0b10..VLLS2/3 mode is allowed - * 0b11..VLLS0/1/2/3 mode is allowed - */ -#define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) -#define SMC_PMPROT_ALLS_MASK (0x8U) -#define SMC_PMPROT_ALLS_SHIFT (3U) -/*! ALLS - Allow Low-Leakage Stop Mode - * 0b0..LLS is not allowed - * 0b1..LLS is allowed - */ -#define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) -#define SMC_PMPROT_AVLP_MASK (0x20U) -#define SMC_PMPROT_AVLP_SHIFT (5U) -/*! AVLP - Allow Very-Low-Power Modes - * 0b0..VLPR, VLPW, and VLPS are not allowed. - * 0b1..VLPR, VLPW, and VLPS are allowed. - */ -#define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) -#define SMC_PMPROT_AHSRUN_MASK (0x80U) -#define SMC_PMPROT_AHSRUN_SHIFT (7U) -/*! AHSRUN - Allow High Speed Run mode - * 0b0..HSRUN is not allowed - * 0b1..HSRUN is allowed - */ -#define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) -/*! @} */ - -/*! @name PMCTRL - Power Mode Control register */ -/*! @{ */ -#define SMC_PMCTRL_STOPM_MASK (0x7U) -#define SMC_PMCTRL_STOPM_SHIFT (0U) -/*! STOPM - Stop Mode Control - * 0b000..Normal Stop (STOP) - * 0b001..Reserved - * 0b010..Very-Low-Power Stop (VLPS) - * 0b011..Low-Leakage Stop (LLS) - * 0b100..Very-Low-Leakage Stop with SRAM retention(VLLS2/3) - * 0b101..Reserved - * 0b110..Very-Low-Leakage Stop without SRAM retention (VLLS0/1) - * 0b111..Reserved - */ -#define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) -#define SMC_PMCTRL_RUNM_MASK (0x300U) -#define SMC_PMCTRL_RUNM_SHIFT (8U) -/*! RUNM - Run Mode Control - * 0b00..Normal Run mode (RUN) - * 0b01..Reserved - * 0b10..Very-Low-Power Run mode (VLPR) - * 0b11..High Speed Run mode (HSRUN) - */ -#define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) -#define SMC_PMCTRL_PSTOPO_MASK (0x30000U) -#define SMC_PMCTRL_PSTOPO_SHIFT (16U) -/*! PSTOPO - Partial Stop Option - * 0b00..STOP - Normal Stop mode - * 0b01..PSTOP1 - Partial Stop with system and bus clock disabled - * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled - * 0b11..PSTOP3 - Partial Stop with system clock enabled and bus clock enabled - */ -#define SMC_PMCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_PSTOPO_SHIFT)) & SMC_PMCTRL_PSTOPO_MASK) -/*! @} */ - -/*! @name PMSTAT - Power Mode Status register */ -/*! @{ */ -#define SMC_PMSTAT_PMSTAT_MASK (0xFFU) -#define SMC_PMSTAT_PMSTAT_SHIFT (0U) -/*! PMSTAT - Power Mode Status - * 0b00000001..Current power mode is RUN. - * 0b00000010..Current power mode is any STOP mode. - * 0b00000100..Current power mode is VLPR. - * 0b10000000..Current power mode is HSRUN - */ -#define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) -#define SMC_PMSTAT_STOPSTAT_MASK (0xFF000000U) -#define SMC_PMSTAT_STOPSTAT_SHIFT (24U) -#define SMC_PMSTAT_STOPSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_STOPSTAT_SHIFT)) & SMC_PMSTAT_STOPSTAT_MASK) -/*! @} */ - -/*! @name SRS - System Reset Status */ -/*! @{ */ -#define SMC_SRS_WAKEUP_MASK (0x1U) -#define SMC_SRS_WAKEUP_SHIFT (0U) -/*! WAKEUP - Wakeup Reset - * 0b0..Reset not generated by wakeup from VLLS mode. - * 0b1..Reset generated by wakeup from VLLS mode. - */ -#define SMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WAKEUP_SHIFT)) & SMC_SRS_WAKEUP_MASK) -#define SMC_SRS_POR_MASK (0x2U) -#define SMC_SRS_POR_SHIFT (1U) -/*! POR - POR Reset - * 0b0..Reset not generated by POR. - * 0b1..Reset generated by POR. - */ -#define SMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_POR_SHIFT)) & SMC_SRS_POR_MASK) -#define SMC_SRS_LVD_MASK (0x4U) -#define SMC_SRS_LVD_SHIFT (2U) -/*! LVD - LVD Reset - * 0b0..Reset not generated by LVD. - * 0b1..Reset generated by LVD. - */ -#define SMC_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LVD_SHIFT)) & SMC_SRS_LVD_MASK) -#define SMC_SRS_HVD_MASK (0x8U) -#define SMC_SRS_HVD_SHIFT (3U) -/*! HVD - HVD Reset - * 0b0..Reset not generated by HVD. - * 0b1..Reset generated by HVD. - */ -#define SMC_SRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_HVD_SHIFT)) & SMC_SRS_HVD_MASK) -#define SMC_SRS_WARM_MASK (0x10U) -#define SMC_SRS_WARM_SHIFT (4U) -/*! WARM - Warm Reset - * 0b0..Reset not generated by Warm Reset source. - * 0b1..Reset generated by Warm Reset source. - */ -#define SMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WARM_SHIFT)) & SMC_SRS_WARM_MASK) -#define SMC_SRS_FATAL_MASK (0x20U) -#define SMC_SRS_FATAL_SHIFT (5U) -/*! FATAL - Fatal Reset - * 0b0..Reset was not generated by a fatal reset source. - * 0b1..Reset was generated by a fatal reset source. - */ -#define SMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_FATAL_SHIFT)) & SMC_SRS_FATAL_MASK) -#define SMC_SRS_CORE_MASK (0x80U) -#define SMC_SRS_CORE_SHIFT (7U) -/*! CORE - Core Reset - * 0b0..Reset source was not core only reset. - * 0b1..Reset source was core reset and reset the core only. - */ -#define SMC_SRS_CORE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE_SHIFT)) & SMC_SRS_CORE_MASK) -#define SMC_SRS_PIN_MASK (0x100U) -#define SMC_SRS_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset was not generated from the assertion of RESET_B pin. - * 0b1..Reset was generated from the assertion of RESET_B pin. - */ -#define SMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_PIN_SHIFT)) & SMC_SRS_PIN_MASK) -#define SMC_SRS_MDM_MASK (0x200U) -#define SMC_SRS_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset was not generated from the MDM reset request. - * 0b1..Reset was generated from the MDM reset request. - */ -#define SMC_SRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_MDM_SHIFT)) & SMC_SRS_MDM_MASK) -#define SMC_SRS_RSTACK_MASK (0x400U) -#define SMC_SRS_RSTACK_SHIFT (10U) -/*! RSTACK - Reset Timeout - * 0b0..Reset not generated from Reset Controller Timeout. - * 0b1..Reset generated from Reset Controller Timeout. - */ -#define SMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_RSTACK_SHIFT)) & SMC_SRS_RSTACK_MASK) -#define SMC_SRS_STOPACK_MASK (0x800U) -#define SMC_SRS_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset not generated by Stop Controller Timeout. - * 0b1..Reset generated by Stop Controller Timeout. - */ -#define SMC_SRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_STOPACK_SHIFT)) & SMC_SRS_STOPACK_MASK) -#define SMC_SRS_SCG_MASK (0x1000U) -#define SMC_SRS_SCG_SHIFT (12U) -/*! SCG - SCG Reset - * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. - * 0b1..Reset is generated from an SCG loss of lock or loss of clock. - */ -#define SMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK) -#define SMC_SRS_WDOG_MASK (0x2000U) -#define SMC_SRS_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset is not generated from the WatchDog timeout. - * 0b1..Reset is generated from the WatchDog timeout. - */ -#define SMC_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WDOG_SHIFT)) & SMC_SRS_WDOG_MASK) -#define SMC_SRS_SW_MASK (0x4000U) -#define SMC_SRS_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset not generated by software request from core. - * 0b1..Reset generated by software request from core. - */ -#define SMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SW_SHIFT)) & SMC_SRS_SW_MASK) -#define SMC_SRS_LOCKUP_MASK (0x8000U) -#define SMC_SRS_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset not generated by core lockup or exception. - * 0b1..Reset generated by core lockup or exception. - */ -#define SMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LOCKUP_SHIFT)) & SMC_SRS_LOCKUP_MASK) -#define SMC_SRS_CORE0_MASK (0x10000U) -#define SMC_SRS_CORE0_SHIFT (16U) -/*! CORE0 - Core0 System Reset - * 0b0..Reset not generated from Core0 system reset source. - * 0b1..Reset generated from Core0 system reset source. - */ -#define SMC_SRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE0_SHIFT)) & SMC_SRS_CORE0_MASK) -#define SMC_SRS_CORE1_MASK (0x20000U) -#define SMC_SRS_CORE1_SHIFT (17U) -/*! CORE1 - Core1 System Reset - * 0b0..Reset not generated from Core1 system reset source. - * 0b1..Reset generated from Core1 system reset source. - */ -#define SMC_SRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE1_SHIFT)) & SMC_SRS_CORE1_MASK) -#define SMC_SRS_JTAG_MASK (0x10000000U) -#define SMC_SRS_JTAG_SHIFT (28U) -/*! JTAG - JTAG System Reset - * 0b0..Reset not generated by JTAG system reset. - * 0b1..Reset generated by JTAG system reset. - */ -#define SMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_JTAG_SHIFT)) & SMC_SRS_JTAG_MASK) -/*! @} */ - -/*! @name RPC - Reset Pin Control */ -/*! @{ */ -#define SMC_RPC_FILTCFG_MASK (0x1FU) -#define SMC_RPC_FILTCFG_SHIFT (0U) -#define SMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTCFG_SHIFT)) & SMC_RPC_FILTCFG_MASK) -#define SMC_RPC_FILTEN_MASK (0x100U) -#define SMC_RPC_FILTEN_SHIFT (8U) -/*! FILTEN - Filter Enable - * 0b0..Slow clock reset pin filter disabled. - * 0b1..Slow clock reset pin filter enabled in Run modes. - */ -#define SMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTEN_SHIFT)) & SMC_RPC_FILTEN_MASK) -#define SMC_RPC_LPOFEN_MASK (0x200U) -#define SMC_RPC_LPOFEN_SHIFT (9U) -/*! LPOFEN - LPO Filter Enable - * 0b0..LPO clock reset pin filter disabled. - * 0b1..LPO clock reset pin filter enabled in all modes. - */ -#define SMC_RPC_LPOFEN(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_LPOFEN_SHIFT)) & SMC_RPC_LPOFEN_MASK) -/*! @} */ - -/*! @name SSRS - Sticky System Reset Status */ -/*! @{ */ -#define SMC_SSRS_WAKEUP_MASK (0x1U) -#define SMC_SSRS_WAKEUP_SHIFT (0U) -/*! WAKEUP - Wakeup Reset - * 0b0..Reset not generated by wakeup from VLLS mode. - * 0b1..Reset generated by wakeup from VLLS mode. - */ -#define SMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WAKEUP_SHIFT)) & SMC_SSRS_WAKEUP_MASK) -#define SMC_SSRS_POR_MASK (0x2U) -#define SMC_SSRS_POR_SHIFT (1U) -/*! POR - POR Reset - * 0b0..Reset not generated by POR. - * 0b1..Reset generated by POR. - */ -#define SMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_POR_SHIFT)) & SMC_SSRS_POR_MASK) -#define SMC_SSRS_LVD_MASK (0x4U) -#define SMC_SSRS_LVD_SHIFT (2U) -/*! LVD - LVD Reset - * 0b0..Reset not generated by LVD. - * 0b1..Reset generated by LVD. - */ -#define SMC_SSRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LVD_SHIFT)) & SMC_SSRS_LVD_MASK) -#define SMC_SSRS_HVD_MASK (0x8U) -#define SMC_SSRS_HVD_SHIFT (3U) -/*! HVD - HVD Reset - * 0b0..Reset not generated by HVD. - * 0b1..Reset generated by HVD. - */ -#define SMC_SSRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_HVD_SHIFT)) & SMC_SSRS_HVD_MASK) -#define SMC_SSRS_WARM_MASK (0x10U) -#define SMC_SSRS_WARM_SHIFT (4U) -/*! WARM - Warm Reset - * 0b0..Reset not generated by system reset source. - * 0b1..Reset generated by system reset source. - */ -#define SMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WARM_SHIFT)) & SMC_SSRS_WARM_MASK) -#define SMC_SSRS_FATAL_MASK (0x20U) -#define SMC_SSRS_FATAL_SHIFT (5U) -/*! FATAL - Fatal Reset - * 0b0..Reset was not generated by a fatal reset source. - * 0b1..Reset was generated by a fatal reset source. - */ -#define SMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_FATAL_SHIFT)) & SMC_SSRS_FATAL_MASK) -#define SMC_SSRS_PIN_MASK (0x100U) -#define SMC_SSRS_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset was not generated from the RESET_B pin. - * 0b1..Reset was generated from the RESET_B pin. - */ -#define SMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_PIN_SHIFT)) & SMC_SSRS_PIN_MASK) -#define SMC_SSRS_MDM_MASK (0x200U) -#define SMC_SSRS_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset was not generated from the MDM reset request. - * 0b1..Reset was generated from the MDM reset request. - */ -#define SMC_SSRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_MDM_SHIFT)) & SMC_SSRS_MDM_MASK) -#define SMC_SSRS_RSTACK_MASK (0x400U) -#define SMC_SSRS_RSTACK_SHIFT (10U) -/*! RSTACK - Reset Timeout - * 0b0..Reset not generated from Reset Controller Timeout. - * 0b1..Reset generated from Reset Controller Timeout. - */ -#define SMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_RSTACK_SHIFT)) & SMC_SSRS_RSTACK_MASK) -#define SMC_SSRS_STOPACK_MASK (0x800U) -#define SMC_SSRS_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset not generated by Stop Controller Timeout. - * 0b1..Reset generated by Stop Controller Timeout. - */ -#define SMC_SSRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_STOPACK_SHIFT)) & SMC_SSRS_STOPACK_MASK) -#define SMC_SSRS_SCG_MASK (0x1000U) -#define SMC_SSRS_SCG_SHIFT (12U) -/*! SCG - SCG Reset - * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. - * 0b1..Reset is generated from an SCG loss of lock or loss of clock. - */ -#define SMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK) -#define SMC_SSRS_WDOG_MASK (0x2000U) -#define SMC_SSRS_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset is not generated from the WatchDog timeout. - * 0b1..Reset is generated from the WatchDog timeout. - */ -#define SMC_SSRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WDOG_SHIFT)) & SMC_SSRS_WDOG_MASK) -#define SMC_SSRS_SW_MASK (0x4000U) -#define SMC_SSRS_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset not generated by software request from core. - * 0b1..Reset generated by software request from core. - */ -#define SMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SW_SHIFT)) & SMC_SSRS_SW_MASK) -#define SMC_SSRS_LOCKUP_MASK (0x8000U) -#define SMC_SSRS_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset not generated by core lockup. - * 0b1..Reset generated by core lockup. - */ -#define SMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LOCKUP_SHIFT)) & SMC_SSRS_LOCKUP_MASK) -#define SMC_SSRS_CORE0_MASK (0x10000U) -#define SMC_SSRS_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Reset not generated from Core0 reset source. - * 0b1..Reset generated from Core0 reset source. - */ -#define SMC_SSRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE0_SHIFT)) & SMC_SSRS_CORE0_MASK) -#define SMC_SSRS_CORE1_MASK (0x20000U) -#define SMC_SSRS_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Reset not generated from Core1 reset source. - * 0b1..Reset generated from Core1 reset source. - */ -#define SMC_SSRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE1_SHIFT)) & SMC_SSRS_CORE1_MASK) -#define SMC_SSRS_JTAG_MASK (0x10000000U) -#define SMC_SSRS_JTAG_SHIFT (28U) -/*! JTAG - JTAG System Reset - * 0b0..Reset not generated by JTAG system reset. - * 0b1..Reset generated by JTAG system reset. - */ -#define SMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_JTAG_SHIFT)) & SMC_SSRS_JTAG_MASK) -/*! @} */ - -/*! @name SRIE - System Reset Interrupt Enable */ -/*! @{ */ -#define SMC_SRIE_PIN_MASK (0x100U) -#define SMC_SRIE_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_PIN_SHIFT)) & SMC_SRIE_PIN_MASK) -#define SMC_SRIE_MDM_MASK (0x200U) -#define SMC_SRIE_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_MDM_SHIFT)) & SMC_SRIE_MDM_MASK) -#define SMC_SRIE_STOPACK_MASK (0x800U) -#define SMC_SRIE_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_STOPACK_SHIFT)) & SMC_SRIE_STOPACK_MASK) -#define SMC_SRIE_WDOG_MASK (0x2000U) -#define SMC_SRIE_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_WDOG_SHIFT)) & SMC_SRIE_WDOG_MASK) -#define SMC_SRIE_SW_MASK (0x4000U) -#define SMC_SRIE_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_SW_SHIFT)) & SMC_SRIE_SW_MASK) -#define SMC_SRIE_LOCKUP_MASK (0x8000U) -#define SMC_SRIE_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_LOCKUP_SHIFT)) & SMC_SRIE_LOCKUP_MASK) -#define SMC_SRIE_CORE0_MASK (0x10000U) -#define SMC_SRIE_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE0_SHIFT)) & SMC_SRIE_CORE0_MASK) -#define SMC_SRIE_CORE1_MASK (0x20000U) -#define SMC_SRIE_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE1_SHIFT)) & SMC_SRIE_CORE1_MASK) -/*! @} */ - -/*! @name SRIF - System Reset Interrupt Flag */ -/*! @{ */ -#define SMC_SRIF_PIN_MASK (0x100U) -#define SMC_SRIF_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_PIN_SHIFT)) & SMC_SRIF_PIN_MASK) -#define SMC_SRIF_MDM_MASK (0x200U) -#define SMC_SRIF_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_MDM_SHIFT)) & SMC_SRIF_MDM_MASK) -#define SMC_SRIF_STOPACK_MASK (0x800U) -#define SMC_SRIF_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_STOPACK_SHIFT)) & SMC_SRIF_STOPACK_MASK) -#define SMC_SRIF_WDOG_MASK (0x2000U) -#define SMC_SRIF_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_WDOG_SHIFT)) & SMC_SRIF_WDOG_MASK) -#define SMC_SRIF_SW_MASK (0x4000U) -#define SMC_SRIF_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_SW_SHIFT)) & SMC_SRIF_SW_MASK) -#define SMC_SRIF_LOCKUP_MASK (0x8000U) -#define SMC_SRIF_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_LOCKUP_SHIFT)) & SMC_SRIF_LOCKUP_MASK) -#define SMC_SRIF_CORE0_MASK (0x10000U) -#define SMC_SRIF_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE0_SHIFT)) & SMC_SRIF_CORE0_MASK) -#define SMC_SRIF_CORE1_MASK (0x20000U) -#define SMC_SRIF_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE1_SHIFT)) & SMC_SRIF_CORE1_MASK) -/*! @} */ - -/*! @name MR - Mode Register */ -/*! @{ */ -#define SMC_MR_BOOTCFG_MASK (0x3U) -#define SMC_MR_BOOTCFG_SHIFT (0U) -/*! BOOTCFG - Boot Configuration - * 0b00..Boot from Flash. - * 0b01..Boot from ROM due to BOOTCFG0 pin assertion. - * 0b10..Boot from ROM due to FOPT configuration. - * 0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration. - */ -#define SMC_MR_BOOTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_MR_BOOTCFG_SHIFT)) & SMC_MR_BOOTCFG_MASK) -/*! @} */ - -/*! @name FM - Force Mode Register */ -/*! @{ */ -#define SMC_FM_FORCECFG_MASK (0x3U) -#define SMC_FM_FORCECFG_SHIFT (0U) -/*! FORCECFG - Boot Configuration - * 0b00..No effect. - * 0b01..Assert corresponding bit in Mode Register on next system reset. - */ -#define SMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_FM_FORCECFG_SHIFT)) & SMC_FM_FORCECFG_MASK) -/*! @} */ - -/*! @name SRAMLPR - SRAM Low Power Register */ -/*! @{ */ -#define SMC_SRAMLPR_LPE_MASK (0xFFFFFFFFU) -#define SMC_SRAMLPR_LPE_SHIFT (0U) -#define SMC_SRAMLPR_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRAMLPR_LPE_SHIFT)) & SMC_SRAMLPR_LPE_MASK) -/*! @} */ - -/*! @name SRAMDSR - SRAM Deep Sleep Register */ -/*! @{ */ -#define SMC_SRAMDSR_DSE_MASK (0xFFFFFFFFU) -#define SMC_SRAMDSR_DSE_SHIFT (0U) -#define SMC_SRAMDSR_DSE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRAMDSR_DSE_SHIFT)) & SMC_SRAMDSR_DSE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SMC_Register_Masks */ - - -/* SMC - Peripheral instance base addresses */ -/** Peripheral SMC0 base address */ -#define SMC0_BASE (0x40020000u) -/** Peripheral SMC0 base pointer */ -#define SMC0 ((SMC_Type *)SMC0_BASE) -/** Peripheral SMC1 base address */ -#define SMC1_BASE (0x41020000u) -/** Peripheral SMC1 base pointer */ -#define SMC1 ((SMC_Type *)SMC1_BASE) -/** Array initializer of SMC peripheral base addresses */ -#define SMC_BASE_ADDRS { SMC0_BASE, SMC1_BASE } -/** Array initializer of SMC peripheral base pointers */ -#define SMC_BASE_PTRS { SMC0, SMC1 } -/** Interrupt vectors for the SMC peripheral type */ -#define SMC_IRQS { CMC0_IRQn, NotAvail_IRQn } - -/*! - * @} - */ /* end of group SMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPM_Peripheral_Access_Layer SPM Peripheral Access Layer - * @{ - */ - -/** SPM - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t RSR; /**< Regulator Status Register, offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RCTRL; /**< Run Control Register, offset: 0x10 */ - __IO uint32_t LPCTRL; /**< Low Power Control Register, offset: 0x14 */ - uint8_t RESERVED_2[232]; - __IO uint32_t CORERCNFG; /**< CORE LDO RUN Configuration Register, offset: 0x100 */ - __IO uint32_t CORELPCNFG; /**< CORE LDO Low Power Configuration register, offset: 0x104 */ - __IO uint32_t CORESC; /**< Core LDO Status And Control register, offset: 0x108 */ - __IO uint32_t LVDSC1; /**< Low Voltage Detect Status and Control 1 register, offset: 0x10C */ - __IO uint32_t LVDSC2; /**< Low Voltage Detect Status and Control 2 register, offset: 0x110 */ - __IO uint32_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0x114 */ - uint8_t RESERVED_3[232]; - __IO uint32_t RFLDOLPCNFG; /**< RF LDO Low Power Configuration register, offset: 0x200 */ - __IO uint32_t RFLDOSC; /**< RF LDO Status And Control register, offset: 0x204 */ - uint8_t RESERVED_4[252]; - __IO uint32_t DCDCSC; /**< DCDC Status Control Register, offset: 0x304 */ - uint8_t RESERVED_5[4]; - __IO uint32_t DCDCC1; /**< DCDC Control Register 1, offset: 0x30C */ - __IO uint32_t DCDCC2; /**< DCDC Control Register 2, offset: 0x310 */ - __IO uint32_t DCDCC3; /**< DCDC Control Register 3, offset: 0x314 */ - __IO uint32_t DCDCC4; /**< DCDC Control Register 4, offset: 0x318 */ - uint8_t RESERVED_6[4]; - __IO uint32_t DCDCC6; /**< DCDC Control Register 6, offset: 0x320 */ - uint8_t RESERVED_7[232]; - __IO uint32_t LPREQPINCNTRL; /**< LP Request Pin Control Register, offset: 0x40C */ -} SPM_Type; - -/* ---------------------------------------------------------------------------- - -- SPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPM_Register_Masks SPM Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SPM_VERID_FEATURE_MASK (0xFFFFU) -#define SPM_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - */ -#define SPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_FEATURE_SHIFT)) & SPM_VERID_FEATURE_MASK) -#define SPM_VERID_MINOR_MASK (0xFF0000U) -#define SPM_VERID_MINOR_SHIFT (16U) -#define SPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MINOR_SHIFT)) & SPM_VERID_MINOR_MASK) -#define SPM_VERID_MAJOR_MASK (0xFF000000U) -#define SPM_VERID_MAJOR_SHIFT (24U) -#define SPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MAJOR_SHIFT)) & SPM_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name RSR - Regulator Status Register */ -/*! @{ */ -#define SPM_RSR_REGSEL_MASK (0x7U) -#define SPM_RSR_REGSEL_SHIFT (0U) -#define SPM_RSR_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_REGSEL_SHIFT)) & SPM_RSR_REGSEL_MASK) -#define SPM_RSR_MCUPMSTAT_MASK (0x1F0000U) -#define SPM_RSR_MCUPMSTAT_SHIFT (16U) -/*! MCUPMSTAT - MCU Power Mode Status - * 0b00000..Reserved - * 0b00001..Last Low Power mode is STOP. - * 0b00010..Last Low Power mode is VLPS. - * 0b00100..Last Low Power mode is LLS. - * 0b01000..Last Low Power mode is VLLS23. - * 0b10000..Last Low Power mode is VLLS01. - */ -#define SPM_RSR_MCUPMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_MCUPMSTAT_SHIFT)) & SPM_RSR_MCUPMSTAT_MASK) -#define SPM_RSR_RFPMSTAT_MASK (0x7000000U) -#define SPM_RSR_RFPMSTAT_SHIFT (24U) -/*! RFPMSTAT - RADIO Power Mode Status - * 0b000..Reserved - * 0b001..Current Power mode is VLPS. - * 0b010..Current Power mode is LLS. - * 0b100..Current Power mode is VLLS. - */ -#define SPM_RSR_RFPMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFPMSTAT_SHIFT)) & SPM_RSR_RFPMSTAT_MASK) -#define SPM_RSR_RFRUNFORCE_MASK (0x8000000U) -#define SPM_RSR_RFRUNFORCE_SHIFT (27U) -/*! RFRUNFORCE - RADIO Run Force Power Mode Status - * 0b0..Radio Run Force Regulator Off - * 0b1..Radio Run Force Regulator On. - */ -#define SPM_RSR_RFRUNFORCE(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFRUNFORCE_SHIFT)) & SPM_RSR_RFRUNFORCE_MASK) -/*! @} */ - -/*! @name RCTRL - Run Control Register */ -/*! @{ */ -#define SPM_RCTRL_REGSEL_MASK (0x7U) -#define SPM_RCTRL_REGSEL_SHIFT (0U) -#define SPM_RCTRL_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RCTRL_REGSEL_SHIFT)) & SPM_RCTRL_REGSEL_MASK) -/*! @} */ - -/*! @name LPCTRL - Low Power Control Register */ -/*! @{ */ -#define SPM_LPCTRL_REGSEL_MASK (0x7U) -#define SPM_LPCTRL_REGSEL_SHIFT (0U) -#define SPM_LPCTRL_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPCTRL_REGSEL_SHIFT)) & SPM_LPCTRL_REGSEL_MASK) -/*! @} */ - -/*! @name CORERCNFG - CORE LDO RUN Configuration Register */ -/*! @{ */ -#define SPM_CORERCNFG_VDDIOVDDMEN_MASK (0x10000U) -#define SPM_CORERCNFG_VDDIOVDDMEN_SHIFT (16U) -/*! VDDIOVDDMEN - VDDIOVDDMEN - * 0b0..VDDIO voltage monitor disabled in run modes. - * 0b1..VDDIO voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_VDDIOVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORERCNFG_VDDIOVDDMEN_MASK) -#define SPM_CORERCNFG_USBVDDMEN_MASK (0x20000U) -#define SPM_CORERCNFG_USBVDDMEN_SHIFT (17U) -/*! USBVDDMEN - USBVDDMEN - * 0b0..USB voltage monitor disabled in run modes. - * 0b1..USB voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_USBVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_USBVDDMEN_SHIFT)) & SPM_CORERCNFG_USBVDDMEN_MASK) -#define SPM_CORERCNFG_RTCVDDMEN_MASK (0x40000U) -#define SPM_CORERCNFG_RTCVDDMEN_SHIFT (18U) -/*! RTCVDDMEN - RTCVDDMEN - * 0b0..RTC voltage monitor disabled in run modes. - * 0b1..RTC voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_RTCVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_RTCVDDMEN_SHIFT)) & SPM_CORERCNFG_RTCVDDMEN_MASK) -/*! @} */ - -/*! @name CORELPCNFG - CORE LDO Low Power Configuration register */ -/*! @{ */ -#define SPM_CORELPCNFG_LPSEL_MASK (0x2U) -#define SPM_CORELPCNFG_LPSEL_SHIFT (1U) -/*! LPSEL - LPSEL - * 0b0..Core LDO enters low power state in VLP/Stop modes. - * 0b1..Core LDO remains in high power state in VLP/Stop modes. If LPSEL = 1 in a low power mode then BGEN must also be set to 1. - */ -#define SPM_CORELPCNFG_LPSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPSEL_SHIFT)) & SPM_CORELPCNFG_LPSEL_MASK) -#define SPM_CORELPCNFG_BGEN_MASK (0x4U) -#define SPM_CORELPCNFG_BGEN_SHIFT (2U) -/*! BGEN - Bandgap Enable In Low Power Mode Operation - * 0b0..Bandgap is disabled in STOP/VLP/LLS and VLLS modes. - * 0b1..Bandgap remains enabled in STOP/VLP/LLS and VLLS modes. - */ -#define SPM_CORELPCNFG_BGEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGEN_SHIFT)) & SPM_CORELPCNFG_BGEN_MASK) -#define SPM_CORELPCNFG_BGBEN_MASK (0x8U) -#define SPM_CORELPCNFG_BGBEN_SHIFT (3U) -/*! BGBEN - Bandgap Buffer Enable - * 0b0..Bandgap buffer not enabled - * 0b1..Bandgap buffer enabled BGEN must be set when this bit is also set. - */ -#define SPM_CORELPCNFG_BGBEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBEN_SHIFT)) & SPM_CORELPCNFG_BGBEN_MASK) -#define SPM_CORELPCNFG_BGBDS_MASK (0x10U) -#define SPM_CORELPCNFG_BGBDS_SHIFT (4U) -/*! BGBDS - Bandgap Buffer Drive Select - * 0b0..Low Drive - * 0b1..High Drive - */ -#define SPM_CORELPCNFG_BGBDS(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBDS_SHIFT)) & SPM_CORELPCNFG_BGBDS_MASK) -#define SPM_CORELPCNFG_LPOEN_MASK (0x80U) -#define SPM_CORELPCNFG_LPOEN_SHIFT (7U) -/*! LPOEN - LPO Enabled - * 0b0..LPO is disabled in VLLS modes. - * 0b1..LPO remains enabled in VLLS modes. - */ -#define SPM_CORELPCNFG_LPOEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPOEN_SHIFT)) & SPM_CORELPCNFG_LPOEN_MASK) -#define SPM_CORELPCNFG_POREN_MASK (0x100U) -#define SPM_CORELPCNFG_POREN_SHIFT (8U) -/*! POREN - POR Enabled - * 0b0..POR brownout is disabled in VLLS0/1 mode. - * 0b1..POR brownout remains enabled in VLLS0/1 mode. - */ -#define SPM_CORELPCNFG_POREN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_POREN_SHIFT)) & SPM_CORELPCNFG_POREN_MASK) -#define SPM_CORELPCNFG_LVDEN_MASK (0x200U) -#define SPM_CORELPCNFG_LVDEN_SHIFT (9U) -/*! LVDEN - LVD Enabled - * 0b0..LVD/HVD is disabled in low power modes. - * 0b1..LVD/HVD remains enabled in low power modes. BGEN must be set when this bit is also set. - */ -#define SPM_CORELPCNFG_LVDEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LVDEN_SHIFT)) & SPM_CORELPCNFG_LVDEN_MASK) -#define SPM_CORELPCNFG_LPHIDRIVE_MASK (0x4000U) -#define SPM_CORELPCNFG_LPHIDRIVE_SHIFT (14U) -/*! LPHIDRIVE - LPHIDRIVE - * 0b0..High Drive disabled. - * 0b1..High Drive enabled. - */ -#define SPM_CORELPCNFG_LPHIDRIVE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPHIDRIVE_SHIFT)) & SPM_CORELPCNFG_LPHIDRIVE_MASK) -#define SPM_CORELPCNFG_ALLREFEN_MASK (0x8000U) -#define SPM_CORELPCNFG_ALLREFEN_SHIFT (15U) -/*! ALLREFEN - All Reference Enable. This bit only has an affect in VLLS0/1. - * 0b0..All references are disabled in VLLS. - * 0b1..All references are enabled in VLLS0/1. - */ -#define SPM_CORELPCNFG_ALLREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_ALLREFEN_SHIFT)) & SPM_CORELPCNFG_ALLREFEN_MASK) -#define SPM_CORELPCNFG_VDDIOVDDMEN_MASK (0x10000U) -#define SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT (16U) -/*! VDDIOVDDMEN - VDDIOVDDMEN - * 0b0..VDDIO voltage monitor disabled in lp modes. - * 0b1..VDDIO voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_VDDIOVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORELPCNFG_VDDIOVDDMEN_MASK) -#define SPM_CORELPCNFG_USBVDDMEN_MASK (0x20000U) -#define SPM_CORELPCNFG_USBVDDMEN_SHIFT (17U) -/*! USBVDDMEN - USBVDDMEN - * 0b0..USB voltage monitor disabled in lp modes. - * 0b1..USB voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_USBVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_USBVDDMEN_SHIFT)) & SPM_CORELPCNFG_USBVDDMEN_MASK) -#define SPM_CORELPCNFG_RTCVDDMEN_MASK (0x40000U) -#define SPM_CORELPCNFG_RTCVDDMEN_SHIFT (18U) -/*! RTCVDDMEN - RTCVDDMEN - * 0b0..RTC voltage monitor disabled in lp modes. - * 0b1..RTC voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_RTCVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_RTCVDDMEN_SHIFT)) & SPM_CORELPCNFG_RTCVDDMEN_MASK) -/*! @} */ - -/*! @name CORESC - Core LDO Status And Control register */ -/*! @{ */ -#define SPM_CORESC_REGONS_MASK (0x4U) -#define SPM_CORESC_REGONS_SHIFT (2U) -/*! REGONS - CORE LDO Regulator in Run Regulation Status - * 0b0..Regulator is in low power state or in transition to/from it. - * 0b1..Regulator is in high power state. - */ -#define SPM_CORESC_REGONS(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_REGONS_SHIFT)) & SPM_CORESC_REGONS_MASK) -#define SPM_CORESC_ACKISO_MASK (0x8U) -#define SPM_CORESC_ACKISO_SHIFT (3U) -/*! ACKISO - Acknowledge Isolation - * 0b0..Peripherals and I/O pads are in normal run state. - * 0b1..Certain peripherals and I/O pads are in a isolated and latched state. - */ -#define SPM_CORESC_ACKISO(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_ACKISO_SHIFT)) & SPM_CORESC_ACKISO_MASK) -#define SPM_CORESC_TRIM_MASK (0x3F00U) -#define SPM_CORESC_TRIM_SHIFT (8U) -#define SPM_CORESC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_TRIM_SHIFT)) & SPM_CORESC_TRIM_MASK) -#define SPM_CORESC_VDDIOOVRIDE_MASK (0x10000U) -#define SPM_CORESC_VDDIOOVRIDE_SHIFT (16U) -/*! VDDIOOVRIDE - VDDIOOVRIDE - * 0b0..VDDIOOK status set to 1'b0. - * 0b1..VDDIOOK status set to 1'b1. - */ -#define SPM_CORESC_VDDIOOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOVRIDE_SHIFT)) & SPM_CORESC_VDDIOOVRIDE_MASK) -#define SPM_CORESC_USBOVRIDE_MASK (0x20000U) -#define SPM_CORESC_USBOVRIDE_SHIFT (17U) -/*! USBOVRIDE - USBOVRIDE - * 0b0..USBVDDOK status set to 1'b0. - * 0b1..USBVDDOK status set to 1'b1. - */ -#define SPM_CORESC_USBOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBOVRIDE_SHIFT)) & SPM_CORESC_USBOVRIDE_MASK) -#define SPM_CORESC_RTCOVRIDE_MASK (0x40000U) -#define SPM_CORESC_RTCOVRIDE_SHIFT (18U) -/*! RTCOVRIDE - RTCOVRIDE - * 0b0..RTCVDDOK status set to 1'b0. - * 0b1..RTCVDDOK status set to 1'b1. - */ -#define SPM_CORESC_RTCOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCOVRIDE_SHIFT)) & SPM_CORESC_RTCOVRIDE_MASK) -#define SPM_CORESC_VDDIOOK_MASK (0x1000000U) -#define SPM_CORESC_VDDIOOK_SHIFT (24U) -#define SPM_CORESC_VDDIOOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOK_SHIFT)) & SPM_CORESC_VDDIOOK_MASK) -#define SPM_CORESC_USBVDDOK_MASK (0x2000000U) -#define SPM_CORESC_USBVDDOK_SHIFT (25U) -#define SPM_CORESC_USBVDDOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBVDDOK_SHIFT)) & SPM_CORESC_USBVDDOK_MASK) -#define SPM_CORESC_RTCVDDOK_MASK (0x4000000U) -#define SPM_CORESC_RTCVDDOK_SHIFT (26U) -#define SPM_CORESC_RTCVDDOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCVDDOK_SHIFT)) & SPM_CORESC_RTCVDDOK_MASK) -/*! @} */ - -/*! @name LVDSC1 - Low Voltage Detect Status and Control 1 register */ -/*! @{ */ -#define SPM_LVDSC1_COREVDD_LVDRE_MASK (0x10U) -#define SPM_LVDSC1_COREVDD_LVDRE_SHIFT (4U) -/*! COREVDD_LVDRE - Core Low-Voltage Detect Reset Enable - * 0b0..COREVDD_LVDF does not generate hardware resets - * 0b1..Force an MCU reset when CORE_LVDF = 1 - */ -#define SPM_LVDSC1_COREVDD_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDRE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDRE_MASK) -#define SPM_LVDSC1_COREVDD_LVDIE_MASK (0x20U) -#define SPM_LVDSC1_COREVDD_LVDIE_SHIFT (5U) -/*! COREVDD_LVDIE - Low-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when LVDF = 1 - */ -#define SPM_LVDSC1_COREVDD_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDIE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDIE_MASK) -#define SPM_LVDSC1_COREVDD_LVDACK_MASK (0x40U) -#define SPM_LVDSC1_COREVDD_LVDACK_SHIFT (6U) -#define SPM_LVDSC1_COREVDD_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDACK_SHIFT)) & SPM_LVDSC1_COREVDD_LVDACK_MASK) -#define SPM_LVDSC1_COREVDD_LVDF_MASK (0x80U) -#define SPM_LVDSC1_COREVDD_LVDF_SHIFT (7U) -/*! COREVDD_LVDF - Low-Voltage Detect Flag - * 0b0..Low-voltage event not detected - * 0b1..Low-voltage event detected - */ -#define SPM_LVDSC1_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDF_SHIFT)) & SPM_LVDSC1_COREVDD_LVDF_MASK) -#define SPM_LVDSC1_VDD_LVDV_MASK (0x30000U) -#define SPM_LVDSC1_VDD_LVDV_SHIFT (16U) -/*! VDD_LVDV - VDD Low-Voltage Detect Voltage Select - * 0b00..Low trip point selected (V LVD = V LVDL ) - * 0b01..High trip point selected (V LVD = V LVDH ) - * 0b10..Reserved - * 0b11..Reserved - */ -#define SPM_LVDSC1_VDD_LVDV(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDV_SHIFT)) & SPM_LVDSC1_VDD_LVDV_MASK) -#define SPM_LVDSC1_VDD_LVDRE_MASK (0x100000U) -#define SPM_LVDSC1_VDD_LVDRE_SHIFT (20U) -/*! VDD_LVDRE - VDD Low-Voltage Detect Reset Enable - * 0b0..VDD_LVDF does not generate hardware resets - * 0b1..Force an MCU reset when VDD_LVDF = 1 - */ -#define SPM_LVDSC1_VDD_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDRE_SHIFT)) & SPM_LVDSC1_VDD_LVDRE_MASK) -#define SPM_LVDSC1_VDD_LVDIE_MASK (0x200000U) -#define SPM_LVDSC1_VDD_LVDIE_SHIFT (21U) -/*! VDD_LVDIE - VDD Low-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when VDD_LVDF = 1 - */ -#define SPM_LVDSC1_VDD_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDIE_SHIFT)) & SPM_LVDSC1_VDD_LVDIE_MASK) -#define SPM_LVDSC1_VDD_LVDACK_MASK (0x400000U) -#define SPM_LVDSC1_VDD_LVDACK_SHIFT (22U) -#define SPM_LVDSC1_VDD_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDACK_SHIFT)) & SPM_LVDSC1_VDD_LVDACK_MASK) -#define SPM_LVDSC1_VDD_LVDF_MASK (0x800000U) -#define SPM_LVDSC1_VDD_LVDF_SHIFT (23U) -/*! VDD_LVDF - VDD Low-Voltage Detect Flag - * 0b0..Low-voltage event not detected - * 0b1..Low-voltage event detected - */ -#define SPM_LVDSC1_VDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDF_SHIFT)) & SPM_LVDSC1_VDD_LVDF_MASK) -/*! @} */ - -/*! @name LVDSC2 - Low Voltage Detect Status and Control 2 register */ -/*! @{ */ -#define SPM_LVDSC2_VDD_LVWV_MASK (0x30000U) -#define SPM_LVDSC2_VDD_LVWV_SHIFT (16U) -/*! VDD_LVWV - VDD Low-Voltage Warning Voltage Select - * 0b00..Low trip point selected (V LVW = VLVW1) - * 0b01..Mid 1 trip point selected (V LVW = VLVW2) - * 0b10..Mid 2 trip point selected (V LVW = VLVW3) - * 0b11..High trip point selected (V LVW = VLVW4) - */ -#define SPM_LVDSC2_VDD_LVWV(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWV_SHIFT)) & SPM_LVDSC2_VDD_LVWV_MASK) -#define SPM_LVDSC2_VDD_LVWIE_MASK (0x200000U) -#define SPM_LVDSC2_VDD_LVWIE_SHIFT (21U) -/*! VDD_LVWIE - VDD Low-Voltage Warning Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when VDD_LVWF = 1 - */ -#define SPM_LVDSC2_VDD_LVWIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWIE_SHIFT)) & SPM_LVDSC2_VDD_LVWIE_MASK) -#define SPM_LVDSC2_VDD_LVWACK_MASK (0x400000U) -#define SPM_LVDSC2_VDD_LVWACK_SHIFT (22U) -#define SPM_LVDSC2_VDD_LVWACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWACK_SHIFT)) & SPM_LVDSC2_VDD_LVWACK_MASK) -#define SPM_LVDSC2_VDD_LVWF_MASK (0x800000U) -#define SPM_LVDSC2_VDD_LVWF_SHIFT (23U) -/*! VDD_LVWF - VDD Low-Voltage Warning Flag - * 0b0..Low-voltage warning event not detected - * 0b1..Low-voltage warning event detected - */ -#define SPM_LVDSC2_VDD_LVWF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWF_SHIFT)) & SPM_LVDSC2_VDD_LVWF_MASK) -/*! @} */ - -/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */ -/*! @{ */ -#define SPM_HVDSC1_VDD_HVDV_MASK (0x10000U) -#define SPM_HVDSC1_VDD_HVDV_SHIFT (16U) -/*! VDD_HVDV - VDD High-Voltage Detect Voltage Select - * 0b0..Low trip point selected (V VDD = V VDD_HVDL ) - * 0b1..High trip point selected (V VDD = V VDD_HVDH ) - */ -#define SPM_HVDSC1_VDD_HVDV(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDV_SHIFT)) & SPM_HVDSC1_VDD_HVDV_MASK) -#define SPM_HVDSC1_VDD_HVDRE_MASK (0x100000U) -#define SPM_HVDSC1_VDD_HVDRE_SHIFT (20U) -/*! VDD_HVDRE - VDD High-Voltage Detect Reset Enable - * 0b0..VDD HVDF does not generate hardware resets - * 0b1..Force an MCU reset when VDD_HVDF = 1 - */ -#define SPM_HVDSC1_VDD_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDRE_SHIFT)) & SPM_HVDSC1_VDD_HVDRE_MASK) -#define SPM_HVDSC1_VDD_HVDIE_MASK (0x200000U) -#define SPM_HVDSC1_VDD_HVDIE_SHIFT (21U) -/*! VDD_HVDIE - VDD High-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when HVDF = 1 - */ -#define SPM_HVDSC1_VDD_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDIE_SHIFT)) & SPM_HVDSC1_VDD_HVDIE_MASK) -#define SPM_HVDSC1_VDD_HVDACK_MASK (0x400000U) -#define SPM_HVDSC1_VDD_HVDACK_SHIFT (22U) -#define SPM_HVDSC1_VDD_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDACK_SHIFT)) & SPM_HVDSC1_VDD_HVDACK_MASK) -#define SPM_HVDSC1_VDD_HVDF_MASK (0x800000U) -#define SPM_HVDSC1_VDD_HVDF_SHIFT (23U) -/*! VDD_HVDF - VDD High-Voltage Detect Flag - * 0b0..Vdd High-voltage event not detected - * 0b1..Vdd High-voltage event detected - */ -#define SPM_HVDSC1_VDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDF_SHIFT)) & SPM_HVDSC1_VDD_HVDF_MASK) -/*! @} */ - -/*! @name RFLDOLPCNFG - RF LDO Low Power Configuration register */ -/*! @{ */ -#define SPM_RFLDOLPCNFG_LPSEL_MASK (0x2U) -#define SPM_RFLDOLPCNFG_LPSEL_SHIFT (1U) -/*! LPSEL - LPSEL - * 0b0..RF LDO regulator enters low power state in VLP/Stop modes. - * 0b1..RF LDO regulator remains in high power state in VLP/Stop modes. - */ -#define SPM_RFLDOLPCNFG_LPSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOLPCNFG_LPSEL_SHIFT)) & SPM_RFLDOLPCNFG_LPSEL_MASK) -/*! @} */ - -/*! @name RFLDOSC - RF LDO Status And Control register */ -/*! @{ */ -#define SPM_RFLDOSC_IOREGVSEL_MASK (0x1U) -#define SPM_RFLDOSC_IOREGVSEL_SHIFT (0U) -/*! IOREGVSEL - IO Regulator Voltage Select - * 0b0..Regulate to 1.8V. - * 0b1..Regulate to 1.5V. - */ -#define SPM_RFLDOSC_IOREGVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOREGVSEL_SHIFT)) & SPM_RFLDOSC_IOREGVSEL_MASK) -#define SPM_RFLDOSC_VDD1P8SEL_MASK (0x10U) -#define SPM_RFLDOSC_VDD1P8SEL_SHIFT (4U) -/*! VDD1P8SEL - VDD 1p8 SNS Pin Select - * 0b0..VDD1p8_SNS0 selected. - * 0b1..VDD1p8_SNS1 selected. - */ -#define SPM_RFLDOSC_VDD1P8SEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_VDD1P8SEL_SHIFT)) & SPM_RFLDOSC_VDD1P8SEL_MASK) -#define SPM_RFLDOSC_ISINKEN_MASK (0x20U) -#define SPM_RFLDOSC_ISINKEN_SHIFT (5U) -/*! ISINKEN - ISINKEN - * 0b0..Disable current sink feature of low power regulator. - * 0b1..Enable current sink feature of low power regulator. - */ -#define SPM_RFLDOSC_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_ISINKEN_SHIFT)) & SPM_RFLDOSC_ISINKEN_MASK) -#define SPM_RFLDOSC_IOTRIM_MASK (0x1F00U) -#define SPM_RFLDOSC_IOTRIM_SHIFT (8U) -#define SPM_RFLDOSC_IOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOTRIM_SHIFT)) & SPM_RFLDOSC_IOTRIM_MASK) -#define SPM_RFLDOSC_IOSSSEL_MASK (0x70000U) -#define SPM_RFLDOSC_IOSSSEL_SHIFT (16U) -/*! IOSSSEL - IO 1.8 Reg Soft Start Select - * 0b000..Soft Start duration set to 110us. - * 0b001..Soft Start duration set to 95us. - * 0b010..Soft Start duration set to 60us. - * 0b011..Soft Start duration set to 48us. - * 0b100..Soft Start duration set to 38us. - * 0b101..Soft Start duration set to 30us. - * 0b110..Soft Start duration set to 24us. - * 0b111..Soft Start duration set to 17us. - */ -#define SPM_RFLDOSC_IOSSSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSSSEL_SHIFT)) & SPM_RFLDOSC_IOSSSEL_MASK) -#define SPM_RFLDOSC_SSDONE_MASK (0x1000000U) -#define SPM_RFLDOSC_SSDONE_SHIFT (24U) -#define SPM_RFLDOSC_SSDONE(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_SSDONE_SHIFT)) & SPM_RFLDOSC_SSDONE_MASK) -#define SPM_RFLDOSC_IOSPARE_OUT_MASK (0xC000000U) -#define SPM_RFLDOSC_IOSPARE_OUT_SHIFT (26U) -#define SPM_RFLDOSC_IOSPARE_OUT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSPARE_OUT_SHIFT)) & SPM_RFLDOSC_IOSPARE_OUT_MASK) -/*! @} */ - -/*! @name DCDCSC - DCDC Status Control Register */ -/*! @{ */ -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK) -#define SPM_DCDCSC_DCDC_SEL_CLK_MASK (0x4U) -#define SPM_DCDCSC_DCDC_SEL_CLK_SHIFT (2U) -#define SPM_DCDCSC_DCDC_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_SEL_CLK_SHIFT)) & SPM_DCDCSC_DCDC_SEL_CLK_MASK) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK (0x8U) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT (3U) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT)) & SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK) -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT (10U) -/*! DCDC_VBAT_DIV_CTRL - DCDC_VBAT_DIV_CTRL - * 0b00..OFF - * 0b01..VBAT - * 0b10..VBAT / 2 - * 0b11..VBAT / 4 - */ -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT)) & SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) -#define SPM_DCDCSC_DCDC_LESS_I_MASK (0x2000000U) -#define SPM_DCDCSC_DCDC_LESS_I_SHIFT (25U) -#define SPM_DCDCSC_DCDC_LESS_I(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_LESS_I_SHIFT)) & SPM_DCDCSC_DCDC_LESS_I_MASK) -#define SPM_DCDCSC_PWD_CMP_OFFSET_MASK (0x4000000U) -#define SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT (26U) -#define SPM_DCDCSC_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT)) & SPM_DCDCSC_PWD_CMP_OFFSET_MASK) -#define SPM_DCDCSC_CLKFLT_FAULT_MASK (0x40000000U) -#define SPM_DCDCSC_CLKFLT_FAULT_SHIFT (30U) -#define SPM_DCDCSC_CLKFLT_FAULT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_CLKFLT_FAULT_SHIFT)) & SPM_DCDCSC_CLKFLT_FAULT_MASK) -#define SPM_DCDCSC_DCDC_STS_DC_OK_MASK (0x80000000U) -#define SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT (31U) -#define SPM_DCDCSC_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT)) & SPM_DCDCSC_DCDC_STS_DC_OK_MASK) -/*! @} */ - -/*! @name DCDCC1 - DCDC Control Register 1 */ -/*! @{ */ -#define SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK (0x7FU) -#define SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT (0U) -#define SPM_DCDCC1_POSLIMIT_BUCK_IN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT)) & SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x4000000U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (26U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x8000000U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (27U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK) -/*! @} */ - -/*! @name DCDCC2 - DCDC Control Register 2 */ -/*! @{ */ -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK (0x2000U) -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U) -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK) -/*! @} */ - -/*! @name DCDCC3 - DCDC Control Register 3 */ -/*! @{ */ -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK (0x1U) -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT (0U) -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT)) & SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK) -#define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK (0x1CU) -#define SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT (2U) -#define SPM_DCDCC3_DCDC_VBAT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK (0xF0000U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT (16U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT (24U) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK (0x2000000U) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT (25U) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK (0x4000000U) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (26U) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK (0x8000000U) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT (27U) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK (0x40000000U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT (30U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x80000000U) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (31U) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK) -/*! @} */ - -/*! @name DCDCC4 - DCDC Control Register 4 */ -/*! @{ */ -#define SPM_DCDCC4_INTEGRATOR_VALUE_MASK (0x7FFFFU) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT (0U) -#define SPM_DCDCC4_INTEGRATOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_MASK) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK (0x80000U) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT (19U) -/*! INTEGRATOR_VALUE_SELECT - INTEGRATOR VALUE SELECT - * 0b0..Select the saved value in hardware - * 0b1..Select the integrator value in this register - */ -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK (0x100000U) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT (20U) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT)) & SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK) -/*! @} */ - -/*! @name DCDCC6 - DCDC Control Register 6 */ -/*! @{ */ -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK (0x1FU) -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT (0U) -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK (0xF00U) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT (8U) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK (0xF000000U) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT (24U) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT)) & SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) -/*! @} */ - -/*! @name LPREQPINCNTRL - LP Request Pin Control Register */ -/*! @{ */ -#define SPM_LPREQPINCNTRL_LPREQOE_MASK (0x1U) -#define SPM_LPREQPINCNTRL_LPREQOE_SHIFT (0U) -/*! LPREQOE - Low Power Request Output Enable Register - * 0b0..Low Power request output pin not enabled. - * 0b1..Low Power request output pin enabled. - */ -#define SPM_LPREQPINCNTRL_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_LPREQOE_SHIFT)) & SPM_LPREQPINCNTRL_LPREQOE_MASK) -#define SPM_LPREQPINCNTRL_POLARITY_MASK (0x2U) -#define SPM_LPREQPINCNTRL_POLARITY_SHIFT (1U) -/*! POLARITY - Low Power Request Output Pin Polarity Control Register - * 0b0..High true polarity. - * 0b1..Low true polarity. - */ -#define SPM_LPREQPINCNTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_POLARITY_SHIFT)) & SPM_LPREQPINCNTRL_POLARITY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPM_Register_Masks */ - - -/* SPM - Peripheral instance base addresses */ -/** Peripheral SPM base address */ -#define SPM_BASE (0x40028000u) -/** Peripheral SPM base pointer */ -#define SPM ((SPM_Type *)SPM_BASE) -/** Array initializer of SPM peripheral base addresses */ -#define SPM_BASE_ADDRS { SPM_BASE } -/** Array initializer of SPM peripheral base pointers */ -#define SPM_BASE_PTRS { SPM } -/** Interrupt vectors for the SPM peripheral type */ -#define SPM_IRQS { SPM_IRQn } - -/*! - * @} - */ /* end of group SPM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TPM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer - * @{ - */ - -/** TPM - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ - __IO uint32_t CNT; /**< Counter, offset: 0x14 */ - __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ - __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ - struct { /* offset: 0x20, array step: 0x8 */ - __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */ - __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */ - } CONTROLS[6]; - uint8_t RESERVED_1[20]; - __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ - uint8_t RESERVED_2[4]; - __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ - __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ - uint8_t RESERVED_4[4]; - __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ - __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ -} TPM_Type; - -/* ---------------------------------------------------------------------------- - -- TPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Register_Masks TPM Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define TPM_VERID_FEATURE_MASK (0xFFFFU) -#define TPM_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - * 0b0000000000000001..Standard feature set. - * 0b0000000000000011..Standard feature set with Filter and Combine registers implemented. - * 0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented. - */ -#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) -#define TPM_VERID_MINOR_MASK (0xFF0000U) -#define TPM_VERID_MINOR_SHIFT (16U) -#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) -#define TPM_VERID_MAJOR_MASK (0xFF000000U) -#define TPM_VERID_MAJOR_SHIFT (24U) -#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define TPM_PARAM_CHAN_MASK (0xFFU) -#define TPM_PARAM_CHAN_SHIFT (0U) -#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) -#define TPM_PARAM_TRIG_MASK (0xFF00U) -#define TPM_PARAM_TRIG_SHIFT (8U) -#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) -#define TPM_PARAM_WIDTH_MASK (0xFF0000U) -#define TPM_PARAM_WIDTH_SHIFT (16U) -#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) -/*! @} */ - -/*! @name GLOBAL - TPM Global Register */ -/*! @{ */ -#define TPM_GLOBAL_NOUPDATE_MASK (0x1U) -#define TPM_GLOBAL_NOUPDATE_SHIFT (0U) -/*! NOUPDATE - No Update - * 0b0..Internal double buffered registers update as normal. - * 0b1..Internal double buffered registers do not update. - */ -#define TPM_GLOBAL_NOUPDATE(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK) -#define TPM_GLOBAL_RST_MASK (0x2U) -#define TPM_GLOBAL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Module is not reset. - * 0b1..Module is reset. - */ -#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) -/*! @} */ - -/*! @name SC - Status and Control */ -/*! @{ */ -#define TPM_SC_PS_MASK (0x7U) -#define TPM_SC_PS_SHIFT (0U) -/*! PS - Prescale Factor Selection - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) -#define TPM_SC_CMOD_MASK (0x18U) -#define TPM_SC_CMOD_SHIFT (3U) -/*! CMOD - Clock Mode Selection - * 0b00..TPM counter is disabled - * 0b01..TPM counter increments on every TPM counter clock - * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock - * 0b11..TPM counter increments on rising edge of the selected external input trigger. - */ -#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) -#define TPM_SC_CPWMS_MASK (0x20U) -#define TPM_SC_CPWMS_SHIFT (5U) -/*! CPWMS - Center-Aligned PWM Select - * 0b0..TPM counter operates in up counting mode. - * 0b1..TPM counter operates in up-down counting mode. - */ -#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) -#define TPM_SC_TOIE_MASK (0x40U) -#define TPM_SC_TOIE_SHIFT (6U) -/*! TOIE - Timer Overflow Interrupt Enable - * 0b0..Disable TOF interrupts. Use software polling or DMA request. - * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. - */ -#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) -#define TPM_SC_TOF_MASK (0x80U) -#define TPM_SC_TOF_SHIFT (7U) -/*! TOF - Timer Overflow Flag - * 0b0..TPM counter has not overflowed. - * 0b1..TPM counter has overflowed. - */ -#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) -#define TPM_SC_DMA_MASK (0x100U) -#define TPM_SC_DMA_SHIFT (8U) -/*! DMA - DMA Enable - * 0b0..Disables DMA transfers. - * 0b1..Enables DMA transfers. - */ -#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) -/*! @} */ - -/*! @name CNT - Counter */ -/*! @{ */ -#define TPM_CNT_COUNT_MASK (0xFFFFU) -#define TPM_CNT_COUNT_SHIFT (0U) -#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) -/*! @} */ - -/*! @name MOD - Modulo */ -/*! @{ */ -#define TPM_MOD_MOD_MASK (0xFFFFU) -#define TPM_MOD_MOD_SHIFT (0U) -#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) -/*! @} */ - -/*! @name STATUS - Capture and Compare Status */ -/*! @{ */ -#define TPM_STATUS_CH0F_MASK (0x1U) -#define TPM_STATUS_CH0F_SHIFT (0U) -/*! CH0F - Channel 0 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) -#define TPM_STATUS_CH1F_MASK (0x2U) -#define TPM_STATUS_CH1F_SHIFT (1U) -/*! CH1F - Channel 1 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) -#define TPM_STATUS_CH2F_MASK (0x4U) -#define TPM_STATUS_CH2F_SHIFT (2U) -/*! CH2F - Channel 2 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) -#define TPM_STATUS_CH3F_MASK (0x8U) -#define TPM_STATUS_CH3F_SHIFT (3U) -/*! CH3F - Channel 3 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) -#define TPM_STATUS_CH4F_MASK (0x10U) -#define TPM_STATUS_CH4F_SHIFT (4U) -/*! CH4F - Channel 4 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) -#define TPM_STATUS_CH5F_MASK (0x20U) -#define TPM_STATUS_CH5F_SHIFT (5U) -/*! CH5F - Channel 5 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) -#define TPM_STATUS_TOF_MASK (0x100U) -#define TPM_STATUS_TOF_SHIFT (8U) -/*! TOF - Timer Overflow Flag - * 0b0..TPM counter has not overflowed. - * 0b1..TPM counter has overflowed. - */ -#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) -/*! @} */ - -/*! @name CnSC - Channel (n) Status and Control */ -/*! @{ */ -#define TPM_CnSC_DMA_MASK (0x1U) -#define TPM_CnSC_DMA_SHIFT (0U) -/*! DMA - DMA Enable - * 0b0..Disable DMA transfers. - * 0b1..Enable DMA transfers. - */ -#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) -#define TPM_CnSC_ELSA_MASK (0x4U) -#define TPM_CnSC_ELSA_SHIFT (2U) -#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) -#define TPM_CnSC_ELSB_MASK (0x8U) -#define TPM_CnSC_ELSB_SHIFT (3U) -#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) -#define TPM_CnSC_MSA_MASK (0x10U) -#define TPM_CnSC_MSA_SHIFT (4U) -#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) -#define TPM_CnSC_MSB_MASK (0x20U) -#define TPM_CnSC_MSB_SHIFT (5U) -#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) -#define TPM_CnSC_CHIE_MASK (0x40U) -#define TPM_CnSC_CHIE_SHIFT (6U) -/*! CHIE - Channel Interrupt Enable - * 0b0..Disable channel interrupts. - * 0b1..Enable channel interrupts. - */ -#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) -#define TPM_CnSC_CHF_MASK (0x80U) -#define TPM_CnSC_CHF_SHIFT (7U) -/*! CHF - Channel Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) -/*! @} */ - -/* The count of TPM_CnSC */ -#define TPM_CnSC_COUNT (6U) - -/*! @name CnV - Channel (n) Value */ -/*! @{ */ -#define TPM_CnV_VAL_MASK (0xFFFFU) -#define TPM_CnV_VAL_SHIFT (0U) -#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) -/*! @} */ - -/* The count of TPM_CnV */ -#define TPM_CnV_COUNT (6U) - -/*! @name COMBINE - Combine Channel Register */ -/*! @{ */ -#define TPM_COMBINE_COMBINE0_MASK (0x1U) -#define TPM_COMBINE_COMBINE0_SHIFT (0U) -/*! COMBINE0 - Combine Channels 0 and 1 - * 0b0..Channels 0 and 1 are independent. - * 0b1..Channels 0 and 1 are combined. - */ -#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) -#define TPM_COMBINE_COMSWAP0_MASK (0x2U) -#define TPM_COMBINE_COMSWAP0_SHIFT (1U) -/*! COMSWAP0 - Combine Channel 0 and 1 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) -#define TPM_COMBINE_COMBINE1_MASK (0x100U) -#define TPM_COMBINE_COMBINE1_SHIFT (8U) -/*! COMBINE1 - Combine Channels 2 and 3 - * 0b0..Channels 2 and 3 are independent. - * 0b1..Channels 2 and 3 are combined. - */ -#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) -#define TPM_COMBINE_COMSWAP1_MASK (0x200U) -#define TPM_COMBINE_COMSWAP1_SHIFT (9U) -/*! COMSWAP1 - Combine Channels 2 and 3 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) -#define TPM_COMBINE_COMBINE2_MASK (0x10000U) -#define TPM_COMBINE_COMBINE2_SHIFT (16U) -/*! COMBINE2 - Combine Channels 4 and 5 - * 0b0..Channels 4 and 5 are independent. - * 0b1..Channels 4 and 5 are combined. - */ -#define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK) -#define TPM_COMBINE_COMSWAP2_MASK (0x20000U) -#define TPM_COMBINE_COMSWAP2_SHIFT (17U) -/*! COMSWAP2 - Combine Channels 4 and 5 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK) -/*! @} */ - -/*! @name TRIG - Channel Trigger */ -/*! @{ */ -#define TPM_TRIG_TRIG0_MASK (0x1U) -#define TPM_TRIG_TRIG0_SHIFT (0U) -/*! TRIG0 - Channel 0 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 0. - */ -#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) -#define TPM_TRIG_TRIG1_MASK (0x2U) -#define TPM_TRIG_TRIG1_SHIFT (1U) -/*! TRIG1 - Channel 1 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 1. - */ -#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) -#define TPM_TRIG_TRIG2_MASK (0x4U) -#define TPM_TRIG_TRIG2_SHIFT (2U) -/*! TRIG2 - Channel 2 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 2. - */ -#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) -#define TPM_TRIG_TRIG3_MASK (0x8U) -#define TPM_TRIG_TRIG3_SHIFT (3U) -/*! TRIG3 - Channel 3 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 3. - */ -#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) -#define TPM_TRIG_TRIG4_MASK (0x10U) -#define TPM_TRIG_TRIG4_SHIFT (4U) -/*! TRIG4 - Channel 4 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 4. - */ -#define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK) -#define TPM_TRIG_TRIG5_MASK (0x20U) -#define TPM_TRIG_TRIG5_SHIFT (5U) -/*! TRIG5 - Channel 5 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 5. - */ -#define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK) -/*! @} */ - -/*! @name POL - Channel Polarity */ -/*! @{ */ -#define TPM_POL_POL0_MASK (0x1U) -#define TPM_POL_POL0_SHIFT (0U) -/*! POL0 - Channel 0 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) -#define TPM_POL_POL1_MASK (0x2U) -#define TPM_POL_POL1_SHIFT (1U) -/*! POL1 - Channel 1 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) -#define TPM_POL_POL2_MASK (0x4U) -#define TPM_POL_POL2_SHIFT (2U) -/*! POL2 - Channel 2 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) -#define TPM_POL_POL3_MASK (0x8U) -#define TPM_POL_POL3_SHIFT (3U) -/*! POL3 - Channel 3 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) -#define TPM_POL_POL4_MASK (0x10U) -#define TPM_POL_POL4_SHIFT (4U) -/*! POL4 - Channel 4 Polarity - * 0b0..The channel polarity is active high - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) -#define TPM_POL_POL5_MASK (0x20U) -#define TPM_POL_POL5_SHIFT (5U) -/*! POL5 - Channel 5 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) -/*! @} */ - -/*! @name FILTER - Filter Control */ -/*! @{ */ -#define TPM_FILTER_CH0FVAL_MASK (0xFU) -#define TPM_FILTER_CH0FVAL_SHIFT (0U) -#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) -#define TPM_FILTER_CH1FVAL_MASK (0xF0U) -#define TPM_FILTER_CH1FVAL_SHIFT (4U) -#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) -#define TPM_FILTER_CH2FVAL_MASK (0xF00U) -#define TPM_FILTER_CH2FVAL_SHIFT (8U) -#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) -#define TPM_FILTER_CH3FVAL_MASK (0xF000U) -#define TPM_FILTER_CH3FVAL_SHIFT (12U) -#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) -#define TPM_FILTER_CH4FVAL_MASK (0xF0000U) -#define TPM_FILTER_CH4FVAL_SHIFT (16U) -#define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK) -#define TPM_FILTER_CH5FVAL_MASK (0xF00000U) -#define TPM_FILTER_CH5FVAL_SHIFT (20U) -#define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK) -/*! @} */ - -/*! @name QDCTRL - Quadrature Decoder Control and Status */ -/*! @{ */ -#define TPM_QDCTRL_QUADEN_MASK (0x1U) -#define TPM_QDCTRL_QUADEN_SHIFT (0U) -/*! QUADEN - QUADEN - * 0b0..Quadrature decoder mode is disabled. - * 0b1..Quadrature decoder mode is enabled. - */ -#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) -#define TPM_QDCTRL_TOFDIR_MASK (0x2U) -#define TPM_QDCTRL_TOFDIR_SHIFT (1U) -/*! TOFDIR - TOFDIR - * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). - * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). - */ -#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) -#define TPM_QDCTRL_QUADIR_MASK (0x4U) -#define TPM_QDCTRL_QUADIR_SHIFT (2U) -/*! QUADIR - Counter Direction in Quadrature Decode Mode - * 0b0..Counter direction is decreasing (counter decrement). - * 0b1..Counter direction is increasing (counter increment). - */ -#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) -#define TPM_QDCTRL_QUADMODE_MASK (0x8U) -#define TPM_QDCTRL_QUADMODE_SHIFT (3U) -/*! QUADMODE - Quadrature Decoder Mode - * 0b0..Phase encoding mode. - * 0b1..Count and direction encoding mode. - */ -#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) -/*! @} */ - -/*! @name CONF - Configuration */ -/*! @{ */ -#define TPM_CONF_DOZEEN_MASK (0x20U) -#define TPM_CONF_DOZEEN_SHIFT (5U) -/*! DOZEEN - Doze Enable - * 0b0..Internal TPM counter continues in Doze mode. - * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. - */ -#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) -#define TPM_CONF_DBGMODE_MASK (0xC0U) -#define TPM_CONF_DBGMODE_SHIFT (6U) -/*! DBGMODE - Debug Mode - * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. - * 0b11..TPM counter continues in debug mode. - */ -#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) -#define TPM_CONF_GTBSYNC_MASK (0x100U) -#define TPM_CONF_GTBSYNC_SHIFT (8U) -/*! GTBSYNC - Global Time Base Synchronization - * 0b0..Global timebase synchronization disabled. - * 0b1..Global timebase synchronization enabled. - */ -#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) -#define TPM_CONF_GTBEEN_MASK (0x200U) -#define TPM_CONF_GTBEEN_SHIFT (9U) -/*! GTBEEN - Global time base enable - * 0b0..All channels use the internally generated TPM counter as their timebase - * 0b1..All channels use an externally generated global timebase as their timebase - */ -#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) -#define TPM_CONF_CSOT_MASK (0x10000U) -#define TPM_CONF_CSOT_SHIFT (16U) -/*! CSOT - Counter Start on Trigger - * 0b0..TPM counter starts to increment immediately, once it is enabled. - * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. - */ -#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) -#define TPM_CONF_CSOO_MASK (0x20000U) -#define TPM_CONF_CSOO_SHIFT (17U) -/*! CSOO - Counter Stop On Overflow - * 0b0..TPM counter continues incrementing or decrementing after overflow - * 0b1..TPM counter stops incrementing or decrementing after overflow. - */ -#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) -#define TPM_CONF_CROT_MASK (0x40000U) -#define TPM_CONF_CROT_SHIFT (18U) -/*! CROT - Counter Reload On Trigger - * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger - * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger - */ -#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) -#define TPM_CONF_CPOT_MASK (0x80000U) -#define TPM_CONF_CPOT_SHIFT (19U) -#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) -#define TPM_CONF_TRGPOL_MASK (0x400000U) -#define TPM_CONF_TRGPOL_SHIFT (22U) -/*! TRGPOL - Trigger Polarity - * 0b0..Trigger is active high. - * 0b1..Trigger is active low. - */ -#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) -#define TPM_CONF_TRGSRC_MASK (0x800000U) -#define TPM_CONF_TRGSRC_SHIFT (23U) -/*! TRGSRC - Trigger Source - * 0b0..Trigger source selected by TRGSEL is external. - * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture). - */ -#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) -#define TPM_CONF_TRGSEL_MASK (0x3000000U) -#define TPM_CONF_TRGSEL_SHIFT (24U) -/*! TRGSEL - Trigger Select - * 0b01..Channel 0 pin input capture - * 0b10..Channel 1 pin input capture - * 0b11..Channel 0 or Channel 1 pin input capture - */ -#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TPM_Register_Masks */ - - -/* TPM - Peripheral instance base addresses */ -/** Peripheral TPM0 base address */ -#define TPM0_BASE (0x40035000u) -/** Peripheral TPM0 base pointer */ -#define TPM0 ((TPM_Type *)TPM0_BASE) -/** Peripheral TPM1 base address */ -#define TPM1_BASE (0x40036000u) -/** Peripheral TPM1 base pointer */ -#define TPM1 ((TPM_Type *)TPM1_BASE) -/** Peripheral TPM2 base address */ -#define TPM2_BASE (0x40037000u) -/** Peripheral TPM2 base pointer */ -#define TPM2 ((TPM_Type *)TPM2_BASE) -/** Peripheral TPM3 base address */ -#define TPM3_BASE (0x4102D000u) -/** Peripheral TPM3 base pointer */ -#define TPM3 ((TPM_Type *)TPM3_BASE) -/** Array initializer of TPM peripheral base addresses */ -#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE } -/** Array initializer of TPM peripheral base pointers */ -#define TPM_BASE_PTRS { TPM0, TPM1, TPM2, TPM3 } -/** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn } - -/*! - * @} - */ /* end of group TPM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRGMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer - * @{ - */ - -/** TRGMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t TRGCFG[25]; /**< TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register, array offset: 0x0, array step: 0x4 */ -} TRGMUX_Type; - -/* ---------------------------------------------------------------------------- - -- TRGMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks - * @{ - */ - -/*! @name TRGCFG - TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register */ -/*! @{ */ -#define TRGMUX_TRGCFG_SEL0_MASK (0x3FU) -#define TRGMUX_TRGCFG_SEL0_SHIFT (0U) -#define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK) -#define TRGMUX_TRGCFG_SEL1_MASK (0x3F00U) -#define TRGMUX_TRGCFG_SEL1_SHIFT (8U) -#define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK) -#define TRGMUX_TRGCFG_SEL2_MASK (0x3F0000U) -#define TRGMUX_TRGCFG_SEL2_SHIFT (16U) -#define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK) -#define TRGMUX_TRGCFG_SEL3_MASK (0x3F000000U) -#define TRGMUX_TRGCFG_SEL3_SHIFT (24U) -#define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK) -#define TRGMUX_TRGCFG_LK_MASK (0x80000000U) -#define TRGMUX_TRGCFG_LK_SHIFT (31U) -/*! LK - TRGMUX register lock. - * 0b0..Register can be written. - * 0b1..Register cannot be written until the next system Reset. - */ -#define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK) -/*! @} */ - -/* The count of TRGMUX_TRGCFG */ -#define TRGMUX_TRGCFG_COUNT (25U) - - -/*! - * @} - */ /* end of group TRGMUX_Register_Masks */ - - -/* TRGMUX - Peripheral instance base addresses */ -/** Peripheral TRGMUX0 base address */ -#define TRGMUX0_BASE (0x40029000u) -/** Peripheral TRGMUX0 base pointer */ -#define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE) -/** Peripheral TRGMUX1 base address */ -#define TRGMUX1_BASE (0x41025000u) -/** Peripheral TRGMUX1 base pointer */ -#define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE) -/** Array initializer of TRGMUX peripheral base addresses */ -#define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE } -/** Array initializer of TRGMUX peripheral base pointers */ -#define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 } - -/*! - * @} - */ /* end of group TRGMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer - * @{ - */ - -/** TRNG - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ - __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ - }; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - union { /* offset: 0x14 */ - __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ - __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ - }; - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - union { /* offset: 0x30 */ - __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ - __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ - }; - union { /* offset: 0x34 */ - __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ - __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ - }; - union { /* offset: 0x38 */ - __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ - __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ - }; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ - __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ - __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ - __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ - __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ - __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ - __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ - __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ - uint8_t RESERVED_0[64]; - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; - -/* ---------------------------------------------------------------------------- - -- TRNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks - * @{ - */ - -/*! @name MCTL - Miscellaneous Control Register */ -/*! @{ */ -#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) -#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) -/*! SAMP_MODE - * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker - * 0b01..use raw data into both Entropy shifter and Statistical Checker - * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker - * 0b11..undefined/reserved. - */ -#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -/*! OSC_DIV - * 0b00..use ring oscillator with no divide - * 0b01..use ring oscillator divided-by-2 - * 0b10..use ring oscillator divided-by-4 - * 0b11..use ring oscillator divided-by-8 - */ -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) -#define TRNG_MCTL_UNUSED4_MASK (0x10U) -#define TRNG_MCTL_UNUSED4_SHIFT (4U) -#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) -#define TRNG_MCTL_TRNG_ACC_MASK (0x20U) -#define TRNG_MCTL_TRNG_ACC_SHIFT (5U) -#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) -#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) -#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) -#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) -#define TRNG_MCTL_TST_OUT_MASK (0x800U) -#define TRNG_MCTL_TST_OUT_SHIFT (11U) -#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) -/*! @} */ - -/*! @name SCMISC - Statistical Check Miscellaneous Register */ -/*! @{ */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) -/*! @} */ - -/*! @name PKRRNG - Poker Range Register */ -/*! @{ */ -#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) -#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) -#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) -/*! @} */ - -/*! @name PKRMAX - Poker Maximum Limit Register */ -/*! @{ */ -#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) -#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) -#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) -/*! @} */ - -/*! @name PKRSQ - Poker Square Calculation Result Register */ -/*! @{ */ -#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) -#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) -#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) -/*! @} */ - -/*! @name SDCTL - Seed Control Register */ -/*! @{ */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) -/*! @} */ - -/*! @name SBLIM - Sparse Bit Limit Register */ -/*! @{ */ -#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) -#define TRNG_SBLIM_SB_LIM_SHIFT (0U) -#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) -/*! @} */ - -/*! @name TOTSAM - Total Samples Register */ -/*! @{ */ -#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) -#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) -#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) -/*! @} */ - -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ -/*! @{ */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) -/*! @} */ - -/*! @name FRQCNT - Frequency Count Register */ -/*! @{ */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) -/*! @} */ - -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ -/*! @{ */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) -/*! @} */ - -/*! @name SCMC - Statistical Check Monobit Count Register */ -/*! @{ */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) -/*! @} */ - -/*! @name SCML - Statistical Check Monobit Limit Register */ -/*! @{ */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) -/*! @} */ - -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ -/*! @{ */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) -/*! @} */ - -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ -/*! @{ */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) -/*! @} */ - -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ -/*! @{ */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) -/*! @} */ - -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -/*! @{ */ -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) -/*! @} */ - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -/*! @{ */ -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) -/*! @} */ - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -/*! @{ */ -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) -/*! @} */ - -/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ -/*! @{ */ -#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) -#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) -#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) -#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) -#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) -#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) -/*! @} */ - -/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ -/*! @{ */ -#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) -#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) -#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) -#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) -#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) -#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) -/*! @} */ - -/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ -/*! @{ */ -#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) -#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) -#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) -#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) -#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) -/*! @} */ - -/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ -/*! @{ */ -#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) -#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) -#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) -#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) -#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) -#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) -/*! @} */ - -/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ -/*! @{ */ -#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) -#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) -#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) -#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) -#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) -/*! @} */ - -/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ -/*! @{ */ -#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) -#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) -#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) -#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) -#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) -#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) -#define TRNG_STATUS_TF4BR0_MASK (0x40U) -#define TRNG_STATUS_TF4BR0_SHIFT (6U) -#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) -#define TRNG_STATUS_TF4BR1_MASK (0x80U) -#define TRNG_STATUS_TF4BR1_SHIFT (7U) -#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) -#define TRNG_STATUS_TF5BR0_MASK (0x100U) -#define TRNG_STATUS_TF5BR0_SHIFT (8U) -#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) -#define TRNG_STATUS_TF5BR1_MASK (0x200U) -#define TRNG_STATUS_TF5BR1_SHIFT (9U) -#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) -#define TRNG_STATUS_TF6PBR0_MASK (0x400U) -#define TRNG_STATUS_TF6PBR0_SHIFT (10U) -#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) -#define TRNG_STATUS_TF6PBR1_MASK (0x800U) -#define TRNG_STATUS_TF6PBR1_SHIFT (11U) -#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) -#define TRNG_STATUS_TFSB_MASK (0x1000U) -#define TRNG_STATUS_TFSB_SHIFT (12U) -#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) -#define TRNG_STATUS_TFP_MASK (0x4000U) -#define TRNG_STATUS_TFP_SHIFT (14U) -#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) -/*! @} */ - -/*! @name ENT - Entropy Read Register */ -/*! @{ */ -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) -/*! @} */ - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (16U) - -/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ -/*! @{ */ -#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) -#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) -#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) -#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) -/*! @} */ - -/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ -/*! @{ */ -#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) -#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) -#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) -#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) -/*! @} */ - -/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ -/*! @{ */ -#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) -#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) -#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) -#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) -/*! @} */ - -/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ -/*! @{ */ -#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) -#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) -#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) -#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) -/*! @} */ - -/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ -/*! @{ */ -#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) -#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) -#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) -#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) -/*! @} */ - -/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ -/*! @{ */ -#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) -#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) -#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) -#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) -/*! @} */ - -/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ -/*! @{ */ -#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) -#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) -#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) -#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) -/*! @} */ - -/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ -/*! @{ */ -#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) -#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) -#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) -#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) -/*! @} */ - -/*! @name SEC_CFG - Security Configuration Register */ -/*! @{ */ -#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) -#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) -#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -/*! NO_PRGM - * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. - * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. - */ -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) -#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) -#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) -/*! @} */ - -/*! @name INT_CTRL - Interrupt Control Register */ -/*! @{ */ -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Corresponding bit of INT_STATUS register cleared. - * 0b1..Corresponding bit of INT_STATUS register active. - */ -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) -#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) -#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) -/*! @} */ - -/*! @name INT_MASK - Mask Register */ -/*! @{ */ -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Corresponding interrupt of INT_STATUS is masked. - * 0b1..Corresponding bit of INT_STATUS is active. - */ -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..no error - * 0b1..error detected. - */ -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Busy generation entropy. Any value read is invalid. - * 0b1..TRNG can be stopped and entropy is valid if read. - */ -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..No hardware nor self test frequency errors. - * 0b1..The frequency counter has detected a failure. - */ -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name VID1 - Version ID Register (MS) */ -/*! @{ */ -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -/*! MIN_REV - * 0b00000000..Minor revision number for TRNG. - */ -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -/*! MAJ_REV - * 0b00000001..Major revision number for TRNG. - */ -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -/*! IP_ID - * 0b0000000000110000..ID for TRNG. - */ -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name VID2 - Version ID Register (LS) */ -/*! @{ */ -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -/*! CONFIG_OPT - * 0b00000000..TRNG_CONFIG_OPT for TRNG. - */ -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -/*! ECO_REV - * 0b00000000..TRNG_ECO_REV for TRNG. - */ -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -/*! INTG_OPT - * 0b00000000..INTG_OPT for TRNG. - */ -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -/*! ERA - * 0b00000000..COMPILE_OPT for TRNG. - */ -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TRNG_Register_Masks */ - - -/* TRNG - Peripheral instance base addresses */ -/** Peripheral TRNG base address */ -#define TRNG_BASE (0x41029000u) -/** Peripheral TRNG base pointer */ -#define TRNG ((TRNG_Type *)TRNG_BASE) -/** Array initializer of TRNG peripheral base addresses */ -#define TRNG_BASE_ADDRS { TRNG_BASE } -/** Array initializer of TRNG peripheral base pointers */ -#define TRNG_BASE_PTRS { TRNG } -/** Interrupt vectors for the TRNG peripheral type */ -#define TRNG_IRQS { TRNG_IRQn } -/** Backward compatibility macros */ -#define TRNG0 TRNG - - -/*! - * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TSTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer - * @{ - */ - -/** TSTMR - Register Layout Typedef */ -typedef struct { - __I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */ - __I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */ -} TSTMR_Type; - -/* ---------------------------------------------------------------------------- - -- TSTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSTMR_Register_Masks TSTMR Register Masks - * @{ - */ - -/*! @name L - Time Stamp Timer Register Low */ -/*! @{ */ -#define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) -#define TSTMR_L_VALUE_SHIFT (0U) -#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) -/*! @} */ - -/*! @name H - Time Stamp Timer Register High */ -/*! @{ */ -#define TSTMR_H_VALUE_MASK (0xFFFFFFU) -#define TSTMR_H_VALUE_SHIFT (0U) -#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TSTMR_Register_Masks */ - - -/* TSTMR - Peripheral instance base addresses */ -/** Peripheral TSTMRA base address */ -#define TSTMRA_BASE (0x40034000u) -/** Peripheral TSTMRA base pointer */ -#define TSTMRA ((TSTMR_Type *)TSTMRA_BASE) -/** Array initializer of TSTMR peripheral base addresses */ -#define TSTMR_BASE_ADDRS { TSTMRA_BASE } -/** Array initializer of TSTMR peripheral base pointers */ -#define TSTMR_BASE_PTRS { TSTMRA } - -/*! - * @} - */ /* end of group TSTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ - uint8_t RESERVED_1[3]; - __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ - uint8_t RESERVED_2[3]; - __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ - uint8_t RESERVED_3[15]; - __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ - uint8_t RESERVED_4[99]; - __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ - uint8_t RESERVED_5[3]; - __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ - uint8_t RESERVED_6[3]; - __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ - uint8_t RESERVED_7[3]; - __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ - uint8_t RESERVED_8[3]; - __I uint8_t STAT; /**< Status register, offset: 0x90 */ - uint8_t RESERVED_9[3]; - __IO uint8_t CTL; /**< Control register, offset: 0x94 */ - uint8_t RESERVED_10[3]; - __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ - uint8_t RESERVED_11[3]; - __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ - uint8_t RESERVED_12[3]; - __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ - uint8_t RESERVED_13[3]; - __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ - uint8_t RESERVED_14[11]; - __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ - uint8_t RESERVED_15[3]; - __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ - uint8_t RESERVED_16[11]; - struct { /* offset: 0xC0, array step: 0x4 */ - __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_0[3]; - } ENDPOINT[16]; - __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ - uint8_t RESERVED_17[3]; - __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ - uint8_t RESERVED_18[3]; - __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ - uint8_t RESERVED_19[3]; - __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ - uint8_t RESERVED_20[23]; - __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */ - uint8_t RESERVED_21[3]; - __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */ - uint8_t RESERVED_22[3]; - __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */ - uint8_t RESERVED_23[3]; - __IO uint8_t STALL_IL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */ - uint8_t RESERVED_24[3]; - __IO uint8_t STALL_IH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */ - uint8_t RESERVED_25[3]; - __IO uint8_t STALL_OL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */ - uint8_t RESERVED_26[3]; - __IO uint8_t STALL_OH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */ - uint8_t RESERVED_27[3]; - __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ - uint8_t RESERVED_28[3]; - __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48MFIRC oscillator enable register, offset: 0x144 */ - uint8_t RESERVED_29[15]; - __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ - uint8_t RESERVED_30[7]; - __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name PERID - Peripheral ID register */ -/*! @{ */ -#define USB_PERID_ID_MASK (0x3FU) -#define USB_PERID_ID_SHIFT (0U) -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) -/*! @} */ - -/*! @name IDCOMP - Peripheral ID Complement register */ -/*! @{ */ -#define USB_IDCOMP_NID_MASK (0x3FU) -#define USB_IDCOMP_NID_SHIFT (0U) -#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) -/*! @} */ - -/*! @name REV - Peripheral Revision register */ -/*! @{ */ -#define USB_REV_REV_MASK (0xFFU) -#define USB_REV_REV_SHIFT (0U) -#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) -/*! @} */ - -/*! @name ADDINFO - Peripheral Additional Info register */ -/*! @{ */ -#define USB_ADDINFO_IEHOST_MASK (0x1U) -#define USB_ADDINFO_IEHOST_SHIFT (0U) -#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) -/*! @} */ - -/*! @name OTGCTL - OTG Control register */ -/*! @{ */ -#define USB_OTGCTL_DPHIGH_MASK (0x80U) -#define USB_OTGCTL_DPHIGH_SHIFT (7U) -/*! DPHIGH - D+ Data Line pullup resistor enable - * 0b0..D+ pullup resistor is not enabled - * 0b1..D+ pullup resistor is enabled - */ -#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) -/*! @} */ - -/*! @name ISTAT - Interrupt Status register */ -/*! @{ */ -#define USB_ISTAT_USBRST_MASK (0x1U) -#define USB_ISTAT_USBRST_SHIFT (0U) -#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) -#define USB_ISTAT_ERROR_MASK (0x2U) -#define USB_ISTAT_ERROR_SHIFT (1U) -#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) -#define USB_ISTAT_SOFTOK_MASK (0x4U) -#define USB_ISTAT_SOFTOK_SHIFT (2U) -#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) -#define USB_ISTAT_TOKDNE_MASK (0x8U) -#define USB_ISTAT_TOKDNE_SHIFT (3U) -#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) -#define USB_ISTAT_SLEEP_MASK (0x10U) -#define USB_ISTAT_SLEEP_SHIFT (4U) -#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) -#define USB_ISTAT_RESUME_MASK (0x20U) -#define USB_ISTAT_RESUME_SHIFT (5U) -#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) -#define USB_ISTAT_STALL_MASK (0x80U) -#define USB_ISTAT_STALL_SHIFT (7U) -#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) -/*! @} */ - -/*! @name INTEN - Interrupt Enable register */ -/*! @{ */ -#define USB_INTEN_USBRSTEN_MASK (0x1U) -#define USB_INTEN_USBRSTEN_SHIFT (0U) -/*! USBRSTEN - USBRST Interrupt Enable - * 0b0..Disables the USBRST interrupt. - * 0b1..Enables the USBRST interrupt. - */ -#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) -#define USB_INTEN_ERROREN_MASK (0x2U) -#define USB_INTEN_ERROREN_SHIFT (1U) -/*! ERROREN - ERROR Interrupt Enable - * 0b0..Disables the ERROR interrupt. - * 0b1..Enables the ERROR interrupt. - */ -#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) -#define USB_INTEN_SOFTOKEN_MASK (0x4U) -#define USB_INTEN_SOFTOKEN_SHIFT (2U) -/*! SOFTOKEN - SOFTOK Interrupt Enable - * 0b0..Disbles the SOFTOK interrupt. - * 0b1..Enables the SOFTOK interrupt. - */ -#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) -#define USB_INTEN_TOKDNEEN_MASK (0x8U) -#define USB_INTEN_TOKDNEEN_SHIFT (3U) -/*! TOKDNEEN - TOKDNE Interrupt Enable - * 0b0..Disables the TOKDNE interrupt. - * 0b1..Enables the TOKDNE interrupt. - */ -#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) -#define USB_INTEN_SLEEPEN_MASK (0x10U) -#define USB_INTEN_SLEEPEN_SHIFT (4U) -/*! SLEEPEN - SLEEP Interrupt Enable - * 0b0..Disables the SLEEP interrupt. - * 0b1..Enables the SLEEP interrupt. - */ -#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) -#define USB_INTEN_RESUMEEN_MASK (0x20U) -#define USB_INTEN_RESUMEEN_SHIFT (5U) -/*! RESUMEEN - RESUME Interrupt Enable - * 0b0..Disables the RESUME interrupt. - * 0b1..Enables the RESUME interrupt. - */ -#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) -#define USB_INTEN_STALLEN_MASK (0x80U) -#define USB_INTEN_STALLEN_SHIFT (7U) -/*! STALLEN - STALL Interrupt Enable - * 0b0..Diasbles the STALL interrupt. - * 0b1..Enables the STALL interrupt. - */ -#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) -/*! @} */ - -/*! @name ERRSTAT - Error Interrupt Status register */ -/*! @{ */ -#define USB_ERRSTAT_PIDERR_MASK (0x1U) -#define USB_ERRSTAT_PIDERR_SHIFT (0U) -#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) -#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) -#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) -#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) -#define USB_ERRSTAT_CRC16_MASK (0x4U) -#define USB_ERRSTAT_CRC16_SHIFT (2U) -#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) -#define USB_ERRSTAT_DFN8_MASK (0x8U) -#define USB_ERRSTAT_DFN8_SHIFT (3U) -#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) -#define USB_ERRSTAT_BTOERR_MASK (0x10U) -#define USB_ERRSTAT_BTOERR_SHIFT (4U) -#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) -#define USB_ERRSTAT_DMAERR_MASK (0x20U) -#define USB_ERRSTAT_DMAERR_SHIFT (5U) -#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) -#define USB_ERRSTAT_OWNERR_MASK (0x40U) -#define USB_ERRSTAT_OWNERR_SHIFT (6U) -#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) -#define USB_ERRSTAT_BTSERR_MASK (0x80U) -#define USB_ERRSTAT_BTSERR_SHIFT (7U) -#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) -/*! @} */ - -/*! @name ERREN - Error Interrupt Enable register */ -/*! @{ */ -#define USB_ERREN_PIDERREN_MASK (0x1U) -#define USB_ERREN_PIDERREN_SHIFT (0U) -/*! PIDERREN - PIDERR Interrupt Enable - * 0b0..Disables the PIDERR interrupt. - * 0b1..Enters the PIDERR interrupt. - */ -#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) -#define USB_ERREN_CRC5EOFEN_MASK (0x2U) -#define USB_ERREN_CRC5EOFEN_SHIFT (1U) -/*! CRC5EOFEN - CRC5/EOF Interrupt Enable - * 0b0..Disables the CRC5/EOF interrupt. - * 0b1..Enables the CRC5/EOF interrupt. - */ -#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) -#define USB_ERREN_CRC16EN_MASK (0x4U) -#define USB_ERREN_CRC16EN_SHIFT (2U) -/*! CRC16EN - CRC16 Interrupt Enable - * 0b0..Disables the CRC16 interrupt. - * 0b1..Enables the CRC16 interrupt. - */ -#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) -#define USB_ERREN_DFN8EN_MASK (0x8U) -#define USB_ERREN_DFN8EN_SHIFT (3U) -/*! DFN8EN - DFN8 Interrupt Enable - * 0b0..Disables the DFN8 interrupt. - * 0b1..Enables the DFN8 interrupt. - */ -#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) -#define USB_ERREN_BTOERREN_MASK (0x10U) -#define USB_ERREN_BTOERREN_SHIFT (4U) -/*! BTOERREN - BTOERR Interrupt Enable - * 0b0..Disables the BTOERR interrupt. - * 0b1..Enables the BTOERR interrupt. - */ -#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) -#define USB_ERREN_DMAERREN_MASK (0x20U) -#define USB_ERREN_DMAERREN_SHIFT (5U) -/*! DMAERREN - DMAERR Interrupt Enable - * 0b0..Disables the DMAERR interrupt. - * 0b1..Enables the DMAERR interrupt. - */ -#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) -#define USB_ERREN_OWNERREN_MASK (0x40U) -#define USB_ERREN_OWNERREN_SHIFT (6U) -/*! OWNERREN - OWNERR Interrupt Enable - * 0b0..Disables the OWNERR interrupt. - * 0b1..Enables the OWNERR interrupt. - */ -#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) -#define USB_ERREN_BTSERREN_MASK (0x80U) -#define USB_ERREN_BTSERREN_SHIFT (7U) -/*! BTSERREN - BTSERR Interrupt Enable - * 0b0..Disables the BTSERR interrupt. - * 0b1..Enables the BTSERR interrupt. - */ -#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) -/*! @} */ - -/*! @name STAT - Status register */ -/*! @{ */ -#define USB_STAT_ODD_MASK (0x4U) -#define USB_STAT_ODD_SHIFT (2U) -#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) -#define USB_STAT_TX_MASK (0x8U) -#define USB_STAT_TX_SHIFT (3U) -/*! TX - Transmit Indicator - * 0b0..The most recent transaction was a receive operation. - * 0b1..The most recent transaction was a transmit operation. - */ -#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) -#define USB_STAT_ENDP_MASK (0xF0U) -#define USB_STAT_ENDP_SHIFT (4U) -#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) -/*! @} */ - -/*! @name CTL - Control register */ -/*! @{ */ -#define USB_CTL_USBENSOFEN_MASK (0x1U) -#define USB_CTL_USBENSOFEN_SHIFT (0U) -/*! USBENSOFEN - USB Enable - * 0b0..Disables the USB Module. - * 0b1..Enables the USB Module. - */ -#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) -#define USB_CTL_ODDRST_MASK (0x2U) -#define USB_CTL_ODDRST_SHIFT (1U) -#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) -#define USB_CTL_RESUME_MASK (0x4U) -#define USB_CTL_RESUME_SHIFT (2U) -#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) -#define USB_CTL_HOSTMODEEN_MASK (0x8U) -#define USB_CTL_HOSTMODEEN_SHIFT (3U) -/*! HOSTMODEEN - Host mode enable - * 0b0..USB Module operates in Device mode. - * 0b1..USB Module operates in Host mode. In Host mode, the USB module performs USB transactions under the programmed control of the host processor. - */ -#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) -#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) -#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) -#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) -#define USB_CTL_SE0_MASK (0x40U) -#define USB_CTL_SE0_SHIFT (6U) -#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) -#define USB_CTL_JSTATE_MASK (0x80U) -#define USB_CTL_JSTATE_SHIFT (7U) -#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) -/*! @} */ - -/*! @name ADDR - Address register */ -/*! @{ */ -#define USB_ADDR_ADDR_MASK (0x7FU) -#define USB_ADDR_ADDR_SHIFT (0U) -#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) -/*! @} */ - -/*! @name BDTPAGE1 - BDT Page register 1 */ -/*! @{ */ -#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) -#define USB_BDTPAGE1_BDTBA_SHIFT (1U) -#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) -/*! @} */ - -/*! @name FRMNUML - Frame Number register Low */ -/*! @{ */ -#define USB_FRMNUML_FRM_MASK (0xFFU) -#define USB_FRMNUML_FRM_SHIFT (0U) -#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) -/*! @} */ - -/*! @name FRMNUMH - Frame Number register High */ -/*! @{ */ -#define USB_FRMNUMH_FRM_MASK (0x7U) -#define USB_FRMNUMH_FRM_SHIFT (0U) -#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) -/*! @} */ - -/*! @name BDTPAGE2 - BDT Page Register 2 */ -/*! @{ */ -#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE2_BDTBA_SHIFT (0U) -#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) -/*! @} */ - -/*! @name BDTPAGE3 - BDT Page Register 3 */ -/*! @{ */ -#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE3_BDTBA_SHIFT (0U) -#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) -/*! @} */ - -/*! @name ENDPT - Endpoint Control register */ -/*! @{ */ -#define USB_ENDPT_EPHSHK_MASK (0x1U) -#define USB_ENDPT_EPHSHK_SHIFT (0U) -#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) -#define USB_ENDPT_EPSTALL_MASK (0x2U) -#define USB_ENDPT_EPSTALL_SHIFT (1U) -#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) -#define USB_ENDPT_EPTXEN_MASK (0x4U) -#define USB_ENDPT_EPTXEN_SHIFT (2U) -#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) -#define USB_ENDPT_EPRXEN_MASK (0x8U) -#define USB_ENDPT_EPRXEN_SHIFT (3U) -#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) -#define USB_ENDPT_EPCTLDIS_MASK (0x10U) -#define USB_ENDPT_EPCTLDIS_SHIFT (4U) -#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) -/*! @} */ - -/* The count of USB_ENDPT */ -#define USB_ENDPT_COUNT (16U) - -/*! @name USBCTRL - USB Control register */ -/*! @{ */ -#define USB_USBCTRL_UARTSEL_MASK (0x10U) -#define USB_USBCTRL_UARTSEL_SHIFT (4U) -/*! UARTSEL - UART Select - * 0b0..USB signals are not used as UART signals. - * 0b1..USB signals are used as UART signals. - */ -#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) -#define USB_USBCTRL_UARTCHLS_MASK (0x20U) -#define USB_USBCTRL_UARTCHLS_SHIFT (5U) -/*! UARTCHLS - UART Signal Channel Select - * 0b0..USB DP/DM signals are used as UART TX/RX. - * 0b1..USB DP/DM signals are used as UART RX/TX. - */ -#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) -#define USB_USBCTRL_PDE_MASK (0x40U) -#define USB_USBCTRL_PDE_SHIFT (6U) -/*! PDE - Pulldown enable - * 0b0..Weak pulldowns are disabled on D+ and D-. - * 0b1..Weak pulldowns are enabled on D+ and D-. - */ -#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) -#define USB_USBCTRL_SUSP_MASK (0x80U) -#define USB_USBCTRL_SUSP_SHIFT (7U) -/*! SUSP - Suspend - * 0b0..USB transceiver is not in the Suspend state. - * 0b1..USB transceiver is in the Suspend state. - */ -#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) -/*! @} */ - -/*! @name OBSERVE - USB OTG Observe register */ -/*! @{ */ -#define USB_OBSERVE_DMPD_MASK (0x10U) -#define USB_OBSERVE_DMPD_SHIFT (4U) -/*! DMPD - DMPD - * 0b0..D- pulldown is disabled. - * 0b1..D- pulldown is enabled. - */ -#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) -#define USB_OBSERVE_DPPD_MASK (0x40U) -#define USB_OBSERVE_DPPD_SHIFT (6U) -/*! DPPD - DPPD - * 0b0..D+ pulldown is disabled. - * 0b1..D+ pulldown is enabled. - */ -#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) -#define USB_OBSERVE_DPPU_MASK (0x80U) -#define USB_OBSERVE_DPPU_SHIFT (7U) -/*! DPPU - DPPU - * 0b0..D+ pullup disabled. - * 0b1..D+ pullup enabled. - */ -#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) -/*! @} */ - -/*! @name CONTROL - USB OTG Control register */ -/*! @{ */ -#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) -#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) -/*! DPPULLUPNONOTG - DPPULLUPNONOTG - * 0b0..DP Pullup in non-OTG Device mode is not enabled. - * 0b1..DP Pullup in non-OTG Device mode is enabled. - */ -#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) -/*! @} */ - -/*! @name USBTRC0 - USB Transceiver Control register 0 */ -/*! @{ */ -#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) -#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) -/*! USB_RESUME_INT - USB Asynchronous Interrupt - * 0b0..No interrupt was generated. - * 0b1..Interrupt was generated because of the USB asynchronous interrupt. - */ -#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) -#define USB_USBTRC0_SYNC_DET_MASK (0x2U) -#define USB_USBTRC0_SYNC_DET_SHIFT (1U) -/*! SYNC_DET - Synchronous USB Interrupt Detect - * 0b0..Synchronous interrupt has not been detected. - * 0b1..Synchronous interrupt has been detected. - */ -#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) -#define USB_USBTRC0_VREDG_DET_MASK (0x8U) -#define USB_USBTRC0_VREDG_DET_SHIFT (3U) -/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect - * 0b0..VREGIN rising edge interrupt has not been detected. - * 0b1..VREGIN rising edge interrupt has been detected. - */ -#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) -#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) -#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) -/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect - * 0b0..VREGIN falling edge interrupt has not been detected. - * 0b1..VREGIN falling edge interrupt has been detected. - */ -#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) -#define USB_USBTRC0_USBRESMEN_MASK (0x20U) -#define USB_USBTRC0_USBRESMEN_SHIFT (5U) -/*! USBRESMEN - Asynchronous Resume Interrupt Enable - * 0b0..USB asynchronous wakeup from Suspend mode is disabled. - * 0b1..USB asynchronous wakeup from Suspend mode is enabled. - */ -#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) -#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) -#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) -#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) -#define USB_USBTRC0_USBRESET_MASK (0x80U) -#define USB_USBTRC0_USBRESET_SHIFT (7U) -/*! USBRESET - USB Reset - * 0b0..Normal USB module operation. - * 0b1..Returns the USB module to its reset state. - */ -#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) -/*! @} */ - -/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */ -/*! @{ */ -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) -/*! STOP_ACK_DLY_EN - STOP_ACK_DLY_EN - * 0b0..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. - * 0b1..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. - */ -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) -/*! WAKE_REQ_EN - WAKE_REQ_EN - * 0b0..USB bus wakeup request is disabled - * 0b1..USB bus wakeup request is enabled - */ -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) -/*! KEEP_ALIVE_STS - Keep Alive Status - * 0b0..USB is not in Keep Alive mode. - * 0b1..USB is in Keep Alive mode. - */ -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) -/*! @} */ - -/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */ -/*! @{ */ -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) -/*! WAKE_ON_THIS - WAKE_ON_THIS - * 0b0001..Wake up after receiving OUT/SETUP token packet. - * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. - */ -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) -/*! @} */ - -/*! @name MISCCTRL - Miscellaneous Control register */ -/*! @{ */ -#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) -#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) -/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode - * 0b0..SOF_TOK interrupt is set when byte times SOF threshold is reached. - * 0b1..SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped. - */ -#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) -#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) -#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) -/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select - * 0b0..SOF_TOK interrupt is set according to SOF threshold value. - * 0b1..SOF_TOK interrupt is set when SOF counter reaches 0. - */ -#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) -#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) -#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) -/*! OWNERRISODIS - OWN Error Detect for ISO IN / ISO OUT Disable - * 0b0..OWN error detect for ISO IN / ISO OUT is not disabled. - * 0b1..OWN error detect for ISO IN / ISO OUT is disabled. - */ -#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) -#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) -#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) -/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable - * 0b0..VREGIN rising edge interrupt disabled. - * 0b1..VREGIN rising edge interrupt enabled. - */ -#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) -#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) -#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) -/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable - * 0b0..VREGIN falling edge interrupt disabled. - * 0b1..VREGIN falling edge interrupt enabled. - */ -#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) -#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) -#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) -/*! STL_ADJ_EN - USB Peripheral mode Stall Adjust Enable - * 0b0..If USB_ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint will be stalled - * 0b1..If USB_ENDPTn[END_STALL] = 1, the USB_STALL_xx_DIS registers control which directions for the associated endpoint will be stalled. - */ -#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) -/*! @} */ - -/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */ -/*! @{ */ -#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) -#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) -/*! STALL_I_DIS0 - STALL_I_DIS0 - * 0b0..Endpoint 0 IN direction stall is enabled. - * 0b1..Endpoint 0 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) -#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) -/*! STALL_I_DIS1 - STALL_I_DIS1 - * 0b0..Endpoint 1 IN direction stall is enabled. - * 0b1..Endpoint 1 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) -#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) -/*! STALL_I_DIS2 - STALL_I_DIS2 - * 0b0..Endpoint 2 IN direction stall is enabled. - * 0b1..Endpoint 2 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) -#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) -/*! STALL_I_DIS3 - STALL_I_DIS3 - * 0b0..Endpoint 3 IN direction stall is enabled. - * 0b1..Endpoint 3 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) -#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) -/*! STALL_I_DIS4 - STALL_I_DIS4 - * 0b0..Endpoint 4 IN direction stall is enabled. - * 0b1..Endpoint 4 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) -#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) -/*! STALL_I_DIS5 - STALL_I_DIS5 - * 0b0..Endpoint 5 IN direction stall is enabled. - * 0b1..Endpoint 5 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) -#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) -/*! STALL_I_DIS6 - STALL_I_DIS6 - * 0b0..Endpoint 6 IN direction stall is enabled. - * 0b1..Endpoint 6 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) -#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) -/*! STALL_I_DIS7 - STALL_I_DIS7 - * 0b0..Endpoint 7 IN direction stall is enabled. - * 0b1..Endpoint 7 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) -/*! @} */ - -/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */ -/*! @{ */ -#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) -#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) -/*! STALL_I_DIS8 - STALL_I_DIS8 - * 0b0..Endpoint 8 IN direction stall is enabled. - * 0b1..Endpoint 8 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) -#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) -/*! STALL_I_DIS9 - STALL_I_DIS9 - * 0b0..Endpoint 9 IN direction stall is enabled. - * 0b1..Endpoint 9 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) -#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) -/*! STALL_I_DIS10 - STALL_I_DIS10 - * 0b0..Endpoint 10 IN direction stall is enabled. - * 0b1..Endpoint 10 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) -#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) -/*! STALL_I_DIS11 - STALL_I_DIS11 - * 0b0..Endpoint 11 IN direction stall is enabled. - * 0b1..Endpoint 11 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) -#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) -/*! STALL_I_DIS12 - STALL_I_DIS12 - * 0b0..Endpoint 12 IN direction stall is enabled. - * 0b1..Endpoint 12 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) -#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) -/*! STALL_I_DIS13 - STALL_I_DIS13 - * 0b0..Endpoint 13 IN direction stall is enabled. - * 0b1..Endpoint 13 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) -#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) -/*! STALL_I_DIS14 - STALL_I_DIS14 - * 0b0..Endpoint 14 IN direction stall is enabled. - * 0b1..Endpoint 14 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) -#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) -/*! STALL_I_DIS15 - STALL_I_DIS15 - * 0b0..Endpoint 15 IN direction stall is enabled. - * 0b1..Endpoint 15 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) -/*! @} */ - -/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */ -/*! @{ */ -#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) -#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) -/*! STALL_O_DIS0 - STALL_O_DIS0 - * 0b0..Endpoint 0 OUT direction stall is enabled. - * 0b1..Endpoint 0 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) -#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) -/*! STALL_O_DIS1 - STALL_O_DIS1 - * 0b0..Endpoint 1 OUT direction stall is enabled. - * 0b1..Endpoint 1 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) -#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) -/*! STALL_O_DIS2 - STALL_O_DIS2 - * 0b0..Endpoint 2 OUT direction stall is enabled. - * 0b1..Endpoint 2 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) -#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) -/*! STALL_O_DIS3 - STALL_O_DIS3 - * 0b0..Endpoint 3 OUT direction stall is enabled. - * 0b1..Endpoint 3 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) -#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) -/*! STALL_O_DIS4 - STALL_O_DIS4 - * 0b0..Endpoint 4 OUT direction stall is enabled. - * 0b1..Endpoint 4 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) -#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) -/*! STALL_O_DIS5 - STALL_O_DIS5 - * 0b0..Endpoint 5 OUT direction stall is enabled. - * 0b1..Endpoint 5 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) -#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) -/*! STALL_O_DIS6 - STALL_O_DIS6 - * 0b0..Endpoint 6 OUT direction stall is enabled. - * 0b1..Endpoint 6 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) -#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) -/*! STALL_O_DIS7 - STALL_O_DIS7 - * 0b0..Endpoint 7 OUT direction stall is enabled. - * 0b1..Endpoint 7 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) -/*! @} */ - -/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */ -/*! @{ */ -#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) -#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) -/*! STALL_O_DIS8 - STALL_O_DIS8 - * 0b0..Endpoint 8 OUT direction stall is enabled. - * 0b1..Endpoint 8 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) -#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) -/*! STALL_O_DIS9 - STALL_O_DIS9 - * 0b0..Endpoint 9 OUT direction stall is enabled. - * 0b1..Endpoint 9 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) -#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) -/*! STALL_O_DIS10 - STALL_O_DIS10 - * 0b0..Endpoint 10 OUT direction stall is enabled. - * 0b1..Endpoint 10 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) -#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) -/*! STALL_O_DIS11 - STALL_O_DIS11 - * 0b0..Endpoint 11 OUT direction stall is enabled. - * 0b1..Endpoint 11 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) -#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) -/*! STALL_O_DIS12 - STALL_O_DIS12 - * 0b0..Endpoint 12 OUT direction stall is enabled. - * 0b1..Endpoint 12 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) -#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) -/*! STALL_O_DIS13 - STALL_O_DIS13 - * 0b0..Endpoint 13 OUT direction stall is enabled. - * 0b1..Endpoint 13 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) -#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) -/*! STALL_O_DIS14 - STALL_O_DIS14 - * 0b0..Endpoint 14 OUT direction stall is enabled. - * 0b1..Endpoint 14 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) -#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) -/*! STALL_O_DIS15 - STALL_O_DIS15 - * 0b0..Endpoint 15 OUT direction stall is enabled. - * 0b1..Endpoint 15 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ -/*! @{ */ -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) -/*! RESTART_IFRTRIM_EN - Restart from IFR trim value - * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default). - * 0b1..Trim fine restarts from the IFR trim value, whenever bus_reset/bus_resume is detected or module enable is desasserted. - */ -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) -/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable - * 0b0..Always works in tracking phase after the first time rough phase, to track transition (default). - * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. - */ -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) -/*! CLOCK_RECOVER_EN - Crystal-less USB enable - * 0b0..Disable clock recovery block (default) - * 0b1..Enable clock recovery block - */ -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_IRC_EN - IRC48MFIRC oscillator enable register */ -/*! @{ */ -#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) -#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) -/*! REG_EN - Regulator enable - * 0b0..IRC48M local regulator is disabled - * 0b1..IRC48M local regulator is enabled (default) - */ -#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) -/*! IRC_EN - IRC_EN - * 0b0..Disable the IRC48M module (default) - * 0b1..Enable the IRC48M module - */ -#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ -/*! @{ */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) -/*! OVF_ERROR_EN - OVF_ERROR_EN - * 0b0..The interrupt will be masked - * 0b1..The interrupt will be enabled (default) - */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ -/*! @{ */ -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) -/*! OVF_ERROR - OVF_ERROR - * 0b0..No interrupt is reported - * 0b1..Unmasked interrupt has been generated - */ -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40045000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBVREG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBVREG_Peripheral_Access_Layer USBVREG Peripheral Access Layer - * @{ - */ - -/** USBVREG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< USB VREG Control Register, offset: 0x0 */ - __IO uint32_t CFGCTRL; /**< USB VREG Configuration Control Register, offset: 0x4 */ -} USBVREG_Type; - -/* ---------------------------------------------------------------------------- - -- USBVREG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBVREG_Register_Masks USBVREG Register Masks - * @{ - */ - -/*! @name CTRL - USB VREG Control Register */ -/*! @{ */ -#define USBVREG_CTRL_VSTBY_MASK (0x20000000U) -#define USBVREG_CTRL_VSTBY_SHIFT (29U) -/*! VSTBY - USB Voltage Regulator in Standby Mode during VLPR and VLPW modes - * 0b0..USB voltage regulator is not in standby during VLPR and VLPW modes. - * 0b1..USB voltage regulator in standby during VLPR and VLPW modes. - */ -#define USBVREG_CTRL_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_VSTBY_SHIFT)) & USBVREG_CTRL_VSTBY_MASK) -#define USBVREG_CTRL_SSTBY_MASK (0x40000000U) -#define USBVREG_CTRL_SSTBY_SHIFT (30U) -/*! SSTBY - USB Voltage Regulator in Standby Mode during Stop, VLPS, LLS and VLLS Modes - * 0b0..USB voltage regulator is not in standby during Stop,VLPS,LLS and VLLS modes. - * 0b1..USB voltage regulator is in standby during Stop,VLPS,LLS and VLLS modes. - */ -#define USBVREG_CTRL_SSTBY(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_SSTBY_SHIFT)) & USBVREG_CTRL_SSTBY_MASK) -#define USBVREG_CTRL_EN_MASK (0x80000000U) -#define USBVREG_CTRL_EN_SHIFT (31U) -/*! EN - USB Voltage Regulator Enable - * 0b0..USB voltage regulator is disabled. - * 0b1..USB voltage regulator is enabled. - */ -#define USBVREG_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_EN_SHIFT)) & USBVREG_CTRL_EN_MASK) -/*! @} */ - -/*! @name CFGCTRL - USB VREG Configuration Control Register */ -/*! @{ */ -#define USBVREG_CFGCTRL_URWE_MASK (0x1000000U) -#define USBVREG_CFGCTRL_URWE_SHIFT (24U) -/*! URWE - USB Voltage Regulator Enable Write Enable - * 0b0..CTRL[EN] can not be written. - * 0b1..CTRL[EN] can be written. - */ -#define USBVREG_CFGCTRL_URWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_URWE_SHIFT)) & USBVREG_CFGCTRL_URWE_MASK) -#define USBVREG_CFGCTRL_UVSWE_MASK (0x2000000U) -#define USBVREG_CFGCTRL_UVSWE_SHIFT (25U) -/*! UVSWE - USB Voltage Regulator VLP Standby Write Enable - * 0b0..CTRL[VSTBY] cannot be written. - * 0b1..CTRL[VSTBY] can be written. - */ -#define USBVREG_CFGCTRL_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_UVSWE_SHIFT)) & USBVREG_CFGCTRL_UVSWE_MASK) -#define USBVREG_CFGCTRL_USSWE_MASK (0x4000000U) -#define USBVREG_CFGCTRL_USSWE_SHIFT (26U) -/*! USSWE - USB Voltage Rregulator Stop Standby Write Enable - * 0b0..CTRL[SSTBY] field cannot be written. - * 0b1..CTRL[SSTBY] can be written. - */ -#define USBVREG_CFGCTRL_USSWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_USSWE_SHIFT)) & USBVREG_CFGCTRL_USSWE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBVREG_Register_Masks */ - - -/* USBVREG - Peripheral instance base addresses */ -/** Peripheral USBVREG base address */ -#define USBVREG_BASE (0x40027000u) -/** Peripheral USBVREG base pointer */ -#define USBVREG ((USBVREG_Type *)USBVREG_BASE) -/** Array initializer of USBVREG peripheral base addresses */ -#define USBVREG_BASE_ADDRS { USBVREG_BASE } -/** Array initializer of USBVREG peripheral base pointers */ -#define USBVREG_BASE_PTRS { USBVREG } - -/*! - * @} - */ /* end of group USBVREG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USDHC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer - * @{ - */ - -/** USDHC - Register Layout Typedef */ -typedef struct { - __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ - __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ - __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ - __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ - __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ - __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ - __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ - __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ - __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ - __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ - __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ - __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ - __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ - __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ - __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ - __I uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ - __I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ - __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ - __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ - uint8_t RESERVED_0[4]; - __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ - __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ - __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ - uint8_t RESERVED_1[100]; - __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ - __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ - __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ -} USDHC_Type; - -/* ---------------------------------------------------------------------------- - -- USDHC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Register_Masks USDHC Register Masks - * @{ - */ - -/*! @name DS_ADDR - DMA System Address */ -/*! @{ */ -#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) -#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) -#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) -/*! @} */ - -/*! @name BLK_ATT - Block Attributes */ -/*! @{ */ -#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) -#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) -/*! BLKSIZE - Block Size - * 0b1000000000000..4096 Bytes - * 0b0100000000000..2048 Bytes - * 0b0001000000000..512 Bytes - * 0b0000111111111..511 Bytes - * 0b0000000000100..4 Bytes - * 0b0000000000011..3 Bytes - * 0b0000000000010..2 Bytes - * 0b0000000000001..1 Byte - * 0b0000000000000..No data transfer - */ -#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) -#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) -#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) -/*! BLKCNT - Block Count - * 0b1111111111111111..65535 blocks - * 0b0000000000000010..2 blocks - * 0b0000000000000001..1 block - * 0b0000000000000000..Stop Count - */ -#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) -/*! @} */ - -/*! @name CMD_ARG - Command Argument */ -/*! @{ */ -#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) -#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) -#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) -/*! @} */ - -/*! @name CMD_XFR_TYP - Command Transfer Type */ -/*! @{ */ -#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) -#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) -/*! RSPTYP - Response Type Select - * 0b00..No Response - * 0b01..Response Length 136 - * 0b10..Response Length 48 - * 0b11..Response Length 48, check Busy after response - */ -#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) -#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) -#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) -/*! CCCEN - Command CRC Check Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) -#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) -#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) -/*! CICEN - Command Index Check Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) -#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) -#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) -/*! DPSEL - Data Present Select - * 0b1..Data Present - * 0b0..No Data Present - */ -#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) -#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) -#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) -/*! CMDTYP - Command Type - * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR - * 0b10..Resume CMD52 for writing Function Select in CCCR - * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR - * 0b00..Normal Other commands - */ -#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) -#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) -#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) -#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) -/*! @} */ - -/*! @name CMD_RSP0 - Command Response0 */ -/*! @{ */ -#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) -#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) -/*! @} */ - -/*! @name CMD_RSP1 - Command Response1 */ -/*! @{ */ -#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) -#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) -/*! @} */ - -/*! @name CMD_RSP2 - Command Response2 */ -/*! @{ */ -#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) -#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) -/*! @} */ - -/*! @name CMD_RSP3 - Command Response3 */ -/*! @{ */ -#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) -#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) -/*! @} */ - -/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ -/*! @{ */ -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) -/*! @} */ - -/*! @name PRES_STATE - Present State */ -/*! @{ */ -#define USDHC_PRES_STATE_CIHB_MASK (0x1U) -#define USDHC_PRES_STATE_CIHB_SHIFT (0U) -/*! CIHB - Command Inhibit (CMD) - * 0b1..Cannot issue command - * 0b0..Can issue command using only CMD line - */ -#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) -#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) -#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) -/*! CDIHB - Command Inhibit (DATA) - * 0b1..Cannot issue command which uses the DATA line - * 0b0..Can issue command which uses the DATA line - */ -#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) -#define USDHC_PRES_STATE_DLA_MASK (0x4U) -#define USDHC_PRES_STATE_DLA_SHIFT (2U) -/*! DLA - Data Line Active - * 0b1..DATA Line Active - * 0b0..DATA Line Inactive - */ -#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) -#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) -#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) -/*! SDSTB - SD Clock Stable - * 0b1..Clock is stable. - * 0b0..Clock is changing frequency and not stable. - */ -#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) -#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) -#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) -/*! IPGOFF - IPG_CLK Gated Off Internally - * 0b1..IPG_CLK is gated off. - * 0b0..IPG_CLK is active. - */ -#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) -#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) -#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) -/*! HCKOFF - HCLK Gated Off Internally - * 0b1..HCLK is gated off. - * 0b0..HCLK is active. - */ -#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) -#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) -#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) -/*! PEROFF - IPG_PERCLK Gated Off Internally - * 0b1..IPG_PERCLK is gated off. - * 0b0..IPG_PERCLK is active. - */ -#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) -#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) -#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) -/*! SDOFF - SD Clock Gated Off Internally - * 0b1..SD Clock is gated off. - * 0b0..SD Clock is active. - */ -#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) -#define USDHC_PRES_STATE_WTA_MASK (0x100U) -#define USDHC_PRES_STATE_WTA_SHIFT (8U) -/*! WTA - Write Transfer Active - * 0b1..Transferring data - * 0b0..No valid data - */ -#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) -#define USDHC_PRES_STATE_RTA_MASK (0x200U) -#define USDHC_PRES_STATE_RTA_SHIFT (9U) -/*! RTA - Read Transfer Active - * 0b1..Transferring data - * 0b0..No valid data - */ -#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) -#define USDHC_PRES_STATE_BWEN_MASK (0x400U) -#define USDHC_PRES_STATE_BWEN_SHIFT (10U) -/*! BWEN - Buffer Write Enable - * 0b1..Write enable - * 0b0..Write disable - */ -#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) -#define USDHC_PRES_STATE_BREN_MASK (0x800U) -#define USDHC_PRES_STATE_BREN_SHIFT (11U) -/*! BREN - Buffer Read Enable - * 0b1..Read enable - * 0b0..Read disable - */ -#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) -#define USDHC_PRES_STATE_CINST_MASK (0x10000U) -#define USDHC_PRES_STATE_CINST_SHIFT (16U) -/*! CINST - Card Inserted - * 0b1..Card Inserted - * 0b0..Power on Reset or No Card - */ -#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) -#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) -#define USDHC_PRES_STATE_CDPL_SHIFT (18U) -/*! CDPL - Card Detect Pin Level - * 0b1..Card present (CD_B = 0) - * 0b0..No card present (CD_B = 1) - */ -#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) -#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) -#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) -/*! WPSPL - Write Protect Switch Pin Level - * 0b1..Write enabled (WP = 0) - * 0b0..Write protected (WP = 1) - */ -#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) -#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) -#define USDHC_PRES_STATE_CLSL_SHIFT (23U) -#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) -#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) -#define USDHC_PRES_STATE_DLSL_SHIFT (24U) -/*! DLSL - DATA[7:0] Line Signal Level - * 0b00000111..Data 7 line signal level - * 0b00000110..Data 6 line signal level - * 0b00000101..Data 5 line signal level - * 0b00000100..Data 4 line signal level - * 0b00000011..Data 3 line signal level - * 0b00000010..Data 2 line signal level - * 0b00000001..Data 1 line signal level - * 0b00000000..Data 0 line signal level - */ -#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) -/*! @} */ - -/*! @name PROT_CTRL - Protocol Control */ -/*! @{ */ -#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) -#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) -/*! LCTL - LED Control - * 0b1..LED on - * 0b0..LED off - */ -#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) -#define USDHC_PROT_CTRL_DTW_MASK (0x6U) -#define USDHC_PROT_CTRL_DTW_SHIFT (1U) -/*! DTW - Data Transfer Width - * 0b10..8-bit mode - * 0b01..4-bit mode - * 0b00..1-bit mode - * 0b11..Reserved - */ -#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) -#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) -#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) -/*! D3CD - DATA3 as Card Detection Pin - * 0b1..DATA3 as Card Detection Pin - * 0b0..DATA3 does not monitor Card Insertion - */ -#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) -#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) -#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) -/*! EMODE - Endian Mode - * 0b00..Big Endian Mode - * 0b01..Half Word Big Endian Mode - * 0b10..Little Endian Mode - * 0b11..Reserved - */ -#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) -#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) -#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) -/*! CDTL - Card Detect Test Level - * 0b1..Card Detect Test Level is 1, card inserted - * 0b0..Card Detect Test Level is 0, no card inserted - */ -#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) -#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) -#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) -/*! CDSS - Card Detect Signal Selection - * 0b1..Card Detection Test Level is selected (for test purpose). - * 0b0..Card Detection Level is selected (for normal purpose). - */ -#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) -#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) -#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) -/*! DMASEL - DMA Select - * 0b00..No DMA or Simple DMA is selected - * 0b01..ADMA1 is selected - * 0b10..ADMA2 is selected - * 0b11..reserved - */ -#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) -#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) -#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) -/*! SABGREQ - Stop At Block Gap Request - * 0b1..Stop - * 0b0..Transfer - */ -#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) -#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) -#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) -/*! CREQ - Continue Request - * 0b1..Restart - * 0b0..No effect - */ -#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) -#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) -#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) -/*! RWCTL - Read Wait Control - * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set - * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set - */ -#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) -#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) -#define USDHC_PROT_CTRL_IABG_SHIFT (19U) -/*! IABG - Interrupt At Block Gap - * 0b1..Enabled - * 0b0..Disabled - */ -#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) -#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) -#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) -/*! WECINT - Wakeup Event Enable On Card Interrupt - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) -#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) -#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) -/*! WECINS - Wakeup Event Enable On SD Card Insertion - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) -#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) -#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) -/*! WECRM - Wakeup Event Enable On SD Card Removal - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) -#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) -#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) -/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP - * 0bxx1..Burst length is enabled for INCR - * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 - * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP - */ -#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) -/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD - * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. - * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. - */ -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) -/*! @} */ - -/*! @name SYS_CTRL - System Control */ -/*! @{ */ -#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) -#define USDHC_SYS_CTRL_DVS_SHIFT (4U) -/*! DVS - Divisor - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) -#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) -#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) -#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) -#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) -#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) -/*! DTOCV - Data Timeout Counter Value - * 0b1111..SDCLK x 2 29 - * 0b1110..SDCLK x 2 28 - * 0b1101..SDCLK x 2 27 - * 0b0001..SDCLK x 2 15 - * 0b0000..SDCLK x 2 14 - */ -#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) -#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) -#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) -#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) -#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) -#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) -/*! RSTA - Software Reset For ALL - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) -#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) -#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) -/*! RSTC - Software Reset For CMD Line - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) -#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) -#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) -/*! RSTD - Software Reset For DATA Line - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) -#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) -#define USDHC_SYS_CTRL_INITA_SHIFT (27U) -#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status */ -/*! @{ */ -#define USDHC_INT_STATUS_CC_MASK (0x1U) -#define USDHC_INT_STATUS_CC_SHIFT (0U) -/*! CC - Command Complete - * 0b1..Command complete - * 0b0..Command not complete - */ -#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) -#define USDHC_INT_STATUS_TC_MASK (0x2U) -#define USDHC_INT_STATUS_TC_SHIFT (1U) -/*! TC - Transfer Complete - * 0b1..Transfer complete - * 0b0..Transfer not complete - */ -#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) -#define USDHC_INT_STATUS_BGE_MASK (0x4U) -#define USDHC_INT_STATUS_BGE_SHIFT (2U) -/*! BGE - Block Gap Event - * 0b1..Transaction stopped at block gap - * 0b0..No block gap event - */ -#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) -#define USDHC_INT_STATUS_DINT_MASK (0x8U) -#define USDHC_INT_STATUS_DINT_SHIFT (3U) -/*! DINT - DMA Interrupt - * 0b1..DMA Interrupt is generated - * 0b0..No DMA Interrupt - */ -#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) -#define USDHC_INT_STATUS_BWR_MASK (0x10U) -#define USDHC_INT_STATUS_BWR_SHIFT (4U) -/*! BWR - Buffer Write Ready - * 0b1..Ready to write buffer: - * 0b0..Not ready to write buffer - */ -#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) -#define USDHC_INT_STATUS_BRR_MASK (0x20U) -#define USDHC_INT_STATUS_BRR_SHIFT (5U) -/*! BRR - Buffer Read Ready - * 0b1..Ready to read buffer - * 0b0..Not ready to read buffer - */ -#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) -#define USDHC_INT_STATUS_CINS_MASK (0x40U) -#define USDHC_INT_STATUS_CINS_SHIFT (6U) -/*! CINS - Card Insertion - * 0b1..Card inserted - * 0b0..Card state unstable or removed - */ -#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) -#define USDHC_INT_STATUS_CRM_MASK (0x80U) -#define USDHC_INT_STATUS_CRM_SHIFT (7U) -/*! CRM - Card Removal - * 0b1..Card removed - * 0b0..Card state unstable or inserted - */ -#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) -#define USDHC_INT_STATUS_CINT_MASK (0x100U) -#define USDHC_INT_STATUS_CINT_SHIFT (8U) -/*! CINT - Card Interrupt - * 0b1..Generate Card Interrupt - * 0b0..No Card Interrupt - */ -#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) -#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) -#define USDHC_INT_STATUS_CTOE_SHIFT (16U) -/*! CTOE - Command Timeout Error - * 0b1..Time out - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) -#define USDHC_INT_STATUS_CCE_MASK (0x20000U) -#define USDHC_INT_STATUS_CCE_SHIFT (17U) -/*! CCE - Command CRC Error - * 0b1..CRC Error Generated. - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) -#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) -#define USDHC_INT_STATUS_CEBE_SHIFT (18U) -/*! CEBE - Command End Bit Error - * 0b1..End Bit Error Generated - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) -#define USDHC_INT_STATUS_CIE_MASK (0x80000U) -#define USDHC_INT_STATUS_CIE_SHIFT (19U) -/*! CIE - Command Index Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) -#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) -#define USDHC_INT_STATUS_DTOE_SHIFT (20U) -/*! DTOE - Data Timeout Error - * 0b1..Time out - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) -#define USDHC_INT_STATUS_DCE_MASK (0x200000U) -#define USDHC_INT_STATUS_DCE_SHIFT (21U) -/*! DCE - Data CRC Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) -#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) -#define USDHC_INT_STATUS_DEBE_SHIFT (22U) -/*! DEBE - Data End Bit Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) -#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) -#define USDHC_INT_STATUS_AC12E_SHIFT (24U) -/*! AC12E - Auto CMD12 Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) -#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) -#define USDHC_INT_STATUS_DMAE_SHIFT (28U) -/*! DMAE - DMA Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) -/*! @} */ - -/*! @name INT_STATUS_EN - Interrupt Status Enable */ -/*! @{ */ -#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) -#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) -/*! CCSEN - Command Complete Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) -#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) -#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) -/*! TCSEN - Transfer Complete Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) -#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) -#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) -/*! BGESEN - Block Gap Event Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) -#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) -#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) -/*! DINTSEN - DMA Interrupt Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) -#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) -#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) -/*! BWRSEN - Buffer Write Ready Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) -#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) -#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) -/*! BRRSEN - Buffer Read Ready Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) -#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) -#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) -/*! CINSSEN - Card Insertion Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) -#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) -#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) -/*! CRMSEN - Card Removal Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) -#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) -#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) -/*! CINTSEN - Card Interrupt Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) -#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) -#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) -/*! CTOESEN - Command Timeout Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) -#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) -#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) -/*! CCESEN - Command CRC Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) -#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) -#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) -/*! CEBESEN - Command End Bit Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) -#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) -#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) -/*! CIESEN - Command Index Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) -#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) -#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) -/*! DTOESEN - Data Timeout Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) -#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) -#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) -/*! DCESEN - Data CRC Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) -#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) -#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) -/*! DEBESEN - Data End Bit Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) -#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) -#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) -/*! AC12ESEN - Auto CMD12 Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) -#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) -#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) -/*! DMAESEN - DMA Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) -/*! @} */ - -/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ -/*! @{ */ -#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) -#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) -/*! CCIEN - Command Complete Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) -#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) -/*! TCIEN - Transfer Complete Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) -#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) -/*! BGEIEN - Block Gap Event Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) -#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) -/*! DINTIEN - DMA Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) -#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) -/*! BWRIEN - Buffer Write Ready Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) -#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) -/*! BRRIEN - Buffer Read Ready Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) -#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) -/*! CINSIEN - Card Insertion Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) -#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) -/*! CRMIEN - Card Removal Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) -#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) -/*! CINTIEN - Card Interrupt Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) -/*! CTOEIEN - Command Timeout Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) -#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) -/*! CCEIEN - Command CRC Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) -/*! CEBEIEN - Command End Bit Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) -#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) -/*! CIEIEN - Command Index Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) -/*! DTOEIEN - Data Timeout Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) -#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) -/*! DCEIEN - Data CRC Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) -/*! DEBEIEN - Data End Bit Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) -/*! AC12EIEN - Auto CMD12 Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) -/*! DMAEIEN - DMA Error Interrupt Enable - * 0b1..Enable - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) -/*! @} */ - -/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ -/*! @{ */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) -/*! AC12NE - Auto CMD12 Not Executed - * 0b1..Not executed - * 0b0..Executed - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) -/*! AC12TOE - Auto CMD12 / 23 Timeout Error - * 0b1..Time out - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) -/*! AC12EBE - Auto CMD12 / 23 End Bit Error - * 0b1..End Bit Error Generated - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) -/*! AC12CE - Auto CMD12 / 23 CRC Error - * 0b1..CRC Error Met in Auto CMD12/23 Response - * 0b0..No CRC error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) -/*! AC12IE - Auto CMD12 / 23 Index Error - * 0b1..Error, the CMD index in response is not CMD12/23 - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) -/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error - * 0b1..Not Issued - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) -/*! @} */ - -/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ -/*! @{ */ -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) -#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) -/*! MBL - Max Block Length - * 0b000..512 bytes - * 0b001..1024 bytes - * 0b010..2048 bytes - * 0b011..4096 bytes - */ -#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) -#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) -#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) -/*! ADMAS - ADMA Support - * 0b1..Advanced DMA Supported - * 0b0..Advanced DMA Not supported - */ -#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) -#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) -#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) -/*! HSS - High Speed Support - * 0b1..High Speed Supported - * 0b0..High Speed Not Supported - */ -#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) -#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) -#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) -/*! DMAS - DMA Support - * 0b1..DMA Supported - * 0b0..DMA not supported - */ -#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) -#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) -#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) -/*! SRS - Suspend / Resume Support - * 0b1..Supported - * 0b0..Not supported - */ -#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) -#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) -#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) -/*! VS33 - Voltage Support 3.3V - * 0b1..3.3V supported - * 0b0..3.3V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) -#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) -#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) -/*! VS30 - Voltage Support 3.0 V - * 0b1..3.0V supported - * 0b0..3.0V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) -#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) -#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) -/*! VS18 - Voltage Support 1.8 V - * 0b1..1.8V supported - * 0b0..1.8V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) -/*! @} */ - -/*! @name WTMK_LVL - Watermark Level */ -/*! @{ */ -#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) -#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) -#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) -#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) -#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) -#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) -#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) -#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) -#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) -#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) -#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) -#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) -/*! @} */ - -/*! @name MIX_CTRL - Mixer Control */ -/*! @{ */ -#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) -#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) -/*! DMAEN - DMA Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) -#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) -#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) -/*! BCEN - Block Count Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) -#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) -#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) -/*! AC12EN - Auto CMD12 Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) -#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) -#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) -#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) -#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) -#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) -/*! DTDSEL - Data Transfer Direction Select - * 0b1..Read (Card to Host) - * 0b0..Write (Host to Card) - */ -#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) -#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) -#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) -/*! MSBSEL - Multi / Single Block Select - * 0b1..Multiple Blocks - * 0b0..Single Block - */ -#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) -#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) -#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) -#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) -#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) -#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) -#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) -/*! @} */ - -/*! @name FORCE_EVENT - Force Event */ -/*! @{ */ -#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) -#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) -#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) -#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) -#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) -#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) -#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) -#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) -#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) -#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) -#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) -#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) -#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) -#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) -#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) -#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) -#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) -#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) -#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) -#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) -#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) -#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) -#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) -#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) -#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) -#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) -#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) -#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) -#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) -#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) -#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) -/*! @} */ - -/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ -/*! @{ */ -#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) -#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) -#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) -#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) -/*! ADMALME - ADMA Length Mismatch Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) -/*! ADMADCE - ADMA Descriptor Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) -/*! @} */ - -/*! @name ADMA_SYS_ADDR - ADMA System Address */ -/*! @{ */ -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) -/*! @} */ - -/*! @name VEND_SPEC - Vendor Specific Register */ -/*! @{ */ -#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) -#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) -/*! VSELECT - Voltage Selection - * 0b1..Change the voltage to low voltage range, around 1.8 V - * 0b0..Change the voltage to high voltage range, around 3.0 V - */ -#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) -/*! CONFLICT_CHK_EN - Conflict check enable. - * 0b0..Conflict check disable - * 0b1..Conflict check enable - */ -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) -/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN - * 0b0..Do not check busy after auto CMD12 for write data packet - * 0b1..Check busy after auto CMD12 for write data packet - */ -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) -/*! FRC_SDCLK_ON - FRC_SDCLK_ON - * 0b0..CLK active or inactive is fully controlled by the hardware. - * 0b1..Force CLK active. - */ -#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) -/*! CRC_CHK_DIS - CRC Check Disable - * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet - * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet - */ -#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) -/*! CMD_BYTE_EN - CMD_BYTE_EN - * 0b0..Disable - * 0b1..Enable - */ -#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) -/*! @} */ - -/*! @name MMC_BOOT - MMC Boot Register */ -/*! @{ */ -#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) -#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) -/*! DTOCV_ACK - DTOCV_ACK - * 0b0000..SDCLK x 2^14 - * 0b0001..SDCLK x 2^15 - * 0b0010..SDCLK x 2^16 - * 0b0011..SDCLK x 2^17 - * 0b0100..SDCLK x 2^18 - * 0b0101..SDCLK x 2^19 - * 0b0110..SDCLK x 2^20 - * 0b0111..SDCLK x 2^21 - * 0b1110..SDCLK x 2^28 - * 0b1111..SDCLK x 2^29 - */ -#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) -#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) -/*! BOOT_ACK - BOOT_ACK - * 0b0..No ack - * 0b1..Ack - */ -#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) -#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) -/*! BOOT_MODE - BOOT_MODE - * 0b0..Normal boot - * 0b1..Alternative boot - */ -#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) -#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) -#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) -/*! BOOT_EN - BOOT_EN - * 0b0..Fast boot disable - * 0b1..Fast boot enable - */ -#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) -/*! DISABLE_TIME_OUT - Disable Time Out - * 0b0..Enable time out - * 0b1..Disable time out - */ -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) -/*! @} */ - -/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ -/*! @{ */ -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) -/*! CARD_INT_D3_TEST - Card Interrupt Detection Test - * 0b0..Check the card interrupt only when DATA3 is high. - * 0b1..Check the card interrupt by ignoring the status of DATA3. - */ -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) -/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 - * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. - * 0b0..Disable - */ -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USDHC_Register_Masks */ - - -/* USDHC - Peripheral instance base addresses */ -/** Peripheral USDHC0 base address */ -#define USDHC0_BASE (0x4003E000u) -/** Peripheral USDHC0 base pointer */ -#define USDHC0 ((USDHC_Type *)USDHC0_BASE) -/** Array initializer of USDHC peripheral base addresses */ -#define USDHC_BASE_ADDRS { USDHC0_BASE } -/** Array initializer of USDHC peripheral base pointers */ -#define USDHC_BASE_PTRS { USDHC0 } -/** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { USDHC0_IRQn } - -/*! - * @} - */ /* end of group USDHC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- VREF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer - * @{ - */ - -/** VREF - Register Layout Typedef */ -typedef struct { - __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ - __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ - uint8_t RESERVED_0[3]; - __IO uint8_t TRM4; /**< VREF Trim 2.1V Register, offset: 0x5 */ -} VREF_Type; - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/*! @name TRM - VREF Trim Register */ -/*! @{ */ -#define VREF_TRM_TRIM_MASK (0x3FU) -#define VREF_TRM_TRIM_SHIFT (0U) -/*! TRIM - Trim bits - * 0b000000..Min - * 0b111111..Max - */ -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) -#define VREF_TRM_CHOPEN_MASK (0x40U) -#define VREF_TRM_CHOPEN_SHIFT (6U) -/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized. - * 0b0..Chop oscillator is disabled. - * 0b1..Chop oscillator is enabled. - */ -#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) -/*! @} */ - -/*! @name SC - VREF Status and Control Register */ -/*! @{ */ -#define VREF_SC_MODE_LV_MASK (0x3U) -#define VREF_SC_MODE_LV_SHIFT (0U) -/*! MODE_LV - Buffer Mode selection - * 0b00..Bandgap on only, for stabilization and startup - * 0b01..High power buffer mode enabled - * 0b10..Low-power buffer mode enabled - * 0b11..Reserved - */ -#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) -#define VREF_SC_VREFST_MASK (0x4U) -#define VREF_SC_VREFST_SHIFT (2U) -/*! VREFST - Internal Voltage Reference stable - * 0b0..The module is disabled or not stable. - * 0b1..The module is stable. - */ -#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) -#define VREF_SC_ICOMPEN_MASK (0x20U) -#define VREF_SC_ICOMPEN_SHIFT (5U) -/*! ICOMPEN - Second order curvature compensation enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) -#define VREF_SC_REGEN_MASK (0x40U) -#define VREF_SC_REGEN_SHIFT (6U) -/*! REGEN - Regulator enable - * 0b0..Internal 1.75 V regulator is disabled. - * 0b1..Internal 1.75 V regulator is enabled. - */ -#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) -#define VREF_SC_VREFEN_MASK (0x80U) -#define VREF_SC_VREFEN_SHIFT (7U) -/*! VREFEN - Internal Voltage Reference enable - * 0b0..The module is disabled. - * 0b1..The module is enabled. - */ -#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) -/*! @} */ - -/*! @name TRM4 - VREF Trim 2.1V Register */ -/*! @{ */ -#define VREF_TRM4_TRIM2V1_MASK (0x3FU) -#define VREF_TRM4_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1V Trim Bits - * 0b000000..Max - * 0b111111..Min - */ -#define VREF_TRM4_TRIM2V1(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_TRIM2V1_SHIFT)) & VREF_TRM4_TRIM2V1_MASK) -#define VREF_TRM4_VREF2V1_EN_MASK (0x80U) -#define VREF_TRM4_VREF2V1_EN_SHIFT (7U) -/*! VREF2V1_EN - Internal Voltage Reference (2.1V) Enable - * 0b0..VREF 2.1V is enabled - * 0b1..VREF 2.1V is disabled - */ -#define VREF_TRM4_VREF2V1_EN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group VREF_Register_Masks */ - - -/* VREF - Peripheral instance base addresses */ -/** Peripheral VREF base address */ -#define VREF_BASE (0x4004D000u) -/** Peripheral VREF base pointer */ -#define VREF ((VREF_Type *)VREF_BASE) -/** Array initializer of VREF peripheral base addresses */ -#define VREF_BASE_ADDRS { VREF_BASE } -/** Array initializer of VREF peripheral base pointers */ -#define VREF_BASE_PTRS { VREF } - -/*! - * @} - */ /* end of group VREF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer - * @{ - */ - -/** WDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ - __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ - __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ - __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ -} WDOG_Type; - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/*! @name CS - Watchdog Control and Status Register */ -/*! @{ */ -#define WDOG_CS_STOP_MASK (0x1U) -#define WDOG_CS_STOP_SHIFT (0U) -/*! STOP - Stop Enable - * 0b0..Watchdog disabled in chip stop mode. - * 0b1..Watchdog enabled in chip stop mode. - */ -#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) -#define WDOG_CS_WAIT_MASK (0x2U) -#define WDOG_CS_WAIT_SHIFT (1U) -/*! WAIT - Wait Enable - * 0b0..Watchdog disabled in chip wait mode. - * 0b1..Watchdog enabled in chip wait mode. - */ -#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) -#define WDOG_CS_DBG_MASK (0x4U) -#define WDOG_CS_DBG_SHIFT (2U) -/*! DBG - Debug Enable - * 0b0..Watchdog disabled in chip debug mode. - * 0b1..Watchdog enabled in chip debug mode. - */ -#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) -#define WDOG_CS_TST_MASK (0x18U) -#define WDOG_CS_TST_SHIFT (3U) -/*! TST - Watchdog Test - * 0b00..Watchdog test mode disabled. - * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. - * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. - * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. - */ -#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) -#define WDOG_CS_UPDATE_MASK (0x20U) -#define WDOG_CS_UPDATE_SHIFT (5U) -/*! UPDATE - Allow updates - * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. - * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. - */ -#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) -#define WDOG_CS_INT_MASK (0x40U) -#define WDOG_CS_INT_SHIFT (6U) -/*! INT - Watchdog Interrupt - * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. - * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. - */ -#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) -#define WDOG_CS_EN_MASK (0x80U) -#define WDOG_CS_EN_SHIFT (7U) -/*! EN - Watchdog Enable - * 0b0..Watchdog disabled. - * 0b1..Watchdog enabled. - */ -#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) -#define WDOG_CS_CLK_MASK (0x300U) -#define WDOG_CS_CLK_SHIFT (8U) -/*! CLK - Watchdog Clock - * 0b00..Bus clock - * 0b01..LPO clock - * 0b10..INTCLK (internal clock) - * 0b11..ERCLK (external reference clock) - */ -#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) -#define WDOG_CS_RCS_MASK (0x400U) -#define WDOG_CS_RCS_SHIFT (10U) -/*! RCS - Reconfiguration Success - * 0b0..Reconfiguring WDOG. - * 0b1..Reconfiguration is successful. - */ -#define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) -#define WDOG_CS_ULK_MASK (0x800U) -#define WDOG_CS_ULK_SHIFT (11U) -/*! ULK - Unlock status - * 0b0..WDOG is locked. - * 0b1..WDOG is unlocked. - */ -#define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) -#define WDOG_CS_PRES_MASK (0x1000U) -#define WDOG_CS_PRES_SHIFT (12U) -/*! PRES - Watchdog prescaler - * 0b0..256 prescaler disabled. - * 0b1..256 prescaler enabled. - */ -#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) -#define WDOG_CS_CMD32EN_MASK (0x2000U) -#define WDOG_CS_CMD32EN_SHIFT (13U) -/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words - * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. - * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. - */ -#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) -#define WDOG_CS_FLG_MASK (0x4000U) -#define WDOG_CS_FLG_SHIFT (14U) -/*! FLG - Watchdog Interrupt Flag - * 0b0..No interrupt occurred. - * 0b1..An interrupt occurred. - */ -#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) -#define WDOG_CS_WIN_MASK (0x8000U) -#define WDOG_CS_WIN_SHIFT (15U) -/*! WIN - Watchdog Window - * 0b0..Window mode disabled. - * 0b1..Window mode enabled. - */ -#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) -/*! @} */ - -/*! @name CNT - Watchdog Counter Register */ -/*! @{ */ -#define WDOG_CNT_CNTLOW_MASK (0xFFU) -#define WDOG_CNT_CNTLOW_SHIFT (0U) -#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) -#define WDOG_CNT_CNTHIGH_MASK (0xFF00U) -#define WDOG_CNT_CNTHIGH_SHIFT (8U) -#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) -/*! @} */ - -/*! @name TOVAL - Watchdog Timeout Value Register */ -/*! @{ */ -#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) -#define WDOG_TOVAL_TOVALLOW_SHIFT (0U) -#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) -#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) -#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) -#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) -/*! @} */ - -/*! @name WIN - Watchdog Window Register */ -/*! @{ */ -#define WDOG_WIN_WINLOW_MASK (0xFFU) -#define WDOG_WIN_WINLOW_SHIFT (0U) -#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) -#define WDOG_WIN_WINHIGH_MASK (0xFF00U) -#define WDOG_WIN_WINHIGH_SHIFT (8U) -#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WDOG_Register_Masks */ - - -/* WDOG - Peripheral instance base addresses */ -/** Peripheral WDOG0 base address */ -#define WDOG0_BASE (0x4002A000u) -/** Peripheral WDOG0 base pointer */ -#define WDOG0 ((WDOG_Type *)WDOG0_BASE) -/** Peripheral WDOG1 base address */ -#define WDOG1_BASE (0x41026000u) -/** Peripheral WDOG1 base pointer */ -#define WDOG1 ((WDOG_Type *)WDOG1_BASE) -/** Array initializer of WDOG peripheral base addresses */ -#define WDOG_BASE_ADDRS { WDOG0_BASE, WDOG1_BASE } -/** Array initializer of WDOG peripheral base pointers */ -#define WDOG_BASE_PTRS { WDOG0, WDOG1 } -/** Interrupt vectors for the WDOG peripheral type */ -#define WDOG_IRQS { WDOG0_IRQn, NotAvail_IRQn } -/* Extra definition */ -#define WDOG_UPDATE_KEY (0xD928C520U) -#define WDOG_REFRESH_KEY (0xB480A602U) - - -/*! - * @} - */ /* end of group WDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XRDC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer - * @{ - */ - -/** XRDC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - uint8_t RESERVED_0[236]; - __I uint32_t HWCFG0; /**< Hardware Configuration Register 0, offset: 0xF0 */ - __I uint32_t HWCFG1; /**< Hardware Configuration Register 1, offset: 0xF4 */ - __I uint32_t HWCFG2; /**< Hardware Configuration Register 2, offset: 0xF8 */ - __I uint32_t HWCFG3; /**< Hardware Configuration Register 3, offset: 0xFC */ - __I uint8_t MDACFG[37]; /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ - uint8_t RESERVED_1[27]; - __I uint8_t MRCFG[2]; /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */ - uint8_t RESERVED_2[186]; - __IO uint32_t FDID; /**< Fault Domain ID, offset: 0x1FC */ - __I uint32_t DERRLOC[3]; /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_3[500]; - __IO uint32_t DERR_W[19][4]; /**< Domain Error Word0 Register..Domain Error Word3 Register, array offset: 0x400, array step: index*0x10, index2*0x4 */ - uint8_t RESERVED_4[464]; - __IO uint32_t PID[37]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ - uint8_t RESERVED_5[108]; - struct { /* offset: 0x800, array step: 0x20 */ - __IO uint32_t MDA_W[2]; /**< Master Domain Assignment, array offset: 0x800, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[24]; - } MDA[37]; - uint8_t RESERVED_6[864]; - __IO uint32_t PDAC_W[289][2]; /**< Peripheral Domain Access Control, array offset: 0x1000, array step: index*0x8, index2*0x4 */ - uint8_t RESERVED_7[1784]; - struct { /* offset: 0x2000, array step: 0x20 */ - __IO uint32_t MRGD_W[5]; /**< Memory Region Descriptor, array offset: 0x2000, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } MRGD[24]; -} XRDC_Type; - -/* ---------------------------------------------------------------------------- - -- XRDC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XRDC_Register_Masks XRDC Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define XRDC_CR_GVLDM_MASK (0x1U) -#define XRDC_CR_GVLDM_SHIFT (0U) -/*! GVLDM - Global Valid MDACs(XRDC global enable/disable). - * 0b0..XRDC MDACs are disabled. - * 0b1..XRDC MDACs are enabled. - */ -#define XRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDM_SHIFT)) & XRDC_CR_GVLDM_MASK) -#define XRDC_CR_HRL_MASK (0x1EU) -#define XRDC_CR_HRL_SHIFT (1U) -#define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK) -#define XRDC_CR_VAW_MASK (0x100U) -#define XRDC_CR_VAW_SHIFT (8U) -/*! VAW - Virtualization aware - * 0b0..Implementation is not virtualization aware. - * 0b1..Implementation is virtualization aware. - */ -#define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK) -#define XRDC_CR_GVLDP_MASK (0x4000U) -#define XRDC_CR_GVLDP_SHIFT (14U) -/*! GVLDP - Global Valid for PACs/MSCs - * 0b0..XRDC PACs/MSCs are disabled. - * 0b1..XRDC PACs/MSCs are enabled. - */ -#define XRDC_CR_GVLDP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDP_SHIFT)) & XRDC_CR_GVLDP_MASK) -#define XRDC_CR_GVLDC_MASK (0x8000U) -#define XRDC_CR_GVLDC_SHIFT (15U) -/*! GVLDC - Global Valid for MRCs - * 0b0..XRDC MRCs are disabled. - * 0b1..XRDC MRCs are enabled. - */ -#define XRDC_CR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDC_SHIFT)) & XRDC_CR_GVLDC_MASK) -#define XRDC_CR_LK1_MASK (0x40000000U) -#define XRDC_CR_LK1_SHIFT (30U) -/*! LK1 - 1-bit Lock - * 0b0..Register can be written by any secure privileged write. - * 0b1..Register is locked (read-only) until the next reset. - */ -#define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK) -/*! @} */ - -/*! @name HWCFG0 - Hardware Configuration Register 0 */ -/*! @{ */ -#define XRDC_HWCFG0_NDID_MASK (0xFFU) -#define XRDC_HWCFG0_NDID_SHIFT (0U) -#define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK) -#define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) -#define XRDC_HWCFG0_NMSTR_SHIFT (8U) -#define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK) -#define XRDC_HWCFG0_NMRC_MASK (0xFF0000U) -#define XRDC_HWCFG0_NMRC_SHIFT (16U) -#define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK) -#define XRDC_HWCFG0_NPAC_MASK (0xF000000U) -#define XRDC_HWCFG0_NPAC_SHIFT (24U) -#define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK) -#define XRDC_HWCFG0_MID_MASK (0xF0000000U) -#define XRDC_HWCFG0_MID_SHIFT (28U) -#define XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK) -/*! @} */ - -/*! @name HWCFG1 - Hardware Configuration Register 1 */ -/*! @{ */ -#define XRDC_HWCFG1_DID_MASK (0xFU) -#define XRDC_HWCFG1_DID_SHIFT (0U) -#define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK) -/*! @} */ - -/*! @name HWCFG2 - Hardware Configuration Register 2 */ -/*! @{ */ -#define XRDC_HWCFG2_PIDP0_MASK (0x1U) -#define XRDC_HWCFG2_PIDP0_SHIFT (0U) -/*! PIDP0 - Process identifier - * 0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP0(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK) -#define XRDC_HWCFG2_PIDP1_MASK (0x2U) -#define XRDC_HWCFG2_PIDP1_SHIFT (1U) -/*! PIDP1 - Process identifier - * 0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK) -#define XRDC_HWCFG2_PIDP2_MASK (0x4U) -#define XRDC_HWCFG2_PIDP2_SHIFT (2U) -/*! PIDP2 - Process identifier - * 0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK) -#define XRDC_HWCFG2_PIDP3_MASK (0x8U) -#define XRDC_HWCFG2_PIDP3_SHIFT (3U) -/*! PIDP3 - Process identifier - * 0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP3(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK) -#define XRDC_HWCFG2_PIDP4_MASK (0x10U) -#define XRDC_HWCFG2_PIDP4_SHIFT (4U) -/*! PIDP4 - Process identifier - * 0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP4(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK) -#define XRDC_HWCFG2_PIDP5_MASK (0x20U) -#define XRDC_HWCFG2_PIDP5_SHIFT (5U) -/*! PIDP5 - Process identifier - * 0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP5(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK) -#define XRDC_HWCFG2_PIDP6_MASK (0x40U) -#define XRDC_HWCFG2_PIDP6_SHIFT (6U) -/*! PIDP6 - Process identifier - * 0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP6(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK) -#define XRDC_HWCFG2_PIDP7_MASK (0x80U) -#define XRDC_HWCFG2_PIDP7_SHIFT (7U) -/*! PIDP7 - Process identifier - * 0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP7(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK) -#define XRDC_HWCFG2_PIDP8_MASK (0x100U) -#define XRDC_HWCFG2_PIDP8_SHIFT (8U) -/*! PIDP8 - Process identifier - * 0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP8(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK) -#define XRDC_HWCFG2_PIDP9_MASK (0x200U) -#define XRDC_HWCFG2_PIDP9_SHIFT (9U) -/*! PIDP9 - Process identifier - * 0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP9(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK) -#define XRDC_HWCFG2_PIDP10_MASK (0x400U) -#define XRDC_HWCFG2_PIDP10_SHIFT (10U) -/*! PIDP10 - Process identifier - * 0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP10(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK) -#define XRDC_HWCFG2_PIDP11_MASK (0x800U) -#define XRDC_HWCFG2_PIDP11_SHIFT (11U) -/*! PIDP11 - Process identifier - * 0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP11(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK) -#define XRDC_HWCFG2_PIDP12_MASK (0x1000U) -#define XRDC_HWCFG2_PIDP12_SHIFT (12U) -/*! PIDP12 - Process identifier - * 0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP12(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK) -#define XRDC_HWCFG2_PIDP13_MASK (0x2000U) -#define XRDC_HWCFG2_PIDP13_SHIFT (13U) -/*! PIDP13 - Process identifier - * 0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP13(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK) -#define XRDC_HWCFG2_PIDP14_MASK (0x4000U) -#define XRDC_HWCFG2_PIDP14_SHIFT (14U) -/*! PIDP14 - Process identifier - * 0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP14(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK) -#define XRDC_HWCFG2_PIDP15_MASK (0x8000U) -#define XRDC_HWCFG2_PIDP15_SHIFT (15U) -/*! PIDP15 - Process identifier - * 0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP15(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK) -#define XRDC_HWCFG2_PIDP16_MASK (0x10000U) -#define XRDC_HWCFG2_PIDP16_SHIFT (16U) -/*! PIDP16 - Process identifier - * 0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP16(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK) -#define XRDC_HWCFG2_PIDP17_MASK (0x20000U) -#define XRDC_HWCFG2_PIDP17_SHIFT (17U) -/*! PIDP17 - Process identifier - * 0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP17(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK) -#define XRDC_HWCFG2_PIDP18_MASK (0x40000U) -#define XRDC_HWCFG2_PIDP18_SHIFT (18U) -/*! PIDP18 - Process identifier - * 0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP18(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK) -#define XRDC_HWCFG2_PIDP19_MASK (0x80000U) -#define XRDC_HWCFG2_PIDP19_SHIFT (19U) -/*! PIDP19 - Process identifier - * 0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP19(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK) -#define XRDC_HWCFG2_PIDP20_MASK (0x100000U) -#define XRDC_HWCFG2_PIDP20_SHIFT (20U) -/*! PIDP20 - Process identifier - * 0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP20(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK) -#define XRDC_HWCFG2_PIDP21_MASK (0x200000U) -#define XRDC_HWCFG2_PIDP21_SHIFT (21U) -/*! PIDP21 - Process identifier - * 0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP21(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK) -#define XRDC_HWCFG2_PIDP22_MASK (0x400000U) -#define XRDC_HWCFG2_PIDP22_SHIFT (22U) -/*! PIDP22 - Process identifier - * 0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP22(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK) -#define XRDC_HWCFG2_PIDP23_MASK (0x800000U) -#define XRDC_HWCFG2_PIDP23_SHIFT (23U) -/*! PIDP23 - Process identifier - * 0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP23(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK) -#define XRDC_HWCFG2_PIDP24_MASK (0x1000000U) -#define XRDC_HWCFG2_PIDP24_SHIFT (24U) -/*! PIDP24 - Process identifier - * 0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP24(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK) -#define XRDC_HWCFG2_PIDP25_MASK (0x2000000U) -#define XRDC_HWCFG2_PIDP25_SHIFT (25U) -/*! PIDP25 - Process identifier - * 0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP25(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK) -#define XRDC_HWCFG2_PIDP26_MASK (0x4000000U) -#define XRDC_HWCFG2_PIDP26_SHIFT (26U) -/*! PIDP26 - Process identifier - * 0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP26(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK) -#define XRDC_HWCFG2_PIDP27_MASK (0x8000000U) -#define XRDC_HWCFG2_PIDP27_SHIFT (27U) -/*! PIDP27 - Process identifier - * 0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP27(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK) -#define XRDC_HWCFG2_PIDP28_MASK (0x10000000U) -#define XRDC_HWCFG2_PIDP28_SHIFT (28U) -/*! PIDP28 - Process identifier - * 0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP28(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK) -#define XRDC_HWCFG2_PIDP29_MASK (0x20000000U) -#define XRDC_HWCFG2_PIDP29_SHIFT (29U) -/*! PIDP29 - Process identifier - * 0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP29(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK) -#define XRDC_HWCFG2_PIDP30_MASK (0x40000000U) -#define XRDC_HWCFG2_PIDP30_SHIFT (30U) -/*! PIDP30 - Process identifier - * 0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP30(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK) -#define XRDC_HWCFG2_PIDP31_MASK (0x80000000U) -#define XRDC_HWCFG2_PIDP31_SHIFT (31U) -/*! PIDP31 - Process identifier - * 0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP31(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK) -/*! @} */ - -/*! @name HWCFG3 - Hardware Configuration Register 3 */ -/*! @{ */ -#define XRDC_HWCFG3_PIDPn_MASK (0xFFFFFFFFU) -#define XRDC_HWCFG3_PIDPn_SHIFT (0U) -#define XRDC_HWCFG3_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDPn_SHIFT)) & XRDC_HWCFG3_PIDPn_MASK) -/*! @} */ - -/*! @name MDACFG - Master Domain Assignment Configuration Register */ -/*! @{ */ -#define XRDC_MDACFG_NMDAR_MASK (0xFU) -#define XRDC_MDACFG_NMDAR_SHIFT (0U) -#define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK) -#define XRDC_MDACFG_NCM_MASK (0x80U) -#define XRDC_MDACFG_NCM_SHIFT (7U) -/*! NCM - Non-CPU Master - * 0b0..Bus master is a processor. - * 0b1..Bus master is a non-processor. - */ -#define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK) -/*! @} */ - -/* The count of XRDC_MDACFG */ -#define XRDC_MDACFG_COUNT (37U) - -/*! @name MRCFG - Memory Region Configuration Register */ -/*! @{ */ -#define XRDC_MRCFG_NMRGD_MASK (0x1FU) -#define XRDC_MRCFG_NMRGD_SHIFT (0U) -#define XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK) -/*! @} */ - -/* The count of XRDC_MRCFG */ -#define XRDC_MRCFG_COUNT (2U) - -/*! @name FDID - Fault Domain ID */ -/*! @{ */ -#define XRDC_FDID_FDID_MASK (0xFU) -#define XRDC_FDID_FDID_SHIFT (0U) -#define XRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_FDID_FDID_SHIFT)) & XRDC_FDID_FDID_MASK) -/*! @} */ - -/*! @name DERRLOC - Domain Error Location Register */ -/*! @{ */ -#define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) -#define XRDC_DERRLOC_MRCINST_SHIFT (0U) -#define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK) -#define XRDC_DERRLOC_PACINST_MASK (0xF0000U) -#define XRDC_DERRLOC_PACINST_SHIFT (16U) -#define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK) -/*! @} */ - -/* The count of XRDC_DERRLOC */ -#define XRDC_DERRLOC_COUNT (3U) - -/*! @name DERR_W - Domain Error Word0 Register..Domain Error Word3 Register */ -/*! @{ */ -#define XRDC_DERR_W_EADDR_MASK (0xFFFFFFFFU) -#define XRDC_DERR_W_EADDR_SHIFT (0U) -#define XRDC_DERR_W_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK) -#define XRDC_DERR_W_EDID_MASK (0xFU) -#define XRDC_DERR_W_EDID_SHIFT (0U) -#define XRDC_DERR_W_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK) -#define XRDC_DERR_W_EATR_MASK (0x700U) -#define XRDC_DERR_W_EATR_SHIFT (8U) -/*! EATR - Error attributes - * 0b000..Secure user mode, instruction fetch access. - * 0b001..Secure user mode, data access. - * 0b010..Secure privileged mode, instruction fetch access. - * 0b011..Secure privileged mode, data access. - * 0b100..Nonsecure user mode, instruction fetch access. - * 0b101..Nonsecure user mode, data access. - * 0b110..Nonsecure privileged mode, instruction fetch access. - * 0b111..Nonsecure privileged mode, data access. - */ -#define XRDC_DERR_W_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK) -#define XRDC_DERR_W_ERW_MASK (0x800U) -#define XRDC_DERR_W_ERW_SHIFT (11U) -/*! ERW - Error read/write - * 0b0..Read access - * 0b1..Write access - */ -#define XRDC_DERR_W_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK) -#define XRDC_DERR_W_EPORT_MASK (0x7000000U) -#define XRDC_DERR_W_EPORT_SHIFT (24U) -#define XRDC_DERR_W_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK) -#define XRDC_DERR_W_EST_MASK (0xC0000000U) -#define XRDC_DERR_W_EST_SHIFT (30U) -/*! EST - Error state - * 0b00..No access violation has been detected. - * 0b01..No access violation has been detected. - * 0b10..A single access violation has been detected. - * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. - */ -#define XRDC_DERR_W_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK) -#define XRDC_DERR_W_RECR_MASK (0xC0000000U) -#define XRDC_DERR_W_RECR_SHIFT (30U) -#define XRDC_DERR_W_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK) -/*! @} */ - -/* The count of XRDC_DERR_W */ -#define XRDC_DERR_W_COUNT (19U) - -/* The count of XRDC_DERR_W */ -#define XRDC_DERR_W_COUNT2 (4U) - -/*! @name PID - Process Identifier */ -/*! @{ */ -#define XRDC_PID_PID_MASK (0x3FU) -#define XRDC_PID_PID_SHIFT (0U) -#define XRDC_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK) -#define XRDC_PID_SP4SM_MASK (0x8000000U) -#define XRDC_PID_SP4SM_SHIFT (27U) -#define XRDC_PID_SP4SM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_SP4SM_SHIFT)) & XRDC_PID_SP4SM_MASK) -#define XRDC_PID_TSM_MASK (0x10000000U) -#define XRDC_PID_TSM_SHIFT (28U) -#define XRDC_PID_TSM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK) -#define XRDC_PID_LK2_MASK (0x60000000U) -#define XRDC_PID_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Register can be written by any secure privileged write. - * 0b01..Register can be written by any secure privileged write. - * 0b10..Register can only be written by a secure privileged write from bus master m. - * 0b11..Register is locked (read-only) until the next reset. - */ -#define XRDC_PID_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK) -/*! @} */ - -/* The count of XRDC_PID */ -#define XRDC_PID_COUNT (37U) - -/*! @name MDA_W - Master Domain Assignment */ -/*! @{ */ -#define XRDC_MDA_W_DID_MASK (0xFU) -#define XRDC_MDA_W_DID_SHIFT (0U) -#define XRDC_MDA_W_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DID_SHIFT)) & XRDC_MDA_W_DID_MASK) -#define XRDC_MDA_W_DIDS_MASK (0x30U) -#define XRDC_MDA_W_DIDS_SHIFT (4U) -/*! DIDS - DID Select - * 0b00..Use MDAm[3:0] as the domain identifier. - * 0b01..Use the input DID as the domain identifier. - * 0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. - * 0b11..Reserved for future use. - */ -#define XRDC_MDA_W_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDS_SHIFT)) & XRDC_MDA_W_DIDS_MASK) -#define XRDC_MDA_W_PA_MASK (0x30U) -#define XRDC_MDA_W_PA_SHIFT (4U) -/*! PA - Privileged attribute - * 0b00..Force the bus attribute for this master to user. - * 0b01..Force the bus attribute for this master to privileged. - * 0b10..Use the bus master's privileged/user attribute directly. - * 0b11..Use the bus master's privileged/user attribute directly. - */ -#define XRDC_MDA_W_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PA_SHIFT)) & XRDC_MDA_W_PA_MASK) -#define XRDC_MDA_W_PE_MASK (0xC0U) -#define XRDC_MDA_W_PE_SHIFT (6U) -/*! PE - Process identifier enable - * 0b00..No process identifier is included in the domain hit evaluation. - * 0b01..No process identifier is included in the domain hit evaluation. - * 0b10..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) - * 0b11..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) - */ -#define XRDC_MDA_W_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PE_SHIFT)) & XRDC_MDA_W_PE_MASK) -#define XRDC_MDA_W_SA_MASK (0xC0U) -#define XRDC_MDA_W_SA_SHIFT (6U) -/*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. - */ -#define XRDC_MDA_W_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_SA_SHIFT)) & XRDC_MDA_W_SA_MASK) -#define XRDC_MDA_W_DIDB_MASK (0x100U) -#define XRDC_MDA_W_DIDB_SHIFT (8U) -/*! DIDB - DID Bypass - * 0b0..Use MDAn[3:0] as the domain identifier. - * 0b1..Use the DID input as the domain identifier. - */ -#define XRDC_MDA_W_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDB_SHIFT)) & XRDC_MDA_W_DIDB_MASK) -#define XRDC_MDA_W_PIDM_MASK (0x3F00U) -#define XRDC_MDA_W_PIDM_SHIFT (8U) -#define XRDC_MDA_W_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PIDM_SHIFT)) & XRDC_MDA_W_PIDM_MASK) -#define XRDC_MDA_W_PID_MASK (0x3F0000U) -#define XRDC_MDA_W_PID_SHIFT (16U) -#define XRDC_MDA_W_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PID_SHIFT)) & XRDC_MDA_W_PID_MASK) -#define XRDC_MDA_W_DFMT_MASK (0x20000000U) -#define XRDC_MDA_W_DFMT_SHIFT (29U) -/*! DFMT - Domain format - * 0b0..Processor-core domain assignment - * 0b1..Non-processor domain assignment - */ -#define XRDC_MDA_W_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DFMT_SHIFT)) & XRDC_MDA_W_DFMT_MASK) -#define XRDC_MDA_W_LK1_MASK (0x40000000U) -#define XRDC_MDA_W_LK1_SHIFT (30U) -/*! LK1 - 1-bit Lock - * 0b0..Register can be written by any secure privileged write. - * 0b1..Register is locked (read-only) until the next reset. - */ -#define XRDC_MDA_W_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_LK1_SHIFT)) & XRDC_MDA_W_LK1_MASK) -#define XRDC_MDA_W_VLD_MASK (0x80000000U) -#define XRDC_MDA_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The Wr domain assignment is invalid. - * 0b1..The Wr domain assignment is valid. - */ -#define XRDC_MDA_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_VLD_SHIFT)) & XRDC_MDA_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_MDA_W */ -#define XRDC_MDA_W_COUNT (37U) - -/* The count of XRDC_MDA_W */ -#define XRDC_MDA_W_COUNT2 (2U) - -/*! @name PDAC_W - Peripheral Domain Access Control */ -/*! @{ */ -#define XRDC_PDAC_W_D0ACP_MASK (0x7U) -#define XRDC_PDAC_W_D0ACP_SHIFT (0U) -#define XRDC_PDAC_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK) -#define XRDC_PDAC_W_D1ACP_MASK (0x38U) -#define XRDC_PDAC_W_D1ACP_SHIFT (3U) -#define XRDC_PDAC_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK) -#define XRDC_PDAC_W_D2ACP_MASK (0x1C0U) -#define XRDC_PDAC_W_D2ACP_SHIFT (6U) -#define XRDC_PDAC_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK) -#define XRDC_PDAC_W_EAL_MASK (0x3000000U) -#define XRDC_PDAC_W_EAL_SHIFT (24U) -/*! EAL - Exclusive Access Lock - * 0b00..Lock disabled - * 0b01..Lock disabled until next reset - * 0b10..Lock enabled, lock state = available - * 0b11..Lock enabled, lock state = not available - */ -#define XRDC_PDAC_W_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EAL_SHIFT)) & XRDC_PDAC_W_EAL_MASK) -#define XRDC_PDAC_W_EALO_MASK (0xF000000U) -#define XRDC_PDAC_W_EALO_SHIFT (24U) -#define XRDC_PDAC_W_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EALO_SHIFT)) & XRDC_PDAC_W_EALO_MASK) -#define XRDC_PDAC_W_LK2_MASK (0x60000000U) -#define XRDC_PDAC_W_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Entire PDACs can be written. - * 0b01..Entire PDACs can be written. - * 0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written. - * 0b11..PDACs is locked (read-only) until the next reset. - */ -#define XRDC_PDAC_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK) -#define XRDC_PDAC_W_VLD_MASK (0x80000000U) -#define XRDC_PDAC_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The PDACs assignment is invalid. - * 0b1..The PDACs assignment is valid. - */ -#define XRDC_PDAC_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_PDAC_W */ -#define XRDC_PDAC_W_COUNT (289U) - -/* The count of XRDC_PDAC_W */ -#define XRDC_PDAC_W_COUNT2 (2U) - -/*! @name MRGD_W - Memory Region Descriptor */ -/*! @{ */ -#define XRDC_MRGD_W_ACCSET1_MASK (0xFFFU) -#define XRDC_MRGD_W_ACCSET1_SHIFT (0U) -#define XRDC_MRGD_W_ACCSET1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET1_SHIFT)) & XRDC_MRGD_W_ACCSET1_MASK) -#define XRDC_MRGD_W_D0SEL_MASK (0x7U) -#define XRDC_MRGD_W_D0SEL_SHIFT (0U) -#define XRDC_MRGD_W_D0SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0SEL_SHIFT)) & XRDC_MRGD_W_D0SEL_MASK) -#define XRDC_MRGD_W_D1SEL_MASK (0x38U) -#define XRDC_MRGD_W_D1SEL_SHIFT (3U) -#define XRDC_MRGD_W_D1SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1SEL_SHIFT)) & XRDC_MRGD_W_D1SEL_MASK) -#define XRDC_MRGD_W_ENDADDR_MASK (0xFFFFFFE0U) -#define XRDC_MRGD_W_ENDADDR_SHIFT (5U) -#define XRDC_MRGD_W_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ENDADDR_SHIFT)) & XRDC_MRGD_W_ENDADDR_MASK) -#define XRDC_MRGD_W_SRTADDR_MASK (0xFFFFFFE0U) -#define XRDC_MRGD_W_SRTADDR_SHIFT (5U) -#define XRDC_MRGD_W_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRTADDR_SHIFT)) & XRDC_MRGD_W_SRTADDR_MASK) -#define XRDC_MRGD_W_D2SEL_MASK (0x1C0U) -#define XRDC_MRGD_W_D2SEL_SHIFT (6U) -#define XRDC_MRGD_W_D2SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2SEL_SHIFT)) & XRDC_MRGD_W_D2SEL_MASK) -#define XRDC_MRGD_W_LKAS1_MASK (0x1000U) -#define XRDC_MRGD_W_LKAS1_SHIFT (12U) -/*! LKAS1 - Lock ACCSET1 - * 0b0..Writes to ACCSET1 affect lesser modes - * 0b1..ACCSET1 cannot be modified - */ -#define XRDC_MRGD_W_LKAS1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS1_SHIFT)) & XRDC_MRGD_W_LKAS1_MASK) -#define XRDC_MRGD_W_ACCSET2_MASK (0xFFF0000U) -#define XRDC_MRGD_W_ACCSET2_SHIFT (16U) -#define XRDC_MRGD_W_ACCSET2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET2_SHIFT)) & XRDC_MRGD_W_ACCSET2_MASK) -#define XRDC_MRGD_W_EAL_MASK (0x3000000U) -#define XRDC_MRGD_W_EAL_SHIFT (24U) -/*! EAL - Exclusive Access Lock - * 0b00..Lock disabled - * 0b01..Lock disabled until next reset - * 0b10..Lock enabled, lock state = available - * 0b11..Lock enabled, lock state = not available - */ -#define XRDC_MRGD_W_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EAL_SHIFT)) & XRDC_MRGD_W_EAL_MASK) -#define XRDC_MRGD_W_EALO_MASK (0xF000000U) -#define XRDC_MRGD_W_EALO_SHIFT (24U) -#define XRDC_MRGD_W_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EALO_SHIFT)) & XRDC_MRGD_W_EALO_MASK) -#define XRDC_MRGD_W_LKAS2_MASK (0x10000000U) -#define XRDC_MRGD_W_LKAS2_SHIFT (28U) -/*! LKAS2 - Lock ACCSET2 - * 0b0..Writes to ACCSET2 affect lesser modes - * 0b1..ACCSET2 cannot be modified - */ -#define XRDC_MRGD_W_LKAS2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS2_SHIFT)) & XRDC_MRGD_W_LKAS2_MASK) -#define XRDC_MRGD_W_LK2_MASK (0x60000000U) -#define XRDC_MRGD_W_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Entire MRGDn can be written. - * 0b01..Entire MRGDn can be written. - * 0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written. - * 0b11..MRGDn is locked (read-only) until the next reset. - */ -#define XRDC_MRGD_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK) -#define XRDC_MRGD_W_CR_MASK (0x80000000U) -#define XRDC_MRGD_W_CR_SHIFT (31U) -#define XRDC_MRGD_W_CR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_CR_SHIFT)) & XRDC_MRGD_W_CR_MASK) -#define XRDC_MRGD_W_VLD_MASK (0x80000000U) -#define XRDC_MRGD_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The MRGDn assignment is invalid. - * 0b1..The MRGDn assignment is valid. - */ -#define XRDC_MRGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_MRGD_W */ -#define XRDC_MRGD_W_COUNT (24U) - -/* The count of XRDC_MRGD_W */ -#define XRDC_MRGD_W_COUNT2 (5U) - - -/*! - * @} - */ /* end of group XRDC_Register_Masks */ - - -/* XRDC - Peripheral instance base addresses */ -/** Peripheral XRDC base address */ -#define XRDC_BASE (0x40014000u) -/** Peripheral XRDC base pointer */ -#define XRDC ((XRDC_Type *)XRDC_BASE) -/** Array initializer of XRDC peripheral base addresses */ -#define XRDC_BASE_ADDRS { XRDC_BASE } -/** Array initializer of XRDC peripheral base pointers */ -#define XRDC_BASE_PTRS { XRDC } - -/*! - * @} - */ /* end of group XRDC_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -#define EVENT_UNIT EVENT0 -#define INTMUX INTMUX0 - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _RV32M1_RI5CY_H_ */ - diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h deleted file mode 100644 index 6e68f8a85f2c2de27c405e26aa4ff2c64779e723..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h +++ /dev/null @@ -1,1561 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2018-10-02 -** Build: b180815 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _RV32M1_ri5cy_FEATURES_H_ -#define _RV32M1_ri5cy_FEATURES_H_ - -/* SOC module features */ - -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (1) -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (1) -/* @brief EVENT availability on the SoC. */ -#define FSL_FEATURE_SOC_EVENT_COUNT (1) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (1) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (5) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (1) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (1) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (2) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (2) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (1) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (2) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (3) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (4) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (1) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (2) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (5) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (1) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (2) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (2) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (1) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (4) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (2) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (1) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (1) -/* @brief USDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_USDHC_COUNT (1) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (1) - -/* LPADC module features */ - -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) - -/* AXBS module features */ - -/* No feature definitions */ - -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) -/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ -#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) - -/* EWM module features */ - -/* @brief Has clock select (register CLKCTRL). */ -#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) -/* @brief Has clock prescaler (register CLKPRESCALER). */ -#define FSL_FEATURE_EWM_HAS_PRESCALER (1) - -/* FB module features */ - -/* No feature definitions */ - -/* FLEXIO module features */ - -/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ -#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) -/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) -/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) -/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) -/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) -/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) -/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ -#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) -/* @brief Reset value of the FLEXIO_VERID register */ -#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) -/* @brief Reset value of the FLEXIO_PARAM register */ -#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) - -/* FLASH module features */ - -/* @brief Current core ID. */ -#define FSL_FEATURE_FLASH_CURRENT_CORE_ID (0) -/* @brief Is of type FTFA. */ -#define FSL_FEATURE_FLASH_IS_FTFA (0) -/* @brief Is of type FTFE. */ -#define FSL_FEATURE_FLASH_IS_FTFE (1) -/* @brief Is of type FTFL. */ -#define FSL_FEATURE_FLASH_IS_FTFL (0) -/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) -/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) -/* @brief Has EEPROM region protection (register FEPROT). */ -#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) -/* @brief Has data flash region protection (register FDPROT). */ -#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) -/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ -#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) -/* @brief Has flash cache control in FMC module. */ -#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) -/* @brief Has flash cache control in MCM module. */ -#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) -/* @brief Has flash cache control in MSCM module. */ -#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1) -/* @brief Has prefetch speculation control in flash, such as kv5x. */ -#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) -/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for RV32M1. */ -#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1) -/* @brief P-Flash start address. */ -#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) -/* @brief P-Flash block count. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) -/* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) -/* @brief P-Flash sector size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) -/* @brief P-Flash write unit size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) -/* @brief P-Flash data path width. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) -/* @brief P-Flash block swap feature. */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) -/* @brief P-Flash protection region count. */ -#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (64) -/* @brief Has multiple flash. */ -#define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1) -/* @brief Flash memory count. */ -#define FSL_FEATURE_FLASH_MEMORY_COUNT (2) -/* @brief P-Flash start address. */ -#define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x01000000) -/* @brief P-Flash block count. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (1) -/* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (262144) -/* @brief P-Flash sector size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (2048) -/* @brief P-Flash write unit size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8) -/* @brief P-Flash data path width. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (8) -/* @brief P-Flash protection region count. */ -#define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (16) -/* @brief P-Flash block swap feature. */ -#define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (0) -/* @brief Has FlexNVM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) -/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) -/* @brief FlexNVM block count. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) -/* @brief FlexNVM block size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) -/* @brief FlexNVM sector size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) -/* @brief FlexNVM write unit size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) -/* @brief FlexNVM data path width. */ -#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) -/* @brief Has FlexRAM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) -/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000) -/* @brief FlexRAM size. */ -#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) -/* @brief Has 0x00 Read 1s Block command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) -/* @brief Flash 1 has 0x00 Read 1s Block command. */ -#define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (0) -/* @brief Has 0x01 Read 1s Section command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) -/* @brief Has 0x02 Program Check command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) -/* @brief Has 0x03 Read Resource command. */ -#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0) -/* @brief Has 0x06 Program Longword command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) -/* @brief Has 0x07 Program Phrase command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) -/* @brief Has 0x08 Erase Flash Block command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) -/* @brief Flash 1 has 0x08 Erase Flash Block command. */ -#define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (0) -/* @brief Has 0x09 Erase Flash Sector command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) -/* @brief Has 0x0B Program Section command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) -/* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */ -#define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1) -/* @brief Has 0x40 Read 1s All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) -/* @brief Has 0x41 Read Once command. */ -#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) -/* @brief Has 0x43 Program Once command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) -/* @brief Has 0x44 Erase All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) -/* @brief Has 0x45 Verify Backdoor Access Key command. */ -#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) -/* @brief Has 0x46 Swap Control command. */ -#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) -/* @brief Flash 1 has 0x46 Swap Control command. */ -#define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (0) -/* @brief Has 0x49 Erase All Blocks Unsecure command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) -/* @brief Has 0x4A Read 1s All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x4B Erase All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x80 Program Partition command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) -/* @brief Has 0x81 Set FlexRAM Function command. */ -#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) -/* @brief P-Flash Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Program/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Program/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash 1 Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Rrogram/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Program check command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) -/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) -/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) -/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) -/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) -/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) -/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) -/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) -/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) -/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) -/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) -/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) -/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) -/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) -/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) -/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) -/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* SAI module features */ - -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ -#define FSL_FEATURE_SAI_FIFO_COUNT (8) -/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ -#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ -#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ -#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ -#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ -#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Interrupt source number */ -#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) -/* @brief Has register of MCR. */ -#define FSL_FEATURE_SAI_HAS_MCR (0) -/* @brief Has bit field MICS of the MCR register. */ -#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) -/* @brief Has register of MDR */ -#define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ -#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) - -/* INTMUX module features */ - -/* @brief Number of INTMUX channels (related to number of register CHn_CSR). */ -#define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8) -/* @brief Number of INTMUX IRQ source. */ -#define FSL_FEATURE_INTMUX_IRQ_COUNT (32) -/* @brief The start IRQ index of first INTMUX source IRQ. */ -#define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32) -/* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */ -#define FSL_FEATURE_INTMUX_DIRECTION_OUT (0) -/* @brief The total number of level1 interrupt vectors. */ -#define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32) - -/* LLWU module features */ - -/* @brief Maximum number of pins connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32) -/* @brief Maximum number of internal modules connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) -/* @brief Number of digital filters. */ -#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) -/* @brief Has MF register. */ -#define FSL_FEATURE_LLWU_HAS_MF (0) -/* @brief Has PF register. */ -#define FSL_FEATURE_LLWU_HAS_PF (1) -/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ -#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -/* @brief Has no internal module wakeup flag register. */ -#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1) -/* @brief Has external pin 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) -/* @brief Has external pin 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) -/* @brief Has external pin 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22) -/* @brief Has external pin 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30) -/* @brief Has external pin 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1) -/* @brief Has external pin 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2) -/* @brief Has external pin 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4) -/* @brief Has external pin 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6) -/* @brief Has external pin 8 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7) -/* @brief Has external pin 9 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8) -/* @brief Has external pin 10 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16) -/* @brief Has external pin 11 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20) -/* @brief Has external pin 12 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22) -/* @brief Has external pin 13 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25) -/* @brief Has external pin 14 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28) -/* @brief Has external pin 15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) -/* @brief Has external pin 16 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9) -/* @brief Has external pin 17 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11) -/* @brief Has external pin 18 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12) -/* @brief Has external pin 19 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8) -/* @brief Has external pin 20 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10) -/* @brief Has external pin 21 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1) -/* @brief Has external pin 22 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3) -/* @brief Has external pin 23 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8) -/* @brief Has external pin 24 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9) -/* @brief Has external pin 25 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10) -/* @brief Has external pin 26 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12) -/* @brief Has external pin 27 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) -/* @brief Has external pin 28 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) -/* @brief Has external pin 29 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) -/* @brief Has external pin 30 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) -/* @brief Has external pin 31 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) -/* @brief Has internal module 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) -/* @brief Has internal module 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) -/* @brief Has internal module 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) -/* @brief Has internal module 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) -/* @brief Has internal module 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) -/* @brief Has internal module 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) -/* @brief Has internal module 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1) -/* @brief Has internal module 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) -/* @brief Has LLWU_VERID. */ -#define FSL_FEATURE_LLWU_HAS_VERID (1) -/* @brief Has LLWU_PARAM. */ -#define FSL_FEATURE_LLWU_HAS_PARAM (1) -/* @brief LLWU register bit width. */ -#define FSL_FEATURE_LLWU_REG_BITWIDTH (32) -/* @brief Has DMA Enable register LLWU_DE. */ -#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1) - -/* LPDAC module features */ - -/* @brief FIFO size. */ -#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) - -/* LPI2C module features */ - -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) - -/* LPIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_LPIT_TIMER_COUNT (4) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_LPIT_HAS_CHAIN_MODE (0) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0) - -/* LPSPI module features */ - -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) - -/* LPUART module features */ - -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (1) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (1) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (1) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (1) - -/* MCM module features */ - -/* @brief Has L1 cache. */ -#define FSL_FEATURE_HAS_L1CACHE (1) - -/* MSCM module features */ - -/* @brief Number of configuration information for processors. */ -#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2) -/* @brief Has data cache. */ -#define FSL_FEATURE_MSCM_HAS_DATACACHE (0) - -/* MU module features */ - -/* @brief MU side for current core */ -#define FSL_FEATURE_MU_SIDE_A (1) -/* @brief MU Has register CCR */ -#define FSL_FEATURE_MU_HAS_CCR (1) -/* @brief MU Has register SR[RS], BSR[ARS] */ -#define FSL_FEATURE_MU_HAS_SR_RS (0) -/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ -#define FSL_FEATURE_MU_HAS_RESET_INT (1) -/* @brief MU Has register SR[MURIP] */ -#define FSL_FEATURE_MU_HAS_SR_MURIP (1) -/* @brief brief MU Has register SR[HRIP] */ -#define FSL_FEATURE_MU_HAS_SR_HRIP (1) -/* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ -#define FSL_FEATURE_MU_NO_CLKE (0) -/* @brief brief MU does not support NMI, CR[NMI]. */ -#define FSL_FEATURE_MU_NO_NMI (0) -/* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ -#define FSL_FEATURE_MU_NO_RSTH (0) -/* @brief brief MU does not supports MU reset, CR[MUR]. */ -#define FSL_FEATURE_MU_NO_MUR (0) -/* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ -#define FSL_FEATURE_MU_NO_HR (0) -/* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ -#define FSL_FEATURE_MU_HAS_HRM (1) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PCC module features */ - -/* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */ -#define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) -/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has independent interrupt control(register ICR). */ -#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1) - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (1) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (1) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (1) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (1) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) -/* @brief Has Tamper Interrupt Register (register TIR). */ -#define FSL_FEATURE_RTC_HAS_TIR (1) -/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_TPIE (1) -/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_SIE (1) -/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_LCIE (1) -/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ -#define FSL_FEATURE_RTC_HAS_SR_TIDF (1) -/* @brief Has Tamper Detect Register (register TDR). */ -#define FSL_FEATURE_RTC_HAS_TDR (1) -/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_TPF (1) -/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_STF (1) -/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_LCTF (1) -/* @brief Has Tamper Time Seconds Register (register TTSR). */ -#define FSL_FEATURE_RTC_HAS_TTSR (1) -/* @brief Has Pin Configuration Register (register PCR). */ -#define FSL_FEATURE_RTC_HAS_PCR (1) -/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) - -/* SCG module features */ - -/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ -#define FSL_FEATURE_SCG_HAS_DIVPLAT (0) -/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ -#define FSL_FEATURE_SCG_HAS_DIVBUS (1) -/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ -#define FSL_FEATURE_SCG_HAS_DIVEXT (1) -/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ -#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) -/* @brief Has SOSCCSR[SOSCERCLKEN]. */ -#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0) -/* @brief Has OSC freq range SOSCCFG[RANGE]. */ -#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0) -/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ -#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) -/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1) -/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1) -/* @brief Has SCG_SIRCCSR[LPOPO]. */ -#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) -/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1) -/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ -#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) -/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ -#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) -/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) -/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ -#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) -/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ -#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) -/* @brief Has SCG_SPLLCFG[PLLS]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) -/* @brief Has SCG_SPLLCFG[BYPASS]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) -/* @brief Has SCG_SPLLCFG[PFDSEL]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) -/* @brief Has SCG_SPLLCSR[SPLLCM]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) -/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ -#define FSL_FEATURE_SCG_HAS_FLLDIV3 (1) -/* @brief Has low power FLL, SCG_LPFLLCSR. */ -#define FSL_FEATURE_SCG_HAS_LPFLL (1) -/* @brief Has system PLL, SCG_SPLLCSR. */ -#define FSL_FEATURE_SCG_HAS_SPLL (0) -/* @brief Has system PLL PFD, SCG_SPLLPFD. */ -#define FSL_FEATURE_SCG_HAS_SPLLPFD (0) -/* @brief Has auxiliary PLL, SCG_APLLCSR. */ -#define FSL_FEATURE_SCG_HAS_APLL (0) -/* @brief Has RTC OSC control, SCG_ROSCCSR. */ -#define FSL_FEATURE_SCG_HAS_ROSC (1) -/* @brief Has RTC OSC clock source. */ -#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1) -/* @brief Has RTC OSC clock out select. */ -#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1) -/* @brief Has EXTERNAL clock out select. */ -#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1) -/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1) -/* @brief Has no SCG_SOSCCSR[SOSCEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (0) -/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (0) -/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (0) -/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */ -#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0) -/* @brief Has FIRC trim source USB0 Start of Frame. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) -/* @brief Has FIRC trim source USB1 Start of Frame. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) -/* @brief Has FIRC trim source system OSC. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) -/* @brief Has FIRC trim source RTC OSC. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1) - -/* SEMA42 module features */ - -/* @brief Gate counts */ -#define FSL_FEATURE_SEMA42_GATE_COUNT (16) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) -/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */ -#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1) -/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1) -/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1) -/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (0) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) -/* @brief Has MISCCTRL reg. */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL (0) -/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0) -/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0) -/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0) -/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0) -/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0) -/* @brief Has SECKEY0 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY0 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */ -#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0) -/* @brief Has SECKEY1 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY1 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */ -#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0) -/* @brief Has SECKEY2 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY2 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */ -#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0) -/* @brief Has SECKEY3 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY3 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */ -#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0) -/* @brief Has no SDID reg. */ -#define FSL_FEATURE_SIM_HAS_NO_SDID (0) -/* @brief Has no UID reg. */ -#define FSL_FEATURE_SIM_HAS_NO_UID (0) -/* @brief Has RFADDRL and RFADDRH registers. */ -#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (1) -/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */ -#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1) -/* @brief Has UIDM registers. */ -#define FSL_FEATURE_SIM_HAS_UIDM (1) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (0) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (0) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (1) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (1) -/* @brief Has SMC_CSRE. */ -#define FSL_FEATURE_SMC_HAS_CSRE (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) -/* @brief Has security violation reset (register bit SRS[VBAT]). */ -#define FSL_FEATURE_SMC_HAS_SRS_VBAT (0) -/* @brief Has security violation reset (register bit SRS[CORE0]). */ -#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1) -/* @brief Has security violation reset (register bit SRS[CORE1]). */ -#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1) -/* @brief Has security violation reset (register bit SRIE[VBAT]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0) -/* @brief Has security violation reset (register bit SRIE[CORE0]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1) -/* @brief Has security violation reset (register bit SRIE[CORE1]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (6) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (6) : \ - ((x) == TPM3 ? (2) : (-1))))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (1) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (1) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (1) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (1) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) - -/* TRGMUX module features */ - -/* No feature definitions */ - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSTMR module features */ - -/* @brief TSTMR clock frequency is 1MHZ. */ -#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1) - -/* USB module features */ - -/* @brief KHCI module instance count */ -#define FSL_FEATURE_USB_KHCI_COUNT (1) -/* @brief HOST mode enabled */ -#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) -/* @brief OTG mode enabled */ -#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088) -/* @brief Has KEEP_ALIVE_CTRL register */ -#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) -/* @brief Mode control of the USB Keep Alive */ -#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) -/* @brief Has the Dynamic SOF threshold compare support */ -#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) -/* @brief Has the VBUS detect support */ -#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) -/* @brief Has the IRC48M module clock support */ -#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) -/* @brief Number of endpoints supported */ -#define FSL_FEATURE_USB_ENDPT_COUNT (16) -/* @brief Has STALL_IL/OL_DIS registers */ -#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) -/* @brief Has STALL_IH/OH_DIS registers */ -#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) - -/* USDHC module features */ - -/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ -#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) -/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ -#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) -/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0) -/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (1) - -/* WDOG module features */ - -/* @brief Watchdog is available. */ -#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) -/* @brief WDOG_CNT can be 32-bit written. */ -#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) - -/* XRDC module features */ - -/* @brief Does not have global valid (register bit CR[GVLD]). */ -#define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1) -/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */ -#define FSL_FEATURE_XRDC_HAS_FDID (1) -/* @brief Has special 4-state model option (register bit PID[SP4SM]). */ -#define FSL_FEATURE_XRDC_PID_SP4SM (1) -/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */ -#define FSL_FEATURE_XRDC_NO_MDA_LPID (1) -/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */ -#define FSL_FEATURE_XRDC_NO_MDA_LPE (1) -/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */ -#define FSL_FEATURE_XRDC_NO_PDAC_SE (1) -/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */ -#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1) -/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */ -#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1) -/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */ -#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1) -/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1) -/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SE (1) -/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1) -/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1) -/* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SZ (1) -/* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SRD (1) -/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1) -/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1) -/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1) -/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1) -/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1) -/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_CR (1) -/* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1) -/* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1) -/* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1) -/* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1) -/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */ -#define FSL_FEATURE_XRDC_DOMAIN_COUNT (3) - -#endif /* _RV32M1_ri5cy_FEATURES_H_ */ - diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h deleted file mode 100644 index 55b369ad5a0d970db3aa73f251d194ba0c9c01a2..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h +++ /dev/null @@ -1,32675 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_zero_riscy -** RV32M1_zero_riscy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** CMSIS Peripheral Access Layer for RV32M1_zero_riscy -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_zero_riscy.h - * @version 1.0 - * @date 2018-10-02 - * @brief CMSIS Peripheral Access Layer for RV32M1_zero_riscy - * - * CMSIS Peripheral Access Layer for RV32M1_zero_riscy - */ - -#ifndef _RV32M1_CM0PLUS_H_ -#define _RV32M1_CM0PLUS_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Device specific interrupts */ - CTI1_IRQn = 0, /**< Cross Trigger Interface 1 */ - DMA1_04_IRQn = 1, /**< DMA1 channel 0/4 transfer complete */ - DMA1_15_IRQn = 2, /**< DMA1 channel 1/5 transfer complete */ - DMA1_26_IRQn = 3, /**< DMA1 channel 2/6 transfer complete */ - DMA1_37_IRQn = 4, /**< DMA1 channel 3/7 transfer complete */ - DMA1_Error_IRQn = 5, /**< DMA1 channel 0-7 error interrupt */ - CMC1_IRQn = 6, /**< Core Mode Controller 1 */ - LLWU1_IRQn = 7, /**< Low leakage wakeup 1 */ - MUB_IRQn = 8, /**< MU Side B interrupt */ - WDOG1_IRQn = 9, /**< WDOG1 interrupt */ - CAU3_Task_Complete_IRQn = 10, /**< Cryptographic Acceleration Unit version 3 Task Complete */ - CAU3_Security_Violation_IRQn = 11, /**< Cryptographic Acceleration Unit version 3 Security Violation */ - TRNG_IRQn = 12, /**< TRNG interrupt */ - LPIT1_IRQn = 13, /**< LPIT1 interrupt */ - LPTMR2_IRQn = 14, /**< LPTMR2 interrupt */ - TPM3_IRQn = 15, /**< TPM3 single interrupt vector for all sources */ - LPI2C3_IRQn = 16, /**< LPI2C3 interrupt */ - RF0_0_IRQn = 17, /**< RF0 interrupt 0 */ - RF0_1_IRQn = 18, /**< RF0 interrupt 1 */ - LPSPI3_IRQn = 19, /**< LPSPI3 single interrupt vector for all sources */ - LPUART3_IRQn = 20, /**< LPUART3 status and error */ - PORTE_IRQn = 21, /**< PORTE Pin detect */ - LPCMP1_IRQn = 22, /**< LPCMP1 interrupt */ - RTC_IRQn = 23, /**< RTC */ - INTMUX1_0_IRQn = 24, /**< INTMUX1 channel0 interrupt */ - INTMUX1_1_IRQn = 25, /**< INTMUX1 channel1 interrupt */ - INTMUX1_2_IRQn = 26, /**< INTMUX1 channel2 interrupt */ - INTMUX1_3_IRQn = 27, /**< INTMUX1 channel3 interrupt */ - INTMUX1_4_IRQn = 28, /**< INTMUX1 channel4 interrupt */ - INTMUX1_5_IRQn = 29, /**< INTMUX1 channel5 interrupt */ - INTMUX1_6_IRQn = 30, /**< INTMUX1 channel6 interrupt */ - INTMUX1_7_IRQn = 31, /**< INTMUX1 channel7 interrupt */ - EWM_IRQn = 32, /**< EWM interrupt (INTMUX1 source IRQ0) */ - FTFE_Command_Complete_IRQn = 33, /**< FTFE interrupt (INTMUX1 source IRQ1) */ - FTFE_Read_Collision_IRQn = 34, /**< FTFE interrupt (INTMUX1 source IRQ2) */ - SPM_IRQn = 35, /**< SPM (INTMUX1 source IRQ3) */ - SCG_IRQn = 36, /**< SCG interrupt (INTMUX1 source IRQ4) */ - LPIT0_IRQn = 37, /**< LPIT0 interrupt (INTMUX1 source IRQ5) */ - LPTMR0_IRQn = 38, /**< LPTMR0 interrupt (INTMUX1 source IRQ6) */ - LPTMR1_IRQn = 39, /**< LPTMR1 interrupt (INTMUX1 source IRQ7) */ - TPM0_IRQn = 40, /**< TPM0 single interrupt vector for all sources (INTMUX1 source IRQ8) */ - TPM1_IRQn = 41, /**< TPM1 single interrupt vector for all sources (INTMUX1 source IRQ9) */ - TPM2_IRQn = 42, /**< TPM2 single interrupt vector for all sources (INTMUX1 source IRQ10) */ - EMVSIM0_IRQn = 43, /**< EMVSIM0 interrupt (INTMUX1 source IRQ11) */ - FLEXIO0_IRQn = 44, /**< FLEXIO0 (INTMUX1 source IRQ12) */ - LPI2C0_IRQn = 45, /**< LPI2C0 interrupt (INTMUX1 source IRQ13) */ - LPI2C1_IRQn = 46, /**< LPI2C1 interrupt (INTMUX1 source IRQ14) */ - LPI2C2_IRQn = 47, /**< LPI2C2 interrupt (INTMUX1 source IRQ15) */ - I2S0_IRQn = 48, /**< I2S0 interrupt (INTMUX1 source IRQ16) */ - USDHC0_IRQn = 49, /**< SDHC0 interrupt (INTMUX1 source IRQ17) */ - LPSPI0_IRQn = 50, /**< LPSPI0 single interrupt vector for all sources (INTMUX1 source IRQ18) */ - LPSPI1_IRQn = 51, /**< LPSPI1 single interrupt vector for all sources (INTMUX1 source IRQ19) */ - LPSPI2_IRQn = 52, /**< LPSPI2 single interrupt vector for all sources (INTMUX1 source IRQ20) */ - LPUART0_IRQn = 53, /**< LPUART0 status and error (INTMUX1 source IRQ21) */ - LPUART1_IRQn = 54, /**< LPUART1 status and error (INTMUX1 source IRQ22) */ - LPUART2_IRQn = 55, /**< LPUART2 status and error (INTMUX1 source IRQ23) */ - USB0_IRQn = 56, /**< USB0 interrupt (INTMUX1 source IRQ24) */ - PORTA_IRQn = 57, /**< PORTA Pin detect (INTMUX1 source IRQ25) */ - PORTB_IRQn = 58, /**< PORTB Pin detect (INTMUX1 source IRQ26) */ - PORTC_IRQn = 59, /**< PORTC Pin detect (INTMUX1 source IRQ27) */ - PORTD_IRQn = 60, /**< PORTD Pin detect (INTMUX1 source IRQ28) */ - ADC0_IRQn = 61, /**< LPADC0 interrupt (INTMUX1 source IRQ29) */ - LPCMP0_IRQn = 62, /**< LPCMP0 interrupt (INTMUX1 source IRQ30) */ - LPDAC0_IRQn = 63 /**< DAC0 interrupt (INTMUX1 source IRQ31) */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_riscv32.h" /* Core Peripheral Access Layer */ -#include "system_RV32M1_zero_riscy.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup edma_request - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the DMA hardware request - * - * Defines the enumeration for the DMA hardware request collections. - */ -typedef enum _dma_request_source -{ - kDmaRequestMux1LLWU1 = 0|0x200U, /**< LLWU1 Wakeup */ - kDmaRequestMux1CAEv3 = 1|0x200U, /**< CAEv3 Data Request */ - kDmaRequestMux1LPTMR2 = 2|0x200U, /**< LPTMR2 Trigger */ - kDmaRequestMux1TPM3Channel0 = 3|0x200U, /**< TPM3 Channel 0 */ - kDmaRequestMux1TPM3Channel1 = 4|0x200U, /**< TPM3 Channel 1 */ - kDmaRequestMux1TPM3Overflow = 5|0x200U, /**< TPM3 Overflow */ - kDmaRequestMux1LPI2C3Rx = 6|0x200U, /**< LPI2C3 Receive */ - kDmaRequestMux1LPI2C3Tx = 7|0x200U, /**< LPI2C3 Transmit */ - kDmaRequestMux1RF0Rx = 8|0x200U, /**< 2.4GHz Radio 0 Receive */ - kDmaRequestMux1LPSPI3Rx = 9|0x200U, /**< LPSPI3 Receive */ - kDmaRequestMux1LPSPI3Tx = 10|0x200U, /**< LPSPI3 Transmit */ - kDmaRequestMux1LPUART3Rx = 11|0x200U, /**< LPUART3 Receive */ - kDmaRequestMux1LPUART3Tx = 12|0x200U, /**< LPUART3 Transmit */ - kDmaRequestMux1PORTE = 13|0x200U, /**< PORTE Pin Request */ - kDmaRequestMux1LPCMP1 = 14|0x200U, /**< LPCMP1 Comparator Trigger */ - kDmaRequestMux1LPTMR1 = 15|0x200U, /**< LPTMR1 Trigger */ - kDmaRequestMux1FLEXIO0Channel0 = 16|0x200U, /**< FLEXIO0 Channel 0 */ - kDmaRequestMux1FLEXIO0Channel1 = 17|0x200U, /**< FLEXIO0 Channel 1 */ - kDmaRequestMux1FLEXIO0Channel2 = 18|0x200U, /**< FLEXIO0 Channel 2 */ - kDmaRequestMux1FLEXIO0Channel3 = 19|0x200U, /**< FLEXIO0 Channel 3 */ - kDmaRequestMux1FLEXIO0Channel4 = 20|0x200U, /**< FLEXIO0 Channel 4 */ - kDmaRequestMux1FLEXIO0Channel5 = 21|0x200U, /**< FLEXIO0 Channel 5 */ - kDmaRequestMux1FLEXIO0Channel6 = 22|0x200U, /**< FLEXIO0 Channel 6 */ - kDmaRequestMux1FLEXIO0Channel7 = 23|0x200U, /**< FLEXIO0 Channel 7 */ - kDmaRequestMux1I2S0Rx = 24|0x200U, /**< I2S0 Receive */ - kDmaRequestMux1I2S0Tx = 25|0x200U, /**< I2S0 Transmit */ - kDmaRequestMux1PORTA = 26|0x200U, /**< PORTA Pin Request */ - kDmaRequestMux1PORTB = 27|0x200U, /**< PORTB Pin Request */ - kDmaRequestMux1PORTC = 28|0x200U, /**< PORTC Pin Request */ - kDmaRequestMux1PORTD = 29|0x200U, /**< PORTD Pin Request */ - kDmaRequestMux1LPADC0 = 30|0x200U, /**< LPADC0 Conversion Complete */ - kDmaRequestMux1DAC0 = 31|0x200U, /**< DAC0 Conversion Complete */ -} dma_request_source_t; - -/* @} */ - -/*! - * @addtogroup trgmux_source - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the TRGMUX source - * - * Defines the enumeration for the TRGMUX source collections. - */ -typedef enum _trgmux_source -{ - kTRGMUX_Source0Disabled = 0U, /**< Trigger function is disabled */ - kTRGMUX_Source1Disabled = 0U, /**< Trigger function is disabled */ - kTRGMUX_Source0Llwu0 = 1U, /**< LLWU0 trigger is selected */ - kTRGMUX_Source1Llwu1 = 1U, /**< LLWU1 trigger is selected */ - kTRGMUX_Source0Lpit0Channel0 = 2U, /**< LPIT0 Channel 0 is selected */ - kTRGMUX_Source1Lpit1Channel0 = 2U, /**< LPIT1 Channel 0 is selected */ - kTRGMUX_Source0Lpit0Channel1 = 3U, /**< LPIT0 Channel 1 is selected */ - kTRGMUX_Source1Lpit1Channel1 = 3U, /**< LPIT1 Channel 1 is selected */ - kTRGMUX_Source0Lpit0Channel2 = 4U, /**< LPIT0 Channel 2 is selected */ - kTRGMUX_Source1Lpit1Channel2 = 4U, /**< LPIT1 Channel 2 is selected */ - kTRGMUX_Source0Lpit0Channel3 = 5U, /**< LPIT0 Channel 3 is selected */ - kTRGMUX_Source1Lpit1Channel3 = 5U, /**< LPIT1 Channel 3 is selected */ - kTRGMUX_Source0RtcAlarm = 6U, /**< RTC Alarm is selected */ - kTRGMUX_Source1Lptmr2Trigger = 6U, /**< LPTMR2 Trigger is selected */ - kTRGMUX_Source0RtcSeconds = 7U, /**< RTC Seconds is selected */ - kTRGMUX_Source1Tpm3ChannelEven = 7U, /**< TPM3 Channel Even is selected */ - kTRGMUX_Source0Lptmr0Trigger = 8U, /**< LPTMR0 Trigger is selected */ - kTRGMUX_Source1Tpm3ChannelOdd = 8U, /**< TPM3 Channel Odd is selected */ - kTRGMUX_Source0Lptmr1Trigger = 9U, /**< LPTMR1 Trigger is selected */ - kTRGMUX_Source1Tpm3Overflow = 9U, /**< TPM3 Overflow is selected */ - kTRGMUX_Source0Tpm0ChannelEven = 10U, /**< TPM0 Channel Even is selected */ - kTRGMUX_Source1Lpi2c3MasterStop = 10U, /**< LPI2C3 Master Stop is selected */ - kTRGMUX_Source0Tpm0ChannelOdd = 11U, /**< TPM0 Channel Odd is selected */ - kTRGMUX_Source1Lpi2c3SlaveStop = 11U, /**< LPI2C3 Slave Stop is selected */ - kTRGMUX_Source0Tpm0Overflow = 12U, /**< TPM0 Overflow is selected */ - kTRGMUX_Source1Lpspi3Frame = 12U, /**< LPSPI3 Frame is selected */ - kTRGMUX_Source0Tpm1ChannelEven = 13U, /**< TPM1 Channel Even is selected */ - kTRGMUX_Source1Lpspi3RX = 13U, /**< LPSPI3 Rx is selected */ - kTRGMUX_Source0Tpm1ChannelOdd = 14U, /**< TPM1 Channel Odd is selected */ - kTRGMUX_Source1Lpuart3RxData = 14U, /**< LPUART3 Rx Data is selected */ - kTRGMUX_Source0Tpm1Overflow = 15U, /**< TPM1 Overflow is selected */ - kTRGMUX_Source1Lpuart3RxIdle = 15U, /**< LPUART3 Rx Idle is selected */ - kTRGMUX_Source0Tpm2ChannelEven = 16U, /**< TPM2 Channel Even is selected */ - kTRGMUX_Source1Lpuart3TxData = 16U, /**< LPUART3 Tx Data is selected */ - kTRGMUX_Source0Tpm2ChannelOdd = 17U, /**< TPM2 Channel Odd is selected */ - kTRGMUX_Source1PortEPinTrigger = 17U, /**< PORTE Pin Trigger is selected */ - kTRGMUX_Source0Tpm2Overflow = 18U, /**< TPM2 Overflow is selected */ - kTRGMUX_Source1Lpcmp1Output = 18U, /**< LPCMP1 Output is selected */ - kTRGMUX_Source0FlexIO0Timer0 = 19U, /**< FlexIO0 Timer 0 is selected */ - kTRGMUX_Source1RtcAlarm = 19U, /**< RTC Alarm is selected */ - kTRGMUX_Source0FlexIO0Timer1 = 20U, /**< FlexIO0 Timer 1 is selected */ - kTRGMUX_Source1RtcSeconds = 20U, /**< RTC Seconds is selected */ - kTRGMUX_Source0FlexIO0Timer2 = 21U, /**< FlexIO0 Timer 2 is selected */ - kTRGMUX_Source1Lptmr0Trigger = 21U, /**< LPTMR0 Trigger is selected */ - kTRGMUX_Source0FlexIO0Timer3 = 22U, /**< FlexIO0 Timer 3 is selected */ - kTRGMUX_Source1Lptmr1Trigger = 22U, /**< LPTMR1 Trigger is selected */ - kTRGMUX_Source0FlexIO0Timer4 = 23U, /**< FLexIO0 Timer 4 is selected */ - kTRGMUX_Source1Tpm1ChannelEven = 23U, /**< TPM1 Channel Even is selected */ - kTRGMUX_Source0FlexIO0Timer5 = 24U, /**< FlexIO0 Timer 5 is selected */ - kTRGMUX_Source1Tpm1ChannelOdd = 24U, /**< TPM1 Channel Odd is selected */ - kTRGMUX_Source0FlexIO0Timer6 = 25U, /**< FlexIO0 Timer 6 is selected */ - kTRGMUX_Source1Tpm1Overflow = 25U, /**< TPM1 Overflow is selected */ - kTRGMUX_Source0FlexIO0Timer7 = 26U, /**< FlexIO0 Timer 7 is selected */ - kTRGMUX_Source1Tpm2ChannelEven = 26U, /**< TPM2 Channel Even is selected */ - kTRGMUX_Source0Lpi2c0MasterStop = 27U, /**< LPI2C0 Master Stop is selected */ - kTRGMUX_Source1Tpm2ChannelOdd = 27U, /**< TPM2 Channel Odd is selected */ - kTRGMUX_Source0Lpi2c0SlaveStop = 28U, /**< LPI2C0 Slave Stop is selected */ - kTRGMUX_Source1Tpm2Overflow = 28U, /**< TPM2 Overflow is selected */ - kTRGMUX_Source0Lpi2c1MasterStop = 29U, /**< LPI2C1 Master Stop is selected */ - kTRGMUX_Source1FlexIO0Timer0 = 29U, /**< FlexIO0 Timer 0 is selected */ - kTRGMUX_Source0Lpi2c1SlaveStop = 30U, /**< LPI2C1 Slave Stop is selected */ - kTRGMUX_Source1FlexIO0Timer1 = 30U, /**< FlexIO0 Timer 1 is selected */ - kTRGMUX_Source0Lpi2c2MasterStop = 31U, /**< LPI2C2 Master Stop is selected */ - kTRGMUX_Source1FlexIO0Timer2 = 31U, /**< FlexIO0 Timer 2 is selected */ - kTRGMUX_Source0Lpi2c2SlaveStop = 32U, /**< LPI2C2 Slave Stop is selected */ - kTRGMUX_Source1FlexIO0Timer3 = 32U, /**< FlexIO0 Timer 3 is selected */ - kTRGMUX_Source0Sai0Rx = 33U, /**< SAI0 Rx Frame Sync is selected */ - kTRGMUX_Source1FlexIO0Timer4 = 33U, /**< FLexIO0 Timer 4 is selected */ - kTRGMUX_Source0Sai0Tx = 34U, /**< SAI0 Tx Frame Sync is selected */ - kTRGMUX_Source1FlexIO0Timer5 = 34U, /**< FlexIO0 Timer 5 is selected */ - kTRGMUX_Source0Lpspi0Frame = 35U, /**< LPSPI0 Frame is selected */ - kTRGMUX_Source1FlexIO0Timer6 = 35U, /**< FlexIO0 Timer 6 is selected */ - kTRGMUX_Source0Lpspi0Rx = 36U, /**< LPSPI0 Rx is selected */ - kTRGMUX_Source1FlexIO0Timer7 = 36U, /**< FlexIO0 Timer 7 is selected */ - kTRGMUX_Source0Lpspi1Frame = 37U, /**< LPSPI1 Frame is selected */ - kTRGMUX_Source1Lpi2c0MasterStop = 37U, /**< LPI2C0 Master Stop is selected */ - kTRGMUX_Source0Lpspi1Rx = 38U, /**< LPSPI1 Rx is selected */ - kTRGMUX_Source1Lpi2c0SlaveStop = 38U, /**< LPI2C0 Slave Stop is selected */ - kTRGMUX_Source0Lpspi2Frame = 39U, /**< LPSPI2 Frame is selected */ - kTRGMUX_Source1Lpi2c1MasterStop = 39U, /**< LPI2C1 Master Stop is selected */ - kTRGMUX_Source0Lpspi2RX = 40U, /**< LPSPI2 Rx is selected */ - kTRGMUX_Source1Lpi2c1SlaveStop = 40U, /**< LPI2C1 Slave Stop is selected */ - kTRGMUX_Source0Lpuart0RxData = 41U, /**< LPUART0 Rx Data is selected */ - kTRGMUX_Source1Lpi2c2MasterStop = 41U, /**< LPI2C2 Master Stop is selected */ - kTRGMUX_Source0Lpuart0RxIdle = 42U, /**< LPUART0 Rx Idle is selected */ - kTRGMUX_Source1Lpi2c2SlaveStop = 42U, /**< LPI2C2 Slave Stop is selected */ - kTRGMUX_Source0Lpuart0TxData = 43U, /**< LPUART0 Tx Data is selected */ - kTRGMUX_Source1Sai0Rx = 43U, /**< SAI0 Rx Frame Sync is selected */ - kTRGMUX_Source0Lpuart1RxData = 44U, /**< LPUART1 Rx Data is selected */ - kTRGMUX_Source1Sai0Tx = 44U, /**< SAI0 Tx Frame Sync is selected */ - kTRGMUX_Source0Lpuart1RxIdle = 45U, /**< LPUART1 Rx Idle is selected */ - kTRGMUX_Source1Lpspi0Frame = 45U, /**< LPSPI0 Frame is selected */ - kTRGMUX_Source0Lpuart1TxData = 46U, /**< LPUART1 TX Data is selected */ - kTRGMUX_Source1Lpspi0Rx = 46U, /**< LPSPI0 Rx is selected */ - kTRGMUX_Source0Lpuart2RxData = 47U, /**< LPUART2 RX Data is selected */ - kTRGMUX_Source1Lpspi1Frame = 47U, /**< LPSPI1 Frame is selected */ - kTRGMUX_Source0Lpuart2RxIdle = 48U, /**< LPUART2 RX Idle is selected */ - kTRGMUX_Source1Lpspi1Rx = 48U, /**< LPSPI1 Rx is selected */ - kTRGMUX_Source0Lpuart2TxData = 49U, /**< LPUART2 TX Data is selected */ - kTRGMUX_Source1Lpspi2Frame = 49U, /**< LPSPI2 Frame is selected */ - kTRGMUX_Source0Usb0Frame = 50U, /**< USB0 Start of Frame is selected */ - kTRGMUX_Source1Lpspi2RX = 50U, /**< LPSPI2 Rx is selected */ - kTRGMUX_Source0PortAPinTrigger = 51U, /**< PORTA Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0RxData = 51U, /**< LPUART0 Rx Data is selected */ - kTRGMUX_Source0PortBPinTrigger = 52U, /**< PORTB Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0RxIdle = 52U, /**< LPUART0 Rx Idle is selected */ - kTRGMUX_Source0PortCPinTrigger = 53U, /**< PORTC Pin Trigger is selected */ - kTRGMUX_Source1Lpuart0TxData = 53U, /**< LPUART0 Tx Data is selected */ - kTRGMUX_Source0PortDPinTrigger = 54U, /**< PORTD Pin Trigger is selected */ - kTRGMUX_Source1Lpuart1RxData = 54U, /**< LPUART1 Rx Data is selected */ - kTRGMUX_Source0Lpcmp0Output = 55U, /**< LPCMP0 Output is selected */ - kTRGMUX_Source1Lpuart1RxIdle = 55U, /**< LPUART1 Rx Idle is selected */ - kTRGMUX_Source0Lpi2c3MasterStop = 56U, /**< LPI2C3 Master Stop is selected */ - kTRGMUX_Source1Lpuart1TxData = 56U, /**< LPUART1 TX Data is selected */ - kTRGMUX_Source0Lpi2c3SlaveStop = 57U, /**< LPI2C3 Slave Stop is selected */ - kTRGMUX_Source1Lpuart2RxData = 57U, /**< LPUART2 RX Data is selected */ - kTRGMUX_Source0Lpspi3Frame = 58U, /**< LPSPI3 Frame is selected */ - kTRGMUX_Source1Lpuart2RxIdle = 58U, /**< LPUART2 RX Idle is selected */ - kTRGMUX_Source0Lpspi3Rx = 59U, /**< LPSPI3 Rx Data is selected */ - kTRGMUX_Source1Lpuart2TxData = 59U, /**< LPUART2 TX Data is selected */ - kTRGMUX_Source0Lpuart3RxData = 60U, /**< LPUART3 Rx Data is selected */ - kTRGMUX_Source1PortAPinTrigger = 60U, /**< PORTA Pin Trigger is selected */ - kTRGMUX_Source0Lpuart3RxIdle = 61U, /**< LPUART3 Rx Idle is selected */ - kTRGMUX_Source1PortBPinTrigger = 61U, /**< PORTB Pin Trigger is selected */ - kTRGMUX_Source0Lpuart3TxData = 62U, /**< LPUART3 Tx Data is selected */ - kTRGMUX_Source1PortCPinTrigger = 62U, /**< PORTC Pin Trigger is selected */ - kTRGMUX_Source0PortEPinTrigger = 63U, /**< PORTE Pin Trigger is selected */ - kTRGMUX_Source1PortDPinTrigger = 63U, /**< PORTD Pin Trigger is selected */ -} trgmux_source_t; - -/* @} */ - -/*! - * @brief Enumeration for the TRGMUX device - * - * Defines the enumeration for the TRGMUX device collections. - */ -typedef enum _trgmux_device -{ - kTRGMUX_Trgmux0Dmamux0 = 0U, /**< DMAMUX0 device trigger input */ - kTRGMUX_Trgmux1Dmamux1 = 0U, /**< DMAMUX1 device trigger input */ - kTRGMUX_Trgmux0Lpit0 = 1U, /**< LPIT0 device trigger input */ - kTRGMUX_Trgmux1Lpit1 = 1U, /**< LPIT1 device trigger input */ - kTRGMUX_Trgmux0Tpm0 = 2U, /**< TPM0 device trigger input */ - kTRGMUX_Trgmux1Tpm3 = 2U, /**< TPM3 device trigger input */ - kTRGMUX_Trgmux0Tpm1 = 3U, /**< TPM1 device trigger input */ - kTRGMUX_Trgmux1Lpi2c3 = 3U, /**< LPI2C3 device trigger input */ - kTRGMUX_Trgmux0Tpm2 = 4U, /**< TPM2 device trigger input */ - kTRGMUX_Trgmux1Lpspi3 = 4U, /**< LPSPI3 device trigger input */ - kTRGMUX_Trgmux0Flexio0 = 5U, /**< FLEXIO0 device trigger input */ - kTRGMUX_Trgmux1Lpuart3 = 5U, /**< LPUART3 device trigger input */ - kTRGMUX_Trgmux0Lpi2c0 = 6U, /**< LPI2C0 device trigger input */ - kTRGMUX_Trgmux1Lpcmp1 = 6U, /**< LPCMP1 device trigger input */ - kTRGMUX_Trgmux0Lpi2c1 = 7U, /**< LPI2C1 device trigger input */ - kTRGMUX_Trgmux1Dmamux0 = 7U, /**< DMAMUX0 device trigger input */ - kTRGMUX_Trgmux0Lpi2c2 = 8U, /**< LPI2C2 device trigger input */ - kTRGMUX_Trgmux1Lpit0 = 8U, /**< LPIT0 device trigger input */ - kTRGMUX_Trgmux0Lpspi0 = 9U, /**< LPSPI0 device trigger input */ - kTRGMUX_Trgmux1Tpm0 = 9U, /**< TPM0 device trigger input */ - kTRGMUX_Trgmux0Lpspi1 = 10U, /**< LPSPI1 device trigger input */ - kTRGMUX_Trgmux1Tpm1 = 10U, /**< TPM1 device trigger input */ - kTRGMUX_Trgmux0Lpspi2 = 11U, /**< LPSPI2 device trigger input */ - kTRGMUX_Trgmux1Tpm2 = 11U, /**< TPM2 device trigger input */ - kTRGMUX_Trgmux0Lpuart0 = 12U, /**< LPUART0 device trigger input */ - kTRGMUX_Trgmux1Flexio0 = 12U, /**< FLEXIO0 device trigger input */ - kTRGMUX_Trgmux0Lpuart1 = 13U, /**< LPUART1 device trigger input */ - kTRGMUX_Trgmux1Lpi2c0 = 13U, /**< LPI2C0 device trigger input */ - kTRGMUX_Trgmux0Lpuart2 = 14U, /**< LPUART2 device trigger input */ - kTRGMUX_Trgmux1Lpi2c1 = 14U, /**< LPI2C1 device trigger input */ - kTRGMUX_Trgmux0Adc0 = 15U, /**< ADC0 device trigger input */ - kTRGMUX_Trgmux1Lpi2c2 = 15U, /**< LPI2C2 device trigger input */ - kTRGMUX_Trgmux0Lpcmp0 = 16U, /**< LPCMP0 device trigger input */ - kTRGMUX_Trgmux1Lpspi0 = 16U, /**< LPSPI0 device trigger input */ - kTRGMUX_Trgmux0Dac0 = 17U, /**< DAC0 device trigger input */ - kTRGMUX_Trgmux1Lpspi1 = 17U, /**< LPSPI1 device trigger input */ - kTRGMUX_Trgmux0Dmamux1 = 18U, /**< DMAMUX1 device trigger input */ - kTRGMUX_Trgmux1Lpspi2 = 18U, /**< LPSPI2 device trigger input */ - kTRGMUX_Trgmux0Lpit1 = 19U, /**< LPIT1 device trigger input */ - kTRGMUX_Trgmux1Lpuart0 = 19U, /**< LPUART0 device trigger input */ - kTRGMUX_Trgmux0Tpm3 = 20U, /**< TPM3 device trigger input */ - kTRGMUX_Trgmux1Lpuart1 = 20U, /**< LPUART1 device trigger input */ - kTRGMUX_Trgmux0Lpi2c3 = 21U, /**< LPI2C3 device trigger input */ - kTRGMUX_Trgmux1Lpuart2 = 21U, /**< LPUART2 device trigger input */ - kTRGMUX_Trgmux0Lpspi3 = 22U, /**< LPSPI3 device trigger input */ - kTRGMUX_Trgmux1Adc0 = 22U, /**< ADC0 device trigger input */ - kTRGMUX_Trgmux0Lpuart3 = 23U, /**< LPUART3 device trigger input */ - kTRGMUX_Trgmux1Lpcmp0 = 23U, /**< LPCMP0 device trigger input */ - kTRGMUX_Trgmux0Lpcmp1 = 24U, /**< LPCMP1 device trigger input */ - kTRGMUX_Trgmux1Lpdac0 = 24U, /**< LPDAC0 device trigger input */ -} trgmux_device_t; - -/* @} */ - -/*! - * @addtogroup xrdc_mapping - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Structure for the XRDC mapping - * - * Defines the structure for the XRDC resource collections. - */ - -typedef enum _xrdc_master -{ - kXRDC_MasterCM4CodeBus = 0U, /**< CM4 C-BUS */ - kXRDC_MasterCM4SystemBus = 1U, /**< CM4 S-BUS */ - kXRDC_MasterRI5CYCodeBus = 16U, /**< RI5CY C-BUS */ - kXRDC_MasterRI5CYSystemBus = 17U, /**< RI5CY S-BUS */ - kXRDC_MasterEdma0 = 2U, /**< EDMA0 */ - kXRDC_MasterUsdhc = 3U, /**< USDHC */ - kXRDC_MasterUsb = 4U, /**< USB */ - kXRDC_MasterCM0P = 32U, /**< CM0P */ - kXRDC_MasterEdma1 = 33U, /**< EDMA1 */ - kXRDC_MasterCau3 = 34U, /**< CAU3 */ - kXRDC_MasterZERORISCYCodeBus = 35U, /**< ZERO RISCY C-BUS */ - kXRDC_MasterZERORISCYSystemBus = 36U, /**< ZERO RISCY S-BUS */ -} xrdc_master_t; - -/* @} */ - -typedef enum _xrdc_mem -{ - kXRDC_MemMrc0_0 = 0U, /**< MRC0 Memory 0 */ - kXRDC_MemMrc0_1 = 1U, /**< MRC0 Memory 1 */ - kXRDC_MemMrc0_2 = 2U, /**< MRC0 Memory 2 */ - kXRDC_MemMrc0_3 = 3U, /**< MRC0 Memory 3 */ - kXRDC_MemMrc0_4 = 4U, /**< MRC0 Memory 4 */ - kXRDC_MemMrc0_5 = 5U, /**< MRC0 Memory 5 */ - kXRDC_MemMrc0_6 = 6U, /**< MRC0 Memory 6 */ - kXRDC_MemMrc0_7 = 7U, /**< MRC0 Memory 7 */ - kXRDC_MemMrc1_0 = 16U, /**< MRC1 Memory 0 */ - kXRDC_MemMrc1_1 = 17U, /**< MRC1 Memory 1 */ - kXRDC_MemMrc1_2 = 18U, /**< MRC1 Memory 2 */ - kXRDC_MemMrc1_3 = 19U, /**< MRC1 Memory 3 */ - kXRDC_MemMrc1_4 = 20U, /**< MRC1 Memory 4 */ - kXRDC_MemMrc1_5 = 21U, /**< MRC1 Memory 5 */ - kXRDC_MemMrc1_6 = 22U, /**< MRC1 Memory 6 */ - kXRDC_MemMrc1_7 = 23U, /**< MRC1 Memory 7 */ -} xrdc_mem_t; - -typedef enum _xrdc_periph -{ - kXRDC_PeriphMscm = 1U, /**< Miscellaneous System Control Module (MSCM) */ - kXRDC_PeriphDma0 = 8U, /**< Direct Memory Access 0 (DMA0) controller */ - kXRDC_PeriphDma0Tcd = 9U, /**< Direct Memory Access 0 (DMA0) controller transfer control descriptors */ - kXRDC_PeriphFlexBus = 12U, /**< External Bus Interface(FlexBus) */ - kXRDC_PeriphXrdcMgr = 20U, /**< Extended Resource Domain Controller (XRDC) MGR */ - kXRDC_PeriphXrdcMdac = 21U, /**< Extended Resource Domain Controller (XRDC) MDAC */ - kXRDC_PeriphXrdcPac = 22U, /**< Extended Resource Domain Controller (XRDC) PAC */ - kXRDC_PeriphXrdcMrc = 23U, /**< Extended Resource Domain Controller (XRDC) MRC */ - kXRDC_PeriphSema420 = 27U, /**< Semaphore Unit 0 (SEMA420) */ - kXRDC_PeriphCmc0 = 32U, /**< Core Mode Controller (CMC) */ - kXRDC_PeriphDmamux0 = 33U, /**< Direct Memory Access Multiplexer 0 (DMAMUX0) */ - kXRDC_PeriphEwm = 34U, /**< External Watchdog Monitor (EWM) */ - kXRDC_PeriphFtfe = 35U, /**< Flash Memory Module (FTFE) */ - kXRDC_PeriphLlwu0 = 36U, /**< Low Leakage Wake-up Unit 0 (LLWU0) */ - kXRDC_PeriphMua = 37U, /**< Message Unit Side A (MU-A) */ - kXRDC_PeriphSim = 38U, /**< System Integration Module (SIM) */ - kXRDC_PeriphSimdgo = 39U, /**< System Integration Module - DGO (SIM-DGO) */ - kXRDC_PeriphSpm = 40U, /**< System Power Management (SPM) */ - kXRDC_PeriphTrgmux0 = 41U, /**< Tirgger Multiplexer 0 (TRGMUX0) */ - kXRDC_PeriphWdog0 = 42U, /**< Watchdog 0 (WDOG0) */ - kXRDC_PeriphPcc0 = 43U, /**< Peripheral Clock Controller 0 (PCC0) */ - kXRDC_PeriphScg = 44U, /**< System Clock Generator (SCG) */ - kXRDC_PeriphSrf = 45U, /**< System Register File */ - kXRDC_PeriphVbat = 46U, /**< VBAT Register File */ - kXRDC_PeriphCrc0 = 47U, /**< Cyclic Redundancy Check 0 (CRC0) */ - kXRDC_PeriphLpit0 = 48U, /**< Low-Power Periodic Interrupt Timer 0 (LPIT0) */ - kXRDC_PeriphRtc = 49U, /**< Real Time Clock (RTC) */ - kXRDC_PeriphLptmr0 = 50U, /**< Low-Power Timer 0 (LPTMR0) */ - kXRDC_PeriphLptmr1 = 51U, /**< Low-Power Timer 1 (LPTMR1) */ - kXRDC_PeriphTstmr0 = 52U, /**< Time Stamp Timer 0 (TSTMR0) */ - kXRDC_PeriphTpm0 = 53U, /**< Timer / Pulse Width Modulator Module 0 (TPM0) - 6 channel */ - kXRDC_PeriphTpm1 = 54U, /**< Timer / Pulse Width Modulator Module 1 (TPM1) - 2 channel */ - kXRDC_PeriphTpm2 = 55U, /**< Timer / Pulse Width Modulator Module 2 (TPM2) - 6 channel */ - kXRDC_PeriphEmvsim0 = 56U, /**< Euro Mastercard Visa Secure Identity Module 0 (EMVSIM0) */ - kXRDC_PeriphFlexio0 = 57U, /**< Flexible Input / Output 0 (FlexIO0) */ - kXRDC_PeriphLpi2c0 = 58U, /**< Low-Power Inter-Integrated Circuit 0 (LPI2C0) */ - kXRDC_PeriphLpi2c1 = 59U, /**< Low-Power Inter-Integrated Circuit 1 (LPI2C1) */ - kXRDC_PeriphLpi2c2 = 60U, /**< Low-Power Inter-Integrated Circuit 2 (LPI2C2) */ - kXRDC_PeriphSai0 = 61U, /**< Serial Audio Interface 0 (SAI0) */ - kXRDC_PeriphSdhc0 = 62U, /**< Secure Digital Host Controller 0 (SDHC0) */ - kXRDC_PeriphLpspi0 = 63U, /**< Low-Power Serial Peripheral Interface 0 (LPSPI0) */ - kXRDC_PeriphLpspi1 = 64U, /**< Low-Power Serial Peripheral Interface 1 (LPSPI1) */ - kXRDC_PeriphLpspi2 = 65U, /**< Low-Power Serial Peripheral Interface 2 (LPSPI2) */ - kXRDC_PeriphLpuart0 = 66U, /**< Low-Power Universal Asynchronous Receive / Transmit 0 (LPUART0) */ - kXRDC_PeriphLpuart1 = 67U, /**< Low-Power Universal Asynchronous Receive / Transmit 1 (LPUART1) */ - kXRDC_PeriphLpuart2 = 68U, /**< Low-Power Universal Asynchronous Receive / Transmit 2 (LPUART2) */ - kXRDC_PeriphUsb0 = 69U, /**< Universal Serial Bus 0 (USB0) - Full Speed, Device Only */ - kXRDC_PeriphPortA = 70U, /**< PORTA Multiplex Control */ - kXRDC_PeriphPortB = 71U, /**< PORTB Multiplex Control */ - kXRDC_PeriphPortC = 72U, /**< PORTC Multiplex Control */ - kXRDC_PeriphPortD = 73U, /**< PORTD Multiplex Control */ - kXRDC_PeriphLpadc0 = 74U, /**< Low-Power Analog-to-Digital Converter 0 (LPADC0) */ - kXRDC_PeriphLpcmp0 = 75U, /**< Low-Power Comparator 0 (LPCMP0) */ - kXRDC_PeriphDac0 = 76U, /**< Digital-to-Analog Converter 0 (DAC0) */ - kXRDC_PeriphVref = 77U, /**< Voltage Reference (VREF) */ - kXRDC_PeriphDma1 = 136U, /**< Direct Memory Access 1 (DMA1) controller */ - kXRDC_PeriphDma1Tcd = 137U, /**< Direct Memory Access 1 (DMA1) controller trasfer control descriptors */ - kXRDC_PeriphFgpio1 = 143U, /**< IO Port Alias */ - kXRDC_PeriphSema421 = 155U, /**< Semaphore Unit 1 (SEMA421) */ - kXRDC_PeriphCmc1 = 160U, /**< Core Mode Controller (CMC) */ - kXRDC_PeriphDmamux1 = 161U, /**< Direct Memory Access Mutiplexer 1 (DMAMUX1) */ - kXRDC_PeriphIntmux0 = 162U, /**< Interrupt Multiplexer 0 (INTMUX0) */ - kXRDC_Periphllwu1 = 163U, /**< Low Leakage Wake-up Unit 1 (LLWU1) */ - kXRDC_PeriphMub = 164U, /**< Messaging Unit - Side B (MU-B) */ - kXRDC_PeriphTrgmux1 = 165U, /**< Trigger Multiplexer 1 (TRGMUX1) */ - kXRDC_PeriphWdog1 = 166U, /**< Watchdog 1 (WDOG1) */ - kXRDC_PeriphPcc1 = 167U, /**< Peripheral Clock Controller 1 (PCC1) */ - kXRDC_PeriphCau3 = 168U, /**< Cryptographic Acceleration Unit (CAU3) */ - kXRDC_PeriphTrng = 169U, /**< True Random Number Generator (TRNG) */ - kXRDC_PeriphLpit1 = 170U, /**< Low-Power Periodic Interrupt Timer 1 (LPIT1) */ - kXRDC_PeriphLptmr2 = 171U, /**< Low-Power Timer 2 (LPTMR2) */ - kXRDC_PeriphTstmr1 = 172U, /**< Time Stamp Timer 1 (TSTMR1) */ - kXRDC_PeriphTpm3 = 173U, /**< Timer / Pulse Width Modulation Module 3 (TPM3) - 2 channel */ - kXRDC_PeriphLpi2c3 = 174U, /**< Low-Power Inter-Integrated Circuit 3 (LPI2C3) */ - kXRDC_PeriphRsim = 175U, /**< 2.4GHz Radio (RF2.4G) - RSIM */ - kXRDC_PeriphXcvr = 176U, /**< 2.4GHz Radio (RF2.4G) - XCVR */ - kXRDC_PeriphAnt = 177U, /**< 2.4GHz Radio (RF2.4G) - ANT+ Link Layer */ - kXRDC_PeriphBle = 178U, /**< 2.4GHz Radio (RF2.4G) - Bluetooth Link layer */ - kXRDC_PeriphGfsk = 179U, /**< 2.4GHz Radio (RF2.4G) - Generic Link layer */ - kXRDC_PeriphIeee = 180U, /**< 2.4GHz Radio (RF2.4G) - IEEE 802.15.4 Link Layer */ - kXRDC_PeriphLpspi3 = 181U, /**< Low-Power Serial Peripheral Interface 3 (LPSPI3) */ - kXRDC_PeriphLpuart3 = 182U, /**< Low-Power Universal Asynchronous Receive / Transmit 3 (LPUART3) */ - kXRDC_PeriphPortE = 183U, /**< PORTE Multiplex Control */ - kXRDC_PeriphLpcmp1 = 214U, /**< Low-Power Comparator 1 (LPCMP1) */ -} xrdc_periph_t; - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ - __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ - uint8_t RESERVED_1[8]; - __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ - __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ - uint8_t RESERVED_3[124]; - __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[48]; - struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ - } CMD[15]; - uint8_t RESERVED_5[136]; - __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[240]; - __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define ADC_VERID_RES_MASK (0x1U) -#define ADC_VERID_RES_SHIFT (0U) -/*! RES - Resolution - * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. - * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. - */ -#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) -#define ADC_VERID_DIFFEN_MASK (0x2U) -#define ADC_VERID_DIFFEN_SHIFT (1U) -/*! DIFFEN - Differential Supported - * 0b0..Differential operation not supported. - * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. - */ -#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) -#define ADC_VERID_MVI_MASK (0x8U) -#define ADC_VERID_MVI_SHIFT (3U) -/*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. - */ -#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) -#define ADC_VERID_CSW_MASK (0x70U) -#define ADC_VERID_CSW_SHIFT (4U) -/*! CSW - Channel Scale Width - * 0b000..Channel scaling not supported. - * 0b001..Channel scaling supported. 1-bit CSCALE control field. - * 0b110..Channel scaling supported. 6-bit CSCALE control field. - */ -#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) -#define ADC_VERID_VR1RNGI_MASK (0x100U) -#define ADC_VERID_VR1RNGI_SHIFT (8U) -/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented - * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. - * 0b1..Range control required. CFG[VREF1RNG] is implemented. - */ -#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) -#define ADC_VERID_IADCKI_MASK (0x200U) -#define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented - * 0b0..Internal clock source not implemented. - * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. - */ -#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) -#define ADC_VERID_CALOFSI_MASK (0x400U) -#define ADC_VERID_CALOFSI_SHIFT (10U) -/*! CALOFSI - Calibration Offset Function Implemented - * 0b0..Offset calibration and offset trimming not implemented. - * 0b1..Offset calibration and offset trimming implemented. - */ -#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) -#define ADC_VERID_MINOR_MASK (0xFF0000U) -#define ADC_VERID_MINOR_SHIFT (16U) -#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) -#define ADC_VERID_MAJOR_MASK (0xFF000000U) -#define ADC_VERID_MAJOR_SHIFT (24U) -#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) -#define ADC_PARAM_TRIG_NUM_SHIFT (0U) -#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) -#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) -#define ADC_PARAM_FIFOSIZE_SHIFT (8U) -/*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. - * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. - */ -#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) -#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) -#define ADC_PARAM_CV_NUM_SHIFT (16U) -#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) -#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) -#define ADC_PARAM_CMD_NUM_SHIFT (24U) -#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) -/*! @} */ - -/*! @name CTRL - ADC Control Register */ -/*! @{ */ -#define ADC_CTRL_ADCEN_MASK (0x1U) -#define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. - */ -#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) -#define ADC_CTRL_RST_MASK (0x2U) -#define ADC_CTRL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. - */ -#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) -#define ADC_CTRL_DOZEN_MASK (0x4U) -#define ADC_CTRL_DOZEN_SHIFT (2U) -/*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. - */ -#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) -#define ADC_CTRL_RSTFIFO_MASK (0x100U) -#define ADC_CTRL_RSTFIFO_SHIFT (8U) -/*! RSTFIFO - Reset FIFO - * 0b0..No effect. - * 0b1..FIFO is reset. - */ -#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) -/*! @} */ - -/*! @name STAT - ADC Status Register */ -/*! @{ */ -#define ADC_STAT_RDY_MASK (0x1U) -#define ADC_STAT_RDY_SHIFT (0U) -/*! RDY - Result FIFO Ready Flag - * 0b0..Result FIFO data level not above watermark level. - * 0b1..Result FIFO holding data above watermark level. - */ -#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) -#define ADC_STAT_FOF_MASK (0x2U) -#define ADC_STAT_FOF_SHIFT (1U) -/*! FOF - Result FIFO Overflow Flag - * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. - * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. - */ -#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) -#define ADC_STAT_TRGACT_MASK (0x30000U) -#define ADC_STAT_TRGACT_SHIFT (16U) -/*! TRGACT - Trigger Active - * 0b00..Command (sequence) associated with Trigger 0 currently being executed. - * 0b01..Command (sequence) associated with Trigger 1 currently being executed. - * 0b10..Command (sequence) associated with Trigger 2 currently being executed. - * 0b11..Command (sequence) associated with Trigger 3 currently being executed. - */ -#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) -#define ADC_STAT_CMDACT_MASK (0xF000000U) -#define ADC_STAT_CMDACT_SHIFT (24U) -/*! CMDACT - Command Active - * 0b0000..No command is currently in progress. - * 0b0001..Command 1 currently being executed. - * 0b0010..Command 2 currently being executed. - * 0b0011-0b1111..Associated command number is currently being executed. - */ -#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) -/*! @} */ - -/*! @name IE - Interrupt Enable Register */ -/*! @{ */ -#define ADC_IE_FWMIE_MASK (0x1U) -#define ADC_IE_FWMIE_SHIFT (0U) -/*! FWMIE - FIFO Watermark Interrupt Enable - * 0b0..FIFO watermark interrupts are not enabled. - * 0b1..FIFO watermark interrupts are enabled. - */ -#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) -#define ADC_IE_FOFIE_MASK (0x2U) -#define ADC_IE_FOFIE_SHIFT (1U) -/*! FOFIE - Result FIFO Overflow Interrupt Enable - * 0b0..FIFO overflow interrupts are not enabled. - * 0b1..FIFO overflow interrupts are enabled. - */ -#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) -/*! @} */ - -/*! @name DE - DMA Enable Register */ -/*! @{ */ -#define ADC_DE_FWMDE_MASK (0x1U) -#define ADC_DE_FWMDE_SHIFT (0U) -/*! FWMDE - FIFO Watermark DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) -/*! @} */ - -/*! @name CFG - ADC Configuration Register */ -/*! @{ */ -#define ADC_CFG_TPRICTRL_MASK (0x1U) -#define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control - * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. - * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion. - */ -#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) -#define ADC_CFG_PWRSEL_MASK (0x30U) -#define ADC_CFG_PWRSEL_SHIFT (4U) -/*! PWRSEL - Power Configuration Select - * 0b00..Level 1 (Lowest power setting) - * 0b01..Level 2 - * 0b10..Level 3 - * 0b11..Level 4 (Highest power setting) - */ -#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) -#define ADC_CFG_REFSEL_MASK (0xC0U) -#define ADC_CFG_REFSEL_SHIFT (6U) -/*! REFSEL - Voltage Reference Selection - * 0b00..(Default) Option 1 setting. - * 0b01..Option 2 setting. - * 0b10..Option 3 setting. - * 0b11..Reserved - */ -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) -#define ADC_CFG_CALOFS_MASK (0x8000U) -#define ADC_CFG_CALOFS_SHIFT (15U) -/*! CALOFS - Configure for offset calibration function - * 0b0..Calibration function disabled - * 0b1..Configure for offset calibration function - */ -#define ADC_CFG_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_CALOFS_SHIFT)) & ADC_CFG_CALOFS_MASK) -#define ADC_CFG_PUDLY_MASK (0xFF0000U) -#define ADC_CFG_PUDLY_SHIFT (16U) -#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) -#define ADC_CFG_PWREN_MASK (0x10000000U) -#define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed. - */ -#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) -#define ADC_CFG_VREF1RNG_MASK (0x20000000U) -#define ADC_CFG_VREF1RNG_SHIFT (29U) -/*! VREF1RNG - Enable support for low voltage reference on Option 1 Reference - * 0b0..Configuration required when Voltage Reference Option 1 input is in high voltage range - * 0b1..Configuration required when Voltage Reference Option 1 input is in low voltage range - */ -#define ADC_CFG_VREF1RNG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF1RNG_SHIFT)) & ADC_CFG_VREF1RNG_MASK) -#define ADC_CFG_ADCKEN_MASK (0x80000000U) -#define ADC_CFG_ADCKEN_SHIFT (31U) -/*! ADCKEN - ADC asynchronous clock enable - * 0b0..ADC internal clock is disabled - * 0b1..ADC internal clock is enabled - */ -#define ADC_CFG_ADCKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADCKEN_SHIFT)) & ADC_CFG_ADCKEN_MASK) -/*! @} */ - -/*! @name PAUSE - ADC Pause Register */ -/*! @{ */ -#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) -#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) -#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) -#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) -#define ADC_PAUSE_PAUSEEN_SHIFT (31U) -/*! PAUSEEN - PAUSE Option Enable - * 0b0..Pause operation disabled - * 0b1..Pause operation enabled - */ -#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) -/*! @} */ - -/*! @name FCTRL - ADC FIFO Control Register */ -/*! @{ */ -#define ADC_FCTRL_FCOUNT_MASK (0x1FU) -#define ADC_FCTRL_FCOUNT_SHIFT (0U) -#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) -#define ADC_FCTRL_FWMARK_MASK (0xF0000U) -#define ADC_FCTRL_FWMARK_SHIFT (16U) -#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) -/*! @} */ - -/*! @name SWTRIG - Software Trigger Register */ -/*! @{ */ -#define ADC_SWTRIG_SWT0_MASK (0x1U) -#define ADC_SWTRIG_SWT0_SHIFT (0U) -/*! SWT0 - Software trigger 0 event - * 0b0..No trigger 0 event generated. - * 0b1..Trigger 0 event generated. - */ -#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) -#define ADC_SWTRIG_SWT1_MASK (0x2U) -#define ADC_SWTRIG_SWT1_SHIFT (1U) -/*! SWT1 - Software trigger 1 event - * 0b0..No trigger 1 event generated. - * 0b1..Trigger 1 event generated. - */ -#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) -#define ADC_SWTRIG_SWT2_MASK (0x4U) -#define ADC_SWTRIG_SWT2_SHIFT (2U) -/*! SWT2 - Software trigger 2 event - * 0b0..No trigger 2 event generated. - * 0b1..Trigger 2 event generated. - */ -#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) -#define ADC_SWTRIG_SWT3_MASK (0x8U) -#define ADC_SWTRIG_SWT3_SHIFT (3U) -/*! SWT3 - Software trigger 3 event - * 0b0..No trigger 3 event generated. - * 0b1..Trigger 3 event generated. - */ -#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) -/*! @} */ - -/*! @name OFSTRIM - ADC Offset Trim Register */ -/*! @{ */ -#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FU) -#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U) -#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK) -/*! @} */ - -/*! @name TCTRL - Trigger Control Register */ -/*! @{ */ -#define ADC_TCTRL_HTEN_MASK (0x1U) -#define ADC_TCTRL_HTEN_SHIFT (0U) -/*! HTEN - Trigger enable - * 0b0..Hardware trigger source disabled - * 0b1..Hardware trigger source enabled - */ -#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) -#define ADC_TCTRL_TPRI_MASK (0x300U) -#define ADC_TCTRL_TPRI_SHIFT (8U) -/*! TPRI - Trigger priority setting - * 0b00..Set to highest priority, Level 1 - * 0b01-0b10..Set to corresponding priority level - * 0b11..Set to lowest priority, Level 4 - */ -#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) -#define ADC_TCTRL_TDLY_MASK (0xF0000U) -#define ADC_TCTRL_TDLY_SHIFT (16U) -#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) -#define ADC_TCTRL_TCMD_MASK (0xF000000U) -#define ADC_TCTRL_TCMD_SHIFT (24U) -/*! TCMD - Trigger command select - * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. - * 0b0001..CMD1 is executed - * 0b0010-0b1110..Corresponding CMD is executed - * 0b1111..CMD15 is executed - */ -#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) -/*! @} */ - -/* The count of ADC_TCTRL */ -#define ADC_TCTRL_COUNT (4U) - -/*! @name CMDL - ADC Command Low Buffer Register */ -/*! @{ */ -#define ADC_CMDL_ADCH_MASK (0x1FU) -#define ADC_CMDL_ADCH_SHIFT (0U) -/*! ADCH - Input channel select - * 0b00000..Select CH0A or CH0B - * 0b00001..Select CH1A or CH1B - * 0b00010..Select CH2A or CH2B - * 0b00011..Select CH3A or CH3B - * 0b00100-0b11101..Select corresponding channel CHnA or CHnB - * 0b11110..Select CH30A or CH30B - * 0b11111..Select CH31A or CH31B - */ -#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) -#define ADC_CMDL_ABSEL_MASK (0x20U) -#define ADC_CMDL_ABSEL_SHIFT (5U) -/*! ABSEL - A-side vs. B-side Select - * 0b0..The associated A-side channel is converted. - * 0b1..The associated B-side channel is converted. - */ -#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) -/*! @} */ - -/* The count of ADC_CMDL */ -#define ADC_CMDL_COUNT (15U) - -/*! @name CMDH - ADC Command High Buffer Register */ -/*! @{ */ -#define ADC_CMDH_CMPEN_MASK (0x3U) -#define ADC_CMDH_CMPEN_SHIFT (0U) -/*! CMPEN - Compare Function Enable - * 0b00..Compare disabled. - * 0b01..Reserved - * 0b10..Compare enabled. Store on true. - * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. - */ -#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) -#define ADC_CMDH_LWI_MASK (0x80U) -#define ADC_CMDH_LWI_SHIFT (7U) -/*! LWI - Loop with Increment - * 0b0..Auto channel increment disabled - * 0b1..Auto channel increment enabled - */ -#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) -#define ADC_CMDH_STS_MASK (0x700U) -#define ADC_CMDH_STS_SHIFT (8U) -/*! STS - Sample Time Select - * 0b000..Minimum sample time of 3 ADCK cycles. - * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. - * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. - * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. - * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. - * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. - * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. - * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. - */ -#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) -#define ADC_CMDH_AVGS_MASK (0x7000U) -#define ADC_CMDH_AVGS_SHIFT (12U) -/*! AVGS - Hardware Average Select - * 0b000..Single conversion. - * 0b001..2 conversions averaged. - * 0b010..4 conversions averaged. - * 0b011..8 conversions averaged. - * 0b100..16 conversions averaged. - * 0b101..32 conversions averaged. - * 0b110..64 conversions averaged. - * 0b111..128 conversions averaged. - */ -#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) -#define ADC_CMDH_LOOP_MASK (0xF0000U) -#define ADC_CMDH_LOOP_SHIFT (16U) -/*! LOOP - Loop Count Select - * 0b0000..Looping not enabled. Command executes 1 time. - * 0b0001..Loop 1 time. Command executes 2 times. - * 0b0010..Loop 2 times. Command executes 3 times. - * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. - * 0b1111..Loop 15 times. Command executes 16 times. - */ -#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) -#define ADC_CMDH_NEXT_MASK (0xF000000U) -#define ADC_CMDH_NEXT_SHIFT (24U) -/*! NEXT - Next Command Select - * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. - * 0b0001..Select CMD1 command buffer register as next command. - * 0b0010-0b1110..Select corresponding CMD command buffer register as next command - * 0b1111..Select CMD15 command buffer register as next command. - */ -#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) -/*! @} */ - -/* The count of ADC_CMDH */ -#define ADC_CMDH_COUNT (15U) - -/*! @name CV - Compare Value Register */ -/*! @{ */ -#define ADC_CV_CVL_MASK (0xFFFFU) -#define ADC_CV_CVL_SHIFT (0U) -#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) -#define ADC_CV_CVH_MASK (0xFFFF0000U) -#define ADC_CV_CVH_SHIFT (16U) -#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) -/*! @} */ - -/* The count of ADC_CV */ -#define ADC_CV_COUNT (4U) - -/*! @name RESFIFO - ADC Data Result FIFO Register */ -/*! @{ */ -#define ADC_RESFIFO_D_MASK (0xFFFFU) -#define ADC_RESFIFO_D_SHIFT (0U) -#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) -#define ADC_RESFIFO_TSRC_MASK (0x30000U) -#define ADC_RESFIFO_TSRC_SHIFT (16U) -/*! TSRC - Trigger Source - * 0b00..Trigger source 0 initiated this conversion. - * 0b01..Trigger source 1 initiated this conversion. - * 0b10..Trigger source 2 initiated this conversion. - * 0b11..Trigger source 3 initiated this conversion. - */ -#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) -#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) -#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) -/*! LOOPCNT - Loop count value - * 0b0000..Result is from initial conversion in command. - * 0b0001..Result is from second conversion in command. - * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. - * 0b1111..Result is from 16th conversion in command. - */ -#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) -#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) -#define ADC_RESFIFO_CMDSRC_SHIFT (24U) -/*! CMDSRC - Command Buffer Source - * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. - * 0b0001..CMD1 buffer used as control settings for this conversion. - * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. - * 0b1111..CMD15 buffer used as control settings for this conversion. - */ -#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) -#define ADC_RESFIFO_VALID_MASK (0x80000000U) -#define ADC_RESFIFO_VALID_SHIFT (31U) -/*! VALID - FIFO entry is valid - * 0b0..FIFO is empty. Discard any read from RESFIFO. - * 0b1..FIFO record read from RESFIFO is valid. - */ -#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x4004A000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { ADC0_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- BTLE_RF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer - * @{ - */ - -/** BTLE_RF - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1536]; - __I uint16_t BLE_PART_ID; /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */ - uint8_t RESERVED_1[2]; - __I uint16_t DSM_STATUS; /**< BLE DSM STATUS, offset: 0x604 */ - uint8_t RESERVED_2[2]; - __IO uint16_t MISC_CTRL; /**< BLE MISCELLANEOUS CONTROL, offset: 0x608 */ - uint8_t RESERVED_3[2]; - __I uint16_t BLE_FSM; /**< BLE STATE MACHINE STATUS, offset: 0x60C */ -} BTLE_RF_Type; - -/* ---------------------------------------------------------------------------- - -- BTLE_RF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks - * @{ - */ - -/*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */ -/*! @{ */ -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK (0xFFFFU) -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT (0U) -/*! BLE_PART_ID - BLE Part ID - * 0b0000000000000000..Pre-production - * 0b0000000000000001..Pre-production - * 0b0000000000000010..KW40 - * 0b0000000000000011..KW41 - * 0b0000000000000100..RV32M1 - * 0b0000000000000101..KW35/KW36 - */ -#define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK) -/*! @} */ - -/*! @name DSM_STATUS - BLE DSM STATUS */ -/*! @{ */ -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK (0x1U) -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT (0U) -#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK (0x2U) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT (1U) -#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK) -#define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK (0x4U) -#define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT (2U) -/*! XCVR_BUSY - Transceiver Busy Status Bit - * 0b0..RF Channel in available (TSM is idle) - * 0b1..RF Channel in use (TSM is busy) - */ -#define BTLE_RF_DSM_STATUS_XCVR_BUSY(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK) -/*! @} */ - -/*! @name MISC_CTRL - BLE MISCELLANEOUS CONTROL */ -/*! @{ */ -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK (0x2U) -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT (1U) -#define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK) -#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL_MASK (0x1CU) -#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL_SHIFT (2U) -#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_BLE_FSM_SEL_SHIFT)) & BTLE_RF_MISC_CTRL_BLE_FSM_SEL_MASK) -/*! @} */ - -/*! @name BLE_FSM - BLE STATE MACHINE STATUS */ -/*! @{ */ -#define BTLE_RF_BLE_FSM_VAR_CS_MASK (0x1FU) -#define BTLE_RF_BLE_FSM_VAR_CS_SHIFT (0U) -#define BTLE_RF_BLE_FSM_VAR_CS(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_VAR_CS_SHIFT)) & BTLE_RF_BLE_FSM_VAR_CS_MASK) -#define BTLE_RF_BLE_FSM_BTLE_TX_EN_MASK (0x20U) -#define BTLE_RF_BLE_FSM_BTLE_TX_EN_SHIFT (5U) -#define BTLE_RF_BLE_FSM_BTLE_TX_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_BTLE_TX_EN_SHIFT)) & BTLE_RF_BLE_FSM_BTLE_TX_EN_MASK) -#define BTLE_RF_BLE_FSM_BTLE_RX_EN_MASK (0x40U) -#define BTLE_RF_BLE_FSM_BTLE_RX_EN_SHIFT (6U) -#define BTLE_RF_BLE_FSM_BTLE_RX_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_BTLE_RX_EN_SHIFT)) & BTLE_RF_BLE_FSM_BTLE_RX_EN_MASK) -#define BTLE_RF_BLE_FSM_TX_CS_MASK (0xF80U) -#define BTLE_RF_BLE_FSM_TX_CS_SHIFT (7U) -#define BTLE_RF_BLE_FSM_TX_CS(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_TX_CS_SHIFT)) & BTLE_RF_BLE_FSM_TX_CS_MASK) -#define BTLE_RF_BLE_FSM_RX_CS_MASK (0xF000U) -#define BTLE_RF_BLE_FSM_RX_CS_SHIFT (12U) -#define BTLE_RF_BLE_FSM_RX_CS(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_RX_CS_SHIFT)) & BTLE_RF_BLE_FSM_RX_CS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group BTLE_RF_Register_Masks */ - - -/* BTLE_RF - Peripheral instance base addresses */ -/** Peripheral BTLE_RF base address */ -#define BTLE_RF_BASE (0x41032000u) -/** Peripheral BTLE_RF base pointer */ -#define BTLE_RF ((BTLE_RF_Type *)BTLE_RF_BASE) -/** Array initializer of BTLE_RF peripheral base addresses */ -#define BTLE_RF_BASE_ADDRS { BTLE_RF_BASE } -/** Array initializer of BTLE_RF peripheral base pointers */ -#define BTLE_RF_BASE_PTRS { BTLE_RF } - -/*! - * @} - */ /* end of group BTLE_RF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAU3 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU3_Peripheral_Access_Layer CAU3 Peripheral Access Layer - * @{ - */ - -/** CAU3 - Register Layout Typedef */ -typedef struct { - __I uint32_t PCT; /**< Processor Core Type, offset: 0x0 */ - __I uint32_t MCFG; /**< Memory Configuration, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DBGCSR; /**< Debug Control/Status Register, offset: 0x20 */ - __IO uint32_t DBGPBR; /**< Debug PC Breakpoint Register, offset: 0x24 */ - uint8_t RESERVED_2[8]; - __IO uint32_t DBGMCMD; /**< Debug Memory Command Register, offset: 0x30 */ - __IO uint32_t DBGMADR; /**< Debug Memory Address Register, offset: 0x34 */ - __IO uint32_t DBGMDR; /**< Debug Memory Data Register, offset: 0x38 */ - uint8_t RESERVED_3[180]; - __IO uint32_t SEMA4; /**< Semaphore Register, offset: 0xF0 */ - __I uint32_t SMOWNR; /**< Semaphore Ownership Register, offset: 0xF4 */ - uint8_t RESERVED_4[4]; - __IO uint32_t ARR; /**< Address Remap Register, offset: 0xFC */ - uint8_t RESERVED_5[128]; - __IO uint32_t CC_R[30]; /**< CryptoCore General Purpose Registers, array offset: 0x180, array step: 0x4 */ - __IO uint32_t CC_R30; /**< General Purpose R30, offset: 0x1F8 */ - __IO uint32_t CC_R31; /**< General Purpose R31, offset: 0x1FC */ - __IO uint32_t CC_PC; /**< Program Counter, offset: 0x200 */ - __O uint32_t CC_CMD; /**< Start Command Register, offset: 0x204 */ - __I uint32_t CC_CF; /**< Condition Flag, offset: 0x208 */ - uint8_t RESERVED_6[500]; - __IO uint32_t MDPK; /**< Mode Register (PublicKey), offset: 0x400 */ - uint8_t RESERVED_7[44]; - __O uint32_t COM; /**< Command Register, offset: 0x430 */ - __IO uint32_t CTL; /**< Control Register, offset: 0x434 */ - uint8_t RESERVED_8[8]; - __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */ - uint8_t RESERVED_9[4]; - __IO uint32_t STA; /**< Status Register, offset: 0x448 */ - __I uint32_t ESTA; /**< Error Status Register, offset: 0x44C */ - uint8_t RESERVED_10[48]; - __IO uint32_t PKASZ; /**< PKHA A Size Register, offset: 0x480 */ - uint8_t RESERVED_11[4]; - __IO uint32_t PKBSZ; /**< PKHA B Size Register, offset: 0x488 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PKNSZ; /**< PKHA N Size Register, offset: 0x490 */ - uint8_t RESERVED_13[4]; - __IO uint32_t PKESZ; /**< PKHA E Size Register, offset: 0x498 */ - uint8_t RESERVED_14[84]; - __I uint32_t PKHA_VID1; /**< PKHA Revision ID 1, offset: 0x4F0 */ - __I uint32_t PKHA_VID2; /**< PKHA Revision ID 2, offset: 0x4F4 */ - __I uint32_t CHA_VID; /**< CHA Revision ID, offset: 0x4F8 */ - uint8_t RESERVED_15[260]; - __IO uint32_t PKHA_CCR; /**< PKHA Clock Control Register, offset: 0x600 */ - __I uint32_t GSR; /**< Global Status Register, offset: 0x604 */ - __IO uint32_t CKLFSR; /**< Clock Linear Feedback Shift Register, offset: 0x608 */ - uint8_t RESERVED_16[500]; - __IO uint32_t PKA0[32]; /**< PKHA A0 Register, array offset: 0x800, array step: 0x4 */ - __IO uint32_t PKA1[32]; /**< PKHA A1 Register, array offset: 0x880, array step: 0x4 */ - __IO uint32_t PKA2[32]; /**< PKHA A2 Register, array offset: 0x900, array step: 0x4 */ - __IO uint32_t PKA3[32]; /**< PKHA A3 Register, array offset: 0x980, array step: 0x4 */ - __IO uint32_t PKB0[32]; /**< PKHA B0 Register, array offset: 0xA00, array step: 0x4 */ - __IO uint32_t PKB1[32]; /**< PKHA B1 Register, array offset: 0xA80, array step: 0x4 */ - __IO uint32_t PKB2[32]; /**< PKHA B2 Register, array offset: 0xB00, array step: 0x4 */ - __IO uint32_t PKB3[32]; /**< PKHA B3 Register, array offset: 0xB80, array step: 0x4 */ - __IO uint32_t PKN0[32]; /**< PKHA N0 Register, array offset: 0xC00, array step: 0x4 */ - __IO uint32_t PKN1[32]; /**< PKHA N1 Register, array offset: 0xC80, array step: 0x4 */ - __IO uint32_t PKN2[32]; /**< PKHA N2 Register, array offset: 0xD00, array step: 0x4 */ - __IO uint32_t PKN3[32]; /**< PKHA N3 Register, array offset: 0xD80, array step: 0x4 */ - __O uint32_t PKE[128]; /**< PKHA E Register, array offset: 0xE00, array step: 0x4 */ -} CAU3_Type; - -/* ---------------------------------------------------------------------------- - -- CAU3 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAU3_Register_Masks CAU3 Register Masks - * @{ - */ - -/*! @name PCT - Processor Core Type */ -/*! @{ */ -#define CAU3_PCT_Y_MASK (0xFU) -#define CAU3_PCT_Y_SHIFT (0U) -/*! Y - Minor version number - * 0b0000..Minor version number - */ -#define CAU3_PCT_Y(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_Y_SHIFT)) & CAU3_PCT_Y_MASK) -#define CAU3_PCT_X_MASK (0xF0U) -#define CAU3_PCT_X_SHIFT (4U) -/*! X - Major version number - * 0b0000..Major version number - */ -#define CAU3_PCT_X(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_X_SHIFT)) & CAU3_PCT_X_MASK) -#define CAU3_PCT_ID_MASK (0xFFFFFF00U) -#define CAU3_PCT_ID_SHIFT (8U) -/*! ID - Module ID number - * 0b010010110100000101100000..ID number for basic configuration - * 0b010010110100000101100001..ID number for PKHA configuration - */ -#define CAU3_PCT_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_ID_SHIFT)) & CAU3_PCT_ID_MASK) -/*! @} */ - -/*! @name MCFG - Memory Configuration */ -/*! @{ */ -#define CAU3_MCFG_DRAM_SZ_MASK (0xF00U) -#define CAU3_MCFG_DRAM_SZ_SHIFT (8U) -/*! DRAM_SZ - Data RAM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_DRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_DRAM_SZ_SHIFT)) & CAU3_MCFG_DRAM_SZ_MASK) -#define CAU3_MCFG_IROM_SZ_MASK (0xF0000U) -#define CAU3_MCFG_IROM_SZ_SHIFT (16U) -/*! IROM_SZ - Instruction ROM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_IROM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IROM_SZ_SHIFT)) & CAU3_MCFG_IROM_SZ_MASK) -#define CAU3_MCFG_IRAM_SZ_MASK (0xF000000U) -#define CAU3_MCFG_IRAM_SZ_SHIFT (24U) -/*! IRAM_SZ - Instruction RAM Size - * 0b0000..No memory module - * 0b0100..2K bytes - * 0b0101..3K bytes - * 0b0110..4K bytes - * 0b0111..6K bytes - * 0b1000..8K bytes - * 0b1001..12K bytes - * 0b1010..16K bytes - * 0b1011..24K bytes - * 0b1100..32K bytes - * 0b1101..48K bytes - * 0b1110..64K bytes - * 0b1111..96K bytes - */ -#define CAU3_MCFG_IRAM_SZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IRAM_SZ_SHIFT)) & CAU3_MCFG_IRAM_SZ_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define CAU3_CR_TCSEIE_MASK (0x1U) -#define CAU3_CR_TCSEIE_SHIFT (0U) -/*! TCSEIE - Task completion with software error interrupt enable - * 0b0..Disables task completion with software error to generate an interrupt request - * 0b1..Enables task completion with software error to generate an interrupt request - */ -#define CAU3_CR_TCSEIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCSEIE_SHIFT)) & CAU3_CR_TCSEIE_MASK) -#define CAU3_CR_ILLIE_MASK (0x2U) -#define CAU3_CR_ILLIE_SHIFT (1U) -/*! ILLIE - Illegal Instruction Interrupt Enable - * 0b0..Illegal instruction interrupt requests are disabled - * 0b1..illegal Instruction interrupt requests are enabled - */ -#define CAU3_CR_ILLIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ILLIE_SHIFT)) & CAU3_CR_ILLIE_MASK) -#define CAU3_CR_ASREIE_MASK (0x8U) -#define CAU3_CR_ASREIE_SHIFT (3U) -/*! ASREIE - AHB Slave Response Error Interrupt Enable - * 0b0..AHB slave response error interruption is not enabled - * 0b1..AHB slave response error interruption is enabled - */ -#define CAU3_CR_ASREIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ASREIE_SHIFT)) & CAU3_CR_ASREIE_MASK) -#define CAU3_CR_IIADIE_MASK (0x10U) -#define CAU3_CR_IIADIE_SHIFT (4U) -/*! IIADIE - IMEM Illegal Address Interrupt Enable - * 0b0..IMEM illegal address interruption is not enabled - * 0b1..IMEM illegal address interruption is enabled - */ -#define CAU3_CR_IIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_IIADIE_SHIFT)) & CAU3_CR_IIADIE_MASK) -#define CAU3_CR_DIADIE_MASK (0x20U) -#define CAU3_CR_DIADIE_SHIFT (5U) -/*! DIADIE - DMEM Illegal Address Interrupt Enable - * 0b0..DMEM illegal address interruption is not enabled - * 0b1..DMEM illegal address interruption is enabled - */ -#define CAU3_CR_DIADIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DIADIE_SHIFT)) & CAU3_CR_DIADIE_MASK) -#define CAU3_CR_SVIE_MASK (0x40U) -#define CAU3_CR_SVIE_SHIFT (6U) -/*! SVIE - Security Violation Interrupt Enable - * 0b0..Security violation interruption is not enabled - * 0b1..Security violation interruption is enabled - */ -#define CAU3_CR_SVIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_SVIE_SHIFT)) & CAU3_CR_SVIE_MASK) -#define CAU3_CR_TCIE_MASK (0x80U) -#define CAU3_CR_TCIE_SHIFT (7U) -/*! TCIE - Task completion with no error interrupt enable - * 0b0..Disables task completion with no error to generate an interrupt request - * 0b1..Enables task completion with no error to generate an interrupt request - */ -#define CAU3_CR_TCIE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCIE_SHIFT)) & CAU3_CR_TCIE_MASK) -#define CAU3_CR_RSTSM4_MASK (0x3000U) -#define CAU3_CR_RSTSM4_SHIFT (12U) -/*! RSTSM4 - Reset Semaphore - * 0b00..Idle state - * 0b01..Wait for second write - * 0b10..Clears semaphore if previous state was "01" - * 0b11..Reserved - */ -#define CAU3_CR_RSTSM4(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_RSTSM4_SHIFT)) & CAU3_CR_RSTSM4_MASK) -#define CAU3_CR_MRST_MASK (0x8000U) -#define CAU3_CR_MRST_SHIFT (15U) -/*! MRST - Module Reset - * 0b0..no action - * 0b1..reset - */ -#define CAU3_CR_MRST(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MRST_SHIFT)) & CAU3_CR_MRST_MASK) -#define CAU3_CR_FSV_MASK (0x10000U) -#define CAU3_CR_FSV_SHIFT (16U) -/*! FSV - Force Security Violation Test - * 0b0..no violation is forced - * 0b1..force security violation - */ -#define CAU3_CR_FSV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_FSV_SHIFT)) & CAU3_CR_FSV_MASK) -#define CAU3_CR_DTCCFG_MASK (0x7000000U) -#define CAU3_CR_DTCCFG_SHIFT (24U) -/*! DTCCFG - Default Task Completion Configuration - * 0b100..Issue a DMA request - * 0b010..Assert Event Completion Signal - * 0b001..Issue an Interrupt Request - * 0b000..no explicit action - */ -#define CAU3_CR_DTCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DTCCFG_SHIFT)) & CAU3_CR_DTCCFG_MASK) -#define CAU3_CR_DSHFI_MASK (0x10000000U) -#define CAU3_CR_DSHFI_SHIFT (28U) -/*! DSHFI - Disable Secure Hash Function Instructions - * 0b0..Secure Hash Functions are enabled - * 0b1..Secure Hash Functions are disabled - */ -#define CAU3_CR_DSHFI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DSHFI_SHIFT)) & CAU3_CR_DSHFI_MASK) -#define CAU3_CR_DDESI_MASK (0x20000000U) -#define CAU3_CR_DDESI_SHIFT (29U) -/*! DDESI - Disable DES Instructions - * 0b0..DES instructions are enabled - * 0b1..DES instructions are disabled - */ -#define CAU3_CR_DDESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DDESI_SHIFT)) & CAU3_CR_DDESI_MASK) -#define CAU3_CR_DAESI_MASK (0x40000000U) -#define CAU3_CR_DAESI_SHIFT (30U) -/*! DAESI - Disable AES Instructions - * 0b0..AES instructions are enabled - * 0b1..AES instructions are disabled - */ -#define CAU3_CR_DAESI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DAESI_SHIFT)) & CAU3_CR_DAESI_MASK) -#define CAU3_CR_MDIS_MASK (0x80000000U) -#define CAU3_CR_MDIS_SHIFT (31U) -/*! MDIS - Module Disable - * 0b0..CAU3 exits from low power mode - * 0b1..CAU3 enters low power mode - */ -#define CAU3_CR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MDIS_SHIFT)) & CAU3_CR_MDIS_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ -#define CAU3_SR_TCSEIRQ_MASK (0x1U) -#define CAU3_SR_TCSEIRQ_SHIFT (0U) -/*! TCSEIRQ - Task completion with software error interrupt request - * 0b0..Task not finished or finished with no software error - * 0b1..Task execution finished with software error - */ -#define CAU3_SR_TCSEIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCSEIRQ_SHIFT)) & CAU3_SR_TCSEIRQ_MASK) -#define CAU3_SR_ILLIRQ_MASK (0x2U) -#define CAU3_SR_ILLIRQ_SHIFT (1U) -/*! ILLIRQ - Illegal instruction interrupt request - * 0b0..no error - * 0b1..illegal instruction detected - */ -#define CAU3_SR_ILLIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ILLIRQ_SHIFT)) & CAU3_SR_ILLIRQ_MASK) -#define CAU3_SR_ASREIRQ_MASK (0x8U) -#define CAU3_SR_ASREIRQ_SHIFT (3U) -/*! ASREIRQ - AHB slave response error interrupt Request - * 0b0..no error - * 0b1..AHB slave response error detected - */ -#define CAU3_SR_ASREIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ASREIRQ_SHIFT)) & CAU3_SR_ASREIRQ_MASK) -#define CAU3_SR_IIADIRQ_MASK (0x10U) -#define CAU3_SR_IIADIRQ_SHIFT (4U) -/*! IIADIRQ - IMEM Illegal address interrupt request - * 0b0..no error - * 0b1..illegal IMEM address detected - */ -#define CAU3_SR_IIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_IIADIRQ_SHIFT)) & CAU3_SR_IIADIRQ_MASK) -#define CAU3_SR_DIADIRQ_MASK (0x20U) -#define CAU3_SR_DIADIRQ_SHIFT (5U) -/*! DIADIRQ - DMEM illegal access interrupt request - * 0b0..no illegal address - * 0b1..illegal address - */ -#define CAU3_SR_DIADIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DIADIRQ_SHIFT)) & CAU3_SR_DIADIRQ_MASK) -#define CAU3_SR_SVIRQ_MASK (0x40U) -#define CAU3_SR_SVIRQ_SHIFT (6U) -/*! SVIRQ - Security violation interrupt request - * 0b0..No security violation - * 0b1..Security violation - */ -#define CAU3_SR_SVIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVIRQ_SHIFT)) & CAU3_SR_SVIRQ_MASK) -#define CAU3_SR_TCIRQ_MASK (0x80U) -#define CAU3_SR_TCIRQ_SHIFT (7U) -/*! TCIRQ - Task completion with no error interrupt request - * 0b0..Task not finished or finished with error - * 0b1..Task execution finished with no error - */ -#define CAU3_SR_TCIRQ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCIRQ_SHIFT)) & CAU3_SR_TCIRQ_MASK) -#define CAU3_SR_TKCS_MASK (0xF00U) -#define CAU3_SR_TKCS_SHIFT (8U) -/*! TKCS - Task completion status - * 0b0000..Initialization RUN - * 0b0001..Running - * 0b0010..Debug Halted - * 0b1001..Stop - Error Free - * 0b1010..Stop - Error - * 0b1110..Stop - Security Violation, assert security violation output signal and set SVIRQ - * 0b1111..Stop - Security Violation and set SVIRQ - */ -#define CAU3_SR_TKCS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TKCS_SHIFT)) & CAU3_SR_TKCS_MASK) -#define CAU3_SR_SVF_MASK (0x10000U) -#define CAU3_SR_SVF_SHIFT (16U) -/*! SVF - Security violation flag - * 0b0..SoC security violation is not asserted - * 0b1..SoC security violation was asserted - */ -#define CAU3_SR_SVF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVF_SHIFT)) & CAU3_SR_SVF_MASK) -#define CAU3_SR_DBG_MASK (0x20000U) -#define CAU3_SR_DBG_SHIFT (17U) -/*! DBG - Debug mode - * 0b0..CAU3 is not in debug mode - * 0b1..CAU3 is in debug mode - */ -#define CAU3_SR_DBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DBG_SHIFT)) & CAU3_SR_DBG_MASK) -#define CAU3_SR_TCCFG_MASK (0x7000000U) -#define CAU3_SR_TCCFG_SHIFT (24U) -/*! TCCFG - Task completion configuration - * 0b100..Issue a DMA request - * 0b010..Assert the Event Completion Signal - * 0b001..Assert an interrupt request - * 0b000..No action - */ -#define CAU3_SR_TCCFG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCCFG_SHIFT)) & CAU3_SR_TCCFG_MASK) -#define CAU3_SR_MDISF_MASK (0x80000000U) -#define CAU3_SR_MDISF_SHIFT (31U) -/*! MDISF - Module disable flag - * 0b0..CCore is not in low power mode - * 0b1..CCore is in low power mode - */ -#define CAU3_SR_MDISF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK) -/*! @} */ - -/*! @name DBGCSR - Debug Control/Status Register */ -/*! @{ */ -#define CAU3_DBGCSR_DDBG_MASK (0x1U) -#define CAU3_DBGCSR_DDBG_SHIFT (0U) -/*! DDBG - Debug Disable - * 0b0..debug is enabled - * 0b1..debug is disabled - */ -#define CAU3_DBGCSR_DDBG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBG_SHIFT)) & CAU3_DBGCSR_DDBG_MASK) -#define CAU3_DBGCSR_DDBGMC_MASK (0x2U) -#define CAU3_DBGCSR_DDBGMC_SHIFT (1U) -/*! DDBGMC - Disable Debug Memory Commands - * 0b0..IPS access to IMEM and DMEM are enabled - * 0b1..IPS access to IMEM and DMEM are disabled - */ -#define CAU3_DBGCSR_DDBGMC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK) -#define CAU3_DBGCSR_PBREN_MASK (0x10U) -#define CAU3_DBGCSR_PBREN_SHIFT (4U) -/*! PBREN - PC Breakpoint Register Enable - * 0b0..PC breakpoint register (DBGPBR) is disabled - * 0b1..PC breakpoint register (DBGPBR) is enabled - */ -#define CAU3_DBGCSR_PBREN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PBREN_SHIFT)) & CAU3_DBGCSR_PBREN_MASK) -#define CAU3_DBGCSR_SIM_MASK (0x20U) -#define CAU3_DBGCSR_SIM_SHIFT (5U) -/*! SIM - Single Instruction Mode - * 0b0..Single instruction mode is disabled - * 0b1..Single instruction mode is enabled - */ -#define CAU3_DBGCSR_SIM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIM_SHIFT)) & CAU3_DBGCSR_SIM_MASK) -#define CAU3_DBGCSR_FRCH_MASK (0x100U) -#define CAU3_DBGCSR_FRCH_SHIFT (8U) -/*! FRCH - Force Debug Halt - * 0b0..Halt state not forced - * 0b1..Force halt state - */ -#define CAU3_DBGCSR_FRCH(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_FRCH_SHIFT)) & CAU3_DBGCSR_FRCH_MASK) -#define CAU3_DBGCSR_DBGGO_MASK (0x1000U) -#define CAU3_DBGCSR_DBGGO_SHIFT (12U) -/*! DBGGO - Debug Go - * 0b0..No action - * 0b1..Resume program execution - */ -#define CAU3_DBGCSR_DBGGO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DBGGO_SHIFT)) & CAU3_DBGCSR_DBGGO_MASK) -#define CAU3_DBGCSR_PCBHF_MASK (0x10000U) -#define CAU3_DBGCSR_PCBHF_SHIFT (16U) -/*! PCBHF - CryptoCore is Halted due to Hardware Breakpoint - * 0b0..CryptoCore is not halted due to a hardware breakpoint - * 0b1..CryptoCore is halted due to a hardware breakpoint - */ -#define CAU3_DBGCSR_PCBHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PCBHF_SHIFT)) & CAU3_DBGCSR_PCBHF_MASK) -#define CAU3_DBGCSR_SIMHF_MASK (0x20000U) -#define CAU3_DBGCSR_SIMHF_SHIFT (17U) -/*! SIMHF - CryptoCore is Halted due to Single Instruction Step - * 0b0..CryptoCore is not in a single step halt - * 0b1..CryptoCore is in a single step halt - */ -#define CAU3_DBGCSR_SIMHF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIMHF_SHIFT)) & CAU3_DBGCSR_SIMHF_MASK) -#define CAU3_DBGCSR_HLTIF_MASK (0x40000U) -#define CAU3_DBGCSR_HLTIF_SHIFT (18U) -/*! HLTIF - CryptoCore is Halted due to HALT Instruction - * 0b0..CryptoCore is not in software breakpoint - * 0b1..CryptoCore is in software breakpoint - */ -#define CAU3_DBGCSR_HLTIF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_HLTIF_SHIFT)) & CAU3_DBGCSR_HLTIF_MASK) -#define CAU3_DBGCSR_CSTPF_MASK (0x40000000U) -#define CAU3_DBGCSR_CSTPF_SHIFT (30U) -/*! CSTPF - CryptoCore is Stopped Status Flag - * 0b0..CryptoCore is not stopped - * 0b1..CryptoCore is stopped - */ -#define CAU3_DBGCSR_CSTPF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CSTPF_SHIFT)) & CAU3_DBGCSR_CSTPF_MASK) -#define CAU3_DBGCSR_CHLTF_MASK (0x80000000U) -#define CAU3_DBGCSR_CHLTF_SHIFT (31U) -/*! CHLTF - CryptoCore is Halted Status Flag - * 0b0..CryptoCore is not halted - * 0b1..CryptoCore is halted - */ -#define CAU3_DBGCSR_CHLTF(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CHLTF_SHIFT)) & CAU3_DBGCSR_CHLTF_MASK) -/*! @} */ - -/*! @name DBGPBR - Debug PC Breakpoint Register */ -/*! @{ */ -#define CAU3_DBGPBR_PCBKPT_MASK (0xFFFFCU) -#define CAU3_DBGPBR_PCBKPT_SHIFT (2U) -#define CAU3_DBGPBR_PCBKPT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGPBR_PCBKPT_SHIFT)) & CAU3_DBGPBR_PCBKPT_MASK) -/*! @} */ - -/*! @name DBGMCMD - Debug Memory Command Register */ -/*! @{ */ -#define CAU3_DBGMCMD_DM_MASK (0x1000000U) -#define CAU3_DBGMCMD_DM_SHIFT (24U) -/*! DM - Instruction/Data Memory Selection - * 0b0..IMEM is selected - * 0b1..DMEM is selected - */ -#define CAU3_DBGMCMD_DM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_DM_SHIFT)) & CAU3_DBGMCMD_DM_MASK) -#define CAU3_DBGMCMD_IA_MASK (0x4000000U) -#define CAU3_DBGMCMD_IA_SHIFT (26U) -/*! IA - Increment Address - * 0b0..Address is not incremented - * 0b1..Address is incremented after the access - */ -#define CAU3_DBGMCMD_IA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_IA_SHIFT)) & CAU3_DBGMCMD_IA_MASK) -#define CAU3_DBGMCMD_Rb_1_MASK (0x8000000U) -#define CAU3_DBGMCMD_Rb_1_SHIFT (27U) -#define CAU3_DBGMCMD_Rb_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_Rb_1_SHIFT)) & CAU3_DBGMCMD_Rb_1_MASK) -#define CAU3_DBGMCMD_BV_MASK (0x10000000U) -#define CAU3_DBGMCMD_BV_SHIFT (28U) -/*! BV - Byte Reversal Control - * 0b0..DMEM bytes are not reversed - * 0b1..DMEM bytes are reversed - */ -#define CAU3_DBGMCMD_BV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_BV_SHIFT)) & CAU3_DBGMCMD_BV_MASK) -#define CAU3_DBGMCMD_R_0_MASK (0x40000000U) -#define CAU3_DBGMCMD_R_0_SHIFT (30U) -#define CAU3_DBGMCMD_R_0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_0_SHIFT)) & CAU3_DBGMCMD_R_0_MASK) -#define CAU3_DBGMCMD_R_1_MASK (0x80000000U) -#define CAU3_DBGMCMD_R_1_SHIFT (31U) -#define CAU3_DBGMCMD_R_1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_1_SHIFT)) & CAU3_DBGMCMD_R_1_MASK) -/*! @} */ - -/*! @name DBGMADR - Debug Memory Address Register */ -/*! @{ */ -#define CAU3_DBGMADR_DMADDR_MASK (0xFFFFFFFCU) -#define CAU3_DBGMADR_DMADDR_SHIFT (2U) -#define CAU3_DBGMADR_DMADDR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMADR_DMADDR_SHIFT)) & CAU3_DBGMADR_DMADDR_MASK) -/*! @} */ - -/*! @name DBGMDR - Debug Memory Data Register */ -/*! @{ */ -#define CAU3_DBGMDR_DMDATA_MASK (0xFFFFFFFFU) -#define CAU3_DBGMDR_DMDATA_SHIFT (0U) -#define CAU3_DBGMDR_DMDATA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMDR_DMDATA_SHIFT)) & CAU3_DBGMDR_DMDATA_MASK) -/*! @} */ - -/*! @name SEMA4 - Semaphore Register */ -/*! @{ */ -#define CAU3_SEMA4_DID_MASK (0xFU) -#define CAU3_SEMA4_DID_SHIFT (0U) -#define CAU3_SEMA4_DID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_DID_SHIFT)) & CAU3_SEMA4_DID_MASK) -#define CAU3_SEMA4_PR_MASK (0x40U) -#define CAU3_SEMA4_PR_SHIFT (6U) -/*! PR - Privilege Attribute of Locked Semaphore Owner - * 0b0..If semaphore is locked, then owner is operating in user mode - * 0b1..If semaphore is locked, then owner is operating in privileged mode - */ -#define CAU3_SEMA4_PR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_PR_SHIFT)) & CAU3_SEMA4_PR_MASK) -#define CAU3_SEMA4_NS_MASK (0x80U) -#define CAU3_SEMA4_NS_SHIFT (7U) -/*! NS - Non Secure Attribute of the Locked Semaphore Owner - * 0b0..If semaphore is locked, owner is operating in secure mode - * 0b1..If semaphore is locked, owner is operating in nonsecure mode - */ -#define CAU3_SEMA4_NS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK) -#define CAU3_SEMA4_MSTRN_MASK (0x3F00U) -#define CAU3_SEMA4_MSTRN_SHIFT (8U) -#define CAU3_SEMA4_MSTRN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_MSTRN_SHIFT)) & CAU3_SEMA4_MSTRN_MASK) -#define CAU3_SEMA4_LK_MASK (0x80000000U) -#define CAU3_SEMA4_LK_SHIFT (31U) -/*! LK - Semaphore Lock and Release Control - * 0b0..Semaphore release - * 0b1..Semaphore lock - */ -#define CAU3_SEMA4_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_LK_SHIFT)) & CAU3_SEMA4_LK_MASK) -/*! @} */ - -/*! @name SMOWNR - Semaphore Ownership Register */ -/*! @{ */ -#define CAU3_SMOWNR_LOCK_MASK (0x1U) -#define CAU3_SMOWNR_LOCK_SHIFT (0U) -/*! LOCK - Semaphore Locked - * 0b0..Semaphore not locked - * 0b1..Semaphore locked - */ -#define CAU3_SMOWNR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_LOCK_SHIFT)) & CAU3_SMOWNR_LOCK_MASK) -#define CAU3_SMOWNR_NOWNER_MASK (0x80000000U) -#define CAU3_SMOWNR_NOWNER_SHIFT (31U) -/*! NOWNER - Semaphore Ownership - * 0b0..The host making the current read access is the semaphore owner - * 0b1..The host making the current read access is NOT the semaphore owner - */ -#define CAU3_SMOWNR_NOWNER(x) (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_NOWNER_SHIFT)) & CAU3_SMOWNR_NOWNER_MASK) -/*! @} */ - -/*! @name ARR - Address Remap Register */ -/*! @{ */ -#define CAU3_ARR_ARRL_MASK (0xFFFFFFFFU) -#define CAU3_ARR_ARRL_SHIFT (0U) -#define CAU3_ARR_ARRL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ARR_ARRL_SHIFT)) & CAU3_ARR_ARRL_MASK) -/*! @} */ - -/*! @name CC_R - CryptoCore General Purpose Registers */ -/*! @{ */ -#define CAU3_CC_R_R_MASK (0xFFFFFFFFU) -#define CAU3_CC_R_R_SHIFT (0U) -#define CAU3_CC_R_R(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R_R_SHIFT)) & CAU3_CC_R_R_MASK) -/*! @} */ - -/* The count of CAU3_CC_R */ -#define CAU3_CC_R_COUNT (30U) - -/*! @name CC_R30 - General Purpose R30 */ -/*! @{ */ -#define CAU3_CC_R30_SP_MASK (0xFFFFFFFFU) -#define CAU3_CC_R30_SP_SHIFT (0U) -#define CAU3_CC_R30_SP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R30_SP_SHIFT)) & CAU3_CC_R30_SP_MASK) -/*! @} */ - -/*! @name CC_R31 - General Purpose R31 */ -/*! @{ */ -#define CAU3_CC_R31_LR_MASK (0xFFFFFFFFU) -#define CAU3_CC_R31_LR_SHIFT (0U) -#define CAU3_CC_R31_LR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R31_LR_SHIFT)) & CAU3_CC_R31_LR_MASK) -/*! @} */ - -/*! @name CC_PC - Program Counter */ -/*! @{ */ -#define CAU3_CC_PC_PC_MASK (0xFFFFFU) -#define CAU3_CC_PC_PC_SHIFT (0U) -#define CAU3_CC_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_PC_PC_SHIFT)) & CAU3_CC_PC_PC_MASK) -/*! @} */ - -/*! @name CC_CMD - Start Command Register */ -/*! @{ */ -#define CAU3_CC_CMD_CMD_MASK (0x70000U) -#define CAU3_CC_CMD_CMD_SHIFT (16U) -/*! CMD - Command - * 0b000..Use CR[DTCCFG] for task completion configuration - * 0b100..Issue a DMA request - * 0b010..Assert Event Completion Signal - * 0b001..Issue an interrupt request - */ -#define CAU3_CC_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CMD_CMD_SHIFT)) & CAU3_CC_CMD_CMD_MASK) -/*! @} */ - -/*! @name CC_CF - Condition Flag */ -/*! @{ */ -#define CAU3_CC_CF_C_MASK (0x1U) -#define CAU3_CC_CF_C_SHIFT (0U) -#define CAU3_CC_CF_C(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_C_SHIFT)) & CAU3_CC_CF_C_MASK) -#define CAU3_CC_CF_V_MASK (0x2U) -#define CAU3_CC_CF_V_SHIFT (1U) -#define CAU3_CC_CF_V(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK) -#define CAU3_CC_CF_Z_MASK (0x4U) -#define CAU3_CC_CF_Z_SHIFT (2U) -#define CAU3_CC_CF_Z(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_Z_SHIFT)) & CAU3_CC_CF_Z_MASK) -#define CAU3_CC_CF_N_MASK (0x8U) -#define CAU3_CC_CF_N_SHIFT (3U) -#define CAU3_CC_CF_N(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_N_SHIFT)) & CAU3_CC_CF_N_MASK) -/*! @} */ - -/*! @name MDPK - Mode Register (PublicKey) */ -/*! @{ */ -#define CAU3_MDPK_PKHA_MODE_LS_MASK (0xFFFU) -#define CAU3_MDPK_PKHA_MODE_LS_SHIFT (0U) -#define CAU3_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_LS_SHIFT)) & CAU3_MDPK_PKHA_MODE_LS_MASK) -#define CAU3_MDPK_PKHA_MODE_MS_MASK (0xF0000U) -#define CAU3_MDPK_PKHA_MODE_MS_SHIFT (16U) -#define CAU3_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_MS_SHIFT)) & CAU3_MDPK_PKHA_MODE_MS_MASK) -#define CAU3_MDPK_ALG_MASK (0xF00000U) -#define CAU3_MDPK_ALG_SHIFT (20U) -/*! ALG - Algorithm - * 0b1000..PKHA - */ -#define CAU3_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_ALG_SHIFT)) & CAU3_MDPK_ALG_MASK) -/*! @} */ - -/*! @name COM - Command Register */ -/*! @{ */ -#define CAU3_COM_ALL_MASK (0x1U) -#define CAU3_COM_ALL_SHIFT (0U) -/*! ALL - Reset All Internal Logic - * 0b0..Do Not Reset - * 0b1..Reset PKHA engine and registers - */ -#define CAU3_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_ALL_SHIFT)) & CAU3_COM_ALL_MASK) -#define CAU3_COM_PK_MASK (0x40U) -#define CAU3_COM_PK_SHIFT (6U) -/*! PK - Reset PKHA - * 0b0..Do Not Reset - * 0b1..Reset Public Key Hardware Accelerator - */ -#define CAU3_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_COM_PK_SHIFT)) & CAU3_COM_PK_MASK) -/*! @} */ - -/*! @name CTL - Control Register */ -/*! @{ */ -#define CAU3_CTL_IM_MASK (0x1U) -#define CAU3_CTL_IM_SHIFT (0U) -/*! IM - Interrupt Mask - * 0b0..Interrupt not masked. - * 0b1..Interrupt masked - */ -#define CAU3_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_IM_SHIFT)) & CAU3_CTL_IM_MASK) -#define CAU3_CTL_PDE_MASK (0x10U) -#define CAU3_CTL_PDE_SHIFT (4U) -/*! PDE - PKHA Register DMA Enable - * 0b0..DMA Request and Done signals disabled for the PKHA Registers. - * 0b1..DMA Request and Done signals enabled for the PKHA Registers. - */ -#define CAU3_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_PDE_SHIFT)) & CAU3_CTL_PDE_MASK) -/*! @} */ - -/*! @name CW - Clear Written Register */ -/*! @{ */ -#define CAU3_CW_CM_MASK (0x1U) -#define CAU3_CW_CM_SHIFT (0U) -#define CAU3_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CM_SHIFT)) & CAU3_CW_CM_MASK) -#define CAU3_CW_CPKA_MASK (0x1000U) -#define CAU3_CW_CPKA_SHIFT (12U) -#define CAU3_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKA_SHIFT)) & CAU3_CW_CPKA_MASK) -#define CAU3_CW_CPKB_MASK (0x2000U) -#define CAU3_CW_CPKB_SHIFT (13U) -#define CAU3_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKB_SHIFT)) & CAU3_CW_CPKB_MASK) -#define CAU3_CW_CPKN_MASK (0x4000U) -#define CAU3_CW_CPKN_SHIFT (14U) -#define CAU3_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKN_SHIFT)) & CAU3_CW_CPKN_MASK) -#define CAU3_CW_CPKE_MASK (0x8000U) -#define CAU3_CW_CPKE_SHIFT (15U) -#define CAU3_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKE_SHIFT)) & CAU3_CW_CPKE_MASK) -/*! @} */ - -/*! @name STA - Status Register */ -/*! @{ */ -#define CAU3_STA_PB_MASK (0x40U) -#define CAU3_STA_PB_SHIFT (6U) -/*! PB - PKHA Busy - * 0b0..PKHA Idle - * 0b1..PKHA Busy. - */ -#define CAU3_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PB_SHIFT)) & CAU3_STA_PB_MASK) -#define CAU3_STA_DI_MASK (0x10000U) -#define CAU3_STA_DI_SHIFT (16U) -#define CAU3_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_DI_SHIFT)) & CAU3_STA_DI_MASK) -#define CAU3_STA_EI_MASK (0x100000U) -#define CAU3_STA_EI_SHIFT (20U) -/*! EI - Error Interrupt - * 0b0..Not Error. - * 0b1..Error Interrupt. - */ -#define CAU3_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_EI_SHIFT)) & CAU3_STA_EI_MASK) -#define CAU3_STA_PKP_MASK (0x10000000U) -#define CAU3_STA_PKP_SHIFT (28U) -#define CAU3_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKP_SHIFT)) & CAU3_STA_PKP_MASK) -#define CAU3_STA_PKO_MASK (0x20000000U) -#define CAU3_STA_PKO_SHIFT (29U) -#define CAU3_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKO_SHIFT)) & CAU3_STA_PKO_MASK) -#define CAU3_STA_PKZ_MASK (0x40000000U) -#define CAU3_STA_PKZ_SHIFT (30U) -#define CAU3_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKZ_SHIFT)) & CAU3_STA_PKZ_MASK) -/*! @} */ - -/*! @name ESTA - Error Status Register */ -/*! @{ */ -#define CAU3_ESTA_ERRID1_MASK (0xFU) -#define CAU3_ESTA_ERRID1_SHIFT (0U) -/*! ERRID1 - Error ID 1 - * 0b0001..Mode Error - * 0b0010..PKHA N Register Size Error - * 0b0011..PKHA E Register Size Error - * 0b0100..PKHA A Register Size Error - * 0b0101..PKHA B Register Size Error - * 0b0110..PKHA C input (as contained in the PKHA B0 quadrant) is Zero - * 0b0111..PKHA Divide by Zero Error - * 0b1000..PKHA Modulus Even Error - * 0b1111..Invalid Crypto Engine Selected - */ -#define CAU3_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_ERRID1_SHIFT)) & CAU3_ESTA_ERRID1_MASK) -#define CAU3_ESTA_CL1_MASK (0xF00U) -#define CAU3_ESTA_CL1_SHIFT (8U) -/*! CL1 - algorithms - * 0b0000..General Error - * 0b1000..Public Key - */ -#define CAU3_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_CL1_SHIFT)) & CAU3_ESTA_CL1_MASK) -/*! @} */ - -/*! @name PKASZ - PKHA A Size Register */ -/*! @{ */ -#define CAU3_PKASZ_PKASZ_MASK (0x1FFU) -#define CAU3_PKASZ_PKASZ_SHIFT (0U) -#define CAU3_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKASZ_PKASZ_SHIFT)) & CAU3_PKASZ_PKASZ_MASK) -/*! @} */ - -/*! @name PKBSZ - PKHA B Size Register */ -/*! @{ */ -#define CAU3_PKBSZ_PKBSZ_MASK (0x1FFU) -#define CAU3_PKBSZ_PKBSZ_SHIFT (0U) -#define CAU3_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKBSZ_PKBSZ_SHIFT)) & CAU3_PKBSZ_PKBSZ_MASK) -/*! @} */ - -/*! @name PKNSZ - PKHA N Size Register */ -/*! @{ */ -#define CAU3_PKNSZ_PKNSZ_MASK (0x1FFU) -#define CAU3_PKNSZ_PKNSZ_SHIFT (0U) -#define CAU3_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKNSZ_PKNSZ_SHIFT)) & CAU3_PKNSZ_PKNSZ_MASK) -/*! @} */ - -/*! @name PKESZ - PKHA E Size Register */ -/*! @{ */ -#define CAU3_PKESZ_PKESZ_MASK (0x1FFU) -#define CAU3_PKESZ_PKESZ_SHIFT (0U) -#define CAU3_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKESZ_PKESZ_SHIFT)) & CAU3_PKESZ_PKESZ_MASK) -/*! @} */ - -/*! @name PKHA_VID1 - PKHA Revision ID 1 */ -/*! @{ */ -#define CAU3_PKHA_VID1_MIN_REV_MASK (0xFFU) -#define CAU3_PKHA_VID1_MIN_REV_SHIFT (0U) -#define CAU3_PKHA_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MIN_REV_SHIFT)) & CAU3_PKHA_VID1_MIN_REV_MASK) -#define CAU3_PKHA_VID1_MAJ_REV_MASK (0xFF00U) -#define CAU3_PKHA_VID1_MAJ_REV_SHIFT (8U) -#define CAU3_PKHA_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MAJ_REV_SHIFT)) & CAU3_PKHA_VID1_MAJ_REV_MASK) -#define CAU3_PKHA_VID1_IP_ID_MASK (0xFFFF0000U) -#define CAU3_PKHA_VID1_IP_ID_SHIFT (16U) -#define CAU3_PKHA_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_IP_ID_SHIFT)) & CAU3_PKHA_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name PKHA_VID2 - PKHA Revision ID 2 */ -/*! @{ */ -#define CAU3_PKHA_VID2_ECO_REV_MASK (0xFFU) -#define CAU3_PKHA_VID2_ECO_REV_SHIFT (0U) -#define CAU3_PKHA_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ECO_REV_SHIFT)) & CAU3_PKHA_VID2_ECO_REV_MASK) -#define CAU3_PKHA_VID2_ARCH_ERA_MASK (0xFF00U) -#define CAU3_PKHA_VID2_ARCH_ERA_SHIFT (8U) -#define CAU3_PKHA_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ARCH_ERA_SHIFT)) & CAU3_PKHA_VID2_ARCH_ERA_MASK) -/*! @} */ - -/*! @name CHA_VID - CHA Revision ID */ -/*! @{ */ -#define CAU3_CHA_VID_PKHAREV_MASK (0xF0000U) -#define CAU3_CHA_VID_PKHAREV_SHIFT (16U) -#define CAU3_CHA_VID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAREV_SHIFT)) & CAU3_CHA_VID_PKHAREV_MASK) -#define CAU3_CHA_VID_PKHAVID_MASK (0xF00000U) -#define CAU3_CHA_VID_PKHAVID_SHIFT (20U) -#define CAU3_CHA_VID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAVID_SHIFT)) & CAU3_CHA_VID_PKHAVID_MASK) -/*! @} */ - -/*! @name PKHA_CCR - PKHA Clock Control Register */ -/*! @{ */ -#define CAU3_PKHA_CCR_CKTHRT_MASK (0x7U) -#define CAU3_PKHA_CCR_CKTHRT_SHIFT (0U) -/*! CKTHRT - Clock Throttle selection - * 0b000..PKHA clock division rate is 8/8 - full speed - * 0b001..PKHA clock division rate is 1/8 - * 0b010..PKHA clock division rate is 2/8 - * 0b011..PKHA clock division rate is 3/8 - * 0b100..PKHA clock division rate is 4/8 - * 0b101..PKHA clock division rate is 5/8 - * 0b110..PKHA clock division rate is 6/8 - * 0b111..PKHA clock division rate is 7/8 - */ -#define CAU3_PKHA_CCR_CKTHRT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_CKTHRT_SHIFT)) & CAU3_PKHA_CCR_CKTHRT_MASK) -#define CAU3_PKHA_CCR_LK_MASK (0x1000000U) -#define CAU3_PKHA_CCR_LK_SHIFT (24U) -/*! LK - Register Lock - * 0b0..Register is unlocked - * 0b1..Register is locked - */ -#define CAU3_PKHA_CCR_LK(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_LK_SHIFT)) & CAU3_PKHA_CCR_LK_MASK) -#define CAU3_PKHA_CCR_ELFR_MASK (0x20000000U) -#define CAU3_PKHA_CCR_ELFR_SHIFT (29U) -/*! ELFR - Enable Linear Feedback Shift Register - * 0b0..LFSR is only enabled if ECT = 1 and ECJ = 1 - * 0b1..LFSR is enabled independently of ECT and ECJ - */ -#define CAU3_PKHA_CCR_ELFR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ELFR_SHIFT)) & CAU3_PKHA_CCR_ELFR_MASK) -#define CAU3_PKHA_CCR_ECJ_MASK (0x40000000U) -#define CAU3_PKHA_CCR_ECJ_SHIFT (30U) -/*! ECJ - Enable Clock Jitter - * 0b0..Clock Jitter is disabled - * 0b1..Clock jitter is enabled - */ -#define CAU3_PKHA_CCR_ECJ(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECJ_SHIFT)) & CAU3_PKHA_CCR_ECJ_MASK) -#define CAU3_PKHA_CCR_ECT_MASK (0x80000000U) -#define CAU3_PKHA_CCR_ECT_SHIFT (31U) -/*! ECT - Enable Clock Throttle - * 0b0..PKHA clock throttle disabled meaning that PKHA is operatiing at full speed - * 0b1..PKHA clock throttle enabled - */ -#define CAU3_PKHA_CCR_ECT(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECT_SHIFT)) & CAU3_PKHA_CCR_ECT_MASK) -/*! @} */ - -/*! @name GSR - Global Status Register */ -/*! @{ */ -#define CAU3_GSR_CDI_MASK (0x400U) -#define CAU3_GSR_CDI_SHIFT (10U) -/*! CDI - CAU3 Done Interrupt occurred - * 0b0..CAU3 Done Interrupt did not occur - * 0b1..CAU3 Done Interrupt occurred - */ -#define CAU3_GSR_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CDI_SHIFT)) & CAU3_GSR_CDI_MASK) -#define CAU3_GSR_CEI_MASK (0x4000U) -#define CAU3_GSR_CEI_SHIFT (14U) -/*! CEI - CAU3 Error Interrupt - * 0b0..CAU3 Error Interrupt did not occur - * 0b1..CAU3 Error Interrupt occurred - */ -#define CAU3_GSR_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CEI_SHIFT)) & CAU3_GSR_CEI_MASK) -#define CAU3_GSR_PEI_MASK (0x8000U) -#define CAU3_GSR_PEI_SHIFT (15U) -/*! PEI - PKHA Done or Error Interrupt - * 0b0..PKHA interrupt did not occur - * 0b1..PKHA interrupt had occurred - */ -#define CAU3_GSR_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PEI_SHIFT)) & CAU3_GSR_PEI_MASK) -#define CAU3_GSR_PBSY_MASK (0x80000000U) -#define CAU3_GSR_PBSY_SHIFT (31U) -/*! PBSY - PKHA Busy - * 0b0..PKHA not busy - * 0b1..PKHA busy - */ -#define CAU3_GSR_PBSY(x) (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PBSY_SHIFT)) & CAU3_GSR_PBSY_MASK) -/*! @} */ - -/*! @name CKLFSR - Clock Linear Feedback Shift Register */ -/*! @{ */ -#define CAU3_CKLFSR_LFSR_MASK (0xFFFFFFFFU) -#define CAU3_CKLFSR_LFSR_SHIFT (0U) -#define CAU3_CKLFSR_LFSR(x) (((uint32_t)(((uint32_t)(x)) << CAU3_CKLFSR_LFSR_SHIFT)) & CAU3_CKLFSR_LFSR_MASK) -/*! @} */ - -/*! @name PKA0 - PKHA A0 Register */ -/*! @{ */ -#define CAU3_PKA0_PKHA_A0_MASK (0xFFFFFFFFU) -#define CAU3_PKA0_PKHA_A0_SHIFT (0U) -#define CAU3_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA0_PKHA_A0_SHIFT)) & CAU3_PKA0_PKHA_A0_MASK) -/*! @} */ - -/* The count of CAU3_PKA0 */ -#define CAU3_PKA0_COUNT (32U) - -/*! @name PKA1 - PKHA A1 Register */ -/*! @{ */ -#define CAU3_PKA1_PKHA_A1_MASK (0xFFFFFFFFU) -#define CAU3_PKA1_PKHA_A1_SHIFT (0U) -#define CAU3_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA1_PKHA_A1_SHIFT)) & CAU3_PKA1_PKHA_A1_MASK) -/*! @} */ - -/* The count of CAU3_PKA1 */ -#define CAU3_PKA1_COUNT (32U) - -/*! @name PKA2 - PKHA A2 Register */ -/*! @{ */ -#define CAU3_PKA2_PKHA_A2_MASK (0xFFFFFFFFU) -#define CAU3_PKA2_PKHA_A2_SHIFT (0U) -#define CAU3_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA2_PKHA_A2_SHIFT)) & CAU3_PKA2_PKHA_A2_MASK) -/*! @} */ - -/* The count of CAU3_PKA2 */ -#define CAU3_PKA2_COUNT (32U) - -/*! @name PKA3 - PKHA A3 Register */ -/*! @{ */ -#define CAU3_PKA3_PKHA_A3_MASK (0xFFFFFFFFU) -#define CAU3_PKA3_PKHA_A3_SHIFT (0U) -#define CAU3_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKA3_PKHA_A3_SHIFT)) & CAU3_PKA3_PKHA_A3_MASK) -/*! @} */ - -/* The count of CAU3_PKA3 */ -#define CAU3_PKA3_COUNT (32U) - -/*! @name PKB0 - PKHA B0 Register */ -/*! @{ */ -#define CAU3_PKB0_PKHA_B0_MASK (0xFFFFFFFFU) -#define CAU3_PKB0_PKHA_B0_SHIFT (0U) -#define CAU3_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB0_PKHA_B0_SHIFT)) & CAU3_PKB0_PKHA_B0_MASK) -/*! @} */ - -/* The count of CAU3_PKB0 */ -#define CAU3_PKB0_COUNT (32U) - -/*! @name PKB1 - PKHA B1 Register */ -/*! @{ */ -#define CAU3_PKB1_PKHA_B1_MASK (0xFFFFFFFFU) -#define CAU3_PKB1_PKHA_B1_SHIFT (0U) -#define CAU3_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB1_PKHA_B1_SHIFT)) & CAU3_PKB1_PKHA_B1_MASK) -/*! @} */ - -/* The count of CAU3_PKB1 */ -#define CAU3_PKB1_COUNT (32U) - -/*! @name PKB2 - PKHA B2 Register */ -/*! @{ */ -#define CAU3_PKB2_PKHA_B2_MASK (0xFFFFFFFFU) -#define CAU3_PKB2_PKHA_B2_SHIFT (0U) -#define CAU3_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB2_PKHA_B2_SHIFT)) & CAU3_PKB2_PKHA_B2_MASK) -/*! @} */ - -/* The count of CAU3_PKB2 */ -#define CAU3_PKB2_COUNT (32U) - -/*! @name PKB3 - PKHA B3 Register */ -/*! @{ */ -#define CAU3_PKB3_PKHA_B3_MASK (0xFFFFFFFFU) -#define CAU3_PKB3_PKHA_B3_SHIFT (0U) -#define CAU3_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKB3_PKHA_B3_SHIFT)) & CAU3_PKB3_PKHA_B3_MASK) -/*! @} */ - -/* The count of CAU3_PKB3 */ -#define CAU3_PKB3_COUNT (32U) - -/*! @name PKN0 - PKHA N0 Register */ -/*! @{ */ -#define CAU3_PKN0_PKHA_N0_MASK (0xFFFFFFFFU) -#define CAU3_PKN0_PKHA_N0_SHIFT (0U) -#define CAU3_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN0_PKHA_N0_SHIFT)) & CAU3_PKN0_PKHA_N0_MASK) -/*! @} */ - -/* The count of CAU3_PKN0 */ -#define CAU3_PKN0_COUNT (32U) - -/*! @name PKN1 - PKHA N1 Register */ -/*! @{ */ -#define CAU3_PKN1_PKHA_N1_MASK (0xFFFFFFFFU) -#define CAU3_PKN1_PKHA_N1_SHIFT (0U) -#define CAU3_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN1_PKHA_N1_SHIFT)) & CAU3_PKN1_PKHA_N1_MASK) -/*! @} */ - -/* The count of CAU3_PKN1 */ -#define CAU3_PKN1_COUNT (32U) - -/*! @name PKN2 - PKHA N2 Register */ -/*! @{ */ -#define CAU3_PKN2_PKHA_N2_MASK (0xFFFFFFFFU) -#define CAU3_PKN2_PKHA_N2_SHIFT (0U) -#define CAU3_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN2_PKHA_N2_SHIFT)) & CAU3_PKN2_PKHA_N2_MASK) -/*! @} */ - -/* The count of CAU3_PKN2 */ -#define CAU3_PKN2_COUNT (32U) - -/*! @name PKN3 - PKHA N3 Register */ -/*! @{ */ -#define CAU3_PKN3_PKHA_N3_MASK (0xFFFFFFFFU) -#define CAU3_PKN3_PKHA_N3_SHIFT (0U) -#define CAU3_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKN3_PKHA_N3_SHIFT)) & CAU3_PKN3_PKHA_N3_MASK) -/*! @} */ - -/* The count of CAU3_PKN3 */ -#define CAU3_PKN3_COUNT (32U) - -/*! @name PKE - PKHA E Register */ -/*! @{ */ -#define CAU3_PKE_PKHA_E_MASK (0xFFFFFFFFU) -#define CAU3_PKE_PKHA_E_SHIFT (0U) -#define CAU3_PKE_PKHA_E(x) (((uint32_t)(((uint32_t)(x)) << CAU3_PKE_PKHA_E_SHIFT)) & CAU3_PKE_PKHA_E_MASK) -/*! @} */ - -/* The count of CAU3_PKE */ -#define CAU3_PKE_COUNT (128U) - - -/*! - * @} - */ /* end of group CAU3_Register_Masks */ - - -/* CAU3 - Peripheral instance base addresses */ -/** Peripheral CAU3 base address */ -#define CAU3_BASE (0x41028000u) -/** Peripheral CAU3 base pointer */ -#define CAU3 ((CAU3_Type *)CAU3_BASE) -/** Array initializer of CAU3 peripheral base addresses */ -#define CAU3_BASE_ADDRS { CAU3_BASE } -/** Array initializer of CAU3 peripheral base pointers */ -#define CAU3_BASE_PTRS { CAU3 } -/** Interrupt vectors for the CAU3 peripheral type */ -#define CAU3_TASK_COMPLETE_IRQS { CAU3_Task_Complete_IRQn } -#define CAU3_SECURITY_VIOLATION_IRQS { CAU3_Security_Violation_IRQn } - -/*! - * @} - */ /* end of group CAU3_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ - __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ - __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ - __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ - } ACCESS8BIT; - struct { /* offset: 0x0 */ - __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ - __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ - } ACCESS16BIT; - }; - union { /* offset: 0x4 */ - __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ - __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ - __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ - __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ - } GPOLY_ACCESS8BIT; - struct { /* offset: 0x4 */ - __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ - __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ - } GPOLY_ACCESS16BIT; - }; - union { /* offset: 0x8 */ - __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ - struct { /* offset: 0x8 */ - uint8_t RESERVED_0[3]; - __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ - } CTRL_ACCESS8BIT; - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name DATA - CRC Data register */ -/*! @{ */ -#define CRC_DATA_LL_MASK (0xFFU) -#define CRC_DATA_LL_SHIFT (0U) -#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) -#define CRC_DATA_LU_MASK (0xFF00U) -#define CRC_DATA_LU_SHIFT (8U) -#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) -#define CRC_DATA_HL_MASK (0xFF0000U) -#define CRC_DATA_HL_SHIFT (16U) -#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) -#define CRC_DATA_HU_MASK (0xFF000000U) -#define CRC_DATA_HU_SHIFT (24U) -#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) -/*! @} */ - -/*! @name DATALL - CRC_DATALL register */ -/*! @{ */ -#define CRC_DATALL_DATALL_MASK (0xFFU) -#define CRC_DATALL_DATALL_SHIFT (0U) -#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) -/*! @} */ - -/*! @name DATALU - CRC_DATALU register */ -/*! @{ */ -#define CRC_DATALU_DATALU_MASK (0xFFU) -#define CRC_DATALU_DATALU_SHIFT (0U) -#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) -/*! @} */ - -/*! @name DATAHL - CRC_DATAHL register */ -/*! @{ */ -#define CRC_DATAHL_DATAHL_MASK (0xFFU) -#define CRC_DATAHL_DATAHL_SHIFT (0U) -#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) -/*! @} */ - -/*! @name DATAHU - CRC_DATAHU register */ -/*! @{ */ -#define CRC_DATAHU_DATAHU_MASK (0xFFU) -#define CRC_DATAHU_DATAHU_SHIFT (0U) -#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) -/*! @} */ - -/*! @name DATAL - CRC_DATAL register */ -/*! @{ */ -#define CRC_DATAL_DATAL_MASK (0xFFFFU) -#define CRC_DATAL_DATAL_SHIFT (0U) -#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) -/*! @} */ - -/*! @name DATAH - CRC_DATAH register */ -/*! @{ */ -#define CRC_DATAH_DATAH_MASK (0xFFFFU) -#define CRC_DATAH_DATAH_SHIFT (0U) -#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) -/*! @} */ - -/*! @name GPOLY - CRC Polynomial register */ -/*! @{ */ -#define CRC_GPOLY_LOW_MASK (0xFFFFU) -#define CRC_GPOLY_LOW_SHIFT (0U) -#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) -#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) -#define CRC_GPOLY_HIGH_SHIFT (16U) -#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) -/*! @} */ - -/*! @name GPOLYLL - CRC_GPOLYLL register */ -/*! @{ */ -#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) -#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) -#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) -/*! @} */ - -/*! @name GPOLYLU - CRC_GPOLYLU register */ -/*! @{ */ -#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) -#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) -#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) -/*! @} */ - -/*! @name GPOLYHL - CRC_GPOLYHL register */ -/*! @{ */ -#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) -#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) -#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) -/*! @} */ - -/*! @name GPOLYHU - CRC_GPOLYHU register */ -/*! @{ */ -#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) -#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) -#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) -/*! @} */ - -/*! @name GPOLYL - CRC_GPOLYL register */ -/*! @{ */ -#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) -#define CRC_GPOLYL_GPOLYL_SHIFT (0U) -#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) -/*! @} */ - -/*! @name GPOLYH - CRC_GPOLYH register */ -/*! @{ */ -#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) -#define CRC_GPOLYH_GPOLYH_SHIFT (0U) -#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) -/*! @} */ - -/*! @name CTRL - CRC Control register */ -/*! @{ */ -#define CRC_CTRL_TCRC_MASK (0x1000000U) -#define CRC_CTRL_TCRC_SHIFT (24U) -/*! TCRC - TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) -#define CRC_CTRL_WAS_MASK (0x2000000U) -#define CRC_CTRL_WAS_SHIFT (25U) -/*! WAS - Write CRC Data Register As Seed - * 0b0..Writes to the CRC data register are data values. - * 0b1..Writes to the CRC data register are seed values. - */ -#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) -#define CRC_CTRL_FXOR_MASK (0x4000000U) -#define CRC_CTRL_FXOR_SHIFT (26U) -/*! FXOR - Complement Read Of CRC Data Register - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC Data register. - */ -#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) -#define CRC_CTRL_TOTR_MASK (0x30000000U) -#define CRC_CTRL_TOTR_SHIFT (28U) -/*! TOTR - Type Of Transpose For Read - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) -#define CRC_CTRL_TOT_MASK (0xC0000000U) -#define CRC_CTRL_TOT_SHIFT (30U) -/*! TOT - Type Of Transpose For Writes - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) -/*! @} */ - -/*! @name CTRLHU - CRC_CTRLHU register */ -/*! @{ */ -#define CRC_CTRLHU_TCRC_MASK (0x1U) -#define CRC_CTRLHU_TCRC_SHIFT (0U) -/*! TCRC - * 0b0..16-bit CRC protocol. - * 0b1..32-bit CRC protocol. - */ -#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) -#define CRC_CTRLHU_WAS_MASK (0x2U) -#define CRC_CTRLHU_WAS_SHIFT (1U) -/*! WAS - * 0b0..Writes to the CRC data register are data values. - * 0b1..Writes to the CRC data register are seed values. - */ -#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) -#define CRC_CTRLHU_FXOR_MASK (0x4U) -#define CRC_CTRLHU_FXOR_SHIFT (2U) -/*! FXOR - * 0b0..No XOR on reading. - * 0b1..Invert or complement the read value of the CRC Data register. - */ -#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) -#define CRC_CTRLHU_TOTR_MASK (0x30U) -#define CRC_CTRLHU_TOTR_SHIFT (4U) -/*! TOTR - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) -#define CRC_CTRLHU_TOT_MASK (0xC0U) -#define CRC_CTRLHU_TOT_SHIFT (6U) -/*! TOT - * 0b00..No transposition. - * 0b01..Bits in bytes are transposed; bytes are not transposed. - * 0b10..Both bits in bytes and bytes are transposed. - * 0b11..Only bytes are transposed; no bits in a byte are transposed. - */ -#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC base address */ -#define CRC_BASE (0x4002F000u) -/** Peripheral CRC base pointer */ -#define CRC0 ((CRC_Type *)CRC_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC0 } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[12]; - __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ - uint8_t RESERVED_6[184]; - __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */ - __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */ - __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */ - __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */ - __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */ - uint8_t RESERVED_7[3832]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[8]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -/*! EDBG - Enable Debug - * 0b0..When in debug mode, the DMA continues to operate. - * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. - */ -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -/*! ERCA - Enable Round Robin Channel Arbitration - * 0b0..Fixed priority arbitration is used for channel selection . - * 0b1..Round robin arbitration is used for channel selection . - */ -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -/*! HOE - Halt On Error - * 0b0..Normal operation - * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. - */ -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -/*! HALT - Halt DMA Operations - * 0b0..Normal operation - * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. - */ -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -/*! CLM - Continuous Link Mode - * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. - * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. - */ -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -/*! EMLM - Enable Minor Loop Mapping - * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. - * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. - */ -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -/*! ECX - Error Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. - */ -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -/*! CX - Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. - */ -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) -#define DMA_CR_ACTIVE_MASK (0x80000000U) -#define DMA_CR_ACTIVE_SHIFT (31U) -/*! ACTIVE - DMA Active Status - * 0b0..eDMA is idle. - * 0b1..eDMA is executing a channel. - */ -#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) -/*! @} */ - -/*! @name ES - Error Status Register */ -/*! @{ */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -/*! DBE - Destination Bus Error - * 0b0..No destination bus error - * 0b1..The last recorded error was a bus error on a destination write - */ -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -/*! SBE - Source Bus Error - * 0b0..No source bus error - * 0b1..The last recorded error was a bus error on a source read - */ -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -/*! SGE - Scatter/Gather Configuration Error - * 0b0..No scatter/gather configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. - */ -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -/*! NCE - NBYTES/CITER Configuration Error - * 0b0..No NBYTES/CITER configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] - */ -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -/*! DOE - Destination Offset Error - * 0b0..No destination offset configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. - */ -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -/*! DAE - Destination Address Error - * 0b0..No destination address configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. - */ -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -/*! SOE - Source Offset Error - * 0b0..No source offset configuration error - * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. - */ -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -/*! SAE - Source Address Error - * 0b0..No source address configuration error. - * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. - */ -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0x700U) -#define DMA_ES_ERRCHN_SHIFT (8U) -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -/*! CPE - Channel Priority Error - * 0b0..No channel priority error - * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. - */ -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -/*! ECX - Transfer Canceled - * 0b0..No canceled transfers - * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input - */ -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -/*! VLD - VLD - * 0b0..No ERR bits are set. - * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. - */ -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) -/*! @} */ - -/*! @name ERQ - Enable Request Register */ -/*! @{ */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -/*! ERQ0 - Enable DMA Request 0 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -/*! ERQ1 - Enable DMA Request 1 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -/*! ERQ2 - Enable DMA Request 2 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -/*! ERQ3 - Enable DMA Request 3 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) -#define DMA_ERQ_ERQ4_MASK (0x10U) -#define DMA_ERQ_ERQ4_SHIFT (4U) -/*! ERQ4 - Enable DMA Request 4 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) -#define DMA_ERQ_ERQ5_MASK (0x20U) -#define DMA_ERQ_ERQ5_SHIFT (5U) -/*! ERQ5 - Enable DMA Request 5 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) -#define DMA_ERQ_ERQ6_MASK (0x40U) -#define DMA_ERQ_ERQ6_SHIFT (6U) -/*! ERQ6 - Enable DMA Request 6 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) -#define DMA_ERQ_ERQ7_MASK (0x80U) -#define DMA_ERQ_ERQ7_SHIFT (7U) -/*! ERQ7 - Enable DMA Request 7 - * 0b0..The DMA request signal for the corresponding channel is disabled - * 0b1..The DMA request signal for the corresponding channel is enabled - */ -#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) -/*! @} */ - -/*! @name EEI - Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -/*! EEI0 - Enable Error Interrupt 0 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -/*! EEI1 - Enable Error Interrupt 1 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -/*! EEI2 - Enable Error Interrupt 2 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -/*! EEI3 - Enable Error Interrupt 3 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) -#define DMA_EEI_EEI4_MASK (0x10U) -#define DMA_EEI_EEI4_SHIFT (4U) -/*! EEI4 - Enable Error Interrupt 4 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) -#define DMA_EEI_EEI5_MASK (0x20U) -#define DMA_EEI_EEI5_SHIFT (5U) -/*! EEI5 - Enable Error Interrupt 5 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) -#define DMA_EEI_EEI6_MASK (0x40U) -#define DMA_EEI_EEI6_SHIFT (6U) -/*! EEI6 - Enable Error Interrupt 6 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) -#define DMA_EEI_EEI7_MASK (0x80U) -#define DMA_EEI_EEI7_SHIFT (7U) -/*! EEI7 - Enable Error Interrupt 7 - * 0b0..The error signal for corresponding channel does not generate an error interrupt - * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request - */ -#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) -/*! @} */ - -/*! @name CEEI - Clear Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_CEEI_CEEI_MASK (0x7U) -#define DMA_CEEI_CEEI_SHIFT (0U) -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -/*! CAEE - Clear All Enable Error Interrupts - * 0b0..Clear only the EEI bit specified in the CEEI field - * 0b1..Clear all bits in EEI - */ -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) -/*! @} */ - -/*! @name SEEI - Set Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_SEEI_SEEI_MASK (0x7U) -#define DMA_SEEI_SEEI_SHIFT (0U) -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -/*! SAEE - Sets All Enable Error Interrupts - * 0b0..Set only the EEI bit specified in the SEEI field. - * 0b1..Sets all bits in EEI - */ -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) -/*! @} */ - -/*! @name CERQ - Clear Enable Request Register */ -/*! @{ */ -#define DMA_CERQ_CERQ_MASK (0x7U) -#define DMA_CERQ_CERQ_SHIFT (0U) -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -/*! CAER - Clear All Enable Requests - * 0b0..Clear only the ERQ bit specified in the CERQ field - * 0b1..Clear all bits in ERQ - */ -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) -/*! @} */ - -/*! @name SERQ - Set Enable Request Register */ -/*! @{ */ -#define DMA_SERQ_SERQ_MASK (0x7U) -#define DMA_SERQ_SERQ_SHIFT (0U) -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -/*! SAER - Set All Enable Requests - * 0b0..Set only the ERQ bit specified in the SERQ field - * 0b1..Set all bits in ERQ - */ -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) -/*! @} */ - -/*! @name CDNE - Clear DONE Status Bit Register */ -/*! @{ */ -#define DMA_CDNE_CDNE_MASK (0x7U) -#define DMA_CDNE_CDNE_SHIFT (0U) -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -/*! CADN - Clears All DONE Bits - * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field - * 0b1..Clears all bits in TCDn_CSR[DONE] - */ -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) -/*! @} */ - -/*! @name SSRT - Set START Bit Register */ -/*! @{ */ -#define DMA_SSRT_SSRT_MASK (0x7U) -#define DMA_SSRT_SSRT_SHIFT (0U) -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -/*! SAST - Set All START Bits (activates all channels) - * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field - * 0b1..Set all bits in TCDn_CSR[START] - */ -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) -/*! @} */ - -/*! @name CERR - Clear Error Register */ -/*! @{ */ -#define DMA_CERR_CERR_MASK (0x7U) -#define DMA_CERR_CERR_SHIFT (0U) -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -/*! CAEI - Clear All Error Indicators - * 0b0..Clear only the ERR bit specified in the CERR field - * 0b1..Clear all bits in ERR - */ -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) -/*! @} */ - -/*! @name CINT - Clear Interrupt Request Register */ -/*! @{ */ -#define DMA_CINT_CINT_MASK (0x7U) -#define DMA_CINT_CINT_SHIFT (0U) -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -/*! CAIR - Clear All Interrupt Requests - * 0b0..Clear only the INT bit specified in the CINT field - * 0b1..Clear all bits in INT - */ -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -/*! NOP - No Op enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other bits in this register - */ -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) -/*! @} */ - -/*! @name INT - Interrupt Request Register */ -/*! @{ */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -/*! INT0 - Interrupt Request 0 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -/*! INT1 - Interrupt Request 1 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -/*! INT2 - Interrupt Request 2 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -/*! INT3 - Interrupt Request 3 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) -#define DMA_INT_INT4_MASK (0x10U) -#define DMA_INT_INT4_SHIFT (4U) -/*! INT4 - Interrupt Request 4 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) -#define DMA_INT_INT5_MASK (0x20U) -#define DMA_INT_INT5_SHIFT (5U) -/*! INT5 - Interrupt Request 5 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) -#define DMA_INT_INT6_MASK (0x40U) -#define DMA_INT_INT6_SHIFT (6U) -/*! INT6 - Interrupt Request 6 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) -#define DMA_INT_INT7_MASK (0x80U) -#define DMA_INT_INT7_SHIFT (7U) -/*! INT7 - Interrupt Request 7 - * 0b0..The interrupt request for corresponding channel is cleared - * 0b1..The interrupt request for corresponding channel is active - */ -#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) -/*! @} */ - -/*! @name ERR - Error Register */ -/*! @{ */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -/*! ERR0 - Error In Channel 0 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -/*! ERR1 - Error In Channel 1 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -/*! ERR2 - Error In Channel 2 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -/*! ERR3 - Error In Channel 3 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) -#define DMA_ERR_ERR4_MASK (0x10U) -#define DMA_ERR_ERR4_SHIFT (4U) -/*! ERR4 - Error In Channel 4 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) -#define DMA_ERR_ERR5_MASK (0x20U) -#define DMA_ERR_ERR5_SHIFT (5U) -/*! ERR5 - Error In Channel 5 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) -#define DMA_ERR_ERR6_MASK (0x40U) -#define DMA_ERR_ERR6_SHIFT (6U) -/*! ERR6 - Error In Channel 6 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) -#define DMA_ERR_ERR7_MASK (0x80U) -#define DMA_ERR_ERR7_SHIFT (7U) -/*! ERR7 - Error In Channel 7 - * 0b0..An error in this channel has not occurred - * 0b1..An error in this channel has occurred - */ -#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) -/*! @} */ - -/*! @name HRS - Hardware Request Status Register */ -/*! @{ */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -/*! HRS0 - Hardware Request Status Channel 0 - * 0b0..A hardware service request for channel 0 is not present - * 0b1..A hardware service request for channel 0 is present - */ -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -/*! HRS1 - Hardware Request Status Channel 1 - * 0b0..A hardware service request for channel 1 is not present - * 0b1..A hardware service request for channel 1 is present - */ -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -/*! HRS2 - Hardware Request Status Channel 2 - * 0b0..A hardware service request for channel 2 is not present - * 0b1..A hardware service request for channel 2 is present - */ -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -/*! HRS3 - Hardware Request Status Channel 3 - * 0b0..A hardware service request for channel 3 is not present - * 0b1..A hardware service request for channel 3 is present - */ -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) -#define DMA_HRS_HRS4_MASK (0x10U) -#define DMA_HRS_HRS4_SHIFT (4U) -/*! HRS4 - Hardware Request Status Channel 4 - * 0b0..A hardware service request for channel 4 is not present - * 0b1..A hardware service request for channel 4 is present - */ -#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) -#define DMA_HRS_HRS5_MASK (0x20U) -#define DMA_HRS_HRS5_SHIFT (5U) -/*! HRS5 - Hardware Request Status Channel 5 - * 0b0..A hardware service request for channel 5 is not present - * 0b1..A hardware service request for channel 5 is present - */ -#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) -#define DMA_HRS_HRS6_MASK (0x40U) -#define DMA_HRS_HRS6_SHIFT (6U) -/*! HRS6 - Hardware Request Status Channel 6 - * 0b0..A hardware service request for channel 6 is not present - * 0b1..A hardware service request for channel 6 is present - */ -#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) -#define DMA_HRS_HRS7_MASK (0x80U) -#define DMA_HRS_HRS7_SHIFT (7U) -/*! HRS7 - Hardware Request Status Channel 7 - * 0b0..A hardware service request for channel 7 is not present - * 0b1..A hardware service request for channel 7 is present - */ -#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) -/*! @} */ - -/*! @name EARS - Enable Asynchronous Request in Stop Register */ -/*! @{ */ -#define DMA_EARS_EDREQ_0_MASK (0x1U) -#define DMA_EARS_EDREQ_0_SHIFT (0U) -/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. - * 0b0..Disable asynchronous DMA request for channel 0. - * 0b1..Enable asynchronous DMA request for channel 0. - */ -#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) -#define DMA_EARS_EDREQ_1_MASK (0x2U) -#define DMA_EARS_EDREQ_1_SHIFT (1U) -/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. - * 0b0..Disable asynchronous DMA request for channel 1 - * 0b1..Enable asynchronous DMA request for channel 1. - */ -#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) -#define DMA_EARS_EDREQ_2_MASK (0x4U) -#define DMA_EARS_EDREQ_2_SHIFT (2U) -/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. - * 0b0..Disable asynchronous DMA request for channel 2. - * 0b1..Enable asynchronous DMA request for channel 2. - */ -#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) -#define DMA_EARS_EDREQ_3_MASK (0x8U) -#define DMA_EARS_EDREQ_3_SHIFT (3U) -/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. - * 0b0..Disable asynchronous DMA request for channel 3. - * 0b1..Enable asynchronous DMA request for channel 3. - */ -#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) -#define DMA_EARS_EDREQ_4_MASK (0x10U) -#define DMA_EARS_EDREQ_4_SHIFT (4U) -/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 - * 0b0..Disable asynchronous DMA request for channel 4. - * 0b1..Enable asynchronous DMA request for channel 4. - */ -#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) -#define DMA_EARS_EDREQ_5_MASK (0x20U) -#define DMA_EARS_EDREQ_5_SHIFT (5U) -/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 - * 0b0..Disable asynchronous DMA request for channel 5. - * 0b1..Enable asynchronous DMA request for channel 5. - */ -#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) -#define DMA_EARS_EDREQ_6_MASK (0x40U) -#define DMA_EARS_EDREQ_6_SHIFT (6U) -/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 - * 0b0..Disable asynchronous DMA request for channel 6. - * 0b1..Enable asynchronous DMA request for channel 6. - */ -#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) -#define DMA_EARS_EDREQ_7_MASK (0x80U) -#define DMA_EARS_EDREQ_7_SHIFT (7U) -/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 - * 0b0..Disable asynchronous DMA request for channel 7. - * 0b1..Enable asynchronous DMA request for channel 7. - */ -#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) -/*! @} */ - -/*! @name DCHPRI3 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI3_CHPRI_MASK (0x7U) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI2 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI2_CHPRI_MASK (0x7U) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI1 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI1_CHPRI_MASK (0x7U) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI0 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI0_CHPRI_MASK (0x7U) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI7 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI7_CHPRI_MASK (0x7U) -#define DMA_DCHPRI7_CHPRI_SHIFT (0U) -#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) -#define DMA_DCHPRI7_DPA_MASK (0x40U) -#define DMA_DCHPRI7_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) -#define DMA_DCHPRI7_ECP_MASK (0x80U) -#define DMA_DCHPRI7_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI6 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI6_CHPRI_MASK (0x7U) -#define DMA_DCHPRI6_CHPRI_SHIFT (0U) -#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) -#define DMA_DCHPRI6_DPA_MASK (0x40U) -#define DMA_DCHPRI6_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) -#define DMA_DCHPRI6_ECP_MASK (0x80U) -#define DMA_DCHPRI6_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI5 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI5_CHPRI_MASK (0x7U) -#define DMA_DCHPRI5_CHPRI_SHIFT (0U) -#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) -#define DMA_DCHPRI5_DPA_MASK (0x40U) -#define DMA_DCHPRI5_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) -#define DMA_DCHPRI5_ECP_MASK (0x80U) -#define DMA_DCHPRI5_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI4 - Channel Priority Register */ -/*! @{ */ -#define DMA_DCHPRI4_CHPRI_MASK (0x7U) -#define DMA_DCHPRI4_CHPRI_SHIFT (0U) -#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) -#define DMA_DCHPRI4_DPA_MASK (0x40U) -#define DMA_DCHPRI4_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel. - * 0b1..Channel n cannot suspend any channel, regardless of channel priority. - */ -#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) -#define DMA_DCHPRI4_ECP_MASK (0x80U) -#define DMA_DCHPRI4_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request. - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. - */ -#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) -/*! @} */ - -/*! @name SADDR - TCD Source Address */ -/*! @{ */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) -/*! @} */ - -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (8U) - -/*! @name SOFF - TCD Signed Source Address Offset */ -/*! @{ */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) -/*! @} */ - -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (8U) - -/*! @name ATTR - TCD Transfer Attributes */ -/*! @{ */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -/*! SSIZE - Source data transfer size - * 0b000..8-bit - * 0b001..16-bit - * 0b010..32-bit - * 0b011..Reserved - * 0b100..16-byte - * 0b101..32-byte - * 0b110..Reserved - * 0b111..Reserved - */ -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -/*! SMOD - Source Address Modulo - * 0b00000..Source address modulo feature is disabled - * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. - */ -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) -/*! @} */ - -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (8U) - -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (8U) - -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR - */ -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR - */ -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (8U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR - */ -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR - */ -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (8U) - -/*! @name SLAST - TCD Last Source Address Adjustment */ -/*! @{ */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) -/*! @} */ - -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (8U) - -/*! @name DADDR - TCD Destination Address */ -/*! @{ */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) -/*! @} */ - -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (8U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ -/*! @{ */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) -/*! @} */ - -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (8U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (8U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (8U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ -/*! @{ */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) -/*! @} */ - -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (8U) - -/*! @name CSR - TCD Control and Status */ -/*! @{ */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -/*! START - Channel Start - * 0b0..The channel is not explicitly started. - * 0b1..The channel is explicitly started via a software initiated service request. - */ -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -/*! INTMAJOR - Enable an interrupt when major iteration count completes. - * 0b0..The end-of-major loop interrupt is disabled. - * 0b1..The end-of-major loop interrupt is enabled. - */ -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -/*! INTHALF - Enable an interrupt when major counter is half complete. - * 0b0..The half-point interrupt is disabled. - * 0b1..The half-point interrupt is enabled. - */ -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -/*! DREQ - Disable Request - * 0b0..The channel's ERQ bit is not affected. - * 0b1..The channel's ERQ bit is cleared when the major loop is complete. - */ -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -/*! ESG - Enable Scatter/Gather Processing - * 0b0..The current channel's TCD is normal format. - * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. - */ -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -/*! MAJORELINK - Enable channel-to-channel linking on major loop complete - * 0b0..The channel-to-channel linking is disabled. - * 0b1..The channel-to-channel linking is enabled. - */ -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0x700U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -/*! BWC - Bandwidth Control - * 0b00..No eDMA engine stalls. - * 0b01..Reserved - * 0b10..eDMA engine stalls for 4 cycles after each R/W. - * 0b11..eDMA engine stalls for 8 cycles after each R/W. - */ -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) -/*! @} */ - -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (8U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (8U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..The channel-to-channel linking is disabled - * 0b1..The channel-to-channel linking is enabled - */ -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (8U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA1 base address */ -#define DMA1_BASE (0x41008000u) -/** Peripheral DMA1 base pointer */ -#define DMA1 ((DMA_Type *)DMA1_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { 0u, DMA1_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { (DMA_Type *)0u, DMA1 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn, DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn } } -#define DMA_ERROR_IRQS { NotAvail_IRQn, DMA1_Error_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CHCFG[8]; /**< Channel 0 Configuration Register..Channel 7 Configuration Register, array offset: 0x0, array step: 0x4 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/*! @name CHCFG - Channel 0 Configuration Register..Channel 7 Configuration Register */ -/*! @{ */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x1FU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) -#define DMAMUX_CHCFG_A_ON_SHIFT (29U) -/*! A_ON - DMA Channel Always Enable - * 0b0..DMA Channel Always ON function is disabled - * 0b1..DMA Channel Always ON function is enabled - */ -#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) -#define DMAMUX_CHCFG_TRIG_SHIFT (30U) -/*! TRIG - DMA Channel Trigger Enable - * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) - * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. - */ -#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) -#define DMAMUX_CHCFG_ENBL_SHIFT (31U) -/*! ENBL - DMA Mux Channel Enable - * 0b0..DMA Mux channel is disabled - * 0b1..DMA Mux channel is enabled - */ -#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) -/*! @} */ - -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (8U) - - -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX1 base address */ -#define DMAMUX1_BASE (0x41021000u) -/** Peripheral DMAMUX1 base pointer */ -#define DMAMUX1 ((DMAMUX_Type *)DMAMUX1_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { 0u, DMAMUX1_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { (DMAMUX_Type *)0u, DMAMUX1 } - -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EMVSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer - * @{ - */ - -/** EMVSIM - Register Layout Typedef */ -typedef struct { - __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ - __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ - __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ - __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ - __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ - __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ - __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ - __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ - __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ - __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ - __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ - __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ - __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ - __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ - __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ - __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ - __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ -} EMVSIM_Type; - -/* ---------------------------------------------------------------------------- - -- EMVSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks - * @{ - */ - -/*! @name VER_ID - Version ID Register */ -/*! @{ */ -#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) -#define EMVSIM_VER_ID_VER_SHIFT (0U) -#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) -#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) -#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) -#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) -#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) -#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) -/*! @} */ - -/*! @name CLKCFG - Clock Configuration Register */ -/*! @{ */ -#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) -#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) -/*! CLK_PRSC - Clock Prescaler Value - * 0b00000010..Divide by 2 - */ -#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) -/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select - * 0b00..Disabled / Reset (default) - * 0b01..Card Clock - * 0b10..Receive Clock - * 0b11..ETU Clock (transmit clock) - */ -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) -/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select - * 0b00..Disabled / Reset (default) - * 0b01..Card Clock - * 0b10..Receive Clock - * 0b11..ETU Clock (transmit clock) - */ -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) -/*! @} */ - -/*! @name DIVISOR - Baud Rate Divisor Register */ -/*! @{ */ -#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) -#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) -/*! DIVISOR_VALUE - Divisor (F/D) Value - * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 - * 0b101110100..Divisor value for F = 372 and D = 1 (default) - */ -#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) -/*! @} */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define EMVSIM_CTRL_IC_MASK (0x1U) -#define EMVSIM_CTRL_IC_SHIFT (0U) -/*! IC - Inverse Convention - * 0b0..Direction convention transfers enabled (default) - * 0b1..Inverse convention transfers enabled - */ -#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) -#define EMVSIM_CTRL_ICM_MASK (0x2U) -#define EMVSIM_CTRL_ICM_SHIFT (1U) -/*! ICM - Initial Character Mode - * 0b0..Initial Character Mode disabled - * 0b1..Initial Character Mode enabled (default) - */ -#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) -#define EMVSIM_CTRL_ANACK_MASK (0x4U) -#define EMVSIM_CTRL_ANACK_SHIFT (2U) -/*! ANACK - Auto NACK Enable - * 0b0..NACK generation on errors disabled - * 0b1..NACK generation on errors enabled (default) - */ -#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) -#define EMVSIM_CTRL_ONACK_MASK (0x8U) -#define EMVSIM_CTRL_ONACK_SHIFT (3U) -/*! ONACK - Overrun NACK Enable - * 0b0..NACK generation on overrun is disabled (default) - * 0b1..NACK generation on overrun is enabled - */ -#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) -#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) -#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) -/*! FLSH_RX - Flush Receiver Bit - * 0b0..EMV SIM Receiver normal operation (default) - * 0b1..EMV SIM Receiver held in Reset - */ -#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) -#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) -#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) -/*! FLSH_TX - Flush Transmitter Bit - * 0b0..EMV SIM Transmitter normal operation (default) - * 0b1..EMV SIM Transmitter held in Reset - */ -#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) -#define EMVSIM_CTRL_SW_RST_MASK (0x400U) -#define EMVSIM_CTRL_SW_RST_SHIFT (10U) -/*! SW_RST - Software Reset Bit - * 0b0..EMV SIM Normal operation (default) - * 0b1..EMV SIM held in Reset - */ -#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) -#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) -#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) -/*! KILL_CLOCKS - Kill all internal clocks - * 0b0..EMV SIM input clock enabled (default) - * 0b1..EMV SIM input clock is disabled - */ -#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) -#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) -#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) -/*! DOZE_EN - Doze Enable - * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) - * 0b1..DOZE instruction has no effect on EMV SIM module - */ -#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) -#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) -#define EMVSIM_CTRL_STOP_EN_SHIFT (13U) -/*! STOP_EN - STOP Enable - * 0b0..STOP instruction shuts down all EMV SIM clocks (default) - * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) - */ -#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) -#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) -#define EMVSIM_CTRL_RCV_EN_SHIFT (16U) -/*! RCV_EN - Receiver Enable - * 0b0..EMV SIM Receiver disabled (default) - * 0b1..EMV SIM Receiver enabled - */ -#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) -#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) -#define EMVSIM_CTRL_XMT_EN_SHIFT (17U) -/*! XMT_EN - Transmitter Enable - * 0b0..EMV SIM Transmitter disabled (default) - * 0b1..EMV SIM Transmitter enabled - */ -#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) -#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) -#define EMVSIM_CTRL_RCVR_11_SHIFT (18U) -/*! RCVR_11 - Receiver 11 ETU Mode Enable - * 0b0..Receiver configured for 12 ETU operation mode (default) - * 0b1..Receiver configured for 11 ETU operation mode - */ -#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) -#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) -#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) -/*! RX_DMA_EN - Receive DMA Enable - * 0b0..No DMA Read Request asserted for Receiver (default) - * 0b1..DMA Read Request asserted for Receiver - */ -#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) -#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) -#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) -/*! TX_DMA_EN - Transmit DMA Enable - * 0b0..No DMA Write Request asserted for Transmitter (default) - * 0b1..DMA Write Request asserted for Transmitter - */ -#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) -#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) -#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) -/*! INV_CRC_VAL - Invert bits in the CRC Output Value - * 0b0..Bits in CRC Output value will not be inverted. - * 0b1..Bits in CRC Output value will be inverted. (default) - */ -#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) -#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) -#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) -/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip - * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) - * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} - */ -#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) -#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) -#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) -/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control - * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) - * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation - */ -#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) -#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) -#define EMVSIM_CTRL_CWT_EN_SHIFT (27U) -/*! CWT_EN - Character Wait Time Counter Enable - * 0b0..Character Wait time Counter is disabled (default) - * 0b1..Character Wait time counter is enabled - */ -#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) -#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) -#define EMVSIM_CTRL_LRC_EN_SHIFT (28U) -/*! LRC_EN - LRC Enable - * 0b0..8-bit Linear Redundancy Checking disabled (default) - * 0b1..8-bit Linear Redundancy Checking enabled - */ -#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) -#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) -#define EMVSIM_CTRL_CRC_EN_SHIFT (29U) -/*! CRC_EN - CRC Enable - * 0b0..16-bit Cyclic Redundancy Checking disabled (default) - * 0b1..16-bit Cyclic Redundancy Checking enabled - */ -#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) -#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) -#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) -/*! XMT_CRC_LRC - Transmit CRC or LRC Enable - * 0b0..No CRC or LRC value is transmitted (default) - * 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled) - */ -#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) -#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) -#define EMVSIM_CTRL_BWT_EN_SHIFT (31U) -/*! BWT_EN - Block Wait Time Counter Enable - * 0b0..Disable BWT, BGT Counters (default) - * 0b1..Enable BWT, BGT Counters - */ -#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) -/*! @} */ - -/*! @name INT_MASK - Interrupt Mask Register */ -/*! @{ */ -#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) -#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) -/*! RDT_IM - Receive Data Threshold Interrupt Mask - * 0b0..RDTF interrupt enabled - * 0b1..RDTF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) -#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) -#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) -/*! TC_IM - Transmit Complete Interrupt Mask - * 0b0..TCF interrupt enabled - * 0b1..TCF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) -#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) -#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) -/*! RFO_IM - Receive FIFO Overflow Interrupt Mask - * 0b0..RFO interrupt enabled - * 0b1..RFO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) -#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) -#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) -/*! ETC_IM - Early Transmit Complete Interrupt Mask - * 0b0..ETC interrupt enabled - * 0b1..ETC interrupt masked (default) - */ -#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) -#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) -#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) -/*! TFE_IM - Transmit FIFO Empty Interrupt Mask - * 0b0..TFE interrupt enabled - * 0b1..TFE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) -#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) -#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) -/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask - * 0b0..TNTE interrupt enabled - * 0b1..TNTE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) -#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) -#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) -/*! TFF_IM - Transmit FIFO Full Interrupt Mask - * 0b0..TFF interrupt enabled - * 0b1..TFF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) -#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) -#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) -/*! TDT_IM - Transmit Data Threshold Interrupt Mask - * 0b0..TDTF interrupt enabled - * 0b1..TDTF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) -#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) -#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) -/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask - * 0b0..GPCNT0_TO interrupt enabled - * 0b1..GPCNT0_TO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) -#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) -#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) -/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask - * 0b0..CWT_ERR interrupt enabled - * 0b1..CWT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) -#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) -/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask - * 0b0..RTE interrupt enabled - * 0b1..RTE interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) -#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) -#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) -/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask - * 0b0..BWT_ERR interrupt enabled - * 0b1..BWT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) -#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) -/*! BGT_ERR_IM - Block Guard Time Error Interrupt - * 0b0..BGT_ERR interrupt enabled - * 0b1..BGT_ERR interrupt masked (default) - */ -#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) -#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) -#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) -/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask - * 0b0..GPCNT1_TO interrupt enabled - * 0b1..GPCNT1_TO interrupt masked (default) - */ -#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) -#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) -#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) -/*! RX_DATA_IM - Receive Data Interrupt Mask - * 0b0..RX_DATA interrupt enabled - * 0b1..RX_DATA interrupt masked (default) - */ -#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) -#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) -#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) -/*! PEF_IM - Parity Error Interrupt Mask - * 0b0..PEF interrupt enabled - * 0b1..PEF interrupt masked (default) - */ -#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) -/*! @} */ - -/*! @name RX_THD - Receiver Threshold Register */ -/*! @{ */ -#define EMVSIM_RX_THD_RDT_MASK (0xFU) -#define EMVSIM_RX_THD_RDT_SHIFT (0U) -#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) -#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) -#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) -/*! RNCK_THD - Receiver NACK Threshold Value - * 0b0000..Zero Threshold. RTE will not be set - */ -#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) -/*! @} */ - -/*! @name TX_THD - Transmitter Threshold Register */ -/*! @{ */ -#define EMVSIM_TX_THD_TDT_MASK (0xFU) -#define EMVSIM_TX_THD_TDT_SHIFT (0U) -#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) -#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) -#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) -/*! TNCK_THD - Transmitter NACK Threshold Value - * 0b0000..TNTE will never be set; retransmission after NACK reception is disabled. - * 0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs. - * 0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs. - * 0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs. - * 0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs. - */ -#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) -/*! @} */ - -/*! @name RX_STATUS - Receive Status Register */ -/*! @{ */ -#define EMVSIM_RX_STATUS_RFO_MASK (0x1U) -#define EMVSIM_RX_STATUS_RFO_SHIFT (0U) -/*! RFO - Receive FIFO Overflow Flag - * 0b0..No overrun error has occurred (default) - * 0b1..A byte was received when the received FIFO was already full - */ -#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) -#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) -#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) -/*! RX_DATA - Receive Data Interrupt Flag - * 0b0..No new byte is received - * 0b1..New byte is received ans stored in Receive FIFO - */ -#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) -#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) -#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) -/*! RDTF - Receive Data Threshold Interrupt Flag - * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). - * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. - */ -#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) -#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) -#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) -/*! LRC_OK - LRC Check OK Flag - * 0b0..Current LRC value does not match remainder. - * 0b1..Current calculated LRC value matches the expected result (i.e. zero). - */ -#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) -#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) -#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) -/*! CRC_OK - CRC Check OK Flag - * 0b0..Current CRC value does not match remainder. - * 0b1..Current calculated CRC value matches the expected result. - */ -#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) -#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) -#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) -/*! CWT_ERR - Character Wait Time Error Flag - * 0b0..No CWT violation has occurred (default). - * 0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT. - */ -#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) -#define EMVSIM_RX_STATUS_RTE_MASK (0x200U) -#define EMVSIM_RX_STATUS_RTE_SHIFT (9U) -/*! RTE - Received NACK Threshold Error Flag - * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] - * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] - */ -#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) -#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) -#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) -/*! BWT_ERR - Block Wait Time Error Flag - * 0b0..Block wait time not exceeded - * 0b1..Block wait time was exceeded - */ -#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) -#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) -#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) -/*! BGT_ERR - Block Guard Time Error Flag - * 0b0..Block guard time was sufficient - * 0b1..Block guard time was too small - */ -#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) -#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) -#define EMVSIM_RX_STATUS_PEF_SHIFT (12U) -/*! PEF - Parity Error Flag - * 0b0..No parity error detected - * 0b1..Parity error detected - */ -#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) -#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) -#define EMVSIM_RX_STATUS_FEF_SHIFT (13U) -/*! FEF - Frame Error Flag - * 0b0..No frame error detected - * 0b1..Frame error detected - */ -#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) -#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) -#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) -#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) -#define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) -#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) -/*! RX_CNT - Receive FIFO Byte Count - * 0b0000..FIFO is emtpy - */ -#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) -/*! @} */ - -/*! @name TX_STATUS - Transmitter Status Register */ -/*! @{ */ -#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) -#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) -/*! TNTE - Transmit NACK Threshold Error Flag - * 0b0..Transmit NACK threshold has not been reached (default) - * 0b1..Transmit NACK threshold reached; transmitter frozen - */ -#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) -#define EMVSIM_TX_STATUS_TFE_MASK (0x8U) -#define EMVSIM_TX_STATUS_TFE_SHIFT (3U) -/*! TFE - Transmit FIFO Empty Flag - * 0b0..Transmit FIFO is not empty - * 0b1..Transmit FIFO is empty (default) - */ -#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) -#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) -#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) -/*! ETCF - Early Transmit Complete Flag - * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) - */ -#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) -#define EMVSIM_TX_STATUS_TCF_MASK (0x20U) -#define EMVSIM_TX_STATUS_TCF_SHIFT (5U) -/*! TCF - Transmit Complete Flag - * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) - */ -#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) -#define EMVSIM_TX_STATUS_TFF_MASK (0x40U) -#define EMVSIM_TX_STATUS_TFF_SHIFT (6U) -/*! TFF - Transmit FIFO Full Flag - * 0b0..Transmit FIFO Full condition has not occurred (default) - * 0b1..A Transmit FIFO Full condition has occurred - */ -#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) -#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) -#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) -/*! TDTF - Transmit Data Threshold Flag - * 0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared - * 0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default) - */ -#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) -#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) -#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) -/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag - * 0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT0_VAL value - */ -#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) -#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) -#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) -/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag - * 0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT1_VAL value - */ -#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) -#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) -#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) -#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) -#define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) -#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) -/*! TX_CNT - Transmit FIFO Byte Count - * 0b0000..FIFO is emtpy - */ -#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) -/*! @} */ - -/*! @name PCSR - Port Control and Status Register */ -/*! @{ */ -#define EMVSIM_PCSR_SAPD_MASK (0x1U) -#define EMVSIM_PCSR_SAPD_SHIFT (0U) -/*! SAPD - Auto Power Down Enable - * 0b0..Auto power down disabled (default) - * 0b1..Auto power down enabled - */ -#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) -#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) -#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) -/*! SVCC_EN - Vcc Enable for Smart Card - * 0b0..Smart Card Voltage disabled (default) - * 0b1..Smart Card Voltage enabled - */ -#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) -#define EMVSIM_PCSR_VCCENP_MASK (0x4U) -#define EMVSIM_PCSR_VCCENP_SHIFT (2U) -/*! VCCENP - VCC Enable Polarity Control - * 0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged. - * 0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted. - */ -#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) -#define EMVSIM_PCSR_SRST_MASK (0x8U) -#define EMVSIM_PCSR_SRST_SHIFT (3U) -/*! SRST - Reset to Smart Card - * 0b0..Smart Card Reset is asserted (default) - * 0b1..Smart Card Reset is de-asserted - */ -#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) -#define EMVSIM_PCSR_SCEN_MASK (0x10U) -#define EMVSIM_PCSR_SCEN_SHIFT (4U) -/*! SCEN - Clock Enable for Smart Card - * 0b0..Smart Card Clock Disabled - * 0b1..Smart Card Clock Enabled - */ -#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) -#define EMVSIM_PCSR_SCSP_MASK (0x20U) -#define EMVSIM_PCSR_SCSP_SHIFT (5U) -/*! SCSP - Smart Card Clock Stop Polarity - * 0b0..Clock is logic 0 when stopped by SCEN - * 0b1..Clock is logic 1 when stopped by SCEN - */ -#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) -#define EMVSIM_PCSR_SPD_MASK (0x80U) -#define EMVSIM_PCSR_SPD_SHIFT (7U) -/*! SPD - Auto Power Down Control - * 0b0..No effect (default) - * 0b1..Start Auto Powerdown or Power Down is in progress - */ -#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) -#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) -#define EMVSIM_PCSR_SPDIM_SHIFT (24U) -/*! SPDIM - Smart Card Presence Detect Interrupt Mask - * 0b0..SIM presence detect interrupt is enabled - * 0b1..SIM presence detect interrupt is masked (default) - */ -#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) -#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) -#define EMVSIM_PCSR_SPDIF_SHIFT (25U) -/*! SPDIF - Smart Card Presence Detect Interrupt Flag - * 0b0..No insertion or removal of Smart Card detected on Port (default) - * 0b1..Insertion or removal of Smart Card detected on Port - */ -#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) -#define EMVSIM_PCSR_SPDP_MASK (0x4000000U) -#define EMVSIM_PCSR_SPDP_SHIFT (26U) -/*! SPDP - Smart Card Presence Detect Pin Status - * 0b0..SIM Presence Detect pin is logic low - * 0b1..SIM Presence Detectpin is logic high - */ -#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) -#define EMVSIM_PCSR_SPDES_MASK (0x8000000U) -#define EMVSIM_PCSR_SPDES_SHIFT (27U) -/*! SPDES - SIM Presence Detect Edge Select - * 0b0..Falling edge on the pin (default) - * 0b1..Rising edge on the pin - */ -#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) -/*! @} */ - -/*! @name RX_BUF - Receive Data Read Buffer */ -/*! @{ */ -#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) -#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) -#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) -/*! @} */ - -/*! @name TX_BUF - Transmit Data Buffer */ -/*! @{ */ -#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) -#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) -#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) -/*! @} */ - -/*! @name TX_GETU - Transmitter Guard ETU Value Register */ -/*! @{ */ -#define EMVSIM_TX_GETU_GETU_MASK (0xFFU) -#define EMVSIM_TX_GETU_GETU_SHIFT (0U) -/*! GETU - Transmitter Guard Time Value in ETU - * 0b00000000..no additional ETUs inserted (default) - * 0b00000001..1 additional ETU inserted - * 0b11111110..254 additional ETUs inserted - * 0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one - */ -#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) -/*! @} */ - -/*! @name CWT_VAL - Character Wait Time Value Register */ -/*! @{ */ -#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) -#define EMVSIM_CWT_VAL_CWT_SHIFT (0U) -#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) -/*! @} */ - -/*! @name BWT_VAL - Block Wait Time Value Register */ -/*! @{ */ -#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) -#define EMVSIM_BWT_VAL_BWT_SHIFT (0U) -#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) -/*! @} */ - -/*! @name BGT_VAL - Block Guard Time Value Register */ -/*! @{ */ -#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) -#define EMVSIM_BGT_VAL_BGT_SHIFT (0U) -#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) -/*! @} */ - -/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ -/*! @{ */ -#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) -#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) -#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) -/*! @} */ - -/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ -/*! @{ */ -#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) -#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) -#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EMVSIM_Register_Masks */ - - -/* EMVSIM - Peripheral instance base addresses */ -/** Peripheral EMVSIM0 base address */ -#define EMVSIM0_BASE (0x40038000u) -/** Peripheral EMVSIM0 base pointer */ -#define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) -/** Array initializer of EMVSIM peripheral base addresses */ -#define EMVSIM_BASE_ADDRS { EMVSIM0_BASE } -/** Array initializer of EMVSIM peripheral base pointers */ -#define EMVSIM_BASE_PTRS { EMVSIM0 } -/** Interrupt vectors for the EMVSIM peripheral type */ -#define EMVSIM_IRQS { EMVSIM0_IRQn } - -/*! - * @} - */ /* end of group EMVSIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EVENT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EVENT_Peripheral_Access_Layer EVENT Peripheral Access Layer - * @{ - */ - -/** EVENT - Register Layout Typedef */ -typedef struct { - __IO uint32_t INTPTEN; /**< Interrupt Enable Register, offset: 0x0 */ - __IO uint32_t INTPTPEND; /**< Interrupt Pengding Register, offset: 0x4 */ - __IO uint32_t INTPTPENDSET; /**< Set Interrupt Pengding Register, offset: 0x8 */ - __IO uint32_t INTPTPENDCLEAR; /**< Clear Interrupt Pengding Register, offset: 0xC */ - __IO uint32_t INTPTSECURE; /**< Interrupt Secure Register, offset: 0x10 */ - __IO uint32_t INTPTPRI[4]; /**< Interrupt Priority 0 Register..Interrupt Priority 3 Register, array offset: 0x14, array step: 0x4 */ - __IO uint32_t INTPRIBASE; /**< Interrupt Priority Base, offset: 0x24 */ - __I uint32_t INTPTENACTIVE; /**< Interrupt Active Register, offset: 0x28 */ - __I uint32_t INTACTPRI[4]; /**< Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register, array offset: 0x2C, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t EVENTEN; /**< Event Enable Register, offset: 0x40 */ - __IO uint32_t EVENTPEND; /**< Event Pengding Register, offset: 0x44 */ - __IO uint32_t EVTPENDSET; /**< Set Event Pengding Register, offset: 0x48 */ - __IO uint32_t EVTPENDCLEAR; /**< Clear Event Pengding Register, offset: 0x4C */ - uint8_t RESERVED_1[48]; - __IO uint32_t SLPCTRL; /**< Sleep Control Register, offset: 0x80 */ - __IO uint32_t SLPSTATUS; /**< Sleep Status Register, offset: 0x84 */ -} EVENT_Type; - -/* ---------------------------------------------------------------------------- - -- EVENT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EVENT_Register_Masks EVENT Register Masks - * @{ - */ - -/*! @name INTPTEN - Interrupt Enable Register */ -/*! @{ */ -#define EVENT_INTPTEN_IEN_MASK (0xFFFFFFFFU) -#define EVENT_INTPTEN_IEN_SHIFT (0U) -/*! IEN - Interrupt n Enable - * 0b00000000000000000000000000000000..Interrupt n is disabled. - * 0b00000000000000000000000000000001..Interrupt n is enabled. - */ -#define EVENT_INTPTEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTEN_IEN_SHIFT)) & EVENT_INTPTEN_IEN_MASK) -/*! @} */ - -/*! @name INTPTPEND - Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPEND_IPEND_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPEND_IPEND_SHIFT (0U) -/*! IPEND - Interrupt n Pending - * 0b00000000000000000000000000000000..Interrupt n is not pending. - * 0b00000000000000000000000000000001..Interrupt n is pending. - */ -#define EVENT_INTPTPEND_IPEND(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPEND_IPEND_SHIFT)) & EVENT_INTPTPEND_IPEND_MASK) -/*! @} */ - -/*! @name INTPTPENDSET - Set Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPENDSET_IPENDSET_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPENDSET_IPENDSET_SHIFT (0U) -/*! IPENDSET - Set Interrupt n Pending - * 0b00000000000000000000000000000000..Not set interrupt n in pending status - * 0b00000000000000000000000000000001..Set interrupt n in pending status. - */ -#define EVENT_INTPTPENDSET_IPENDSET(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDSET_IPENDSET_SHIFT)) & EVENT_INTPTPENDSET_IPENDSET_MASK) -/*! @} */ - -/*! @name INTPTPENDCLEAR - Clear Interrupt Pengding Register */ -/*! @{ */ -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK (0xFFFFFFFFU) -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT (0U) -/*! IPENDCLEAR - Clear Interrupt n out of Pending - * 0b00000000000000000000000000000000..Not clear interrupt n out of pending status - * 0b00000000000000000000000000000001..Clear interrupt n out of pending status. - */ -#define EVENT_INTPTPENDCLEAR_IPENDCLEAR(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT)) & EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK) -/*! @} */ - -/*! @name INTPTSECURE - Interrupt Secure Register */ -/*! @{ */ -#define EVENT_INTPTSECURE_ISECURE_MASK (0xFFFFFFFFU) -#define EVENT_INTPTSECURE_ISECURE_SHIFT (0U) -/*! ISECURE - Set secure feature of Interrupt n - * 0b00000000000000000000000000000000..Set interrupt n out of security - * 0b00000000000000000000000000000001..Set interrupt n in secruity. - */ -#define EVENT_INTPTSECURE_ISECURE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTSECURE_ISECURE_SHIFT)) & EVENT_INTPTSECURE_ISECURE_MASK) -/*! @} */ - -/*! @name INTPTPRI - Interrupt Priority 0 Register..Interrupt Priority 3 Register */ -/*! @{ */ -#define EVENT_INTPTPRI_IPRI0_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI0_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI0(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI0_SHIFT)) & EVENT_INTPTPRI_IPRI0_MASK) -#define EVENT_INTPTPRI_IPRI8_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI8_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI8(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI8_SHIFT)) & EVENT_INTPTPRI_IPRI8_MASK) -#define EVENT_INTPTPRI_IPRI16_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI16_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI16(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI16_SHIFT)) & EVENT_INTPTPRI_IPRI16_MASK) -#define EVENT_INTPTPRI_IPRI24_MASK (0x7U) -#define EVENT_INTPTPRI_IPRI24_SHIFT (0U) -#define EVENT_INTPTPRI_IPRI24(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI24_SHIFT)) & EVENT_INTPTPRI_IPRI24_MASK) -#define EVENT_INTPTPRI_IPRI1_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI1_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI1(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI1_SHIFT)) & EVENT_INTPTPRI_IPRI1_MASK) -#define EVENT_INTPTPRI_IPRI9_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI9_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI9(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI9_SHIFT)) & EVENT_INTPTPRI_IPRI9_MASK) -#define EVENT_INTPTPRI_IPRI17_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI17_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI17(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI17_SHIFT)) & EVENT_INTPTPRI_IPRI17_MASK) -#define EVENT_INTPTPRI_IPRI25_MASK (0x70U) -#define EVENT_INTPTPRI_IPRI25_SHIFT (4U) -#define EVENT_INTPTPRI_IPRI25(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI25_SHIFT)) & EVENT_INTPTPRI_IPRI25_MASK) -#define EVENT_INTPTPRI_IPRI2_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI2_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI2(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI2_SHIFT)) & EVENT_INTPTPRI_IPRI2_MASK) -#define EVENT_INTPTPRI_IPRI10_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI10_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI10(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI10_SHIFT)) & EVENT_INTPTPRI_IPRI10_MASK) -#define EVENT_INTPTPRI_IPRI18_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI18_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI18(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI18_SHIFT)) & EVENT_INTPTPRI_IPRI18_MASK) -#define EVENT_INTPTPRI_IPRI26_MASK (0x700U) -#define EVENT_INTPTPRI_IPRI26_SHIFT (8U) -#define EVENT_INTPTPRI_IPRI26(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI26_SHIFT)) & EVENT_INTPTPRI_IPRI26_MASK) -#define EVENT_INTPTPRI_IPRI3_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI3_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI3(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI3_SHIFT)) & EVENT_INTPTPRI_IPRI3_MASK) -#define EVENT_INTPTPRI_IPRI11_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI11_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI11(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI11_SHIFT)) & EVENT_INTPTPRI_IPRI11_MASK) -#define EVENT_INTPTPRI_IPRI19_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI19_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI19(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI19_SHIFT)) & EVENT_INTPTPRI_IPRI19_MASK) -#define EVENT_INTPTPRI_IPRI27_MASK (0x7000U) -#define EVENT_INTPTPRI_IPRI27_SHIFT (12U) -#define EVENT_INTPTPRI_IPRI27(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI27_SHIFT)) & EVENT_INTPTPRI_IPRI27_MASK) -#define EVENT_INTPTPRI_IPRI4_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI4_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI4(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI4_SHIFT)) & EVENT_INTPTPRI_IPRI4_MASK) -#define EVENT_INTPTPRI_IPRI12_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI12_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI12(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI12_SHIFT)) & EVENT_INTPTPRI_IPRI12_MASK) -#define EVENT_INTPTPRI_IPRI20_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI20_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI20(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI20_SHIFT)) & EVENT_INTPTPRI_IPRI20_MASK) -#define EVENT_INTPTPRI_IPRI28_MASK (0x70000U) -#define EVENT_INTPTPRI_IPRI28_SHIFT (16U) -#define EVENT_INTPTPRI_IPRI28(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI28_SHIFT)) & EVENT_INTPTPRI_IPRI28_MASK) -#define EVENT_INTPTPRI_IPRI5_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI5_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI5(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI5_SHIFT)) & EVENT_INTPTPRI_IPRI5_MASK) -#define EVENT_INTPTPRI_IPRI13_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI13_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI13(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI13_SHIFT)) & EVENT_INTPTPRI_IPRI13_MASK) -#define EVENT_INTPTPRI_IPRI21_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI21_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI21(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI21_SHIFT)) & EVENT_INTPTPRI_IPRI21_MASK) -#define EVENT_INTPTPRI_IPRI29_MASK (0x700000U) -#define EVENT_INTPTPRI_IPRI29_SHIFT (20U) -#define EVENT_INTPTPRI_IPRI29(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI29_SHIFT)) & EVENT_INTPTPRI_IPRI29_MASK) -#define EVENT_INTPTPRI_IPRI6_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI6_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI6(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI6_SHIFT)) & EVENT_INTPTPRI_IPRI6_MASK) -#define EVENT_INTPTPRI_IPRI14_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI14_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI14(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI14_SHIFT)) & EVENT_INTPTPRI_IPRI14_MASK) -#define EVENT_INTPTPRI_IPRI22_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI22_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI22(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI22_SHIFT)) & EVENT_INTPTPRI_IPRI22_MASK) -#define EVENT_INTPTPRI_IPRI30_MASK (0x7000000U) -#define EVENT_INTPTPRI_IPRI30_SHIFT (24U) -#define EVENT_INTPTPRI_IPRI30(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI30_SHIFT)) & EVENT_INTPTPRI_IPRI30_MASK) -#define EVENT_INTPTPRI_IPRI7_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI7_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI7(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI7_SHIFT)) & EVENT_INTPTPRI_IPRI7_MASK) -#define EVENT_INTPTPRI_IPRI15_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI15_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI15(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI15_SHIFT)) & EVENT_INTPTPRI_IPRI15_MASK) -#define EVENT_INTPTPRI_IPRI23_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI23_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI23(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI23_SHIFT)) & EVENT_INTPTPRI_IPRI23_MASK) -#define EVENT_INTPTPRI_IPRI31_MASK (0x70000000U) -#define EVENT_INTPTPRI_IPRI31_SHIFT (28U) -#define EVENT_INTPTPRI_IPRI31(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI31_SHIFT)) & EVENT_INTPTPRI_IPRI31_MASK) -/*! @} */ - -/* The count of EVENT_INTPTPRI */ -#define EVENT_INTPTPRI_COUNT (4U) - -/*! @name INTPRIBASE - Interrupt Priority Base */ -/*! @{ */ -#define EVENT_INTPRIBASE_IPBASE_MASK (0xFU) -#define EVENT_INTPRIBASE_IPBASE_SHIFT (0U) -#define EVENT_INTPRIBASE_IPBASE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPRIBASE_IPBASE_SHIFT)) & EVENT_INTPRIBASE_IPBASE_MASK) -/*! @} */ - -/*! @name INTPTENACTIVE - Interrupt Active Register */ -/*! @{ */ -#define EVENT_INTPTENACTIVE_IACTIVE_MASK (0xFFFFFFFFU) -#define EVENT_INTPTENACTIVE_IACTIVE_SHIFT (0U) -/*! IACTIVE - Interrupt n Enable - * 0b00000000000000000000000000000000..Interrupt n is not active. - * 0b00000000000000000000000000000001..Interrupt n is active.. - */ -#define EVENT_INTPTENACTIVE_IACTIVE(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTENACTIVE_IACTIVE_SHIFT)) & EVENT_INTPTENACTIVE_IACTIVE_MASK) -/*! @} */ - -/*! @name INTACTPRI - Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register */ -/*! @{ */ -#define EVENT_INTACTPRI_IAPRI0_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI0_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI0(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI0_SHIFT)) & EVENT_INTACTPRI_IAPRI0_MASK) -#define EVENT_INTACTPRI_IAPRI8_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI8_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI8(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI8_SHIFT)) & EVENT_INTACTPRI_IAPRI8_MASK) -#define EVENT_INTACTPRI_IAPRI16_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI16_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI16(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI16_SHIFT)) & EVENT_INTACTPRI_IAPRI16_MASK) -#define EVENT_INTACTPRI_IAPRI24_MASK (0x7U) -#define EVENT_INTACTPRI_IAPRI24_SHIFT (0U) -#define EVENT_INTACTPRI_IAPRI24(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI24_SHIFT)) & EVENT_INTACTPRI_IAPRI24_MASK) -#define EVENT_INTACTPRI_IAPRI1_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI1_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI1(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI1_SHIFT)) & EVENT_INTACTPRI_IAPRI1_MASK) -#define EVENT_INTACTPRI_IAPRI9_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI9_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI9(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI9_SHIFT)) & EVENT_INTACTPRI_IAPRI9_MASK) -#define EVENT_INTACTPRI_IAPRI17_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI17_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI17(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI17_SHIFT)) & EVENT_INTACTPRI_IAPRI17_MASK) -#define EVENT_INTACTPRI_IAPRI25_MASK (0x70U) -#define EVENT_INTACTPRI_IAPRI25_SHIFT (4U) -#define EVENT_INTACTPRI_IAPRI25(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI25_SHIFT)) & EVENT_INTACTPRI_IAPRI25_MASK) -#define EVENT_INTACTPRI_IAPRI2_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI2_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI2(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI2_SHIFT)) & EVENT_INTACTPRI_IAPRI2_MASK) -#define EVENT_INTACTPRI_IAPRI10_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI10_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI10(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI10_SHIFT)) & EVENT_INTACTPRI_IAPRI10_MASK) -#define EVENT_INTACTPRI_IAPRI18_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI18_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI18(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI18_SHIFT)) & EVENT_INTACTPRI_IAPRI18_MASK) -#define EVENT_INTACTPRI_IAPRI26_MASK (0x700U) -#define EVENT_INTACTPRI_IAPRI26_SHIFT (8U) -#define EVENT_INTACTPRI_IAPRI26(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI26_SHIFT)) & EVENT_INTACTPRI_IAPRI26_MASK) -#define EVENT_INTACTPRI_IAPRI3_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI3_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI3(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI3_SHIFT)) & EVENT_INTACTPRI_IAPRI3_MASK) -#define EVENT_INTACTPRI_IAPRI11_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI11_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI11(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI11_SHIFT)) & EVENT_INTACTPRI_IAPRI11_MASK) -#define EVENT_INTACTPRI_IAPRI19_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI19_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI19(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI19_SHIFT)) & EVENT_INTACTPRI_IAPRI19_MASK) -#define EVENT_INTACTPRI_IAPRI27_MASK (0x7000U) -#define EVENT_INTACTPRI_IAPRI27_SHIFT (12U) -#define EVENT_INTACTPRI_IAPRI27(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI27_SHIFT)) & EVENT_INTACTPRI_IAPRI27_MASK) -#define EVENT_INTACTPRI_IAPRI4_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI4_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI4(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI4_SHIFT)) & EVENT_INTACTPRI_IAPRI4_MASK) -#define EVENT_INTACTPRI_IAPRI12_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI12_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI12(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI12_SHIFT)) & EVENT_INTACTPRI_IAPRI12_MASK) -#define EVENT_INTACTPRI_IAPRI20_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI20_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI20(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI20_SHIFT)) & EVENT_INTACTPRI_IAPRI20_MASK) -#define EVENT_INTACTPRI_IAPRI28_MASK (0x70000U) -#define EVENT_INTACTPRI_IAPRI28_SHIFT (16U) -#define EVENT_INTACTPRI_IAPRI28(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI28_SHIFT)) & EVENT_INTACTPRI_IAPRI28_MASK) -#define EVENT_INTACTPRI_IAPRI5_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI5_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI5(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI5_SHIFT)) & EVENT_INTACTPRI_IAPRI5_MASK) -#define EVENT_INTACTPRI_IAPRI13_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI13_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI13(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI13_SHIFT)) & EVENT_INTACTPRI_IAPRI13_MASK) -#define EVENT_INTACTPRI_IAPRI21_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI21_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI21(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI21_SHIFT)) & EVENT_INTACTPRI_IAPRI21_MASK) -#define EVENT_INTACTPRI_IAPRI29_MASK (0x700000U) -#define EVENT_INTACTPRI_IAPRI29_SHIFT (20U) -#define EVENT_INTACTPRI_IAPRI29(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI29_SHIFT)) & EVENT_INTACTPRI_IAPRI29_MASK) -#define EVENT_INTACTPRI_IAPRI6_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI6_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI6(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI6_SHIFT)) & EVENT_INTACTPRI_IAPRI6_MASK) -#define EVENT_INTACTPRI_IAPRI14_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI14_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI14(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI14_SHIFT)) & EVENT_INTACTPRI_IAPRI14_MASK) -#define EVENT_INTACTPRI_IAPRI22_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI22_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI22(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI22_SHIFT)) & EVENT_INTACTPRI_IAPRI22_MASK) -#define EVENT_INTACTPRI_IAPRI30_MASK (0x7000000U) -#define EVENT_INTACTPRI_IAPRI30_SHIFT (24U) -#define EVENT_INTACTPRI_IAPRI30(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI30_SHIFT)) & EVENT_INTACTPRI_IAPRI30_MASK) -#define EVENT_INTACTPRI_IAPRI7_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI7_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI7(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI7_SHIFT)) & EVENT_INTACTPRI_IAPRI7_MASK) -#define EVENT_INTACTPRI_IAPRI15_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI15_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI15(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI15_SHIFT)) & EVENT_INTACTPRI_IAPRI15_MASK) -#define EVENT_INTACTPRI_IAPRI23_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI23_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI23(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI23_SHIFT)) & EVENT_INTACTPRI_IAPRI23_MASK) -#define EVENT_INTACTPRI_IAPRI31_MASK (0x70000000U) -#define EVENT_INTACTPRI_IAPRI31_SHIFT (28U) -#define EVENT_INTACTPRI_IAPRI31(x) (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI31_SHIFT)) & EVENT_INTACTPRI_IAPRI31_MASK) -/*! @} */ - -/* The count of EVENT_INTACTPRI */ -#define EVENT_INTACTPRI_COUNT (4U) - -/*! @name EVENTEN - Event Enable Register */ -/*! @{ */ -#define EVENT_EVENTEN_EEN_MASK (0xFFFFFFFFU) -#define EVENT_EVENTEN_EEN_SHIFT (0U) -/*! EEN - Event n Enable - * 0b00000000000000000000000000000000..Event n is disabled. - * 0b00000000000000000000000000000001..Event n is enabled. - */ -#define EVENT_EVENTEN_EEN(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTEN_EEN_SHIFT)) & EVENT_EVENTEN_EEN_MASK) -/*! @} */ - -/*! @name EVENTPEND - Event Pengding Register */ -/*! @{ */ -#define EVENT_EVENTPEND_EPEND_MASK (0xFFFFFFFFU) -#define EVENT_EVENTPEND_EPEND_SHIFT (0U) -/*! EPEND - Event n Pending - * 0b00000000000000000000000000000000..Event n is not pending. - * 0b00000000000000000000000000000001..Event n is pending. - */ -#define EVENT_EVENTPEND_EPEND(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTPEND_EPEND_SHIFT)) & EVENT_EVENTPEND_EPEND_MASK) -/*! @} */ - -/*! @name EVTPENDSET - Set Event Pengding Register */ -/*! @{ */ -#define EVENT_EVTPENDSET_EPENDSET_MASK (0xFFFFFFFFU) -#define EVENT_EVTPENDSET_EPENDSET_SHIFT (0U) -/*! EPENDSET - Set Event n Pending - * 0b00000000000000000000000000000000..Not set event n in pending status - * 0b00000000000000000000000000000001..Set event n in pending status. - */ -#define EVENT_EVTPENDSET_EPENDSET(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDSET_EPENDSET_SHIFT)) & EVENT_EVTPENDSET_EPENDSET_MASK) -/*! @} */ - -/*! @name EVTPENDCLEAR - Clear Event Pengding Register */ -/*! @{ */ -#define EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK (0xFFFFFFFFU) -#define EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT (0U) -/*! EPENDCLEAR - Clear Event n out of Pending - * 0b00000000000000000000000000000000..Not clear event n out of pending status - * 0b00000000000000000000000000000001..Clear event n out of pending status. - */ -#define EVENT_EVTPENDCLEAR_EPENDCLEAR(x) (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT)) & EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK) -/*! @} */ - -/*! @name SLPCTRL - Sleep Control Register */ -/*! @{ */ -#define EVENT_SLPCTRL_SLPCTRL_MASK (0x3U) -#define EVENT_SLPCTRL_SLPCTRL_SHIFT (0U) -/*! SLPCTRL - Sleep Mode Control - * 0b01..Sleep enable - * 0b10..Deep sleep enable - */ -#define EVENT_SLPCTRL_SLPCTRL(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SLPCTRL_SHIFT)) & EVENT_SLPCTRL_SLPCTRL_MASK) -#define EVENT_SLPCTRL_SYSRSTREQST_MASK (0x80000000U) -#define EVENT_SLPCTRL_SYSRSTREQST_SHIFT (31U) -/*! SYSRSTREQST - System Reset Request - * 0b0..Do not send system reset request. - * 0b1..Send system reset request - */ -#define EVENT_SLPCTRL_SYSRSTREQST(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SYSRSTREQST_SHIFT)) & EVENT_SLPCTRL_SYSRSTREQST_MASK) -/*! @} */ - -/*! @name SLPSTATUS - Sleep Status Register */ -/*! @{ */ -#define EVENT_SLPSTATUS_SLPSTAT_MASK (0x3U) -#define EVENT_SLPSTATUS_SLPSTAT_SHIFT (0U) -/*! SLPSTAT - Sleep Status - * 0b01..In sleep mode - * 0b10..In deep sleep mode - */ -#define EVENT_SLPSTATUS_SLPSTAT(x) (((uint32_t)(((uint32_t)(x)) << EVENT_SLPSTATUS_SLPSTAT_SHIFT)) & EVENT_SLPSTATUS_SLPSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EVENT_Register_Masks */ - - -/* EVENT - Peripheral instance base addresses */ -/** Peripheral EVENT1 base address */ -#define EVENT1_BASE (0x4101F000u) -/** Peripheral EVENT1 base pointer */ -#define EVENT1 ((EVENT_Type *)EVENT1_BASE) -/** Array initializer of EVENT peripheral base addresses */ -#define EVENT_BASE_ADDRS { EVENT1_BASE } -/** Array initializer of EVENT peripheral base pointers */ -#define EVENT_BASE_PTRS { EVENT1 } - -/*! - * @} - */ /* end of group EVENT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer - * @{ - */ - -/** EWM - Register Layout Typedef */ -typedef struct { - __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ - __O uint8_t SERV; /**< Service Register, offset: 0x1 */ - __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ - __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ - uint8_t RESERVED_0[1]; - __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ -} EWM_Type; - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define EWM_CTRL_EWMEN_MASK (0x1U) -#define EWM_CTRL_EWMEN_SHIFT (0U) -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) -#define EWM_CTRL_ASSIN_MASK (0x2U) -#define EWM_CTRL_ASSIN_SHIFT (1U) -#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) -#define EWM_CTRL_INEN_MASK (0x4U) -#define EWM_CTRL_INEN_SHIFT (2U) -#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) -#define EWM_CTRL_INTEN_MASK (0x8U) -#define EWM_CTRL_INTEN_SHIFT (3U) -#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) -/*! @} */ - -/*! @name SERV - Service Register */ -/*! @{ */ -#define EWM_SERV_SERVICE_MASK (0xFFU) -#define EWM_SERV_SERVICE_SHIFT (0U) -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) -/*! @} */ - -/*! @name CMPL - Compare Low Register */ -/*! @{ */ -#define EWM_CMPL_COMPAREL_MASK (0xFFU) -#define EWM_CMPL_COMPAREL_SHIFT (0U) -#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) -/*! @} */ - -/*! @name CMPH - Compare High Register */ -/*! @{ */ -#define EWM_CMPH_COMPAREH_MASK (0xFFU) -#define EWM_CMPH_COMPAREH_SHIFT (0U) -#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) -/*! @} */ - -/*! @name CLKPRESCALER - Clock Prescaler Register */ -/*! @{ */ -#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) -#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) -#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EWM_Register_Masks */ - - -/* EWM - Peripheral instance base addresses */ -/** Peripheral EWM base address */ -#define EWM_BASE (0x40022000u) -/** Peripheral EWM base pointer */ -#define EWM ((EWM_Type *)EWM_BASE) -/** Array initializer of EWM peripheral base addresses */ -#define EWM_BASE_ADDRS { EWM_BASE } -/** Array initializer of EWM peripheral base pointers */ -#define EWM_BASE_PTRS { EWM } -/** Interrupt vectors for the EWM peripheral type */ -#define EWM_IRQS { EWM_IRQn } - -/*! - * @} - */ /* end of group EWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer - * @{ - */ - -/** FB - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0xC */ - __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ - __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ - __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ - } CS[6]; - uint8_t RESERVED_0[24]; - __IO uint32_t CSPMCR; /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */ -} FB_Type; - -/* ---------------------------------------------------------------------------- - -- FB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FB_Register_Masks FB Register Masks - * @{ - */ - -/*! @name CSAR - Chip Select Address Register */ -/*! @{ */ -#define FB_CSAR_BA_MASK (0xFFFF0000U) -#define FB_CSAR_BA_SHIFT (16U) -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) -/*! @} */ - -/* The count of FB_CSAR */ -#define FB_CSAR_COUNT (6U) - -/*! @name CSMR - Chip Select Mask Register */ -/*! @{ */ -#define FB_CSMR_V_MASK (0x1U) -#define FB_CSMR_V_SHIFT (0U) -/*! V - Valid - * 0b0..Chip-select is invalid. - * 0b1..Chip-select is valid. - */ -#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) -#define FB_CSMR_WP_MASK (0x100U) -#define FB_CSMR_WP_SHIFT (8U) -/*! WP - Write Protect - * 0b0..Write accesses are allowed. - * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. - */ -#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) -#define FB_CSMR_BAM_MASK (0xFFFF0000U) -#define FB_CSMR_BAM_SHIFT (16U) -/*! BAM - Base Address Mask - * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. - * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode. - */ -#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) -/*! @} */ - -/* The count of FB_CSMR */ -#define FB_CSMR_COUNT (6U) - -/*! @name CSCR - Chip Select Control Register */ -/*! @{ */ -#define FB_CSCR_BSTW_MASK (0x8U) -#define FB_CSCR_BSTW_SHIFT (3U) -/*! BSTW - Burst-Write Enable - * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. - * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. - */ -#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) -#define FB_CSCR_BSTR_MASK (0x10U) -#define FB_CSCR_BSTR_SHIFT (4U) -/*! BSTR - Burst-Read Enable - * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. - * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. - */ -#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) -#define FB_CSCR_BEM_MASK (0x20U) -#define FB_CSCR_BEM_SHIFT (5U) -/*! BEM - Byte-Enable Mode - * 0b0..FB_BE_B is asserted for data write only. - * 0b1..FB_BE_B is asserted for data read and write accesses. - */ -#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) -#define FB_CSCR_PS_MASK (0xC0U) -#define FB_CSCR_PS_SHIFT (6U) -/*! PS - Port Size - * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. - * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. - * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. - */ -#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) -#define FB_CSCR_AA_MASK (0x100U) -#define FB_CSCR_AA_SHIFT (8U) -/*! AA - Auto-Acknowledge Enable - * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. - * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS. - */ -#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) -#define FB_CSCR_BLS_MASK (0x200U) -#define FB_CSCR_BLS_SHIFT (9U) -/*! BLS - Byte-Lane Shift - * 0b0..Not shifted. Data is left-aligned on FB_AD. - * 0b1..Shifted. Data is right-aligned on FB_AD. - */ -#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) -#define FB_CSCR_WS_MASK (0xFC00U) -#define FB_CSCR_WS_SHIFT (10U) -#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) -#define FB_CSCR_WRAH_MASK (0x30000U) -#define FB_CSCR_WRAH_SHIFT (16U) -/*! WRAH - Write Address Hold or Deselect - * 0b00..1 cycle (default for all but FB_CS0_B) - * 0b01..2 cycles - * 0b10..3 cycles - * 0b11..4 cycles (default for FB_CS0_B) - */ -#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) -#define FB_CSCR_RDAH_MASK (0xC0000U) -#define FB_CSCR_RDAH_SHIFT (18U) -/*! RDAH - Read Address Hold or Deselect - * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. - * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. - * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. - * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. - */ -#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) -#define FB_CSCR_ASET_MASK (0x300000U) -#define FB_CSCR_ASET_SHIFT (20U) -/*! ASET - Address Setup - * 0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B). - * 0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted. - * 0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted. - * 0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ). - */ -#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) -#define FB_CSCR_EXTS_MASK (0x400000U) -#define FB_CSCR_EXTS_SHIFT (22U) -/*! EXTS - EXTS - * 0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle. - * 0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts. - */ -#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) -#define FB_CSCR_SWSEN_MASK (0x800000U) -#define FB_CSCR_SWSEN_SHIFT (23U) -/*! SWSEN - Secondary Wait State Enable - * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. - * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. - */ -#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) -#define FB_CSCR_SWS_MASK (0xFC000000U) -#define FB_CSCR_SWS_SHIFT (26U) -#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) -/*! @} */ - -/* The count of FB_CSCR */ -#define FB_CSCR_COUNT (6U) - -/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */ -/*! @{ */ -#define FB_CSPMCR_GROUP5_MASK (0xF000U) -#define FB_CSPMCR_GROUP5_SHIFT (12U) -/*! GROUP5 - FlexBus Signal Group 5 Multiplex control - * 0b0000..FB_TA_B - * 0b0001..FB_CS3_B. You must also write 1b to CSCR[AA]. - * 0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA]. - */ -#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) -#define FB_CSPMCR_GROUP4_MASK (0xF0000U) -#define FB_CSPMCR_GROUP4_SHIFT (16U) -/*! GROUP4 - FlexBus Signal Group 4 Multiplex control - * 0b0000..FB_TBST_B - * 0b0001..FB_CS2_B - * 0b0010..FB_BE_15_8_B - */ -#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) -#define FB_CSPMCR_GROUP3_MASK (0xF00000U) -#define FB_CSPMCR_GROUP3_SHIFT (20U) -/*! GROUP3 - FlexBus Signal Group 3 Multiplex control - * 0b0000..FB_CS5_B - * 0b0001..FB_TSIZ1 - * 0b0010..FB_BE_23_16_B - */ -#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) -#define FB_CSPMCR_GROUP2_MASK (0xF000000U) -#define FB_CSPMCR_GROUP2_SHIFT (24U) -/*! GROUP2 - FlexBus Signal Group 2 Multiplex control - * 0b0000..FB_CS4_B - * 0b0001..FB_TSIZ0 - * 0b0010..FB_BE_31_24_B - */ -#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) -#define FB_CSPMCR_GROUP1_MASK (0xF0000000U) -#define FB_CSPMCR_GROUP1_SHIFT (28U) -/*! GROUP1 - FlexBus Signal Group 1 Multiplex control - * 0b0000..FB_ALE - * 0b0001..FB_CS1_B - * 0b0010..FB_TS_B - */ -#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FB_Register_Masks */ - - -/* FB - Peripheral instance base addresses */ -/** Peripheral FB base address */ -#define FB_BASE (0x4000C000u) -/** Peripheral FB base pointer */ -#define FB ((FB_Type *)FB_BASE) -/** Array initializer of FB peripheral base addresses */ -#define FB_BASE_ADDRS { FB_BASE } -/** Array initializer of FB peripheral base pointers */ -#define FB_BASE_PTRS { FB } - -/*! - * @} - */ /* end of group FB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FGPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer - * @{ - */ - -/** FGPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} FGPIO_Type; - -/* ---------------------------------------------------------------------------- - -- FGPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FGPIO_Register_Masks FGPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -/*! @{ */ -#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define FGPIO_PDOR_PDO_SHIFT (0U) -#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) -/*! @} */ - -/*! @name PSOR - Port Set Output Register */ -/*! @{ */ -#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define FGPIO_PSOR_PTSO_SHIFT (0U) -#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) -/*! @} */ - -/*! @name PCOR - Port Clear Output Register */ -/*! @{ */ -#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define FGPIO_PCOR_PTCO_SHIFT (0U) -#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) -/*! @} */ - -/*! @name PTOR - Port Toggle Output Register */ -/*! @{ */ -#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define FGPIO_PTOR_PTTO_SHIFT (0U) -#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) -/*! @} */ - -/*! @name PDIR - Port Data Input Register */ -/*! @{ */ -#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define FGPIO_PDIR_PDI_SHIFT (0U) -#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) -/*! @} */ - -/*! @name PDDR - Port Data Direction Register */ -/*! @{ */ -#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define FGPIO_PDDR_PDD_SHIFT (0U) -#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FGPIO_Register_Masks */ - - -/* FGPIO - Peripheral instance base addresses */ -/** Peripheral FGPIOE base address */ -#define FGPIOE_BASE (0xF8000000u) -/** Peripheral FGPIOE base pointer */ -#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) -/** Array initializer of FGPIO peripheral base addresses */ -#define FGPIO_BASE_ADDRS { 0u, 0u, 0u, 0u, FGPIOE_BASE } -/** Array initializer of FGPIO peripheral base pointers */ -#define FGPIO_BASE_PTRS { (FGPIO_Type *)0u, (FGPIO_Type *)0u, (FGPIO_Type *)0u, (FGPIO_Type *)0u, FGPIOE } - -/*! - * @} - */ /* end of group FGPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer - * @{ - */ - -/** FLEXIO - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ - __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ - __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ - __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ - __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ - __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ - __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ - uint8_t RESERVED_2[12]; - __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ - uint8_t RESERVED_3[60]; - __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_4[96]; - __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_5[224]; - __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[96]; - __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ - uint8_t RESERVED_7[96]; - __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_8[96]; - __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ - uint8_t RESERVED_9[96]; - __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_10[96]; - __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ - uint8_t RESERVED_11[96]; - __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_12[352]; - __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_13[96]; - __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ - uint8_t RESERVED_14[96]; - __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ -} FLEXIO_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) -#define FLEXIO_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - * 0b0000000000000001..Supports state, logic and parallel modes. - */ -#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) -#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) -#define FLEXIO_VERID_MINOR_SHIFT (16U) -#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) -#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) -#define FLEXIO_VERID_MAJOR_SHIFT (24U) -#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) -#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) -#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) -#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) -#define FLEXIO_PARAM_TIMER_SHIFT (8U) -#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) -#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) -#define FLEXIO_PARAM_PIN_SHIFT (16U) -#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) -#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) -#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) -#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) -/*! @} */ - -/*! @name CTRL - FlexIO Control Register */ -/*! @{ */ -#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) -#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) -/*! FLEXEN - FlexIO Enable - * 0b0..FlexIO module is disabled. - * 0b1..FlexIO module is enabled. - */ -#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) -#define FLEXIO_CTRL_SWRST_MASK (0x2U) -#define FLEXIO_CTRL_SWRST_SHIFT (1U) -/*! SWRST - Software Reset - * 0b0..Software reset is disabled - * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. - */ -#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) -#define FLEXIO_CTRL_FASTACC_MASK (0x4U) -#define FLEXIO_CTRL_FASTACC_SHIFT (2U) -/*! FASTACC - Fast Access - * 0b0..Configures for normal register accesses to FlexIO - * 0b1..Configures for fast register accesses to FlexIO - */ -#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) -#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) -#define FLEXIO_CTRL_DBGE_SHIFT (30U) -/*! DBGE - Debug Enable - * 0b0..FlexIO is disabled in debug modes. - * 0b1..FlexIO is enabled in debug modes - */ -#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) -#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) -#define FLEXIO_CTRL_DOZEN_SHIFT (31U) -/*! DOZEN - Doze Enable - * 0b0..FlexIO enabled in Doze modes. - * 0b1..FlexIO disabled in Doze modes. - */ -#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) -/*! @} */ - -/*! @name PIN - Pin State Register */ -/*! @{ */ -#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) -#define FLEXIO_PIN_PDI_SHIFT (0U) -#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) -/*! @} */ - -/*! @name SHIFTSTAT - Shifter Status Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) -#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) -#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) -/*! @} */ - -/*! @name SHIFTERR - Shifter Error Register */ -/*! @{ */ -#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) -#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) -#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) -/*! @} */ - -/*! @name TIMSTAT - Timer Status Register */ -/*! @{ */ -#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) -#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) -#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) -/*! @} */ - -/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) -#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) -#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) -/*! @} */ - -/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) -#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) -#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) -/*! @} */ - -/*! @name TIMIEN - Timer Interrupt Enable Register */ -/*! @{ */ -#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) -#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) -#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) -/*! @} */ - -/*! @name SHIFTSDEN - Shifter Status DMA Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) -#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) -#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) -/*! @} */ - -/*! @name SHIFTSTATE - Shifter State Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) -#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) -#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) -/*! @} */ - -/*! @name SHIFTCTL - Shifter Control N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) -#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) -/*! SMOD - Shifter Mode - * 0b000..Disabled. - * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. - * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. - * 0b011..Reserved. - * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. - * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. - * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. - * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. - */ -#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) -#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) -#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) -/*! PINPOL - Shifter Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low - */ -#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) -#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) -#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) -#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) -/*! PINCFG - Shifter Pin Configuration - * 0b00..Shifter pin output disabled - * 0b01..Shifter pin open drain or bidirectional output enable - * 0b10..Shifter pin bidirectional output data - * 0b11..Shifter pin output - */ -#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) -#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) -#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) -/*! TIMPOL - Timer Polarity - * 0b0..Shift on posedge of Shift clock - * 0b1..Shift on negedge of Shift clock - */ -#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) -#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) -#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) -#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCTL */ -#define FLEXIO_SHIFTCTL_COUNT (8U) - -/*! @name SHIFTCFG - Shifter Configuration N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) -#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) -/*! SSTART - Shifter Start bit - * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable - * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift - * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 - * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 - */ -#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) -#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) -#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) -/*! SSTOP - Shifter Stop bit - * 0b00..Stop bit disabled for transmitter/receiver/match store - * 0b01..Reserved for transmitter/receiver/match store - * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 - * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 - */ -#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) -#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) -#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) -/*! INSRC - Input Source - * 0b0..Pin - * 0b1..Shifter N+1 Output - */ -#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) -#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) -#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) -#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCFG */ -#define FLEXIO_SHIFTCFG_COUNT (8U) - -/*! @name SHIFTBUF - Shifter Buffer N Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) -#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUF */ -#define FLEXIO_SHIFTBUF_COUNT (8U) - -/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBIS */ -#define FLEXIO_SHIFTBUFBIS_COUNT (8U) - -/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBYS */ -#define FLEXIO_SHIFTBUFBYS_COUNT (8U) - -/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBBS */ -#define FLEXIO_SHIFTBUFBBS_COUNT (8U) - -/*! @name TIMCTL - Timer Control N Register */ -/*! @{ */ -#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) -#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) -/*! TIMOD - Timer Mode - * 0b00..Timer Disabled. - * 0b01..Dual 8-bit counters baud mode. - * 0b10..Dual 8-bit counters PWM high mode. - * 0b11..Single 16-bit counter mode. - */ -#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) -#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) -#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) -/*! PINPOL - Timer Pin Polarity - * 0b0..Pin is active high - * 0b1..Pin is active low - */ -#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) -#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) -#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) -#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) -/*! PINCFG - Timer Pin Configuration - * 0b00..Timer pin output disabled - * 0b01..Timer pin open drain or bidirectional output enable - * 0b10..Timer pin bidirectional output data - * 0b11..Timer pin output - */ -#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) -#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) -#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) -/*! TRGSRC - Trigger Source - * 0b0..External trigger selected - * 0b1..Internal trigger selected - */ -#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) -#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) -#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) -/*! TRGPOL - Trigger Polarity - * 0b0..Trigger active high - * 0b1..Trigger active low - */ -#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) -#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) -#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) -#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCTL */ -#define FLEXIO_TIMCTL_COUNT (8U) - -/*! @name TIMCFG - Timer Configuration N Register */ -/*! @{ */ -#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) -#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) -/*! TSTART - Timer Start Bit - * 0b0..Start bit disabled - * 0b1..Start bit enabled - */ -#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) -#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) -#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) -/*! TSTOP - Timer Stop Bit - * 0b00..Stop bit disabled - * 0b01..Stop bit is enabled on timer compare - * 0b10..Stop bit is enabled on timer disable - * 0b11..Stop bit is enabled on timer compare and timer disable - */ -#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) -#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) -#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) -/*! TIMENA - Timer Enable - * 0b000..Timer always enabled - * 0b001..Timer enabled on Timer N-1 enable - * 0b010..Timer enabled on Trigger high - * 0b011..Timer enabled on Trigger high and Pin high - * 0b100..Timer enabled on Pin rising edge - * 0b101..Timer enabled on Pin rising edge and Trigger high - * 0b110..Timer enabled on Trigger rising edge - * 0b111..Timer enabled on Trigger rising or falling edge - */ -#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) -#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) -#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) -/*! TIMDIS - Timer Disable - * 0b000..Timer never disabled - * 0b001..Timer disabled on Timer N-1 disable - * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) - * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low - * 0b100..Timer disabled on Pin rising or falling edge - * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high - * 0b110..Timer disabled on Trigger falling edge - * 0b111..Reserved - */ -#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) -#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) -#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) -/*! TIMRST - Timer Reset - * 0b000..Timer never reset - * 0b001..Reserved - * 0b010..Timer reset on Timer Pin equal to Timer Output - * 0b011..Timer reset on Timer Trigger equal to Timer Output - * 0b100..Timer reset on Timer Pin rising edge - * 0b101..Reserved - * 0b110..Timer reset on Trigger rising edge - * 0b111..Timer reset on Trigger rising or falling edge - */ -#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) -#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) -#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) -/*! TIMDEC - Timer Decrement - * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. - * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. - * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. - * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. - */ -#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) -#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) -#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) -/*! TIMOUT - Timer Output - * 0b00..Timer output is logic one when enabled and is not affected by timer reset - * 0b01..Timer output is logic zero when enabled and is not affected by timer reset - * 0b10..Timer output is logic one when enabled and on timer reset - * 0b11..Timer output is logic zero when enabled and on timer reset - */ -#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCFG */ -#define FLEXIO_TIMCFG_COUNT (8U) - -/*! @name TIMCMP - Timer Compare N Register */ -/*! @{ */ -#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) -#define FLEXIO_TIMCMP_CMP_SHIFT (0U) -#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCMP */ -#define FLEXIO_TIMCMP_COUNT (8U) - -/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNBS */ -#define FLEXIO_SHIFTBUFNBS_COUNT (8U) - -/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFHWS */ -#define FLEXIO_SHIFTBUFHWS_COUNT (8U) - -/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNIS */ -#define FLEXIO_SHIFTBUFNIS_COUNT (8U) - - -/*! - * @} - */ /* end of group FLEXIO_Register_Masks */ - - -/* FLEXIO - Peripheral instance base addresses */ -/** Peripheral FLEXIO0 base address */ -#define FLEXIO0_BASE (0x40039000u) -/** Peripheral FLEXIO0 base pointer */ -#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) -/** Array initializer of FLEXIO peripheral base addresses */ -#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } -/** Array initializer of FLEXIO peripheral base pointers */ -#define FLEXIO_BASE_PTRS { FLEXIO0 } -/** Interrupt vectors for the FLEXIO peripheral type */ -#define FLEXIO_IRQS { FLEXIO0_IRQn } - -/*! - * @} - */ /* end of group FLEXIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTFE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer - * @{ - */ - -/** FTFE - Register Layout Typedef */ -typedef struct { - __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ - __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ - __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ - uint8_t RESERVED_0[1]; - __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ - __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ - __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ - __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ - __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ - __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ - __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ - __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ - __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ - __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ - __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ - __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ - __I uint8_t FOPT3; /**< Flash Option Registers, offset: 0x10 */ - __I uint8_t FOPT2; /**< Flash Option Registers, offset: 0x11 */ - __I uint8_t FOPT1; /**< Flash Option Registers, offset: 0x12 */ - __I uint8_t FOPT0; /**< Flash Option Registers, offset: 0x13 */ - uint8_t RESERVED_1[4]; - __IO uint8_t FPROTH3; /**< Primary Program Flash Protection Registers, offset: 0x18 */ - __IO uint8_t FPROTH2; /**< Primary Program Flash Protection Registers, offset: 0x19 */ - __IO uint8_t FPROTH1; /**< Primary Program Flash Protection Registers, offset: 0x1A */ - __IO uint8_t FPROTH0; /**< Primary Program Flash Protection Registers, offset: 0x1B */ - __IO uint8_t FPROTL3; /**< Primary Program Flash Protection Registers, offset: 0x1C */ - __IO uint8_t FPROTL2; /**< Primary Program Flash Protection Registers, offset: 0x1D */ - __IO uint8_t FPROTL1; /**< Primary Program Flash Protection Registers, offset: 0x1E */ - __IO uint8_t FPROTL0; /**< Primary Program Flash Protection Registers, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint8_t FPROTSL; /**< Secondary Program Flash Protection Registers, offset: 0x24 */ - __IO uint8_t FPROTSH; /**< Secondary Program Flash Protection Registers, offset: 0x25 */ - uint8_t RESERVED_3[6]; - __I uint8_t FACSS; /**< Primary Flash Access Segment Size Register, offset: 0x2C */ - __I uint8_t FACSN; /**< Primary Flash Access Segment Number Register, offset: 0x2D */ - __I uint8_t FACSSS; /**< Secondary Flash Access Segment Size Register, offset: 0x2E */ - __I uint8_t FACSNS; /**< Secondary Flash Access Segment Number Register, offset: 0x2F */ - __I uint8_t XACCH3; /**< Primary Execute-only Access Registers, offset: 0x30 */ - __I uint8_t XACCH2; /**< Primary Execute-only Access Registers, offset: 0x31 */ - __I uint8_t XACCH1; /**< Primary Execute-only Access Registers, offset: 0x32 */ - __I uint8_t XACCH0; /**< Primary Execute-only Access Registers, offset: 0x33 */ - __I uint8_t XACCL3; /**< Primary Execute-only Access Registers, offset: 0x34 */ - __I uint8_t XACCL2; /**< Primary Execute-only Access Registers, offset: 0x35 */ - __I uint8_t XACCL1; /**< Primary Execute-only Access Registers, offset: 0x36 */ - __I uint8_t XACCL0; /**< Primary Execute-only Access Registers, offset: 0x37 */ - __I uint8_t SACCH3; /**< Primary Supervisor-only Access Registers, offset: 0x38 */ - __I uint8_t SACCH2; /**< Primary Supervisor-only Access Registers, offset: 0x39 */ - __I uint8_t SACCH1; /**< Primary Supervisor-only Access Registers, offset: 0x3A */ - __I uint8_t SACCH0; /**< Primary Supervisor-only Access Registers, offset: 0x3B */ - __I uint8_t SACCL3; /**< Primary Supervisor-only Access Registers, offset: 0x3C */ - __I uint8_t SACCL2; /**< Primary Supervisor-only Access Registers, offset: 0x3D */ - __I uint8_t SACCL1; /**< Primary Supervisor-only Access Registers, offset: 0x3E */ - __I uint8_t SACCL0; /**< Primary Supervisor-only Access Registers, offset: 0x3F */ - uint8_t RESERVED_4[4]; - __I uint8_t XACCSL; /**< Secondary Execute-only Access Registers, offset: 0x44 */ - __I uint8_t XACCSH; /**< Secondary Execute-only Access Registers, offset: 0x45 */ - uint8_t RESERVED_5[6]; - __I uint8_t SACCSL; /**< Secondary Supervisor-only Access Registers, offset: 0x4C */ - __I uint8_t SACCSH; /**< Secondary Supervisor-only Access Registers, offset: 0x4D */ - uint8_t RESERVED_6[4]; - __I uint8_t FSTDBYCTL; /**< Flash Standby Control Register, offset: 0x52 */ - __IO uint8_t FSTDBY; /**< Flash Standby Register, offset: 0x53 */ -} FTFE_Type; - -/* ---------------------------------------------------------------------------- - -- FTFE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FTFE_Register_Masks FTFE Register Masks - * @{ - */ - -/*! @name FSTAT - Flash Status Register */ -/*! @{ */ -#define FTFE_FSTAT_MGSTAT0_MASK (0x1U) -#define FTFE_FSTAT_MGSTAT0_SHIFT (0U) -#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) -#define FTFE_FSTAT_FPVIOL_MASK (0x10U) -#define FTFE_FSTAT_FPVIOL_SHIFT (4U) -/*! FPVIOL - Flash Protection Violation Flag - * 0b0..No protection violation detected - * 0b1..Protection violation detected - */ -#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) -#define FTFE_FSTAT_ACCERR_MASK (0x20U) -#define FTFE_FSTAT_ACCERR_SHIFT (5U) -/*! ACCERR - Flash Access Error Flag - * 0b0..No access error detected - * 0b1..Access error detected - */ -#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) -#define FTFE_FSTAT_RDCOLERR_MASK (0x40U) -#define FTFE_FSTAT_RDCOLERR_SHIFT (6U) -/*! RDCOLERR - Flash Read Collision Error Flag - * 0b0..No collision error detected - * 0b1..Collision error detected - */ -#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) -#define FTFE_FSTAT_CCIF_MASK (0x80U) -#define FTFE_FSTAT_CCIF_SHIFT (7U) -/*! CCIF - Command Complete Interrupt Flag - * 0b0..Flash command in progress - * 0b1..Flash command has completed - */ -#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) -/*! @} */ - -/*! @name FCNFG - Flash Configuration Register */ -/*! @{ */ -#define FTFE_FCNFG_RAMRDY_MASK (0x2U) -#define FTFE_FCNFG_RAMRDY_SHIFT (1U) -/*! RAMRDY - RAM Ready - * 0b0..Programming acceleration RAM is not available - * 0b1..Programming acceleration RAM is available - */ -#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) -#define FTFE_FCNFG_CRCRDY_MASK (0x4U) -#define FTFE_FCNFG_CRCRDY_SHIFT (2U) -/*! CRCRDY - CRC Ready - * 0b0..Programming acceleration RAM is not available for CRC operations - * 0b1..Programming acceleration RAM is available for CRC operations - */ -#define FTFE_FCNFG_CRCRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CRCRDY_SHIFT)) & FTFE_FCNFG_CRCRDY_MASK) -#define FTFE_FCNFG_SWAP_MASK (0x8U) -#define FTFE_FCNFG_SWAP_SHIFT (3U) -/*! SWAP - Swap - * 0b0..Program flash 0 block is located at relative address 0x0000 - * 0b1..Program flash 1 block is located at relative address 0x0000 - */ -#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) -#define FTFE_FCNFG_ERSSUSP_MASK (0x10U) -#define FTFE_FCNFG_ERSSUSP_SHIFT (4U) -/*! ERSSUSP - Erase Suspend - * 0b0..No suspend requested - * 0b1..Suspend the current Erase Flash Sector command execution - */ -#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) -#define FTFE_FCNFG_ERSAREQ_MASK (0x20U) -#define FTFE_FCNFG_ERSAREQ_SHIFT (5U) -/*! ERSAREQ - Erase All Request - * 0b0..No request or request complete - * 0b1..Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the FSEC[SEC] field to the unsecure state. - */ -#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) -#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) -#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) -/*! RDCOLLIE - Read Collision Error Interrupt Enable - * 0b0..Read collision error interrupt disabled - * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision error is detected (see the description of FSTAT[RDCOLERR]). - */ -#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) -#define FTFE_FCNFG_CCIE_MASK (0x80U) -#define FTFE_FCNFG_CCIE_SHIFT (7U) -/*! CCIE - Command Complete Interrupt Enable - * 0b0..Command complete interrupt disabled - * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. - */ -#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) -/*! @} */ - -/*! @name FSEC - Flash Security Register */ -/*! @{ */ -#define FTFE_FSEC_SEC_MASK (0x3U) -#define FTFE_FSEC_SEC_SHIFT (0U) -/*! SEC - Flash Security - * 0b00..MCU security status is secure - * 0b01..MCU security status is secure - * 0b10..MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.) - * 0b11..MCU security status is secure - */ -#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) -#define FTFE_FSEC_FSLACC_MASK (0xCU) -#define FTFE_FSEC_FSLACC_SHIFT (2U) -/*! FSLACC - Factory Security Level Access Code - * 0b00..Factory access granted - * 0b01..Factory access denied - * 0b10..Factory access denied - * 0b11..Factory access granted - */ -#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) -#define FTFE_FSEC_MEEN_MASK (0x30U) -#define FTFE_FSEC_MEEN_SHIFT (4U) -/*! MEEN - Mass Erase Enable Bits - * 0b00..Mass erase is enabled - * 0b01..Mass erase is enabled - * 0b10..Mass erase is disabled - * 0b11..Mass erase is enabled - */ -#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) -#define FTFE_FSEC_KEYEN_MASK (0xC0U) -#define FTFE_FSEC_KEYEN_SHIFT (6U) -/*! KEYEN - Backdoor Key Security Enable - * 0b00..Backdoor key access disabled - * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) - * 0b10..Backdoor key access enabled - * 0b11..Backdoor key access disabled - */ -#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) -/*! @} */ - -/*! @name FCCOB3 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB3_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB3_CCOBn_SHIFT (0U) -#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB2 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB2_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB2_CCOBn_SHIFT (0U) -#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB1 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB1_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB1_CCOBn_SHIFT (0U) -#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB0 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB0_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB0_CCOBn_SHIFT (0U) -#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB7 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB7_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB7_CCOBn_SHIFT (0U) -#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB6 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB6_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB6_CCOBn_SHIFT (0U) -#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB5 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB5_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB5_CCOBn_SHIFT (0U) -#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB4 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB4_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB4_CCOBn_SHIFT (0U) -#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOBB - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOBB_CCOBn_MASK (0xFFU) -#define FTFE_FCCOBB_CCOBn_SHIFT (0U) -#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOBA - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOBA_CCOBn_MASK (0xFFU) -#define FTFE_FCCOBA_CCOBn_SHIFT (0U) -#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB9 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB9_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB9_CCOBn_SHIFT (0U) -#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) -/*! @} */ - -/*! @name FCCOB8 - Flash Common Command Object Registers */ -/*! @{ */ -#define FTFE_FCCOB8_CCOBn_MASK (0xFFU) -#define FTFE_FCCOB8_CCOBn_SHIFT (0U) -#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) -/*! @} */ - -/*! @name FOPT3 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT3_OPT_MASK (0xFFU) -#define FTFE_FOPT3_OPT_SHIFT (0U) -#define FTFE_FOPT3_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT3_OPT_SHIFT)) & FTFE_FOPT3_OPT_MASK) -/*! @} */ - -/*! @name FOPT2 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT2_OPT_MASK (0xFFU) -#define FTFE_FOPT2_OPT_SHIFT (0U) -#define FTFE_FOPT2_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT2_OPT_SHIFT)) & FTFE_FOPT2_OPT_MASK) -/*! @} */ - -/*! @name FOPT1 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT1_OPT_MASK (0xFFU) -#define FTFE_FOPT1_OPT_SHIFT (0U) -#define FTFE_FOPT1_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT1_OPT_SHIFT)) & FTFE_FOPT1_OPT_MASK) -/*! @} */ - -/*! @name FOPT0 - Flash Option Registers */ -/*! @{ */ -#define FTFE_FOPT0_OPT_MASK (0xFFU) -#define FTFE_FOPT0_OPT_SHIFT (0U) -#define FTFE_FOPT0_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT0_OPT_SHIFT)) & FTFE_FOPT0_OPT_MASK) -/*! @} */ - -/*! @name FPROTH3 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH3_PROT_MASK (0xFFU) -#define FTFE_FPROTH3_PROT_SHIFT (0U) -#define FTFE_FPROTH3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH3_PROT_SHIFT)) & FTFE_FPROTH3_PROT_MASK) -/*! @} */ - -/*! @name FPROTH2 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH2_PROT_MASK (0xFFU) -#define FTFE_FPROTH2_PROT_SHIFT (0U) -#define FTFE_FPROTH2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH2_PROT_SHIFT)) & FTFE_FPROTH2_PROT_MASK) -/*! @} */ - -/*! @name FPROTH1 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH1_PROT_MASK (0xFFU) -#define FTFE_FPROTH1_PROT_SHIFT (0U) -#define FTFE_FPROTH1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH1_PROT_SHIFT)) & FTFE_FPROTH1_PROT_MASK) -/*! @} */ - -/*! @name FPROTH0 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTH0_PROT_MASK (0xFFU) -#define FTFE_FPROTH0_PROT_SHIFT (0U) -#define FTFE_FPROTH0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH0_PROT_SHIFT)) & FTFE_FPROTH0_PROT_MASK) -/*! @} */ - -/*! @name FPROTL3 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL3_PROT_MASK (0xFFU) -#define FTFE_FPROTL3_PROT_SHIFT (0U) -#define FTFE_FPROTL3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL3_PROT_SHIFT)) & FTFE_FPROTL3_PROT_MASK) -/*! @} */ - -/*! @name FPROTL2 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL2_PROT_MASK (0xFFU) -#define FTFE_FPROTL2_PROT_SHIFT (0U) -#define FTFE_FPROTL2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL2_PROT_SHIFT)) & FTFE_FPROTL2_PROT_MASK) -/*! @} */ - -/*! @name FPROTL1 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL1_PROT_MASK (0xFFU) -#define FTFE_FPROTL1_PROT_SHIFT (0U) -#define FTFE_FPROTL1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL1_PROT_SHIFT)) & FTFE_FPROTL1_PROT_MASK) -/*! @} */ - -/*! @name FPROTL0 - Primary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTL0_PROT_MASK (0xFFU) -#define FTFE_FPROTL0_PROT_SHIFT (0U) -#define FTFE_FPROTL0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL0_PROT_SHIFT)) & FTFE_FPROTL0_PROT_MASK) -/*! @} */ - -/*! @name FPROTSL - Secondary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTSL_PROTS_MASK (0xFFU) -#define FTFE_FPROTSL_PROTS_SHIFT (0U) -#define FTFE_FPROTSL_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSL_PROTS_SHIFT)) & FTFE_FPROTSL_PROTS_MASK) -/*! @} */ - -/*! @name FPROTSH - Secondary Program Flash Protection Registers */ -/*! @{ */ -#define FTFE_FPROTSH_PROTS_MASK (0xFFU) -#define FTFE_FPROTSH_PROTS_SHIFT (0U) -#define FTFE_FPROTSH_PROTS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSH_PROTS_SHIFT)) & FTFE_FPROTSH_PROTS_MASK) -/*! @} */ - -/*! @name FACSS - Primary Flash Access Segment Size Register */ -/*! @{ */ -#define FTFE_FACSS_SGSIZE_MASK (0xFFU) -#define FTFE_FACSS_SGSIZE_SHIFT (0U) -#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK) -/*! @} */ - -/*! @name FACSN - Primary Flash Access Segment Number Register */ -/*! @{ */ -#define FTFE_FACSN_NUMSG_MASK (0xFFU) -#define FTFE_FACSN_NUMSG_SHIFT (0U) -/*! NUMSG - Number of Segments Indicator - * 0b00110000..Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) - * 0b01000000..Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes) - */ -#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK) -/*! @} */ - -/*! @name FACSSS - Secondary Flash Access Segment Size Register */ -/*! @{ */ -#define FTFE_FACSSS_SGSIZE_S_MASK (0xFFU) -#define FTFE_FACSSS_SGSIZE_S_SHIFT (0U) -#define FTFE_FACSSS_SGSIZE_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSSS_SGSIZE_S_SHIFT)) & FTFE_FACSSS_SGSIZE_S_MASK) -/*! @} */ - -/*! @name FACSNS - Secondary Flash Access Segment Number Register */ -/*! @{ */ -#define FTFE_FACSNS_NUMSG_S_MASK (0xFFU) -#define FTFE_FACSNS_NUMSG_S_SHIFT (0U) -/*! NUMSG_S - Number of Segments Indicator - * 0b00010000..Secondary Program flash memory is divided into 16 segments - */ -#define FTFE_FACSNS_NUMSG_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSNS_NUMSG_S_SHIFT)) & FTFE_FACSNS_NUMSG_S_MASK) -/*! @} */ - -/*! @name XACCH3 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH3_XA_MASK (0xFFU) -#define FTFE_XACCH3_XA_SHIFT (0U) -#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK) -/*! @} */ - -/*! @name XACCH2 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH2_XA_MASK (0xFFU) -#define FTFE_XACCH2_XA_SHIFT (0U) -#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK) -/*! @} */ - -/*! @name XACCH1 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH1_XA_MASK (0xFFU) -#define FTFE_XACCH1_XA_SHIFT (0U) -#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK) -/*! @} */ - -/*! @name XACCH0 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCH0_XA_MASK (0xFFU) -#define FTFE_XACCH0_XA_SHIFT (0U) -#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK) -/*! @} */ - -/*! @name XACCL3 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL3_XA_MASK (0xFFU) -#define FTFE_XACCL3_XA_SHIFT (0U) -#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK) -/*! @} */ - -/*! @name XACCL2 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL2_XA_MASK (0xFFU) -#define FTFE_XACCL2_XA_SHIFT (0U) -#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK) -/*! @} */ - -/*! @name XACCL1 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL1_XA_MASK (0xFFU) -#define FTFE_XACCL1_XA_SHIFT (0U) -#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK) -/*! @} */ - -/*! @name XACCL0 - Primary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCL0_XA_MASK (0xFFU) -#define FTFE_XACCL0_XA_SHIFT (0U) -#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK) -/*! @} */ - -/*! @name SACCH3 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH3_SA_MASK (0xFFU) -#define FTFE_SACCH3_SA_SHIFT (0U) -#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK) -/*! @} */ - -/*! @name SACCH2 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH2_SA_MASK (0xFFU) -#define FTFE_SACCH2_SA_SHIFT (0U) -#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK) -/*! @} */ - -/*! @name SACCH1 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH1_SA_MASK (0xFFU) -#define FTFE_SACCH1_SA_SHIFT (0U) -#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK) -/*! @} */ - -/*! @name SACCH0 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCH0_SA_MASK (0xFFU) -#define FTFE_SACCH0_SA_SHIFT (0U) -#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK) -/*! @} */ - -/*! @name SACCL3 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL3_SA_MASK (0xFFU) -#define FTFE_SACCL3_SA_SHIFT (0U) -#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK) -/*! @} */ - -/*! @name SACCL2 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL2_SA_MASK (0xFFU) -#define FTFE_SACCL2_SA_SHIFT (0U) -#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK) -/*! @} */ - -/*! @name SACCL1 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL1_SA_MASK (0xFFU) -#define FTFE_SACCL1_SA_SHIFT (0U) -#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK) -/*! @} */ - -/*! @name SACCL0 - Primary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCL0_SA_MASK (0xFFU) -#define FTFE_SACCL0_SA_SHIFT (0U) -#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK) -/*! @} */ - -/*! @name XACCSL - Secondary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCSL_XA_S_MASK (0xFFU) -#define FTFE_XACCSL_XA_S_SHIFT (0U) -#define FTFE_XACCSL_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSL_XA_S_SHIFT)) & FTFE_XACCSL_XA_S_MASK) -/*! @} */ - -/*! @name XACCSH - Secondary Execute-only Access Registers */ -/*! @{ */ -#define FTFE_XACCSH_XA_S_MASK (0xFFU) -#define FTFE_XACCSH_XA_S_SHIFT (0U) -#define FTFE_XACCSH_XA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSH_XA_S_SHIFT)) & FTFE_XACCSH_XA_S_MASK) -/*! @} */ - -/*! @name SACCSL - Secondary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCSL_SA_S_MASK (0xFFU) -#define FTFE_SACCSL_SA_S_SHIFT (0U) -#define FTFE_SACCSL_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSL_SA_S_SHIFT)) & FTFE_SACCSL_SA_S_MASK) -/*! @} */ - -/*! @name SACCSH - Secondary Supervisor-only Access Registers */ -/*! @{ */ -#define FTFE_SACCSH_SA_S_MASK (0xFFU) -#define FTFE_SACCSH_SA_S_SHIFT (0U) -#define FTFE_SACCSH_SA_S(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK) -/*! @} */ - -/*! @name FSTDBYCTL - Flash Standby Control Register */ -/*! @{ */ -#define FTFE_FSTDBYCTL_STDBYDIS_MASK (0x1U) -#define FTFE_FSTDBYCTL_STDBYDIS_SHIFT (0U) -/*! STDBYDIS - Standy Mode Disable - * 0b0..Standby mode enabled for flash blocks selected by STDBYx - * 0b1..Standby mode disabled (STDBYx ignored) - */ -#define FTFE_FSTDBYCTL_STDBYDIS(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBYCTL_STDBYDIS_SHIFT)) & FTFE_FSTDBYCTL_STDBYDIS_MASK) -/*! @} */ - -/*! @name FSTDBY - Flash Standby Register */ -/*! @{ */ -#define FTFE_FSTDBY_STDBY0_MASK (0x1U) -#define FTFE_FSTDBY_STDBY0_SHIFT (0U) -/*! STDBY0 - Standy Mode for Flash Block 0 - * 0b0..Standby mode not enabled for flash block 0 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block) - */ -#define FTFE_FSTDBY_STDBY0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY0_SHIFT)) & FTFE_FSTDBY_STDBY0_MASK) -#define FTFE_FSTDBY_STDBY1_MASK (0x2U) -#define FTFE_FSTDBY_STDBY1_SHIFT (1U) -/*! STDBY1 - Standy Mode for Flash Block 1 - * 0b0..Standby mode not enabled for flash block 1 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block) - */ -#define FTFE_FSTDBY_STDBY1(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY1_SHIFT)) & FTFE_FSTDBY_STDBY1_MASK) -#define FTFE_FSTDBY_STDBY2_MASK (0x4U) -#define FTFE_FSTDBY_STDBY2_SHIFT (2U) -/*! STDBY2 - Standy Mode for Flash Block 2 - * 0b0..Standby mode not enabled for flash block 2 - * 0b1..If STDBYDIS is clear, standby mode is enabled for flash block 2 - */ -#define FTFE_FSTDBY_STDBY2(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY2_SHIFT)) & FTFE_FSTDBY_STDBY2_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FTFE_Register_Masks */ - - -/* FTFE - Peripheral instance base addresses */ -/** Peripheral FTFE base address */ -#define FTFE_BASE (0x40023000u) -/** Peripheral FTFE base pointer */ -#define FTFE ((FTFE_Type *)FTFE_BASE) -/** Array initializer of FTFE peripheral base addresses */ -#define FTFE_BASE_ADDRS { FTFE_BASE } -/** Array initializer of FTFE peripheral base pointers */ -#define FTFE_BASE_PTRS { FTFE } -/** Interrupt vectors for the FTFE peripheral type */ -#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_Command_Complete_IRQn } -#define FTFE_READ_COLLISION_IRQS { FTFE_Read_Collision_IRQn } - -/*! - * @} - */ /* end of group FTFE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GENFSK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer - * @{ - */ - -/** GENFSK - Register Layout Typedef */ -typedef struct { - __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */ - __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */ - __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */ - __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */ - __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */ - __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */ - __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */ - __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */ - __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */ - __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */ - __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */ - __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */ - __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */ - __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */ - __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */ - __IO uint32_t RX_WATERMARK; /**< RECEIVE WATERMARK, offset: 0x3C */ - __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */ - __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */ - uint8_t RESERVED_0[24]; - __IO uint32_t PACKET_CFG; /**< PACKET CONFIGURATION, offset: 0x60 */ - __IO uint32_t H0_CFG; /**< H0 CONFIGURATION, offset: 0x64 */ - __IO uint32_t H1_CFG; /**< H1 CONFIGURATION, offset: 0x68 */ - __IO uint32_t CRC_CFG; /**< CRC CONFIGURATION, offset: 0x6C */ - __IO uint32_t CRC_INIT; /**< CRC INITIALIZATION, offset: 0x70 */ - __IO uint32_t CRC_POLY; /**< CRC POLYNOMIAL, offset: 0x74 */ - __IO uint32_t CRC_XOR_OUT; /**< CRC XOR OUT, offset: 0x78 */ - __IO uint32_t WHITEN_CFG; /**< WHITENER CONFIGURATION, offset: 0x7C */ - __IO uint32_t WHITEN_POLY; /**< WHITENER POLYNOMIAL, offset: 0x80 */ - __IO uint32_t WHITEN_SZ_THR; /**< WHITENER SIZE THRESHOLD, offset: 0x84 */ - __IO uint32_t BITRATE; /**< BIT RATE, offset: 0x88 */ - __IO uint32_t PB_PARTITION; /**< PACKET BUFFER PARTITION POINT, offset: 0x8C */ - uint8_t RESERVED_1[1648]; - __IO uint16_t PACKET_BUFFER[1088]; /**< PACKET BUFFER, array offset: 0x700, array step: 0x2 */ -} GENFSK_Type; - -/* ---------------------------------------------------------------------------- - -- GENFSK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GENFSK_Register_Masks GENFSK Register Masks - * @{ - */ - -/*! @name IRQ_CTRL - IRQ CONTROL */ -/*! @{ */ -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U) -/*! SEQ_END_IRQ - Sequence End Interrupt - * 0b0..Sequence End Interrupt is not asserted. - * 0b1..Sequence End Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK) -#define GENFSK_IRQ_CTRL_TX_IRQ_MASK (0x2U) -#define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT (1U) -/*! TX_IRQ - TX Interrupt - * 0b0..TX Interrupt is not asserted. - * 0b1..TX Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK) -#define GENFSK_IRQ_CTRL_RX_IRQ_MASK (0x4U) -#define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT (2U) -/*! RX_IRQ - RX Interrupt - * 0b0..RX Interrupt is not asserted. - * 0b1..RX Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U) -/*! NTW_ADR_IRQ - Network Address Match Interrupt - * 0b0..Network Address Match Interrupt is not asserted. - * 0b1..Network Address Match Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK) -#define GENFSK_IRQ_CTRL_T1_IRQ_MASK (0x10U) -#define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT (4U) -/*! T1_IRQ - Timer1 (T1) Compare Interrupt - * 0b0..Timer1 (T1) Compare Interrupt is not asserted. - * 0b1..Timer1 (T1) Compare Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK) -#define GENFSK_IRQ_CTRL_T2_IRQ_MASK (0x20U) -#define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT (5U) -/*! T2_IRQ - Timer2 (T2) Compare Interrupt - * 0b0..Timer2 (T2) Compare Interrupt is not asserted. - * 0b1..Timer2 (T2) Compare Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U) -/*! PLL_UNLOCK_IRQ - PLL Unlock Interrupt - * 0b0..PLL Unlock Interrupt is not asserted. - * 0b1..PLL Unlock Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK (0x80U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT (7U) -/*! WAKE_IRQ - Wake Interrrupt - * 0b0..Wake Interrupt is not asserted. - * 0b1..Wake Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U) -/*! RX_WATERMARK_IRQ - RX Watermark Interrupt - * 0b0..RX Watermark Interrupt is not asserted. - * 0b1..RX Watermark Interrupt is asserted. - */ -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK) -#define GENFSK_IRQ_CTRL_TSM_IRQ_MASK (0x200U) -#define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT (9U) -/*! TSM_IRQ - TSM Interrupt - * 0b0..TSM0_IRQ and TSM1_IRQ are both clear. - * 0b1..Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS. - */ -#define GENFSK_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U) -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U) -/*! SEQ_END_IRQ_EN - SEQ_END_IRQ Enable - * 0b0..Sequence End Interrupt is not enabled. - * 0b1..Sequence End Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U) -#define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U) -/*! TX_IRQ_EN - TX_IRQ Enable - * 0b0..TX Interrupt is not enabled. - * 0b1..TX Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U) -#define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U) -/*! RX_IRQ_EN - RX_IRQ Enable - * 0b0..RX Interrupt is not enabled. - * 0b1..RX Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U) -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U) -/*! NTW_ADR_IRQ_EN - NTW_ADR_IRQ Enable - * 0b0..Network Address Match Interrupt is not enabled. - * 0b1..Network Address Match Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U) -#define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U) -/*! T1_IRQ_EN - T1_IRQ Enable - * 0b0..Timer1 (T1) Compare Interrupt is not enabled. - * 0b1..Timer1 (T1) Compare Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) -#define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U) -/*! T2_IRQ_EN - T2_IRQ Enable - * 0b0..Timer1 (T2) Compare Interrupt is not enabled. - * 0b1..Timer1 (T2) Compare Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U) -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U) -/*! PLL_UNLOCK_IRQ_EN - PLL_UNLOCK_IRQ Enable - * 0b0..PLL Unlock Interrupt is not enabled. - * 0b1..PLL Unlock Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U) -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U) -/*! WAKE_IRQ_EN - WAKE_IRQ Enable - * 0b0..Wake Interrupt is not enabled. - * 0b1..Wake Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U) -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U) -/*! RX_WATERMARK_IRQ_EN - RX_WATERMARK_IRQ Enable - * 0b0..RX Watermark Interrupt is not enabled. - * 0b1..RX Watermark Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U) -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U) -/*! TSM_IRQ_EN - TSM_IRQ Enable - * 0b0..TSM Interrupt is not enabled. - * 0b1..TSM Interrupt is enabled. - */ -#define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK (0x4000000U) -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U) -/*! GENERIC_FSK_IRQ_EN - GENERIC_FSK_IRQ Master Enable - * 0b0..All GENERIC_FSK Interrupts are disabled. - * 0b1..All GENERIC_FSK Interrupts can be enabled. - */ -#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK) -#define GENFSK_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U) -#define GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT (27U) -/*! CRC_IGNORE - CRC Ignore - * 0b0..RX_IRQ will not be asserted for a received packet which fails CRC verification. - * 0b1..RX_IRQ will be asserted even for a received packet which fails CRC verification. - */ -#define GENFSK_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT)) & GENFSK_IRQ_CTRL_CRC_IGNORE_MASK) -#define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) -#define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT (31U) -/*! CRC_VALID - CRC Valid - * 0b0..CRC of RX packet is not valid. - * 0b1..CRC of RX packet is valid. - */ -#define GENFSK_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK) -/*! @} */ - -/*! @name EVENT_TMR - EVENT TIMER */ -/*! @{ */ -#define GENFSK_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU) -#define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT (0U) -#define GENFSK_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U) -#define GENFSK_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U) -#define GENFSK_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK) -/*! @} */ - -/*! @name T1_CMP - T1 COMPARE */ -/*! @{ */ -#define GENFSK_T1_CMP_T1_CMP_MASK (0xFFFFFFU) -#define GENFSK_T1_CMP_T1_CMP_SHIFT (0U) -#define GENFSK_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK) -#define GENFSK_T1_CMP_T1_CMP_EN_MASK (0x1000000U) -#define GENFSK_T1_CMP_T1_CMP_EN_SHIFT (24U) -#define GENFSK_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_EN_SHIFT)) & GENFSK_T1_CMP_T1_CMP_EN_MASK) -/*! @} */ - -/*! @name T2_CMP - T2 COMPARE */ -/*! @{ */ -#define GENFSK_T2_CMP_T2_CMP_MASK (0xFFFFFFU) -#define GENFSK_T2_CMP_T2_CMP_SHIFT (0U) -#define GENFSK_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK) -#define GENFSK_T2_CMP_T2_CMP_EN_MASK (0x1000000U) -#define GENFSK_T2_CMP_T2_CMP_EN_SHIFT (24U) -#define GENFSK_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_EN_SHIFT)) & GENFSK_T2_CMP_T2_CMP_EN_MASK) -/*! @} */ - -/*! @name TIMESTAMP - TIMESTAMP */ -/*! @{ */ -#define GENFSK_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU) -#define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define GENFSK_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK) -/*! @} */ - -/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ -/*! @{ */ -#define GENFSK_XCVR_CTRL_SEQCMD_MASK (0xFU) -#define GENFSK_XCVR_CTRL_SEQCMD_SHIFT (0U) -/*! SEQCMD - Sequence Commands - * 0b0000..No Action - * 0b0001..TX Start Now - * 0b0010..TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) - * 0b0011..TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) - * 0b0100..TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress - * 0b0101..RX Start Now - * 0b0110..RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) - * 0b0111..RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) - * 0b1000..RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP) - * 0b1001..RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP) - * 0b1010..RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress - * 0b1011..Abort All - Cancels all pending events and abort any sequence-in-progress - * 0b1100..Reserved - * 0b1101..Reserved - * 0b1110..Reserved - * 0b1111..Reserved - */ -#define GENFSK_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK) -#define GENFSK_XCVR_CTRL_LENGTH_EXT_MASK (0x7FF00U) -#define GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT (8U) -#define GENFSK_XCVR_CTRL_LENGTH_EXT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT)) & GENFSK_XCVR_CTRL_LENGTH_EXT_MASK) -#define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) -#define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT (24U) -#define GENFSK_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK) -#define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U) -#define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT (31U) -/*! XCVR_BUSY - Transceiver Busy - * 0b0..IDLE - * 0b1..BUSY - */ -#define GENFSK_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK) -/*! @} */ - -/*! @name XCVR_STS - TRANSCEIVER STATUS */ -/*! @{ */ -#define GENFSK_XCVR_STS_TX_START_T1_PEND_MASK (0x1U) -#define GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT (0U) -#define GENFSK_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T1_PEND_MASK) -#define GENFSK_XCVR_STS_TX_START_T2_PEND_MASK (0x2U) -#define GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT (1U) -#define GENFSK_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T2_PEND_MASK) -#define GENFSK_XCVR_STS_TX_IN_WARMUP_MASK (0x4U) -#define GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT (2U) -#define GENFSK_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMUP_MASK) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U) -#define GENFSK_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK) -#define GENFSK_XCVR_STS_TX_IN_WARMDN_MASK (0x10U) -#define GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT (4U) -#define GENFSK_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMDN_MASK) -#define GENFSK_XCVR_STS_RX_START_T1_PEND_MASK (0x20U) -#define GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT (5U) -#define GENFSK_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T1_PEND_MASK) -#define GENFSK_XCVR_STS_RX_START_T2_PEND_MASK (0x40U) -#define GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT (6U) -#define GENFSK_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T2_PEND_MASK) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U) -#define GENFSK_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U) -#define GENFSK_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK) -#define GENFSK_XCVR_STS_RX_IN_WARMUP_MASK (0x200U) -#define GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT (9U) -#define GENFSK_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMUP_MASK) -#define GENFSK_XCVR_STS_RX_IN_SEARCH_MASK (0x400U) -#define GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT (10U) -#define GENFSK_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_XCVR_STS_RX_IN_SEARCH_MASK) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U) -#define GENFSK_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK) -#define GENFSK_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U) -#define GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT (12U) -#define GENFSK_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMDN_MASK) -#define GENFSK_XCVR_STS_LQI_VALID_MASK (0x4000U) -#define GENFSK_XCVR_STS_LQI_VALID_SHIFT (14U) -/*! LQI_VALID - LQI Valid Indicator - * 0b0..LQI is not yet valid for RX packet. - * 0b1..LQI is valid for RX packet. - */ -#define GENFSK_XCVR_STS_LQI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK) -#define GENFSK_XCVR_STS_CRC_VALID_MASK (0x8000U) -#define GENFSK_XCVR_STS_CRC_VALID_SHIFT (15U) -/*! CRC_VALID - CRC Valid Indicator - * 0b0..CRC is not valid for RX packet. - * 0b1..CRC is valid for RX packet. - */ -#define GENFSK_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_CRC_VALID_SHIFT)) & GENFSK_XCVR_STS_CRC_VALID_MASK) -#define GENFSK_XCVR_STS_RSSI_MASK (0xFF0000U) -#define GENFSK_XCVR_STS_RSSI_SHIFT (16U) -#define GENFSK_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK) -#define GENFSK_XCVR_STS_LQI_MASK (0xFF000000U) -#define GENFSK_XCVR_STS_LQI_SHIFT (24U) -#define GENFSK_XCVR_STS_LQI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK) -/*! @} */ - -/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */ -/*! @{ */ -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U) -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U) -#define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U) -#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK) -#define GENFSK_XCVR_CFG_SW_CRC_EN_MASK (0x4U) -#define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT (2U) -#define GENFSK_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK) -#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK (0x8U) -#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT (3U) -/*! STOP_POSTPONE_ON_AA - Postpone Stop Command Timeout On Access Address Match Enable - * 0b0..STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of ntw_adr_matched - * 0b1..STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if ntw_adr_matched is asserted; otherwise the RX_STOP Abort will occur immediately - */ -#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT)) & GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK (0x70U) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U) -#define GENFSK_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK) -#define GENFSK_XCVR_CFG_TX_WARMUP_MASK (0xFF00U) -#define GENFSK_XCVR_CFG_TX_WARMUP_SHIFT (8U) -#define GENFSK_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_TX_WARMUP_MASK) -#define GENFSK_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) -#define GENFSK_XCVR_CFG_RX_WARMUP_SHIFT (16U) -#define GENFSK_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK) -/*! @} */ - -/*! @name CHANNEL_NUM - CHANNEL NUMBER */ -/*! @{ */ -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU) -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U) -#define GENFSK_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK) -/*! @} */ - -/*! @name TX_POWER - TRANSMIT POWER */ -/*! @{ */ -#define GENFSK_TX_POWER_TX_POWER_MASK (0x3FU) -#define GENFSK_TX_POWER_TX_POWER_SHIFT (0U) -#define GENFSK_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK) -/*! @} */ - -/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */ -/*! @{ */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U) -/*! NTW_ADR_EN - Network Address Enable - * 0b0001..Enable Network Address 0 for correlation - * 0b0010..Enable Network Address 1 for correlation - * 0b0100..Enable Network Address 2 for correlation - * 0b1000..Enable Network Address 3 for correlation - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U) -/*! NTW_ADR_MCH - Network Address Match - * 0b0001..Network Address 0 has matched - * 0b0010..Network Address 1 has matched - * 0b0100..Network Address 2 has matched - * 0b1000..Network Address 3 has matched - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U) -/*! NTW_ADR0_SZ - Network Address 0 Size - * 0b00..Network Address 0 requires a 8-bit correlation - * 0b01..Network Address 0 requires a 16-bit correlation - * 0b10..Network Address 0 requires a 24-bit correlation - * 0b11..Network Address 0 requires a 32-bit correlation - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U) -/*! NTW_ADR1_SZ - Network Address 1 Size - * 0b00..Network Address 1 requires a 8-bit correlation - * 0b01..Network Address 1 requires a 16-bit correlation - * 0b10..Network Address 1 requires a 24-bit correlation - * 0b11..Network Address 1 requires a 32-bit correlation - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U) -/*! NTW_ADR2_SZ - Network Address 2 Size - * 0b00..Network Address 2 requires a 8-bit correlation - * 0b01..Network Address 2 requires a 16-bit correlation - * 0b10..Network Address 2 requires a 24-bit correlation - * 0b11..Network Address 2 requires a 32-bit correlation - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U) -/*! NTW_ADR3_SZ - Network Address 3 Size - * 0b00..Network Address 3 requires a 8-bit correlation - * 0b01..Network Address 3 requires a 16-bit correlation - * 0b10..Network Address 3 requires a 24-bit correlation - * 0b11..Network Address 3 requires a 32-bit correlation - */ -#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U) -#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK) -/*! @} */ - -/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */ -/*! @{ */ -#define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT (0U) -#define GENFSK_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK) -/*! @} */ - -/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */ -/*! @{ */ -#define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT (0U) -#define GENFSK_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK) -/*! @} */ - -/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */ -/*! @{ */ -#define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT (0U) -#define GENFSK_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK) -/*! @} */ - -/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */ -/*! @{ */ -#define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU) -#define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT (0U) -#define GENFSK_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK) -/*! @} */ - -/*! @name RX_WATERMARK - RECEIVE WATERMARK */ -/*! @{ */ -#define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK (0x1FFFU) -#define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT (0U) -#define GENFSK_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK (0x1FFF0000U) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U) -#define GENFSK_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK) -/*! @} */ - -/*! @name DSM_CTRL - DSM CONTROL */ -/*! @{ */ -#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK (0x1U) -#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT (0U) -#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT)) & GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK) -/*! @} */ - -/*! @name PART_ID - PART ID */ -/*! @{ */ -#define GENFSK_PART_ID_PART_ID_MASK (0xFFU) -#define GENFSK_PART_ID_PART_ID_SHIFT (0U) -#define GENFSK_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK) -/*! @} */ - -/*! @name PACKET_CFG - PACKET CONFIGURATION */ -/*! @{ */ -#define GENFSK_PACKET_CFG_LENGTH_SZ_MASK (0x1FU) -#define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT (0U) -#define GENFSK_PACKET_CFG_LENGTH_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK (0x20U) -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT (5U) -/*! LENGTH_BIT_ORD - LENGTH Bit Order - * 0b0..LS Bit First - * 0b1..MS Bit First - */ -#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (0xC0U) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT (6U) -#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_MASK (0xFF00U) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT (8U) -#define GENFSK_PACKET_CFG_LENGTH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_MASK) -#define GENFSK_PACKET_CFG_H0_SZ_MASK (0x1F0000U) -#define GENFSK_PACKET_CFG_H0_SZ_SHIFT (16U) -#define GENFSK_PACKET_CFG_H0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_MASK (0x200000U) -#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_SHIFT (21U) -/*! LENGTH_ADJ_UNSIGNED - Length Adjustment Unsigned Enabled - * 0b0..Hardware interprets LENGTH_ADJ as a signed integer (default) - * 0b1..Hardware interprets LENGTH_ADJ as a unsigned integer - */ -#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_MASK) -#define GENFSK_PACKET_CFG_H1_SZ_MASK (0x1F000000U) -#define GENFSK_PACKET_CFG_H1_SZ_SHIFT (24U) -#define GENFSK_PACKET_CFG_H1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK) -#define GENFSK_PACKET_CFG_H1_FAIL_MASK (0x20000000U) -#define GENFSK_PACKET_CFG_H1_FAIL_SHIFT (29U) -#define GENFSK_PACKET_CFG_H1_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK) -#define GENFSK_PACKET_CFG_H0_FAIL_MASK (0x40000000U) -#define GENFSK_PACKET_CFG_H0_FAIL_SHIFT (30U) -#define GENFSK_PACKET_CFG_H0_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK) -#define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK (0x80000000U) -#define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT (31U) -#define GENFSK_PACKET_CFG_LENGTH_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK) -/*! @} */ - -/*! @name H0_CFG - H0 CONFIGURATION */ -/*! @{ */ -#define GENFSK_H0_CFG_H0_MATCH_MASK (0xFFFFU) -#define GENFSK_H0_CFG_H0_MATCH_SHIFT (0U) -#define GENFSK_H0_CFG_H0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK) -#define GENFSK_H0_CFG_H0_MASK_MASK (0xFFFF0000U) -#define GENFSK_H0_CFG_H0_MASK_SHIFT (16U) -#define GENFSK_H0_CFG_H0_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK) -/*! @} */ - -/*! @name H1_CFG - H1 CONFIGURATION */ -/*! @{ */ -#define GENFSK_H1_CFG_H1_MATCH_MASK (0xFFFFU) -#define GENFSK_H1_CFG_H1_MATCH_SHIFT (0U) -#define GENFSK_H1_CFG_H1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK) -#define GENFSK_H1_CFG_H1_MASK_MASK (0xFFFF0000U) -#define GENFSK_H1_CFG_H1_MASK_SHIFT (16U) -#define GENFSK_H1_CFG_H1_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK) -/*! @} */ - -/*! @name CRC_CFG - CRC CONFIGURATION */ -/*! @{ */ -#define GENFSK_CRC_CFG_CRC_SZ_MASK (0x7U) -#define GENFSK_CRC_CFG_CRC_SZ_SHIFT (0U) -#define GENFSK_CRC_CFG_CRC_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_SZ_SHIFT)) & GENFSK_CRC_CFG_CRC_SZ_MASK) -#define GENFSK_CRC_CFG_CRC_START_BYTE_MASK (0xF00U) -#define GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT (8U) -#define GENFSK_CRC_CFG_CRC_START_BYTE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT)) & GENFSK_CRC_CFG_CRC_START_BYTE_MASK) -#define GENFSK_CRC_CFG_CRC_REF_IN_MASK (0x10000U) -#define GENFSK_CRC_CFG_CRC_REF_IN_SHIFT (16U) -/*! CRC_REF_IN - CRC Reflect In - * 0b0..do not manipulate input data stream - * 0b1..reflect each byte in the input stream bitwise - */ -#define GENFSK_CRC_CFG_CRC_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_IN_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_IN_MASK) -#define GENFSK_CRC_CFG_CRC_REF_OUT_MASK (0x20000U) -#define GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT (17U) -/*! CRC_REF_OUT - CRC Reflect Out - * 0b0..do not manipulate CRC result - * 0b1..CRC result is to be reflected bitwise (operated on entire word) - */ -#define GENFSK_CRC_CFG_CRC_REF_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_OUT_MASK) -#define GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK (0x40000U) -#define GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT (18U) -/*! CRC_BYTE_ORD - CRC Byte Order - * 0b0..LS Byte First - * 0b1..MS Byte First - */ -#define GENFSK_CRC_CFG_CRC_BYTE_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT)) & GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK) -/*! @} */ - -/*! @name CRC_INIT - CRC INITIALIZATION */ -/*! @{ */ -#define GENFSK_CRC_INIT_CRC_SEED_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_INIT_CRC_SEED_SHIFT (0U) -#define GENFSK_CRC_INIT_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_INIT_CRC_SEED_SHIFT)) & GENFSK_CRC_INIT_CRC_SEED_MASK) -/*! @} */ - -/*! @name CRC_POLY - CRC POLYNOMIAL */ -/*! @{ */ -#define GENFSK_CRC_POLY_CRC_POLY_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_POLY_CRC_POLY_SHIFT (0U) -#define GENFSK_CRC_POLY_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_POLY_CRC_POLY_SHIFT)) & GENFSK_CRC_POLY_CRC_POLY_MASK) -/*! @} */ - -/*! @name CRC_XOR_OUT - CRC XOR OUT */ -/*! @{ */ -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK (0xFFFFFFFFU) -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT (0U) -#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK) -/*! @} */ - -/*! @name WHITEN_CFG - WHITENER CONFIGURATION */ -/*! @{ */ -#define GENFSK_WHITEN_CFG_WHITEN_START_MASK (0x3U) -#define GENFSK_WHITEN_CFG_WHITEN_START_SHIFT (0U) -/*! WHITEN_START - Configure Whitener Start Point - * 0b00..no whitening - * 0b01..start whitening at start-of-H0 - * 0b10..start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR - * 0b11..start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR - */ -#define GENFSK_WHITEN_CFG_WHITEN_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_START_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_START_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_END_MASK (0x4U) -#define GENFSK_WHITEN_CFG_WHITEN_END_SHIFT (2U) -/*! WHITEN_END - Configure end-of-whitening - * 0b0..end whiten at end-of-payload - * 0b1..end whiten at end-of-crc - */ -#define GENFSK_WHITEN_CFG_WHITEN_END(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK (0x8U) -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT (3U) -/*! WHITEN_B4_CRC - Congifure for Whitening-before-CRC - * 0b0..CRC before whiten/de-whiten - * 0b1..Whiten/de-whiten before CRC - */ -#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK (0x10U) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT (4U) -#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK (0x20U) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT (5U) -#define GENFSK_WHITEN_CFG_WHITEN_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U) -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U) -/*! WHITEN_PAYLOAD_REINIT - Configure for Whitener re-initialization - * 0b0..Don't re-initialize Whitener LFSR at start-of-payload - * 0b1..Re-initialize Whitener LFSR at start-of-payload - */ -#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK (0xF00U) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT (8U) -#define GENFSK_WHITEN_CFG_WHITEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK (0x1000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT (12U) -/*! MANCHESTER_EN - Configure for Manchester Encoding/Decoding - * 0b0..Disable Manchester encoding (TX) and decoding (RX) - * 0b1..Enable Manchester encoding (TX) and decoding (RX) - */ -#define GENFSK_WHITEN_CFG_MANCHESTER_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (0x2000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT (13U) -/*! MANCHESTER_INV - Configure for Inverted Manchester Encoding - * 0b0..Manchester coding as per 802.3 - * 0b1..Manchester coding as per 802.3 but with the encoding signal inverted - */ -#define GENFSK_WHITEN_CFG_MANCHESTER_INV(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK) -#define GENFSK_WHITEN_CFG_MANCHESTER_START_MASK (0x4000U) -#define GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT (14U) -/*! MANCHESTER_START - Configure Manchester Encoding Start Point - * 0b0..Start Manchester coding at start-of-payload - * 0b1..Start Manchester coding at start-of-header - */ -#define GENFSK_WHITEN_CFG_MANCHESTER_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_START_MASK) -#define GENFSK_WHITEN_CFG_WHITEN_INIT_MASK (0x1FF0000U) -#define GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT (16U) -#define GENFSK_WHITEN_CFG_WHITEN_INIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_INIT_MASK) -/*! @} */ - -/*! @name WHITEN_POLY - WHITENER POLYNOMIAL */ -/*! @{ */ -#define GENFSK_WHITEN_POLY_WHITEN_POLY_MASK (0x1FFU) -#define GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT (0U) -#define GENFSK_WHITEN_POLY_WHITEN_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT)) & GENFSK_WHITEN_POLY_WHITEN_POLY_MASK) -/*! @} */ - -/*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */ -/*! @{ */ -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK (0xFFFU) -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT (0U) -#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK (0x7F0000U) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT (16U) -#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT)) & GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK) -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK (0x800000U) -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT (23U) -/*! REC_BAD_PKT - Receive Bad Packets - * 0b0..packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed - * 0b1..packets which fail H0, H1, or LENGTH_MAX are received in their entirety - */ -#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT)) & GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK) -/*! @} */ - -/*! @name BITRATE - BIT RATE */ -/*! @{ */ -#define GENFSK_BITRATE_BITRATE_MASK (0x3U) -#define GENFSK_BITRATE_BITRATE_SHIFT (0U) -/*! BITRATE - Bit Rate - * 0b00..1Mbit/sec - * 0b01..500Kbit/sec - * 0b10..250Kbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1) - * 0b11..2Mbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1) - */ -#define GENFSK_BITRATE_BITRATE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_BITRATE_BITRATE_SHIFT)) & GENFSK_BITRATE_BITRATE_MASK) -/*! @} */ - -/*! @name PB_PARTITION - PACKET BUFFER PARTITION POINT */ -/*! @{ */ -#define GENFSK_PB_PARTITION_PB_PARTITION_MASK (0x7FFU) -#define GENFSK_PB_PARTITION_PB_PARTITION_SHIFT (0U) -#define GENFSK_PB_PARTITION_PB_PARTITION(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PB_PARTITION_PB_PARTITION_SHIFT)) & GENFSK_PB_PARTITION_PB_PARTITION_MASK) -/*! @} */ - -/*! @name PACKET_BUFFER - PACKET BUFFER */ -/*! @{ */ -#define GENFSK_PACKET_BUFFER_PACKET_BUFFER_MASK (0xFFFFU) -#define GENFSK_PACKET_BUFFER_PACKET_BUFFER_SHIFT (0U) -#define GENFSK_PACKET_BUFFER_PACKET_BUFFER(x) (((uint16_t)(((uint16_t)(x)) << GENFSK_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & GENFSK_PACKET_BUFFER_PACKET_BUFFER_MASK) -/*! @} */ - -/* The count of GENFSK_PACKET_BUFFER */ -#define GENFSK_PACKET_BUFFER_COUNT (1088U) - - -/*! - * @} - */ /* end of group GENFSK_Register_Masks */ - - -/* GENFSK - Peripheral instance base addresses */ -/** Peripheral GENFSK base address */ -#define GENFSK_BASE (0x41033000u) -/** Peripheral GENFSK base pointer */ -#define GENFSK ((GENFSK_Type *)GENFSK_BASE) -/** Array initializer of GENFSK peripheral base addresses */ -#define GENFSK_BASE_ADDRS { GENFSK_BASE } -/** Array initializer of GENFSK peripheral base pointers */ -#define GENFSK_BASE_PTRS { GENFSK } - -/*! - * @} - */ /* end of group GENFSK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name PDOR - Port Data Output Register */ -/*! @{ */ -#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) -#define GPIO_PDOR_PDO_SHIFT (0U) -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) -/*! @} */ - -/*! @name PSOR - Port Set Output Register */ -/*! @{ */ -#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) -#define GPIO_PSOR_PTSO_SHIFT (0U) -#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) -/*! @} */ - -/*! @name PCOR - Port Clear Output Register */ -/*! @{ */ -#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) -#define GPIO_PCOR_PTCO_SHIFT (0U) -#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) -/*! @} */ - -/*! @name PTOR - Port Toggle Output Register */ -/*! @{ */ -#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) -#define GPIO_PTOR_PTTO_SHIFT (0U) -#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) -/*! @} */ - -/*! @name PDIR - Port Data Input Register */ -/*! @{ */ -#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) -#define GPIO_PDIR_PDI_SHIFT (0U) -#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) -/*! @} */ - -/*! @name PDDR - Port Data Direction Register */ -/*! @{ */ -#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) -#define GPIO_PDDR_PDD_SHIFT (0U) -#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIOA base address */ -#define GPIOA_BASE (0x48020000u) -/** Peripheral GPIOA base pointer */ -#define GPIOA ((GPIO_Type *)GPIOA_BASE) -/** Peripheral GPIOB base address */ -#define GPIOB_BASE (0x48020040u) -/** Peripheral GPIOB base pointer */ -#define GPIOB ((GPIO_Type *)GPIOB_BASE) -/** Peripheral GPIOC base address */ -#define GPIOC_BASE (0x48020080u) -/** Peripheral GPIOC base pointer */ -#define GPIOC ((GPIO_Type *)GPIOC_BASE) -/** Peripheral GPIOD base address */ -#define GPIOD_BASE (0x480200C0u) -/** Peripheral GPIOD base pointer */ -#define GPIOD ((GPIO_Type *)GPIOD_BASE) -/** Peripheral GPIOE base address */ -#define GPIOE_BASE (0x4100F000u) -/** Peripheral GPIOE base pointer */ -#define GPIOE ((GPIO_Type *)GPIOE_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ - __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_0[24]; - __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ - uint8_t RESERVED_2[36]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ - __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_3[24]; - __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[24]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define I2S_VERID_FEATURE_MASK (0xFFFFU) -#define I2S_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard feature set. - */ -#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) -#define I2S_VERID_MINOR_MASK (0xFF0000U) -#define I2S_VERID_MINOR_SHIFT (16U) -#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) -#define I2S_VERID_MAJOR_MASK (0xFF000000U) -#define I2S_VERID_MAJOR_SHIFT (24U) -#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define I2S_PARAM_DATALINE_MASK (0xFU) -#define I2S_PARAM_DATALINE_SHIFT (0U) -#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) -#define I2S_PARAM_FIFO_MASK (0xF00U) -#define I2S_PARAM_FIFO_SHIFT (8U) -#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) -#define I2S_PARAM_FRAME_MASK (0xF0000U) -#define I2S_PARAM_FRAME_SHIFT (16U) -#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) -/*! @} */ - -/*! @name TCSR - SAI Transmit Control Register */ -/*! @{ */ -#define I2S_TCSR_FRDE_MASK (0x1U) -#define I2S_TCSR_FRDE_SHIFT (0U) -/*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) -#define I2S_TCSR_FWDE_MASK (0x2U) -#define I2S_TCSR_FWDE_SHIFT (1U) -/*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) -#define I2S_TCSR_FRIE_MASK (0x100U) -#define I2S_TCSR_FRIE_SHIFT (8U) -/*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) -#define I2S_TCSR_FWIE_MASK (0x200U) -#define I2S_TCSR_FWIE_SHIFT (9U) -/*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) -#define I2S_TCSR_FEIE_MASK (0x400U) -#define I2S_TCSR_FEIE_SHIFT (10U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) -#define I2S_TCSR_SEIE_MASK (0x800U) -#define I2S_TCSR_SEIE_SHIFT (11U) -/*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) -#define I2S_TCSR_WSIE_MASK (0x1000U) -#define I2S_TCSR_WSIE_SHIFT (12U) -/*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) -#define I2S_TCSR_FRF_MASK (0x10000U) -#define I2S_TCSR_FRF_SHIFT (16U) -/*! FRF - FIFO Request Flag - * 0b0..Transmit FIFO watermark has not been reached. - * 0b1..Transmit FIFO watermark has been reached. - */ -#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) -#define I2S_TCSR_FWF_MASK (0x20000U) -#define I2S_TCSR_FWF_SHIFT (17U) -/*! FWF - FIFO Warning Flag - * 0b0..No enabled transmit FIFO is empty. - * 0b1..Enabled transmit FIFO is empty. - */ -#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) -#define I2S_TCSR_FEF_MASK (0x40000U) -#define I2S_TCSR_FEF_SHIFT (18U) -/*! FEF - FIFO Error Flag - * 0b0..Transmit underrun not detected. - * 0b1..Transmit underrun detected. - */ -#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) -#define I2S_TCSR_SEF_MASK (0x80000U) -#define I2S_TCSR_SEF_SHIFT (19U) -/*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. - */ -#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) -#define I2S_TCSR_WSF_MASK (0x100000U) -#define I2S_TCSR_WSF_SHIFT (20U) -/*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. - */ -#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) -#define I2S_TCSR_SR_MASK (0x1000000U) -#define I2S_TCSR_SR_SHIFT (24U) -/*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. - */ -#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) -#define I2S_TCSR_FR_MASK (0x2000000U) -#define I2S_TCSR_FR_SHIFT (25U) -/*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. - */ -#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) -#define I2S_TCSR_BCE_MASK (0x10000000U) -#define I2S_TCSR_BCE_SHIFT (28U) -/*! BCE - Bit Clock Enable - * 0b0..Transmit bit clock is disabled. - * 0b1..Transmit bit clock is enabled. - */ -#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) -#define I2S_TCSR_DBGE_MASK (0x20000000U) -#define I2S_TCSR_DBGE_SHIFT (29U) -/*! DBGE - Debug Enable - * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. - * 0b1..Transmitter is enabled in Debug mode. - */ -#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) -#define I2S_TCSR_STOPE_MASK (0x40000000U) -#define I2S_TCSR_STOPE_SHIFT (30U) -/*! STOPE - Stop Enable - * 0b0..Transmitter disabled in Stop mode. - * 0b1..Transmitter enabled in Stop mode. - */ -#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) -#define I2S_TCSR_TE_MASK (0x80000000U) -#define I2S_TCSR_TE_SHIFT (31U) -/*! TE - Transmitter Enable - * 0b0..Transmitter is disabled. - * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. - */ -#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) -/*! @} */ - -/*! @name TCR1 - SAI Transmit Configuration 1 Register */ -/*! @{ */ -#define I2S_TCR1_TFW_MASK (0x7U) -#define I2S_TCR1_TFW_SHIFT (0U) -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) -/*! @} */ - -/*! @name TCR2 - SAI Transmit Configuration 2 Register */ -/*! @{ */ -#define I2S_TCR2_DIV_MASK (0xFFU) -#define I2S_TCR2_DIV_SHIFT (0U) -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) -#define I2S_TCR2_BCD_MASK (0x1000000U) -#define I2S_TCR2_BCD_SHIFT (24U) -/*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. - */ -#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) -#define I2S_TCR2_BCP_MASK (0x2000000U) -#define I2S_TCR2_BCP_SHIFT (25U) -/*! BCP - Bit Clock Polarity - * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. - */ -#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) -#define I2S_TCR2_MSEL_MASK (0xC000000U) -#define I2S_TCR2_MSEL_SHIFT (26U) -/*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. - */ -#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) -#define I2S_TCR2_BCI_MASK (0x10000000U) -#define I2S_TCR2_BCI_SHIFT (28U) -/*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. - */ -#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) -#define I2S_TCR2_BCS_MASK (0x20000000U) -#define I2S_TCR2_BCS_SHIFT (29U) -/*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. - */ -#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) -#define I2S_TCR2_SYNC_MASK (0xC0000000U) -#define I2S_TCR2_SYNC_SHIFT (30U) -/*! SYNC - Synchronous Mode - * 0b00..Asynchronous mode. - * 0b01..Synchronous with receiver. - * 0b10..Synchronous with another SAI transmitter. - * 0b11..Synchronous with another SAI receiver. - */ -#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) -/*! @} */ - -/*! @name TCR3 - SAI Transmit Configuration 3 Register */ -/*! @{ */ -#define I2S_TCR3_WDFL_MASK (0x1FU) -#define I2S_TCR3_WDFL_SHIFT (0U) -#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) -#define I2S_TCR3_TCE_MASK (0x30000U) -#define I2S_TCR3_TCE_SHIFT (16U) -#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) -#define I2S_TCR3_CFR_MASK (0x3000000U) -#define I2S_TCR3_CFR_SHIFT (24U) -#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) -/*! @} */ - -/*! @name TCR4 - SAI Transmit Configuration 4 Register */ -/*! @{ */ -#define I2S_TCR4_FSD_MASK (0x1U) -#define I2S_TCR4_FSD_SHIFT (0U) -/*! FSD - Frame Sync Direction - * 0b0..Frame sync is generated externally in Slave mode. - * 0b1..Frame sync is generated internally in Master mode. - */ -#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) -#define I2S_TCR4_FSP_MASK (0x2U) -#define I2S_TCR4_FSP_SHIFT (1U) -/*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. - */ -#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) -#define I2S_TCR4_ONDEM_MASK (0x4U) -#define I2S_TCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. - */ -#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) -#define I2S_TCR4_FSE_MASK (0x8U) -#define I2S_TCR4_FSE_SHIFT (3U) -/*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. - */ -#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) -#define I2S_TCR4_MF_MASK (0x10U) -#define I2S_TCR4_MF_SHIFT (4U) -/*! MF - MSB First - * 0b0..LSB is transmitted first. - * 0b1..MSB is transmitted first. - */ -#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) -#define I2S_TCR4_CHMOD_MASK (0x20U) -#define I2S_TCR4_CHMOD_SHIFT (5U) -/*! CHMOD - Channel Mode - * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. - * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. - */ -#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) -#define I2S_TCR4_SYWD_MASK (0x1F00U) -#define I2S_TCR4_SYWD_SHIFT (8U) -#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) -#define I2S_TCR4_FRSZ_MASK (0x1F0000U) -#define I2S_TCR4_FRSZ_SHIFT (16U) -#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) -#define I2S_TCR4_FPACK_MASK (0x3000000U) -#define I2S_TCR4_FPACK_SHIFT (24U) -/*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled - * 0b01..Reserved - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled - */ -#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) -#define I2S_TCR4_FCOMB_MASK (0xC000000U) -#define I2S_TCR4_FCOMB_SHIFT (26U) -/*! FCOMB - FIFO Combine Mode - * 0b00..FIFO combine mode disabled. - * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). - * 0b10..FIFO combine mode enabled on FIFO writes (by software). - * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). - */ -#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) -#define I2S_TCR4_FCONT_MASK (0x10000000U) -#define I2S_TCR4_FCONT_SHIFT (28U) -/*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. - */ -#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) -/*! @} */ - -/*! @name TCR5 - SAI Transmit Configuration 5 Register */ -/*! @{ */ -#define I2S_TCR5_FBT_MASK (0x1F00U) -#define I2S_TCR5_FBT_SHIFT (8U) -#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) -#define I2S_TCR5_W0W_MASK (0x1F0000U) -#define I2S_TCR5_W0W_SHIFT (16U) -#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) -#define I2S_TCR5_WNW_MASK (0x1F000000U) -#define I2S_TCR5_WNW_SHIFT (24U) -#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) -/*! @} */ - -/*! @name TDR - SAI Transmit Data Register */ -/*! @{ */ -#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) -#define I2S_TDR_TDR_SHIFT (0U) -#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) -/*! @} */ - -/* The count of I2S_TDR */ -#define I2S_TDR_COUNT (2U) - -/*! @name TFR - SAI Transmit FIFO Register */ -/*! @{ */ -#define I2S_TFR_RFP_MASK (0xFU) -#define I2S_TFR_RFP_SHIFT (0U) -#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) -#define I2S_TFR_WFP_MASK (0xF0000U) -#define I2S_TFR_WFP_SHIFT (16U) -#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) -#define I2S_TFR_WCP_MASK (0x80000000U) -#define I2S_TFR_WCP_SHIFT (31U) -/*! WCP - Write Channel Pointer - * 0b0..No effect. - * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. - */ -#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) -/*! @} */ - -/* The count of I2S_TFR */ -#define I2S_TFR_COUNT (2U) - -/*! @name TMR - SAI Transmit Mask Register */ -/*! @{ */ -#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) -#define I2S_TMR_TWM_SHIFT (0U) -/*! TWM - Transmit Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. - */ -#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) -/*! @} */ - -/*! @name RCSR - SAI Receive Control Register */ -/*! @{ */ -#define I2S_RCSR_FRDE_MASK (0x1U) -#define I2S_RCSR_FRDE_SHIFT (0U) -/*! FRDE - FIFO Request DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) -#define I2S_RCSR_FWDE_MASK (0x2U) -#define I2S_RCSR_FWDE_SHIFT (1U) -/*! FWDE - FIFO Warning DMA Enable - * 0b0..Disables the DMA request. - * 0b1..Enables the DMA request. - */ -#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) -#define I2S_RCSR_FRIE_MASK (0x100U) -#define I2S_RCSR_FRIE_SHIFT (8U) -/*! FRIE - FIFO Request Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) -#define I2S_RCSR_FWIE_MASK (0x200U) -#define I2S_RCSR_FWIE_SHIFT (9U) -/*! FWIE - FIFO Warning Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) -#define I2S_RCSR_FEIE_MASK (0x400U) -#define I2S_RCSR_FEIE_SHIFT (10U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disables the interrupt. - * 0b1..Enables the interrupt. - */ -#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) -#define I2S_RCSR_SEIE_MASK (0x800U) -#define I2S_RCSR_SEIE_SHIFT (11U) -/*! SEIE - Sync Error Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) -#define I2S_RCSR_WSIE_MASK (0x1000U) -#define I2S_RCSR_WSIE_SHIFT (12U) -/*! WSIE - Word Start Interrupt Enable - * 0b0..Disables interrupt. - * 0b1..Enables interrupt. - */ -#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) -#define I2S_RCSR_FRF_MASK (0x10000U) -#define I2S_RCSR_FRF_SHIFT (16U) -/*! FRF - FIFO Request Flag - * 0b0..Receive FIFO watermark not reached. - * 0b1..Receive FIFO watermark has been reached. - */ -#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) -#define I2S_RCSR_FWF_MASK (0x20000U) -#define I2S_RCSR_FWF_SHIFT (17U) -/*! FWF - FIFO Warning Flag - * 0b0..No enabled receive FIFO is full. - * 0b1..Enabled receive FIFO is full. - */ -#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) -#define I2S_RCSR_FEF_MASK (0x40000U) -#define I2S_RCSR_FEF_SHIFT (18U) -/*! FEF - FIFO Error Flag - * 0b0..Receive overflow not detected. - * 0b1..Receive overflow detected. - */ -#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) -#define I2S_RCSR_SEF_MASK (0x80000U) -#define I2S_RCSR_SEF_SHIFT (19U) -/*! SEF - Sync Error Flag - * 0b0..Sync error not detected. - * 0b1..Frame sync error detected. - */ -#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) -#define I2S_RCSR_WSF_MASK (0x100000U) -#define I2S_RCSR_WSF_SHIFT (20U) -/*! WSF - Word Start Flag - * 0b0..Start of word not detected. - * 0b1..Start of word detected. - */ -#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) -#define I2S_RCSR_SR_MASK (0x1000000U) -#define I2S_RCSR_SR_SHIFT (24U) -/*! SR - Software Reset - * 0b0..No effect. - * 0b1..Software reset. - */ -#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) -#define I2S_RCSR_FR_MASK (0x2000000U) -#define I2S_RCSR_FR_SHIFT (25U) -/*! FR - FIFO Reset - * 0b0..No effect. - * 0b1..FIFO reset. - */ -#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) -#define I2S_RCSR_BCE_MASK (0x10000000U) -#define I2S_RCSR_BCE_SHIFT (28U) -/*! BCE - Bit Clock Enable - * 0b0..Receive bit clock is disabled. - * 0b1..Receive bit clock is enabled. - */ -#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) -#define I2S_RCSR_DBGE_MASK (0x20000000U) -#define I2S_RCSR_DBGE_SHIFT (29U) -/*! DBGE - Debug Enable - * 0b0..Receiver is disabled in Debug mode, after completing the current frame. - * 0b1..Receiver is enabled in Debug mode. - */ -#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) -#define I2S_RCSR_STOPE_MASK (0x40000000U) -#define I2S_RCSR_STOPE_SHIFT (30U) -/*! STOPE - Stop Enable - * 0b0..Receiver disabled in Stop mode. - * 0b1..Receiver enabled in Stop mode. - */ -#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) -#define I2S_RCSR_RE_MASK (0x80000000U) -#define I2S_RCSR_RE_SHIFT (31U) -/*! RE - Receiver Enable - * 0b0..Receiver is disabled. - * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. - */ -#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) -/*! @} */ - -/*! @name RCR1 - SAI Receive Configuration 1 Register */ -/*! @{ */ -#define I2S_RCR1_RFW_MASK (0x7U) -#define I2S_RCR1_RFW_SHIFT (0U) -#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) -/*! @} */ - -/*! @name RCR2 - SAI Receive Configuration 2 Register */ -/*! @{ */ -#define I2S_RCR2_DIV_MASK (0xFFU) -#define I2S_RCR2_DIV_SHIFT (0U) -#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) -#define I2S_RCR2_BCD_MASK (0x1000000U) -#define I2S_RCR2_BCD_SHIFT (24U) -/*! BCD - Bit Clock Direction - * 0b0..Bit clock is generated externally in Slave mode. - * 0b1..Bit clock is generated internally in Master mode. - */ -#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) -#define I2S_RCR2_BCP_MASK (0x2000000U) -#define I2S_RCR2_BCP_SHIFT (25U) -/*! BCP - Bit Clock Polarity - * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. - * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. - */ -#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) -#define I2S_RCR2_MSEL_MASK (0xC000000U) -#define I2S_RCR2_MSEL_SHIFT (26U) -/*! MSEL - MCLK Select - * 0b00..Bus Clock selected. - * 0b01..Master Clock (MCLK) 1 option selected. - * 0b10..Master Clock (MCLK) 2 option selected. - * 0b11..Master Clock (MCLK) 3 option selected. - */ -#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) -#define I2S_RCR2_BCI_MASK (0x10000000U) -#define I2S_RCR2_BCI_SHIFT (28U) -/*! BCI - Bit Clock Input - * 0b0..No effect. - * 0b1..Internal logic is clocked as if bit clock was externally generated. - */ -#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) -#define I2S_RCR2_BCS_MASK (0x20000000U) -#define I2S_RCR2_BCS_SHIFT (29U) -/*! BCS - Bit Clock Swap - * 0b0..Use the normal bit clock source. - * 0b1..Swap the bit clock source. - */ -#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) -#define I2S_RCR2_SYNC_MASK (0xC0000000U) -#define I2S_RCR2_SYNC_SHIFT (30U) -/*! SYNC - Synchronous Mode - * 0b00..Asynchronous mode. - * 0b01..Synchronous with transmitter. - * 0b10..Synchronous with another SAI receiver. - * 0b11..Synchronous with another SAI transmitter. - */ -#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) -/*! @} */ - -/*! @name RCR3 - SAI Receive Configuration 3 Register */ -/*! @{ */ -#define I2S_RCR3_WDFL_MASK (0x1FU) -#define I2S_RCR3_WDFL_SHIFT (0U) -#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) -#define I2S_RCR3_RCE_MASK (0x30000U) -#define I2S_RCR3_RCE_SHIFT (16U) -#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) -#define I2S_RCR3_CFR_MASK (0x3000000U) -#define I2S_RCR3_CFR_SHIFT (24U) -#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) -/*! @} */ - -/*! @name RCR4 - SAI Receive Configuration 4 Register */ -/*! @{ */ -#define I2S_RCR4_FSD_MASK (0x1U) -#define I2S_RCR4_FSD_SHIFT (0U) -/*! FSD - Frame Sync Direction - * 0b0..Frame Sync is generated externally in Slave mode. - * 0b1..Frame Sync is generated internally in Master mode. - */ -#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) -#define I2S_RCR4_FSP_MASK (0x2U) -#define I2S_RCR4_FSP_SHIFT (1U) -/*! FSP - Frame Sync Polarity - * 0b0..Frame sync is active high. - * 0b1..Frame sync is active low. - */ -#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) -#define I2S_RCR4_ONDEM_MASK (0x4U) -#define I2S_RCR4_ONDEM_SHIFT (2U) -/*! ONDEM - On Demand Mode - * 0b0..Internal frame sync is generated continuously. - * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. - */ -#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) -#define I2S_RCR4_FSE_MASK (0x8U) -#define I2S_RCR4_FSE_SHIFT (3U) -/*! FSE - Frame Sync Early - * 0b0..Frame sync asserts with the first bit of the frame. - * 0b1..Frame sync asserts one bit before the first bit of the frame. - */ -#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) -#define I2S_RCR4_MF_MASK (0x10U) -#define I2S_RCR4_MF_SHIFT (4U) -/*! MF - MSB First - * 0b0..LSB is received first. - * 0b1..MSB is received first. - */ -#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) -#define I2S_RCR4_SYWD_MASK (0x1F00U) -#define I2S_RCR4_SYWD_SHIFT (8U) -#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) -#define I2S_RCR4_FRSZ_MASK (0x1F0000U) -#define I2S_RCR4_FRSZ_SHIFT (16U) -#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) -#define I2S_RCR4_FPACK_MASK (0x3000000U) -#define I2S_RCR4_FPACK_SHIFT (24U) -/*! FPACK - FIFO Packing Mode - * 0b00..FIFO packing is disabled - * 0b01..Reserved. - * 0b10..8-bit FIFO packing is enabled - * 0b11..16-bit FIFO packing is enabled - */ -#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) -#define I2S_RCR4_FCOMB_MASK (0xC000000U) -#define I2S_RCR4_FCOMB_SHIFT (26U) -/*! FCOMB - FIFO Combine Mode - * 0b00..FIFO combine mode disabled. - * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). - * 0b10..FIFO combine mode enabled on FIFO reads (by software). - * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). - */ -#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) -#define I2S_RCR4_FCONT_MASK (0x10000000U) -#define I2S_RCR4_FCONT_SHIFT (28U) -/*! FCONT - FIFO Continue on Error - * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. - * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. - */ -#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) -/*! @} */ - -/*! @name RCR5 - SAI Receive Configuration 5 Register */ -/*! @{ */ -#define I2S_RCR5_FBT_MASK (0x1F00U) -#define I2S_RCR5_FBT_SHIFT (8U) -#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) -#define I2S_RCR5_W0W_MASK (0x1F0000U) -#define I2S_RCR5_W0W_SHIFT (16U) -#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) -#define I2S_RCR5_WNW_MASK (0x1F000000U) -#define I2S_RCR5_WNW_SHIFT (24U) -#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) -/*! @} */ - -/*! @name RDR - SAI Receive Data Register */ -/*! @{ */ -#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) -#define I2S_RDR_RDR_SHIFT (0U) -#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) -/*! @} */ - -/* The count of I2S_RDR */ -#define I2S_RDR_COUNT (2U) - -/*! @name RFR - SAI Receive FIFO Register */ -/*! @{ */ -#define I2S_RFR_RFP_MASK (0xFU) -#define I2S_RFR_RFP_SHIFT (0U) -#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) -#define I2S_RFR_RCP_MASK (0x8000U) -#define I2S_RFR_RCP_SHIFT (15U) -/*! RCP - Receive Channel Pointer - * 0b0..No effect. - * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. - */ -#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) -#define I2S_RFR_WFP_MASK (0xF0000U) -#define I2S_RFR_WFP_SHIFT (16U) -#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) -/*! @} */ - -/* The count of I2S_RFR */ -#define I2S_RFR_COUNT (2U) - -/*! @name RMR - SAI Receive Mask Register */ -/*! @{ */ -#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) -#define I2S_RMR_RWM_SHIFT (0U) -/*! RWM - Receive Word Mask - * 0b00000000000000000000000000000000..Word N is enabled. - * 0b00000000000000000000000000000001..Word N is masked. - */ -#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x4003D000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { I2S0_IRQn } -#define I2S_TX_IRQS { I2S0_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer - * @{ - */ - -/** INTMUX - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x40 */ - __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */ - __I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */ - uint8_t RESERVED_1[12]; - __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */ - uint8_t RESERVED_2[28]; - } CHANNEL[8]; -} INTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INTMUX_Register_Masks INTMUX Register Masks - * @{ - */ - -/*! @name CHn_CSR - Channel n Control Status Register */ -/*! @{ */ -#define INTMUX_CHn_CSR_RST_MASK (0x1U) -#define INTMUX_CHn_CSR_RST_SHIFT (0U) -/*! RST - Software Reset - * 0b0..No operation. - * 0b1..Perform a software reset on this channel. - */ -#define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK) -#define INTMUX_CHn_CSR_AND_MASK (0x2U) -#define INTMUX_CHn_CSR_AND_SHIFT (1U) -/*! AND - Logic AND - * 0b0..Logic OR all enabled interrupt inputs. - * 0b1..Logic AND all enabled interrupt inputs. - */ -#define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK) -#define INTMUX_CHn_CSR_IRQN_MASK (0x30U) -#define INTMUX_CHn_CSR_IRQN_SHIFT (4U) -/*! IRQN - Channel Input Number - * 0b00..32 interrupt inputs - * 0b01..Reserved - * 0b10..Reserved - * 0b11..Reserved - */ -#define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK) -#define INTMUX_CHn_CSR_CHIN_MASK (0xF00U) -#define INTMUX_CHn_CSR_CHIN_SHIFT (8U) -#define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK) -#define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) -#define INTMUX_CHn_CSR_IRQP_SHIFT (31U) -/*! IRQP - Channel Interrupt Request Pending - * 0b0..No interrupt is pending. - * 0b1..The interrupt output of this channel is pending. - */ -#define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_CSR */ -#define INTMUX_CHn_CSR_COUNT (8U) - -/*! @name CHn_VEC - Channel n Vector Number Register */ -/*! @{ */ -#define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU) -#define INTMUX_CHn_VEC_VECN_SHIFT (2U) -#define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_VEC */ -#define INTMUX_CHn_VEC_COUNT (8U) - -/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */ -/*! @{ */ -#define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU) -#define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U) -#define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_IER_31_0 */ -#define INTMUX_CHn_IER_31_0_COUNT (8U) - -/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */ -/*! @{ */ -#define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU) -#define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U) -#define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK) -/*! @} */ - -/* The count of INTMUX_CHn_IPR_31_0 */ -#define INTMUX_CHn_IPR_31_0_COUNT (8U) - - -/*! - * @} - */ /* end of group INTMUX_Register_Masks */ - - -/* INTMUX - Peripheral instance base addresses */ -/** Peripheral INTMUX1 base address */ -#define INTMUX1_BASE (0x41022000u) -/** Peripheral INTMUX1 base pointer */ -#define INTMUX1 ((INTMUX_Type *)INTMUX1_BASE) -/** Array initializer of INTMUX peripheral base addresses */ -#define INTMUX_BASE_ADDRS { 0u, INTMUX1_BASE } -/** Array initializer of INTMUX peripheral base pointers */ -#define INTMUX_BASE_PTRS { (INTMUX_Type *)0u, INTMUX1 } -/** Interrupt vectors for the INTMUX peripheral type */ -#define INTMUX_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { INTMUX1_0_IRQn, INTMUX1_1_IRQn, INTMUX1_2_IRQn, INTMUX1_3_IRQn, INTMUX1_4_IRQn, INTMUX1_5_IRQn, INTMUX1_6_IRQn, INTMUX1_7_IRQn } } - -/*! - * @} - */ /* end of group INTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer - * @{ - */ - -/** LLWU - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t PE1; /**< Pin Enable 1 register, offset: 0x8 */ - __IO uint32_t PE2; /**< Pin Enable 2 register, offset: 0xC */ - uint8_t RESERVED_0[8]; - __IO uint32_t ME; /**< Module Interrupt Enable register, offset: 0x18 */ - __IO uint32_t DE; /**< Module DMA/Trigger Enable register, offset: 0x1C */ - __IO uint32_t PF; /**< Pin Flag register, offset: 0x20 */ - uint8_t RESERVED_1[12]; - __IO uint32_t FILT; /**< Pin Filter register, offset: 0x30 */ - uint8_t RESERVED_2[4]; - __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1 register, offset: 0x38 */ - __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2 register, offset: 0x3C */ - uint8_t RESERVED_3[8]; - __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration register, offset: 0x48 */ - uint8_t RESERVED_4[4]; - __IO uint32_t PMC; /**< Pin Mode Configuration register, offset: 0x50 */ - uint8_t RESERVED_5[4]; - __IO uint32_t FMC; /**< Pin Filter Mode Configuration register, offset: 0x58 */ -} LLWU_Type; - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LLWU_VERID_FEATURE_MASK (0xFFFFU) -#define LLWU_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented - * 0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled. - */ -#define LLWU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK) -#define LLWU_VERID_MINOR_MASK (0xFF0000U) -#define LLWU_VERID_MINOR_SHIFT (16U) -#define LLWU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK) -#define LLWU_VERID_MAJOR_MASK (0xFF000000U) -#define LLWU_VERID_MAJOR_SHIFT (24U) -#define LLWU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LLWU_PARAM_FILTERS_MASK (0xFFU) -#define LLWU_PARAM_FILTERS_SHIFT (0U) -#define LLWU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK) -#define LLWU_PARAM_DMAS_MASK (0xFF00U) -#define LLWU_PARAM_DMAS_SHIFT (8U) -#define LLWU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK) -#define LLWU_PARAM_MODULES_MASK (0xFF0000U) -#define LLWU_PARAM_MODULES_SHIFT (16U) -#define LLWU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK) -#define LLWU_PARAM_PINS_MASK (0xFF000000U) -#define LLWU_PARAM_PINS_SHIFT (24U) -#define LLWU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK) -/*! @} */ - -/*! @name PE1 - Pin Enable 1 register */ -/*! @{ */ -#define LLWU_PE1_WUPE0_MASK (0x3U) -#define LLWU_PE1_WUPE0_SHIFT (0U) -/*! WUPE0 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) -#define LLWU_PE1_WUPE1_MASK (0xCU) -#define LLWU_PE1_WUPE1_SHIFT (2U) -/*! WUPE1 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) -#define LLWU_PE1_WUPE2_MASK (0x30U) -#define LLWU_PE1_WUPE2_SHIFT (4U) -/*! WUPE2 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) -#define LLWU_PE1_WUPE3_MASK (0xC0U) -#define LLWU_PE1_WUPE3_SHIFT (6U) -/*! WUPE3 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) -#define LLWU_PE1_WUPE4_MASK (0x300U) -#define LLWU_PE1_WUPE4_SHIFT (8U) -/*! WUPE4 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK) -#define LLWU_PE1_WUPE5_MASK (0xC00U) -#define LLWU_PE1_WUPE5_SHIFT (10U) -/*! WUPE5 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK) -#define LLWU_PE1_WUPE6_MASK (0x3000U) -#define LLWU_PE1_WUPE6_SHIFT (12U) -/*! WUPE6 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK) -#define LLWU_PE1_WUPE7_MASK (0xC000U) -#define LLWU_PE1_WUPE7_SHIFT (14U) -/*! WUPE7 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK) -#define LLWU_PE1_WUPE8_MASK (0x30000U) -#define LLWU_PE1_WUPE8_SHIFT (16U) -/*! WUPE8 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK) -#define LLWU_PE1_WUPE9_MASK (0xC0000U) -#define LLWU_PE1_WUPE9_SHIFT (18U) -/*! WUPE9 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK) -#define LLWU_PE1_WUPE10_MASK (0x300000U) -#define LLWU_PE1_WUPE10_SHIFT (20U) -/*! WUPE10 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK) -#define LLWU_PE1_WUPE11_MASK (0xC00000U) -#define LLWU_PE1_WUPE11_SHIFT (22U) -/*! WUPE11 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK) -#define LLWU_PE1_WUPE12_MASK (0x3000000U) -#define LLWU_PE1_WUPE12_SHIFT (24U) -/*! WUPE12 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK) -#define LLWU_PE1_WUPE13_MASK (0xC000000U) -#define LLWU_PE1_WUPE13_SHIFT (26U) -/*! WUPE13 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK) -#define LLWU_PE1_WUPE14_MASK (0x30000000U) -#define LLWU_PE1_WUPE14_SHIFT (28U) -/*! WUPE14 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK) -#define LLWU_PE1_WUPE15_MASK (0xC0000000U) -#define LLWU_PE1_WUPE15_SHIFT (30U) -/*! WUPE15 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK) -/*! @} */ - -/*! @name PE2 - Pin Enable 2 register */ -/*! @{ */ -#define LLWU_PE2_WUPE16_MASK (0x3U) -#define LLWU_PE2_WUPE16_SHIFT (0U) -/*! WUPE16 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK) -#define LLWU_PE2_WUPE17_MASK (0xCU) -#define LLWU_PE2_WUPE17_SHIFT (2U) -/*! WUPE17 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK) -#define LLWU_PE2_WUPE18_MASK (0x30U) -#define LLWU_PE2_WUPE18_SHIFT (4U) -/*! WUPE18 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK) -#define LLWU_PE2_WUPE19_MASK (0xC0U) -#define LLWU_PE2_WUPE19_SHIFT (6U) -/*! WUPE19 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK) -#define LLWU_PE2_WUPE20_MASK (0x300U) -#define LLWU_PE2_WUPE20_SHIFT (8U) -/*! WUPE20 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK) -#define LLWU_PE2_WUPE21_MASK (0xC00U) -#define LLWU_PE2_WUPE21_SHIFT (10U) -/*! WUPE21 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK) -#define LLWU_PE2_WUPE22_MASK (0x3000U) -#define LLWU_PE2_WUPE22_SHIFT (12U) -/*! WUPE22 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK) -#define LLWU_PE2_WUPE23_MASK (0xC000U) -#define LLWU_PE2_WUPE23_SHIFT (14U) -/*! WUPE23 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK) -#define LLWU_PE2_WUPE24_MASK (0x30000U) -#define LLWU_PE2_WUPE24_SHIFT (16U) -/*! WUPE24 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK) -#define LLWU_PE2_WUPE25_MASK (0xC0000U) -#define LLWU_PE2_WUPE25_SHIFT (18U) -/*! WUPE25 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK) -#define LLWU_PE2_WUPE26_MASK (0x300000U) -#define LLWU_PE2_WUPE26_SHIFT (20U) -/*! WUPE26 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK) -#define LLWU_PE2_Reserved27_MASK (0xC00000U) -#define LLWU_PE2_Reserved27_SHIFT (22U) -/*! Reserved27 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved27_SHIFT)) & LLWU_PE2_Reserved27_MASK) -#define LLWU_PE2_Reserved28_MASK (0x3000000U) -#define LLWU_PE2_Reserved28_SHIFT (24U) -/*! Reserved28 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved28_SHIFT)) & LLWU_PE2_Reserved28_MASK) -#define LLWU_PE2_WUPE29_MASK (0xC000000U) -#define LLWU_PE2_WUPE29_SHIFT (26U) -/*! WUPE29 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK) -#define LLWU_PE2_WUPE30_MASK (0x30000000U) -#define LLWU_PE2_WUPE30_SHIFT (28U) -/*! WUPE30 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK) -#define LLWU_PE2_WUPE31_MASK (0xC0000000U) -#define LLWU_PE2_WUPE31_SHIFT (30U) -/*! WUPE31 - Wakeup pin enable for LLWU_Pn - * 0b00..External input pin disabled as wakeup input - * 0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..External input pin enabled with any change detection when configured as interrupt/DMA request - */ -#define LLWU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK) -/*! @} */ - -/*! @name ME - Module Interrupt Enable register */ -/*! @{ */ -#define LLWU_ME_WUME0_MASK (0x1U) -#define LLWU_ME_WUME0_SHIFT (0U) -/*! WUME0 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) -#define LLWU_ME_WUME1_MASK (0x2U) -#define LLWU_ME_WUME1_SHIFT (1U) -/*! WUME1 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) -#define LLWU_ME_WUME2_MASK (0x4U) -#define LLWU_ME_WUME2_SHIFT (2U) -/*! WUME2 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) -#define LLWU_ME_Reserved3_MASK (0x8U) -#define LLWU_ME_Reserved3_SHIFT (3U) -/*! Reserved3 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK) -#define LLWU_ME_WUME3_MASK (0x8U) -#define LLWU_ME_WUME3_SHIFT (3U) -/*! WUME3 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) -#define LLWU_ME_Reserved4_MASK (0x10U) -#define LLWU_ME_Reserved4_SHIFT (4U) -/*! Reserved4 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved4_SHIFT)) & LLWU_ME_Reserved4_MASK) -#define LLWU_ME_WUME5_MASK (0x20U) -#define LLWU_ME_WUME5_SHIFT (5U) -/*! WUME5 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) -#define LLWU_ME_WUME6_MASK (0x40U) -#define LLWU_ME_WUME6_SHIFT (6U) -/*! WUME6 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) -#define LLWU_ME_WUME7_MASK (0x80U) -#define LLWU_ME_WUME7_SHIFT (7U) -/*! WUME7 - Wakeup module enable for module n - * 0b0..Internal module flag not used as wakeup source - * 0b1..Internal module flag used as wakeup source - */ -#define LLWU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) -/*! @} */ - -/*! @name DE - Module DMA/Trigger Enable register */ -/*! @{ */ -#define LLWU_DE_WUDE0_MASK (0x1U) -#define LLWU_DE_WUDE0_SHIFT (0U) -/*! WUDE0 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK) -#define LLWU_DE_WUDE1_MASK (0x2U) -#define LLWU_DE_WUDE1_SHIFT (1U) -/*! WUDE1 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK) -#define LLWU_DE_WUDE2_MASK (0x4U) -#define LLWU_DE_WUDE2_SHIFT (2U) -/*! WUDE2 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK) -#define LLWU_DE_Reserved3_MASK (0x8U) -#define LLWU_DE_Reserved3_SHIFT (3U) -/*! Reserved3 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved3_SHIFT)) & LLWU_DE_Reserved3_MASK) -#define LLWU_DE_WUDE4_MASK (0x10U) -#define LLWU_DE_WUDE4_SHIFT (4U) -/*! WUDE4 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK) -#define LLWU_DE_WUDE5_MASK (0x20U) -#define LLWU_DE_WUDE5_SHIFT (5U) -/*! WUDE5 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK) -#define LLWU_DE_WUDE6_MASK (0x40U) -#define LLWU_DE_WUDE6_SHIFT (6U) -/*! WUDE6 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK) -#define LLWU_DE_Reserved7_MASK (0x80U) -#define LLWU_DE_Reserved7_SHIFT (7U) -/*! Reserved7 - DMA/Trigger wakeup enable for module n - * 0b0..Internal module request not enabled as a DMA/Trigger wakeup source - * 0b1..Internal module request enabled as a DMA/Trigger wakeup source - */ -#define LLWU_DE_Reserved7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved7_SHIFT)) & LLWU_DE_Reserved7_MASK) -/*! @} */ - -/*! @name PF - Pin Flag register */ -/*! @{ */ -#define LLWU_PF_WUF0_MASK (0x1U) -#define LLWU_PF_WUF0_SHIFT (0U) -/*! WUF0 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK) -#define LLWU_PF_WUF1_MASK (0x2U) -#define LLWU_PF_WUF1_SHIFT (1U) -/*! WUF1 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK) -#define LLWU_PF_WUF2_MASK (0x4U) -#define LLWU_PF_WUF2_SHIFT (2U) -/*! WUF2 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK) -#define LLWU_PF_WUF3_MASK (0x8U) -#define LLWU_PF_WUF3_SHIFT (3U) -/*! WUF3 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK) -#define LLWU_PF_WUF4_MASK (0x10U) -#define LLWU_PF_WUF4_SHIFT (4U) -/*! WUF4 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK) -#define LLWU_PF_WUF5_MASK (0x20U) -#define LLWU_PF_WUF5_SHIFT (5U) -/*! WUF5 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK) -#define LLWU_PF_WUF6_MASK (0x40U) -#define LLWU_PF_WUF6_SHIFT (6U) -/*! WUF6 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK) -#define LLWU_PF_WUF7_MASK (0x80U) -#define LLWU_PF_WUF7_SHIFT (7U) -/*! WUF7 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK) -#define LLWU_PF_WUF8_MASK (0x100U) -#define LLWU_PF_WUF8_SHIFT (8U) -/*! WUF8 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK) -#define LLWU_PF_WUF9_MASK (0x200U) -#define LLWU_PF_WUF9_SHIFT (9U) -/*! WUF9 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK) -#define LLWU_PF_WUF10_MASK (0x400U) -#define LLWU_PF_WUF10_SHIFT (10U) -/*! WUF10 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK) -#define LLWU_PF_WUF11_MASK (0x800U) -#define LLWU_PF_WUF11_SHIFT (11U) -/*! WUF11 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK) -#define LLWU_PF_WUF12_MASK (0x1000U) -#define LLWU_PF_WUF12_SHIFT (12U) -/*! WUF12 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK) -#define LLWU_PF_WUF13_MASK (0x2000U) -#define LLWU_PF_WUF13_SHIFT (13U) -/*! WUF13 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK) -#define LLWU_PF_WUF14_MASK (0x4000U) -#define LLWU_PF_WUF14_SHIFT (14U) -/*! WUF14 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK) -#define LLWU_PF_WUF15_MASK (0x8000U) -#define LLWU_PF_WUF15_SHIFT (15U) -/*! WUF15 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK) -#define LLWU_PF_WUF16_MASK (0x10000U) -#define LLWU_PF_WUF16_SHIFT (16U) -/*! WUF16 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK) -#define LLWU_PF_WUF17_MASK (0x20000U) -#define LLWU_PF_WUF17_SHIFT (17U) -/*! WUF17 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK) -#define LLWU_PF_WUF18_MASK (0x40000U) -#define LLWU_PF_WUF18_SHIFT (18U) -/*! WUF18 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK) -#define LLWU_PF_WUF19_MASK (0x80000U) -#define LLWU_PF_WUF19_SHIFT (19U) -/*! WUF19 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK) -#define LLWU_PF_WUF20_MASK (0x100000U) -#define LLWU_PF_WUF20_SHIFT (20U) -/*! WUF20 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK) -#define LLWU_PF_WUF21_MASK (0x200000U) -#define LLWU_PF_WUF21_SHIFT (21U) -/*! WUF21 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK) -#define LLWU_PF_WUF22_MASK (0x400000U) -#define LLWU_PF_WUF22_SHIFT (22U) -/*! WUF22 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK) -#define LLWU_PF_WUF23_MASK (0x800000U) -#define LLWU_PF_WUF23_SHIFT (23U) -/*! WUF23 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK) -#define LLWU_PF_WUF24_MASK (0x1000000U) -#define LLWU_PF_WUF24_SHIFT (24U) -/*! WUF24 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK) -#define LLWU_PF_WUF25_MASK (0x2000000U) -#define LLWU_PF_WUF25_SHIFT (25U) -/*! WUF25 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK) -#define LLWU_PF_WUF26_MASK (0x4000000U) -#define LLWU_PF_WUF26_SHIFT (26U) -/*! WUF26 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK) -#define LLWU_PF_Reserved27_MASK (0x8000000U) -#define LLWU_PF_Reserved27_SHIFT (27U) -/*! Reserved27 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved27_SHIFT)) & LLWU_PF_Reserved27_MASK) -#define LLWU_PF_Reserved28_MASK (0x10000000U) -#define LLWU_PF_Reserved28_SHIFT (28U) -/*! Reserved28 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved28_SHIFT)) & LLWU_PF_Reserved28_MASK) -#define LLWU_PF_WUF29_MASK (0x20000000U) -#define LLWU_PF_WUF29_SHIFT (29U) -/*! WUF29 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK) -#define LLWU_PF_WUF30_MASK (0x40000000U) -#define LLWU_PF_WUF30_SHIFT (30U) -/*! WUF30 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK) -#define LLWU_PF_WUF31_MASK (0x80000000U) -#define LLWU_PF_WUF31_SHIFT (31U) -/*! WUF31 - Wakeup flag for LLWU_Pn - * 0b0..LLWU_Pn input was not a wakeup source - * 0b1..LLWU_Pn input was a wakeup source - */ -#define LLWU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK) -/*! @} */ - -/*! @name FILT - Pin Filter register */ -/*! @{ */ -#define LLWU_FILT_FILTSEL1_MASK (0x1FU) -#define LLWU_FILT_FILTSEL1_SHIFT (0U) -/*! FILTSEL1 - Filter 1 Pin Select - * 0b00000..Select LLWU_P0 for filter - * 0b11111..Select LLWU_P31 for filter - */ -#define LLWU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK) -#define LLWU_FILT_FILTE1_MASK (0x60U) -#define LLWU_FILT_FILTE1_SHIFT (5U) -/*! FILTE1 - Filter 1 Enable - * 0b00..Filter disabled - * 0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..Filter any edge detect enabled when configured as interrupt/DMA request - */ -#define LLWU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK) -#define LLWU_FILT_FILTF1_MASK (0x80U) -#define LLWU_FILT_FILTF1_SHIFT (7U) -/*! FILTF1 - Filter 1 Flag - * 0b0..Pin Filter 1 was not a wakeup source - * 0b1..Pin Filter 1 was a wakeup source - */ -#define LLWU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK) -#define LLWU_FILT_FILTSEL2_MASK (0x1F00U) -#define LLWU_FILT_FILTSEL2_SHIFT (8U) -/*! FILTSEL2 - Filter 2 Pin Select - * 0b00000..Select LLWU_P0 for filter - * 0b11111..Select LLWU_P31 for filter - */ -#define LLWU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK) -#define LLWU_FILT_FILTE2_MASK (0x6000U) -#define LLWU_FILT_FILTE2_SHIFT (13U) -/*! FILTE2 - Filter 2 Enable - * 0b00..Filter disabled - * 0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request - * 0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request - * 0b11..Filter any edge detect enabled when configured as interrupt/DMA request - */ -#define LLWU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK) -#define LLWU_FILT_FILTF2_MASK (0x8000U) -#define LLWU_FILT_FILTF2_SHIFT (15U) -/*! FILTF2 - Filter 2 Flag - * 0b0..Pin Filter 2 was not a wakeup source - * 0b1..Pin Filter 2 was a wakeup source - */ -#define LLWU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK) -/*! @} */ - -/*! @name PDC1 - Pin DMA/Trigger Configuration 1 register */ -/*! @{ */ -#define LLWU_PDC1_WUPDC0_MASK (0x3U) -#define LLWU_PDC1_WUPDC0_SHIFT (0U) -/*! WUPDC0 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC0_SHIFT)) & LLWU_PDC1_WUPDC0_MASK) -#define LLWU_PDC1_WUPDC1_MASK (0xCU) -#define LLWU_PDC1_WUPDC1_SHIFT (2U) -/*! WUPDC1 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC1_SHIFT)) & LLWU_PDC1_WUPDC1_MASK) -#define LLWU_PDC1_WUPDC2_MASK (0x30U) -#define LLWU_PDC1_WUPDC2_SHIFT (4U) -/*! WUPDC2 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC2_SHIFT)) & LLWU_PDC1_WUPDC2_MASK) -#define LLWU_PDC1_WUPDC3_MASK (0xC0U) -#define LLWU_PDC1_WUPDC3_SHIFT (6U) -/*! WUPDC3 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC3_SHIFT)) & LLWU_PDC1_WUPDC3_MASK) -#define LLWU_PDC1_WUPDC4_MASK (0x300U) -#define LLWU_PDC1_WUPDC4_SHIFT (8U) -/*! WUPDC4 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC4_SHIFT)) & LLWU_PDC1_WUPDC4_MASK) -#define LLWU_PDC1_WUPDC5_MASK (0xC00U) -#define LLWU_PDC1_WUPDC5_SHIFT (10U) -/*! WUPDC5 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC5_SHIFT)) & LLWU_PDC1_WUPDC5_MASK) -#define LLWU_PDC1_WUPDC6_MASK (0x3000U) -#define LLWU_PDC1_WUPDC6_SHIFT (12U) -/*! WUPDC6 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC6_SHIFT)) & LLWU_PDC1_WUPDC6_MASK) -#define LLWU_PDC1_WUPDC7_MASK (0xC000U) -#define LLWU_PDC1_WUPDC7_SHIFT (14U) -/*! WUPDC7 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC7_SHIFT)) & LLWU_PDC1_WUPDC7_MASK) -#define LLWU_PDC1_WUPDC8_MASK (0x30000U) -#define LLWU_PDC1_WUPDC8_SHIFT (16U) -/*! WUPDC8 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC8_SHIFT)) & LLWU_PDC1_WUPDC8_MASK) -#define LLWU_PDC1_WUPDC9_MASK (0xC0000U) -#define LLWU_PDC1_WUPDC9_SHIFT (18U) -/*! WUPDC9 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC9_SHIFT)) & LLWU_PDC1_WUPDC9_MASK) -#define LLWU_PDC1_WUPDC10_MASK (0x300000U) -#define LLWU_PDC1_WUPDC10_SHIFT (20U) -/*! WUPDC10 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC10_SHIFT)) & LLWU_PDC1_WUPDC10_MASK) -#define LLWU_PDC1_WUPDC11_MASK (0xC00000U) -#define LLWU_PDC1_WUPDC11_SHIFT (22U) -/*! WUPDC11 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC11_SHIFT)) & LLWU_PDC1_WUPDC11_MASK) -#define LLWU_PDC1_WUPDC12_MASK (0x3000000U) -#define LLWU_PDC1_WUPDC12_SHIFT (24U) -/*! WUPDC12 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC12_SHIFT)) & LLWU_PDC1_WUPDC12_MASK) -#define LLWU_PDC1_WUPDC13_MASK (0xC000000U) -#define LLWU_PDC1_WUPDC13_SHIFT (26U) -/*! WUPDC13 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC13_SHIFT)) & LLWU_PDC1_WUPDC13_MASK) -#define LLWU_PDC1_WUPDC14_MASK (0x30000000U) -#define LLWU_PDC1_WUPDC14_SHIFT (28U) -/*! WUPDC14 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC14_SHIFT)) & LLWU_PDC1_WUPDC14_MASK) -#define LLWU_PDC1_WUPDC15_MASK (0xC0000000U) -#define LLWU_PDC1_WUPDC15_SHIFT (30U) -/*! WUPDC15 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC15_SHIFT)) & LLWU_PDC1_WUPDC15_MASK) -/*! @} */ - -/*! @name PDC2 - Pin DMA/Trigger Configuration 2 register */ -/*! @{ */ -#define LLWU_PDC2_WUPDC16_MASK (0x3U) -#define LLWU_PDC2_WUPDC16_SHIFT (0U) -/*! WUPDC16 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC16_SHIFT)) & LLWU_PDC2_WUPDC16_MASK) -#define LLWU_PDC2_WUPDC17_MASK (0xCU) -#define LLWU_PDC2_WUPDC17_SHIFT (2U) -/*! WUPDC17 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC17_SHIFT)) & LLWU_PDC2_WUPDC17_MASK) -#define LLWU_PDC2_WUPDC18_MASK (0x30U) -#define LLWU_PDC2_WUPDC18_SHIFT (4U) -/*! WUPDC18 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC18_SHIFT)) & LLWU_PDC2_WUPDC18_MASK) -#define LLWU_PDC2_WUPDC19_MASK (0xC0U) -#define LLWU_PDC2_WUPDC19_SHIFT (6U) -/*! WUPDC19 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC19_SHIFT)) & LLWU_PDC2_WUPDC19_MASK) -#define LLWU_PDC2_WUPDC20_MASK (0x300U) -#define LLWU_PDC2_WUPDC20_SHIFT (8U) -/*! WUPDC20 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC20_SHIFT)) & LLWU_PDC2_WUPDC20_MASK) -#define LLWU_PDC2_WUPDC21_MASK (0xC00U) -#define LLWU_PDC2_WUPDC21_SHIFT (10U) -/*! WUPDC21 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC21_SHIFT)) & LLWU_PDC2_WUPDC21_MASK) -#define LLWU_PDC2_WUPDC22_MASK (0x3000U) -#define LLWU_PDC2_WUPDC22_SHIFT (12U) -/*! WUPDC22 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC22_SHIFT)) & LLWU_PDC2_WUPDC22_MASK) -#define LLWU_PDC2_WUPDC23_MASK (0xC000U) -#define LLWU_PDC2_WUPDC23_SHIFT (14U) -/*! WUPDC23 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC23_SHIFT)) & LLWU_PDC2_WUPDC23_MASK) -#define LLWU_PDC2_WUPDC24_MASK (0x30000U) -#define LLWU_PDC2_WUPDC24_SHIFT (16U) -/*! WUPDC24 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC24_SHIFT)) & LLWU_PDC2_WUPDC24_MASK) -#define LLWU_PDC2_WUPDC25_MASK (0xC0000U) -#define LLWU_PDC2_WUPDC25_SHIFT (18U) -/*! WUPDC25 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC25_SHIFT)) & LLWU_PDC2_WUPDC25_MASK) -#define LLWU_PDC2_WUPDC26_MASK (0x300000U) -#define LLWU_PDC2_WUPDC26_SHIFT (20U) -/*! WUPDC26 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC26_SHIFT)) & LLWU_PDC2_WUPDC26_MASK) -#define LLWU_PDC2_Reserved27_MASK (0xC00000U) -#define LLWU_PDC2_Reserved27_SHIFT (22U) -/*! Reserved27 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved27_SHIFT)) & LLWU_PDC2_Reserved27_MASK) -#define LLWU_PDC2_Reserved28_MASK (0x3000000U) -#define LLWU_PDC2_Reserved28_SHIFT (24U) -/*! Reserved28 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved28_SHIFT)) & LLWU_PDC2_Reserved28_MASK) -#define LLWU_PDC2_WUPDC29_MASK (0xC000000U) -#define LLWU_PDC2_WUPDC29_SHIFT (26U) -/*! WUPDC29 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC29_SHIFT)) & LLWU_PDC2_WUPDC29_MASK) -#define LLWU_PDC2_WUPDC30_MASK (0x30000000U) -#define LLWU_PDC2_WUPDC30_SHIFT (28U) -/*! WUPDC30 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC30_SHIFT)) & LLWU_PDC2_WUPDC30_MASK) -#define LLWU_PDC2_WUPDC31_MASK (0xC0000000U) -#define LLWU_PDC2_WUPDC31_SHIFT (30U) -/*! WUPDC31 - Wakeup pin configuration for LLWU_Pn - * 0b00..External input pin configured as interrupt - * 0b01..External input pin configured as DMA request - * 0b10..External input pin configured as trigger event - * 0b11..Reserved - */ -#define LLWU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC31_SHIFT)) & LLWU_PDC2_WUPDC31_MASK) -/*! @} */ - -/*! @name FDC - Pin Filter DMA/Trigger Configuration register */ -/*! @{ */ -#define LLWU_FDC_FILTC1_MASK (0x3U) -#define LLWU_FDC_FILTC1_SHIFT (0U) -/*! FILTC1 - Filter configuration for FILT1 - * 0b00..Filter output configured as interrupt - * 0b01..Filter output configured as DMA request - * 0b10..Filter output configured as trigger event - * 0b11..Reserved - */ -#define LLWU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC1_SHIFT)) & LLWU_FDC_FILTC1_MASK) -#define LLWU_FDC_FILTC2_MASK (0xCU) -#define LLWU_FDC_FILTC2_SHIFT (2U) -/*! FILTC2 - Filter configuration for FILT2 - * 0b00..Filter output configured as interrupt - * 0b01..Filter output configured as DMA request - * 0b10..Filter output configured as trigger event - * 0b11..Reserved - */ -#define LLWU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC2_SHIFT)) & LLWU_FDC_FILTC2_MASK) -/*! @} */ - -/*! @name PMC - Pin Mode Configuration register */ -/*! @{ */ -#define LLWU_PMC_WUPMC0_MASK (0x1U) -#define LLWU_PMC_WUPMC0_SHIFT (0U) -/*! WUPMC0 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC0_SHIFT)) & LLWU_PMC_WUPMC0_MASK) -#define LLWU_PMC_WUPMC1_MASK (0x2U) -#define LLWU_PMC_WUPMC1_SHIFT (1U) -/*! WUPMC1 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC1_SHIFT)) & LLWU_PMC_WUPMC1_MASK) -#define LLWU_PMC_WUPMC2_MASK (0x4U) -#define LLWU_PMC_WUPMC2_SHIFT (2U) -/*! WUPMC2 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC2_SHIFT)) & LLWU_PMC_WUPMC2_MASK) -#define LLWU_PMC_WUPMC3_MASK (0x8U) -#define LLWU_PMC_WUPMC3_SHIFT (3U) -/*! WUPMC3 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC3_SHIFT)) & LLWU_PMC_WUPMC3_MASK) -#define LLWU_PMC_WUPMC4_MASK (0x10U) -#define LLWU_PMC_WUPMC4_SHIFT (4U) -/*! WUPMC4 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC4_SHIFT)) & LLWU_PMC_WUPMC4_MASK) -#define LLWU_PMC_WUPMC5_MASK (0x20U) -#define LLWU_PMC_WUPMC5_SHIFT (5U) -/*! WUPMC5 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC5_SHIFT)) & LLWU_PMC_WUPMC5_MASK) -#define LLWU_PMC_WUPMC6_MASK (0x40U) -#define LLWU_PMC_WUPMC6_SHIFT (6U) -/*! WUPMC6 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC6_SHIFT)) & LLWU_PMC_WUPMC6_MASK) -#define LLWU_PMC_WUPMC7_MASK (0x80U) -#define LLWU_PMC_WUPMC7_SHIFT (7U) -/*! WUPMC7 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC7_SHIFT)) & LLWU_PMC_WUPMC7_MASK) -#define LLWU_PMC_WUPMC8_MASK (0x100U) -#define LLWU_PMC_WUPMC8_SHIFT (8U) -/*! WUPMC8 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC8_SHIFT)) & LLWU_PMC_WUPMC8_MASK) -#define LLWU_PMC_WUPMC9_MASK (0x200U) -#define LLWU_PMC_WUPMC9_SHIFT (9U) -/*! WUPMC9 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC9_SHIFT)) & LLWU_PMC_WUPMC9_MASK) -#define LLWU_PMC_WUPMC10_MASK (0x400U) -#define LLWU_PMC_WUPMC10_SHIFT (10U) -/*! WUPMC10 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC10_SHIFT)) & LLWU_PMC_WUPMC10_MASK) -#define LLWU_PMC_WUPMC11_MASK (0x800U) -#define LLWU_PMC_WUPMC11_SHIFT (11U) -/*! WUPMC11 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC11_SHIFT)) & LLWU_PMC_WUPMC11_MASK) -#define LLWU_PMC_WUPMC12_MASK (0x1000U) -#define LLWU_PMC_WUPMC12_SHIFT (12U) -/*! WUPMC12 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC12_SHIFT)) & LLWU_PMC_WUPMC12_MASK) -#define LLWU_PMC_WUPMC13_MASK (0x2000U) -#define LLWU_PMC_WUPMC13_SHIFT (13U) -/*! WUPMC13 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC13_SHIFT)) & LLWU_PMC_WUPMC13_MASK) -#define LLWU_PMC_WUPMC14_MASK (0x4000U) -#define LLWU_PMC_WUPMC14_SHIFT (14U) -/*! WUPMC14 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC14_SHIFT)) & LLWU_PMC_WUPMC14_MASK) -#define LLWU_PMC_WUPMC15_MASK (0x8000U) -#define LLWU_PMC_WUPMC15_SHIFT (15U) -/*! WUPMC15 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC15_SHIFT)) & LLWU_PMC_WUPMC15_MASK) -#define LLWU_PMC_WUPMC16_MASK (0x10000U) -#define LLWU_PMC_WUPMC16_SHIFT (16U) -/*! WUPMC16 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC16_SHIFT)) & LLWU_PMC_WUPMC16_MASK) -#define LLWU_PMC_WUPMC17_MASK (0x20000U) -#define LLWU_PMC_WUPMC17_SHIFT (17U) -/*! WUPMC17 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC17_SHIFT)) & LLWU_PMC_WUPMC17_MASK) -#define LLWU_PMC_WUPMC18_MASK (0x40000U) -#define LLWU_PMC_WUPMC18_SHIFT (18U) -/*! WUPMC18 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC18_SHIFT)) & LLWU_PMC_WUPMC18_MASK) -#define LLWU_PMC_WUPMC19_MASK (0x80000U) -#define LLWU_PMC_WUPMC19_SHIFT (19U) -/*! WUPMC19 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC19_SHIFT)) & LLWU_PMC_WUPMC19_MASK) -#define LLWU_PMC_WUPMC20_MASK (0x100000U) -#define LLWU_PMC_WUPMC20_SHIFT (20U) -/*! WUPMC20 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC20_SHIFT)) & LLWU_PMC_WUPMC20_MASK) -#define LLWU_PMC_WUPMC21_MASK (0x200000U) -#define LLWU_PMC_WUPMC21_SHIFT (21U) -/*! WUPMC21 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC21_SHIFT)) & LLWU_PMC_WUPMC21_MASK) -#define LLWU_PMC_WUPMC22_MASK (0x400000U) -#define LLWU_PMC_WUPMC22_SHIFT (22U) -/*! WUPMC22 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC22_SHIFT)) & LLWU_PMC_WUPMC22_MASK) -#define LLWU_PMC_WUPMC23_MASK (0x800000U) -#define LLWU_PMC_WUPMC23_SHIFT (23U) -/*! WUPMC23 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC23_SHIFT)) & LLWU_PMC_WUPMC23_MASK) -#define LLWU_PMC_WUPMC24_MASK (0x1000000U) -#define LLWU_PMC_WUPMC24_SHIFT (24U) -/*! WUPMC24 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC24_SHIFT)) & LLWU_PMC_WUPMC24_MASK) -#define LLWU_PMC_WUPMC25_MASK (0x2000000U) -#define LLWU_PMC_WUPMC25_SHIFT (25U) -/*! WUPMC25 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC25_SHIFT)) & LLWU_PMC_WUPMC25_MASK) -#define LLWU_PMC_WUPMC26_MASK (0x4000000U) -#define LLWU_PMC_WUPMC26_SHIFT (26U) -/*! WUPMC26 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC26_SHIFT)) & LLWU_PMC_WUPMC26_MASK) -#define LLWU_PMC_Reserved27_MASK (0x8000000U) -#define LLWU_PMC_Reserved27_SHIFT (27U) -/*! Reserved27 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_Reserved27(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved27_SHIFT)) & LLWU_PMC_Reserved27_MASK) -#define LLWU_PMC_Reserved28_MASK (0x10000000U) -#define LLWU_PMC_Reserved28_SHIFT (28U) -/*! Reserved28 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved28_SHIFT)) & LLWU_PMC_Reserved28_MASK) -#define LLWU_PMC_WUPMC29_MASK (0x20000000U) -#define LLWU_PMC_WUPMC29_SHIFT (29U) -/*! WUPMC29 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC29_SHIFT)) & LLWU_PMC_WUPMC29_MASK) -#define LLWU_PMC_WUPMC30_MASK (0x40000000U) -#define LLWU_PMC_WUPMC30_SHIFT (30U) -/*! WUPMC30 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC30_SHIFT)) & LLWU_PMC_WUPMC30_MASK) -#define LLWU_PMC_WUPMC31_MASK (0x80000000U) -#define LLWU_PMC_WUPMC31_SHIFT (31U) -/*! WUPMC31 - Wakeup pin mode for LLWU_Pn - * 0b0..External input pin detection active only during LLS/VLLS mode - * 0b1..External input pin detection active during all power modes - */ -#define LLWU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC31_SHIFT)) & LLWU_PMC_WUPMC31_MASK) -/*! @} */ - -/*! @name FMC - Pin Filter Mode Configuration register */ -/*! @{ */ -#define LLWU_FMC_FILTM1_MASK (0x1U) -#define LLWU_FMC_FILTM1_SHIFT (0U) -/*! FILTM1 - Filter Mode for FILT1 - * 0b0..External input pin filter detection active only during LLS/VLLS mode - * 0b1..External input pin filter detection active during all power modes - */ -#define LLWU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM1_SHIFT)) & LLWU_FMC_FILTM1_MASK) -#define LLWU_FMC_FILTM2_MASK (0x2U) -#define LLWU_FMC_FILTM2_SHIFT (1U) -/*! FILTM2 - Filter Mode for FILT2 - * 0b0..External input pin filter detection active only during LLS/VLLS mode - * 0b1..External input pin filter detection active during all power modes - */ -#define LLWU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM2_SHIFT)) & LLWU_FMC_FILTM2_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LLWU_Register_Masks */ - - -/* LLWU - Peripheral instance base addresses */ -/** Peripheral LLWU0 base address */ -#define LLWU0_BASE (0x40024000u) -/** Peripheral LLWU0 base pointer */ -#define LLWU0 ((LLWU_Type *)LLWU0_BASE) -/** Peripheral LLWU1 base address */ -#define LLWU1_BASE (0x41023000u) -/** Peripheral LLWU1 base pointer */ -#define LLWU1 ((LLWU_Type *)LLWU1_BASE) -/** Array initializer of LLWU peripheral base addresses */ -#define LLWU_BASE_ADDRS { LLWU0_BASE, LLWU1_BASE } -/** Array initializer of LLWU peripheral base pointers */ -#define LLWU_BASE_PTRS { LLWU0, LLWU1 } -/** Interrupt vectors for the LLWU peripheral type */ -#define LLWU_IRQS { NotAvail_IRQn, LLWU1_IRQn } - -/*! - * @} - */ /* end of group LLWU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPCMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer - * @{ - */ - -/** LPCMP - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ - __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ - __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DCR; /**< DAC Control Register, offset: 0x18 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ -} LPCMP_Type; - -/* ---------------------------------------------------------------------------- - -- LPCMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPCMP_Register_Masks LPCMP Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) -#define LPCMP_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000001..Round robin feature - */ -#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) -#define LPCMP_VERID_MINOR_MASK (0xFF0000U) -#define LPCMP_VERID_MINOR_SHIFT (16U) -#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) -#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) -#define LPCMP_VERID_MAJOR_SHIFT (24U) -#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPCMP_PARAM_DAC_RES_MASK (0xFU) -#define LPCMP_PARAM_DAC_RES_SHIFT (0U) -/*! DAC_RES - DAC resolution - * 0b0000..4 bit DAC - * 0b0001..6 bit DAC - * 0b0010..8 bit DAC - * 0b0011..10 bit DAC - * 0b0100..12 bit DAC - * 0b0101..14 bit DAC - * 0b0110..16 bit DAC - */ -#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) -/*! @} */ - -/*! @name CCR0 - Comparator Control Register 0 */ -/*! @{ */ -#define LPCMP_CCR0_CMP_EN_MASK (0x1U) -#define LPCMP_CCR0_CMP_EN_SHIFT (0U) -/*! CMP_EN - Comparator Module Enable - * 0b0..Analog Comparator is disabled. - * 0b1..Analog Comparator is enabled. - */ -#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) -#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) -#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) -/*! CMP_STOP_EN - Comparator Module STOP Mode Enable - * 0b0..Comparator is disabled in STOP modes regardless of CMP_EN. - * 0b1..Comparator is enabled in STOP mode if CMP_EN is active - */ -#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) -/*! @} */ - -/*! @name CCR1 - Comparator Control Register 1 */ -/*! @{ */ -#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) -#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) -/*! WINDOW_EN - Windowing Enable - * 0b0..Windowing mode is not selected. - * 0b1..Windowing mode is selected. - */ -#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) -#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) -#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) -/*! SAMPLE_EN - Sample Enable - * 0b0..Sampling mode is not selected. - * 0b1..Sampling mode is selected. - */ -#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) -#define LPCMP_CCR1_DMA_EN_MASK (0x4U) -#define LPCMP_CCR1_DMA_EN_SHIFT (2U) -/*! DMA_EN - DMA Enable - * 0b0..DMA is disabled. - * 0b1..DMA is enabled. - */ -#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) -#define LPCMP_CCR1_COUT_INV_MASK (0x8U) -#define LPCMP_CCR1_COUT_INV_SHIFT (3U) -/*! COUT_INV - Comparator invert - * 0b0..Does not invert the comparator output. - * 0b1..Inverts the comparator output. - */ -#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) -#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) -#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) -/*! COUT_SEL - Comparator Output Select - * 0b0..Set CMPO to equal COUT (filtered comparator output). - * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). - */ -#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) -#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) -#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) -/*! COUT_PEN - Comparator Output Pin Enable - * 0b0..When COUT_PEN is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. - * 0b1..When COUT_PEN is 1, and if the software has configured the comparator to own a packaged pin, the comparator output is available in a packaged pin. - */ -#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) -#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) -#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) -/*! FILT_CNT - Filter Sample Count - * 0b000..Filter is disabled. If SAMPLE_EN = 1, then COUT is a logic zero (this is not a legal state in , and is not recommended). If SAMPLE_EN = 0, COUT = COUTA. - * 0b001..1 consecutive sample must agree (comparator output is simply sampled). - * 0b010..2 consecutive samples must agree. - * 0b011..3 consecutive samples must agree. - * 0b100..4 consecutive samples must agree. - * 0b101..5 consecutive samples must agree. - * 0b110..6 consecutive samples must agree. - * 0b111..7 consecutive samples must agree. - */ -#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) -#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) -#define LPCMP_CCR1_FILT_PER_SHIFT (24U) -#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) -/*! @} */ - -/*! @name CCR2 - Comparator Control Register 2 */ -/*! @{ */ -#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) -#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) -/*! CMP_HPMD - CMP High Power Mode Select - * 0b0..Low speed comparison mode is selected.(when CMP_NPMD is 0) - * 0b1..High speed comparison mode is selected.(when CMP_NPMD is 0) - */ -#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) -#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) -#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) -/*! CMP_NPMD - CMP Nano Power Mode Select - * 0b0..Nano Power Comparator is not enabled (mode is determined by CMP_HPMD) - * 0b1..Nano Power Comparator is enabled - */ -#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) -#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) -#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) -/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level - * 0b00..The hard block output has level 0 hysteresis internally. - * 0b01..The hard block output has level 1 hysteresis internally. - * 0b10..The hard block output has level 2 hysteresis internally. - * 0b11..The hard block output has level 3 hysteresis internally. - */ -#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) -#define LPCMP_CCR2_PSEL_MASK (0x70000U) -#define LPCMP_CCR2_PSEL_SHIFT (16U) -/*! PSEL - Plus Input MUX Control - * 0b000..Input 0 - * 0b001..Input 1 - * 0b010..Input 2 - * 0b011..Input 3 - * 0b100..Input 4 - * 0b101..Input 5 - * 0b110..Input 6 - * 0b111..Internal DAC output - */ -#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) -#define LPCMP_CCR2_MSEL_MASK (0x700000U) -#define LPCMP_CCR2_MSEL_SHIFT (20U) -/*! MSEL - Minus Input MUX Control - * 0b000..Input 0 - * 0b001..Input 1 - * 0b010..Input 2 - * 0b011..Input 3 - * 0b100..Input 4 - * 0b101..Input 5 - * 0b110..Input 6 - * 0b111..Internal DAC output - */ -#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) -/*! @} */ - -/*! @name DCR - DAC Control Register */ -/*! @{ */ -#define LPCMP_DCR_DAC_EN_MASK (0x1U) -#define LPCMP_DCR_DAC_EN_SHIFT (0U) -/*! DAC_EN - DAC Enable - * 0b0..DAC is disabled. - * 0b1..DAC is enabled. - */ -#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) -#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) -#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) -/*! DAC_HPMD - DAC High Power Mode Select - * 0b0..DAC high power mode is not enabled. - * 0b1..DAC high power mode is enabled. - */ -#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) -#define LPCMP_DCR_VRSEL_MASK (0x100U) -#define LPCMP_DCR_VRSEL_SHIFT (8U) -/*! VRSEL - Supply Voltage Reference Source Select - * 0b0..vrefh_int is selected as resistor ladder network supply reference Vin. - * 0b1..vrefh_ext is selected as resistor ladder network supply reference Vin. - */ -#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) -#define LPCMP_DCR_DAC_DATA_MASK (0x3F0000U) -#define LPCMP_DCR_DAC_DATA_SHIFT (16U) -#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ -#define LPCMP_IER_CFR_IE_MASK (0x1U) -#define LPCMP_IER_CFR_IE_SHIFT (0U) -/*! CFR_IE - Comparator Flag Rising Interrupt Enable - * 0b0..CFR interrupt is disabled. - * 0b1..CFR interrupt is enabled. - */ -#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) -#define LPCMP_IER_CFF_IE_MASK (0x2U) -#define LPCMP_IER_CFF_IE_SHIFT (1U) -/*! CFF_IE - Comparator Flag Falling Interrupt Enable - * 0b0..CFF interrupt is disabled. - * 0b1..CFF interrupt is enabled. - */ -#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) -/*! @} */ - -/*! @name CSR - Comparator Status Register */ -/*! @{ */ -#define LPCMP_CSR_CFR_MASK (0x1U) -#define LPCMP_CSR_CFR_SHIFT (0U) -/*! CFR - Analog Comparator Flag Rising - * 0b0..A rising edge has not been detected on COUT. - * 0b1..A rising edge on COUT has occurred. - */ -#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) -#define LPCMP_CSR_CFF_MASK (0x2U) -#define LPCMP_CSR_CFF_SHIFT (1U) -/*! CFF - Analog Comparator Flag Falling - * 0b0..A falling edge has not been detected on COUT. - * 0b1..A falling edge on COUT has occurred. - */ -#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) -#define LPCMP_CSR_COUT_MASK (0x100U) -#define LPCMP_CSR_COUT_SHIFT (8U) -#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPCMP_Register_Masks */ - - -/* LPCMP - Peripheral instance base addresses */ -/** Peripheral LPCMP0 base address */ -#define LPCMP0_BASE (0x4004B000u) -/** Peripheral LPCMP0 base pointer */ -#define LPCMP0 ((LPCMP_Type *)LPCMP0_BASE) -/** Peripheral LPCMP1 base address */ -#define LPCMP1_BASE (0x41038000u) -/** Peripheral LPCMP1 base pointer */ -#define LPCMP1 ((LPCMP_Type *)LPCMP1_BASE) -/** Array initializer of LPCMP peripheral base addresses */ -#define LPCMP_BASE_ADDRS { LPCMP0_BASE, LPCMP1_BASE } -/** Array initializer of LPCMP peripheral base pointers */ -#define LPCMP_BASE_PTRS { LPCMP0, LPCMP1 } -/** Interrupt vectors for the LPCMP peripheral type */ -#define LPCMP_IRQS { LPCMP0_IRQn, LPCMP1_IRQn } - -/*! - * @} - */ /* end of group LPCMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPDAC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer - * @{ - */ - -/** LPDAC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */ - __IO uint32_t GCR; /**< DAC Global Control Register, offset: 0xC */ - __IO uint32_t FCR; /**< DAC FIFO Control Register, offset: 0x10 */ - __I uint32_t FPR; /**< DAC FIFO Pointer Register, offset: 0x14 */ - __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x18 */ - __IO uint32_t IER; /**< DAC Interrupt Enable Register, offset: 0x1C */ - __IO uint32_t DER; /**< DAC DMA Enable Register, offset: 0x20 */ - __IO uint32_t RCR; /**< DAC Reset Control Register, offset: 0x24 */ - __O uint32_t TCR; /**< DAC Trigger Control Register, offset: 0x28 */ -} LPDAC_Type; - -/* ---------------------------------------------------------------------------- - -- LPDAC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPDAC_Register_Masks LPDAC Register Masks - * @{ - */ - -/*! @name VERID - Version Identifier Register */ -/*! @{ */ -#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) -#define LPDAC_VERID_FEATURE_SHIFT (0U) -#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) -#define LPDAC_VERID_MINOR_MASK (0xFF0000U) -#define LPDAC_VERID_MINOR_SHIFT (16U) -#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) -#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) -#define LPDAC_VERID_MAJOR_SHIFT (24U) -#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) -#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) -/*! FIFOSZ - FIFO size - * 0b000..Reserved - * 0b001..FIFO depth is 4 - * 0b010..FIFO depth is 8 - * 0b011..FIFO depth is 16 - * 0b100..FIFO depth is 32 - * 0b101..FIFO depth is 64 - * 0b110..FIFO depth is 128 - * 0b111..FIFO depth is 256 - */ -#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) -/*! @} */ - -/*! @name DATA - DAC Data Register */ -/*! @{ */ -#define LPDAC_DATA_DATA_MASK (0xFFFU) -#define LPDAC_DATA_DATA_SHIFT (0U) -#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) -/*! @} */ - -/*! @name GCR - DAC Global Control Register */ -/*! @{ */ -#define LPDAC_GCR_DACEN_MASK (0x1U) -#define LPDAC_GCR_DACEN_SHIFT (0U) -/*! DACEN - DAC Enable - * 0b0..The DAC system is disabled. - * 0b1..The DAC system is enabled. - */ -#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) -#define LPDAC_GCR_DACRFS_MASK (0x2U) -#define LPDAC_GCR_DACRFS_SHIFT (1U) -/*! DACRFS - DAC Reference Select - * 0b0..The DAC selects VREFH_INT as the reference voltage. - * 0b1..The DAC selects VREFH_EXT as the reference voltage. - */ -#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) -#define LPDAC_GCR_LPEN_MASK (0x4U) -#define LPDAC_GCR_LPEN_SHIFT (2U) -/*! LPEN - Low Power Enable - * 0b0..High-Power mode - * 0b1..Low-Power mode - */ -#define LPDAC_GCR_LPEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LPEN_SHIFT)) & LPDAC_GCR_LPEN_MASK) -#define LPDAC_GCR_FIFOEN_MASK (0x8U) -#define LPDAC_GCR_FIFOEN_SHIFT (3U) -/*! FIFOEN - FIFO Enable - * 0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion. - * 0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion - */ -#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) -#define LPDAC_GCR_SWMD_MASK (0x10U) -#define LPDAC_GCR_SWMD_SHIFT (4U) -/*! SWMD - Swing Back Mode - * 0b0..Swing back mode disable - * 0b1..Swing back mode enable - */ -#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) -#define LPDAC_GCR_TRGSEL_MASK (0x20U) -#define LPDAC_GCR_TRGSEL_SHIFT (5U) -/*! TRGSEL - DAC Trigger Select - * 0b0..The DAC hardware trigger is selected. - * 0b1..The DAC software trigger is selected. - */ -#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) -/*! @} */ - -/*! @name FCR - DAC FIFO Control Register */ -/*! @{ */ -#define LPDAC_FCR_WML_MASK (0xFU) -#define LPDAC_FCR_WML_SHIFT (0U) -#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) -/*! @} */ - -/*! @name FPR - DAC FIFO Pointer Register */ -/*! @{ */ -#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) -#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) -#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) -#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) -#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) -#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ -#define LPDAC_FSR_FULL_MASK (0x1U) -#define LPDAC_FSR_FULL_SHIFT (0U) -/*! FULL - FIFO Full Flag - * 0b0..FIFO is not full - * 0b1..FIFO is full - */ -#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) -#define LPDAC_FSR_EMPTY_MASK (0x2U) -#define LPDAC_FSR_EMPTY_SHIFT (1U) -/*! EMPTY - FIFO Empty Flag - * 0b0..FIFO is not empty - * 0b1..FIFO is empty - */ -#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) -#define LPDAC_FSR_WM_MASK (0x4U) -#define LPDAC_FSR_WM_SHIFT (2U) -/*! WM - FIFO Watermark Status Flag - * 0b0..Data in FIFO is more than watermark level - * 0b1..Data in FIFO is less than or equal to watermark level - */ -#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) -#define LPDAC_FSR_SWBK_MASK (0x8U) -#define LPDAC_FSR_SWBK_SHIFT (3U) -/*! SWBK - Swing Back One Cycle Complete Flag - * 0b0..No swing back cycle has completed since the last time the flag was cleared. - * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) -#define LPDAC_FSR_OF_MASK (0x40U) -#define LPDAC_FSR_OF_SHIFT (6U) -/*! OF - FIFO Overflow Flag - * 0b0..No overflow has occurred since the last time the flag was cleared. - * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) -#define LPDAC_FSR_UF_MASK (0x80U) -#define LPDAC_FSR_UF_SHIFT (7U) -/*! UF - FIFO Underflow Flag - * 0b0..No underflow has occurred since the last time the flag was cleared. - * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. - */ -#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) -/*! @} */ - -/*! @name IER - DAC Interrupt Enable Register */ -/*! @{ */ -#define LPDAC_IER_FULL_IE_MASK (0x1U) -#define LPDAC_IER_FULL_IE_SHIFT (0U) -/*! FULL_IE - FIFO Full Interrupt Enable - * 0b0..FIFO Full interrupt is disabled. - * 0b1..FIFO Full interrupt is enabled. - */ -#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) -#define LPDAC_IER_EMPTY_IE_MASK (0x2U) -#define LPDAC_IER_EMPTY_IE_SHIFT (1U) -/*! EMPTY_IE - FIFO Empty Interrupt Enable - * 0b0..FIFO Empty interrupt is disabled. - * 0b1..FIFO Empty interrupt is enabled. - */ -#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) -#define LPDAC_IER_WM_IE_MASK (0x4U) -#define LPDAC_IER_WM_IE_SHIFT (2U) -/*! WM_IE - FIFO Watermark Interrupt Enable - * 0b0..Watermark interrupt is disabled. - * 0b1..Watermark interrupt is enabled. - */ -#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) -#define LPDAC_IER_SWBK_IE_MASK (0x8U) -#define LPDAC_IER_SWBK_IE_SHIFT (3U) -/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable - * 0b0..Swing back one time complete interrupt is disabled. - * 0b1..Swing back one time complete interrupt is enabled. - */ -#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) -#define LPDAC_IER_OF_IE_MASK (0x40U) -#define LPDAC_IER_OF_IE_SHIFT (6U) -/*! OF_IE - FIFO Overflow Interrupt Enable - * 0b0..Overflow interrupt is disabled - * 0b1..Overflow interrupt is enabled. - */ -#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) -#define LPDAC_IER_UF_IE_MASK (0x80U) -#define LPDAC_IER_UF_IE_SHIFT (7U) -/*! UF_IE - FIFO Underflow Interrupt Enable - * 0b0..Underflow interrupt is disabled. - * 0b1..Underflow interrupt is enabled. - */ -#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) -/*! @} */ - -/*! @name DER - DAC DMA Enable Register */ -/*! @{ */ -#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) -#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) -/*! EMPTY_DMAEN - FIFO Empty DMA Enable - * 0b0..FIFO Empty DMA request is disabled. - * 0b1..FIFO Empty DMA request is enabled. - */ -#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) -#define LPDAC_DER_WM_DMAEN_MASK (0x4U) -#define LPDAC_DER_WM_DMAEN_SHIFT (2U) -/*! WM_DMAEN - FIFO Watermark DMA Enable - * 0b0..Watermark DMA request is disabled. - * 0b1..Watermark DMA request is enabled. - */ -#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) -/*! @} */ - -/*! @name RCR - DAC Reset Control Register */ -/*! @{ */ -#define LPDAC_RCR_SWRST_MASK (0x1U) -#define LPDAC_RCR_SWRST_SHIFT (0U) -/*! SWRST - Software Reset - * 0b0..No effect - * 0b1..Software reset - */ -#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) -#define LPDAC_RCR_FIFORST_MASK (0x2U) -#define LPDAC_RCR_FIFORST_SHIFT (1U) -/*! FIFORST - FIFO Reset - * 0b0..No effect - * 0b1..FIFO reset - */ -#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) -/*! @} */ - -/*! @name TCR - DAC Trigger Control Register */ -/*! @{ */ -#define LPDAC_TCR_SWTRG_MASK (0x1U) -#define LPDAC_TCR_SWTRG_SHIFT (0U) -/*! SWTRG - Software Trigger - * 0b0..The DAC soft trigger is not valid. - * 0b1..The DAC soft trigger is valid. - */ -#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPDAC_Register_Masks */ - - -/* LPDAC - Peripheral instance base addresses */ -/** Peripheral LPDAC0 base address */ -#define LPDAC0_BASE (0x4004C000u) -/** Peripheral LPDAC0 base pointer */ -#define LPDAC0 ((LPDAC_Type *)LPDAC0_BASE) -/** Array initializer of LPDAC peripheral base addresses */ -#define LPDAC_BASE_ADDRS { LPDAC0_BASE } -/** Array initializer of LPDAC peripheral base pointers */ -#define LPDAC_BASE_PTRS { LPDAC0 } -/** Interrupt vectors for the LPDAC peripheral type */ -#define LPDAC_IRQS { LPDAC0_IRQn } - -/*! - * @} - */ /* end of group LPDAC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPI2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer - * @{ - */ - -/** LPI2C - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ - __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ - __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ - __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ - __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ - __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ - __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ - uint8_t RESERVED_1[16]; - __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ - __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ - __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ - uint8_t RESERVED_5[12]; - __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ - uint8_t RESERVED_6[156]; - __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ - __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ - __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ - __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ - uint8_t RESERVED_7[4]; - __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ - __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ - uint8_t RESERVED_8[20]; - __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ - uint8_t RESERVED_9[12]; - __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ - __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ - uint8_t RESERVED_10[8]; - __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ - uint8_t RESERVED_11[12]; - __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ -} LPI2C_Type; - -/* ---------------------------------------------------------------------------- - -- LPI2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Register_Masks LPI2C Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) -#define LPI2C_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000010..Master only, with standard feature set - * 0b0000000000000011..Master and slave, with standard feature set - */ -#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) -#define LPI2C_VERID_MINOR_MASK (0xFF0000U) -#define LPI2C_VERID_MINOR_SHIFT (16U) -#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) -#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) -#define LPI2C_VERID_MAJOR_SHIFT (24U) -#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) -#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) -#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) -#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) -#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) -#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) -/*! @} */ - -/*! @name MCR - Master Control Register */ -/*! @{ */ -#define LPI2C_MCR_MEN_MASK (0x1U) -#define LPI2C_MCR_MEN_SHIFT (0U) -/*! MEN - Master Enable - * 0b0..Master logic is disabled - * 0b1..Master logic is enabled - */ -#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) -#define LPI2C_MCR_RST_MASK (0x2U) -#define LPI2C_MCR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Master logic is not reset - * 0b1..Master logic is reset - */ -#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) -#define LPI2C_MCR_DOZEN_MASK (0x4U) -#define LPI2C_MCR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Master is enabled in Doze mode - * 0b1..Master is disabled in Doze mode - */ -#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) -#define LPI2C_MCR_DBGEN_MASK (0x8U) -#define LPI2C_MCR_DBGEN_SHIFT (3U) -/*! DBGEN - Debug Enable - * 0b0..Master is disabled in debug mode - * 0b1..Master is enabled in debug mode - */ -#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) -#define LPI2C_MCR_RTF_MASK (0x100U) -#define LPI2C_MCR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit FIFO is reset - */ -#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) -#define LPI2C_MCR_RRF_MASK (0x200U) -#define LPI2C_MCR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive FIFO is reset - */ -#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) -/*! @} */ - -/*! @name MSR - Master Status Register */ -/*! @{ */ -#define LPI2C_MSR_TDF_MASK (0x1U) -#define LPI2C_MSR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data is not requested - * 0b1..Transmit data is requested - */ -#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) -#define LPI2C_MSR_RDF_MASK (0x2U) -#define LPI2C_MSR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive Data is not ready - * 0b1..Receive data is ready - */ -#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) -#define LPI2C_MSR_EPF_MASK (0x100U) -#define LPI2C_MSR_EPF_SHIFT (8U) -/*! EPF - End Packet Flag - * 0b0..Master has not generated a STOP or Repeated START condition - * 0b1..Master has generated a STOP or Repeated START condition - */ -#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) -#define LPI2C_MSR_SDF_MASK (0x200U) -#define LPI2C_MSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Master has not generated a STOP condition - * 0b1..Master has generated a STOP condition - */ -#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) -#define LPI2C_MSR_NDF_MASK (0x400U) -#define LPI2C_MSR_NDF_SHIFT (10U) -/*! NDF - NACK Detect Flag - * 0b0..Unexpected NACK was not detected - * 0b1..Unexpected NACK was detected - */ -#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) -#define LPI2C_MSR_ALF_MASK (0x800U) -#define LPI2C_MSR_ALF_SHIFT (11U) -/*! ALF - Arbitration Lost Flag - * 0b0..Master has not lost arbitration - * 0b1..Master has lost arbitration - */ -#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) -#define LPI2C_MSR_FEF_MASK (0x1000U) -#define LPI2C_MSR_FEF_SHIFT (12U) -/*! FEF - FIFO Error Flag - * 0b0..No error - * 0b1..Master sending or receiving data without a START condition - */ -#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) -#define LPI2C_MSR_PLTF_MASK (0x2000U) -#define LPI2C_MSR_PLTF_SHIFT (13U) -/*! PLTF - Pin Low Timeout Flag - * 0b0..Pin low timeout has not occurred or is disabled - * 0b1..Pin low timeout has occurred - */ -#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) -#define LPI2C_MSR_DMF_MASK (0x4000U) -#define LPI2C_MSR_DMF_SHIFT (14U) -/*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data - */ -#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) -#define LPI2C_MSR_MBF_MASK (0x1000000U) -#define LPI2C_MSR_MBF_SHIFT (24U) -/*! MBF - Master Busy Flag - * 0b0..I2C Master is idle - * 0b1..I2C Master is busy - */ -#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) -#define LPI2C_MSR_BBF_MASK (0x2000000U) -#define LPI2C_MSR_BBF_SHIFT (25U) -/*! BBF - Bus Busy Flag - * 0b0..I2C Bus is idle - * 0b1..I2C Bus is busy - */ -#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) -/*! @} */ - -/*! @name MIER - Master Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_MIER_TDIE_MASK (0x1U) -#define LPI2C_MIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) -#define LPI2C_MIER_RDIE_MASK (0x2U) -#define LPI2C_MIER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) -#define LPI2C_MIER_EPIE_MASK (0x100U) -#define LPI2C_MIER_EPIE_SHIFT (8U) -/*! EPIE - End Packet Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) -#define LPI2C_MIER_SDIE_MASK (0x200U) -#define LPI2C_MIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) -#define LPI2C_MIER_NDIE_MASK (0x400U) -#define LPI2C_MIER_NDIE_SHIFT (10U) -/*! NDIE - NACK Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) -#define LPI2C_MIER_ALIE_MASK (0x800U) -#define LPI2C_MIER_ALIE_SHIFT (11U) -/*! ALIE - Arbitration Lost Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) -#define LPI2C_MIER_FEIE_MASK (0x1000U) -#define LPI2C_MIER_FEIE_SHIFT (12U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled - */ -#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) -#define LPI2C_MIER_PLTIE_MASK (0x2000U) -#define LPI2C_MIER_PLTIE_SHIFT (13U) -/*! PLTIE - Pin Low Timeout Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) -#define LPI2C_MIER_DMIE_MASK (0x4000U) -#define LPI2C_MIER_DMIE_SHIFT (14U) -/*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) -/*! @} */ - -/*! @name MDER - Master DMA Enable Register */ -/*! @{ */ -#define LPI2C_MDER_TDDE_MASK (0x1U) -#define LPI2C_MDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) -#define LPI2C_MDER_RDDE_MASK (0x2U) -#define LPI2C_MDER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) -/*! @} */ - -/*! @name MCFGR0 - Master Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCFGR0_HREN_MASK (0x1U) -#define LPI2C_MCFGR0_HREN_SHIFT (0U) -/*! HREN - Host Request Enable - * 0b0..Host request input is disabled - * 0b1..Host request input is enabled - */ -#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) -#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) -#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host Request Polarity - * 0b0..Active low - * 0b1..Active high - */ -#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) -#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) -#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host Request Select - * 0b0..Host request input is pin HREQ - * 0b1..Host request input is input trigger - */ -#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) -#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) -#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO Enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled - */ -#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) -#define LPI2C_MCFGR0_RDMO_MASK (0x200U) -#define LPI2C_MCFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive Data Match Only - * 0b0..Received data is stored in the receive FIFO - * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set - */ -#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) -/*! @} */ - -/*! @name MCFGR1 - Master Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) -#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) -/*! PRESCALE - Prescaler - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) -#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) -#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) -/*! AUTOSTOP - Automatic STOP Generation - * 0b0..No effect - * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy - */ -#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) -#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) -#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) -/*! IGNACK - IGNACK - * 0b0..LPI2C Master will receive ACK and NACK normally - * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK - */ -#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) -#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) -#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) -/*! TIMECFG - Timeout Configuration - * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout - * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout - */ -#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) -#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) -#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) -/*! MATCFG - Match Configuration - * 0b000..Match is disabled - * 0b001..Reserved - * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) - * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) - * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) - * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) - * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) - * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) - */ -#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) -#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) -#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) -/*! PINCFG - Pin Configuration - * 0b000..2-pin open drain mode - * 0b001..2-pin output only mode (ultra-fast mode) - * 0b010..2-pin push-pull mode - * 0b011..4-pin push-pull mode - * 0b100..2-pin open drain mode with separate LPI2C slave - * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave - * 0b110..2-pin push-pull mode with separate LPI2C slave - * 0b111..4-pin push-pull mode (inverted outputs) - */ -#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) -/*! @} */ - -/*! @name MCFGR2 - Master Configuration Register 2 */ -/*! @{ */ -#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) -#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) -#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) -#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) -#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name MCFGR3 - Master Configuration Register 3 */ -/*! @{ */ -#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) -#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) -#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) -/*! @} */ - -/*! @name MDMR - Master Data Match Register */ -/*! @{ */ -#define LPI2C_MDMR_MATCH0_MASK (0xFFU) -#define LPI2C_MDMR_MATCH0_SHIFT (0U) -#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) -#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) -#define LPI2C_MDMR_MATCH1_SHIFT (16U) -#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) -/*! @} */ - -/*! @name MCCR0 - Master Clock Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR0_CLKLO_SHIFT (0U) -#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) -#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR0_CLKHI_SHIFT (8U) -#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) -#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) -#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR0_DATAVD_SHIFT (24U) -#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) -/*! @} */ - -/*! @name MCCR1 - Master Clock Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR1_CLKLO_SHIFT (0U) -#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) -#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR1_CLKHI_SHIFT (8U) -#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) -#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) -#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR1_DATAVD_SHIFT (24U) -#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) -/*! @} */ - -/*! @name MFCR - Master FIFO Control Register */ -/*! @{ */ -#define LPI2C_MFCR_TXWATER_MASK (0x3U) -#define LPI2C_MFCR_TXWATER_SHIFT (0U) -#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) -#define LPI2C_MFCR_RXWATER_MASK (0x30000U) -#define LPI2C_MFCR_RXWATER_SHIFT (16U) -#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) -/*! @} */ - -/*! @name MFSR - Master FIFO Status Register */ -/*! @{ */ -#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) -#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) -#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) -#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) -#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) -#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name MTDR - Master Transmit Data Register */ -/*! @{ */ -#define LPI2C_MTDR_DATA_MASK (0xFFU) -#define LPI2C_MTDR_DATA_SHIFT (0U) -#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) -#define LPI2C_MTDR_CMD_MASK (0x700U) -#define LPI2C_MTDR_CMD_SHIFT (8U) -/*! CMD - Command Data - * 0b000..Transmit DATA[7:0] - * 0b001..Receive (DATA[7:0] + 1) bytes - * 0b010..Generate STOP condition - * 0b011..Receive and discard (DATA[7:0] + 1) bytes - * 0b100..Generate (repeated) START and transmit address in DATA[7:0] - * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. - * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode - * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. - */ -#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) -/*! @} */ - -/*! @name MRDR - Master Receive Data Register */ -/*! @{ */ -#define LPI2C_MRDR_DATA_MASK (0xFFU) -#define LPI2C_MRDR_DATA_SHIFT (0U) -#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) -#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty - * 0b0..Receive FIFO is not empty - * 0b1..Receive FIFO is empty - */ -#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) -/*! @} */ - -/*! @name SCR - Slave Control Register */ -/*! @{ */ -#define LPI2C_SCR_SEN_MASK (0x1U) -#define LPI2C_SCR_SEN_SHIFT (0U) -/*! SEN - Slave Enable - * 0b0..I2C Slave mode is disabled - * 0b1..I2C Slave mode is enabled - */ -#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) -#define LPI2C_SCR_RST_MASK (0x2U) -#define LPI2C_SCR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Slave mode logic is not reset - * 0b1..Slave mode logic is reset - */ -#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) -#define LPI2C_SCR_FILTEN_MASK (0x10U) -#define LPI2C_SCR_FILTEN_SHIFT (4U) -/*! FILTEN - Filter Enable - * 0b0..Disable digital filter and output delay counter for slave mode - * 0b1..Enable digital filter and output delay counter for slave mode - */ -#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) -#define LPI2C_SCR_FILTDZ_MASK (0x20U) -#define LPI2C_SCR_FILTDZ_SHIFT (5U) -/*! FILTDZ - Filter Doze Enable - * 0b0..Filter remains enabled in Doze mode - * 0b1..Filter is disabled in Doze mode - */ -#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) -#define LPI2C_SCR_RTF_MASK (0x100U) -#define LPI2C_SCR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit Data Register is now empty - */ -#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) -#define LPI2C_SCR_RRF_MASK (0x200U) -#define LPI2C_SCR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive Data Register is now empty - */ -#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) -/*! @} */ - -/*! @name SSR - Slave Status Register */ -/*! @{ */ -#define LPI2C_SSR_TDF_MASK (0x1U) -#define LPI2C_SSR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data not requested - * 0b1..Transmit data is requested - */ -#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) -#define LPI2C_SSR_RDF_MASK (0x2U) -#define LPI2C_SSR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive data is not ready - * 0b1..Receive data is ready - */ -#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) -#define LPI2C_SSR_AVF_MASK (0x4U) -#define LPI2C_SSR_AVF_SHIFT (2U) -/*! AVF - Address Valid Flag - * 0b0..Address Status Register is not valid - * 0b1..Address Status Register is valid - */ -#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) -#define LPI2C_SSR_TAF_MASK (0x8U) -#define LPI2C_SSR_TAF_SHIFT (3U) -/*! TAF - Transmit ACK Flag - * 0b0..Transmit ACK/NACK is not required - * 0b1..Transmit ACK/NACK is required - */ -#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) -#define LPI2C_SSR_RSF_MASK (0x100U) -#define LPI2C_SSR_RSF_SHIFT (8U) -/*! RSF - Repeated Start Flag - * 0b0..Slave has not detected a Repeated START condition - * 0b1..Slave has detected a Repeated START condition - */ -#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) -#define LPI2C_SSR_SDF_MASK (0x200U) -#define LPI2C_SSR_SDF_SHIFT (9U) -/*! SDF - STOP Detect Flag - * 0b0..Slave has not detected a STOP condition - * 0b1..Slave has detected a STOP condition - */ -#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) -#define LPI2C_SSR_BEF_MASK (0x400U) -#define LPI2C_SSR_BEF_SHIFT (10U) -/*! BEF - Bit Error Flag - * 0b0..Slave has not detected a bit error - * 0b1..Slave has detected a bit error - */ -#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) -#define LPI2C_SSR_FEF_MASK (0x800U) -#define LPI2C_SSR_FEF_SHIFT (11U) -/*! FEF - FIFO Error Flag - * 0b0..FIFO underflow or overflow was not detected - * 0b1..FIFO underflow or overflow was detected - */ -#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) -#define LPI2C_SSR_AM0F_MASK (0x1000U) -#define LPI2C_SSR_AM0F_SHIFT (12U) -/*! AM0F - Address Match 0 Flag - * 0b0..Have not received an ADDR0 matching address - * 0b1..Have received an ADDR0 matching address - */ -#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) -#define LPI2C_SSR_AM1F_MASK (0x2000U) -#define LPI2C_SSR_AM1F_SHIFT (13U) -/*! AM1F - Address Match 1 Flag - * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address - * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address - */ -#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) -#define LPI2C_SSR_GCF_MASK (0x4000U) -#define LPI2C_SSR_GCF_SHIFT (14U) -/*! GCF - General Call Flag - * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled - * 0b1..Slave has detected the General Call Address - */ -#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) -#define LPI2C_SSR_SARF_MASK (0x8000U) -#define LPI2C_SSR_SARF_SHIFT (15U) -/*! SARF - SMBus Alert Response Flag - * 0b0..SMBus Alert Response is disabled or not detected - * 0b1..SMBus Alert Response is enabled and detected - */ -#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) -#define LPI2C_SSR_SBF_MASK (0x1000000U) -#define LPI2C_SSR_SBF_SHIFT (24U) -/*! SBF - Slave Busy Flag - * 0b0..I2C Slave is idle - * 0b1..I2C Slave is busy - */ -#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) -#define LPI2C_SSR_BBF_MASK (0x2000000U) -#define LPI2C_SSR_BBF_SHIFT (25U) -/*! BBF - Bus Busy Flag - * 0b0..I2C Bus is idle - * 0b1..I2C Bus is busy - */ -#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) -/*! @} */ - -/*! @name SIER - Slave Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_SIER_TDIE_MASK (0x1U) -#define LPI2C_SIER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) -#define LPI2C_SIER_RDIE_MASK (0x2U) -#define LPI2C_SIER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) -#define LPI2C_SIER_AVIE_MASK (0x4U) -#define LPI2C_SIER_AVIE_SHIFT (2U) -/*! AVIE - Address Valid Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) -#define LPI2C_SIER_TAIE_MASK (0x8U) -#define LPI2C_SIER_TAIE_SHIFT (3U) -/*! TAIE - Transmit ACK Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) -#define LPI2C_SIER_RSIE_MASK (0x100U) -#define LPI2C_SIER_RSIE_SHIFT (8U) -/*! RSIE - Repeated Start Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) -#define LPI2C_SIER_SDIE_MASK (0x200U) -#define LPI2C_SIER_SDIE_SHIFT (9U) -/*! SDIE - STOP Detect Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) -#define LPI2C_SIER_BEIE_MASK (0x400U) -#define LPI2C_SIER_BEIE_SHIFT (10U) -/*! BEIE - Bit Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) -#define LPI2C_SIER_FEIE_MASK (0x800U) -#define LPI2C_SIER_FEIE_SHIFT (11U) -/*! FEIE - FIFO Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) -#define LPI2C_SIER_AM0IE_MASK (0x1000U) -#define LPI2C_SIER_AM0IE_SHIFT (12U) -/*! AM0IE - Address Match 0 Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled - */ -#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) -#define LPI2C_SIER_AM1F_MASK (0x2000U) -#define LPI2C_SIER_AM1F_SHIFT (13U) -/*! AM1F - Address Match 1 Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) -#define LPI2C_SIER_GCIE_MASK (0x4000U) -#define LPI2C_SIER_GCIE_SHIFT (14U) -/*! GCIE - General Call Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) -#define LPI2C_SIER_SARIE_MASK (0x8000U) -#define LPI2C_SIER_SARIE_SHIFT (15U) -/*! SARIE - SMBus Alert Response Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) -/*! @} */ - -/*! @name SDER - Slave DMA Enable Register */ -/*! @{ */ -#define LPI2C_SDER_TDDE_MASK (0x1U) -#define LPI2C_SDER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) -#define LPI2C_SDER_RDDE_MASK (0x2U) -#define LPI2C_SDER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) -#define LPI2C_SDER_AVDE_MASK (0x4U) -#define LPI2C_SDER_AVDE_SHIFT (2U) -/*! AVDE - Address Valid DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) -/*! @} */ - -/*! @name SCFGR1 - Slave Configuration Register 1 */ -/*! @{ */ -#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) -#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) -/*! ADRSTALL - Address SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) -#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) -#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) -/*! RXSTALL - RX SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) -#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) -#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) -/*! TXDSTALL - TX Data SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) -#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) -#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) -/*! ACKSTALL - ACK SCL Stall - * 0b0..Clock stretching is disabled - * 0b1..Clock stretching is enabled - */ -#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) -#define LPI2C_SCFGR1_GCEN_MASK (0x100U) -#define LPI2C_SCFGR1_GCEN_SHIFT (8U) -/*! GCEN - General Call Enable - * 0b0..General Call address is disabled - * 0b1..General Call address is enabled - */ -#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) -#define LPI2C_SCFGR1_SAEN_MASK (0x200U) -#define LPI2C_SCFGR1_SAEN_SHIFT (9U) -/*! SAEN - SMBus Alert Enable - * 0b0..Disables match on SMBus Alert - * 0b1..Enables match on SMBus Alert - */ -#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) -#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) -#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) -/*! TXCFG - Transmit Flag Configuration - * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty - * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty - */ -#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) -#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) -#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) -/*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). - */ -#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) -#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) -#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) -/*! IGNACK - Ignore NACK - * 0b0..Slave will end transfer when NACK is detected - * 0b1..Slave will not end transfer when NACK detected - */ -#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) -#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) -#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) -/*! HSMEN - High Speed Mode Enable - * 0b0..Disables detection of HS-mode master code - * 0b1..Enables detection of HS-mode master code - */ -#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) -#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) -#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) -/*! ADDRCFG - Address Configuration - * 0b000..Address match 0 (7-bit) - * 0b001..Address match 0 (10-bit) - * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) - * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) - * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) - * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) - * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) - * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) - */ -#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) -/*! @} */ - -/*! @name SCFGR2 - Slave Configuration Register 2 */ -/*! @{ */ -#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) -#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) -#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) -#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) -#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) -#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) -#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) -#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name SAMR - Slave Address Match Register */ -/*! @{ */ -#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) -#define LPI2C_SAMR_ADDR0_SHIFT (1U) -#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) -#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) -#define LPI2C_SAMR_ADDR1_SHIFT (17U) -#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) -/*! @} */ - -/*! @name SASR - Slave Address Status Register */ -/*! @{ */ -#define LPI2C_SASR_RADDR_MASK (0x7FFU) -#define LPI2C_SASR_RADDR_SHIFT (0U) -#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) -#define LPI2C_SASR_ANV_MASK (0x4000U) -#define LPI2C_SASR_ANV_SHIFT (14U) -/*! ANV - Address Not Valid - * 0b0..Received Address (RADDR) is valid - * 0b1..Received Address (RADDR) is not valid - */ -#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) -/*! @} */ - -/*! @name STAR - Slave Transmit ACK Register */ -/*! @{ */ -#define LPI2C_STAR_TXNACK_MASK (0x1U) -#define LPI2C_STAR_TXNACK_SHIFT (0U) -/*! TXNACK - Transmit NACK - * 0b0..Write a Transmit ACK for each received word - * 0b1..Write a Transmit NACK for each received word - */ -#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) -/*! @} */ - -/*! @name STDR - Slave Transmit Data Register */ -/*! @{ */ -#define LPI2C_STDR_DATA_MASK (0xFFU) -#define LPI2C_STDR_DATA_SHIFT (0U) -#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) -/*! @} */ - -/*! @name SRDR - Slave Receive Data Register */ -/*! @{ */ -#define LPI2C_SRDR_DATA_MASK (0xFFU) -#define LPI2C_SRDR_DATA_SHIFT (0U) -#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) -#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -/*! RXEMPTY - RX Empty - * 0b0..The Receive Data Register is not empty - * 0b1..The Receive Data Register is empty - */ -#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) -#define LPI2C_SRDR_SOF_MASK (0x8000U) -#define LPI2C_SRDR_SOF_SHIFT (15U) -/*! SOF - Start Of Frame - * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition - * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition - */ -#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPI2C_Register_Masks */ - - -/* LPI2C - Peripheral instance base addresses */ -/** Peripheral LPI2C0 base address */ -#define LPI2C0_BASE (0x4003A000u) -/** Peripheral LPI2C0 base pointer */ -#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) -/** Peripheral LPI2C1 base address */ -#define LPI2C1_BASE (0x4003B000u) -/** Peripheral LPI2C1 base pointer */ -#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) -/** Peripheral LPI2C2 base address */ -#define LPI2C2_BASE (0x4003C000u) -/** Peripheral LPI2C2 base pointer */ -#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) -/** Peripheral LPI2C3 base address */ -#define LPI2C3_BASE (0x4102E000u) -/** Peripheral LPI2C3 base pointer */ -#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) -/** Array initializer of LPI2C peripheral base addresses */ -#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } -/** Array initializer of LPI2C peripheral base pointers */ -#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } -/** Interrupt vectors for the LPI2C peripheral type */ -#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } - -/*! - * @} - */ /* end of group LPI2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer - * @{ - */ - -/** LPIT - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ - __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ - __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ - __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ - __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - struct { /* offset: 0x20, array step: 0x10 */ - __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[4]; -} LPIT_Type; - -/* ---------------------------------------------------------------------------- - -- LPIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPIT_Register_Masks LPIT Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPIT_VERID_FEATURE_MASK (0xFFFFU) -#define LPIT_VERID_FEATURE_SHIFT (0U) -#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) -#define LPIT_VERID_MINOR_MASK (0xFF0000U) -#define LPIT_VERID_MINOR_SHIFT (16U) -#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) -#define LPIT_VERID_MAJOR_MASK (0xFF000000U) -#define LPIT_VERID_MAJOR_SHIFT (24U) -#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPIT_PARAM_CHANNEL_MASK (0xFFU) -#define LPIT_PARAM_CHANNEL_SHIFT (0U) -#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) -#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) -#define LPIT_PARAM_EXT_TRIG_SHIFT (8U) -#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) -/*! @} */ - -/*! @name MCR - Module Control Register */ -/*! @{ */ -#define LPIT_MCR_M_CEN_MASK (0x1U) -#define LPIT_MCR_M_CEN_SHIFT (0U) -/*! M_CEN - Module Clock Enable - * 0b0..Disable peripheral clock to timers - * 0b1..Enable peripheral clock to timers - */ -#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) -#define LPIT_MCR_SW_RST_MASK (0x2U) -#define LPIT_MCR_SW_RST_SHIFT (1U) -/*! SW_RST - Software Reset Bit - * 0b0..Timer channels and registers are not reset - * 0b1..Reset timer channels and registers - */ -#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) -#define LPIT_MCR_DOZE_EN_MASK (0x4U) -#define LPIT_MCR_DOZE_EN_SHIFT (2U) -/*! DOZE_EN - DOZE Mode Enable Bit - * 0b0..Stop timer channels in DOZE mode - * 0b1..Allow timer channels to continue to run in DOZE mode - */ -#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) -#define LPIT_MCR_DBG_EN_MASK (0x8U) -#define LPIT_MCR_DBG_EN_SHIFT (3U) -/*! DBG_EN - Debug Enable Bit - * 0b0..Stop timer channels in Debug mode - * 0b1..Allow timer channels to continue to run in Debug mode - */ -#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) -/*! @} */ - -/*! @name MSR - Module Status Register */ -/*! @{ */ -#define LPIT_MSR_TIF0_MASK (0x1U) -#define LPIT_MSR_TIF0_SHIFT (0U) -/*! TIF0 - Channel 0 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) -#define LPIT_MSR_TIF1_MASK (0x2U) -#define LPIT_MSR_TIF1_SHIFT (1U) -/*! TIF1 - Channel 1 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) -#define LPIT_MSR_TIF2_MASK (0x4U) -#define LPIT_MSR_TIF2_SHIFT (2U) -/*! TIF2 - Channel 2 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) -#define LPIT_MSR_TIF3_MASK (0x8U) -#define LPIT_MSR_TIF3_SHIFT (3U) -/*! TIF3 - Channel 3 Timer Interrupt Flag - * 0b0..Timer has not timed out - * 0b1..Timeout has occurred (timer has timed out) - */ -#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) -/*! @} */ - -/*! @name MIER - Module Interrupt Enable Register */ -/*! @{ */ -#define LPIT_MIER_TIE0_MASK (0x1U) -#define LPIT_MIER_TIE0_SHIFT (0U) -/*! TIE0 - Channel 0 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) -#define LPIT_MIER_TIE1_MASK (0x2U) -#define LPIT_MIER_TIE1_SHIFT (1U) -/*! TIE1 - Channel 1 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) -#define LPIT_MIER_TIE2_MASK (0x4U) -#define LPIT_MIER_TIE2_SHIFT (2U) -/*! TIE2 - Channel 2 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) -#define LPIT_MIER_TIE3_MASK (0x8U) -#define LPIT_MIER_TIE3_SHIFT (3U) -/*! TIE3 - Channel 3 Timer Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) -/*! @} */ - -/*! @name SETTEN - Set Timer Enable Register */ -/*! @{ */ -#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) -#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) -/*! SET_T_EN_0 - Set Timer 0 Enable - * 0b0..No effect - * 0b1..Enables Timer Channel 0 - */ -#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) -#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) -#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) -/*! SET_T_EN_1 - Set Timer 1 Enable - * 0b0..No Effect - * 0b1..Enables Timer Channel 1 - */ -#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) -#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) -#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) -/*! SET_T_EN_2 - Set Timer 2 Enable - * 0b0..No Effect - * 0b1..Enables Timer Channel 2 - */ -#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) -#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) -#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) -/*! SET_T_EN_3 - Set Timer 3 Enable - * 0b0..No effect - * 0b1..Enables Timer Channel 3 - */ -#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) -/*! @} */ - -/*! @name CLRTEN - Clear Timer Enable Register */ -/*! @{ */ -#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) -#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) -/*! CLR_T_EN_0 - Clear Timer 0 Enable - * 0b0..No action - * 0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 - */ -#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) -#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) -#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) -/*! CLR_T_EN_1 - Clear Timer 1 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 - */ -#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) -#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) -#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) -/*! CLR_T_EN_2 - Clear Timer 2 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 - */ -#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) -#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) -#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) -/*! CLR_T_EN_3 - Clear Timer 3 Enable - * 0b0..No Action - * 0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 - */ -#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) -/*! @} */ - -/*! @name TVAL - Timer Value Register */ -/*! @{ */ -#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) -#define LPIT_TVAL_TMR_VAL_SHIFT (0U) -/*! TMR_VAL - Timer Value - * 0b00000000000000000000000000000000..Invalid load value in compare mode - * 0b00000000000000000000000000000001..Invalid load value in compare mode - * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer - */ -#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) -/*! @} */ - -/* The count of LPIT_TVAL */ -#define LPIT_TVAL_COUNT (4U) - -/*! @name CVAL - Current Timer Value */ -/*! @{ */ -#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) -#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) -#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) -/*! @} */ - -/* The count of LPIT_CVAL */ -#define LPIT_CVAL_COUNT (4U) - -/*! @name TCTRL - Timer Control Register */ -/*! @{ */ -#define LPIT_TCTRL_T_EN_MASK (0x1U) -#define LPIT_TCTRL_T_EN_SHIFT (0U) -/*! T_EN - Timer Enable - * 0b0..Timer Channel is disabled - * 0b1..Timer Channel is enabled - */ -#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) -#define LPIT_TCTRL_CHAIN_MASK (0x2U) -#define LPIT_TCTRL_CHAIN_SHIFT (1U) -/*! CHAIN - Chain Channel - * 0b0..Channel Chaining is disabled. The channel timer runs independently. - * 0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout. - */ -#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) -#define LPIT_TCTRL_MODE_MASK (0xCU) -#define LPIT_TCTRL_MODE_SHIFT (2U) -/*! MODE - Timer Operation Mode - * 0b00..32-bit Periodic Counter - * 0b01..Dual 16-bit Periodic Counter - * 0b10..32-bit Trigger Accumulator - * 0b11..32-bit Trigger Input Capture - */ -#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) -#define LPIT_TCTRL_TSOT_MASK (0x10000U) -#define LPIT_TCTRL_TSOT_SHIFT (16U) -/*! TSOT - Timer Start On Trigger - * 0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) - * 0b1..Timer starts to decrement when a rising edge on a selected trigger is detected - */ -#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) -#define LPIT_TCTRL_TSOI_MASK (0x20000U) -#define LPIT_TCTRL_TSOI_SHIFT (17U) -/*! TSOI - Timer Stop On Interrupt - * 0b0..The channel timer does not stop after timeout - * 0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. - */ -#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) -#define LPIT_TCTRL_TROT_MASK (0x40000U) -#define LPIT_TCTRL_TROT_SHIFT (18U) -/*! TROT - Timer Reload On Trigger - * 0b0..Timer will not reload on the selected trigger - * 0b1..Timer will reload on the selected trigger - */ -#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) -#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) -#define LPIT_TCTRL_TRG_SRC_SHIFT (23U) -/*! TRG_SRC - Trigger Source - * 0b0..Selects external triggers - * 0b1..Selects internal triggers - */ -#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) -#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) -#define LPIT_TCTRL_TRG_SEL_SHIFT (24U) -/*! TRG_SEL - Trigger Select - * 0b0000-0b0011..Timer channel 0 - 3 trigger source is selected - * 0b0100-0b1111..Reserved - */ -#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) -/*! @} */ - -/* The count of LPIT_TCTRL */ -#define LPIT_TCTRL_COUNT (4U) - - -/*! - * @} - */ /* end of group LPIT_Register_Masks */ - - -/* LPIT - Peripheral instance base addresses */ -/** Peripheral LPIT0 base address */ -#define LPIT0_BASE (0x40030000u) -/** Peripheral LPIT0 base pointer */ -#define LPIT0 ((LPIT_Type *)LPIT0_BASE) -/** Peripheral LPIT1 base address */ -#define LPIT1_BASE (0x4102A000u) -/** Peripheral LPIT1 base pointer */ -#define LPIT1 ((LPIT_Type *)LPIT1_BASE) -/** Array initializer of LPIT peripheral base addresses */ -#define LPIT_BASE_ADDRS { LPIT0_BASE, LPIT1_BASE } -/** Array initializer of LPIT peripheral base pointers */ -#define LPIT_BASE_PTRS { LPIT0, LPIT1 } -/** Interrupt vectors for the LPIT peripheral type */ -#define LPIT_IRQS { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }, { LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn } } - -/*! - * @} - */ /* end of group LPIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPSPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer - * @{ - */ - -/** LPSPI - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ - __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ - __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ - uint8_t RESERVED_3[20]; - __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ - __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ - __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ - __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ - uint8_t RESERVED_4[8]; - __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ - __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ -} LPSPI_Type; - -/* ---------------------------------------------------------------------------- - -- LPSPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Register_Masks LPSPI Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) -#define LPSPI_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Module Identification Number - * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. - */ -#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) -#define LPSPI_VERID_MINOR_MASK (0xFF0000U) -#define LPSPI_VERID_MINOR_SHIFT (16U) -#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) -#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) -#define LPSPI_VERID_MAJOR_SHIFT (24U) -#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) -#define LPSPI_PARAM_TXFIFO_SHIFT (0U) -#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) -#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) -#define LPSPI_PARAM_RXFIFO_SHIFT (8U) -#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define LPSPI_CR_MEN_MASK (0x1U) -#define LPSPI_CR_MEN_SHIFT (0U) -/*! MEN - Module Enable - * 0b0..Module is disabled - * 0b1..Module is enabled - */ -#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) -#define LPSPI_CR_RST_MASK (0x2U) -#define LPSPI_CR_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Master logic is not reset - * 0b1..Master logic is reset - */ -#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) -#define LPSPI_CR_DOZEN_MASK (0x4U) -#define LPSPI_CR_DOZEN_SHIFT (2U) -/*! DOZEN - Doze mode enable - * 0b0..Module is enabled in Doze mode - * 0b1..Module is disabled in Doze mode - */ -#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) -#define LPSPI_CR_DBGEN_MASK (0x8U) -#define LPSPI_CR_DBGEN_SHIFT (3U) -/*! DBGEN - Debug Enable - * 0b0..Module is disabled in debug mode - * 0b1..Module is enabled in debug mode - */ -#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) -#define LPSPI_CR_RTF_MASK (0x100U) -#define LPSPI_CR_RTF_SHIFT (8U) -/*! RTF - Reset Transmit FIFO - * 0b0..No effect - * 0b1..Transmit FIFO is reset - */ -#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) -#define LPSPI_CR_RRF_MASK (0x200U) -#define LPSPI_CR_RRF_SHIFT (9U) -/*! RRF - Reset Receive FIFO - * 0b0..No effect - * 0b1..Receive FIFO is reset - */ -#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ -#define LPSPI_SR_TDF_MASK (0x1U) -#define LPSPI_SR_TDF_SHIFT (0U) -/*! TDF - Transmit Data Flag - * 0b0..Transmit data not requested - * 0b1..Transmit data is requested - */ -#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) -#define LPSPI_SR_RDF_MASK (0x2U) -#define LPSPI_SR_RDF_SHIFT (1U) -/*! RDF - Receive Data Flag - * 0b0..Receive Data is not ready - * 0b1..Receive data is ready - */ -#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) -#define LPSPI_SR_WCF_MASK (0x100U) -#define LPSPI_SR_WCF_SHIFT (8U) -/*! WCF - Word Complete Flag - * 0b0..Transfer of a received word has not yet completed - * 0b1..Transfer of a received word has completed - */ -#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) -#define LPSPI_SR_FCF_MASK (0x200U) -#define LPSPI_SR_FCF_SHIFT (9U) -/*! FCF - Frame Complete Flag - * 0b0..Frame transfer has not completed - * 0b1..Frame transfer has completed - */ -#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) -#define LPSPI_SR_TCF_MASK (0x400U) -#define LPSPI_SR_TCF_SHIFT (10U) -/*! TCF - Transfer Complete Flag - * 0b0..All transfers have not completed - * 0b1..All transfers have completed - */ -#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) -#define LPSPI_SR_TEF_MASK (0x800U) -#define LPSPI_SR_TEF_SHIFT (11U) -/*! TEF - Transmit Error Flag - * 0b0..Transmit FIFO underrun has not occurred - * 0b1..Transmit FIFO underrun has occurred - */ -#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) -#define LPSPI_SR_REF_MASK (0x1000U) -#define LPSPI_SR_REF_SHIFT (12U) -/*! REF - Receive Error Flag - * 0b0..Receive FIFO has not overflowed - * 0b1..Receive FIFO has overflowed - */ -#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) -#define LPSPI_SR_DMF_MASK (0x2000U) -#define LPSPI_SR_DMF_SHIFT (13U) -/*! DMF - Data Match Flag - * 0b0..Have not received matching data - * 0b1..Have received matching data - */ -#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) -#define LPSPI_SR_MBF_MASK (0x1000000U) -#define LPSPI_SR_MBF_SHIFT (24U) -/*! MBF - Module Busy Flag - * 0b0..LPSPI is idle - * 0b1..LPSPI is busy - */ -#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ -#define LPSPI_IER_TDIE_MASK (0x1U) -#define LPSPI_IER_TDIE_SHIFT (0U) -/*! TDIE - Transmit Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) -#define LPSPI_IER_RDIE_MASK (0x2U) -#define LPSPI_IER_RDIE_SHIFT (1U) -/*! RDIE - Receive Data Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) -#define LPSPI_IER_WCIE_MASK (0x100U) -#define LPSPI_IER_WCIE_SHIFT (8U) -/*! WCIE - Word Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) -#define LPSPI_IER_FCIE_MASK (0x200U) -#define LPSPI_IER_FCIE_SHIFT (9U) -/*! FCIE - Frame Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) -#define LPSPI_IER_TCIE_MASK (0x400U) -#define LPSPI_IER_TCIE_SHIFT (10U) -/*! TCIE - Transfer Complete Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) -#define LPSPI_IER_TEIE_MASK (0x800U) -#define LPSPI_IER_TEIE_SHIFT (11U) -/*! TEIE - Transmit Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) -#define LPSPI_IER_REIE_MASK (0x1000U) -#define LPSPI_IER_REIE_SHIFT (12U) -/*! REIE - Receive Error Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) -#define LPSPI_IER_DMIE_MASK (0x2000U) -#define LPSPI_IER_DMIE_SHIFT (13U) -/*! DMIE - Data Match Interrupt Enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) -/*! @} */ - -/*! @name DER - DMA Enable Register */ -/*! @{ */ -#define LPSPI_DER_TDDE_MASK (0x1U) -#define LPSPI_DER_TDDE_SHIFT (0U) -/*! TDDE - Transmit Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) -#define LPSPI_DER_RDDE_MASK (0x2U) -#define LPSPI_DER_RDDE_SHIFT (1U) -/*! RDDE - Receive Data DMA Enable - * 0b0..DMA request is disabled - * 0b1..DMA request is enabled - */ -#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) -/*! @} */ - -/*! @name CFGR0 - Configuration Register 0 */ -/*! @{ */ -#define LPSPI_CFGR0_HREN_MASK (0x1U) -#define LPSPI_CFGR0_HREN_SHIFT (0U) -/*! HREN - Host Request Enable - * 0b0..Host request is disabled - * 0b1..Host request is enabled - */ -#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) -#define LPSPI_CFGR0_HRPOL_MASK (0x2U) -#define LPSPI_CFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host Request Polarity - * 0b0..Active low - * 0b1..Active high - */ -#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) -#define LPSPI_CFGR0_HRSEL_MASK (0x4U) -#define LPSPI_CFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host Request Select - * 0b0..Host request input is the LPSPI_HREQ pin - * 0b1..Host request input is the input trigger - */ -#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) -#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) -#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) -/*! CIRFIFO - Circular FIFO Enable - * 0b0..Circular FIFO is disabled - * 0b1..Circular FIFO is enabled - */ -#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) -#define LPSPI_CFGR0_RDMO_MASK (0x200U) -#define LPSPI_CFGR0_RDMO_SHIFT (9U) -/*! RDMO - Receive Data Match Only - * 0b0..Received data is stored in the receive FIFO as in normal operations - * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set - */ -#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) -/*! @} */ - -/*! @name CFGR1 - Configuration Register 1 */ -/*! @{ */ -#define LPSPI_CFGR1_MASTER_MASK (0x1U) -#define LPSPI_CFGR1_MASTER_SHIFT (0U) -/*! MASTER - Master Mode - * 0b0..Slave mode - * 0b1..Master mode - */ -#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) -#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) -#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) -/*! SAMPLE - Sample Point - * 0b0..Input data is sampled on SCK edge - * 0b1..Input data is sampled on delayed SCK edge - */ -#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) -#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) -#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) -/*! AUTOPCS - Automatic PCS - * 0b0..Automatic PCS generation is disabled - * 0b1..Automatic PCS generation is enabled - */ -#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) -#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) -#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) -/*! NOSTALL - No Stall - * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full - * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur - */ -#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) -#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) -#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) -/*! PCSPOL - Peripheral Chip Select Polarity - * 0b0000..The Peripheral Chip Select pin PCSx is active low - * 0b0001..The Peripheral Chip Select pin PCSx is active high - */ -#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) -#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) -#define LPSPI_CFGR1_MATCFG_SHIFT (16U) -/*! MATCFG - Match Configuration - * 0b000..Match is disabled - * 0b001..Reserved - * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) - * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) - * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] - * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] - * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] - * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] - */ -#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) -#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) -#define LPSPI_CFGR1_PINCFG_SHIFT (24U) -/*! PINCFG - Pin Configuration - * 0b00..SIN is used for input data and SOUT is used for output data - * 0b01..SIN is used for both input and output data - * 0b10..SOUT is used for both input and output data - * 0b11..SOUT is used for input data and SIN is used for output data - */ -#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) -#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) -#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) -/*! OUTCFG - Output Config - * 0b0..Output data retains last value when chip select is negated - * 0b1..Output data is tristated when chip select is negated - */ -#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) -#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) -#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) -/*! PCSCFG - Peripheral Chip Select Configuration - * 0b0..PCS[3:2] are enabled - * 0b1..PCS[3:2] are disabled - */ -#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) -/*! @} */ - -/*! @name DMR0 - Data Match Register 0 */ -/*! @{ */ -#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) -#define LPSPI_DMR0_MATCH0_SHIFT (0U) -#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) -/*! @} */ - -/*! @name DMR1 - Data Match Register 1 */ -/*! @{ */ -#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) -#define LPSPI_DMR1_MATCH1_SHIFT (0U) -#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) -/*! @} */ - -/*! @name CCR - Clock Configuration Register */ -/*! @{ */ -#define LPSPI_CCR_SCKDIV_MASK (0xFFU) -#define LPSPI_CCR_SCKDIV_SHIFT (0U) -#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) -#define LPSPI_CCR_DBT_MASK (0xFF00U) -#define LPSPI_CCR_DBT_SHIFT (8U) -#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) -#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) -#define LPSPI_CCR_PCSSCK_SHIFT (16U) -#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) -#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) -#define LPSPI_CCR_SCKPCS_SHIFT (24U) -#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) -/*! @} */ - -/*! @name FCR - FIFO Control Register */ -/*! @{ */ -#define LPSPI_FCR_TXWATER_MASK (0x3U) -#define LPSPI_FCR_TXWATER_SHIFT (0U) -#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) -#define LPSPI_FCR_RXWATER_MASK (0x30000U) -#define LPSPI_FCR_RXWATER_SHIFT (16U) -#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ -#define LPSPI_FSR_TXCOUNT_MASK (0x7U) -#define LPSPI_FSR_TXCOUNT_SHIFT (0U) -#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) -#define LPSPI_FSR_RXCOUNT_MASK (0x70000U) -#define LPSPI_FSR_RXCOUNT_SHIFT (16U) -#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name TCR - Transmit Command Register */ -/*! @{ */ -#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) -#define LPSPI_TCR_FRAMESZ_SHIFT (0U) -#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) -#define LPSPI_TCR_WIDTH_MASK (0x30000U) -#define LPSPI_TCR_WIDTH_SHIFT (16U) -/*! WIDTH - Transfer Width - * 0b00..1 bit transfer - * 0b01..2 bit transfer - * 0b10..4 bit transfer - * 0b11..Reserved - */ -#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) -#define LPSPI_TCR_TXMSK_MASK (0x40000U) -#define LPSPI_TCR_TXMSK_SHIFT (18U) -/*! TXMSK - Transmit Data Mask - * 0b0..Normal transfer - * 0b1..Mask transmit data - */ -#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) -#define LPSPI_TCR_RXMSK_MASK (0x80000U) -#define LPSPI_TCR_RXMSK_SHIFT (19U) -/*! RXMSK - Receive Data Mask - * 0b0..Normal transfer - * 0b1..Receive data is masked - */ -#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) -#define LPSPI_TCR_CONTC_MASK (0x100000U) -#define LPSPI_TCR_CONTC_SHIFT (20U) -/*! CONTC - Continuing Command - * 0b0..Command word for start of new transfer - * 0b1..Command word for continuing transfer - */ -#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) -#define LPSPI_TCR_CONT_MASK (0x200000U) -#define LPSPI_TCR_CONT_SHIFT (21U) -/*! CONT - Continuous Transfer - * 0b0..Continuous transfer is disabled - * 0b1..Continuous transfer is enabled - */ -#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) -#define LPSPI_TCR_BYSW_MASK (0x400000U) -#define LPSPI_TCR_BYSW_SHIFT (22U) -/*! BYSW - Byte Swap - * 0b0..Byte swap is disabled - * 0b1..Byte swap is enabled - */ -#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) -#define LPSPI_TCR_LSBF_MASK (0x800000U) -#define LPSPI_TCR_LSBF_SHIFT (23U) -/*! LSBF - LSB First - * 0b0..Data is transferred MSB first - * 0b1..Data is transferred LSB first - */ -#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) -#define LPSPI_TCR_PCS_MASK (0x3000000U) -#define LPSPI_TCR_PCS_SHIFT (24U) -/*! PCS - Peripheral Chip Select - * 0b00..Transfer using LPSPI_PCS[0] - * 0b01..Transfer using LPSPI_PCS[1] - * 0b10..Transfer using LPSPI_PCS[2] - * 0b11..Transfer using LPSPI_PCS[3] - */ -#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) -#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) -#define LPSPI_TCR_PRESCALE_SHIFT (27U) -/*! PRESCALE - Prescaler Value - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) -#define LPSPI_TCR_CPHA_MASK (0x40000000U) -#define LPSPI_TCR_CPHA_SHIFT (30U) -/*! CPHA - Clock Phase - * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK - * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK - */ -#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) -#define LPSPI_TCR_CPOL_MASK (0x80000000U) -#define LPSPI_TCR_CPOL_SHIFT (31U) -/*! CPOL - Clock Polarity - * 0b0..The inactive state value of SCK is low - * 0b1..The inactive state value of SCK is high - */ -#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) -/*! @} */ - -/*! @name TDR - Transmit Data Register */ -/*! @{ */ -#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_TDR_DATA_SHIFT (0U) -#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) -/*! @} */ - -/*! @name RSR - Receive Status Register */ -/*! @{ */ -#define LPSPI_RSR_SOF_MASK (0x1U) -#define LPSPI_RSR_SOF_SHIFT (0U) -/*! SOF - Start Of Frame - * 0b0..Subsequent data word received after LPSPI_PCS assertion - * 0b1..First data word received after LPSPI_PCS assertion - */ -#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) -#define LPSPI_RSR_RXEMPTY_MASK (0x2U) -#define LPSPI_RSR_RXEMPTY_SHIFT (1U) -/*! RXEMPTY - RX FIFO Empty - * 0b0..RX FIFO is not empty - * 0b1..RX FIFO is empty - */ -#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) -/*! @} */ - -/*! @name RDR - Receive Data Register */ -/*! @{ */ -#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_RDR_DATA_SHIFT (0U) -#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPSPI_Register_Masks */ - - -/* LPSPI - Peripheral instance base addresses */ -/** Peripheral LPSPI0 base address */ -#define LPSPI0_BASE (0x4003F000u) -/** Peripheral LPSPI0 base pointer */ -#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) -/** Peripheral LPSPI1 base address */ -#define LPSPI1_BASE (0x40040000u) -/** Peripheral LPSPI1 base pointer */ -#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) -/** Peripheral LPSPI2 base address */ -#define LPSPI2_BASE (0x40041000u) -/** Peripheral LPSPI2 base pointer */ -#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) -/** Peripheral LPSPI3 base address */ -#define LPSPI3_BASE (0x41035000u) -/** Peripheral LPSPI3 base pointer */ -#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) -/** Array initializer of LPSPI peripheral base addresses */ -#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE } -/** Array initializer of LPSPI peripheral base pointers */ -#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3 } -/** Interrupt vectors for the LPSPI peripheral type */ -#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn } - -/*! - * @} - */ /* end of group LPSPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer - * @{ - */ - -/** LPTMR - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ - __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ - __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ - __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ -} LPTMR_Type; - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/*! @name CSR - Low Power Timer Control Status Register */ -/*! @{ */ -#define LPTMR_CSR_TEN_MASK (0x1U) -#define LPTMR_CSR_TEN_SHIFT (0U) -/*! TEN - Timer Enable - * 0b0..LPTMR is disabled and internal logic is reset. - * 0b1..LPTMR is enabled. - */ -#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) -#define LPTMR_CSR_TMS_MASK (0x2U) -#define LPTMR_CSR_TMS_SHIFT (1U) -/*! TMS - Timer Mode Select - * 0b0..Time Counter mode. - * 0b1..Pulse Counter mode. - */ -#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) -#define LPTMR_CSR_TFC_MASK (0x4U) -#define LPTMR_CSR_TFC_SHIFT (2U) -/*! TFC - Timer Free-Running Counter - * 0b0..CNR is reset whenever TCF is set. - * 0b1..CNR is reset on overflow. - */ -#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) -#define LPTMR_CSR_TPP_MASK (0x8U) -#define LPTMR_CSR_TPP_SHIFT (3U) -/*! TPP - Timer Pin Polarity - * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. - * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. - */ -#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) -#define LPTMR_CSR_TPS_MASK (0x30U) -#define LPTMR_CSR_TPS_SHIFT (4U) -/*! TPS - Timer Pin Select - * 0b00..Pulse counter input 0 is selected. - * 0b01..Pulse counter input 1 is selected. - * 0b10..Pulse counter input 2 is selected. - * 0b11..Pulse counter input 3 is selected. - */ -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) -#define LPTMR_CSR_TIE_MASK (0x40U) -#define LPTMR_CSR_TIE_SHIFT (6U) -/*! TIE - Timer Interrupt Enable - * 0b0..Timer interrupt disabled. - * 0b1..Timer interrupt enabled. - */ -#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) -#define LPTMR_CSR_TCF_MASK (0x80U) -#define LPTMR_CSR_TCF_SHIFT (7U) -/*! TCF - Timer Compare Flag - * 0b0..The value of CNR is not equal to CMR and increments. - * 0b1..The value of CNR is equal to CMR and increments. - */ -#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) -#define LPTMR_CSR_TDRE_MASK (0x100U) -#define LPTMR_CSR_TDRE_SHIFT (8U) -/*! TDRE - Timer DMA Request Enable - * 0b0..Timer DMA Request disabled. - * 0b1..Timer DMA Request enabled. - */ -#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) -/*! @} */ - -/*! @name PSR - Low Power Timer Prescale Register */ -/*! @{ */ -#define LPTMR_PSR_PCS_MASK (0x3U) -#define LPTMR_PSR_PCS_SHIFT (0U) -/*! PCS - Prescaler Clock Select - * 0b00..Prescaler/glitch filter clock 0 selected. - * 0b01..Prescaler/glitch filter clock 1 selected. - * 0b10..Prescaler/glitch filter clock 2 selected. - * 0b11..Prescaler/glitch filter clock 3 selected. - */ -#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) -#define LPTMR_PSR_PBYP_MASK (0x4U) -#define LPTMR_PSR_PBYP_SHIFT (2U) -/*! PBYP - Prescaler Bypass - * 0b0..Prescaler/glitch filter is enabled. - * 0b1..Prescaler/glitch filter is bypassed. - */ -#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) -#define LPTMR_PSR_PRESCALE_MASK (0x78U) -#define LPTMR_PSR_PRESCALE_SHIFT (3U) -/*! PRESCALE - Prescale Value - * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. - * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. - * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. - * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. - * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. - * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. - * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. - * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. - * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. - * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. - * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. - * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. - * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. - * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. - * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. - * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. - */ -#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) -/*! @} */ - -/*! @name CMR - Low Power Timer Compare Register */ -/*! @{ */ -#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) -#define LPTMR_CMR_COMPARE_SHIFT (0U) -#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) -/*! @} */ - -/*! @name CNR - Low Power Timer Counter Register */ -/*! @{ */ -#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) -#define LPTMR_CNR_COUNTER_SHIFT (0U) -#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPTMR_Register_Masks */ - - -/* LPTMR - Peripheral instance base addresses */ -/** Peripheral LPTMR0 base address */ -#define LPTMR0_BASE (0x40032000u) -/** Peripheral LPTMR0 base pointer */ -#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) -/** Peripheral LPTMR1 base address */ -#define LPTMR1_BASE (0x40033000u) -/** Peripheral LPTMR1 base pointer */ -#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) -/** Peripheral LPTMR2 base address */ -#define LPTMR2_BASE (0x4102B000u) -/** Peripheral LPTMR2 base pointer */ -#define LPTMR2 ((LPTMR_Type *)LPTMR2_BASE) -/** Array initializer of LPTMR peripheral base addresses */ -#define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE, LPTMR2_BASE } -/** Array initializer of LPTMR peripheral base pointers */ -#define LPTMR_BASE_PTRS { LPTMR0, LPTMR1, LPTMR2 } -/** Interrupt vectors for the LPTMR peripheral type */ -#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn } - -/*! - * @} - */ /* end of group LPTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer - * @{ - */ - -/** LPUART - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ - __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ - __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ - __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ - __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ - __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ - __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ - __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ - __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ - __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ -} LPUART_Type; - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPUART_VERID_FEATURE_MASK (0xFFFFU) -#define LPUART_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - * 0b0000000000000001..Standard feature set. - * 0b0000000000000011..Standard feature set with MODEM/IrDA support. - */ -#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) -#define LPUART_VERID_MINOR_MASK (0xFF0000U) -#define LPUART_VERID_MINOR_SHIFT (16U) -#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) -#define LPUART_VERID_MAJOR_MASK (0xFF000000U) -#define LPUART_VERID_MAJOR_SHIFT (24U) -#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPUART_PARAM_TXFIFO_MASK (0xFFU) -#define LPUART_PARAM_TXFIFO_SHIFT (0U) -#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) -#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) -#define LPUART_PARAM_RXFIFO_SHIFT (8U) -#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) -/*! @} */ - -/*! @name GLOBAL - LPUART Global Register */ -/*! @{ */ -#define LPUART_GLOBAL_RST_MASK (0x2U) -#define LPUART_GLOBAL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Module is not reset. - * 0b1..Module is reset. - */ -#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) -/*! @} */ - -/*! @name PINCFG - LPUART Pin Configuration Register */ -/*! @{ */ -#define LPUART_PINCFG_TRGSEL_MASK (0x3U) -#define LPUART_PINCFG_TRGSEL_SHIFT (0U) -/*! TRGSEL - Trigger Select - * 0b00..Input trigger is disabled. - * 0b01..Input trigger is used instead of RXD pin input. - * 0b10..Input trigger is used instead of CTS_B pin input. - * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. - */ -#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) -/*! @} */ - -/*! @name BAUD - LPUART Baud Rate Register */ -/*! @{ */ -#define LPUART_BAUD_SBR_MASK (0x1FFFU) -#define LPUART_BAUD_SBR_SHIFT (0U) -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) -#define LPUART_BAUD_SBNS_MASK (0x2000U) -#define LPUART_BAUD_SBNS_SHIFT (13U) -/*! SBNS - Stop Bit Number Select - * 0b0..One stop bit. - * 0b1..Two stop bits. - */ -#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) -#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) -#define LPUART_BAUD_RXEDGIE_SHIFT (14U) -/*! RXEDGIE - RX Input Active Edge Interrupt Enable - * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. - * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. - */ -#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) -#define LPUART_BAUD_LBKDIE_MASK (0x8000U) -#define LPUART_BAUD_LBKDIE_SHIFT (15U) -/*! LBKDIE - LIN Break Detect Interrupt Enable - * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). - * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. - */ -#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) -#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) -#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) -/*! RESYNCDIS - Resynchronization Disable - * 0b0..Resynchronization during received data word is supported - * 0b1..Resynchronization during received data word is disabled - */ -#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) -#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) -#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) -/*! BOTHEDGE - Both Edge Sampling - * 0b0..Receiver samples input data using the rising edge of the baud rate clock. - * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. - */ -#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) -#define LPUART_BAUD_MATCFG_MASK (0xC0000U) -#define LPUART_BAUD_MATCFG_SHIFT (18U) -/*! MATCFG - Match Configuration - * 0b00..Address Match Wakeup - * 0b01..Idle Match Wakeup - * 0b10..Match On and Match Off - * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input - */ -#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) -#define LPUART_BAUD_RIDMAE_MASK (0x100000U) -#define LPUART_BAUD_RIDMAE_SHIFT (20U) -/*! RIDMAE - Receiver Idle DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) -#define LPUART_BAUD_RDMAE_MASK (0x200000U) -#define LPUART_BAUD_RDMAE_SHIFT (21U) -/*! RDMAE - Receiver Full DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) -#define LPUART_BAUD_TDMAE_MASK (0x800000U) -#define LPUART_BAUD_TDMAE_SHIFT (23U) -/*! TDMAE - Transmitter DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) -#define LPUART_BAUD_OSR_MASK (0x1F000000U) -#define LPUART_BAUD_OSR_SHIFT (24U) -/*! OSR - Oversampling Ratio - * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 - * 0b00001..Reserved - * 0b00010..Reserved - * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. - * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. - * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. - * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. - * 0b00111..Oversampling ratio of 8. - * 0b01000..Oversampling ratio of 9. - * 0b01001..Oversampling ratio of 10. - * 0b01010..Oversampling ratio of 11. - * 0b01011..Oversampling ratio of 12. - * 0b01100..Oversampling ratio of 13. - * 0b01101..Oversampling ratio of 14. - * 0b01110..Oversampling ratio of 15. - * 0b01111..Oversampling ratio of 16. - * 0b10000..Oversampling ratio of 17. - * 0b10001..Oversampling ratio of 18. - * 0b10010..Oversampling ratio of 19. - * 0b10011..Oversampling ratio of 20. - * 0b10100..Oversampling ratio of 21. - * 0b10101..Oversampling ratio of 22. - * 0b10110..Oversampling ratio of 23. - * 0b10111..Oversampling ratio of 24. - * 0b11000..Oversampling ratio of 25. - * 0b11001..Oversampling ratio of 26. - * 0b11010..Oversampling ratio of 27. - * 0b11011..Oversampling ratio of 28. - * 0b11100..Oversampling ratio of 29. - * 0b11101..Oversampling ratio of 30. - * 0b11110..Oversampling ratio of 31. - * 0b11111..Oversampling ratio of 32. - */ -#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) -#define LPUART_BAUD_M10_MASK (0x20000000U) -#define LPUART_BAUD_M10_SHIFT (29U) -/*! M10 - 10-bit Mode select - * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. - * 0b1..Receiver and transmitter use 10-bit data characters. - */ -#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) -#define LPUART_BAUD_MAEN2_MASK (0x40000000U) -#define LPUART_BAUD_MAEN2_SHIFT (30U) -/*! MAEN2 - Match Address Mode Enable 2 - * 0b0..Normal operation. - * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. - */ -#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) -#define LPUART_BAUD_MAEN1_MASK (0x80000000U) -#define LPUART_BAUD_MAEN1_SHIFT (31U) -/*! MAEN1 - Match Address Mode Enable 1 - * 0b0..Normal operation. - * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. - */ -#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) -/*! @} */ - -/*! @name STAT - LPUART Status Register */ -/*! @{ */ -#define LPUART_STAT_MA2F_MASK (0x4000U) -#define LPUART_STAT_MA2F_SHIFT (14U) -/*! MA2F - Match 2 Flag - * 0b0..Received data is not equal to MA2 - * 0b1..Received data is equal to MA2 - */ -#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) -#define LPUART_STAT_MA1F_MASK (0x8000U) -#define LPUART_STAT_MA1F_SHIFT (15U) -/*! MA1F - Match 1 Flag - * 0b0..Received data is not equal to MA1 - * 0b1..Received data is equal to MA1 - */ -#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) -#define LPUART_STAT_PF_MASK (0x10000U) -#define LPUART_STAT_PF_SHIFT (16U) -/*! PF - Parity Error Flag - * 0b0..No parity error. - * 0b1..Parity error. - */ -#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) -#define LPUART_STAT_FE_MASK (0x20000U) -#define LPUART_STAT_FE_SHIFT (17U) -/*! FE - Framing Error Flag - * 0b0..No framing error detected. This does not guarantee the framing is correct. - * 0b1..Framing error. - */ -#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) -#define LPUART_STAT_NF_MASK (0x40000U) -#define LPUART_STAT_NF_SHIFT (18U) -/*! NF - Noise Flag - * 0b0..No noise detected. - * 0b1..Noise detected in the received character in LPUART_DATA. - */ -#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) -#define LPUART_STAT_OR_MASK (0x80000U) -#define LPUART_STAT_OR_SHIFT (19U) -/*! OR - Receiver Overrun Flag - * 0b0..No overrun. - * 0b1..Receive overrun (new LPUART data lost). - */ -#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) -#define LPUART_STAT_IDLE_MASK (0x100000U) -#define LPUART_STAT_IDLE_SHIFT (20U) -/*! IDLE - Idle Line Flag - * 0b0..No idle line detected. - * 0b1..Idle line was detected. - */ -#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) -#define LPUART_STAT_RDRF_MASK (0x200000U) -#define LPUART_STAT_RDRF_SHIFT (21U) -/*! RDRF - Receive Data Register Full Flag - * 0b0..Receive data buffer empty. - * 0b1..Receive data buffer full. - */ -#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) -#define LPUART_STAT_TC_MASK (0x400000U) -#define LPUART_STAT_TC_SHIFT (22U) -/*! TC - Transmission Complete Flag - * 0b0..Transmitter active (sending data, a preamble, or a break). - * 0b1..Transmitter idle (transmission activity complete). - */ -#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) -#define LPUART_STAT_TDRE_MASK (0x800000U) -#define LPUART_STAT_TDRE_SHIFT (23U) -/*! TDRE - Transmit Data Register Empty Flag - * 0b0..Transmit data buffer full. - * 0b1..Transmit data buffer empty. - */ -#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) -#define LPUART_STAT_RAF_MASK (0x1000000U) -#define LPUART_STAT_RAF_SHIFT (24U) -/*! RAF - Receiver Active Flag - * 0b0..LPUART receiver idle waiting for a start bit. - * 0b1..LPUART receiver active (RXD input not idle). - */ -#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) -#define LPUART_STAT_LBKDE_MASK (0x2000000U) -#define LPUART_STAT_LBKDE_SHIFT (25U) -/*! LBKDE - LIN Break Detection Enable - * 0b0..LIN break detect is disabled, normal break character can be detected. - * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). - */ -#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) -#define LPUART_STAT_BRK13_MASK (0x4000000U) -#define LPUART_STAT_BRK13_SHIFT (26U) -/*! BRK13 - Break Character Generation Length - * 0b0..Break character is transmitted with length of 9 to 13 bit times. - * 0b1..Break character is transmitted with length of 12 to 15 bit times. - */ -#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) -#define LPUART_STAT_RWUID_MASK (0x8000000U) -#define LPUART_STAT_RWUID_SHIFT (27U) -/*! RWUID - Receive Wake Up Idle Detect - * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. - * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. - */ -#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) -#define LPUART_STAT_RXINV_MASK (0x10000000U) -#define LPUART_STAT_RXINV_SHIFT (28U) -/*! RXINV - Receive Data Inversion - * 0b0..Receive data not inverted. - * 0b1..Receive data inverted. - */ -#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) -#define LPUART_STAT_MSBF_MASK (0x20000000U) -#define LPUART_STAT_MSBF_SHIFT (29U) -/*! MSBF - MSB First - * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. - * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. - */ -#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) -#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) -#define LPUART_STAT_RXEDGIF_SHIFT (30U) -/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag - * 0b0..No active edge on the receive pin has occurred. - * 0b1..An active edge on the receive pin has occurred. - */ -#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) -#define LPUART_STAT_LBKDIF_MASK (0x80000000U) -#define LPUART_STAT_LBKDIF_SHIFT (31U) -/*! LBKDIF - LIN Break Detect Interrupt Flag - * 0b0..No LIN break character has been detected. - * 0b1..LIN break character has been detected. - */ -#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) -/*! @} */ - -/*! @name CTRL - LPUART Control Register */ -/*! @{ */ -#define LPUART_CTRL_PT_MASK (0x1U) -#define LPUART_CTRL_PT_SHIFT (0U) -/*! PT - Parity Type - * 0b0..Even parity. - * 0b1..Odd parity. - */ -#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) -#define LPUART_CTRL_PE_MASK (0x2U) -#define LPUART_CTRL_PE_SHIFT (1U) -/*! PE - Parity Enable - * 0b0..No hardware parity generation or checking. - * 0b1..Parity enabled. - */ -#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) -#define LPUART_CTRL_ILT_MASK (0x4U) -#define LPUART_CTRL_ILT_SHIFT (2U) -/*! ILT - Idle Line Type Select - * 0b0..Idle character bit count starts after start bit. - * 0b1..Idle character bit count starts after stop bit. - */ -#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) -#define LPUART_CTRL_WAKE_MASK (0x8U) -#define LPUART_CTRL_WAKE_SHIFT (3U) -/*! WAKE - Receiver Wakeup Method Select - * 0b0..Configures RWU for idle-line wakeup. - * 0b1..Configures RWU with address-mark wakeup. - */ -#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) -#define LPUART_CTRL_M_MASK (0x10U) -#define LPUART_CTRL_M_SHIFT (4U) -/*! M - 9-Bit or 8-Bit Mode Select - * 0b0..Receiver and transmitter use 8-bit data characters. - * 0b1..Receiver and transmitter use 9-bit data characters. - */ -#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) -#define LPUART_CTRL_RSRC_MASK (0x20U) -#define LPUART_CTRL_RSRC_SHIFT (5U) -/*! RSRC - Receiver Source Select - * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. - * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. - */ -#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) -#define LPUART_CTRL_DOZEEN_MASK (0x40U) -#define LPUART_CTRL_DOZEEN_SHIFT (6U) -/*! DOZEEN - Doze Enable - * 0b0..LPUART is enabled in Doze mode. - * 0b1..LPUART is disabled in Doze mode. - */ -#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) -#define LPUART_CTRL_LOOPS_MASK (0x80U) -#define LPUART_CTRL_LOOPS_SHIFT (7U) -/*! LOOPS - Loop Mode Select - * 0b0..Normal operation - RXD and TXD use separate pins. - * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). - */ -#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) -#define LPUART_CTRL_IDLECFG_MASK (0x700U) -#define LPUART_CTRL_IDLECFG_SHIFT (8U) -/*! IDLECFG - Idle Configuration - * 0b000..1 idle character - * 0b001..2 idle characters - * 0b010..4 idle characters - * 0b011..8 idle characters - * 0b100..16 idle characters - * 0b101..32 idle characters - * 0b110..64 idle characters - * 0b111..128 idle characters - */ -#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) -#define LPUART_CTRL_M7_MASK (0x800U) -#define LPUART_CTRL_M7_SHIFT (11U) -/*! M7 - 7-Bit Mode Select - * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. - * 0b1..Receiver and transmitter use 7-bit data characters. - */ -#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) -#define LPUART_CTRL_MA2IE_MASK (0x4000U) -#define LPUART_CTRL_MA2IE_SHIFT (14U) -/*! MA2IE - Match 2 Interrupt Enable - * 0b0..MA2F interrupt disabled - * 0b1..MA2F interrupt enabled - */ -#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) -#define LPUART_CTRL_MA1IE_MASK (0x8000U) -#define LPUART_CTRL_MA1IE_SHIFT (15U) -/*! MA1IE - Match 1 Interrupt Enable - * 0b0..MA1F interrupt disabled - * 0b1..MA1F interrupt enabled - */ -#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) -#define LPUART_CTRL_SBK_MASK (0x10000U) -#define LPUART_CTRL_SBK_SHIFT (16U) -/*! SBK - Send Break - * 0b0..Normal transmitter operation. - * 0b1..Queue break character(s) to be sent. - */ -#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) -#define LPUART_CTRL_RWU_MASK (0x20000U) -#define LPUART_CTRL_RWU_SHIFT (17U) -/*! RWU - Receiver Wakeup Control - * 0b0..Normal receiver operation. - * 0b1..LPUART receiver in standby waiting for wakeup condition. - */ -#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) -#define LPUART_CTRL_RE_MASK (0x40000U) -#define LPUART_CTRL_RE_SHIFT (18U) -/*! RE - Receiver Enable - * 0b0..Receiver disabled. - * 0b1..Receiver enabled. - */ -#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) -#define LPUART_CTRL_TE_MASK (0x80000U) -#define LPUART_CTRL_TE_SHIFT (19U) -/*! TE - Transmitter Enable - * 0b0..Transmitter disabled. - * 0b1..Transmitter enabled. - */ -#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) -#define LPUART_CTRL_ILIE_MASK (0x100000U) -#define LPUART_CTRL_ILIE_SHIFT (20U) -/*! ILIE - Idle Line Interrupt Enable - * 0b0..Hardware interrupts from IDLE disabled; use polling. - * 0b1..Hardware interrupt requested when IDLE flag is 1. - */ -#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) -#define LPUART_CTRL_RIE_MASK (0x200000U) -#define LPUART_CTRL_RIE_SHIFT (21U) -/*! RIE - Receiver Interrupt Enable - * 0b0..Hardware interrupts from RDRF disabled; use polling. - * 0b1..Hardware interrupt requested when RDRF flag is 1. - */ -#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) -#define LPUART_CTRL_TCIE_MASK (0x400000U) -#define LPUART_CTRL_TCIE_SHIFT (22U) -/*! TCIE - Transmission Complete Interrupt Enable for - * 0b0..Hardware interrupts from TC disabled; use polling. - * 0b1..Hardware interrupt requested when TC flag is 1. - */ -#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) -#define LPUART_CTRL_TIE_MASK (0x800000U) -#define LPUART_CTRL_TIE_SHIFT (23U) -/*! TIE - Transmit Interrupt Enable - * 0b0..Hardware interrupts from TDRE disabled; use polling. - * 0b1..Hardware interrupt requested when TDRE flag is 1. - */ -#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) -#define LPUART_CTRL_PEIE_MASK (0x1000000U) -#define LPUART_CTRL_PEIE_SHIFT (24U) -/*! PEIE - Parity Error Interrupt Enable - * 0b0..PF interrupts disabled; use polling). - * 0b1..Hardware interrupt requested when PF is set. - */ -#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) -#define LPUART_CTRL_FEIE_MASK (0x2000000U) -#define LPUART_CTRL_FEIE_SHIFT (25U) -/*! FEIE - Framing Error Interrupt Enable - * 0b0..FE interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when FE is set. - */ -#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) -#define LPUART_CTRL_NEIE_MASK (0x4000000U) -#define LPUART_CTRL_NEIE_SHIFT (26U) -/*! NEIE - Noise Error Interrupt Enable - * 0b0..NF interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when NF is set. - */ -#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) -#define LPUART_CTRL_ORIE_MASK (0x8000000U) -#define LPUART_CTRL_ORIE_SHIFT (27U) -/*! ORIE - Overrun Interrupt Enable - * 0b0..OR interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when OR is set. - */ -#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) -#define LPUART_CTRL_TXINV_MASK (0x10000000U) -#define LPUART_CTRL_TXINV_SHIFT (28U) -/*! TXINV - Transmit Data Inversion - * 0b0..Transmit data not inverted. - * 0b1..Transmit data inverted. - */ -#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) -#define LPUART_CTRL_TXDIR_MASK (0x20000000U) -#define LPUART_CTRL_TXDIR_SHIFT (29U) -/*! TXDIR - TXD Pin Direction in Single-Wire Mode - * 0b0..TXD pin is an input in single-wire mode. - * 0b1..TXD pin is an output in single-wire mode. - */ -#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) -#define LPUART_CTRL_R9T8_MASK (0x40000000U) -#define LPUART_CTRL_R9T8_SHIFT (30U) -#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) -#define LPUART_CTRL_R8T9_MASK (0x80000000U) -#define LPUART_CTRL_R8T9_SHIFT (31U) -#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) -/*! @} */ - -/*! @name DATA - LPUART Data Register */ -/*! @{ */ -#define LPUART_DATA_R0T0_MASK (0x1U) -#define LPUART_DATA_R0T0_SHIFT (0U) -#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) -#define LPUART_DATA_R1T1_MASK (0x2U) -#define LPUART_DATA_R1T1_SHIFT (1U) -#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) -#define LPUART_DATA_R2T2_MASK (0x4U) -#define LPUART_DATA_R2T2_SHIFT (2U) -#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) -#define LPUART_DATA_R3T3_MASK (0x8U) -#define LPUART_DATA_R3T3_SHIFT (3U) -#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) -#define LPUART_DATA_R4T4_MASK (0x10U) -#define LPUART_DATA_R4T4_SHIFT (4U) -#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) -#define LPUART_DATA_R5T5_MASK (0x20U) -#define LPUART_DATA_R5T5_SHIFT (5U) -#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) -#define LPUART_DATA_R6T6_MASK (0x40U) -#define LPUART_DATA_R6T6_SHIFT (6U) -#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) -#define LPUART_DATA_R7T7_MASK (0x80U) -#define LPUART_DATA_R7T7_SHIFT (7U) -#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) -#define LPUART_DATA_R8T8_MASK (0x100U) -#define LPUART_DATA_R8T8_SHIFT (8U) -#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) -#define LPUART_DATA_R9T9_MASK (0x200U) -#define LPUART_DATA_R9T9_SHIFT (9U) -#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) -#define LPUART_DATA_IDLINE_MASK (0x800U) -#define LPUART_DATA_IDLINE_SHIFT (11U) -/*! IDLINE - Idle Line - * 0b0..Receiver was not idle before receiving this character. - * 0b1..Receiver was idle before receiving this character. - */ -#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) -#define LPUART_DATA_RXEMPT_MASK (0x1000U) -#define LPUART_DATA_RXEMPT_SHIFT (12U) -/*! RXEMPT - Receive Buffer Empty - * 0b0..Receive buffer contains valid data. - * 0b1..Receive buffer is empty, data returned on read is not valid. - */ -#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) -#define LPUART_DATA_FRETSC_MASK (0x2000U) -#define LPUART_DATA_FRETSC_SHIFT (13U) -/*! FRETSC - Frame Error / Transmit Special Character - * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. - * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. - */ -#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) -#define LPUART_DATA_PARITYE_MASK (0x4000U) -#define LPUART_DATA_PARITYE_SHIFT (14U) -/*! PARITYE - PARITYE - * 0b0..The dataword was received without a parity error. - * 0b1..The dataword was received with a parity error. - */ -#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) -#define LPUART_DATA_NOISY_MASK (0x8000U) -#define LPUART_DATA_NOISY_SHIFT (15U) -/*! NOISY - NOISY - * 0b0..The dataword was received without noise. - * 0b1..The data was received with noise. - */ -#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) -/*! @} */ - -/*! @name MATCH - LPUART Match Address Register */ -/*! @{ */ -#define LPUART_MATCH_MA1_MASK (0x3FFU) -#define LPUART_MATCH_MA1_SHIFT (0U) -#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) -#define LPUART_MATCH_MA2_MASK (0x3FF0000U) -#define LPUART_MATCH_MA2_SHIFT (16U) -#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) -/*! @} */ - -/*! @name MODIR - LPUART Modem IrDA Register */ -/*! @{ */ -#define LPUART_MODIR_TXCTSE_MASK (0x1U) -#define LPUART_MODIR_TXCTSE_SHIFT (0U) -/*! TXCTSE - Transmitter clear-to-send enable - * 0b0..CTS has no effect on the transmitter. - * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. - */ -#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) -#define LPUART_MODIR_TXRTSE_MASK (0x2U) -#define LPUART_MODIR_TXRTSE_SHIFT (1U) -/*! TXRTSE - Transmitter request-to-send enable - * 0b0..The transmitter has no effect on RTS. - * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. - */ -#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) -#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) -#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) -/*! TXRTSPOL - Transmitter request-to-send polarity - * 0b0..Transmitter RTS is active low. - * 0b1..Transmitter RTS is active high. - */ -#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) -#define LPUART_MODIR_RXRTSE_MASK (0x8U) -#define LPUART_MODIR_RXRTSE_SHIFT (3U) -/*! RXRTSE - Receiver request-to-send enable - * 0b0..The receiver has no effect on RTS. - * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. - */ -#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) -#define LPUART_MODIR_TXCTSC_MASK (0x10U) -#define LPUART_MODIR_TXCTSC_SHIFT (4U) -/*! TXCTSC - Transmit CTS Configuration - * 0b0..CTS input is sampled at the start of each character. - * 0b1..CTS input is sampled when the transmitter is idle. - */ -#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) -#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) -#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) -/*! TXCTSSRC - Transmit CTS Source - * 0b0..CTS input is the CTS_B pin. - * 0b1..CTS input is the inverted Receiver Match result. - */ -#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) -#define LPUART_MODIR_RTSWATER_MASK (0x700U) -#define LPUART_MODIR_RTSWATER_SHIFT (8U) -#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) -#define LPUART_MODIR_TNP_MASK (0x30000U) -#define LPUART_MODIR_TNP_SHIFT (16U) -/*! TNP - Transmitter narrow pulse - * 0b00..1/OSR. - * 0b01..2/OSR. - * 0b10..3/OSR. - * 0b11..4/OSR. - */ -#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) -#define LPUART_MODIR_IREN_MASK (0x40000U) -#define LPUART_MODIR_IREN_SHIFT (18U) -/*! IREN - Infrared enable - * 0b0..IR disabled. - * 0b1..IR enabled. - */ -#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) -/*! @} */ - -/*! @name FIFO - LPUART FIFO Register */ -/*! @{ */ -#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) -#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) -/*! RXFIFOSIZE - Receive FIFO. Buffer Depth - * 0b000..Receive FIFO/Buffer depth = 1 dataword. - * 0b001..Receive FIFO/Buffer depth = 4 datawords. - * 0b010..Receive FIFO/Buffer depth = 8 datawords. - * 0b011..Receive FIFO/Buffer depth = 16 datawords. - * 0b100..Receive FIFO/Buffer depth = 32 datawords. - * 0b101..Receive FIFO/Buffer depth = 64 datawords. - * 0b110..Receive FIFO/Buffer depth = 128 datawords. - * 0b111..Receive FIFO/Buffer depth = 256 datawords. - */ -#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) -#define LPUART_FIFO_RXFE_MASK (0x8U) -#define LPUART_FIFO_RXFE_SHIFT (3U) -/*! RXFE - Receive FIFO Enable - * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) - * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. - */ -#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) -#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) -#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) -/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth - * 0b000..Transmit FIFO/Buffer depth = 1 dataword. - * 0b001..Transmit FIFO/Buffer depth = 4 datawords. - * 0b010..Transmit FIFO/Buffer depth = 8 datawords. - * 0b011..Transmit FIFO/Buffer depth = 16 datawords. - * 0b100..Transmit FIFO/Buffer depth = 32 datawords. - * 0b101..Transmit FIFO/Buffer depth = 64 datawords. - * 0b110..Transmit FIFO/Buffer depth = 128 datawords. - * 0b111..Transmit FIFO/Buffer depth = 256 datawords - */ -#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) -#define LPUART_FIFO_TXFE_MASK (0x80U) -#define LPUART_FIFO_TXFE_SHIFT (7U) -/*! TXFE - Transmit FIFO Enable - * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). - * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. - */ -#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) -#define LPUART_FIFO_RXUFE_MASK (0x100U) -#define LPUART_FIFO_RXUFE_SHIFT (8U) -/*! RXUFE - Receive FIFO Underflow Interrupt Enable - * 0b0..RXUF flag does not generate an interrupt to the host. - * 0b1..RXUF flag generates an interrupt to the host. - */ -#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) -#define LPUART_FIFO_TXOFE_MASK (0x200U) -#define LPUART_FIFO_TXOFE_SHIFT (9U) -/*! TXOFE - Transmit FIFO Overflow Interrupt Enable - * 0b0..TXOF flag does not generate an interrupt to the host. - * 0b1..TXOF flag generates an interrupt to the host. - */ -#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) -#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) -#define LPUART_FIFO_RXIDEN_SHIFT (10U) -/*! RXIDEN - Receiver Idle Empty Enable - * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. - * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. - * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. - * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. - * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. - * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. - * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. - * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. - */ -#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) -#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) -#define LPUART_FIFO_RXFLUSH_SHIFT (14U) -/*! RXFLUSH - Receive FIFO/Buffer Flush - * 0b0..No flush operation occurs. - * 0b1..All data in the receive FIFO/buffer is cleared out. - */ -#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) -#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) -#define LPUART_FIFO_TXFLUSH_SHIFT (15U) -/*! TXFLUSH - Transmit FIFO/Buffer Flush - * 0b0..No flush operation occurs. - * 0b1..All data in the transmit FIFO/Buffer is cleared out. - */ -#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) -#define LPUART_FIFO_RXUF_MASK (0x10000U) -#define LPUART_FIFO_RXUF_SHIFT (16U) -/*! RXUF - Receiver Buffer Underflow Flag - * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. - * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. - */ -#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) -#define LPUART_FIFO_TXOF_MASK (0x20000U) -#define LPUART_FIFO_TXOF_SHIFT (17U) -/*! TXOF - Transmitter Buffer Overflow Flag - * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. - * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. - */ -#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) -#define LPUART_FIFO_RXEMPT_MASK (0x400000U) -#define LPUART_FIFO_RXEMPT_SHIFT (22U) -/*! RXEMPT - Receive Buffer/FIFO Empty - * 0b0..Receive buffer is not empty. - * 0b1..Receive buffer is empty. - */ -#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) -#define LPUART_FIFO_TXEMPT_MASK (0x800000U) -#define LPUART_FIFO_TXEMPT_SHIFT (23U) -/*! TXEMPT - Transmit Buffer/FIFO Empty - * 0b0..Transmit buffer is not empty. - * 0b1..Transmit buffer is empty. - */ -#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) -/*! @} */ - -/*! @name WATER - LPUART Watermark Register */ -/*! @{ */ -#define LPUART_WATER_TXWATER_MASK (0x7U) -#define LPUART_WATER_TXWATER_SHIFT (0U) -#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) -#define LPUART_WATER_TXCOUNT_MASK (0xF00U) -#define LPUART_WATER_TXCOUNT_SHIFT (8U) -#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) -#define LPUART_WATER_RXWATER_MASK (0x70000U) -#define LPUART_WATER_RXWATER_SHIFT (16U) -#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) -#define LPUART_WATER_RXCOUNT_MASK (0xF000000U) -#define LPUART_WATER_RXCOUNT_SHIFT (24U) -#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPUART_Register_Masks */ - - -/* LPUART - Peripheral instance base addresses */ -/** Peripheral LPUART0 base address */ -#define LPUART0_BASE (0x40042000u) -/** Peripheral LPUART0 base pointer */ -#define LPUART0 ((LPUART_Type *)LPUART0_BASE) -/** Peripheral LPUART1 base address */ -#define LPUART1_BASE (0x40043000u) -/** Peripheral LPUART1 base pointer */ -#define LPUART1 ((LPUART_Type *)LPUART1_BASE) -/** Peripheral LPUART2 base address */ -#define LPUART2_BASE (0x40044000u) -/** Peripheral LPUART2 base pointer */ -#define LPUART2 ((LPUART_Type *)LPUART2_BASE) -/** Peripheral LPUART3 base address */ -#define LPUART3_BASE (0x41036000u) -/** Peripheral LPUART3 base pointer */ -#define LPUART3 ((LPUART_Type *)LPUART3_BASE) -/** Array initializer of LPUART peripheral base addresses */ -#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE } -/** Array initializer of LPUART peripheral base pointers */ -#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3 } -/** Interrupt vectors for the LPUART peripheral type */ -#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } -#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn } - -/*! - * @} - */ /* end of group LPUART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer - * @{ - */ - -/** MCM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[8]; - __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ - __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ - __IO uint32_t CPCR; /**< Core Platform Control Register, offset: 0xC */ - uint8_t RESERVED_1[36]; - __IO uint32_t CPCR2; /**< Core Platform Control Register 2, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ -} MCM_Type; - -/* ---------------------------------------------------------------------------- - -- MCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MCM_Register_Masks MCM Register Masks - * @{ - */ - -/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ -/*! @{ */ -#define MCM_PLASC_ASC_MASK (0xFFU) -#define MCM_PLASC_ASC_SHIFT (0U) -/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. - * 0b00000000..A bus slave connection to AXBS input port n is absent - * 0b00000001..A bus slave connection to AXBS input port n is present - */ -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) -/*! @} */ - -/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ -/*! @{ */ -#define MCM_PLAMC_AMC_MASK (0xFFU) -#define MCM_PLAMC_AMC_SHIFT (0U) -/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. - * 0b00000000..A bus master connection to AXBS input port n is absent - * 0b00000001..A bus master connection to AXBS input port n is present - */ -#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) -/*! @} */ - -/*! @name CPCR - Core Platform Control Register */ -/*! @{ */ -#define MCM_CPCR_ARB_MASK (0x200U) -#define MCM_CPCR_ARB_SHIFT (9U) -/*! ARB - Arbitration select - * 0b0..Fixed-priority arbitration for the crossbar masters - * 0b1..Round-robin arbitration for the crossbar masters - */ -#define MCM_CPCR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_ARB_SHIFT)) & MCM_CPCR_ARB_MASK) -/*! @} */ - -/*! @name CPCR2 - Core Platform Control Register 2 */ -/*! @{ */ -#define MCM_CPCR2_CCBC_MASK (0x1U) -#define MCM_CPCR2_CCBC_SHIFT (0U) -#define MCM_CPCR2_CCBC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCBC_SHIFT)) & MCM_CPCR2_CCBC_MASK) -#define MCM_CPCR2_DCC_MASK (0x8U) -#define MCM_CPCR2_DCC_SHIFT (3U) -#define MCM_CPCR2_DCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCC_SHIFT)) & MCM_CPCR2_DCC_MASK) -#define MCM_CPCR2_CCSIZ_MASK (0xF0U) -#define MCM_CPCR2_CCSIZ_SHIFT (4U) -/*! CCSIZ - Code cache size - * 0b0000..No cache - * 0b0010..2KB - * 0b0011..4KB - * 0b0100..8KB - */ -#define MCM_CPCR2_CCSIZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCSIZ_SHIFT)) & MCM_CPCR2_CCSIZ_MASK) -/*! @} */ - -/*! @name CPO - Compute Operation Control Register */ -/*! @{ */ -#define MCM_CPO_CPOREQ_MASK (0x1U) -#define MCM_CPO_CPOREQ_SHIFT (0U) -/*! CPOREQ - Compute Operation request - * 0b0..Request is cleared. - * 0b1..Request Compute Operation. - */ -#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) -#define MCM_CPO_CPOACK_MASK (0x2U) -#define MCM_CPO_CPOACK_SHIFT (1U) -/*! CPOACK - Compute Operation acknowledge - * 0b0..Compute operation entry has not completed or compute operation exit has completed. - * 0b1..Compute operation entry has completed or compute operation exit has not completed. - */ -#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) -#define MCM_CPO_CPOWOI_MASK (0x4U) -#define MCM_CPO_CPOWOI_SHIFT (2U) -/*! CPOWOI - Compute Operation wakeup on interrupt - * 0b0..No effect. - * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. - */ -#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MCM_Register_Masks */ - - -/* MCM - Peripheral instance base addresses */ -/** Peripheral MCM1 base address */ -#define MCM1_BASE (0xF0003000u) -/** Peripheral MCM1 base pointer */ -#define MCM1 ((MCM_Type *)MCM1_BASE) -/** Array initializer of MCM peripheral base addresses */ -#define MCM_BASE_ADDRS { 0u, MCM1_BASE } -/** Array initializer of MCM peripheral base pointers */ -#define MCM_BASE_PTRS { (MCM_Type *)0u, MCM1 } -/* MCM compatibility definitions */ -#define MCM_BASE MCM1_BASE -#define MCM MCM1 - - -/*! - * @} - */ /* end of group MCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MMDVSQ Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer - * @{ - */ - -/** MMDVSQ - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */ - __IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */ - __IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */ - __IO uint32_t RES; /**< Result Register, offset: 0xC */ - __O uint32_t RCND; /**< Radicand Register, offset: 0x10 */ -} MMDVSQ_Type; - -/* ---------------------------------------------------------------------------- - -- MMDVSQ Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks - * @{ - */ - -/*! @name DEND - Dividend Register */ -/*! @{ */ -#define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU) -#define MMDVSQ_DEND_DIVIDEND_SHIFT (0U) -#define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK) -/*! @} */ - -/*! @name DSOR - Divisor Register */ -/*! @{ */ -#define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU) -#define MMDVSQ_DSOR_DIVISOR_SHIFT (0U) -#define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK) -/*! @} */ - -/*! @name CSR - Control/Status Register */ -/*! @{ */ -#define MMDVSQ_CSR_SRT_MASK (0x1U) -#define MMDVSQ_CSR_SRT_SHIFT (0U) -/*! SRT - Start - * 0b0..No operation initiated - * 0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore - */ -#define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK) -#define MMDVSQ_CSR_USGN_MASK (0x2U) -#define MMDVSQ_CSR_USGN_SHIFT (1U) -/*! USGN - Unsigned calculation - * 0b0..Perform a signed divide - * 0b1..Perform an unsigned divide - */ -#define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK) -#define MMDVSQ_CSR_REM_MASK (0x4U) -#define MMDVSQ_CSR_REM_SHIFT (2U) -/*! REM - REMainder calculation - * 0b0..Return the quotient in the RES for the divide calculation - * 0b1..Return the remainder in the RES for the divide calculation - */ -#define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK) -#define MMDVSQ_CSR_DZE_MASK (0x8U) -#define MMDVSQ_CSR_DZE_SHIFT (3U) -/*! DZE - Divide-by-Zero-Enable - * 0b0..Reads of the RES register return the register contents - * 0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned - */ -#define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK) -#define MMDVSQ_CSR_DZ_MASK (0x10U) -#define MMDVSQ_CSR_DZ_SHIFT (4U) -/*! DZ - Divide-by-Zero - * 0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0 - * 0b1..The last divide operation had a zero divisor, that is, DSOR = 0 - */ -#define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK) -#define MMDVSQ_CSR_DFS_MASK (0x20U) -#define MMDVSQ_CSR_DFS_SHIFT (5U) -/*! DFS - Disable Fast Start - * 0b0..A divide operation is initiated by a write to the DSOR register - * 0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 - */ -#define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK) -#define MMDVSQ_CSR_SQRT_MASK (0x20000000U) -#define MMDVSQ_CSR_SQRT_SHIFT (29U) -/*! SQRT - SQUARE ROOT - * 0b0..Current or last MMDVSQ operation was not a square root - * 0b1..Current or last MMDVSQ operation was a square root - */ -#define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK) -#define MMDVSQ_CSR_DIV_MASK (0x40000000U) -#define MMDVSQ_CSR_DIV_SHIFT (30U) -/*! DIV - DIVIDE - * 0b0..Current or last MMDVSQ operation was not a divide - * 0b1..Current or last MMDVSQ operation was a divide - */ -#define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK) -#define MMDVSQ_CSR_BUSY_MASK (0x80000000U) -#define MMDVSQ_CSR_BUSY_SHIFT (31U) -/*! BUSY - BUSY - * 0b0..MMDVSQ is idle - * 0b1..MMDVSQ is busy performing a divide or square root calculation - */ -#define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK) -/*! @} */ - -/*! @name RES - Result Register */ -/*! @{ */ -#define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU) -#define MMDVSQ_RES_RESULT_SHIFT (0U) -#define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK) -/*! @} */ - -/*! @name RCND - Radicand Register */ -/*! @{ */ -#define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU) -#define MMDVSQ_RCND_RADICAND_SHIFT (0U) -#define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MMDVSQ_Register_Masks */ - - -/* MMDVSQ - Peripheral instance base addresses */ -/** Peripheral MMDVSQ1 base address */ -#define MMDVSQ1_BASE (0xF0004000u) -/** Peripheral MMDVSQ1 base pointer */ -#define MMDVSQ1 ((MMDVSQ_Type *)MMDVSQ1_BASE) -/** Array initializer of MMDVSQ peripheral base addresses */ -#define MMDVSQ_BASE_ADDRS { 0u, MMDVSQ1_BASE } -/** Array initializer of MMDVSQ peripheral base pointers */ -#define MMDVSQ_BASE_PTRS { (MMDVSQ_Type *)0u, MMDVSQ1 } - -/*! - * @} - */ /* end of group MMDVSQ_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MSCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer - * @{ - */ - -/** MSCM - Register Layout Typedef */ -typedef struct { - __I uint32_t CPXTYPE; /**< Processor X Type Register, offset: 0x0 */ - __I uint32_t CPXNUM; /**< Processor X Number Register, offset: 0x4 */ - __I uint32_t CPXMASTER; /**< Processor X Master Register, offset: 0x8 */ - __I uint32_t CPXCOUNT; /**< Processor X Count Register, offset: 0xC */ - __I uint32_t CPXCFG0; /**< Processor X Configuration Register 0, offset: 0x10 */ - __I uint32_t CPXCFG1; /**< Processor X Configuration Register 1, offset: 0x14 */ - __I uint32_t CPXCFG2; /**< Processor X Configuration Register 2, offset: 0x18 */ - __I uint32_t CPXCFG3; /**< Processor X Configuration Register 3, offset: 0x1C */ - struct { /* offset: 0x20, array step: 0x20 */ - __I uint32_t TYPE; /**< Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20 */ - __I uint32_t NUM; /**< Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20 */ - __I uint32_t MASTER; /**< Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20 */ - __I uint32_t COUNT; /**< Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20 */ - __I uint32_t CFG0; /**< Processor 0 Configuration Register 0..Processor 1 Configuration Register 0, array offset: 0x30, array step: 0x20 */ - __I uint32_t CFG1; /**< Processor 0 Configuration Register 1..Processor 1 Configuration Register 1, array offset: 0x34, array step: 0x20 */ - __I uint32_t CFG2; /**< Processor 0 Configuration Register 2..Processor 1 Configuration Register 2, array offset: 0x38, array step: 0x20 */ - __I uint32_t CFG3; /**< Processor 0 Configuration Register 3..Processor 1 Configuration Register 3, array offset: 0x3C, array step: 0x20 */ - } CP[2]; - uint8_t RESERVED_0[928]; - __IO uint32_t OCMDR0; /**< On-Chip Memory Descriptor Register, offset: 0x400 */ - __IO uint32_t OCMDR1; /**< On-Chip Memory Descriptor Register, offset: 0x404 */ - __IO uint32_t OCMDR2; /**< On-Chip Memory Descriptor Register, offset: 0x408 */ - __IO uint32_t OCMDR3; /**< On-Chip Memory Descriptor Register, offset: 0x40C */ -} MSCM_Type; - -/* ---------------------------------------------------------------------------- - -- MSCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MSCM_Register_Masks MSCM Register Masks - * @{ - */ - -/*! @name CPXTYPE - Processor X Type Register */ -/*! @{ */ -#define MSCM_CPXTYPE_RYPZ_MASK (0xFFU) -#define MSCM_CPXTYPE_RYPZ_SHIFT (0U) -#define MSCM_CPXTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_RYPZ_SHIFT)) & MSCM_CPXTYPE_RYPZ_MASK) -#define MSCM_CPXTYPE_PERSONALITY_MASK (0xFFFFFF00U) -#define MSCM_CPXTYPE_PERSONALITY_SHIFT (8U) -#define MSCM_CPXTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK) -/*! @} */ - -/*! @name CPXNUM - Processor X Number Register */ -/*! @{ */ -#define MSCM_CPXNUM_CPN_MASK (0x1U) -#define MSCM_CPXNUM_CPN_SHIFT (0U) -#define MSCM_CPXNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK) -/*! @} */ - -/*! @name CPXMASTER - Processor X Master Register */ -/*! @{ */ -#define MSCM_CPXMASTER_PPMN_MASK (0x3FU) -#define MSCM_CPXMASTER_PPMN_SHIFT (0U) -#define MSCM_CPXMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXMASTER_PPMN_SHIFT)) & MSCM_CPXMASTER_PPMN_MASK) -/*! @} */ - -/*! @name CPXCOUNT - Processor X Count Register */ -/*! @{ */ -#define MSCM_CPXCOUNT_PCNT_MASK (0x3U) -#define MSCM_CPXCOUNT_PCNT_SHIFT (0U) -#define MSCM_CPXCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCOUNT_PCNT_SHIFT)) & MSCM_CPXCOUNT_PCNT_MASK) -/*! @} */ - -/*! @name CPXCFG0 - Processor X Configuration Register 0 */ -/*! @{ */ -#define MSCM_CPXCFG0_DCWY_MASK (0xFFU) -#define MSCM_CPXCFG0_DCWY_SHIFT (0U) -#define MSCM_CPXCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK) -#define MSCM_CPXCFG0_DCSZ_MASK (0xFF00U) -#define MSCM_CPXCFG0_DCSZ_SHIFT (8U) -#define MSCM_CPXCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK) -#define MSCM_CPXCFG0_ICWY_MASK (0xFF0000U) -#define MSCM_CPXCFG0_ICWY_SHIFT (16U) -#define MSCM_CPXCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK) -#define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) -#define MSCM_CPXCFG0_ICSZ_SHIFT (24U) -#define MSCM_CPXCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK) -/*! @} */ - -/*! @name CPXCFG1 - Processor X Configuration Register 1 */ -/*! @{ */ -#define MSCM_CPXCFG1_L2WY_MASK (0xFF0000U) -#define MSCM_CPXCFG1_L2WY_SHIFT (16U) -#define MSCM_CPXCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK) -#define MSCM_CPXCFG1_L2SZ_MASK (0xFF000000U) -#define MSCM_CPXCFG1_L2SZ_SHIFT (24U) -#define MSCM_CPXCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK) -/*! @} */ - -/*! @name CPXCFG2 - Processor X Configuration Register 2 */ -/*! @{ */ -#define MSCM_CPXCFG2_TMUSZ_MASK (0xFF00U) -#define MSCM_CPXCFG2_TMUSZ_SHIFT (8U) -#define MSCM_CPXCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMUSZ_SHIFT)) & MSCM_CPXCFG2_TMUSZ_MASK) -#define MSCM_CPXCFG2_TMLSZ_MASK (0xFF000000U) -#define MSCM_CPXCFG2_TMLSZ_SHIFT (24U) -#define MSCM_CPXCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMLSZ_SHIFT)) & MSCM_CPXCFG2_TMLSZ_MASK) -/*! @} */ - -/*! @name CPXCFG3 - Processor X Configuration Register 3 */ -/*! @{ */ -#define MSCM_CPXCFG3_FPU_MASK (0x1U) -#define MSCM_CPXCFG3_FPU_SHIFT (0U) -/*! FPU - Floating Point Unit - * 0b0..FPU support is not included. - * 0b1..FPU support is included. - */ -#define MSCM_CPXCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK) -#define MSCM_CPXCFG3_SIMD_MASK (0x2U) -#define MSCM_CPXCFG3_SIMD_SHIFT (1U) -/*! SIMD - SIMD/NEON instruction support - * 0b0..SIMD/NEON support is not included. - * 0b1..SIMD/NEON support is included. - */ -#define MSCM_CPXCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK) -#define MSCM_CPXCFG3_JAZ_MASK (0x4U) -#define MSCM_CPXCFG3_JAZ_SHIFT (2U) -/*! JAZ - Jazelle support - * 0b0..Jazelle support is not included. - * 0b1..Jazelle support is included. - */ -#define MSCM_CPXCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_JAZ_SHIFT)) & MSCM_CPXCFG3_JAZ_MASK) -#define MSCM_CPXCFG3_MMU_MASK (0x8U) -#define MSCM_CPXCFG3_MMU_SHIFT (3U) -/*! MMU - Memory Management Unit - * 0b0..MMU support is not included. - * 0b1..MMU support is included. - */ -#define MSCM_CPXCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK) -#define MSCM_CPXCFG3_TZ_MASK (0x10U) -#define MSCM_CPXCFG3_TZ_SHIFT (4U) -/*! TZ - Trust Zone - * 0b0..Trust Zone support is not included. - * 0b1..Trust Zone support is included. - */ -#define MSCM_CPXCFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_TZ_SHIFT)) & MSCM_CPXCFG3_TZ_MASK) -#define MSCM_CPXCFG3_CMP_MASK (0x20U) -#define MSCM_CPXCFG3_CMP_SHIFT (5U) -/*! CMP - Core Memory Protection unit - * 0b0..Core Memory Protection is not included. - * 0b1..Core Memory Protection is included. - */ -#define MSCM_CPXCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK) -#define MSCM_CPXCFG3_BB_MASK (0x40U) -#define MSCM_CPXCFG3_BB_SHIFT (6U) -/*! BB - Bit Banding - * 0b0..Bit Banding is not supported. - * 0b1..Bit Banding is supported. - */ -#define MSCM_CPXCFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_BB_SHIFT)) & MSCM_CPXCFG3_BB_MASK) -#define MSCM_CPXCFG3_SBP_MASK (0x300U) -#define MSCM_CPXCFG3_SBP_SHIFT (8U) -#define MSCM_CPXCFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SBP_SHIFT)) & MSCM_CPXCFG3_SBP_MASK) -/*! @} */ - -/*! @name TYPE - Processor 0 Type Register..Processor 1 Type Register */ -/*! @{ */ -#define MSCM_TYPE_RYPZ_MASK (0xFFU) -#define MSCM_TYPE_RYPZ_SHIFT (0U) -#define MSCM_TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK) -#define MSCM_TYPE_PERSONALITY_MASK (0xFFFFFF00U) -#define MSCM_TYPE_PERSONALITY_SHIFT (8U) -#define MSCM_TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK) -/*! @} */ - -/* The count of MSCM_TYPE */ -#define MSCM_TYPE_COUNT (2U) - -/*! @name NUM - Processor 0 Number Register..Processor 1 Number Register */ -/*! @{ */ -#define MSCM_NUM_CPN_MASK (0x1U) -#define MSCM_NUM_CPN_SHIFT (0U) -#define MSCM_NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK) -/*! @} */ - -/* The count of MSCM_NUM */ -#define MSCM_NUM_COUNT (2U) - -/*! @name MASTER - Processor 0 Master Register..Processor 1 Master Register */ -/*! @{ */ -#define MSCM_MASTER_PPMN_MASK (0x3FU) -#define MSCM_MASTER_PPMN_SHIFT (0U) -#define MSCM_MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPMN_SHIFT)) & MSCM_MASTER_PPMN_MASK) -/*! @} */ - -/* The count of MSCM_MASTER */ -#define MSCM_MASTER_COUNT (2U) - -/*! @name COUNT - Processor 0 Count Register..Processor 1 Count Register */ -/*! @{ */ -#define MSCM_COUNT_PCNT_MASK (0x3U) -#define MSCM_COUNT_PCNT_SHIFT (0U) -#define MSCM_COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK) -/*! @} */ - -/* The count of MSCM_COUNT */ -#define MSCM_COUNT_COUNT (2U) - -/*! @name CFG0 - Processor 0 Configuration Register 0..Processor 1 Configuration Register 0 */ -/*! @{ */ -#define MSCM_CFG0_DCWY_MASK (0xFFU) -#define MSCM_CFG0_DCWY_SHIFT (0U) -#define MSCM_CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCWY_SHIFT)) & MSCM_CFG0_DCWY_MASK) -#define MSCM_CFG0_DCSZ_MASK (0xFF00U) -#define MSCM_CFG0_DCSZ_SHIFT (8U) -#define MSCM_CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCSZ_SHIFT)) & MSCM_CFG0_DCSZ_MASK) -#define MSCM_CFG0_ICWY_MASK (0xFF0000U) -#define MSCM_CFG0_ICWY_SHIFT (16U) -#define MSCM_CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICWY_SHIFT)) & MSCM_CFG0_ICWY_MASK) -#define MSCM_CFG0_ICSZ_MASK (0xFF000000U) -#define MSCM_CFG0_ICSZ_SHIFT (24U) -#define MSCM_CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICSZ_SHIFT)) & MSCM_CFG0_ICSZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG0 */ -#define MSCM_CFG0_COUNT (2U) - -/*! @name CFG1 - Processor 0 Configuration Register 1..Processor 1 Configuration Register 1 */ -/*! @{ */ -#define MSCM_CFG1_L2WY_MASK (0xFF0000U) -#define MSCM_CFG1_L2WY_SHIFT (16U) -#define MSCM_CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2WY_SHIFT)) & MSCM_CFG1_L2WY_MASK) -#define MSCM_CFG1_L2SZ_MASK (0xFF000000U) -#define MSCM_CFG1_L2SZ_SHIFT (24U) -#define MSCM_CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2SZ_SHIFT)) & MSCM_CFG1_L2SZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG1 */ -#define MSCM_CFG1_COUNT (2U) - -/*! @name CFG2 - Processor 0 Configuration Register 2..Processor 1 Configuration Register 2 */ -/*! @{ */ -#define MSCM_CFG2_TMUSZ_MASK (0xFF00U) -#define MSCM_CFG2_TMUSZ_SHIFT (8U) -#define MSCM_CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMUSZ_SHIFT)) & MSCM_CFG2_TMUSZ_MASK) -#define MSCM_CFG2_TMLSZ_MASK (0xFF000000U) -#define MSCM_CFG2_TMLSZ_SHIFT (24U) -#define MSCM_CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMLSZ_SHIFT)) & MSCM_CFG2_TMLSZ_MASK) -/*! @} */ - -/* The count of MSCM_CFG2 */ -#define MSCM_CFG2_COUNT (2U) - -/*! @name CFG3 - Processor 0 Configuration Register 3..Processor 1 Configuration Register 3 */ -/*! @{ */ -#define MSCM_CFG3_FPU_MASK (0x1U) -#define MSCM_CFG3_FPU_SHIFT (0U) -/*! FPU - Floating Point Unit - * 0b0..FPU support is not included. - * 0b1..FPU support is included. - */ -#define MSCM_CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK) -#define MSCM_CFG3_SIMD_MASK (0x2U) -#define MSCM_CFG3_SIMD_SHIFT (1U) -/*! SIMD - SIMD/NEON instruction support - * 0b0..SIMD/NEON support is not included. - * 0b1..SIMD/NEON support is included. - */ -#define MSCM_CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SIMD_SHIFT)) & MSCM_CFG3_SIMD_MASK) -#define MSCM_CFG3_JAZ_MASK (0x4U) -#define MSCM_CFG3_JAZ_SHIFT (2U) -/*! JAZ - Jazelle support - * 0b0..Jazelle support is not included. - * 0b1..Jazelle support is included. - */ -#define MSCM_CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_JAZ_SHIFT)) & MSCM_CFG3_JAZ_MASK) -#define MSCM_CFG3_MMU_MASK (0x8U) -#define MSCM_CFG3_MMU_SHIFT (3U) -/*! MMU - Memory Management Unit - * 0b0..MMU support is not included. - * 0b1..MMU support is included. - */ -#define MSCM_CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_MMU_SHIFT)) & MSCM_CFG3_MMU_MASK) -#define MSCM_CFG3_TZ_MASK (0x10U) -#define MSCM_CFG3_TZ_SHIFT (4U) -/*! TZ - Trust Zone - * 0b0..Trust Zone support is not included. - * 0b1..Trust Zone support is included. - */ -#define MSCM_CFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_TZ_SHIFT)) & MSCM_CFG3_TZ_MASK) -#define MSCM_CFG3_CMP_MASK (0x20U) -#define MSCM_CFG3_CMP_SHIFT (5U) -/*! CMP - Core Memory Protection unit - * 0b0..Core Memory Protection is not included. - * 0b1..Core Memory Protection is included. - */ -#define MSCM_CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_CMP_SHIFT)) & MSCM_CFG3_CMP_MASK) -#define MSCM_CFG3_BB_MASK (0x40U) -#define MSCM_CFG3_BB_SHIFT (6U) -/*! BB - Bit Banding - * 0b0..Bit Banding is not supported. - * 0b1..Bit Banding is supported. - */ -#define MSCM_CFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_BB_SHIFT)) & MSCM_CFG3_BB_MASK) -#define MSCM_CFG3_SBP_MASK (0x300U) -#define MSCM_CFG3_SBP_SHIFT (8U) -#define MSCM_CFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SBP_SHIFT)) & MSCM_CFG3_SBP_MASK) -/*! @} */ - -/* The count of MSCM_CFG3 */ -#define MSCM_CFG3_COUNT (2U) - -/*! @name OCMDR0 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR0_OCM1_MASK (0x30U) -#define MSCM_OCMDR0_OCM1_SHIFT (4U) -#define MSCM_OCMDR0_OCM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCM1_SHIFT)) & MSCM_OCMDR0_OCM1_MASK) -#define MSCM_OCMDR0_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR0_OCMPU_SHIFT (12U) -#define MSCM_OCMDR0_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMPU_SHIFT)) & MSCM_OCMDR0_OCMPU_MASK) -#define MSCM_OCMDR0_OCMT_MASK (0xE000U) -#define MSCM_OCMDR0_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR0_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMT_SHIFT)) & MSCM_OCMDR0_OCMT_MASK) -#define MSCM_OCMDR0_RO_MASK (0x10000U) -#define MSCM_OCMDR0_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR0_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_RO_SHIFT)) & MSCM_OCMDR0_RO_MASK) -#define MSCM_OCMDR0_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR0_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR0_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMW_SHIFT)) & MSCM_OCMDR0_OCMW_MASK) -#define MSCM_OCMDR0_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR0_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR0_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZ_SHIFT)) & MSCM_OCMDR0_OCMSZ_MASK) -#define MSCM_OCMDR0_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR0_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR0_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZH_SHIFT)) & MSCM_OCMDR0_OCMSZH_MASK) -#define MSCM_OCMDR0_V_MASK (0x80000000U) -#define MSCM_OCMDR0_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR0_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_V_SHIFT)) & MSCM_OCMDR0_V_MASK) -/*! @} */ - -/*! @name OCMDR1 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR1_OCM1_MASK (0x30U) -#define MSCM_OCMDR1_OCM1_SHIFT (4U) -#define MSCM_OCMDR1_OCM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCM1_SHIFT)) & MSCM_OCMDR1_OCM1_MASK) -#define MSCM_OCMDR1_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR1_OCMPU_SHIFT (12U) -#define MSCM_OCMDR1_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMPU_SHIFT)) & MSCM_OCMDR1_OCMPU_MASK) -#define MSCM_OCMDR1_OCMT_MASK (0xE000U) -#define MSCM_OCMDR1_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR1_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMT_SHIFT)) & MSCM_OCMDR1_OCMT_MASK) -#define MSCM_OCMDR1_RO_MASK (0x10000U) -#define MSCM_OCMDR1_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR1_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_RO_SHIFT)) & MSCM_OCMDR1_RO_MASK) -#define MSCM_OCMDR1_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR1_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR1_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMW_SHIFT)) & MSCM_OCMDR1_OCMW_MASK) -#define MSCM_OCMDR1_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR1_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR1_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZ_SHIFT)) & MSCM_OCMDR1_OCMSZ_MASK) -#define MSCM_OCMDR1_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR1_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR1_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZH_SHIFT)) & MSCM_OCMDR1_OCMSZH_MASK) -#define MSCM_OCMDR1_V_MASK (0x80000000U) -#define MSCM_OCMDR1_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR1_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_V_SHIFT)) & MSCM_OCMDR1_V_MASK) -/*! @} */ - -/*! @name OCMDR2 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR2_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR2_OCMPU_SHIFT (12U) -#define MSCM_OCMDR2_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMPU_SHIFT)) & MSCM_OCMDR2_OCMPU_MASK) -#define MSCM_OCMDR2_OCMT_MASK (0xE000U) -#define MSCM_OCMDR2_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR2_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMT_SHIFT)) & MSCM_OCMDR2_OCMT_MASK) -#define MSCM_OCMDR2_RO_MASK (0x10000U) -#define MSCM_OCMDR2_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR2_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_RO_SHIFT)) & MSCM_OCMDR2_RO_MASK) -#define MSCM_OCMDR2_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR2_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR2_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMW_SHIFT)) & MSCM_OCMDR2_OCMW_MASK) -#define MSCM_OCMDR2_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR2_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR2_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZ_SHIFT)) & MSCM_OCMDR2_OCMSZ_MASK) -#define MSCM_OCMDR2_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR2_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR2_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZH_SHIFT)) & MSCM_OCMDR2_OCMSZH_MASK) -#define MSCM_OCMDR2_V_MASK (0x80000000U) -#define MSCM_OCMDR2_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR2_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_V_SHIFT)) & MSCM_OCMDR2_V_MASK) -/*! @} */ - -/*! @name OCMDR3 - On-Chip Memory Descriptor Register */ -/*! @{ */ -#define MSCM_OCMDR3_OCMPU_MASK (0x1000U) -#define MSCM_OCMDR3_OCMPU_SHIFT (12U) -#define MSCM_OCMDR3_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMPU_SHIFT)) & MSCM_OCMDR3_OCMPU_MASK) -#define MSCM_OCMDR3_OCMT_MASK (0xE000U) -#define MSCM_OCMDR3_OCMT_SHIFT (13U) -/*! OCMT - OCMT - * 0b000..Reserved - * 0b001..Reserved - * 0b010..Reserved - * 0b011..OCMEMn is a ROM. - * 0b100..OCMEMn is a Program Flash. - * 0b101..Reserved - * 0b110..OCMEMn is an EEE. - * 0b111..Reserved - */ -#define MSCM_OCMDR3_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMT_SHIFT)) & MSCM_OCMDR3_OCMT_MASK) -#define MSCM_OCMDR3_RO_MASK (0x10000U) -#define MSCM_OCMDR3_RO_SHIFT (16U) -/*! RO - RO - * 0b0..Writes to the OCMDRn[11:0] are allowed - * 0b1..Writes to the OCMDRn[11:0] are ignored - */ -#define MSCM_OCMDR3_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_RO_SHIFT)) & MSCM_OCMDR3_RO_MASK) -#define MSCM_OCMDR3_OCMW_MASK (0xE0000U) -#define MSCM_OCMDR3_OCMW_SHIFT (17U) -/*! OCMW - OCMW - * 0b000-0b001..Reserved - * 0b010..OCMEMn 32-bits wide - * 0b011..OCMEMn 64-bits wide - * 0b100..OCMEMn 128-bits wide - * 0b101..OCMEMn 256-bits wide - * 0b110-0b111..Reserved - */ -#define MSCM_OCMDR3_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMW_SHIFT)) & MSCM_OCMDR3_OCMW_MASK) -#define MSCM_OCMDR3_OCMSZ_MASK (0xF000000U) -#define MSCM_OCMDR3_OCMSZ_SHIFT (24U) -/*! OCMSZ - OCMSZ - * 0b0000..no OCMEMn - * 0b0001..1KB OCMEMn - * 0b0010..2KB OCMEMn - * 0b0011..4KB OCMEMn - * 0b0100..8KB OCMEMn - * 0b0101..16KB OCMEMn - * 0b0110..32KB OCMEMn - * 0b0111..64KB OCMEMn - * 0b1000..128KB OCMEMn - * 0b1001..256KB OCMEMn - * 0b1010..512KB OCMEMn - * 0b1011..1MB OCMEMn - * 0b1100..2MB OCMEMn - * 0b1101..4MB OCMEMn - * 0b1110..8MB OCMEMn - * 0b1111..16MB OCMEMn - */ -#define MSCM_OCMDR3_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZ_SHIFT)) & MSCM_OCMDR3_OCMSZ_MASK) -#define MSCM_OCMDR3_OCMSZH_MASK (0x10000000U) -#define MSCM_OCMDR3_OCMSZH_SHIFT (28U) -/*! OCMSZH - OCMSZH - * 0b0..OCMEMn is a power-of-2 capacity. - * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. - */ -#define MSCM_OCMDR3_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZH_SHIFT)) & MSCM_OCMDR3_OCMSZH_MASK) -#define MSCM_OCMDR3_V_MASK (0x80000000U) -#define MSCM_OCMDR3_V_SHIFT (31U) -/*! V - V - * 0b0..OCMEMn is not present. - * 0b1..OCMEMn is present. - */ -#define MSCM_OCMDR3_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_V_SHIFT)) & MSCM_OCMDR3_V_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MSCM_Register_Masks */ - - -/* MSCM - Peripheral instance base addresses */ -/** Peripheral MSCM base address */ -#define MSCM_BASE (0x40001000u) -/** Peripheral MSCM base pointer */ -#define MSCM ((MSCM_Type *)MSCM_BASE) -/** Array initializer of MSCM peripheral base addresses */ -#define MSCM_BASE_ADDRS { MSCM_BASE } -/** Array initializer of MSCM peripheral base pointers */ -#define MSCM_BASE_PTRS { MSCM } - -/*! - * @} - */ /* end of group MSCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MTB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer - * @{ - */ - -/** MTB - Register Layout Typedef */ -typedef struct { - __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ - __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ - __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ - __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ - uint8_t RESERVED_0[3824]; - __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ - uint8_t RESERVED_1[156]; - __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ - __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ - uint8_t RESERVED_2[8]; - __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ - __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ - __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ - __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ - uint8_t RESERVED_3[8]; - __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ - __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} MTB_Type; - -/* ---------------------------------------------------------------------------- - -- MTB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTB_Register_Masks MTB Register Masks - * @{ - */ - -/*! @name POSITION - MTB Position Register */ -/*! @{ */ -#define MTB_POSITION_WRAP_MASK (0x4U) -#define MTB_POSITION_WRAP_SHIFT (2U) -#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) -#define MTB_POSITION_POINTER_MASK (0xFFF8U) -#define MTB_POSITION_POINTER_SHIFT (3U) -#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) -/*! @} */ - -/*! @name MASTER - MTB Master Register */ -/*! @{ */ -#define MTB_MASTER_MASK_MASK (0x1FU) -#define MTB_MASTER_MASK_SHIFT (0U) -#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) -#define MTB_MASTER_TSTARTEN_MASK (0x20U) -#define MTB_MASTER_TSTARTEN_SHIFT (5U) -#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) -#define MTB_MASTER_TSTOPEN_MASK (0x40U) -#define MTB_MASTER_TSTOPEN_SHIFT (6U) -#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) -#define MTB_MASTER_SFRWPRIV_MASK (0x80U) -#define MTB_MASTER_SFRWPRIV_SHIFT (7U) -#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) -#define MTB_MASTER_RAMPRIV_MASK (0x100U) -#define MTB_MASTER_RAMPRIV_SHIFT (8U) -#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) -#define MTB_MASTER_HALTREQ_MASK (0x200U) -#define MTB_MASTER_HALTREQ_SHIFT (9U) -#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) -#define MTB_MASTER_EN_MASK (0x80000000U) -#define MTB_MASTER_EN_SHIFT (31U) -#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) -/*! @} */ - -/*! @name FLOW - MTB Flow Register */ -/*! @{ */ -#define MTB_FLOW_AUTOSTOP_MASK (0x1U) -#define MTB_FLOW_AUTOSTOP_SHIFT (0U) -#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) -#define MTB_FLOW_AUTOHALT_MASK (0x2U) -#define MTB_FLOW_AUTOHALT_SHIFT (1U) -#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) -#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) -#define MTB_FLOW_WATERMARK_SHIFT (3U) -#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) -/*! @} */ - -/*! @name BASE - MTB Base Register */ -/*! @{ */ -#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) -#define MTB_BASE_BASEADDR_SHIFT (0U) -#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) -/*! @} */ - -/*! @name MODECTRL - Integration Mode Control Register */ -/*! @{ */ -#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) -#define MTB_MODECTRL_MODECTRL_SHIFT (0U) -#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) -/*! @} */ - -/*! @name TAGSET - Claim TAG Set Register */ -/*! @{ */ -#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) -#define MTB_TAGSET_TAGSET_SHIFT (0U) -#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) -/*! @} */ - -/*! @name TAGCLEAR - Claim TAG Clear Register */ -/*! @{ */ -#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) -#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) -#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) -/*! @} */ - -/*! @name LOCKACCESS - Lock Access Register */ -/*! @{ */ -#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) -#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) -#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) -/*! @} */ - -/*! @name LOCKSTAT - Lock Status Register */ -/*! @{ */ -#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) -#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) -#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) -/*! @} */ - -/*! @name AUTHSTAT - Authentication Status Register */ -/*! @{ */ -#define MTB_AUTHSTAT_BIT0_MASK (0x1U) -#define MTB_AUTHSTAT_BIT0_SHIFT (0U) -#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) -#define MTB_AUTHSTAT_BIT1_MASK (0x2U) -#define MTB_AUTHSTAT_BIT1_SHIFT (1U) -#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) -#define MTB_AUTHSTAT_BIT2_MASK (0x4U) -#define MTB_AUTHSTAT_BIT2_SHIFT (2U) -#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) -#define MTB_AUTHSTAT_BIT3_MASK (0x8U) -#define MTB_AUTHSTAT_BIT3_SHIFT (3U) -#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) -/*! @} */ - -/*! @name DEVICEARCH - Device Architecture Register */ -/*! @{ */ -#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) -#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) -#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) -/*! @} */ - -/*! @name DEVICECFG - Device Configuration Register */ -/*! @{ */ -#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) -#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) -#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) -/*! @} */ - -/*! @name DEVICETYPID - Device Type Identifier Register */ -/*! @{ */ -#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) -#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) -#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) -/*! @} */ - -/*! @name PERIPHID4 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID4_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID5 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID5_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID6 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID6_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID7 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID7_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID0 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID0_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID1 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID1_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID2 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID2_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID3 - Peripheral ID Register */ -/*! @{ */ -#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define MTB_PERIPHID3_PERIPHID_SHIFT (0U) -#define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) -/*! @} */ - -/*! @name COMPID - Component ID Register */ -/*! @{ */ -#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define MTB_COMPID_COMPID_SHIFT (0U) -#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) -/*! @} */ - -/* The count of MTB_COMPID */ -#define MTB_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group MTB_Register_Masks */ - - -/* MTB - Peripheral instance base addresses */ -/** Peripheral MTB base address */ -#define MTB_BASE (0xF0000000u) -/** Peripheral MTB base pointer */ -#define MTB ((MTB_Type *)MTB_BASE) -/** Array initializer of MTB peripheral base addresses */ -#define MTB_BASE_ADDRS { MTB_BASE } -/** Array initializer of MTB peripheral base pointers */ -#define MTB_BASE_PTRS { MTB } - -/*! - * @} - */ /* end of group MTB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MTBDWT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer - * @{ - */ - -/** MTBDWT - Register Layout Typedef */ -typedef struct { - __I uint32_t CTRL; /**< DWT Control Register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - struct { /* offset: 0x20, array step: 0x10 */ - __IO uint32_t COMP; /**< DWT Comparator Register, array offset: 0x20, array step: 0x10 */ - __IO uint32_t MASK; /**< DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ - __IO uint32_t FCT; /**< DWT Comparator Function Register 0..DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } COMPARATOR[2]; - uint8_t RESERVED_1[448]; - __IO uint32_t TBCTRL; /**< DWT Trace Buffer Control Register, offset: 0x200 */ - uint8_t RESERVED_2[3524]; - __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ - __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} MTBDWT_Type; - -/* ---------------------------------------------------------------------------- - -- MTBDWT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks - * @{ - */ - -/*! @name CTRL - DWT Control Register */ -/*! @{ */ -#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) -#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) -#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) -#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) -#define MTBDWT_CTRL_NUMCMP_SHIFT (28U) -#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) -/*! @} */ - -/*! @name COMP - DWT Comparator Register */ -/*! @{ */ -#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) -#define MTBDWT_COMP_COMP_SHIFT (0U) -#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) -/*! @} */ - -/* The count of MTBDWT_COMP */ -#define MTBDWT_COMP_COUNT (2U) - -/*! @name MASK - DWT Comparator Mask Register */ -/*! @{ */ -#define MTBDWT_MASK_MASK_MASK (0x1FU) -#define MTBDWT_MASK_MASK_SHIFT (0U) -#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) -/*! @} */ - -/* The count of MTBDWT_MASK */ -#define MTBDWT_MASK_COUNT (2U) - -/*! @name FCT - DWT Comparator Function Register 0..DWT Comparator Function Register 1 */ -/*! @{ */ -#define MTBDWT_FCT_FUNCTION_MASK (0xFU) -#define MTBDWT_FCT_FUNCTION_SHIFT (0U) -/*! FUNCTION - Function - * 0b0000..Disabled. - * 0b0001-0b0011..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. - * 0b0100..Instruction fetch. - * 0b0101..Data operand read. - * 0b0110..Data operand write. - * 0b0111..Data operand (read + write). - * 0b1000-0b1111..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. - */ -#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) -#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) -#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) -/*! DATAVMATCH - Data Value Match - * 0b0..Perform address comparison. - * 0b1..Perform data value comparison. - */ -#define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) -#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) -#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) -/*! DATAVSIZE - Data Value Size - * 0b00..Byte. - * 0b01..Halfword. - * 0b10..Word. - * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. - */ -#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) -#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) -#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) -#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) -#define MTBDWT_FCT_MATCHED_MASK (0x1000000U) -#define MTBDWT_FCT_MATCHED_SHIFT (24U) -/*! MATCHED - Comparator match - * 0b0..No match. - * 0b1..Match occurred. - */ -#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) -/*! @} */ - -/* The count of MTBDWT_FCT */ -#define MTBDWT_FCT_COUNT (2U) - -/*! @name TBCTRL - DWT Trace Buffer Control Register */ -/*! @{ */ -#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) -#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) -/*! ACOMP0 - Action based on Comparator 0 match - * 0b0..Trigger TSTOP based on the assertion of FCT0[MATCHED]. - * 0b1..Trigger TSTART based on the assertion of FCT0[MATCHED]. - */ -#define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) -#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) -#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) -/*! ACOMP1 - Action based on Comparator 1 match - * 0b0..Trigger TSTOP based on the assertion of FCT1[MATCHED]. - * 0b1..Trigger TSTART based on the assertion of FCT1[MATCHED]. - */ -#define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) -#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) -#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) -#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) -/*! @} */ - -/*! @name DEVICECFG - Device Configuration Register */ -/*! @{ */ -#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) -#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) -#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) -/*! @} */ - -/*! @name DEVICETYPID - Device Type Identifier Register */ -/*! @{ */ -#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) -#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) -#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) -/*! @} */ - -/*! @name PERIPHID4 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID5 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID6 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID7 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID0 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID1 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID2 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID3 - Peripheral ID Register */ -/*! @{ */ -#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) -#define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) -/*! @} */ - -/*! @name COMPID - Component ID Register */ -/*! @{ */ -#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define MTBDWT_COMPID_COMPID_SHIFT (0U) -#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) -/*! @} */ - -/* The count of MTBDWT_COMPID */ -#define MTBDWT_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group MTBDWT_Register_Masks */ - - -/* MTBDWT - Peripheral instance base addresses */ -/** Peripheral MTBDWT base address */ -#define MTBDWT_BASE (0xF0001000u) -/** Peripheral MTBDWT base pointer */ -#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) -/** Array initializer of MTBDWT peripheral base addresses */ -#define MTBDWT_BASE_ADDRS { MTBDWT_BASE } -/** Array initializer of MTBDWT peripheral base pointers */ -#define MTBDWT_BASE_PTRS { MTBDWT } - -/*! - * @} - */ /* end of group MTBDWT_Peripheral_Access_Layer */ - -/*! - * @brief Core boot mode. - */ -typedef enum _mu_core_boot_mode -{ - kMU_CoreBootFromPflashBase = 0x00U, /*!< Boot from pflash base. */ - kMU_CoreBootFromCore0RamBase = 0x02U, /*!< Boot from RI5CY RAM base. */ -} mu_core_boot_mode_t; -/*! - * @brief Power mode on the other side definition. - */ -typedef enum _mu_power_mode -{ - kMU_PowerModeRun = 0x00U, /*!< Run mode. */ - kMU_PowerModeCoo = 0x01U, /*!< COO mode. */ - kMU_PowerModeWait = 0x02U, /*!< WAIT mode. */ - kMU_PowerModeStop = 0x03U, /*!< STOP/VLPS mode. */ - kMU_PowerModeDsm = 0x04U /*!< DSM: LLS/VLLS mode. */ -} mu_power_mode_t; - - -/* ---------------------------------------------------------------------------- - -- MU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer - * @{ - */ - -/** MU - Register Layout Typedef */ -typedef struct { - __I uint32_t VER; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[24]; - __IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[16]; - __IO uint32_t SR; /**< Status Register, offset: 0x60 */ - __IO uint32_t CR; /**< Control Register, offset: 0x64 */ - __IO uint32_t CCR; /**< Core Control Register, offset: 0x68 */ -} MU_Type; - -/* ---------------------------------------------------------------------------- - -- MU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MU_Register_Masks MU Register Masks - * @{ - */ - -/*! @name VER - Version ID Register */ -/*! @{ */ -#define MU_VER_FEATURE_MASK (0xFFFFU) -#define MU_VER_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB. - * 0b000000000000xx1x..RAIP/RAIE register bits are implemented. - * 0b000000000000xxx0..Standard features implemented - */ -#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) -#define MU_VER_MINOR_MASK (0xFF0000U) -#define MU_VER_MINOR_SHIFT (16U) -#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) -#define MU_VER_MAJOR_MASK (0xFF000000U) -#define MU_VER_MAJOR_SHIFT (24U) -#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) -/*! @} */ - -/*! @name PAR - Parameter Register */ -/*! @{ */ -#define MU_PAR_PARAMETER_MASK (0xFFFFFFFFU) -#define MU_PAR_PARAMETER_SHIFT (0U) -#define MU_PAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK) -/*! @} */ - -/*! @name TR - Transmit Register */ -/*! @{ */ -#define MU_TR_DATA_MASK (0xFFFFFFFFU) -#define MU_TR_DATA_SHIFT (0U) -#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK) -/*! @} */ - -/* The count of MU_TR */ -#define MU_TR_COUNT (4U) - -/*! @name RR - Receive Register */ -/*! @{ */ -#define MU_RR_DATA_MASK (0xFFFFFFFFU) -#define MU_RR_DATA_SHIFT (0U) -#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK) -/*! @} */ - -/* The count of MU_RR */ -#define MU_RR_COUNT (4U) - -/*! @name SR - Status Register */ -/*! @{ */ -#define MU_SR_Fn_MASK (0x7U) -#define MU_SR_Fn_SHIFT (0U) -/*! Fn - Fn - * 0b000..Fn bit in the MUA CR register is written 0 (default). - * 0b001..Fn bit in the MUA CR register is written 1. - */ -#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) -#define MU_SR_NMIC_MASK (0x8U) -#define MU_SR_NMIC_SHIFT (3U) -/*! NMIC - NMIC - * 0b0..Default - * 0b1..Writing "1" clears the NMI bit in the MUA CR register. - */ -#define MU_SR_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK) -#define MU_SR_EP_MASK (0x10U) -#define MU_SR_EP_SHIFT (4U) -/*! EP - EP - * 0b0..The MUB side event is not pending (default). - * 0b1..The MUB side event is pending. - */ -#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) -#define MU_SR_HRIP_MASK (0x80U) -#define MU_SR_HRIP_SHIFT (7U) -/*! HRIP - HRIP - * 0b0..MUA didn't issue hardware reset to Processor B - * 0b1..MUA had initiated a hardware reset to Processor B through HR bit. - */ -#define MU_SR_HRIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_HRIP_SHIFT)) & MU_SR_HRIP_MASK) -#define MU_SR_FUP_MASK (0x100U) -#define MU_SR_FUP_SHIFT (8U) -/*! FUP - FUP - * 0b0..No flags updated, initiated by the MUB, in progress (default) - * 0b1..MUB initiated flags update, processing - */ -#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) -#define MU_SR_RDIP_MASK (0x200U) -#define MU_SR_RDIP_SHIFT (9U) -/*! RDIP - RDIP - * 0b0..Processor A did not exit reset - * 0b1..Processor A exited from reset - */ -#define MU_SR_RDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK) -#define MU_SR_RAIP_MASK (0x400U) -#define MU_SR_RAIP_SHIFT (10U) -/*! RAIP - RAIP - * 0b0..Processor A did not enter reset - * 0b1..Processor A entered reset - */ -#define MU_SR_RAIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK) -#define MU_SR_MURIP_MASK (0x800U) -#define MU_SR_MURIP_SHIFT (11U) -/*! MURIP - MURIP - * 0b0..Processor A did not issue MU reset - * 0b1..Processor A issued MU reset - */ -#define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) -#define MU_SR_PM_MASK (0x7000U) -#define MU_SR_PM_SHIFT (12U) -/*! PM - PM - * 0b000..The MUA processor is in Run Mode. - * 0b001..The MUA processor is in COO Mode. - * 0b010..The MUA processor is in WAIT Mode. - * 0b011..The MUA processor is in STOP/VLPS Mode. - * 0b100..The MUA processor is in LLS/VLLS Mode. - */ -#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK) -#define MU_SR_TEn_MASK (0xF00000U) -#define MU_SR_TEn_SHIFT (20U) -/*! TEn - TEn - * 0b0000..MUB TRn register is not empty. - * 0b0001..MUB TRn register is empty (default). - */ -#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) -#define MU_SR_RFn_MASK (0xF000000U) -#define MU_SR_RFn_SHIFT (24U) -/*! RFn - RFn - * 0b0000..MUB RRn register is not full (default). - * 0b0001..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB. - */ -#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) -#define MU_SR_GIPn_MASK (0xF0000000U) -#define MU_SR_GIPn_SHIFT (28U) -/*! GIPn - GIPn - * 0b0000..MUB general purpose interrupt n is not pending. (default) - * 0b0001..MUB general purpose interrupt n is pending. - */ -#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define MU_CR_Fn_MASK (0x7U) -#define MU_CR_Fn_SHIFT (0U) -/*! Fn - Fn - * 0b000..Clears the Fn bit in the SR register. - * 0b001..Sets the Fn bit in the SR register. - */ -#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) -#define MU_CR_NMI_MASK (0x8U) -#define MU_CR_NMI_SHIFT (3U) -/*! NMI - NMI - * 0b0..Non-maskable interrupt is not issued to the Processor A by the Processor B (default). - * 0b1..Non-maskable interrupt is issued to the Processor A by the Processor B. - */ -#define MU_CR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK) -#define MU_CR_MUR_MASK (0x20U) -#define MU_CR_MUR_SHIFT (5U) -/*! MUR - MUR - * 0b0..N/A. Self clearing bit (default). - * 0b1..Asserts the MU reset. - */ -#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) -#define MU_CR_RDIE_MASK (0x40U) -#define MU_CR_RDIE_SHIFT (6U) -/*! RDIE - RDIE - * 0b0..Disables Processor B General Purpose Interrupt 3 request due to Processor A reset de-assertion. - * 0b1..Enables Processor B General Purpose Interrupt 3 request due to Processor A reset de-assertion. - */ -#define MU_CR_RDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK) -#define MU_CR_HRIE_MASK (0x80U) -#define MU_CR_HRIE_SHIFT (7U) -/*! HRIE - Processor B hardware reset interrupt enable - * 0b0..Disables Processor B General Purpose Interrupt 3 request due to Processor A issued HR to Processor B. - * 0b1..Enables Processor B General Purpose Interrupt 3 request due to Processor A issued HR to Processor B. - */ -#define MU_CR_HRIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRIE_SHIFT)) & MU_CR_HRIE_MASK) -#define MU_CR_MURIE_MASK (0x800U) -#define MU_CR_MURIE_SHIFT (11U) -/*! MURIE - MURIE - * 0b0..Disables Processor B-side General Purpose Interrupt 3 request due to MU reset issued by MUA. - * 0b1..Enables Processor B-side General Purpose Interrupt 3 request due to MU reset issued by MUA. - */ -#define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) -#define MU_CR_RAIE_MASK (0x1000U) -#define MU_CR_RAIE_SHIFT (12U) -/*! RAIE - RAIE - * 0b0..Disables Processor B-side General Purpose Interrupt 3 request due to Processor A reset assertion. - * 0b1..Enables Processor B-side General Purpose Interrupt 3 request due to Processor A reset assertion. - */ -#define MU_CR_RAIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK) -#define MU_CR_GIRn_MASK (0xF0000U) -#define MU_CR_GIRn_SHIFT (16U) -/*! GIRn - GIRn - * 0b0000..MUB General Interrupt n is not requested to the MUA (default). - * 0b0001..MUB General Interrupt n is requested to the MUA. - */ -#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) -#define MU_CR_TIEn_MASK (0xF00000U) -#define MU_CR_TIEn_SHIFT (20U) -/*! TIEn - TIEn - * 0b0000..Disables MUB Transmit Interrupt n. (default) - * 0b0001..Enables MUB Transmit Interrupt n. - */ -#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) -#define MU_CR_RIEn_MASK (0xF000000U) -#define MU_CR_RIEn_SHIFT (24U) -/*! RIEn - RIEn - * 0b0000..Disables MUB Receive Interrupt n. (default) - * 0b0001..Enables MUB Receive Interrupt n. - */ -#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) -#define MU_CR_GIEn_MASK (0xF0000000U) -#define MU_CR_GIEn_SHIFT (28U) -/*! GIEn - GIEn - * 0b0000..Disables MUB General Interrupt n. (default) - * 0b0001..Enables MUB General Interrupt n. - */ -#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) -/*! @} */ - -/*! @name CCR - Core Control Register */ -/*! @{ */ -#define MU_CCR_HR_MASK (0x1U) -#define MU_CCR_HR_SHIFT (0U) -/*! HR - HR - * 0b0..De-assert Hardware reset to the Processor A. (default) - * 0b1..Assert Hardware reset to the Processor A. - */ -#define MU_CCR_HR(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_HR_SHIFT)) & MU_CCR_HR_MASK) -#define MU_CCR_HRM_MASK (0x2U) -#define MU_CCR_HRM_SHIFT (1U) -/*! HRM - When set, HR bit in MUA CCR has no effect - * 0b0..HR bit in MUA CCR is not masked, enables the hardware reset to the Processor B (default after hardware reset). - * 0b1..HR bit in MUA CCR is masked, disables the hardware reset request to the Processor B. - */ -#define MU_CCR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_HRM_SHIFT)) & MU_CCR_HRM_MASK) -#define MU_CCR_RSTH_MASK (0x4U) -#define MU_CCR_RSTH_SHIFT (2U) -/*! RSTH - Processor A Reset Hold - * 0b0..Release Processor A from reset - * 0b1..Hold Processor A in reset - */ -#define MU_CCR_RSTH(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_RSTH_SHIFT)) & MU_CCR_RSTH_MASK) -#define MU_CCR_CLKE_MASK (0x8U) -#define MU_CCR_CLKE_SHIFT (3U) -/*! CLKE - MUA clock enable - * 0b0..MUA platform clock gated when MUA-side enters a stop mode. - * 0b1..MUA platform clock kept running after MUA-side enters a stop mode, until MUB also enters a stop mode. - */ -#define MU_CCR_CLKE(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_CLKE_SHIFT)) & MU_CCR_CLKE_MASK) -#define MU_CCR_BOOT_MASK (0x30U) -#define MU_CCR_BOOT_SHIFT (4U) -/*! BOOT - Slave Processor A Boot Config. - * 0b00..Boot from Pflash base - * 0b01..Reserved - * 0b10..Boot from CM4 RAM base - * 0b11..Reserved - */ -#define MU_CCR_BOOT(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR_BOOT_SHIFT)) & MU_CCR_BOOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MU_Register_Masks */ - - -/* MU - Peripheral instance base addresses */ -/** Peripheral MUB base address */ -#define MUB_BASE (0x41024000u) -/** Peripheral MUB base pointer */ -#define MUB ((MU_Type *)MUB_BASE) -/** Array initializer of MU peripheral base addresses */ -#define MU_BASE_ADDRS { MUB_BASE } -/** Array initializer of MU peripheral base pointers */ -#define MU_BASE_PTRS { MUB } -/** Interrupt vectors for the MU peripheral type */ -#define MU_IRQS { MUB_IRQn } - -/*! - * @} - */ /* end of group MU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PCC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer - * @{ - */ - -/** PCC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CLKCFG[130]; /**< PCC MSCM Register..PCC EXT_CLK Register, array offset: 0x0, array step: 0x4 */ -} PCC_Type; - -/* ---------------------------------------------------------------------------- - -- PCC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PCC_Register_Masks PCC Register Masks - * @{ - */ - -/*! @name CLKCFG - PCC MSCM Register..PCC EXT_CLK Register */ -/*! @{ */ -#define PCC_CLKCFG_PCD_MASK (0x7U) -#define PCC_CLKCFG_PCD_SHIFT (0U) -/*! PCD - Peripheral Clock Divider Select - * 0b000..Divide by 1. - * 0b001..Divide by 2. - * 0b010..Divide by 3. - * 0b011..Divide by 4. - * 0b100..Divide by 5. - * 0b101..Divide by 6. - * 0b110..Divide by 7. - * 0b111..Divide by 8. - */ -#define PCC_CLKCFG_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK) -#define PCC_CLKCFG_FRAC_MASK (0x8U) -#define PCC_CLKCFG_FRAC_SHIFT (3U) -/*! FRAC - Peripheral Clock Divider Fraction - * 0b0..Fractional value is 0. - * 0b1..Fractional value is 1. - */ -#define PCC_CLKCFG_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK) -#define PCC_CLKCFG_PCS_MASK (0x7000000U) -#define PCC_CLKCFG_PCS_SHIFT (24U) -/*! PCS - Peripheral Clock Source Select - * 0b000..Clock is off. An external clock can be enabled for this peripheral. - * 0b001..Clock option 1 - * 0b010..Clock option 2 - * 0b011..Clock option 3 - * 0b100..Clock option 4 - * 0b101..Clock option 5 - * 0b110..Clock option 6 - * 0b111..Clock option 7 - */ -#define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK) -#define PCC_CLKCFG_INUSE_MASK (0x20000000U) -#define PCC_CLKCFG_INUSE_SHIFT (29U) -/*! INUSE - In use flag - * 0b0..Peripheral is not being used. - * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. - */ -#define PCC_CLKCFG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK) -#define PCC_CLKCFG_CGC_MASK (0x40000000U) -#define PCC_CLKCFG_CGC_SHIFT (30U) -/*! CGC - Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled. The current clock selection and divider options are locked. - */ -#define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK) -#define PCC_CLKCFG_PR_MASK (0x80000000U) -#define PCC_CLKCFG_PR_SHIFT (31U) -/*! PR - Present - * 0b0..Peripheral is not present. - * 0b1..Peripheral is present. - */ -#define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK) -/*! @} */ - -/* The count of PCC_CLKCFG */ -#define PCC_CLKCFG_COUNT (130U) - - -/*! - * @} - */ /* end of group PCC_Register_Masks */ - - -/* PCC - Peripheral instance base addresses */ -/** Peripheral PCC0 base address */ -#define PCC0_BASE (0x4002B000u) -/** Peripheral PCC0 base pointer */ -#define PCC0 ((PCC_Type *)PCC0_BASE) -/** Peripheral PCC1 base address */ -#define PCC1_BASE (0x41027000u) -/** Peripheral PCC1 base pointer */ -#define PCC1 ((PCC_Type *)PCC1_BASE) -/** Array initializer of PCC peripheral base addresses */ -#define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE } -/** Array initializer of PCC peripheral base pointers */ -#define PCC_BASE_PTRS { PCC0, PCC1 } -#define PCC_INSTANCE_MASK (0xFu) -#define PCC_INSTANCE_SHIFT (12u) -#define PCC_PERIPHERAL_MASK (0xFFFu) -#define PCC_PERIPHERAL_SHIFT (0u) -#define PCC_INSTANCE_0 (0u) -#define PCC_INSTANCE_1 (1u) - -#define PCC_MSCM_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 1U) -#define PCC_AXBS0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 4U) -#define PCC_DMA0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U) -#define PCC_FLEXBUS_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 12U) -#define PCC_XRDC_MGR_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 20U) -#define PCC0_XRDC_PAC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U) -#define PCC0_XRDC_MRC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U) -#define PCC_SEMA42_0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U) -#define PCC_DMAMUX0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U) -#define PCC_EWM_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U) -#define PCC_MUA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37U) -#define PCC_CRC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 47U) -#define PCC_LPIT0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48U) -#define PCC_TPM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U) -#define PCC_TPM1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U) -#define PCC_TPM2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U) -#define PCC_EMVSIM0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56U) -#define PCC_FLEXIO0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 57U) -#define PCC_LPI2C0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 58U) -#define PCC_LPI2C1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 59U) -#define PCC_LPI2C2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60U) -#define PCC_I2S0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61U) -#define PCC_USDHC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62U) -#define PCC_LPSPI0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 63U) -#define PCC_LPSPI1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64U) -#define PCC_LPSPI2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65U) -#define PCC_LPUART0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66U) -#define PCC_LPUART1_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 67U) -#define PCC_LPUART2_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68U) -#define PCC_USB0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69U) -#define PCC_PORTA_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70U) -#define PCC_PORTB_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 71U) -#define PCC_PORTC_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 72U) -#define PCC_PORTD_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 73U) -#define PCC_ADC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74U) -#define PCC_LPDAC0_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 76U) -#define PCC_VREF_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 77U) -#define PCC_TRACE_INDEX ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U) -#define PCC_DMA1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U) -#define PCC_GPIOE_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 15U) -#define PCC1_XRDC_PAC_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U) -#define PCC1_XRDC_MRC_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U) -#define PCC_SEMA42_1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U) -#define PCC_DMAMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U) -#define PCC_INTMUX1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U) -#define PCC_MUB_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36U) -#define PCC_CAU3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 40U) -#define PCC_TRNG_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 41U) -#define PCC_LPIT1_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 42U) -#define PCC_TPM3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45U) -#define PCC_LPI2C3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46U) -#define PCC_LPSPI3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U) -#define PCC_LPUART3_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U) -#define PCC_PORTE_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U) -#define PCC_MTB_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U) -#define PCC_EXT_CLK_INDEX ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 129U) -#define PCC_MSCM (PCC0->CLKCFG[1]) -#define PCC_AXBS0 (PCC0->CLKCFG[4]) -#define PCC_DMA0 (PCC0->CLKCFG[8]) -#define PCC_FLEXBUS (PCC0->CLKCFG[12]) -#define PCC_XRDC_MGR (PCC0->CLKCFG[20]) -#define PCC0_XRDC_PAC (PCC0->CLKCFG[22]) -#define PCC0_XRDC_MRC (PCC0->CLKCFG[23]) -#define PCC_SEMA42_0 (PCC0->CLKCFG[27]) -#define PCC_DMAMUX0 (PCC0->CLKCFG[33]) -#define PCC_EWM (PCC0->CLKCFG[34]) -#define PCC_MUA (PCC0->CLKCFG[37]) -#define PCC_CRC0 (PCC0->CLKCFG[47]) -#define PCC_LPIT0 (PCC0->CLKCFG[48]) -#define PCC_TPM0 (PCC0->CLKCFG[53]) -#define PCC_TPM1 (PCC0->CLKCFG[54]) -#define PCC_TPM2 (PCC0->CLKCFG[55]) -#define PCC_EMVSIM0 (PCC0->CLKCFG[56]) -#define PCC_FLEXIO0 (PCC0->CLKCFG[57]) -#define PCC_LPI2C0 (PCC0->CLKCFG[58]) -#define PCC_LPI2C1 (PCC0->CLKCFG[59]) -#define PCC_LPI2C2 (PCC0->CLKCFG[60]) -#define PCC_I2S0 (PCC0->CLKCFG[61]) -#define PCC_USDHC0 (PCC0->CLKCFG[62]) -#define PCC_LPSPI0 (PCC0->CLKCFG[63]) -#define PCC_LPSPI1 (PCC0->CLKCFG[64]) -#define PCC_LPSPI2 (PCC0->CLKCFG[65]) -#define PCC_LPUART0 (PCC0->CLKCFG[66]) -#define PCC_LPUART1 (PCC0->CLKCFG[67]) -#define PCC_LPUART2 (PCC0->CLKCFG[68]) -#define PCC_USB0 (PCC0->CLKCFG[69]) -#define PCC_PORTA (PCC0->CLKCFG[70]) -#define PCC_PORTB (PCC0->CLKCFG[71]) -#define PCC_PORTC (PCC0->CLKCFG[72]) -#define PCC_PORTD (PCC0->CLKCFG[73]) -#define PCC_ADC0 (PCC0->CLKCFG[74]) -#define PCC_LPDAC0 (PCC0->CLKCFG[76]) -#define PCC_VREF (PCC0->CLKCFG[77]) -#define PCC_TRACE (PCC0->CLKCFG[128]) -#define PCC_DMA1 (PCC1->CLKCFG[8]) -#define PCC_GPIOE (PCC1->CLKCFG[15]) -#define PCC1_XRDC_PAC (PCC1->CLKCFG[22]) -#define PCC1_XRDC_MRC (PCC1->CLKCFG[23]) -#define PCC_SEMA42_1 (PCC1->CLKCFG[27]) -#define PCC_DMAMUX1 (PCC1->CLKCFG[33]) -#define PCC_INTMUX1 (PCC1->CLKCFG[34]) -#define PCC_MUB (PCC1->CLKCFG[36]) -#define PCC_CAU3 (PCC1->CLKCFG[40]) -#define PCC_TRNG (PCC1->CLKCFG[41]) -#define PCC_LPIT1 (PCC1->CLKCFG[42]) -#define PCC_TPM3 (PCC1->CLKCFG[45]) -#define PCC_LPI2C3 (PCC1->CLKCFG[46]) -#define PCC_LPSPI3 (PCC1->CLKCFG[53]) -#define PCC_LPUART3 (PCC1->CLKCFG[54]) -#define PCC_PORTE (PCC1->CLKCFG[55]) -#define PCC_MTB (PCC1->CLKCFG[128]) -#define PCC_EXT_CLK (PCC1->CLKCFG[129]) - - -/*! - * @} - */ /* end of group PCC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PORT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer - * @{ - */ - -/** PORT - Register Layout Typedef */ -typedef struct { - __IO uint32_t PCR[32]; /**< Pin Control Register 0..Pin Control Register 30, array offset: 0x0, array step: 0x4 */ - __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ - __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ - __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ - __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ - uint8_t RESERVED_0[16]; - __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ - uint8_t RESERVED_1[28]; - __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ - __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ - __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ -} PORT_Type; - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/*! @name PCR - Pin Control Register 0..Pin Control Register 30 */ -/*! @{ */ -#define PORT_PCR_PS_MASK (0x1U) -#define PORT_PCR_PS_SHIFT (0U) -/*! PS - Pull Select - * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. - * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. - */ -#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) -#define PORT_PCR_PE_MASK (0x2U) -#define PORT_PCR_PE_SHIFT (1U) -/*! PE - Pull Enable - * 0b0..Internal pull resistor is not enabled on the corresponding pin. - * 0b1..Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input. - */ -#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) -#define PORT_PCR_SRE_MASK (0x4U) -#define PORT_PCR_SRE_SHIFT (2U) -/*! SRE - Slew Rate Enable - * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. - * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. - */ -#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) -#define PORT_PCR_PFE_MASK (0x10U) -#define PORT_PCR_PFE_SHIFT (4U) -/*! PFE - Passive Filter Enable - * 0b0..Passive input filter is disabled on the corresponding pin. - * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. - */ -#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) -#define PORT_PCR_ODE_MASK (0x20U) -#define PORT_PCR_ODE_SHIFT (5U) -/*! ODE - Open Drain Enable - * 0b0..Open drain output is disabled on the corresponding pin. - * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. - */ -#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) -#define PORT_PCR_DSE_MASK (0x40U) -#define PORT_PCR_DSE_SHIFT (6U) -/*! DSE - Drive Strength Enable - * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. - * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. - */ -#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) -#define PORT_PCR_MUX_MASK (0x700U) -#define PORT_PCR_MUX_SHIFT (8U) -/*! MUX - Pin Mux Control - * 0b000..Pin disabled (Alternative 0) (analog). - * 0b001..Alternative 1 (GPIO). - * 0b010..Alternative 2 (chip-specific). - * 0b011..Alternative 3 (chip-specific). - * 0b100..Alternative 4 (chip-specific). - * 0b101..Alternative 5 (chip-specific). - * 0b110..Alternative 6 (chip-specific). - * 0b111..Alternative 7 (chip-specific). - */ -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) -#define PORT_PCR_LK_MASK (0x8000U) -#define PORT_PCR_LK_SHIFT (15U) -/*! LK - Lock Register - * 0b0..Pin Control Register is not locked. - * 0b1..Pin Control Register is locked and cannot be updated until the next system reset. - */ -#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) -#define PORT_PCR_IRQC_MASK (0xF0000U) -#define PORT_PCR_IRQC_SHIFT (16U) -/*! IRQC - Interrupt Configuration - * 0b0000..Interrupt Status Flag (ISF) is disabled. - * 0b0001..ISF flag and DMA request on rising edge. - * 0b0010..ISF flag and DMA request on falling edge. - * 0b0011..ISF flag and DMA request on either edge. - * 0b0100..Reserved. - * 0b0101..Flag sets on rising edge. - * 0b0110..Flag sets on falling edge. - * 0b0111..Flag sets on either edge. - * 0b1000..ISF flag and Interrupt when logic 0. - * 0b1001..ISF flag and Interrupt on rising-edge. - * 0b1010..ISF flag and Interrupt on falling-edge. - * 0b1011..ISF flag and Interrupt on either edge. - * 0b1100..ISF flag and Interrupt when logic 1. - * 0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] - * 0b1110..Enable active low trigger output, flag is disabled. - * 0b1111..Reserved. - */ -#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) -#define PORT_PCR_ISF_MASK (0x1000000U) -#define PORT_PCR_ISF_SHIFT (24U) -/*! ISF - Interrupt Status Flag - * 0b0..Configured interrupt is not detected. - * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. - */ -#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) -/*! @} */ - -/* The count of PORT_PCR */ -#define PORT_PCR_COUNT (32U) - -/*! @name GPCLR - Global Pin Control Low Register */ -/*! @{ */ -#define PORT_GPCLR_GPWD_MASK (0xFFFFU) -#define PORT_GPCLR_GPWD_SHIFT (0U) -#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) -#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCLR_GPWE_SHIFT (16U) -#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) -/*! @} */ - -/*! @name GPCHR - Global Pin Control High Register */ -/*! @{ */ -#define PORT_GPCHR_GPWD_MASK (0xFFFFU) -#define PORT_GPCHR_GPWD_SHIFT (0U) -#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) -#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) -#define PORT_GPCHR_GPWE_SHIFT (16U) -#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) -/*! @} */ - -/*! @name GICLR - Global Interrupt Control Low Register */ -/*! @{ */ -#define PORT_GICLR_GIWE_MASK (0xFFFFU) -#define PORT_GICLR_GIWE_SHIFT (0U) -#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) -#define PORT_GICLR_GIWD_MASK (0xFFFF0000U) -#define PORT_GICLR_GIWD_SHIFT (16U) -#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) -/*! @} */ - -/*! @name GICHR - Global Interrupt Control High Register */ -/*! @{ */ -#define PORT_GICHR_GIWE_MASK (0xFFFFU) -#define PORT_GICHR_GIWE_SHIFT (0U) -#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) -#define PORT_GICHR_GIWD_MASK (0xFFFF0000U) -#define PORT_GICHR_GIWD_SHIFT (16U) -#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) -/*! @} */ - -/*! @name ISFR - Interrupt Status Flag Register */ -/*! @{ */ -#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) -#define PORT_ISFR_ISF_SHIFT (0U) -#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) -/*! @} */ - -/*! @name DFER - Digital Filter Enable Register */ -/*! @{ */ -#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) -#define PORT_DFER_DFE_SHIFT (0U) -#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) -/*! @} */ - -/*! @name DFCR - Digital Filter Clock Register */ -/*! @{ */ -#define PORT_DFCR_CS_MASK (0x1U) -#define PORT_DFCR_CS_SHIFT (0U) -/*! CS - Clock Source - * 0b0..Digital filters are clocked by the bus clock. - * 0b1..Digital filters are clocked by the 8 clock. - */ -#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) -/*! @} */ - -/*! @name DFWR - Digital Filter Width Register */ -/*! @{ */ -#define PORT_DFWR_FILT_MASK (0x1FU) -#define PORT_DFWR_FILT_SHIFT (0U) -#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PORT_Register_Masks */ - - -/* PORT - Peripheral instance base addresses */ -/** Peripheral PORTA base address */ -#define PORTA_BASE (0x40046000u) -/** Peripheral PORTA base pointer */ -#define PORTA ((PORT_Type *)PORTA_BASE) -/** Peripheral PORTB base address */ -#define PORTB_BASE (0x40047000u) -/** Peripheral PORTB base pointer */ -#define PORTB ((PORT_Type *)PORTB_BASE) -/** Peripheral PORTC base address */ -#define PORTC_BASE (0x40048000u) -/** Peripheral PORTC base pointer */ -#define PORTC ((PORT_Type *)PORTC_BASE) -/** Peripheral PORTD base address */ -#define PORTD_BASE (0x40049000u) -/** Peripheral PORTD base pointer */ -#define PORTD ((PORT_Type *)PORTD_BASE) -/** Peripheral PORTE base address */ -#define PORTE_BASE (0x41037000u) -/** Peripheral PORTE base pointer */ -#define PORTE ((PORT_Type *)PORTE_BASE) -/** Array initializer of PORT peripheral base addresses */ -#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } -/** Array initializer of PORT peripheral base pointers */ -#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } -/** Interrupt vectors for the PORT peripheral type */ -#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } - -/*! - * @} - */ /* end of group PORT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ROM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer - * @{ - */ - -/** ROM - Register Layout Typedef */ -typedef struct { - __I uint32_t ENTRY[4]; /**< Entry, array offset: 0x0, array step: 0x4 */ - __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0x10 */ - uint8_t RESERVED_0[4024]; - __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ - __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ - __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ - __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ - __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ - __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ - __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ - __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ - __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ - __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ -} ROM_Type; - -/* ---------------------------------------------------------------------------- - -- ROM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Register_Masks ROM Register Masks - * @{ - */ - -/*! @name ENTRY - Entry */ -/*! @{ */ -#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) -#define ROM_ENTRY_ENTRY_SHIFT (0U) -#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) -/*! @} */ - -/* The count of ROM_ENTRY */ -#define ROM_ENTRY_COUNT (4U) - -/*! @name TABLEMARK - End of Table Marker Register */ -/*! @{ */ -#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) -#define ROM_TABLEMARK_MARK_SHIFT (0U) -#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) -/*! @} */ - -/*! @name SYSACCESS - System Access Register */ -/*! @{ */ -#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) -#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) -#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) -/*! @} */ - -/*! @name PERIPHID4 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID4_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID5 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID5_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID6 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID6_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID7 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID7_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID0 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID0_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID1 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID1_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID2 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID2_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) -/*! @} */ - -/*! @name PERIPHID3 - Peripheral ID Register */ -/*! @{ */ -#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) -#define ROM_PERIPHID3_PERIPHID_SHIFT (0U) -#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) -/*! @} */ - -/*! @name COMPID - Component ID Register */ -/*! @{ */ -#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) -#define ROM_COMPID_COMPID_SHIFT (0U) -#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) -/*! @} */ - -/* The count of ROM_COMPID */ -#define ROM_COMPID_COUNT (4U) - - -/*! - * @} - */ /* end of group ROM_Register_Masks */ - - -/* ROM - Peripheral instance base addresses */ -/** Peripheral ROM base address */ -#define ROM_BASE (0xF0002000u) -/** Peripheral ROM base pointer */ -#define ROM ((ROM_Type *)ROM_BASE) -/** Array initializer of ROM peripheral base addresses */ -#define ROM_BASE_ADDRS { ROM_BASE } -/** Array initializer of ROM peripheral base pointers */ -#define ROM_BASE_PTRS { ROM } - -/*! - * @} - */ /* end of group ROM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer - * @{ - */ - -/** RSIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Radio System Control, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t MISC; /**< Radio Miscellaneous, offset: 0x10 */ - __IO uint32_t POWER; /**< RSIM Power Control, offset: 0x14 */ - __IO uint32_t SW_CONFIG; /**< Radio Software Configuration, offset: 0x18 */ - uint8_t RESERVED_1[228]; - __I uint32_t DSM_TIMER; /**< Deep Sleep Timer, offset: 0x100 */ - __IO uint32_t DSM_CONTROL; /**< Deep Sleep Timer Control, offset: 0x104 */ - __IO uint32_t DSM_WAKEUP; /**< Deep Sleep Wakeup Sequence, offset: 0x108 */ - __I uint32_t WOR_DURATION; /**< WOR Deep Sleep Duration, offset: 0x10C */ - __IO uint32_t WOR_WAKE; /**< WOR Deep Sleep Wake Time, offset: 0x110 */ - uint8_t RESERVED_2[8]; - __IO uint32_t MAN_SLEEP; /**< MAN Deep Sleep Time, offset: 0x11C */ - __IO uint32_t MAN_WAKE; /**< MAN Deep Sleep Wake Time, offset: 0x120 */ - __IO uint32_t RF_OSC_CTRL; /**< Radio Oscillator Control, offset: 0x124 */ - __IO uint32_t ANA_TEST; /**< Radio Analog Test Registers, offset: 0x128 */ - __IO uint32_t ANA_TRIM; /**< Radio Analog Trim Registers, offset: 0x12C */ -} RSIM_Type; - -/* ---------------------------------------------------------------------------- - -- RSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RSIM_Register_Masks RSIM Register Masks - * @{ - */ - -/*! @name CONTROL - Radio System Control */ -/*! @{ */ -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK (0x1U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT (0U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK (0x2U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT (1U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK (0x10U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT (4U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK (0x20U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT (5U) -#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK) -#define RSIM_CONTROL_RF_OSC_EN_MASK (0x100U) -#define RSIM_CONTROL_RF_OSC_EN_SHIFT (8U) -#define RSIM_CONTROL_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U) -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U) -/*! RADIO_GASKET_BYPASS_OVRD - Radio Gasket Bypass Override - * 0b0..XCVR and Link Layer Register Clock is the RF Ref Osc Clock - * 0b1..XCVR and Link Layer Register Clock is the SoC IPG Clock - */ -#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK (0x4000U) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT (14U) -#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT)) & RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK (0x8000U) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT (15U) -#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK (0x10000U) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT (16U) -#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK (0x40000U) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT (18U) -#define RSIM_CONTROL_IPP_OBE_RF_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK (0x80000U) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT (19U) -#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK) -#define RSIM_CONTROL_BLE_DSM_EXIT_MASK (0x100000U) -#define RSIM_CONTROL_BLE_DSM_EXIT_SHIFT (20U) -#define RSIM_CONTROL_BLE_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_DSM_EXIT_SHIFT)) & RSIM_CONTROL_BLE_DSM_EXIT_MASK) -#define RSIM_CONTROL_WOR_DSM_EXIT_MASK (0x200000U) -#define RSIM_CONTROL_WOR_DSM_EXIT_SHIFT (21U) -#define RSIM_CONTROL_WOR_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_WOR_DSM_EXIT_SHIFT)) & RSIM_CONTROL_WOR_DSM_EXIT_MASK) -#define RSIM_CONTROL_RF_OSC_READY_MASK (0x1000000U) -#define RSIM_CONTROL_RF_OSC_READY_SHIFT (24U) -#define RSIM_CONTROL_RF_OSC_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK (0x2000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT (25U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK (0x4000000U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT (26U) -#define RSIM_CONTROL_RF_OSC_READY_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK) -#define RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK (0x8000000U) -#define RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT (27U) -/*! RSIM_CGC_BLE_EN - BLE Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_BLE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK (0x10000000U) -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT (28U) -/*! RSIM_CGC_XCVR_EN - XCVR Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_XCVR_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK (0x20000000U) -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT (29U) -/*! RSIM_CGC_ZIG_EN - ZIG Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_ZIG_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK) -#define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK (0x80000000U) -#define RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT (31U) -/*! RSIM_CGC_GEN_EN - GEN Clock Gate Control - * 0b0..Clock disabled - * 0b1..Clock enabled - */ -#define RSIM_CONTROL_RSIM_CGC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK) -/*! @} */ - -/*! @name MISC - Radio Miscellaneous */ -/*! @{ */ -#define RSIM_MISC_RADIO_VERSION_MASK (0xFF000000U) -#define RSIM_MISC_RADIO_VERSION_SHIFT (24U) -#define RSIM_MISC_RADIO_VERSION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK) -/*! @} */ - -/*! @name POWER - RSIM Power Control */ -/*! @{ */ -#define RSIM_POWER_RADIO_STOP_MODE_STAT_MASK (0x7U) -#define RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT (0U) -#define RSIM_POWER_RADIO_STOP_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_STAT_MASK) -#define RSIM_POWER_SPM_STOP_ACK_STAT_MASK (0x8U) -#define RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT (3U) -#define RSIM_POWER_SPM_STOP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_STOP_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK (0x70U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT (4U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK (0x80U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT (7U) -#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK) -#define RSIM_POWER_RADIO_STOP_ACK_STAT_MASK (0x100U) -#define RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT (8U) -#define RSIM_POWER_RADIO_STOP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_STOP_REQ_STAT_MASK (0x200U) -#define RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT (9U) -#define RSIM_POWER_RADIO_STOP_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_REQ_STAT_MASK) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK (0x400U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT (10U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK (0x800U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT (11U) -#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK) -#define RSIM_POWER_RF_OSC_EN_OVRD_MASK (0x1000U) -#define RSIM_POWER_RF_OSC_EN_OVRD_SHIFT (12U) -#define RSIM_POWER_RF_OSC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_MASK) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK (0x2000U) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT (13U) -#define RSIM_POWER_RF_OSC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK) -#define RSIM_POWER_RF_POWER_EN_OVRD_MASK (0x4000U) -#define RSIM_POWER_RF_POWER_EN_OVRD_SHIFT (14U) -#define RSIM_POWER_RF_POWER_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_MASK) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK (0x8000U) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT (15U) -#define RSIM_POWER_RF_POWER_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK) -#define RSIM_POWER_SPM_ISO_STAT_MASK (0x10000U) -#define RSIM_POWER_SPM_ISO_STAT_SHIFT (16U) -#define RSIM_POWER_SPM_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_ISO_STAT_SHIFT)) & RSIM_POWER_SPM_ISO_STAT_MASK) -#define RSIM_POWER_RADIO_ISO_STAT_MASK (0x20000U) -#define RSIM_POWER_RADIO_ISO_STAT_SHIFT (17U) -#define RSIM_POWER_RADIO_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_ISO_STAT_SHIFT)) & RSIM_POWER_RADIO_ISO_STAT_MASK) -#define RSIM_POWER_RSIM_ISO_OVRD_MASK (0x40000U) -#define RSIM_POWER_RSIM_ISO_OVRD_SHIFT (18U) -#define RSIM_POWER_RSIM_ISO_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_MASK) -#define RSIM_POWER_RSIM_ISO_OVRD_EN_MASK (0x80000U) -#define RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT (19U) -#define RSIM_POWER_RSIM_ISO_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_EN_MASK) -#define RSIM_POWER_SPM_RUN_ACK_STAT_MASK (0x100000U) -#define RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT (20U) -#define RSIM_POWER_SPM_RUN_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) -#define RSIM_POWER_RADIO_RUN_REQ_STAT_MASK (0x200000U) -#define RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT (21U) -#define RSIM_POWER_RADIO_RUN_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_RUN_REQ_STAT_MASK) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK (0x400000U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT (22U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK (0x800000U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT (23U) -#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK (0x1000000U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT (24U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK (0x2000000U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT (25U) -#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK (0x4000000U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT (26U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK (0x8000000U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT (27U) -#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK) -#define RSIM_POWER_RSIM_STOP_MODE_MASK (0x70000000U) -#define RSIM_POWER_RSIM_STOP_MODE_SHIFT (28U) -/*! RSIM_STOP_MODE - RSIM lowest allowed Stop Mode - * 0b000..Reserved - * 0b001..Reserved - * 0b011..RLLS mode (Radio State Retention mode) - * 0b111..RVLLS mode (This is the POR setting) - */ -#define RSIM_POWER_RSIM_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_MODE_SHIFT)) & RSIM_POWER_RSIM_STOP_MODE_MASK) -#define RSIM_POWER_RSIM_RUN_REQUEST_MASK (0x80000000U) -#define RSIM_POWER_RSIM_RUN_REQUEST_SHIFT (31U) -#define RSIM_POWER_RSIM_RUN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQUEST_SHIFT)) & RSIM_POWER_RSIM_RUN_REQUEST_MASK) -/*! @} */ - -/*! @name SW_CONFIG - Radio Software Configuration */ -/*! @{ */ -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK (0x1U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT (0U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK (0x2U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT (1U) -#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK (0x10U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT (4U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK (0x20U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT (5U) -#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK) -#define RSIM_SW_CONFIG_RADIO_POR_BIT_MASK (0x100U) -#define RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT (8U) -#define RSIM_SW_CONFIG_RADIO_POR_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_POR_BIT_MASK) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK (0x1000U) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT (12U) -#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK (0x10000U) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT (16U) -#define RSIM_SW_CONFIG_RADIO_RESET_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK) -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK (0x300000U) -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT (20U) -/*! WAKEUP_INTERRUPT_SOURCE - RSIM Wakeup Interrupt Source Selector - * 0b00..No Radio Power-On Sequence interrupt will be generated. - * 0b01..A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC. - * 0b10..A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source. - * 0b11..A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs - */ -#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT)) & RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK (0x1000000U) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT (24U) -#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK (0x2000000U) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT (25U) -#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK (0x10000000U) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT (28U) -#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK (0x20000000U) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT (29U) -#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK (0x40000000U) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT (30U) -#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT)) & RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK (0x80000000U) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT (31U) -#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT)) & RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK) -/*! @} */ - -/*! @name DSM_TIMER - Deep Sleep Timer */ -/*! @{ */ -#define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU) -#define RSIM_DSM_TIMER_DSM_TIMER_SHIFT (0U) -#define RSIM_DSM_TIMER_DSM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK) -/*! @} */ - -/*! @name DSM_CONTROL - Deep Sleep Timer Control */ -/*! @{ */ -#define RSIM_DSM_CONTROL_DSM_WOR_READY_MASK (0x1U) -#define RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT (0U) -#define RSIM_DSM_CONTROL_DSM_WOR_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_READY_MASK) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK (0x2U) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT (1U) -#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK (0x4U) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT (2U) -#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK (0x8U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT (3U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK (0x10U) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT (4U) -#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK (0x20U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT (5U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK (0x40U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT (6U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK (0x80U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT (7U) -#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_DSM_MAN_READY_MASK (0x100U) -#define RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT (8U) -#define RSIM_DSM_CONTROL_DSM_MAN_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_READY_MASK) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK (0x200U) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT (9U) -#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK (0x400U) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT (10U) -#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK (0x800U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT (11U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK (0x1000U) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT (12U) -#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK (0x2000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT (13U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK (0x4000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT (14U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK (0x8000U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT (15U) -#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK (0x10000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT (16U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_1(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK (0x20000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT (17U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_2(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK (0x40000U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT (18U) -#define RSIM_DSM_CONTROL_WIFI_COEXIST_3(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x100000U) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (20U) -#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x200000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (21U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK (0x400000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT (22U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK (0x800000U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT (23U) -#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT (27U) -#define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK (0x80000000U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT (31U) -#define RSIM_DSM_CONTROL_DSM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK) -/*! @} */ - -/*! @name DSM_WAKEUP - Deep Sleep Wakeup Sequence */ -/*! @{ */ -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK (0x3FFU) -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT (0U) -#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT)) & RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK (0x3F000U) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT (12U) -#define RSIM_DSM_WAKEUP_ACTIVE_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT)) & RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK) -#define RSIM_DSM_WAKEUP_FINE_DELAY_MASK (0x3F00000U) -#define RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT (20U) -#define RSIM_DSM_WAKEUP_FINE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_FINE_DELAY_MASK) -#define RSIM_DSM_WAKEUP_COARSE_DELAY_MASK (0xF0000000U) -#define RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT (28U) -#define RSIM_DSM_WAKEUP_COARSE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_COARSE_DELAY_MASK) -/*! @} */ - -/*! @name WOR_DURATION - WOR Deep Sleep Duration */ -/*! @{ */ -#define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK (0xFFFFFFU) -#define RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT (0U) -#define RSIM_WOR_DURATION_WOR_DSM_DURATION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK) -/*! @} */ - -/*! @name WOR_WAKE - WOR Deep Sleep Wake Time */ -/*! @{ */ -#define RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT (0U) -#define RSIM_WOR_WAKE_WOR_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT)) & RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK) -#define RSIM_WOR_WAKE_WOR_FSM_STATE_MASK (0x70000000U) -#define RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT (28U) -#define RSIM_WOR_WAKE_WOR_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT)) & RSIM_WOR_WAKE_WOR_FSM_STATE_MASK) -/*! @} */ - -/*! @name MAN_SLEEP - MAN Deep Sleep Time */ -/*! @{ */ -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK (0xFFFFFFU) -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT (0U) -#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT)) & RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK) -/*! @} */ - -/*! @name MAN_WAKE - MAN Deep Sleep Wake Time */ -/*! @{ */ -#define RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK (0xFFFFFFU) -#define RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT (0U) -#define RSIM_MAN_WAKE_MAN_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT)) & RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK) -#define RSIM_MAN_WAKE_MAN_FSM_STATE_MASK (0x70000000U) -#define RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT (28U) -#define RSIM_MAN_WAKE_MAN_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT)) & RSIM_MAN_WAKE_MAN_FSM_STATE_MASK) -/*! @} */ - -/*! @name RF_OSC_CTRL - Radio Oscillator Control */ -/*! @{ */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U) -/*! BB_XTAL_ALC_COUNT_SEL - rmap_bb_xtal_alc_count_sel_hv[1:0] - * 0b00..2048 (64 us @ 32 MHz) - * 0b01..4096 (128 us @ 32 MHz) - * 0b10..8192 (256 us @ 32 MHz) - * 0b11..16384 (512 us @ 32 MHz) - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK (0x4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT (2U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK (0x8U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT (3U) -#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK (0x1F0U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK (0x400U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT (10U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK (0x1F000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT (12U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK (0x20000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT (17U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U) -/*! BB_XTAL_ON_OVRD_ON - rmap_bb_xtal_on_ovrd_on_hv - * 0b0..rfctrl_bb_xtal_on_hv is asserted - * 0b1..rfctrl_bb_xtal_on_ovrd_hv is asserted - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U) -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U) -/*! BB_XTAL_READY_COUNT_SEL - rmap_bb_xtal_ready_count_sel_hv[1:0] - * 0b00..1024 counts (32 us @ 32 MHz) - * 0b01..2048 (64 us @ 32 MHz) - * 0b10..4096 (128 us @ 32 MHz) - * 0b11..8192 (256 us @ 32 MHz) - */ -#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U) -#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK (0x40000000U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT (30U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK (0x80000000U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT (31U) -#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK) -/*! @} */ - -/*! @name ANA_TEST - Radio Analog Test Registers */ -/*! @{ */ -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK (0x10U) -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT (4U) -#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT)) & RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK) -/*! @} */ - -/*! @name ANA_TRIM - Radio Analog Trim Registers */ -/*! @{ */ -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK (0x3U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT (0U) -#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK (0x38U) -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT (3U) -/*! BB_LDO_LS_TRIM - rmap_bb_ldo_ls_trim_hv[2:0] - * 0b000..1.20 V (Default) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK (0xC0U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT (6U) -#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK (0x700U) -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT (8U) -/*! BB_LDO_XO_TRIM - rmap_bb_ldo_xo_trim_hv[2:0] - * 0b000..1.20 V (Default) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK (0xF800U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT (11U) -#define RSIM_ANA_TRIM_BB_XTAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK (0xFF0000U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT (16U) -#define RSIM_ANA_TRIM_BB_XTAL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_1V_TRIM_MASK (0xF000000U) -#define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT (24U) -/*! BG_1V_TRIM - rmap_bg_1v_trim_hv[3:0] - * 0b0000..954.14 mV - * 0b0001..959.26 mV - * 0b0010..964.38 mV - * 0b0011..969.5 mV - * 0b0100..974.6 mV - * 0b0101..979.7 mV - * 0b0110..984.8 mV - * 0b0111..989.9 mV - * 0b1000..995 mV (Default) - * 0b1001..1 V - * 0b1010..1.005 V - * 0b1011..1.01 V - * 0b1100..1.015 V - * 0b1101..1.02 V - * 0b1110..1.025 V - * 0b1111..1.031 V - */ -#define RSIM_ANA_TRIM_BG_1V_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK (0xF0000000U) -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT (28U) -/*! BG_IBIAS_5U_TRIM - rmap_bg_ibias_5u_trim_hv[3:0] - * 0b0000..3.55 uA - * 0b0001..3.73 uA - * 0b0010..4.04 uA - * 0b0011..4.22 uA - * 0b0100..4.39 uA - * 0b0101..4.57 uA - * 0b0110..4.89 uA - * 0b0111..5.06 (Default) - * 0b1000..5.23 uA - * 0b1001..5.41 uA - * 0b1010..5.72 uA - * 0b1011..5.9 uA - * 0b1100..6.07 uA - * 0b1101..6.25 uA - * 0b1110..6.56 uA - * 0b1111..6.74 uA - */ -#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RSIM_Register_Masks */ - - -/* RSIM - Peripheral instance base addresses */ -/** Peripheral RSIM base address */ -#define RSIM_BASE (0x4102F000u) -/** Peripheral RSIM base pointer */ -#define RSIM ((RSIM_Type *)RSIM_BASE) -/** Array initializer of RSIM peripheral base addresses */ -#define RSIM_BASE_ADDRS { RSIM_BASE } -/** Array initializer of RSIM peripheral base pointers */ -#define RSIM_BASE_PTRS { RSIM } - -/*! - * @} - */ /* end of group RSIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ - __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ - __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ - __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ - __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ - __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ - __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ - __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */ - __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */ - __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */ - __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */ - uint8_t RESERVED_0[4]; - __IO uint32_t TDR; /**< RTC Tamper Detect Register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t TIR; /**< RTC Tamper Interrupt Register, offset: 0x3C */ - __IO uint32_t PCR[4]; /**< RTC Pin Configuration Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[1968]; - __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ - __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name TSR - RTC Time Seconds Register */ -/*! @{ */ -#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) -#define RTC_TSR_TSR_SHIFT (0U) -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) -/*! @} */ - -/*! @name TPR - RTC Time Prescaler Register */ -/*! @{ */ -#define RTC_TPR_TPR_MASK (0xFFFFU) -#define RTC_TPR_TPR_SHIFT (0U) -#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) -/*! @} */ - -/*! @name TAR - RTC Time Alarm Register */ -/*! @{ */ -#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) -#define RTC_TAR_TAR_SHIFT (0U) -#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) -/*! @} */ - -/*! @name TCR - RTC Time Compensation Register */ -/*! @{ */ -#define RTC_TCR_TCR_MASK (0xFFU) -#define RTC_TCR_TCR_SHIFT (0U) -/*! TCR - Time Compensation Register - * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. - * 0b10000001..Time Prescaler Register overflows every 32895 clock cycles. - * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. - * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. - * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. - * 0b01111110..Time Prescaler Register overflows every 32642 clock cycles. - * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. - */ -#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) -#define RTC_TCR_CIR_MASK (0xFF00U) -#define RTC_TCR_CIR_SHIFT (8U) -#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) -#define RTC_TCR_TCV_MASK (0xFF0000U) -#define RTC_TCR_TCV_SHIFT (16U) -#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) -#define RTC_TCR_CIC_MASK (0xFF000000U) -#define RTC_TCR_CIC_SHIFT (24U) -#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) -/*! @} */ - -/*! @name CR - RTC Control Register */ -/*! @{ */ -#define RTC_CR_SWR_MASK (0x1U) -#define RTC_CR_SWR_SHIFT (0U) -/*! SWR - Software Reset - * 0b0..No effect. - * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it. - */ -#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) -#define RTC_CR_WPE_MASK (0x2U) -#define RTC_CR_WPE_SHIFT (1U) -/*! WPE - Wakeup Pin Enable - * 0b0..RTC_WAKEUP pin is disabled. - * 0b1..RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on. - */ -#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) -#define RTC_CR_SUP_MASK (0x4U) -#define RTC_CR_SUP_SHIFT (2U) -/*! SUP - Supervisor Access - * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. - * 0b1..Non-supervisor mode write accesses are supported. - */ -#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) -#define RTC_CR_UM_MASK (0x8U) -#define RTC_CR_UM_SHIFT (3U) -/*! UM - Update Mode - * 0b0..Registers cannot be written when locked. - * 0b1..Registers can be written when locked under limited conditions. - */ -#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) -#define RTC_CR_WPS_MASK (0x10U) -#define RTC_CR_WPS_SHIFT (4U) -/*! WPS - Wakeup Pin Select - * 0b0..RTC_WAKEUP pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. - * 0b1..RTC_WAKEUP pin outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. - */ -#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) -#define RTC_CR_CPS_MASK (0x20U) -#define RTC_CR_CPS_SHIFT (5U) -/*! CPS - Clock Pin Select - * 0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. - * 0b1..The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. - */ -#define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK) -#define RTC_CR_LPOS_MASK (0x80U) -#define RTC_CR_LPOS_SHIFT (7U) -/*! LPOS - LPO Select - * 0b0..RTC prescaler increments using 32.768 kHz clock. - * 0b1..RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. - */ -#define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) -#define RTC_CR_OSCE_MASK (0x100U) -#define RTC_CR_OSCE_SHIFT (8U) -/*! OSCE - Oscillator Enable - * 0b0..32.768 kHz oscillator is disabled. - * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. - */ -#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) -#define RTC_CR_CLKO_MASK (0x200U) -#define RTC_CR_CLKO_SHIFT (9U) -/*! CLKO - Clock Output - * 0b0..The 32 kHz clock is output to other peripherals. - * 0b1..The 32 kHz clock is not output to other peripherals. - */ -#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) -#define RTC_CR_SC16P_MASK (0x400U) -#define RTC_CR_SC16P_SHIFT (10U) -/*! SC16P - Oscillator 16pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) -#define RTC_CR_SC8P_MASK (0x800U) -#define RTC_CR_SC8P_SHIFT (11U) -/*! SC8P - Oscillator 8pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) -#define RTC_CR_SC4P_MASK (0x1000U) -#define RTC_CR_SC4P_SHIFT (12U) -/*! SC4P - Oscillator 4pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) -#define RTC_CR_SC2P_MASK (0x2000U) -#define RTC_CR_SC2P_SHIFT (13U) -/*! SC2P - Oscillator 2pF Load Configure - * 0b0..Disable the load. - * 0b1..Enable the additional load. - */ -#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) -#define RTC_CR_OSCM_MASK (0x8000U) -#define RTC_CR_OSCM_SHIFT (15U) -/*! OSCM - Oscillator Mode Select - * 0b0..Configures the 32.768kHz crystal oscillator for robust operation supporting a wide range of crystals. - * 0b1..Configures the 32.768kHz crystal oscillator for low power operation supporting a more limited range of crystals. - */ -#define RTC_CR_OSCM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCM_SHIFT)) & RTC_CR_OSCM_MASK) -#define RTC_CR_PORS_MASK (0x30000U) -#define RTC_CR_PORS_SHIFT (16U) -/*! PORS - POR Select - * 0b00..POR brownout enabled for 120us every 128ms. - * 0b01..POR brownout enabled for 120us every 64ms. - * 0b10..POR brownout enabled for 120us every 32ms. - * 0b11..POR brownout always enabled. - */ -#define RTC_CR_PORS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_PORS_SHIFT)) & RTC_CR_PORS_MASK) -#define RTC_CR_CPE_MASK (0x3000000U) -#define RTC_CR_CPE_SHIFT (24U) -/*! CPE - Clock Pin Enable - * 0b00..The RTC_CLKOUT function is disabled. - * 0b01..Enable RTC_CLKOUT pin on pin 1. - * 0b10..Enable RTC_CLKOUT pin on pin 2. - * 0b11..Enable RTC_CLKOUT pin on pin 3. - */ -#define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK) -/*! @} */ - -/*! @name SR - RTC Status Register */ -/*! @{ */ -#define RTC_SR_TIF_MASK (0x1U) -#define RTC_SR_TIF_SHIFT (0U) -/*! TIF - Time Invalid Flag - * 0b0..Time is valid. - * 0b1..Time is invalid and time counter is read as zero. - */ -#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) -#define RTC_SR_TOF_MASK (0x2U) -#define RTC_SR_TOF_SHIFT (1U) -/*! TOF - Time Overflow Flag - * 0b0..Time overflow has not occurred. - * 0b1..Time overflow has occurred and time counter is read as zero. - */ -#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) -#define RTC_SR_TAF_MASK (0x4U) -#define RTC_SR_TAF_SHIFT (2U) -/*! TAF - Time Alarm Flag - * 0b0..Time alarm has not occurred. - * 0b1..Time alarm has occurred. - */ -#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) -#define RTC_SR_MOF_MASK (0x8U) -#define RTC_SR_MOF_SHIFT (3U) -/*! MOF - Monotonic Overflow Flag - * 0b0..Monotonic counter overflow has not occurred. - * 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero. - */ -#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK) -#define RTC_SR_TCE_MASK (0x10U) -#define RTC_SR_TCE_SHIFT (4U) -/*! TCE - Time Counter Enable - * 0b0..Time counter is disabled. - * 0b1..Time counter is enabled. - */ -#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) -#define RTC_SR_TIDF_MASK (0x80U) -#define RTC_SR_TIDF_SHIFT (7U) -/*! TIDF - Tamper Interrupt Detect Flag - * 0b0..Tamper interrupt has not asserted. - * 0b1..Tamper interrupt has asserted. - */ -#define RTC_SR_TIDF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIDF_SHIFT)) & RTC_SR_TIDF_MASK) -/*! @} */ - -/*! @name LR - RTC Lock Register */ -/*! @{ */ -#define RTC_LR_TCL_MASK (0x8U) -#define RTC_LR_TCL_SHIFT (3U) -/*! TCL - Time Compensation Lock - * 0b0..Time Compensation Register is locked and writes are ignored. - * 0b1..Time Compensation Register is not locked and writes complete as normal. - */ -#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) -#define RTC_LR_CRL_MASK (0x10U) -#define RTC_LR_CRL_SHIFT (4U) -/*! CRL - Control Register Lock - * 0b0..Control Register is locked and writes are ignored. - * 0b1..Control Register is not locked and writes complete as normal. - */ -#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) -#define RTC_LR_SRL_MASK (0x20U) -#define RTC_LR_SRL_SHIFT (5U) -/*! SRL - Status Register Lock - * 0b0..Status Register is locked and writes are ignored. - * 0b1..Status Register is not locked and writes complete as normal. - */ -#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) -#define RTC_LR_LRL_MASK (0x40U) -#define RTC_LR_LRL_SHIFT (6U) -/*! LRL - Lock Register Lock - * 0b0..Lock Register is locked and writes are ignored. - * 0b1..Lock Register is not locked and writes complete as normal. - */ -#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) -#define RTC_LR_TTSL_MASK (0x100U) -#define RTC_LR_TTSL_SHIFT (8U) -/*! TTSL - Tamper Time Seconds Lock - * 0b0..Tamper Time Seconds Register is locked and writes are ignored. - * 0b1..Tamper Time Seconds Register is not locked and writes complete as normal. - */ -#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK) -#define RTC_LR_MEL_MASK (0x200U) -#define RTC_LR_MEL_SHIFT (9U) -/*! MEL - Monotonic Enable Lock - * 0b0..Monotonic Enable Register is locked and writes are ignored. - * 0b1..Monotonic Enable Register is not locked and writes complete as normal. - */ -#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK) -#define RTC_LR_MCLL_MASK (0x400U) -#define RTC_LR_MCLL_SHIFT (10U) -/*! MCLL - Monotonic Counter Low Lock - * 0b0..Monotonic Counter Low Register is locked and writes are ignored. - * 0b1..Monotonic Counter Low Register is not locked and writes complete as normal. - */ -#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK) -#define RTC_LR_MCHL_MASK (0x800U) -#define RTC_LR_MCHL_SHIFT (11U) -/*! MCHL - Monotonic Counter High Lock - * 0b0..Monotonic Counter High Register is locked and writes are ignored. - * 0b1..Monotonic Counter High Register is not locked and writes complete as normal. - */ -#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK) -#define RTC_LR_TDL_MASK (0x2000U) -#define RTC_LR_TDL_SHIFT (13U) -/*! TDL - Tamper Detect Lock - * 0b0..Tamper Detect Register is locked and writes are ignored. - * 0b1..Tamper Detect Register is not locked and writes complete as normal. - */ -#define RTC_LR_TDL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TDL_SHIFT)) & RTC_LR_TDL_MASK) -#define RTC_LR_TIL_MASK (0x8000U) -#define RTC_LR_TIL_SHIFT (15U) -/*! TIL - Tamper Interrupt Lock - * 0b0..Tamper Interrupt Register is locked and writes are ignored. - * 0b1..Tamper Interrupt Register is not locked and writes complete as normal. - */ -#define RTC_LR_TIL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TIL_SHIFT)) & RTC_LR_TIL_MASK) -#define RTC_LR_PCL_MASK (0xF0000U) -#define RTC_LR_PCL_SHIFT (16U) -#define RTC_LR_PCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK) -/*! @} */ - -/*! @name IER - RTC Interrupt Enable Register */ -/*! @{ */ -#define RTC_IER_TIIE_MASK (0x1U) -#define RTC_IER_TIIE_SHIFT (0U) -/*! TIIE - Time Invalid Interrupt Enable - * 0b0..Time invalid flag does not generate an interrupt. - * 0b1..Time invalid flag does generate an interrupt. - */ -#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) -#define RTC_IER_TOIE_MASK (0x2U) -#define RTC_IER_TOIE_SHIFT (1U) -/*! TOIE - Time Overflow Interrupt Enable - * 0b0..Time overflow flag does not generate an interrupt. - * 0b1..Time overflow flag does generate an interrupt. - */ -#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) -#define RTC_IER_TAIE_MASK (0x4U) -#define RTC_IER_TAIE_SHIFT (2U) -/*! TAIE - Time Alarm Interrupt Enable - * 0b0..Time alarm flag does not generate an interrupt. - * 0b1..Time alarm flag does generate an interrupt. - */ -#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) -#define RTC_IER_MOIE_MASK (0x8U) -#define RTC_IER_MOIE_SHIFT (3U) -/*! MOIE - Monotonic Overflow Interrupt Enable - * 0b0..Monotonic overflow flag does not generate an interrupt. - * 0b1..Monotonic overflow flag does generate an interrupt. - */ -#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK) -#define RTC_IER_TSIE_MASK (0x10U) -#define RTC_IER_TSIE_SHIFT (4U) -/*! TSIE - Time Seconds Interrupt Enable - * 0b0..Seconds interrupt is disabled. - * 0b1..Seconds interrupt is enabled. - */ -#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) -#define RTC_IER_WPON_MASK (0x80U) -#define RTC_IER_WPON_SHIFT (7U) -/*! WPON - Wakeup Pin On - * 0b0..No effect. - * 0b1..If the RTC_WAKEUP pin is enabled, then the pin will assert. - */ -#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) -#define RTC_IER_TSIC_MASK (0x70000U) -#define RTC_IER_TSIC_SHIFT (16U) -/*! TSIC - Timer Seconds Interrupt Configuration - * 0b000..1 Hz. - * 0b001..2 Hz. - * 0b010..4 Hz. - * 0b011..8 Hz. - * 0b100..16 Hz. - * 0b101..32 Hz. - * 0b110..64 Hz. - * 0b111..128 Hz. - */ -#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) -/*! @} */ - -/*! @name TTSR - RTC Tamper Time Seconds Register */ -/*! @{ */ -#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU) -#define RTC_TTSR_TTS_SHIFT (0U) -#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK) -/*! @} */ - -/*! @name MER - RTC Monotonic Enable Register */ -/*! @{ */ -#define RTC_MER_MCE_MASK (0x10U) -#define RTC_MER_MCE_SHIFT (4U) -/*! MCE - Monotonic Counter Enable - * 0b0..Writes to the monotonic counter load the counter with the value written. - * 0b1..Writes to the monotonic counter increment the counter. - */ -#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK) -/*! @} */ - -/*! @name MCLR - RTC Monotonic Counter Low Register */ -/*! @{ */ -#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU) -#define RTC_MCLR_MCL_SHIFT (0U) -#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK) -/*! @} */ - -/*! @name MCHR - RTC Monotonic Counter High Register */ -/*! @{ */ -#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU) -#define RTC_MCHR_MCH_SHIFT (0U) -#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK) -/*! @} */ - -/*! @name TDR - RTC Tamper Detect Register */ -/*! @{ */ -#define RTC_TDR_LCTF_MASK (0x10U) -#define RTC_TDR_LCTF_SHIFT (4U) -/*! LCTF - Loss of Clock Tamper Flag - * 0b0..Tamper not detected. - * 0b1..Loss of Clock tamper detected. - */ -#define RTC_TDR_LCTF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_LCTF_SHIFT)) & RTC_TDR_LCTF_MASK) -#define RTC_TDR_STF_MASK (0x20U) -#define RTC_TDR_STF_SHIFT (5U) -/*! STF - Security Tamper Flag - * 0b0..Tamper not detected. - * 0b1..Security module tamper detected. - */ -#define RTC_TDR_STF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_STF_SHIFT)) & RTC_TDR_STF_MASK) -#define RTC_TDR_FSF_MASK (0x40U) -#define RTC_TDR_FSF_SHIFT (6U) -/*! FSF - Flash Security Flag - * 0b0..Tamper not detected. - * 0b1..Flash security tamper detected. - */ -#define RTC_TDR_FSF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_FSF_SHIFT)) & RTC_TDR_FSF_MASK) -#define RTC_TDR_TMF_MASK (0x80U) -#define RTC_TDR_TMF_SHIFT (7U) -/*! TMF - Test Mode Flag - * 0b0..Tamper not detected. - * 0b1..Test mode tamper detected. - */ -#define RTC_TDR_TMF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TMF_SHIFT)) & RTC_TDR_TMF_MASK) -#define RTC_TDR_TPF_MASK (0xF0000U) -#define RTC_TDR_TPF_SHIFT (16U) -#define RTC_TDR_TPF(x) (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TPF_SHIFT)) & RTC_TDR_TPF_MASK) -/*! @} */ - -/*! @name TIR - RTC Tamper Interrupt Register */ -/*! @{ */ -#define RTC_TIR_LCIE_MASK (0x10U) -#define RTC_TIR_LCIE_SHIFT (4U) -/*! LCIE - Loss of Clock Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the loss of clock flag is set. - */ -#define RTC_TIR_LCIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_LCIE_SHIFT)) & RTC_TIR_LCIE_MASK) -#define RTC_TIR_SIE_MASK (0x20U) -#define RTC_TIR_SIE_SHIFT (5U) -/*! SIE - Security Module Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the security module flag is set. - */ -#define RTC_TIR_SIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_SIE_SHIFT)) & RTC_TIR_SIE_MASK) -#define RTC_TIR_FSIE_MASK (0x40U) -#define RTC_TIR_FSIE_SHIFT (6U) -/*! FSIE - Flash Security Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the flash security flag is set. - */ -#define RTC_TIR_FSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_FSIE_SHIFT)) & RTC_TIR_FSIE_MASK) -#define RTC_TIR_TMIE_MASK (0x80U) -#define RTC_TIR_TMIE_SHIFT (7U) -/*! TMIE - Test Mode Interrupt Enable - * 0b0..Interupt disabled. - * 0b1..An interrupt is generated when the test mode flag is set. - */ -#define RTC_TIR_TMIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TMIE_SHIFT)) & RTC_TIR_TMIE_MASK) -#define RTC_TIR_TPIE_MASK (0xF0000U) -#define RTC_TIR_TPIE_SHIFT (16U) -#define RTC_TIR_TPIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TPIE_SHIFT)) & RTC_TIR_TPIE_MASK) -/*! @} */ - -/*! @name PCR - RTC Pin Configuration Register */ -/*! @{ */ -#define RTC_PCR_TPE_MASK (0x1000000U) -#define RTC_PCR_TPE_SHIFT (24U) -/*! TPE - Tamper Pull Enable - * 0b0..Pull resistor is disabled on tamper pin. - * 0b1..Pull resistor is enabled on tamper pin. - */ -#define RTC_PCR_TPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPE_SHIFT)) & RTC_PCR_TPE_MASK) -#define RTC_PCR_TPS_MASK (0x2000000U) -#define RTC_PCR_TPS_SHIFT (25U) -/*! TPS - Tamper Pull Select - * 0b0..Tamper pin pull resistor direction will assert the tamper pin. - * 0b1..Tamper pin pull resistor direction will negate the tamper pin. - */ -#define RTC_PCR_TPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPS_SHIFT)) & RTC_PCR_TPS_MASK) -#define RTC_PCR_TFE_MASK (0x4000000U) -#define RTC_PCR_TFE_SHIFT (26U) -/*! TFE - Tamper Filter Enable - * 0b0..Input filter is disabled on the tamper pin. - * 0b1..Input filter is enabled on the tamper pin. - */ -#define RTC_PCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TFE_SHIFT)) & RTC_PCR_TFE_MASK) -#define RTC_PCR_TPP_MASK (0x8000000U) -#define RTC_PCR_TPP_SHIFT (27U) -/*! TPP - Tamper Pin Polarity - * 0b0..Tamper pin is active high. - * 0b1..Tamper pin is active low. - */ -#define RTC_PCR_TPP(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPP_SHIFT)) & RTC_PCR_TPP_MASK) -#define RTC_PCR_TPID_MASK (0x80000000U) -#define RTC_PCR_TPID_SHIFT (31U) -/*! TPID - Tamper Pin Input Data - * 0b0..Tamper pin input data is logic zero. - * 0b1..Tamper pin input data is logic one. - */ -#define RTC_PCR_TPID(x) (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPID_SHIFT)) & RTC_PCR_TPID_MASK) -/*! @} */ - -/* The count of RTC_PCR */ -#define RTC_PCR_COUNT (4U) - -/*! @name WAR - RTC Write Access Register */ -/*! @{ */ -#define RTC_WAR_TSRW_MASK (0x1U) -#define RTC_WAR_TSRW_SHIFT (0U) -/*! TSRW - Time Seconds Register Write - * 0b0..Writes to the Time Seconds Register are ignored. - * 0b1..Writes to the Time Seconds Register complete as normal. - */ -#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) -#define RTC_WAR_TPRW_MASK (0x2U) -#define RTC_WAR_TPRW_SHIFT (1U) -/*! TPRW - Time Prescaler Register Write - * 0b0..Writes to the Time Prescaler Register are ignored. - * 0b1..Writes to the Time Prescaler Register complete as normal. - */ -#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) -#define RTC_WAR_TARW_MASK (0x4U) -#define RTC_WAR_TARW_SHIFT (2U) -/*! TARW - Time Alarm Register Write - * 0b0..Writes to the Time Alarm Register are ignored. - * 0b1..Writes to the Time Alarm Register complete as normal. - */ -#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) -#define RTC_WAR_TCRW_MASK (0x8U) -#define RTC_WAR_TCRW_SHIFT (3U) -/*! TCRW - Time Compensation Register Write - * 0b0..Writes to the Time Compensation Register are ignored. - * 0b1..Writes to the Time Compensation Register complete as normal. - */ -#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) -#define RTC_WAR_CRW_MASK (0x10U) -#define RTC_WAR_CRW_SHIFT (4U) -/*! CRW - Control Register Write - * 0b0..Writes to the Control Register are ignored. - * 0b1..Writes to the Control Register complete as normal. - */ -#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) -#define RTC_WAR_SRW_MASK (0x20U) -#define RTC_WAR_SRW_SHIFT (5U) -/*! SRW - Status Register Write - * 0b0..Writes to the Status Register are ignored. - * 0b1..Writes to the Status Register complete as normal. - */ -#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) -#define RTC_WAR_LRW_MASK (0x40U) -#define RTC_WAR_LRW_SHIFT (6U) -/*! LRW - Lock Register Write - * 0b0..Writes to the Lock Register are ignored. - * 0b1..Writes to the Lock Register complete as normal. - */ -#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) -#define RTC_WAR_IERW_MASK (0x80U) -#define RTC_WAR_IERW_SHIFT (7U) -/*! IERW - Interrupt Enable Register Write - * 0b0..Writes to the Interupt Enable Register are ignored. - * 0b1..Writes to the Interrupt Enable Register complete as normal. - */ -#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) -#define RTC_WAR_TTSW_MASK (0x100U) -#define RTC_WAR_TTSW_SHIFT (8U) -/*! TTSW - Tamper Time Seconds Write - * 0b0..Writes to the Tamper Time Seconds Register are ignored. - * 0b1..Writes to the Tamper Time Seconds Register complete as normal. - */ -#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK) -#define RTC_WAR_MERW_MASK (0x200U) -#define RTC_WAR_MERW_SHIFT (9U) -/*! MERW - Monotonic Enable Register Write - * 0b0..Writes to the Monotonic Enable Register are ignored. - * 0b1..Writes to the Monotonic Enable Register complete as normal. - */ -#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK) -#define RTC_WAR_MCLW_MASK (0x400U) -#define RTC_WAR_MCLW_SHIFT (10U) -/*! MCLW - Monotonic Counter Low Write - * 0b0..Writes to the Monotonic Counter Low Register are ignored. - * 0b1..Writes to the Monotonic Counter Low Register complete as normal. - */ -#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK) -#define RTC_WAR_MCHW_MASK (0x800U) -#define RTC_WAR_MCHW_SHIFT (11U) -/*! MCHW - Monotonic Counter High Write - * 0b0..Writes to the Monotonic Counter High Register are ignored. - * 0b1..Writes to the Monotonic Counter High Register complete as normal. - */ -#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK) -#define RTC_WAR_TDRW_MASK (0x2000U) -#define RTC_WAR_TDRW_SHIFT (13U) -/*! TDRW - Tamper Detect Register Write - * 0b0..Writes to the Tamper Detect Register are ignored. - * 0b1..Writes to the Tamper Detect Register complete as normal. - */ -#define RTC_WAR_TDRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TDRW_SHIFT)) & RTC_WAR_TDRW_MASK) -#define RTC_WAR_TIRW_MASK (0x8000U) -#define RTC_WAR_TIRW_SHIFT (15U) -/*! TIRW - Tamper Interrupt Register Write - * 0b0..Writes to the Tamper Interrupt Register are ignored. - * 0b1..Writes to the Tamper Interrupt Register complete as normal. - */ -#define RTC_WAR_TIRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TIRW_SHIFT)) & RTC_WAR_TIRW_MASK) -#define RTC_WAR_PCRW_MASK (0xF0000U) -#define RTC_WAR_PCRW_SHIFT (16U) -#define RTC_WAR_PCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_PCRW_SHIFT)) & RTC_WAR_PCRW_MASK) -/*! @} */ - -/*! @name RAR - RTC Read Access Register */ -/*! @{ */ -#define RTC_RAR_TSRR_MASK (0x1U) -#define RTC_RAR_TSRR_SHIFT (0U) -/*! TSRR - Time Seconds Register Read - * 0b0..Reads to the Time Seconds Register are ignored. - * 0b1..Reads to the Time Seconds Register complete as normal. - */ -#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) -#define RTC_RAR_TPRR_MASK (0x2U) -#define RTC_RAR_TPRR_SHIFT (1U) -/*! TPRR - Time Prescaler Register Read - * 0b0..Reads to the Time Pprescaler Register are ignored. - * 0b1..Reads to the Time Prescaler Register complete as normal. - */ -#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) -#define RTC_RAR_TARR_MASK (0x4U) -#define RTC_RAR_TARR_SHIFT (2U) -/*! TARR - Time Alarm Register Read - * 0b0..Reads to the Time Alarm Register are ignored. - * 0b1..Reads to the Time Alarm Register complete as normal. - */ -#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) -#define RTC_RAR_TCRR_MASK (0x8U) -#define RTC_RAR_TCRR_SHIFT (3U) -/*! TCRR - Time Compensation Register Read - * 0b0..Reads to the Time Compensation Register are ignored. - * 0b1..Reads to the Time Compensation Register complete as normal. - */ -#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) -#define RTC_RAR_CRR_MASK (0x10U) -#define RTC_RAR_CRR_SHIFT (4U) -/*! CRR - Control Register Read - * 0b0..Reads to the Control Register are ignored. - * 0b1..Reads to the Control Register complete as normal. - */ -#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) -#define RTC_RAR_SRR_MASK (0x20U) -#define RTC_RAR_SRR_SHIFT (5U) -/*! SRR - Status Register Read - * 0b0..Reads to the Status Register are ignored. - * 0b1..Reads to the Status Register complete as normal. - */ -#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) -#define RTC_RAR_LRR_MASK (0x40U) -#define RTC_RAR_LRR_SHIFT (6U) -/*! LRR - Lock Register Read - * 0b0..Reads to the Lock Register are ignored. - * 0b1..Reads to the Lock Register complete as normal. - */ -#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) -#define RTC_RAR_IERR_MASK (0x80U) -#define RTC_RAR_IERR_SHIFT (7U) -/*! IERR - Interrupt Enable Register Read - * 0b0..Reads to the Interrupt Enable Register are ignored. - * 0b1..Reads to the Interrupt Enable Register complete as normal. - */ -#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) -#define RTC_RAR_TTSR_MASK (0x100U) -#define RTC_RAR_TTSR_SHIFT (8U) -/*! TTSR - Tamper Time Seconds Read - * 0b0..Reads to the Tamper Time Seconds Register are ignored. - * 0b1..Reads to the Tamper Time Seconds Register complete as normal. - */ -#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK) -#define RTC_RAR_MERR_MASK (0x200U) -#define RTC_RAR_MERR_SHIFT (9U) -/*! MERR - Monotonic Enable Register Read - * 0b0..Reads to the Monotonic Enable Register are ignored. - * 0b1..Reads to the Monotonic Enable Register complete as normal. - */ -#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK) -#define RTC_RAR_MCLR_MASK (0x400U) -#define RTC_RAR_MCLR_SHIFT (10U) -/*! MCLR - Monotonic Counter Low Read - * 0b0..Reads to the Monotonic Counter Low Register are ignored. - * 0b1..Reads to the Monotonic Counter Low Register complete as normal. - */ -#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK) -#define RTC_RAR_MCHR_MASK (0x800U) -#define RTC_RAR_MCHR_SHIFT (11U) -/*! MCHR - Monotonic Counter High Read - * 0b0..Reads to the Monotonic Counter High Register are ignored. - * 0b1..Reads to the Monotonic Counter High Register complete as normal. - */ -#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK) -#define RTC_RAR_TDRR_MASK (0x2000U) -#define RTC_RAR_TDRR_SHIFT (13U) -/*! TDRR - Tamper Detect Register Read - * 0b0..Reads to the Tamper Detect Register are ignored. - * 0b1..Reads to the Tamper Detect Register complete as normal. - */ -#define RTC_RAR_TDRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TDRR_SHIFT)) & RTC_RAR_TDRR_MASK) -#define RTC_RAR_TIRR_MASK (0x8000U) -#define RTC_RAR_TIRR_SHIFT (15U) -/*! TIRR - Tamper Interrupt Register Read - * 0b0..Reads to the Tamper Interrupt Register are ignored. - * 0b1..Reads to the Tamper Interrupt Register complete as normal. - */ -#define RTC_RAR_TIRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TIRR_SHIFT)) & RTC_RAR_TIRR_MASK) -#define RTC_RAR_PCRR_MASK (0xF0000U) -#define RTC_RAR_PCRR_SHIFT (16U) -#define RTC_RAR_PCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_PCRR_SHIFT)) & RTC_RAR_PCRR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x40031000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer - * @{ - */ - -/** SCG - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ - __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ - __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ - __IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ - __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ - uint8_t RESERVED_1[220]; - __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ - __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ - uint8_t RESERVED_2[248]; - __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ - __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ - __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ - uint8_t RESERVED_3[244]; - __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ - __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ - __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ - __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */ - uint8_t RESERVED_4[8]; - __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */ - uint8_t RESERVED_5[228]; - __IO uint32_t ROSCCSR; /**< RTC OSC Control Status Register, offset: 0x400 */ - uint8_t RESERVED_6[252]; - __IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offset: 0x500 */ - __IO uint32_t LPFLLDIV; /**< Low Power FLL Divide Register, offset: 0x504 */ - __IO uint32_t LPFLLCFG; /**< Low Power FLL Configuration Register, offset: 0x508 */ - __IO uint32_t LPFLLTCFG; /**< Low Power FLL Trim Configuration Register, offset: 0x50C */ - uint8_t RESERVED_7[4]; - __IO uint32_t LPFLLSTAT; /**< Low Power FLL Status Register, offset: 0x514 */ -} SCG_Type; - -/* ---------------------------------------------------------------------------- - -- SCG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCG_Register_Masks SCG Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) -#define SCG_VERID_VERSION_SHIFT (0U) -#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define SCG_PARAM_CLKPRES_MASK (0xFFU) -#define SCG_PARAM_CLKPRES_SHIFT (0U) -/*! CLKPRES - Clock Present - * 0b00000000-0b00000001..Reserved. - * 0bxxxxxx1x..System OSC (SOSC) is present. - * 0bxxxxx1xx..Slow IRC (SIRC) is present. - * 0bxxxx1xxx..Fast IRC (FIRC) is present. - * 0bxxx1xxxx..RTC OSC (ROSC) is present. - * 0bxx1xxxxx..Low Power FLL (LPFLL) is present. - */ -#define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) -#define SCG_PARAM_DIVPRES_MASK (0xF8000000U) -#define SCG_PARAM_DIVPRES_SHIFT (27U) -/*! DIVPRES - Divider Present - * 0bxxxx1..System DIVSLOW is present. - * 0bxxx1x..System DIVBUS is present. - * 0bxx1xx..System DIVEXT is present. - * 0b1xxxx..System DIVCORE is present. - */ -#define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) -/*! @} */ - -/*! @name CSR - Clock Status Register */ -/*! @{ */ -#define SCG_CSR_DIVSLOW_MASK (0xFU) -#define SCG_CSR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) -#define SCG_CSR_DIVBUS_MASK (0xF0U) -#define SCG_CSR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK) -#define SCG_CSR_DIVEXT_MASK (0xF00U) -#define SCG_CSR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVEXT_SHIFT)) & SCG_CSR_DIVEXT_MASK) -#define SCG_CSR_DIVCORE_MASK (0xF0000U) -#define SCG_CSR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) -#define SCG_CSR_SCS_MASK (0xF000000U) -#define SCG_CSR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) -/*! @} */ - -/*! @name RCCR - Run Clock Control Register */ -/*! @{ */ -#define SCG_RCCR_DIVSLOW_MASK (0xFU) -#define SCG_RCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) -#define SCG_RCCR_DIVBUS_MASK (0xF0U) -#define SCG_RCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK) -#define SCG_RCCR_DIVEXT_MASK (0xF00U) -#define SCG_RCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVEXT_SHIFT)) & SCG_RCCR_DIVEXT_MASK) -#define SCG_RCCR_DIVCORE_MASK (0xF0000U) -#define SCG_RCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) -#define SCG_RCCR_SCS_MASK (0x7000000U) -#define SCG_RCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b000..Reserved - * 0b001..System OSC (SOSC_CLK) - * 0b010..Slow IRC (SIRC_CLK) - * 0b011..Fast IRC (FIRC_CLK) - * 0b100..RTC OSC (ROSC_CLK) - * 0b101..Low Power FLL (LPFLL_CLK) - * 0b110..Reserved - * 0b111..Reserved - */ -#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) -/*! @} */ - -/*! @name VCCR - VLPR Clock Control Register */ -/*! @{ */ -#define SCG_VCCR_DIVSLOW_MASK (0xFU) -#define SCG_VCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) -#define SCG_VCCR_DIVBUS_MASK (0xF0U) -#define SCG_VCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK) -#define SCG_VCCR_DIVEXT_MASK (0xF00U) -#define SCG_VCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVEXT_SHIFT)) & SCG_VCCR_DIVEXT_MASK) -#define SCG_VCCR_DIVCORE_MASK (0xF0000U) -#define SCG_VCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) -#define SCG_VCCR_SCS_MASK (0xF000000U) -#define SCG_VCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Reserved - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Reserved - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) -/*! @} */ - -/*! @name HCCR - HSRUN Clock Control Register */ -/*! @{ */ -#define SCG_HCCR_DIVSLOW_MASK (0xFU) -#define SCG_HCCR_DIVSLOW_SHIFT (0U) -/*! DIVSLOW - Slow Clock Divide Ratio - * 0b0000..Reserved - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK) -#define SCG_HCCR_DIVBUS_MASK (0xF0U) -#define SCG_HCCR_DIVBUS_SHIFT (4U) -/*! DIVBUS - Bus Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK) -#define SCG_HCCR_DIVEXT_MASK (0xF00U) -#define SCG_HCCR_DIVEXT_SHIFT (8U) -/*! DIVEXT - External Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVEXT(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVEXT_SHIFT)) & SCG_HCCR_DIVEXT_MASK) -#define SCG_HCCR_DIVCORE_MASK (0xF0000U) -#define SCG_HCCR_DIVCORE_SHIFT (16U) -/*! DIVCORE - Core Clock Divide Ratio - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b0010..Divide-by-3 - * 0b0011..Divide-by-4 - * 0b0100..Divide-by-5 - * 0b0101..Divide-by-6 - * 0b0110..Divide-by-7 - * 0b0111..Divide-by-8 - * 0b1000..Divide-by-9 - * 0b1001..Divide-by-10 - * 0b1010..Divide-by-11 - * 0b1011..Divide-by-12 - * 0b1100..Divide-by-13 - * 0b1101..Divide-by-14 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK) -#define SCG_HCCR_SCS_MASK (0xF000000U) -#define SCG_HCCR_SCS_SHIFT (24U) -/*! SCS - System Clock Source - * 0b0000..Reserved - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - */ -#define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK) -/*! @} */ - -/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ -/*! @{ */ -#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) -#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) -/*! CLKOUTSEL - SCG Clkout Select - * 0b0000..SCG EXTERNAL Clock - * 0b0001..System OSC (SOSC_CLK) - * 0b0010..Slow IRC (SIRC_CLK) - * 0b0011..Fast IRC (FIRC_CLK) - * 0b0100..RTC OSC (ROSC_CLK) - * 0b0101..Low Power FLL (LPFLL_CLK) - * 0b0110..Reserved - * 0b0111..Reserved - * 0b1111..Reserved - */ -#define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) -/*! @} */ - -/*! @name SOSCCSR - System OSC Control Status Register */ -/*! @{ */ -#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) -#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) -/*! SOSCEN - System OSC Enable - * 0b0..System OSC is disabled - * 0b1..System OSC is enabled - */ -#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) -#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) -#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) -/*! SOSCSTEN - System OSC Stop Enable - * 0b0..System OSC is disabled in Stop modes - * 0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1. - */ -#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) -#define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U) -#define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U) -/*! SOSCLPEN - System OSC Low Power Enable - * 0b0..System OSC is disabled in VLP modes - * 0b1..System OSC is enabled in VLP modes - */ -#define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK) -#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) -#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) -/*! SOSCCM - System OSC Clock Monitor - * 0b0..System OSC Clock Monitor is disabled - * 0b1..System OSC Clock Monitor is enabled - */ -#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) -#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) -#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) -/*! SOSCCMRE - System OSC Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) -#define SCG_SOSCCSR_LK_MASK (0x800000U) -#define SCG_SOSCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..This Control Status Register can be written. - * 0b1..This Control Status Register cannot be written. - */ -#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) -#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) -#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) -/*! SOSCVLD - System OSC Valid - * 0b0..System OSC is not enabled or clock is not valid - * 0b1..System OSC is enabled and output clock is valid - */ -#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) -#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) -#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) -/*! SOSCSEL - System OSC Selected - * 0b0..System OSC is not the system clock source - * 0b1..System OSC is the system clock source - */ -#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) -#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) -#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) -/*! SOSCERR - System OSC Clock Error - * 0b0..System OSC Clock Monitor is disabled or has not detected an error - * 0b1..System OSC Clock Monitor is enabled and detected an error - */ -#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) -/*! @} */ - -/*! @name SOSCDIV - System OSC Divide Register */ -/*! @{ */ -#define SCG_SOSCDIV_SOSCDIV1_MASK (0x7U) -#define SCG_SOSCDIV_SOSCDIV1_SHIFT (0U) -/*! SOSCDIV1 - System OSC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK) -#define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) -#define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) -/*! SOSCDIV2 - System OSC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) -#define SCG_SOSCDIV_SOSCDIV3_MASK (0x70000U) -#define SCG_SOSCDIV_SOSCDIV3_SHIFT (16U) -/*! SOSCDIV3 - System OSC Clock Divide 3 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SOSCDIV_SOSCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK) -/*! @} */ - -/*! @name SIRCCSR - Slow IRC Control Status Register */ -/*! @{ */ -#define SCG_SIRCCSR_SIRCEN_MASK (0x1U) -#define SCG_SIRCCSR_SIRCEN_SHIFT (0U) -/*! SIRCEN - Slow IRC Enable - * 0b0..Slow IRC is disabled - * 0b1..Slow IRC is enabled - */ -#define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) -#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) -#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) -/*! SIRCSTEN - Slow IRC Stop Enable - * 0b0..Slow IRC is disabled in Stop modes - * 0b1..Slow IRC is enabled in Stop modes - */ -#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) -#define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) -#define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) -/*! SIRCLPEN - Slow IRC Low Power Enable - * 0b0..Slow IRC is disabled in VLP modes - * 0b1..Slow IRC is enabled in VLP modes - */ -#define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) -#define SCG_SIRCCSR_LK_MASK (0x800000U) -#define SCG_SIRCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) -#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) -#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) -/*! SIRCVLD - Slow IRC Valid - * 0b0..Slow IRC is not enabled or clock is not valid - * 0b1..Slow IRC is enabled and output clock is valid - */ -#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) -#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) -#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) -/*! SIRCSEL - Slow IRC Selected - * 0b0..Slow IRC is not the system clock source - * 0b1..Slow IRC is the system clock source - */ -#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) -/*! @} */ - -/*! @name SIRCDIV - Slow IRC Divide Register */ -/*! @{ */ -#define SCG_SIRCDIV_SIRCDIV1_MASK (0x7U) -#define SCG_SIRCDIV_SIRCDIV1_SHIFT (0U) -/*! SIRCDIV1 - Slow IRC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK) -#define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) -#define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) -/*! SIRCDIV2 - Slow IRC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) -#define SCG_SIRCDIV_SIRCDIV3_MASK (0x70000U) -#define SCG_SIRCDIV_SIRCDIV3_SHIFT (16U) -/*! SIRCDIV3 - Slow IRC Clock Divider 3 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_SIRCDIV_SIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK) -/*! @} */ - -/*! @name SIRCCFG - Slow IRC Configuration Register */ -/*! @{ */ -#define SCG_SIRCCFG_RANGE_MASK (0x1U) -#define SCG_SIRCCFG_RANGE_SHIFT (0U) -/*! RANGE - Frequency Range - * 0b0..Slow IRC low range clock (2MHz) - * 0b1..Slow IRC high range clock (8 MHz) - */ -#define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) -/*! @} */ - -/*! @name FIRCCSR - Fast IRC Control Status Register */ -/*! @{ */ -#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) -#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) -/*! FIRCEN - Fast IRC Enable - * 0b0..Fast IRC is disabled - * 0b1..Fast IRC is enabled - */ -#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) -#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) -#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) -/*! FIRCSTEN - Fast IRC Stop Enable - * 0b0..Fast IRC is disabled in Stop modes. - * 0b1..Fast IRC is enabled in Stop modes - */ -#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) -#define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U) -#define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U) -/*! FIRCLPEN - Fast IRC Low Power Enable - * 0b0..Fast IRC is disabled in VLP modes - * 0b1..Fast IRC is enabled in VLP modes - */ -#define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK) -#define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) -#define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) -/*! FIRCREGOFF - Fast IRC Regulator Enable - * 0b0..Fast IRC Regulator is enabled. - * 0b1..Fast IRC Regulator is disabled. - */ -#define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) -#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) -#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) -/*! FIRCTREN - Fast IRC Trim Enable - * 0b0..Disable trimming Fast IRC to an external clock source - * 0b1..Enable trimming Fast IRC to an external clock source - */ -#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) -#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) -#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) -/*! FIRCTRUP - Fast IRC Trim Update - * 0b0..Disable Fast IRC trimming updates - * 0b1..Enable Fast IRC trimming updates - */ -#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) -#define SCG_FIRCCSR_LK_MASK (0x800000U) -#define SCG_FIRCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) -#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) -#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) -/*! FIRCVLD - Fast IRC Valid status - * 0b0..Fast IRC is not enabled or clock is not valid. - * 0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. - */ -#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) -#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) -#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) -/*! FIRCSEL - Fast IRC Selected status - * 0b0..Fast IRC is not the system clock source - * 0b1..Fast IRC is the system clock source - */ -#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) -#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) -#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) -/*! FIRCERR - Fast IRC Clock Error - * 0b0..Error not detected with the Fast IRC trimming. - * 0b1..Error detected with the Fast IRC trimming. - */ -#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) -/*! @} */ - -/*! @name FIRCDIV - Fast IRC Divide Register */ -/*! @{ */ -#define SCG_FIRCDIV_FIRCDIV1_MASK (0x7U) -#define SCG_FIRCDIV_FIRCDIV1_SHIFT (0U) -/*! FIRCDIV1 - Fast IRC Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK) -#define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) -#define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) -/*! FIRCDIV2 - Fast IRC Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) -#define SCG_FIRCDIV_FIRCDIV3_MASK (0x70000U) -#define SCG_FIRCDIV_FIRCDIV3_SHIFT (16U) -/*! FIRCDIV3 - Fast IRC Clock Divider 3 - * 0b000..Clock disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_FIRCDIV_FIRCDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK) -/*! @} */ - -/*! @name FIRCCFG - Fast IRC Configuration Register */ -/*! @{ */ -#define SCG_FIRCCFG_RANGE_MASK (0x3U) -#define SCG_FIRCCFG_RANGE_SHIFT (0U) -/*! RANGE - Frequency Range - * 0b00..Fast IRC is trimmed to 48 MHz - * 0b01..Fast IRC is trimmed to 52 MHz - * 0b10..Fast IRC is trimmed to 56 MHz - * 0b11..Fast IRC is trimmed to 60 MHz - */ -#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) -/*! @} */ - -/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */ -/*! @{ */ -#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) -#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) -/*! TRIMSRC - Trim Source - * 0b00..Reserved - * 0b01..Reserved - * 0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency slower than 32kHz. - * 0b11..RTC OSC (32.768 kHz) - */ -#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) -#define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U) -#define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U) -/*! TRIMDIV - Fast IRC Trim Predivide - * 0b000..Divide by 1 - * 0b001..Divide by 128 - * 0b010..Divide by 256 - * 0b011..Divide by 512 - * 0b100..Divide by 1024 - * 0b101..Divide by 2048 - * 0b110..Reserved. Writing this value will result in Divide by 1. - * 0b111..Reserved. Writing this value will result in a Divide by 1. - */ -#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) -/*! @} */ - -/*! @name FIRCSTAT - Fast IRC Status Register */ -/*! @{ */ -#define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU) -#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) -#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) -#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) -#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) -#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) -/*! @} */ - -/*! @name ROSCCSR - RTC OSC Control Status Register */ -/*! @{ */ -#define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) -#define SCG_ROSCCSR_ROSCCM_SHIFT (16U) -/*! ROSCCM - RTC OSC Clock Monitor - * 0b0..RTC OSC Clock Monitor is disabled - * 0b1..RTC OSC Clock Monitor is enabled - */ -#define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) -#define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) -#define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) -/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) -#define SCG_ROSCCSR_LK_MASK (0x800000U) -#define SCG_ROSCCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) -#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) -#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) -/*! ROSCVLD - RTC OSC Valid - * 0b0..RTC OSC is not enabled or clock is not valid - * 0b1..RTC OSC is enabled and output clock is valid - */ -#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) -#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) -#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) -/*! ROSCSEL - RTC OSC Selected - * 0b0..RTC OSC is not the system clock source - * 0b1..RTC OSC is the system clock source - */ -#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) -#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) -#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) -/*! ROSCERR - RTC OSC Clock Error - * 0b0..RTC OSC Clock Monitor is disabled or has not detected an error - * 0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error - */ -#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) -/*! @} */ - -/*! @name LPFLLCSR - Low Power FLL Control Status Register */ -/*! @{ */ -#define SCG_LPFLLCSR_LPFLLEN_MASK (0x1U) -#define SCG_LPFLLCSR_LPFLLEN_SHIFT (0U) -/*! LPFLLEN - LPFLL Enable - * 0b0..LPFLL is disabled - * 0b1..LPFLL is enabled - */ -#define SCG_LPFLLCSR_LPFLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK) -#define SCG_LPFLLCSR_LPFLLSTEN_MASK (0x2U) -#define SCG_LPFLLCSR_LPFLLSTEN_SHIFT (1U) -/*! LPFLLSTEN - LPFLL Stop Enable - * 0b0..LPFLL is disabled in Stop modes. - * 0b1..LPFLL is enabled in Stop modes - */ -#define SCG_LPFLLCSR_LPFLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSTEN_SHIFT)) & SCG_LPFLLCSR_LPFLLSTEN_MASK) -#define SCG_LPFLLCSR_LPFLLTREN_MASK (0x100U) -#define SCG_LPFLLCSR_LPFLLTREN_SHIFT (8U) -/*! LPFLLTREN - LPFLL Trim Enable - * 0b0..Disable trimming LPFLL to an reference clock source - * 0b1..Enable trimming LPFLL to an reference clock source - */ -#define SCG_LPFLLCSR_LPFLLTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK) -#define SCG_LPFLLCSR_LPFLLTRUP_MASK (0x200U) -#define SCG_LPFLLCSR_LPFLLTRUP_SHIFT (9U) -/*! LPFLLTRUP - LPFLL Trim Update - * 0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. - * 0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication - */ -#define SCG_LPFLLCSR_LPFLLTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK) -#define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) -#define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT (10U) -/*! LPFLLTRMLOCK - LPFLL Trim LOCK - * 0b0..LPFLL not Locked - * 0b1..LPFLL trimmed and Locked - */ -#define SCG_LPFLLCSR_LPFLLTRMLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK) -#define SCG_LPFLLCSR_LPFLLCM_MASK (0x10000U) -#define SCG_LPFLLCSR_LPFLLCM_SHIFT (16U) -/*! LPFLLCM - LPFLL Clock Monitor - * 0b0..LPFLL Clock Monitor is disabled - * 0b1..LPFLL Clock Monitor is enabled - */ -#define SCG_LPFLLCSR_LPFLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK) -#define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) -#define SCG_LPFLLCSR_LPFLLCMRE_SHIFT (17U) -/*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable - * 0b0..Clock Monitor generates interrupt when error detected - * 0b1..Clock Monitor generates reset when error detected - */ -#define SCG_LPFLLCSR_LPFLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK) -#define SCG_LPFLLCSR_LK_MASK (0x800000U) -#define SCG_LPFLLCSR_LK_SHIFT (23U) -/*! LK - Lock Register - * 0b0..Control Status Register can be written. - * 0b1..Control Status Register cannot be written. - */ -#define SCG_LPFLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK) -#define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) -#define SCG_LPFLLCSR_LPFLLVLD_SHIFT (24U) -/*! LPFLLVLD - LPFLL Valid - * 0b0..LPFLL is not enabled or clock is not valid. - * 0b1..LPFLL is enabled and output clock is valid. - */ -#define SCG_LPFLLCSR_LPFLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK) -#define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) -#define SCG_LPFLLCSR_LPFLLSEL_SHIFT (25U) -/*! LPFLLSEL - LPFLL Selected - * 0b0..LPFLL is not the system clock source - * 0b1..LPFLL is the system clock source - */ -#define SCG_LPFLLCSR_LPFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK) -#define SCG_LPFLLCSR_LPFLLERR_MASK (0x4000000U) -#define SCG_LPFLLCSR_LPFLLERR_SHIFT (26U) -/*! LPFLLERR - LPFLL Clock Error - * 0b0..Error not detected with the LPFLL trimming. - * 0b1..Error detected with the LPFLL trimming. - */ -#define SCG_LPFLLCSR_LPFLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK) -/*! @} */ - -/*! @name LPFLLDIV - Low Power FLL Divide Register */ -/*! @{ */ -#define SCG_LPFLLDIV_LPFLLDIV1_MASK (0x7U) -#define SCG_LPFLLDIV_LPFLLDIV1_SHIFT (0U) -/*! LPFLLDIV1 - LPFLL Clock Divide 1 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV1(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV1_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV1_MASK) -#define SCG_LPFLLDIV_LPFLLDIV2_MASK (0x700U) -#define SCG_LPFLLDIV_LPFLLDIV2_SHIFT (8U) -/*! LPFLLDIV2 - LPFLL Clock Divide 2 - * 0b000..Output disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK) -#define SCG_LPFLLDIV_LPFLLDIV3_MASK (0x70000U) -#define SCG_LPFLLDIV_LPFLLDIV3_SHIFT (16U) -/*! LPFLLDIV3 - LPFLL Clock Divide 3 - * 0b000..Clock disabled - * 0b001..Divide by 1 - * 0b010..Divide by 2 - * 0b011..Divide by 4 - * 0b100..Divide by 8 - * 0b101..Divide by 16 - * 0b110..Divide by 32 - * 0b111..Divide by 64 - */ -#define SCG_LPFLLDIV_LPFLLDIV3(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK) -/*! @} */ - -/*! @name LPFLLCFG - Low Power FLL Configuration Register */ -/*! @{ */ -#define SCG_LPFLLCFG_FSEL_MASK (0x3U) -#define SCG_LPFLLCFG_FSEL_SHIFT (0U) -/*! FSEL - Frequency Select - * 0b00..LPFLL is trimmed to 48 MHz. - * 0b01..LPFLL is trimmed to 72 MHz. - * 0b10..Reserved - * 0b11..Reserved - */ -#define SCG_LPFLLCFG_FSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK) -/*! @} */ - -/*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */ -/*! @{ */ -#define SCG_LPFLLTCFG_TRIMSRC_MASK (0x3U) -#define SCG_LPFLLTCFG_TRIMSRC_SHIFT (0U) -/*! TRIMSRC - Trim Source - * 0b00..SIRC - * 0b01..FIRC - * 0b10..System OSC - * 0b11..RTC OSC - */ -#define SCG_LPFLLTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK) -#define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) -#define SCG_LPFLLTCFG_TRIMDIV_SHIFT (8U) -#define SCG_LPFLLTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK) -#define SCG_LPFLLTCFG_LOCKW2LSB_MASK (0x10000U) -#define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT (16U) -/*! LOCKW2LSB - Lock LPFLL with 2 LSBS - * 0b0..LPFLL locks within 1LSB (0.4%) - * 0b1..LPFLL locks within 2LSB (0.8%) - */ -#define SCG_LPFLLTCFG_LOCKW2LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK) -/*! @} */ - -/*! @name LPFLLSTAT - Low Power FLL Status Register */ -/*! @{ */ -#define SCG_LPFLLSTAT_AUTOTRIM_MASK (0xFFU) -#define SCG_LPFLLSTAT_AUTOTRIM_SHIFT (0U) -#define SCG_LPFLLSTAT_AUTOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SCG_Register_Masks */ - - -/* SCG - Peripheral instance base addresses */ -/** Peripheral SCG base address */ -#define SCG_BASE (0x4002C000u) -/** Peripheral SCG base pointer */ -#define SCG ((SCG_Type *)SCG_BASE) -/** Array initializer of SCG peripheral base addresses */ -#define SCG_BASE_ADDRS { SCG_BASE } -/** Array initializer of SCG peripheral base pointers */ -#define SCG_BASE_PTRS { SCG } -/** Interrupt vectors for the SCG peripheral type */ -#define SCG_IRQS { SCG_IRQn } - -/*! - * @} - */ /* end of group SCG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SEMA42 Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer - * @{ - */ - -/** SEMA42 - Register Layout Typedef */ -typedef struct { - __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ - __IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */ - __IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */ - __IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */ - __IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */ - __IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */ - __IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */ - __IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */ - __IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */ - __IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */ - __IO uint8_t GATE9; /**< Gate Register, offset: 0xA */ - __IO uint8_t GATE8; /**< Gate Register, offset: 0xB */ - __IO uint8_t GATE15; /**< Gate Register, offset: 0xC */ - __IO uint8_t GATE14; /**< Gate Register, offset: 0xD */ - __IO uint8_t GATE13; /**< Gate Register, offset: 0xE */ - __IO uint8_t GATE12; /**< Gate Register, offset: 0xF */ - uint8_t RESERVED_0[50]; - union { /* offset: 0x42 */ - __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ - __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ - }; -} SEMA42_Type; - -/* ---------------------------------------------------------------------------- - -- SEMA42 Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks - * @{ - */ - -/*! @name GATE3 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE3_GTFSM_MASK (0xFU) -#define SEMA42_GATE3_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) -/*! @} */ - -/*! @name GATE2 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE2_GTFSM_MASK (0xFU) -#define SEMA42_GATE2_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) -/*! @} */ - -/*! @name GATE1 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE1_GTFSM_MASK (0xFU) -#define SEMA42_GATE1_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) -/*! @} */ - -/*! @name GATE0 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE0_GTFSM_MASK (0xFU) -#define SEMA42_GATE0_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) -/*! @} */ - -/*! @name GATE7 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE7_GTFSM_MASK (0xFU) -#define SEMA42_GATE7_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) -/*! @} */ - -/*! @name GATE6 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE6_GTFSM_MASK (0xFU) -#define SEMA42_GATE6_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) -/*! @} */ - -/*! @name GATE5 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE5_GTFSM_MASK (0xFU) -#define SEMA42_GATE5_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) -/*! @} */ - -/*! @name GATE4 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE4_GTFSM_MASK (0xFU) -#define SEMA42_GATE4_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) -/*! @} */ - -/*! @name GATE11 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE11_GTFSM_MASK (0xFU) -#define SEMA42_GATE11_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) -/*! @} */ - -/*! @name GATE10 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE10_GTFSM_MASK (0xFU) -#define SEMA42_GATE10_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) -/*! @} */ - -/*! @name GATE9 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE9_GTFSM_MASK (0xFU) -#define SEMA42_GATE9_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) -/*! @} */ - -/*! @name GATE8 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE8_GTFSM_MASK (0xFU) -#define SEMA42_GATE8_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) -/*! @} */ - -/*! @name GATE15 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE15_GTFSM_MASK (0xFU) -#define SEMA42_GATE15_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) -/*! @} */ - -/*! @name GATE14 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE14_GTFSM_MASK (0xFU) -#define SEMA42_GATE14_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) -/*! @} */ - -/*! @name GATE13 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE13_GTFSM_MASK (0xFU) -#define SEMA42_GATE13_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) -/*! @} */ - -/*! @name GATE12 - Gate Register */ -/*! @{ */ -#define SEMA42_GATE12_GTFSM_MASK (0xFU) -#define SEMA42_GATE12_GTFSM_SHIFT (0U) -/*! GTFSM - GTFSM - * 0b0000..The gate is unlocked (free). - * 0b0001..The gate has been locked by processor 0. - * 0b0010..The gate has been locked by processor 1. - * 0b0011..The gate has been locked by processor 2. - * 0b0100..The gate has been locked by processor 3. - * 0b0101..The gate has been locked by processor 4. - * 0b0110..The gate has been locked by processor 5. - * 0b0111..The gate has been locked by processor 6. - * 0b1000..The gate has been locked by processor 7. - * 0b1001..The gate has been locked by processor 8. - * 0b1010..The gate has been locked by processor 9. - * 0b1011..The gate has been locked by processor 10. - * 0b1100..The gate has been locked by processor 11. - * 0b1101..The gate has been locked by processor 12. - * 0b1110..The gate has been locked by processor 13. - * 0b1111..The gate has been locked by processor 14. - */ -#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) -/*! @} */ - -/*! @name RSTGT_R - Reset Gate Read */ -/*! @{ */ -#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) -#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) -#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) -#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) -#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) -#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) -#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) -#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) -/*! RSTGSM - RSTGSM - * 0b00..Idle, waiting for the first data pattern write. - * 0b01..Waiting for the second data pattern write. - * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state. - * 0b11..This state encoding is never used and therefore reserved. - */ -#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) -#define SEMA42_RSTGT_R_ROZ_MASK (0xC000U) -#define SEMA42_RSTGT_R_ROZ_SHIFT (14U) -#define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK) -/*! @} */ - -/*! @name RSTGT_W - Reset Gate Write */ -/*! @{ */ -#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) -#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) -#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) -#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) -#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) -#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SEMA42_Register_Masks */ - - -/* SEMA42 - Peripheral instance base addresses */ -/** Peripheral SEMA420 base address */ -#define SEMA420_BASE (0x4001B000u) -/** Peripheral SEMA420 base pointer */ -#define SEMA420 ((SEMA42_Type *)SEMA420_BASE) -/** Peripheral SEMA421 base address */ -#define SEMA421_BASE (0x4101B000u) -/** Peripheral SEMA421 base pointer */ -#define SEMA421 ((SEMA42_Type *)SEMA421_BASE) -/** Array initializer of SEMA42 peripheral base addresses */ -#define SEMA42_BASE_ADDRS { SEMA420_BASE, SEMA421_BASE } -/** Array initializer of SEMA42 peripheral base pointers */ -#define SEMA42_BASE_PTRS { SEMA420, SEMA421 } - -/*! - * @} - */ /* end of group SEMA42_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer - * @{ - */ - -/** SIM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __IO uint32_t CHIPCTRL; /**< Chip Control Register, offset: 0x4 */ - uint8_t RESERVED_1[28]; - __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ - uint8_t RESERVED_2[36]; - __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ - __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x50 */ - uint8_t RESERVED_3[4]; - __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x58 */ - __I uint32_t UIDM; /**< Unique Identification Register Mid Middle, offset: 0x5C */ - __I uint32_t UIDL; /**< Unique Identification Register Mid Low, offset: 0x60 */ - __I uint32_t RFADDRL; /**< RF Mac Address Low, offset: 0x64 */ - __I uint32_t RFADDRH; /**< RF MAC Address High, offset: 0x68 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MISC2; /**< MISC2 Register, offset: 0x70 */ -} SIM_Type; - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/*! @name CHIPCTRL - Chip Control Register */ -/*! @{ */ -#define SIM_CHIPCTRL_FBSL_MASK (0x300U) -#define SIM_CHIPCTRL_FBSL_SHIFT (8U) -/*! FBSL - FLEXBUS security level - * 0b00..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed - * 0b01..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed - * 0b10..off-chip instruction access are disallowed, data access are allowed - * 0b11..off-chip instruction access and data access are allowed - */ -#define SIM_CHIPCTRL_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTRL_FBSL_SHIFT)) & SIM_CHIPCTRL_FBSL_MASK) -/*! @} */ - -/*! @name SDID - System Device Identification Register */ -/*! @{ */ -#define SIM_SDID_PINID_MASK (0xFU) -#define SIM_SDID_PINID_SHIFT (0U) -/*! PINID - PINID - * 0b1000..176-pin - * 0b1101..191-pin - */ -#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) -#define SIM_SDID_DIEID_MASK (0xF80U) -#define SIM_SDID_DIEID_SHIFT (7U) -#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) -#define SIM_SDID_REVID_MASK (0xF000U) -#define SIM_SDID_REVID_SHIFT (12U) -#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) -#define SIM_SDID_SERIESID_MASK (0xF00000U) -#define SIM_SDID_SERIESID_SHIFT (20U) -#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) -#define SIM_SDID_SUBFAMID_MASK (0xF000000U) -#define SIM_SDID_SUBFAMID_SHIFT (24U) -/*! SUBFAMID - SUBFAMID - * 0b0010..02 - * 0b0011..03 - * 0b0100..04 - */ -#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) -#define SIM_SDID_FAMID_MASK (0xF0000000U) -#define SIM_SDID_FAMID_SHIFT (28U) -/*! FAMID - FAMID - * 0b0000..RV32M1 - */ -#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) -/*! @} */ - -/*! @name FCFG1 - Flash Configuration Register 1 */ -/*! @{ */ -#define SIM_FCFG1_FLASHDIS_MASK (0x1U) -#define SIM_FCFG1_FLASHDIS_SHIFT (0U) -/*! FLASHDIS - Flash disable - * 0b0..Flash is enabled - * 0b1..Flash is disabled - */ -#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) -#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) -#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) -/*! FLASHDOZE - Flash Doze - * 0b0..Flash remains enabled during Doze mode - * 0b1..Flash is disabled for the duration of Doze mode - */ -#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) -#define SIM_FCFG1_FLSAUTODISEN_MASK (0x4U) -#define SIM_FCFG1_FLSAUTODISEN_SHIFT (2U) -/*! FLSAUTODISEN - Flash auto disable enabled. - * 0b0..Disable flash auto disable function - * 0b1..Enable flash auto disable function - */ -#define SIM_FCFG1_FLSAUTODISEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK) -#define SIM_FCFG1_FLSAUTODISWD_MASK (0x3FF8U) -#define SIM_FCFG1_FLSAUTODISWD_SHIFT (3U) -#define SIM_FCFG1_FLSAUTODISWD(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK) -#define SIM_FCFG1_CORE1_SRAMSIZE_MASK (0xF0000U) -#define SIM_FCFG1_CORE1_SRAMSIZE_SHIFT (16U) -/*! CORE1_SRAMSIZE - * 0b1001..CM0+ has 128 KB SRAM - */ -#define SIM_FCFG1_CORE1_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE1_SRAMSIZE_MASK) -#define SIM_FCFG1_CORE0_SRAMSIZE_MASK (0xF00000U) -#define SIM_FCFG1_CORE0_SRAMSIZE_SHIFT (20U) -/*! CORE0_SRAMSIZE - * 0b1010..CM4 has 256 KB SRAM - */ -#define SIM_FCFG1_CORE0_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE0_SRAMSIZE_MASK) -#define SIM_FCFG1_CORE1_PFSIZE_MASK (0xF000000U) -#define SIM_FCFG1_CORE1_PFSIZE_SHIFT (24U) -/*! CORE1_PFSIZE - * 0b1010..CM0+ has 256 KB flash size. - */ -#define SIM_FCFG1_CORE1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_PFSIZE_SHIFT)) & SIM_FCFG1_CORE1_PFSIZE_MASK) -#define SIM_FCFG1_CORE0_PFSIZE_MASK (0xF0000000U) -#define SIM_FCFG1_CORE0_PFSIZE_SHIFT (28U) -/*! CORE0_PFSIZE - * 0b1100..CM4 has 1 MB flash size. - */ -#define SIM_FCFG1_CORE0_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_PFSIZE_SHIFT)) & SIM_FCFG1_CORE0_PFSIZE_MASK) -/*! @} */ - -/*! @name FCFG2 - Flash Configuration Register 2 */ -/*! @{ */ -#define SIM_FCFG2_MAXADDR2_MASK (0x3F0000U) -#define SIM_FCFG2_MAXADDR2_SHIFT (16U) -#define SIM_FCFG2_MAXADDR2(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK) -#define SIM_FCFG2_MAXADDR01_MASK (0x7F000000U) -#define SIM_FCFG2_MAXADDR01_SHIFT (24U) -#define SIM_FCFG2_MAXADDR01(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR01_SHIFT)) & SIM_FCFG2_MAXADDR01_MASK) -#define SIM_FCFG2_SWAP_MASK (0x80000000U) -#define SIM_FCFG2_SWAP_SHIFT (31U) -/*! SWAP - SWAP - * 0b0..Logical P-flash Block 0 is located at relative address 0x0000 - * 0b1..Logical P-flash Block 1 is located at relative address 0x0000 - */ -#define SIM_FCFG2_SWAP(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAP_SHIFT)) & SIM_FCFG2_SWAP_MASK) -/*! @} */ - -/*! @name UIDH - Unique Identification Register High */ -/*! @{ */ -#define SIM_UIDH_UID_MASK (0xFFFFU) -#define SIM_UIDH_UID_SHIFT (0U) -#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) -/*! @} */ - -/*! @name UIDM - Unique Identification Register Mid Middle */ -/*! @{ */ -#define SIM_UIDM_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDM_UID_SHIFT (0U) -#define SIM_UIDM_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDM_UID_SHIFT)) & SIM_UIDM_UID_MASK) -/*! @} */ - -/*! @name UIDL - Unique Identification Register Mid Low */ -/*! @{ */ -#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) -#define SIM_UIDL_UID_SHIFT (0U) -#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) -/*! @} */ - -/*! @name RFADDRL - RF Mac Address Low */ -/*! @{ */ -#define SIM_RFADDRL_MACADDR0_MASK (0xFFU) -#define SIM_RFADDRL_MACADDR0_SHIFT (0U) -#define SIM_RFADDRL_MACADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR0_SHIFT)) & SIM_RFADDRL_MACADDR0_MASK) -#define SIM_RFADDRL_MACADDR1_MASK (0xFF00U) -#define SIM_RFADDRL_MACADDR1_SHIFT (8U) -#define SIM_RFADDRL_MACADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR1_SHIFT)) & SIM_RFADDRL_MACADDR1_MASK) -#define SIM_RFADDRL_MACADDR2_MASK (0xFF0000U) -#define SIM_RFADDRL_MACADDR2_SHIFT (16U) -#define SIM_RFADDRL_MACADDR2(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR2_SHIFT)) & SIM_RFADDRL_MACADDR2_MASK) -#define SIM_RFADDRL_MACADDR3_MASK (0xFF000000U) -#define SIM_RFADDRL_MACADDR3_SHIFT (24U) -#define SIM_RFADDRL_MACADDR3(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR3_SHIFT)) & SIM_RFADDRL_MACADDR3_MASK) -/*! @} */ - -/*! @name RFADDRH - RF MAC Address High */ -/*! @{ */ -#define SIM_RFADDRH_MACADDR4_MASK (0xFFU) -#define SIM_RFADDRH_MACADDR4_SHIFT (0U) -#define SIM_RFADDRH_MACADDR4(x) (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRH_MACADDR4_SHIFT)) & SIM_RFADDRH_MACADDR4_MASK) -/*! @} */ - -/*! @name MISC2 - MISC2 Register */ -/*! @{ */ -#define SIM_MISC2_SYSTICK_CLK_EN_MASK (0x1U) -#define SIM_MISC2_SYSTICK_CLK_EN_SHIFT (0U) -/*! systick_clk_en - Systick clock enable - * 0b0..Systick clock is disabled - * 0b1..Systick clock is enabled - */ -#define SIM_MISC2_SYSTICK_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC2_SYSTICK_CLK_EN_SHIFT)) & SIM_MISC2_SYSTICK_CLK_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SIM_Register_Masks */ - - -/* SIM - Peripheral instance base addresses */ -/** Peripheral SIM base address */ -#define SIM_BASE (0x40026000u) -/** Peripheral SIM base pointer */ -#define SIM ((SIM_Type *)SIM_BASE) -/** Array initializer of SIM peripheral base addresses */ -#define SIM_BASE_ADDRS { SIM_BASE } -/** Array initializer of SIM peripheral base pointers */ -#define SIM_BASE_PTRS { SIM } - -/*! - * @} - */ /* end of group SIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer - * @{ - */ - -/** SMC - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0x10 */ - uint8_t RESERVED_1[4]; - __IO uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x18 */ - uint8_t RESERVED_2[4]; - __I uint32_t SRS; /**< System Reset Status, offset: 0x20 */ - __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x24 */ - __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x28 */ - __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x2C */ - __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x30 */ - uint8_t RESERVED_3[12]; - __IO uint32_t MR; /**< Mode Register, offset: 0x40 */ - uint8_t RESERVED_4[12]; - __IO uint32_t FM; /**< Force Mode Register, offset: 0x50 */ - uint8_t RESERVED_5[12]; - __IO uint32_t SRAMLPR; /**< SRAM Low Power Register, offset: 0x60 */ - __IO uint32_t SRAMDSR; /**< SRAM Deep Sleep Register, offset: 0x64 */ -} SMC_Type; - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SMC_VERID_FEATURE_MASK (0xFFFFU) -#define SMC_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000010101011..Default features supported - */ -#define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) -#define SMC_VERID_MINOR_MASK (0xFF0000U) -#define SMC_VERID_MINOR_SHIFT (16U) -#define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) -#define SMC_VERID_MAJOR_MASK (0xFF000000U) -#define SMC_VERID_MAJOR_SHIFT (24U) -#define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define SMC_PARAM_PWRD_INDPT_MASK (0x1U) -#define SMC_PARAM_PWRD_INDPT_SHIFT (0U) -#define SMC_PARAM_PWRD_INDPT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_PWRD_INDPT_SHIFT)) & SMC_PARAM_PWRD_INDPT_MASK) -/*! @} */ - -/*! @name PMPROT - Power Mode Protection register */ -/*! @{ */ -#define SMC_PMPROT_AVLLS_MASK (0x3U) -#define SMC_PMPROT_AVLLS_SHIFT (0U) -/*! AVLLS - Allow Very-Low-Leakage Stop Mode - * 0b00..VLLS mode is not allowed - * 0b01..VLLS0/1 mode is allowed - * 0b10..VLLS2/3 mode is allowed - * 0b11..VLLS0/1/2/3 mode is allowed - */ -#define SMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) -#define SMC_PMPROT_ALLS_MASK (0x8U) -#define SMC_PMPROT_ALLS_SHIFT (3U) -/*! ALLS - Allow Low-Leakage Stop Mode - * 0b0..LLS is not allowed - * 0b1..LLS is allowed - */ -#define SMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) -#define SMC_PMPROT_AVLP_MASK (0x20U) -#define SMC_PMPROT_AVLP_SHIFT (5U) -/*! AVLP - Allow Very-Low-Power Modes - * 0b0..VLPR, VLPW, and VLPS are not allowed. - * 0b1..VLPR, VLPW, and VLPS are allowed. - */ -#define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) -#define SMC_PMPROT_AHSRUN_MASK (0x80U) -#define SMC_PMPROT_AHSRUN_SHIFT (7U) -/*! AHSRUN - Allow High Speed Run mode - * 0b0..HSRUN is not allowed - * 0b1..HSRUN is allowed - */ -#define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) -/*! @} */ - -/*! @name PMCTRL - Power Mode Control register */ -/*! @{ */ -#define SMC_PMCTRL_STOPM_MASK (0x7U) -#define SMC_PMCTRL_STOPM_SHIFT (0U) -/*! STOPM - Stop Mode Control - * 0b000..Normal Stop (STOP) - * 0b001..Reserved - * 0b010..Very-Low-Power Stop (VLPS) - * 0b011..Low-Leakage Stop (LLS) - * 0b100..Very-Low-Leakage Stop with SRAM retention(VLLS2/3) - * 0b101..Reserved - * 0b110..Very-Low-Leakage Stop without SRAM retention (VLLS0/1) - * 0b111..Reserved - */ -#define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) -#define SMC_PMCTRL_RUNM_MASK (0x300U) -#define SMC_PMCTRL_RUNM_SHIFT (8U) -/*! RUNM - Run Mode Control - * 0b00..Normal Run mode (RUN) - * 0b01..Reserved - * 0b10..Very-Low-Power Run mode (VLPR) - * 0b11..High Speed Run mode (HSRUN) - */ -#define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) -#define SMC_PMCTRL_PSTOPO_MASK (0x30000U) -#define SMC_PMCTRL_PSTOPO_SHIFT (16U) -/*! PSTOPO - Partial Stop Option - * 0b00..STOP - Normal Stop mode - * 0b01..PSTOP1 - Partial Stop with system and bus clock disabled - * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled - * 0b11..PSTOP3 - Partial Stop with system clock enabled and bus clock enabled - */ -#define SMC_PMCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_PSTOPO_SHIFT)) & SMC_PMCTRL_PSTOPO_MASK) -/*! @} */ - -/*! @name PMSTAT - Power Mode Status register */ -/*! @{ */ -#define SMC_PMSTAT_PMSTAT_MASK (0xFFU) -#define SMC_PMSTAT_PMSTAT_SHIFT (0U) -/*! PMSTAT - Power Mode Status - * 0b00000001..Current power mode is RUN. - * 0b00000010..Current power mode is any STOP mode. - * 0b00000100..Current power mode is VLPR. - * 0b10000000..Current power mode is HSRUN - */ -#define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) -#define SMC_PMSTAT_STOPSTAT_MASK (0xFF000000U) -#define SMC_PMSTAT_STOPSTAT_SHIFT (24U) -#define SMC_PMSTAT_STOPSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_STOPSTAT_SHIFT)) & SMC_PMSTAT_STOPSTAT_MASK) -/*! @} */ - -/*! @name SRS - System Reset Status */ -/*! @{ */ -#define SMC_SRS_WAKEUP_MASK (0x1U) -#define SMC_SRS_WAKEUP_SHIFT (0U) -/*! WAKEUP - Wakeup Reset - * 0b0..Reset not generated by wakeup from VLLS mode. - * 0b1..Reset generated by wakeup from VLLS mode. - */ -#define SMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WAKEUP_SHIFT)) & SMC_SRS_WAKEUP_MASK) -#define SMC_SRS_POR_MASK (0x2U) -#define SMC_SRS_POR_SHIFT (1U) -/*! POR - POR Reset - * 0b0..Reset not generated by POR. - * 0b1..Reset generated by POR. - */ -#define SMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_POR_SHIFT)) & SMC_SRS_POR_MASK) -#define SMC_SRS_LVD_MASK (0x4U) -#define SMC_SRS_LVD_SHIFT (2U) -/*! LVD - LVD Reset - * 0b0..Reset not generated by LVD. - * 0b1..Reset generated by LVD. - */ -#define SMC_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LVD_SHIFT)) & SMC_SRS_LVD_MASK) -#define SMC_SRS_HVD_MASK (0x8U) -#define SMC_SRS_HVD_SHIFT (3U) -/*! HVD - HVD Reset - * 0b0..Reset not generated by HVD. - * 0b1..Reset generated by HVD. - */ -#define SMC_SRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_HVD_SHIFT)) & SMC_SRS_HVD_MASK) -#define SMC_SRS_WARM_MASK (0x10U) -#define SMC_SRS_WARM_SHIFT (4U) -/*! WARM - Warm Reset - * 0b0..Reset not generated by Warm Reset source. - * 0b1..Reset generated by Warm Reset source. - */ -#define SMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WARM_SHIFT)) & SMC_SRS_WARM_MASK) -#define SMC_SRS_FATAL_MASK (0x20U) -#define SMC_SRS_FATAL_SHIFT (5U) -/*! FATAL - Fatal Reset - * 0b0..Reset was not generated by a fatal reset source. - * 0b1..Reset was generated by a fatal reset source. - */ -#define SMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_FATAL_SHIFT)) & SMC_SRS_FATAL_MASK) -#define SMC_SRS_CORE_MASK (0x80U) -#define SMC_SRS_CORE_SHIFT (7U) -/*! CORE - Core Reset - * 0b0..Reset source was not core only reset. - * 0b1..Reset source was core reset and reset the core only. - */ -#define SMC_SRS_CORE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE_SHIFT)) & SMC_SRS_CORE_MASK) -#define SMC_SRS_PIN_MASK (0x100U) -#define SMC_SRS_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset was not generated from the assertion of RESET_B pin. - * 0b1..Reset was generated from the assertion of RESET_B pin. - */ -#define SMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_PIN_SHIFT)) & SMC_SRS_PIN_MASK) -#define SMC_SRS_MDM_MASK (0x200U) -#define SMC_SRS_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset was not generated from the MDM reset request. - * 0b1..Reset was generated from the MDM reset request. - */ -#define SMC_SRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_MDM_SHIFT)) & SMC_SRS_MDM_MASK) -#define SMC_SRS_RSTACK_MASK (0x400U) -#define SMC_SRS_RSTACK_SHIFT (10U) -/*! RSTACK - Reset Timeout - * 0b0..Reset not generated from Reset Controller Timeout. - * 0b1..Reset generated from Reset Controller Timeout. - */ -#define SMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_RSTACK_SHIFT)) & SMC_SRS_RSTACK_MASK) -#define SMC_SRS_STOPACK_MASK (0x800U) -#define SMC_SRS_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset not generated by Stop Controller Timeout. - * 0b1..Reset generated by Stop Controller Timeout. - */ -#define SMC_SRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_STOPACK_SHIFT)) & SMC_SRS_STOPACK_MASK) -#define SMC_SRS_SCG_MASK (0x1000U) -#define SMC_SRS_SCG_SHIFT (12U) -/*! SCG - SCG Reset - * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. - * 0b1..Reset is generated from an SCG loss of lock or loss of clock. - */ -#define SMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK) -#define SMC_SRS_WDOG_MASK (0x2000U) -#define SMC_SRS_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset is not generated from the WatchDog timeout. - * 0b1..Reset is generated from the WatchDog timeout. - */ -#define SMC_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WDOG_SHIFT)) & SMC_SRS_WDOG_MASK) -#define SMC_SRS_SW_MASK (0x4000U) -#define SMC_SRS_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset not generated by software request from core. - * 0b1..Reset generated by software request from core. - */ -#define SMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SW_SHIFT)) & SMC_SRS_SW_MASK) -#define SMC_SRS_LOCKUP_MASK (0x8000U) -#define SMC_SRS_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset not generated by core lockup or exception. - * 0b1..Reset generated by core lockup or exception. - */ -#define SMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LOCKUP_SHIFT)) & SMC_SRS_LOCKUP_MASK) -#define SMC_SRS_CORE0_MASK (0x10000U) -#define SMC_SRS_CORE0_SHIFT (16U) -/*! CORE0 - Core0 System Reset - * 0b0..Reset not generated from Core0 system reset source. - * 0b1..Reset generated from Core0 system reset source. - */ -#define SMC_SRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE0_SHIFT)) & SMC_SRS_CORE0_MASK) -#define SMC_SRS_CORE1_MASK (0x20000U) -#define SMC_SRS_CORE1_SHIFT (17U) -/*! CORE1 - Core1 System Reset - * 0b0..Reset not generated from Core1 system reset source. - * 0b1..Reset generated from Core1 system reset source. - */ -#define SMC_SRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE1_SHIFT)) & SMC_SRS_CORE1_MASK) -#define SMC_SRS_JTAG_MASK (0x10000000U) -#define SMC_SRS_JTAG_SHIFT (28U) -/*! JTAG - JTAG System Reset - * 0b0..Reset not generated by JTAG system reset. - * 0b1..Reset generated by JTAG system reset. - */ -#define SMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRS_JTAG_SHIFT)) & SMC_SRS_JTAG_MASK) -/*! @} */ - -/*! @name RPC - Reset Pin Control */ -/*! @{ */ -#define SMC_RPC_FILTCFG_MASK (0x1FU) -#define SMC_RPC_FILTCFG_SHIFT (0U) -#define SMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTCFG_SHIFT)) & SMC_RPC_FILTCFG_MASK) -#define SMC_RPC_FILTEN_MASK (0x100U) -#define SMC_RPC_FILTEN_SHIFT (8U) -/*! FILTEN - Filter Enable - * 0b0..Slow clock reset pin filter disabled. - * 0b1..Slow clock reset pin filter enabled in Run modes. - */ -#define SMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTEN_SHIFT)) & SMC_RPC_FILTEN_MASK) -#define SMC_RPC_LPOFEN_MASK (0x200U) -#define SMC_RPC_LPOFEN_SHIFT (9U) -/*! LPOFEN - LPO Filter Enable - * 0b0..LPO clock reset pin filter disabled. - * 0b1..LPO clock reset pin filter enabled in all modes. - */ -#define SMC_RPC_LPOFEN(x) (((uint32_t)(((uint32_t)(x)) << SMC_RPC_LPOFEN_SHIFT)) & SMC_RPC_LPOFEN_MASK) -/*! @} */ - -/*! @name SSRS - Sticky System Reset Status */ -/*! @{ */ -#define SMC_SSRS_WAKEUP_MASK (0x1U) -#define SMC_SSRS_WAKEUP_SHIFT (0U) -/*! WAKEUP - Wakeup Reset - * 0b0..Reset not generated by wakeup from VLLS mode. - * 0b1..Reset generated by wakeup from VLLS mode. - */ -#define SMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WAKEUP_SHIFT)) & SMC_SSRS_WAKEUP_MASK) -#define SMC_SSRS_POR_MASK (0x2U) -#define SMC_SSRS_POR_SHIFT (1U) -/*! POR - POR Reset - * 0b0..Reset not generated by POR. - * 0b1..Reset generated by POR. - */ -#define SMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_POR_SHIFT)) & SMC_SSRS_POR_MASK) -#define SMC_SSRS_LVD_MASK (0x4U) -#define SMC_SSRS_LVD_SHIFT (2U) -/*! LVD - LVD Reset - * 0b0..Reset not generated by LVD. - * 0b1..Reset generated by LVD. - */ -#define SMC_SSRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LVD_SHIFT)) & SMC_SSRS_LVD_MASK) -#define SMC_SSRS_HVD_MASK (0x8U) -#define SMC_SSRS_HVD_SHIFT (3U) -/*! HVD - HVD Reset - * 0b0..Reset not generated by HVD. - * 0b1..Reset generated by HVD. - */ -#define SMC_SSRS_HVD(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_HVD_SHIFT)) & SMC_SSRS_HVD_MASK) -#define SMC_SSRS_WARM_MASK (0x10U) -#define SMC_SSRS_WARM_SHIFT (4U) -/*! WARM - Warm Reset - * 0b0..Reset not generated by system reset source. - * 0b1..Reset generated by system reset source. - */ -#define SMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WARM_SHIFT)) & SMC_SSRS_WARM_MASK) -#define SMC_SSRS_FATAL_MASK (0x20U) -#define SMC_SSRS_FATAL_SHIFT (5U) -/*! FATAL - Fatal Reset - * 0b0..Reset was not generated by a fatal reset source. - * 0b1..Reset was generated by a fatal reset source. - */ -#define SMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_FATAL_SHIFT)) & SMC_SSRS_FATAL_MASK) -#define SMC_SSRS_PIN_MASK (0x100U) -#define SMC_SSRS_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset was not generated from the RESET_B pin. - * 0b1..Reset was generated from the RESET_B pin. - */ -#define SMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_PIN_SHIFT)) & SMC_SSRS_PIN_MASK) -#define SMC_SSRS_MDM_MASK (0x200U) -#define SMC_SSRS_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset was not generated from the MDM reset request. - * 0b1..Reset was generated from the MDM reset request. - */ -#define SMC_SSRS_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_MDM_SHIFT)) & SMC_SSRS_MDM_MASK) -#define SMC_SSRS_RSTACK_MASK (0x400U) -#define SMC_SSRS_RSTACK_SHIFT (10U) -/*! RSTACK - Reset Timeout - * 0b0..Reset not generated from Reset Controller Timeout. - * 0b1..Reset generated from Reset Controller Timeout. - */ -#define SMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_RSTACK_SHIFT)) & SMC_SSRS_RSTACK_MASK) -#define SMC_SSRS_STOPACK_MASK (0x800U) -#define SMC_SSRS_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset not generated by Stop Controller Timeout. - * 0b1..Reset generated by Stop Controller Timeout. - */ -#define SMC_SSRS_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_STOPACK_SHIFT)) & SMC_SSRS_STOPACK_MASK) -#define SMC_SSRS_SCG_MASK (0x1000U) -#define SMC_SSRS_SCG_SHIFT (12U) -/*! SCG - SCG Reset - * 0b0..Reset is not generated from an SCG loss of lock or loss of clock. - * 0b1..Reset is generated from an SCG loss of lock or loss of clock. - */ -#define SMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK) -#define SMC_SSRS_WDOG_MASK (0x2000U) -#define SMC_SSRS_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset is not generated from the WatchDog timeout. - * 0b1..Reset is generated from the WatchDog timeout. - */ -#define SMC_SSRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WDOG_SHIFT)) & SMC_SSRS_WDOG_MASK) -#define SMC_SSRS_SW_MASK (0x4000U) -#define SMC_SSRS_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset not generated by software request from core. - * 0b1..Reset generated by software request from core. - */ -#define SMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SW_SHIFT)) & SMC_SSRS_SW_MASK) -#define SMC_SSRS_LOCKUP_MASK (0x8000U) -#define SMC_SSRS_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset not generated by core lockup. - * 0b1..Reset generated by core lockup. - */ -#define SMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LOCKUP_SHIFT)) & SMC_SSRS_LOCKUP_MASK) -#define SMC_SSRS_CORE0_MASK (0x10000U) -#define SMC_SSRS_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Reset not generated from Core0 reset source. - * 0b1..Reset generated from Core0 reset source. - */ -#define SMC_SSRS_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE0_SHIFT)) & SMC_SSRS_CORE0_MASK) -#define SMC_SSRS_CORE1_MASK (0x20000U) -#define SMC_SSRS_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Reset not generated from Core1 reset source. - * 0b1..Reset generated from Core1 reset source. - */ -#define SMC_SSRS_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE1_SHIFT)) & SMC_SSRS_CORE1_MASK) -#define SMC_SSRS_JTAG_MASK (0x10000000U) -#define SMC_SSRS_JTAG_SHIFT (28U) -/*! JTAG - JTAG System Reset - * 0b0..Reset not generated by JTAG system reset. - * 0b1..Reset generated by JTAG system reset. - */ -#define SMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_JTAG_SHIFT)) & SMC_SSRS_JTAG_MASK) -/*! @} */ - -/*! @name SRIE - System Reset Interrupt Enable */ -/*! @{ */ -#define SMC_SRIE_PIN_MASK (0x100U) -#define SMC_SRIE_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_PIN_SHIFT)) & SMC_SRIE_PIN_MASK) -#define SMC_SRIE_MDM_MASK (0x200U) -#define SMC_SRIE_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_MDM_SHIFT)) & SMC_SRIE_MDM_MASK) -#define SMC_SRIE_STOPACK_MASK (0x800U) -#define SMC_SRIE_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_STOPACK_SHIFT)) & SMC_SRIE_STOPACK_MASK) -#define SMC_SRIE_WDOG_MASK (0x2000U) -#define SMC_SRIE_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_WDOG_SHIFT)) & SMC_SRIE_WDOG_MASK) -#define SMC_SRIE_SW_MASK (0x4000U) -#define SMC_SRIE_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_SW_SHIFT)) & SMC_SRIE_SW_MASK) -#define SMC_SRIE_LOCKUP_MASK (0x8000U) -#define SMC_SRIE_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_LOCKUP_SHIFT)) & SMC_SRIE_LOCKUP_MASK) -#define SMC_SRIE_CORE0_MASK (0x10000U) -#define SMC_SRIE_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE0_SHIFT)) & SMC_SRIE_CORE0_MASK) -#define SMC_SRIE_CORE1_MASK (0x20000U) -#define SMC_SRIE_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Interrupt disabled. - * 0b1..Interrupt enabled. - */ -#define SMC_SRIE_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE1_SHIFT)) & SMC_SRIE_CORE1_MASK) -/*! @} */ - -/*! @name SRIF - System Reset Interrupt Flag */ -/*! @{ */ -#define SMC_SRIF_PIN_MASK (0x100U) -#define SMC_SRIF_PIN_SHIFT (8U) -/*! PIN - Pin Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_PIN_SHIFT)) & SMC_SRIF_PIN_MASK) -#define SMC_SRIF_MDM_MASK (0x200U) -#define SMC_SRIF_MDM_SHIFT (9U) -/*! MDM - MDM Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_MDM(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_MDM_SHIFT)) & SMC_SRIF_MDM_MASK) -#define SMC_SRIF_STOPACK_MASK (0x800U) -#define SMC_SRIF_STOPACK_SHIFT (11U) -/*! STOPACK - Stop Timeout Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_STOPACK(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_STOPACK_SHIFT)) & SMC_SRIF_STOPACK_MASK) -#define SMC_SRIF_WDOG_MASK (0x2000U) -#define SMC_SRIF_WDOG_SHIFT (13U) -/*! WDOG - Watchdog Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_WDOG_SHIFT)) & SMC_SRIF_WDOG_MASK) -#define SMC_SRIF_SW_MASK (0x4000U) -#define SMC_SRIF_SW_SHIFT (14U) -/*! SW - Software Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_SW_SHIFT)) & SMC_SRIF_SW_MASK) -#define SMC_SRIF_LOCKUP_MASK (0x8000U) -#define SMC_SRIF_LOCKUP_SHIFT (15U) -/*! LOCKUP - Lockup Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_LOCKUP_SHIFT)) & SMC_SRIF_LOCKUP_MASK) -#define SMC_SRIF_CORE0_MASK (0x10000U) -#define SMC_SRIF_CORE0_SHIFT (16U) -/*! CORE0 - Core0 Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_CORE0(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE0_SHIFT)) & SMC_SRIF_CORE0_MASK) -#define SMC_SRIF_CORE1_MASK (0x20000U) -#define SMC_SRIF_CORE1_SHIFT (17U) -/*! CORE1 - Core1 Reset - * 0b0..Reset source not pending. - * 0b1..Reset source pending. - */ -#define SMC_SRIF_CORE1(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE1_SHIFT)) & SMC_SRIF_CORE1_MASK) -/*! @} */ - -/*! @name MR - Mode Register */ -/*! @{ */ -#define SMC_MR_BOOTCFG_MASK (0x3U) -#define SMC_MR_BOOTCFG_SHIFT (0U) -/*! BOOTCFG - Boot Configuration - * 0b00..Boot from Flash. - * 0b01..Boot from ROM due to BOOTCFG0 pin assertion. - * 0b10..Boot from ROM due to FOPT configuration. - * 0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration. - */ -#define SMC_MR_BOOTCFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_MR_BOOTCFG_SHIFT)) & SMC_MR_BOOTCFG_MASK) -/*! @} */ - -/*! @name FM - Force Mode Register */ -/*! @{ */ -#define SMC_FM_FORCECFG_MASK (0x3U) -#define SMC_FM_FORCECFG_SHIFT (0U) -/*! FORCECFG - Boot Configuration - * 0b00..No effect. - * 0b01..Assert corresponding bit in Mode Register on next system reset. - */ -#define SMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << SMC_FM_FORCECFG_SHIFT)) & SMC_FM_FORCECFG_MASK) -/*! @} */ - -/*! @name SRAMLPR - SRAM Low Power Register */ -/*! @{ */ -#define SMC_SRAMLPR_LPE_MASK (0xFFFFFFFFU) -#define SMC_SRAMLPR_LPE_SHIFT (0U) -#define SMC_SRAMLPR_LPE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRAMLPR_LPE_SHIFT)) & SMC_SRAMLPR_LPE_MASK) -/*! @} */ - -/*! @name SRAMDSR - SRAM Deep Sleep Register */ -/*! @{ */ -#define SMC_SRAMDSR_DSE_MASK (0xFFFFFFFFU) -#define SMC_SRAMDSR_DSE_SHIFT (0U) -#define SMC_SRAMDSR_DSE(x) (((uint32_t)(((uint32_t)(x)) << SMC_SRAMDSR_DSE_SHIFT)) & SMC_SRAMDSR_DSE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SMC_Register_Masks */ - - -/* SMC - Peripheral instance base addresses */ -/** Peripheral SMC0 base address */ -#define SMC0_BASE (0x40020000u) -/** Peripheral SMC0 base pointer */ -#define SMC0 ((SMC_Type *)SMC0_BASE) -/** Peripheral SMC1 base address */ -#define SMC1_BASE (0x41020000u) -/** Peripheral SMC1 base pointer */ -#define SMC1 ((SMC_Type *)SMC1_BASE) -/** Array initializer of SMC peripheral base addresses */ -#define SMC_BASE_ADDRS { SMC0_BASE, SMC1_BASE } -/** Array initializer of SMC peripheral base pointers */ -#define SMC_BASE_PTRS { SMC0, SMC1 } -/** Interrupt vectors for the SMC peripheral type */ -#define SMC_IRQS { NotAvail_IRQn, CMC1_IRQn } - -/*! - * @} - */ /* end of group SMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPM_Peripheral_Access_Layer SPM Peripheral Access Layer - * @{ - */ - -/** SPM - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t RSR; /**< Regulator Status Register, offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RCTRL; /**< Run Control Register, offset: 0x10 */ - __IO uint32_t LPCTRL; /**< Low Power Control Register, offset: 0x14 */ - uint8_t RESERVED_2[232]; - __IO uint32_t CORERCNFG; /**< CORE LDO RUN Configuration Register, offset: 0x100 */ - __IO uint32_t CORELPCNFG; /**< CORE LDO Low Power Configuration register, offset: 0x104 */ - __IO uint32_t CORESC; /**< Core LDO Status And Control register, offset: 0x108 */ - __IO uint32_t LVDSC1; /**< Low Voltage Detect Status and Control 1 register, offset: 0x10C */ - __IO uint32_t LVDSC2; /**< Low Voltage Detect Status and Control 2 register, offset: 0x110 */ - __IO uint32_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0x114 */ - uint8_t RESERVED_3[232]; - __IO uint32_t RFLDOLPCNFG; /**< RF LDO Low Power Configuration register, offset: 0x200 */ - __IO uint32_t RFLDOSC; /**< RF LDO Status And Control register, offset: 0x204 */ - uint8_t RESERVED_4[252]; - __IO uint32_t DCDCSC; /**< DCDC Status Control Register, offset: 0x304 */ - uint8_t RESERVED_5[4]; - __IO uint32_t DCDCC1; /**< DCDC Control Register 1, offset: 0x30C */ - __IO uint32_t DCDCC2; /**< DCDC Control Register 2, offset: 0x310 */ - __IO uint32_t DCDCC3; /**< DCDC Control Register 3, offset: 0x314 */ - __IO uint32_t DCDCC4; /**< DCDC Control Register 4, offset: 0x318 */ - uint8_t RESERVED_6[4]; - __IO uint32_t DCDCC6; /**< DCDC Control Register 6, offset: 0x320 */ - uint8_t RESERVED_7[232]; - __IO uint32_t LPREQPINCNTRL; /**< LP Request Pin Control Register, offset: 0x40C */ -} SPM_Type; - -/* ---------------------------------------------------------------------------- - -- SPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPM_Register_Masks SPM Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define SPM_VERID_FEATURE_MASK (0xFFFFU) -#define SPM_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number - * 0b0000000000000000..Standard features implemented. - */ -#define SPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_FEATURE_SHIFT)) & SPM_VERID_FEATURE_MASK) -#define SPM_VERID_MINOR_MASK (0xFF0000U) -#define SPM_VERID_MINOR_SHIFT (16U) -#define SPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MINOR_SHIFT)) & SPM_VERID_MINOR_MASK) -#define SPM_VERID_MAJOR_MASK (0xFF000000U) -#define SPM_VERID_MAJOR_SHIFT (24U) -#define SPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MAJOR_SHIFT)) & SPM_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name RSR - Regulator Status Register */ -/*! @{ */ -#define SPM_RSR_REGSEL_MASK (0x7U) -#define SPM_RSR_REGSEL_SHIFT (0U) -#define SPM_RSR_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_REGSEL_SHIFT)) & SPM_RSR_REGSEL_MASK) -#define SPM_RSR_MCUPMSTAT_MASK (0x1F0000U) -#define SPM_RSR_MCUPMSTAT_SHIFT (16U) -/*! MCUPMSTAT - MCU Power Mode Status - * 0b00000..Reserved - * 0b00001..Last Low Power mode is STOP. - * 0b00010..Last Low Power mode is VLPS. - * 0b00100..Last Low Power mode is LLS. - * 0b01000..Last Low Power mode is VLLS23. - * 0b10000..Last Low Power mode is VLLS01. - */ -#define SPM_RSR_MCUPMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_MCUPMSTAT_SHIFT)) & SPM_RSR_MCUPMSTAT_MASK) -#define SPM_RSR_RFPMSTAT_MASK (0x7000000U) -#define SPM_RSR_RFPMSTAT_SHIFT (24U) -/*! RFPMSTAT - RADIO Power Mode Status - * 0b000..Reserved - * 0b001..Current Power mode is VLPS. - * 0b010..Current Power mode is LLS. - * 0b100..Current Power mode is VLLS. - */ -#define SPM_RSR_RFPMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFPMSTAT_SHIFT)) & SPM_RSR_RFPMSTAT_MASK) -#define SPM_RSR_RFRUNFORCE_MASK (0x8000000U) -#define SPM_RSR_RFRUNFORCE_SHIFT (27U) -/*! RFRUNFORCE - RADIO Run Force Power Mode Status - * 0b0..Radio Run Force Regulator Off - * 0b1..Radio Run Force Regulator On. - */ -#define SPM_RSR_RFRUNFORCE(x) (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFRUNFORCE_SHIFT)) & SPM_RSR_RFRUNFORCE_MASK) -/*! @} */ - -/*! @name RCTRL - Run Control Register */ -/*! @{ */ -#define SPM_RCTRL_REGSEL_MASK (0x7U) -#define SPM_RCTRL_REGSEL_SHIFT (0U) -#define SPM_RCTRL_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RCTRL_REGSEL_SHIFT)) & SPM_RCTRL_REGSEL_MASK) -/*! @} */ - -/*! @name LPCTRL - Low Power Control Register */ -/*! @{ */ -#define SPM_LPCTRL_REGSEL_MASK (0x7U) -#define SPM_LPCTRL_REGSEL_SHIFT (0U) -#define SPM_LPCTRL_REGSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPCTRL_REGSEL_SHIFT)) & SPM_LPCTRL_REGSEL_MASK) -/*! @} */ - -/*! @name CORERCNFG - CORE LDO RUN Configuration Register */ -/*! @{ */ -#define SPM_CORERCNFG_VDDIOVDDMEN_MASK (0x10000U) -#define SPM_CORERCNFG_VDDIOVDDMEN_SHIFT (16U) -/*! VDDIOVDDMEN - VDDIOVDDMEN - * 0b0..VDDIO voltage monitor disabled in run modes. - * 0b1..VDDIO voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_VDDIOVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORERCNFG_VDDIOVDDMEN_MASK) -#define SPM_CORERCNFG_USBVDDMEN_MASK (0x20000U) -#define SPM_CORERCNFG_USBVDDMEN_SHIFT (17U) -/*! USBVDDMEN - USBVDDMEN - * 0b0..USB voltage monitor disabled in run modes. - * 0b1..USB voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_USBVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_USBVDDMEN_SHIFT)) & SPM_CORERCNFG_USBVDDMEN_MASK) -#define SPM_CORERCNFG_RTCVDDMEN_MASK (0x40000U) -#define SPM_CORERCNFG_RTCVDDMEN_SHIFT (18U) -/*! RTCVDDMEN - RTCVDDMEN - * 0b0..RTC voltage monitor disabled in run modes. - * 0b1..RTC voltage monitor enabled in run modes. - */ -#define SPM_CORERCNFG_RTCVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_RTCVDDMEN_SHIFT)) & SPM_CORERCNFG_RTCVDDMEN_MASK) -/*! @} */ - -/*! @name CORELPCNFG - CORE LDO Low Power Configuration register */ -/*! @{ */ -#define SPM_CORELPCNFG_LPSEL_MASK (0x2U) -#define SPM_CORELPCNFG_LPSEL_SHIFT (1U) -/*! LPSEL - LPSEL - * 0b0..Core LDO enters low power state in VLP/Stop modes. - * 0b1..Core LDO remains in high power state in VLP/Stop modes. If LPSEL = 1 in a low power mode then BGEN must also be set to 1. - */ -#define SPM_CORELPCNFG_LPSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPSEL_SHIFT)) & SPM_CORELPCNFG_LPSEL_MASK) -#define SPM_CORELPCNFG_BGEN_MASK (0x4U) -#define SPM_CORELPCNFG_BGEN_SHIFT (2U) -/*! BGEN - Bandgap Enable In Low Power Mode Operation - * 0b0..Bandgap is disabled in STOP/VLP/LLS and VLLS modes. - * 0b1..Bandgap remains enabled in STOP/VLP/LLS and VLLS modes. - */ -#define SPM_CORELPCNFG_BGEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGEN_SHIFT)) & SPM_CORELPCNFG_BGEN_MASK) -#define SPM_CORELPCNFG_BGBEN_MASK (0x8U) -#define SPM_CORELPCNFG_BGBEN_SHIFT (3U) -/*! BGBEN - Bandgap Buffer Enable - * 0b0..Bandgap buffer not enabled - * 0b1..Bandgap buffer enabled BGEN must be set when this bit is also set. - */ -#define SPM_CORELPCNFG_BGBEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBEN_SHIFT)) & SPM_CORELPCNFG_BGBEN_MASK) -#define SPM_CORELPCNFG_BGBDS_MASK (0x10U) -#define SPM_CORELPCNFG_BGBDS_SHIFT (4U) -/*! BGBDS - Bandgap Buffer Drive Select - * 0b0..Low Drive - * 0b1..High Drive - */ -#define SPM_CORELPCNFG_BGBDS(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBDS_SHIFT)) & SPM_CORELPCNFG_BGBDS_MASK) -#define SPM_CORELPCNFG_LPOEN_MASK (0x80U) -#define SPM_CORELPCNFG_LPOEN_SHIFT (7U) -/*! LPOEN - LPO Enabled - * 0b0..LPO is disabled in VLLS modes. - * 0b1..LPO remains enabled in VLLS modes. - */ -#define SPM_CORELPCNFG_LPOEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPOEN_SHIFT)) & SPM_CORELPCNFG_LPOEN_MASK) -#define SPM_CORELPCNFG_POREN_MASK (0x100U) -#define SPM_CORELPCNFG_POREN_SHIFT (8U) -/*! POREN - POR Enabled - * 0b0..POR brownout is disabled in VLLS0/1 mode. - * 0b1..POR brownout remains enabled in VLLS0/1 mode. - */ -#define SPM_CORELPCNFG_POREN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_POREN_SHIFT)) & SPM_CORELPCNFG_POREN_MASK) -#define SPM_CORELPCNFG_LVDEN_MASK (0x200U) -#define SPM_CORELPCNFG_LVDEN_SHIFT (9U) -/*! LVDEN - LVD Enabled - * 0b0..LVD/HVD is disabled in low power modes. - * 0b1..LVD/HVD remains enabled in low power modes. BGEN must be set when this bit is also set. - */ -#define SPM_CORELPCNFG_LVDEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LVDEN_SHIFT)) & SPM_CORELPCNFG_LVDEN_MASK) -#define SPM_CORELPCNFG_LPHIDRIVE_MASK (0x4000U) -#define SPM_CORELPCNFG_LPHIDRIVE_SHIFT (14U) -/*! LPHIDRIVE - LPHIDRIVE - * 0b0..High Drive disabled. - * 0b1..High Drive enabled. - */ -#define SPM_CORELPCNFG_LPHIDRIVE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPHIDRIVE_SHIFT)) & SPM_CORELPCNFG_LPHIDRIVE_MASK) -#define SPM_CORELPCNFG_ALLREFEN_MASK (0x8000U) -#define SPM_CORELPCNFG_ALLREFEN_SHIFT (15U) -/*! ALLREFEN - All Reference Enable. This bit only has an affect in VLLS0/1. - * 0b0..All references are disabled in VLLS. - * 0b1..All references are enabled in VLLS0/1. - */ -#define SPM_CORELPCNFG_ALLREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_ALLREFEN_SHIFT)) & SPM_CORELPCNFG_ALLREFEN_MASK) -#define SPM_CORELPCNFG_VDDIOVDDMEN_MASK (0x10000U) -#define SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT (16U) -/*! VDDIOVDDMEN - VDDIOVDDMEN - * 0b0..VDDIO voltage monitor disabled in lp modes. - * 0b1..VDDIO voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_VDDIOVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORELPCNFG_VDDIOVDDMEN_MASK) -#define SPM_CORELPCNFG_USBVDDMEN_MASK (0x20000U) -#define SPM_CORELPCNFG_USBVDDMEN_SHIFT (17U) -/*! USBVDDMEN - USBVDDMEN - * 0b0..USB voltage monitor disabled in lp modes. - * 0b1..USB voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_USBVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_USBVDDMEN_SHIFT)) & SPM_CORELPCNFG_USBVDDMEN_MASK) -#define SPM_CORELPCNFG_RTCVDDMEN_MASK (0x40000U) -#define SPM_CORELPCNFG_RTCVDDMEN_SHIFT (18U) -/*! RTCVDDMEN - RTCVDDMEN - * 0b0..RTC voltage monitor disabled in lp modes. - * 0b1..RTC voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. - */ -#define SPM_CORELPCNFG_RTCVDDMEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_RTCVDDMEN_SHIFT)) & SPM_CORELPCNFG_RTCVDDMEN_MASK) -/*! @} */ - -/*! @name CORESC - Core LDO Status And Control register */ -/*! @{ */ -#define SPM_CORESC_REGONS_MASK (0x4U) -#define SPM_CORESC_REGONS_SHIFT (2U) -/*! REGONS - CORE LDO Regulator in Run Regulation Status - * 0b0..Regulator is in low power state or in transition to/from it. - * 0b1..Regulator is in high power state. - */ -#define SPM_CORESC_REGONS(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_REGONS_SHIFT)) & SPM_CORESC_REGONS_MASK) -#define SPM_CORESC_ACKISO_MASK (0x8U) -#define SPM_CORESC_ACKISO_SHIFT (3U) -/*! ACKISO - Acknowledge Isolation - * 0b0..Peripherals and I/O pads are in normal run state. - * 0b1..Certain peripherals and I/O pads are in a isolated and latched state. - */ -#define SPM_CORESC_ACKISO(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_ACKISO_SHIFT)) & SPM_CORESC_ACKISO_MASK) -#define SPM_CORESC_TRIM_MASK (0x3F00U) -#define SPM_CORESC_TRIM_SHIFT (8U) -#define SPM_CORESC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_TRIM_SHIFT)) & SPM_CORESC_TRIM_MASK) -#define SPM_CORESC_VDDIOOVRIDE_MASK (0x10000U) -#define SPM_CORESC_VDDIOOVRIDE_SHIFT (16U) -/*! VDDIOOVRIDE - VDDIOOVRIDE - * 0b0..VDDIOOK status set to 1'b0. - * 0b1..VDDIOOK status set to 1'b1. - */ -#define SPM_CORESC_VDDIOOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOVRIDE_SHIFT)) & SPM_CORESC_VDDIOOVRIDE_MASK) -#define SPM_CORESC_USBOVRIDE_MASK (0x20000U) -#define SPM_CORESC_USBOVRIDE_SHIFT (17U) -/*! USBOVRIDE - USBOVRIDE - * 0b0..USBVDDOK status set to 1'b0. - * 0b1..USBVDDOK status set to 1'b1. - */ -#define SPM_CORESC_USBOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBOVRIDE_SHIFT)) & SPM_CORESC_USBOVRIDE_MASK) -#define SPM_CORESC_RTCOVRIDE_MASK (0x40000U) -#define SPM_CORESC_RTCOVRIDE_SHIFT (18U) -/*! RTCOVRIDE - RTCOVRIDE - * 0b0..RTCVDDOK status set to 1'b0. - * 0b1..RTCVDDOK status set to 1'b1. - */ -#define SPM_CORESC_RTCOVRIDE(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCOVRIDE_SHIFT)) & SPM_CORESC_RTCOVRIDE_MASK) -#define SPM_CORESC_VDDIOOK_MASK (0x1000000U) -#define SPM_CORESC_VDDIOOK_SHIFT (24U) -#define SPM_CORESC_VDDIOOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOK_SHIFT)) & SPM_CORESC_VDDIOOK_MASK) -#define SPM_CORESC_USBVDDOK_MASK (0x2000000U) -#define SPM_CORESC_USBVDDOK_SHIFT (25U) -#define SPM_CORESC_USBVDDOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBVDDOK_SHIFT)) & SPM_CORESC_USBVDDOK_MASK) -#define SPM_CORESC_RTCVDDOK_MASK (0x4000000U) -#define SPM_CORESC_RTCVDDOK_SHIFT (26U) -#define SPM_CORESC_RTCVDDOK(x) (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCVDDOK_SHIFT)) & SPM_CORESC_RTCVDDOK_MASK) -/*! @} */ - -/*! @name LVDSC1 - Low Voltage Detect Status and Control 1 register */ -/*! @{ */ -#define SPM_LVDSC1_COREVDD_LVDRE_MASK (0x10U) -#define SPM_LVDSC1_COREVDD_LVDRE_SHIFT (4U) -/*! COREVDD_LVDRE - Core Low-Voltage Detect Reset Enable - * 0b0..COREVDD_LVDF does not generate hardware resets - * 0b1..Force an MCU reset when CORE_LVDF = 1 - */ -#define SPM_LVDSC1_COREVDD_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDRE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDRE_MASK) -#define SPM_LVDSC1_COREVDD_LVDIE_MASK (0x20U) -#define SPM_LVDSC1_COREVDD_LVDIE_SHIFT (5U) -/*! COREVDD_LVDIE - Low-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when LVDF = 1 - */ -#define SPM_LVDSC1_COREVDD_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDIE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDIE_MASK) -#define SPM_LVDSC1_COREVDD_LVDACK_MASK (0x40U) -#define SPM_LVDSC1_COREVDD_LVDACK_SHIFT (6U) -#define SPM_LVDSC1_COREVDD_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDACK_SHIFT)) & SPM_LVDSC1_COREVDD_LVDACK_MASK) -#define SPM_LVDSC1_COREVDD_LVDF_MASK (0x80U) -#define SPM_LVDSC1_COREVDD_LVDF_SHIFT (7U) -/*! COREVDD_LVDF - Low-Voltage Detect Flag - * 0b0..Low-voltage event not detected - * 0b1..Low-voltage event detected - */ -#define SPM_LVDSC1_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDF_SHIFT)) & SPM_LVDSC1_COREVDD_LVDF_MASK) -#define SPM_LVDSC1_VDD_LVDV_MASK (0x30000U) -#define SPM_LVDSC1_VDD_LVDV_SHIFT (16U) -/*! VDD_LVDV - VDD Low-Voltage Detect Voltage Select - * 0b00..Low trip point selected (V LVD = V LVDL ) - * 0b01..High trip point selected (V LVD = V LVDH ) - * 0b10..Reserved - * 0b11..Reserved - */ -#define SPM_LVDSC1_VDD_LVDV(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDV_SHIFT)) & SPM_LVDSC1_VDD_LVDV_MASK) -#define SPM_LVDSC1_VDD_LVDRE_MASK (0x100000U) -#define SPM_LVDSC1_VDD_LVDRE_SHIFT (20U) -/*! VDD_LVDRE - VDD Low-Voltage Detect Reset Enable - * 0b0..VDD_LVDF does not generate hardware resets - * 0b1..Force an MCU reset when VDD_LVDF = 1 - */ -#define SPM_LVDSC1_VDD_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDRE_SHIFT)) & SPM_LVDSC1_VDD_LVDRE_MASK) -#define SPM_LVDSC1_VDD_LVDIE_MASK (0x200000U) -#define SPM_LVDSC1_VDD_LVDIE_SHIFT (21U) -/*! VDD_LVDIE - VDD Low-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when VDD_LVDF = 1 - */ -#define SPM_LVDSC1_VDD_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDIE_SHIFT)) & SPM_LVDSC1_VDD_LVDIE_MASK) -#define SPM_LVDSC1_VDD_LVDACK_MASK (0x400000U) -#define SPM_LVDSC1_VDD_LVDACK_SHIFT (22U) -#define SPM_LVDSC1_VDD_LVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDACK_SHIFT)) & SPM_LVDSC1_VDD_LVDACK_MASK) -#define SPM_LVDSC1_VDD_LVDF_MASK (0x800000U) -#define SPM_LVDSC1_VDD_LVDF_SHIFT (23U) -/*! VDD_LVDF - VDD Low-Voltage Detect Flag - * 0b0..Low-voltage event not detected - * 0b1..Low-voltage event detected - */ -#define SPM_LVDSC1_VDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDF_SHIFT)) & SPM_LVDSC1_VDD_LVDF_MASK) -/*! @} */ - -/*! @name LVDSC2 - Low Voltage Detect Status and Control 2 register */ -/*! @{ */ -#define SPM_LVDSC2_VDD_LVWV_MASK (0x30000U) -#define SPM_LVDSC2_VDD_LVWV_SHIFT (16U) -/*! VDD_LVWV - VDD Low-Voltage Warning Voltage Select - * 0b00..Low trip point selected (V LVW = VLVW1) - * 0b01..Mid 1 trip point selected (V LVW = VLVW2) - * 0b10..Mid 2 trip point selected (V LVW = VLVW3) - * 0b11..High trip point selected (V LVW = VLVW4) - */ -#define SPM_LVDSC2_VDD_LVWV(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWV_SHIFT)) & SPM_LVDSC2_VDD_LVWV_MASK) -#define SPM_LVDSC2_VDD_LVWIE_MASK (0x200000U) -#define SPM_LVDSC2_VDD_LVWIE_SHIFT (21U) -/*! VDD_LVWIE - VDD Low-Voltage Warning Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when VDD_LVWF = 1 - */ -#define SPM_LVDSC2_VDD_LVWIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWIE_SHIFT)) & SPM_LVDSC2_VDD_LVWIE_MASK) -#define SPM_LVDSC2_VDD_LVWACK_MASK (0x400000U) -#define SPM_LVDSC2_VDD_LVWACK_SHIFT (22U) -#define SPM_LVDSC2_VDD_LVWACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWACK_SHIFT)) & SPM_LVDSC2_VDD_LVWACK_MASK) -#define SPM_LVDSC2_VDD_LVWF_MASK (0x800000U) -#define SPM_LVDSC2_VDD_LVWF_SHIFT (23U) -/*! VDD_LVWF - VDD Low-Voltage Warning Flag - * 0b0..Low-voltage warning event not detected - * 0b1..Low-voltage warning event detected - */ -#define SPM_LVDSC2_VDD_LVWF(x) (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWF_SHIFT)) & SPM_LVDSC2_VDD_LVWF_MASK) -/*! @} */ - -/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */ -/*! @{ */ -#define SPM_HVDSC1_VDD_HVDV_MASK (0x10000U) -#define SPM_HVDSC1_VDD_HVDV_SHIFT (16U) -/*! VDD_HVDV - VDD High-Voltage Detect Voltage Select - * 0b0..Low trip point selected (V VDD = V VDD_HVDL ) - * 0b1..High trip point selected (V VDD = V VDD_HVDH ) - */ -#define SPM_HVDSC1_VDD_HVDV(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDV_SHIFT)) & SPM_HVDSC1_VDD_HVDV_MASK) -#define SPM_HVDSC1_VDD_HVDRE_MASK (0x100000U) -#define SPM_HVDSC1_VDD_HVDRE_SHIFT (20U) -/*! VDD_HVDRE - VDD High-Voltage Detect Reset Enable - * 0b0..VDD HVDF does not generate hardware resets - * 0b1..Force an MCU reset when VDD_HVDF = 1 - */ -#define SPM_HVDSC1_VDD_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDRE_SHIFT)) & SPM_HVDSC1_VDD_HVDRE_MASK) -#define SPM_HVDSC1_VDD_HVDIE_MASK (0x200000U) -#define SPM_HVDSC1_VDD_HVDIE_SHIFT (21U) -/*! VDD_HVDIE - VDD High-Voltage Detect Interrupt Enable - * 0b0..Hardware interrupt disabled (use polling) - * 0b1..Request a hardware interrupt when HVDF = 1 - */ -#define SPM_HVDSC1_VDD_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDIE_SHIFT)) & SPM_HVDSC1_VDD_HVDIE_MASK) -#define SPM_HVDSC1_VDD_HVDACK_MASK (0x400000U) -#define SPM_HVDSC1_VDD_HVDACK_SHIFT (22U) -#define SPM_HVDSC1_VDD_HVDACK(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDACK_SHIFT)) & SPM_HVDSC1_VDD_HVDACK_MASK) -#define SPM_HVDSC1_VDD_HVDF_MASK (0x800000U) -#define SPM_HVDSC1_VDD_HVDF_SHIFT (23U) -/*! VDD_HVDF - VDD High-Voltage Detect Flag - * 0b0..Vdd High-voltage event not detected - * 0b1..Vdd High-voltage event detected - */ -#define SPM_HVDSC1_VDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDF_SHIFT)) & SPM_HVDSC1_VDD_HVDF_MASK) -/*! @} */ - -/*! @name RFLDOLPCNFG - RF LDO Low Power Configuration register */ -/*! @{ */ -#define SPM_RFLDOLPCNFG_LPSEL_MASK (0x2U) -#define SPM_RFLDOLPCNFG_LPSEL_SHIFT (1U) -/*! LPSEL - LPSEL - * 0b0..RF LDO regulator enters low power state in VLP/Stop modes. - * 0b1..RF LDO regulator remains in high power state in VLP/Stop modes. - */ -#define SPM_RFLDOLPCNFG_LPSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOLPCNFG_LPSEL_SHIFT)) & SPM_RFLDOLPCNFG_LPSEL_MASK) -/*! @} */ - -/*! @name RFLDOSC - RF LDO Status And Control register */ -/*! @{ */ -#define SPM_RFLDOSC_IOREGVSEL_MASK (0x1U) -#define SPM_RFLDOSC_IOREGVSEL_SHIFT (0U) -/*! IOREGVSEL - IO Regulator Voltage Select - * 0b0..Regulate to 1.8V. - * 0b1..Regulate to 1.5V. - */ -#define SPM_RFLDOSC_IOREGVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOREGVSEL_SHIFT)) & SPM_RFLDOSC_IOREGVSEL_MASK) -#define SPM_RFLDOSC_VDD1P8SEL_MASK (0x10U) -#define SPM_RFLDOSC_VDD1P8SEL_SHIFT (4U) -/*! VDD1P8SEL - VDD 1p8 SNS Pin Select - * 0b0..VDD1p8_SNS0 selected. - * 0b1..VDD1p8_SNS1 selected. - */ -#define SPM_RFLDOSC_VDD1P8SEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_VDD1P8SEL_SHIFT)) & SPM_RFLDOSC_VDD1P8SEL_MASK) -#define SPM_RFLDOSC_ISINKEN_MASK (0x20U) -#define SPM_RFLDOSC_ISINKEN_SHIFT (5U) -/*! ISINKEN - ISINKEN - * 0b0..Disable current sink feature of low power regulator. - * 0b1..Enable current sink feature of low power regulator. - */ -#define SPM_RFLDOSC_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_ISINKEN_SHIFT)) & SPM_RFLDOSC_ISINKEN_MASK) -#define SPM_RFLDOSC_IOTRIM_MASK (0x1F00U) -#define SPM_RFLDOSC_IOTRIM_SHIFT (8U) -#define SPM_RFLDOSC_IOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOTRIM_SHIFT)) & SPM_RFLDOSC_IOTRIM_MASK) -#define SPM_RFLDOSC_IOSSSEL_MASK (0x70000U) -#define SPM_RFLDOSC_IOSSSEL_SHIFT (16U) -/*! IOSSSEL - IO 1.8 Reg Soft Start Select - * 0b000..Soft Start duration set to 110us. - * 0b001..Soft Start duration set to 95us. - * 0b010..Soft Start duration set to 60us. - * 0b011..Soft Start duration set to 48us. - * 0b100..Soft Start duration set to 38us. - * 0b101..Soft Start duration set to 30us. - * 0b110..Soft Start duration set to 24us. - * 0b111..Soft Start duration set to 17us. - */ -#define SPM_RFLDOSC_IOSSSEL(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSSSEL_SHIFT)) & SPM_RFLDOSC_IOSSSEL_MASK) -#define SPM_RFLDOSC_SSDONE_MASK (0x1000000U) -#define SPM_RFLDOSC_SSDONE_SHIFT (24U) -#define SPM_RFLDOSC_SSDONE(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_SSDONE_SHIFT)) & SPM_RFLDOSC_SSDONE_MASK) -#define SPM_RFLDOSC_IOSPARE_OUT_MASK (0xC000000U) -#define SPM_RFLDOSC_IOSPARE_OUT_SHIFT (26U) -#define SPM_RFLDOSC_IOSPARE_OUT(x) (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSPARE_OUT_SHIFT)) & SPM_RFLDOSC_IOSPARE_OUT_MASK) -/*! @} */ - -/*! @name DCDCSC - DCDC Status Control Register */ -/*! @{ */ -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) -#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK) -#define SPM_DCDCSC_DCDC_SEL_CLK_MASK (0x4U) -#define SPM_DCDCSC_DCDC_SEL_CLK_SHIFT (2U) -#define SPM_DCDCSC_DCDC_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_SEL_CLK_SHIFT)) & SPM_DCDCSC_DCDC_SEL_CLK_MASK) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK (0x8U) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT (3U) -#define SPM_DCDCSC_DCDC_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT)) & SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK) -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT (10U) -/*! DCDC_VBAT_DIV_CTRL - DCDC_VBAT_DIV_CTRL - * 0b00..OFF - * 0b01..VBAT - * 0b10..VBAT / 2 - * 0b11..VBAT / 4 - */ -#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT)) & SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) -#define SPM_DCDCSC_DCDC_LESS_I_MASK (0x2000000U) -#define SPM_DCDCSC_DCDC_LESS_I_SHIFT (25U) -#define SPM_DCDCSC_DCDC_LESS_I(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_LESS_I_SHIFT)) & SPM_DCDCSC_DCDC_LESS_I_MASK) -#define SPM_DCDCSC_PWD_CMP_OFFSET_MASK (0x4000000U) -#define SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT (26U) -#define SPM_DCDCSC_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT)) & SPM_DCDCSC_PWD_CMP_OFFSET_MASK) -#define SPM_DCDCSC_CLKFLT_FAULT_MASK (0x40000000U) -#define SPM_DCDCSC_CLKFLT_FAULT_SHIFT (30U) -#define SPM_DCDCSC_CLKFLT_FAULT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_CLKFLT_FAULT_SHIFT)) & SPM_DCDCSC_CLKFLT_FAULT_MASK) -#define SPM_DCDCSC_DCDC_STS_DC_OK_MASK (0x80000000U) -#define SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT (31U) -#define SPM_DCDCSC_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT)) & SPM_DCDCSC_DCDC_STS_DC_OK_MASK) -/*! @} */ - -/*! @name DCDCC1 - DCDC Control Register 1 */ -/*! @{ */ -#define SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK (0x7FU) -#define SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT (0U) -#define SPM_DCDCC1_POSLIMIT_BUCK_IN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT)) & SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x4000000U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (26U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x8000000U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (27U) -#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK) -/*! @} */ - -/*! @name DCDCC2 - DCDC Control Register 2 */ -/*! @{ */ -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK (0x2000U) -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U) -#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U) -#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK) -/*! @} */ - -/*! @name DCDCC3 - DCDC Control Register 3 */ -/*! @{ */ -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK (0x1U) -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT (0U) -#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT)) & SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK) -#define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK (0x1CU) -#define SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT (2U) -#define SPM_DCDCC3_DCDC_VBAT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK (0xF0000U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT (16U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT (24U) -#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK (0x2000000U) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT (25U) -#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK (0x4000000U) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (26U) -#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK (0x8000000U) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT (27U) -#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK (0x40000000U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT (30U) -#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x80000000U) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (31U) -#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK) -/*! @} */ - -/*! @name DCDCC4 - DCDC Control Register 4 */ -/*! @{ */ -#define SPM_DCDCC4_INTEGRATOR_VALUE_MASK (0x7FFFFU) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT (0U) -#define SPM_DCDCC4_INTEGRATOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_MASK) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK (0x80000U) -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT (19U) -/*! INTEGRATOR_VALUE_SELECT - INTEGRATOR VALUE SELECT - * 0b0..Select the saved value in hardware - * 0b1..Select the integrator value in this register - */ -#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK (0x100000U) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT (20U) -#define SPM_DCDCC4_PULSE_RUN_SPEEDUP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT)) & SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK) -/*! @} */ - -/*! @name DCDCC6 - DCDC Control Register 6 */ -/*! @{ */ -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK (0x1FU) -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT (0U) -#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK (0xF00U) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT (8U) -#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK (0xF000000U) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT (24U) -#define SPM_DCDCC6_DCDC_HSVDD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT)) & SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) -/*! @} */ - -/*! @name LPREQPINCNTRL - LP Request Pin Control Register */ -/*! @{ */ -#define SPM_LPREQPINCNTRL_LPREQOE_MASK (0x1U) -#define SPM_LPREQPINCNTRL_LPREQOE_SHIFT (0U) -/*! LPREQOE - Low Power Request Output Enable Register - * 0b0..Low Power request output pin not enabled. - * 0b1..Low Power request output pin enabled. - */ -#define SPM_LPREQPINCNTRL_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_LPREQOE_SHIFT)) & SPM_LPREQPINCNTRL_LPREQOE_MASK) -#define SPM_LPREQPINCNTRL_POLARITY_MASK (0x2U) -#define SPM_LPREQPINCNTRL_POLARITY_SHIFT (1U) -/*! POLARITY - Low Power Request Output Pin Polarity Control Register - * 0b0..High true polarity. - * 0b1..Low true polarity. - */ -#define SPM_LPREQPINCNTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_POLARITY_SHIFT)) & SPM_LPREQPINCNTRL_POLARITY_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPM_Register_Masks */ - - -/* SPM - Peripheral instance base addresses */ -/** Peripheral SPM base address */ -#define SPM_BASE (0x40028000u) -/** Peripheral SPM base pointer */ -#define SPM ((SPM_Type *)SPM_BASE) -/** Array initializer of SPM peripheral base addresses */ -#define SPM_BASE_ADDRS { SPM_BASE } -/** Array initializer of SPM peripheral base pointers */ -#define SPM_BASE_PTRS { SPM } -/** Interrupt vectors for the SPM peripheral type */ -#define SPM_IRQS { SPM_IRQn } - -/*! - * @} - */ /* end of group SPM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TPM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer - * @{ - */ - -/** TPM - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ - __IO uint32_t CNT; /**< Counter, offset: 0x14 */ - __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ - __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ - struct { /* offset: 0x20, array step: 0x8 */ - __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */ - __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */ - } CONTROLS[6]; - uint8_t RESERVED_1[20]; - __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ - uint8_t RESERVED_2[4]; - __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ - __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ - uint8_t RESERVED_4[4]; - __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ - __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ -} TPM_Type; - -/* ---------------------------------------------------------------------------- - -- TPM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TPM_Register_Masks TPM Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define TPM_VERID_FEATURE_MASK (0xFFFFU) -#define TPM_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - * 0b0000000000000001..Standard feature set. - * 0b0000000000000011..Standard feature set with Filter and Combine registers implemented. - * 0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented. - */ -#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) -#define TPM_VERID_MINOR_MASK (0xFF0000U) -#define TPM_VERID_MINOR_SHIFT (16U) -#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) -#define TPM_VERID_MAJOR_MASK (0xFF000000U) -#define TPM_VERID_MAJOR_SHIFT (24U) -#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define TPM_PARAM_CHAN_MASK (0xFFU) -#define TPM_PARAM_CHAN_SHIFT (0U) -#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) -#define TPM_PARAM_TRIG_MASK (0xFF00U) -#define TPM_PARAM_TRIG_SHIFT (8U) -#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) -#define TPM_PARAM_WIDTH_MASK (0xFF0000U) -#define TPM_PARAM_WIDTH_SHIFT (16U) -#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) -/*! @} */ - -/*! @name GLOBAL - TPM Global Register */ -/*! @{ */ -#define TPM_GLOBAL_NOUPDATE_MASK (0x1U) -#define TPM_GLOBAL_NOUPDATE_SHIFT (0U) -/*! NOUPDATE - No Update - * 0b0..Internal double buffered registers update as normal. - * 0b1..Internal double buffered registers do not update. - */ -#define TPM_GLOBAL_NOUPDATE(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK) -#define TPM_GLOBAL_RST_MASK (0x2U) -#define TPM_GLOBAL_RST_SHIFT (1U) -/*! RST - Software Reset - * 0b0..Module is not reset. - * 0b1..Module is reset. - */ -#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) -/*! @} */ - -/*! @name SC - Status and Control */ -/*! @{ */ -#define TPM_SC_PS_MASK (0x7U) -#define TPM_SC_PS_SHIFT (0U) -/*! PS - Prescale Factor Selection - * 0b000..Divide by 1 - * 0b001..Divide by 2 - * 0b010..Divide by 4 - * 0b011..Divide by 8 - * 0b100..Divide by 16 - * 0b101..Divide by 32 - * 0b110..Divide by 64 - * 0b111..Divide by 128 - */ -#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) -#define TPM_SC_CMOD_MASK (0x18U) -#define TPM_SC_CMOD_SHIFT (3U) -/*! CMOD - Clock Mode Selection - * 0b00..TPM counter is disabled - * 0b01..TPM counter increments on every TPM counter clock - * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock - * 0b11..TPM counter increments on rising edge of the selected external input trigger. - */ -#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) -#define TPM_SC_CPWMS_MASK (0x20U) -#define TPM_SC_CPWMS_SHIFT (5U) -/*! CPWMS - Center-Aligned PWM Select - * 0b0..TPM counter operates in up counting mode. - * 0b1..TPM counter operates in up-down counting mode. - */ -#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) -#define TPM_SC_TOIE_MASK (0x40U) -#define TPM_SC_TOIE_SHIFT (6U) -/*! TOIE - Timer Overflow Interrupt Enable - * 0b0..Disable TOF interrupts. Use software polling or DMA request. - * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. - */ -#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) -#define TPM_SC_TOF_MASK (0x80U) -#define TPM_SC_TOF_SHIFT (7U) -/*! TOF - Timer Overflow Flag - * 0b0..TPM counter has not overflowed. - * 0b1..TPM counter has overflowed. - */ -#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) -#define TPM_SC_DMA_MASK (0x100U) -#define TPM_SC_DMA_SHIFT (8U) -/*! DMA - DMA Enable - * 0b0..Disables DMA transfers. - * 0b1..Enables DMA transfers. - */ -#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) -/*! @} */ - -/*! @name CNT - Counter */ -/*! @{ */ -#define TPM_CNT_COUNT_MASK (0xFFFFU) -#define TPM_CNT_COUNT_SHIFT (0U) -#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) -/*! @} */ - -/*! @name MOD - Modulo */ -/*! @{ */ -#define TPM_MOD_MOD_MASK (0xFFFFU) -#define TPM_MOD_MOD_SHIFT (0U) -#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) -/*! @} */ - -/*! @name STATUS - Capture and Compare Status */ -/*! @{ */ -#define TPM_STATUS_CH0F_MASK (0x1U) -#define TPM_STATUS_CH0F_SHIFT (0U) -/*! CH0F - Channel 0 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) -#define TPM_STATUS_CH1F_MASK (0x2U) -#define TPM_STATUS_CH1F_SHIFT (1U) -/*! CH1F - Channel 1 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) -#define TPM_STATUS_CH2F_MASK (0x4U) -#define TPM_STATUS_CH2F_SHIFT (2U) -/*! CH2F - Channel 2 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) -#define TPM_STATUS_CH3F_MASK (0x8U) -#define TPM_STATUS_CH3F_SHIFT (3U) -/*! CH3F - Channel 3 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) -#define TPM_STATUS_CH4F_MASK (0x10U) -#define TPM_STATUS_CH4F_SHIFT (4U) -/*! CH4F - Channel 4 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) -#define TPM_STATUS_CH5F_MASK (0x20U) -#define TPM_STATUS_CH5F_SHIFT (5U) -/*! CH5F - Channel 5 Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) -#define TPM_STATUS_TOF_MASK (0x100U) -#define TPM_STATUS_TOF_SHIFT (8U) -/*! TOF - Timer Overflow Flag - * 0b0..TPM counter has not overflowed. - * 0b1..TPM counter has overflowed. - */ -#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) -/*! @} */ - -/*! @name CnSC - Channel (n) Status and Control */ -/*! @{ */ -#define TPM_CnSC_DMA_MASK (0x1U) -#define TPM_CnSC_DMA_SHIFT (0U) -/*! DMA - DMA Enable - * 0b0..Disable DMA transfers. - * 0b1..Enable DMA transfers. - */ -#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) -#define TPM_CnSC_ELSA_MASK (0x4U) -#define TPM_CnSC_ELSA_SHIFT (2U) -#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) -#define TPM_CnSC_ELSB_MASK (0x8U) -#define TPM_CnSC_ELSB_SHIFT (3U) -#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) -#define TPM_CnSC_MSA_MASK (0x10U) -#define TPM_CnSC_MSA_SHIFT (4U) -#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) -#define TPM_CnSC_MSB_MASK (0x20U) -#define TPM_CnSC_MSB_SHIFT (5U) -#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) -#define TPM_CnSC_CHIE_MASK (0x40U) -#define TPM_CnSC_CHIE_SHIFT (6U) -/*! CHIE - Channel Interrupt Enable - * 0b0..Disable channel interrupts. - * 0b1..Enable channel interrupts. - */ -#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) -#define TPM_CnSC_CHF_MASK (0x80U) -#define TPM_CnSC_CHF_SHIFT (7U) -/*! CHF - Channel Flag - * 0b0..No channel event has occurred. - * 0b1..A channel event has occurred. - */ -#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) -/*! @} */ - -/* The count of TPM_CnSC */ -#define TPM_CnSC_COUNT (6U) - -/*! @name CnV - Channel (n) Value */ -/*! @{ */ -#define TPM_CnV_VAL_MASK (0xFFFFU) -#define TPM_CnV_VAL_SHIFT (0U) -#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) -/*! @} */ - -/* The count of TPM_CnV */ -#define TPM_CnV_COUNT (6U) - -/*! @name COMBINE - Combine Channel Register */ -/*! @{ */ -#define TPM_COMBINE_COMBINE0_MASK (0x1U) -#define TPM_COMBINE_COMBINE0_SHIFT (0U) -/*! COMBINE0 - Combine Channels 0 and 1 - * 0b0..Channels 0 and 1 are independent. - * 0b1..Channels 0 and 1 are combined. - */ -#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) -#define TPM_COMBINE_COMSWAP0_MASK (0x2U) -#define TPM_COMBINE_COMSWAP0_SHIFT (1U) -/*! COMSWAP0 - Combine Channel 0 and 1 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) -#define TPM_COMBINE_COMBINE1_MASK (0x100U) -#define TPM_COMBINE_COMBINE1_SHIFT (8U) -/*! COMBINE1 - Combine Channels 2 and 3 - * 0b0..Channels 2 and 3 are independent. - * 0b1..Channels 2 and 3 are combined. - */ -#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) -#define TPM_COMBINE_COMSWAP1_MASK (0x200U) -#define TPM_COMBINE_COMSWAP1_SHIFT (9U) -/*! COMSWAP1 - Combine Channels 2 and 3 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) -#define TPM_COMBINE_COMBINE2_MASK (0x10000U) -#define TPM_COMBINE_COMBINE2_SHIFT (16U) -/*! COMBINE2 - Combine Channels 4 and 5 - * 0b0..Channels 4 and 5 are independent. - * 0b1..Channels 4 and 5 are combined. - */ -#define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK) -#define TPM_COMBINE_COMSWAP2_MASK (0x20000U) -#define TPM_COMBINE_COMSWAP2_SHIFT (17U) -/*! COMSWAP2 - Combine Channels 4 and 5 Swap - * 0b0..Even channel is used for input capture and 1st compare. - * 0b1..Odd channel is used for input capture and 1st compare. - */ -#define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK) -/*! @} */ - -/*! @name TRIG - Channel Trigger */ -/*! @{ */ -#define TPM_TRIG_TRIG0_MASK (0x1U) -#define TPM_TRIG_TRIG0_SHIFT (0U) -/*! TRIG0 - Channel 0 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 0. - */ -#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) -#define TPM_TRIG_TRIG1_MASK (0x2U) -#define TPM_TRIG_TRIG1_SHIFT (1U) -/*! TRIG1 - Channel 1 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 1. - */ -#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) -#define TPM_TRIG_TRIG2_MASK (0x4U) -#define TPM_TRIG_TRIG2_SHIFT (2U) -/*! TRIG2 - Channel 2 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 2. - */ -#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) -#define TPM_TRIG_TRIG3_MASK (0x8U) -#define TPM_TRIG_TRIG3_SHIFT (3U) -/*! TRIG3 - Channel 3 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 3. - */ -#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) -#define TPM_TRIG_TRIG4_MASK (0x10U) -#define TPM_TRIG_TRIG4_SHIFT (4U) -/*! TRIG4 - Channel 4 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 0 to be used by channel 4. - */ -#define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK) -#define TPM_TRIG_TRIG5_MASK (0x20U) -#define TPM_TRIG_TRIG5_SHIFT (5U) -/*! TRIG5 - Channel 5 Trigger - * 0b0..No effect. - * 0b1..Configures trigger input 1 to be used by channel 5. - */ -#define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK) -/*! @} */ - -/*! @name POL - Channel Polarity */ -/*! @{ */ -#define TPM_POL_POL0_MASK (0x1U) -#define TPM_POL_POL0_SHIFT (0U) -/*! POL0 - Channel 0 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) -#define TPM_POL_POL1_MASK (0x2U) -#define TPM_POL_POL1_SHIFT (1U) -/*! POL1 - Channel 1 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) -#define TPM_POL_POL2_MASK (0x4U) -#define TPM_POL_POL2_SHIFT (2U) -/*! POL2 - Channel 2 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) -#define TPM_POL_POL3_MASK (0x8U) -#define TPM_POL_POL3_SHIFT (3U) -/*! POL3 - Channel 3 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) -#define TPM_POL_POL4_MASK (0x10U) -#define TPM_POL_POL4_SHIFT (4U) -/*! POL4 - Channel 4 Polarity - * 0b0..The channel polarity is active high - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) -#define TPM_POL_POL5_MASK (0x20U) -#define TPM_POL_POL5_SHIFT (5U) -/*! POL5 - Channel 5 Polarity - * 0b0..The channel polarity is active high. - * 0b1..The channel polarity is active low. - */ -#define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) -/*! @} */ - -/*! @name FILTER - Filter Control */ -/*! @{ */ -#define TPM_FILTER_CH0FVAL_MASK (0xFU) -#define TPM_FILTER_CH0FVAL_SHIFT (0U) -#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) -#define TPM_FILTER_CH1FVAL_MASK (0xF0U) -#define TPM_FILTER_CH1FVAL_SHIFT (4U) -#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) -#define TPM_FILTER_CH2FVAL_MASK (0xF00U) -#define TPM_FILTER_CH2FVAL_SHIFT (8U) -#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) -#define TPM_FILTER_CH3FVAL_MASK (0xF000U) -#define TPM_FILTER_CH3FVAL_SHIFT (12U) -#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) -#define TPM_FILTER_CH4FVAL_MASK (0xF0000U) -#define TPM_FILTER_CH4FVAL_SHIFT (16U) -#define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK) -#define TPM_FILTER_CH5FVAL_MASK (0xF00000U) -#define TPM_FILTER_CH5FVAL_SHIFT (20U) -#define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK) -/*! @} */ - -/*! @name QDCTRL - Quadrature Decoder Control and Status */ -/*! @{ */ -#define TPM_QDCTRL_QUADEN_MASK (0x1U) -#define TPM_QDCTRL_QUADEN_SHIFT (0U) -/*! QUADEN - QUADEN - * 0b0..Quadrature decoder mode is disabled. - * 0b1..Quadrature decoder mode is enabled. - */ -#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) -#define TPM_QDCTRL_TOFDIR_MASK (0x2U) -#define TPM_QDCTRL_TOFDIR_SHIFT (1U) -/*! TOFDIR - TOFDIR - * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). - * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). - */ -#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) -#define TPM_QDCTRL_QUADIR_MASK (0x4U) -#define TPM_QDCTRL_QUADIR_SHIFT (2U) -/*! QUADIR - Counter Direction in Quadrature Decode Mode - * 0b0..Counter direction is decreasing (counter decrement). - * 0b1..Counter direction is increasing (counter increment). - */ -#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) -#define TPM_QDCTRL_QUADMODE_MASK (0x8U) -#define TPM_QDCTRL_QUADMODE_SHIFT (3U) -/*! QUADMODE - Quadrature Decoder Mode - * 0b0..Phase encoding mode. - * 0b1..Count and direction encoding mode. - */ -#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) -/*! @} */ - -/*! @name CONF - Configuration */ -/*! @{ */ -#define TPM_CONF_DOZEEN_MASK (0x20U) -#define TPM_CONF_DOZEEN_SHIFT (5U) -/*! DOZEEN - Doze Enable - * 0b0..Internal TPM counter continues in Doze mode. - * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. - */ -#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) -#define TPM_CONF_DBGMODE_MASK (0xC0U) -#define TPM_CONF_DBGMODE_SHIFT (6U) -/*! DBGMODE - Debug Mode - * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state. - * 0b11..TPM counter continues in debug mode. - */ -#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) -#define TPM_CONF_GTBSYNC_MASK (0x100U) -#define TPM_CONF_GTBSYNC_SHIFT (8U) -/*! GTBSYNC - Global Time Base Synchronization - * 0b0..Global timebase synchronization disabled. - * 0b1..Global timebase synchronization enabled. - */ -#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) -#define TPM_CONF_GTBEEN_MASK (0x200U) -#define TPM_CONF_GTBEEN_SHIFT (9U) -/*! GTBEEN - Global time base enable - * 0b0..All channels use the internally generated TPM counter as their timebase - * 0b1..All channels use an externally generated global timebase as their timebase - */ -#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) -#define TPM_CONF_CSOT_MASK (0x10000U) -#define TPM_CONF_CSOT_SHIFT (16U) -/*! CSOT - Counter Start on Trigger - * 0b0..TPM counter starts to increment immediately, once it is enabled. - * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. - */ -#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) -#define TPM_CONF_CSOO_MASK (0x20000U) -#define TPM_CONF_CSOO_SHIFT (17U) -/*! CSOO - Counter Stop On Overflow - * 0b0..TPM counter continues incrementing or decrementing after overflow - * 0b1..TPM counter stops incrementing or decrementing after overflow. - */ -#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) -#define TPM_CONF_CROT_MASK (0x40000U) -#define TPM_CONF_CROT_SHIFT (18U) -/*! CROT - Counter Reload On Trigger - * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger - * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger - */ -#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) -#define TPM_CONF_CPOT_MASK (0x80000U) -#define TPM_CONF_CPOT_SHIFT (19U) -#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) -#define TPM_CONF_TRGPOL_MASK (0x400000U) -#define TPM_CONF_TRGPOL_SHIFT (22U) -/*! TRGPOL - Trigger Polarity - * 0b0..Trigger is active high. - * 0b1..Trigger is active low. - */ -#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) -#define TPM_CONF_TRGSRC_MASK (0x800000U) -#define TPM_CONF_TRGSRC_SHIFT (23U) -/*! TRGSRC - Trigger Source - * 0b0..Trigger source selected by TRGSEL is external. - * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture). - */ -#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) -#define TPM_CONF_TRGSEL_MASK (0x3000000U) -#define TPM_CONF_TRGSEL_SHIFT (24U) -/*! TRGSEL - Trigger Select - * 0b01..Channel 0 pin input capture - * 0b10..Channel 1 pin input capture - * 0b11..Channel 0 or Channel 1 pin input capture - */ -#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TPM_Register_Masks */ - - -/* TPM - Peripheral instance base addresses */ -/** Peripheral TPM0 base address */ -#define TPM0_BASE (0x40035000u) -/** Peripheral TPM0 base pointer */ -#define TPM0 ((TPM_Type *)TPM0_BASE) -/** Peripheral TPM1 base address */ -#define TPM1_BASE (0x40036000u) -/** Peripheral TPM1 base pointer */ -#define TPM1 ((TPM_Type *)TPM1_BASE) -/** Peripheral TPM2 base address */ -#define TPM2_BASE (0x40037000u) -/** Peripheral TPM2 base pointer */ -#define TPM2 ((TPM_Type *)TPM2_BASE) -/** Peripheral TPM3 base address */ -#define TPM3_BASE (0x4102D000u) -/** Peripheral TPM3 base pointer */ -#define TPM3 ((TPM_Type *)TPM3_BASE) -/** Array initializer of TPM peripheral base addresses */ -#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE } -/** Array initializer of TPM peripheral base pointers */ -#define TPM_BASE_PTRS { TPM0, TPM1, TPM2, TPM3 } -/** Interrupt vectors for the TPM peripheral type */ -#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn } - -/*! - * @} - */ /* end of group TPM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRGMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer - * @{ - */ - -/** TRGMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t TRGCFG[25]; /**< TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register, array offset: 0x0, array step: 0x4 */ -} TRGMUX_Type; - -/* ---------------------------------------------------------------------------- - -- TRGMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks - * @{ - */ - -/*! @name TRGCFG - TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register */ -/*! @{ */ -#define TRGMUX_TRGCFG_SEL0_MASK (0x3FU) -#define TRGMUX_TRGCFG_SEL0_SHIFT (0U) -#define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK) -#define TRGMUX_TRGCFG_SEL1_MASK (0x3F00U) -#define TRGMUX_TRGCFG_SEL1_SHIFT (8U) -#define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK) -#define TRGMUX_TRGCFG_SEL2_MASK (0x3F0000U) -#define TRGMUX_TRGCFG_SEL2_SHIFT (16U) -#define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK) -#define TRGMUX_TRGCFG_SEL3_MASK (0x3F000000U) -#define TRGMUX_TRGCFG_SEL3_SHIFT (24U) -#define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK) -#define TRGMUX_TRGCFG_LK_MASK (0x80000000U) -#define TRGMUX_TRGCFG_LK_SHIFT (31U) -/*! LK - TRGMUX register lock. - * 0b0..Register can be written. - * 0b1..Register cannot be written until the next system Reset. - */ -#define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK) -/*! @} */ - -/* The count of TRGMUX_TRGCFG */ -#define TRGMUX_TRGCFG_COUNT (25U) - - -/*! - * @} - */ /* end of group TRGMUX_Register_Masks */ - - -/* TRGMUX - Peripheral instance base addresses */ -/** Peripheral TRGMUX0 base address */ -#define TRGMUX0_BASE (0x40029000u) -/** Peripheral TRGMUX0 base pointer */ -#define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE) -/** Peripheral TRGMUX1 base address */ -#define TRGMUX1_BASE (0x41025000u) -/** Peripheral TRGMUX1 base pointer */ -#define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE) -/** Array initializer of TRGMUX peripheral base addresses */ -#define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE } -/** Array initializer of TRGMUX peripheral base pointers */ -#define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 } - -/*! - * @} - */ /* end of group TRGMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer - * @{ - */ - -/** TRNG - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ - __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ - }; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - union { /* offset: 0x14 */ - __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ - __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ - }; - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - union { /* offset: 0x30 */ - __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ - __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ - }; - union { /* offset: 0x34 */ - __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ - __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ - }; - union { /* offset: 0x38 */ - __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ - __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ - }; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ - __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ - __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ - __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ - __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ - __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ - __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ - __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ - uint8_t RESERVED_0[64]; - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; - -/* ---------------------------------------------------------------------------- - -- TRNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks - * @{ - */ - -/*! @name MCTL - Miscellaneous Control Register */ -/*! @{ */ -#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) -#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) -/*! SAMP_MODE - * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker - * 0b01..use raw data into both Entropy shifter and Statistical Checker - * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker - * 0b11..undefined/reserved. - */ -#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -/*! OSC_DIV - * 0b00..use ring oscillator with no divide - * 0b01..use ring oscillator divided-by-2 - * 0b10..use ring oscillator divided-by-4 - * 0b11..use ring oscillator divided-by-8 - */ -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) -#define TRNG_MCTL_UNUSED4_MASK (0x10U) -#define TRNG_MCTL_UNUSED4_SHIFT (4U) -#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) -#define TRNG_MCTL_TRNG_ACC_MASK (0x20U) -#define TRNG_MCTL_TRNG_ACC_SHIFT (5U) -#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) -#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) -#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) -#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) -#define TRNG_MCTL_TST_OUT_MASK (0x800U) -#define TRNG_MCTL_TST_OUT_SHIFT (11U) -#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) -/*! @} */ - -/*! @name SCMISC - Statistical Check Miscellaneous Register */ -/*! @{ */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) -/*! @} */ - -/*! @name PKRRNG - Poker Range Register */ -/*! @{ */ -#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) -#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) -#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) -/*! @} */ - -/*! @name PKRMAX - Poker Maximum Limit Register */ -/*! @{ */ -#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) -#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) -#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) -/*! @} */ - -/*! @name PKRSQ - Poker Square Calculation Result Register */ -/*! @{ */ -#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) -#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) -#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) -/*! @} */ - -/*! @name SDCTL - Seed Control Register */ -/*! @{ */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) -/*! @} */ - -/*! @name SBLIM - Sparse Bit Limit Register */ -/*! @{ */ -#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) -#define TRNG_SBLIM_SB_LIM_SHIFT (0U) -#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) -/*! @} */ - -/*! @name TOTSAM - Total Samples Register */ -/*! @{ */ -#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) -#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) -#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) -/*! @} */ - -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ -/*! @{ */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) -/*! @} */ - -/*! @name FRQCNT - Frequency Count Register */ -/*! @{ */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) -/*! @} */ - -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ -/*! @{ */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) -/*! @} */ - -/*! @name SCMC - Statistical Check Monobit Count Register */ -/*! @{ */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) -/*! @} */ - -/*! @name SCML - Statistical Check Monobit Limit Register */ -/*! @{ */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) -/*! @} */ - -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ -/*! @{ */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) -/*! @} */ - -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ -/*! @{ */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) -/*! @} */ - -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ -/*! @{ */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) -/*! @} */ - -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -/*! @{ */ -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) -/*! @} */ - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -/*! @{ */ -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) -/*! @} */ - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -/*! @{ */ -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) -/*! @} */ - -/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ -/*! @{ */ -#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) -#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) -#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) -#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) -#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) -#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) -/*! @} */ - -/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ -/*! @{ */ -#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) -#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) -#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) -#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) -#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) -#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) -/*! @} */ - -/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ -/*! @{ */ -#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) -#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) -#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) -#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) -#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) -/*! @} */ - -/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ -/*! @{ */ -#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) -#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) -#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) -#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) -#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) -#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) -/*! @} */ - -/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ -/*! @{ */ -#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) -#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) -#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) -#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) -#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) -/*! @} */ - -/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ -/*! @{ */ -#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) -#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) -#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) -#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) -#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) -#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) -#define TRNG_STATUS_TF4BR0_MASK (0x40U) -#define TRNG_STATUS_TF4BR0_SHIFT (6U) -#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) -#define TRNG_STATUS_TF4BR1_MASK (0x80U) -#define TRNG_STATUS_TF4BR1_SHIFT (7U) -#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) -#define TRNG_STATUS_TF5BR0_MASK (0x100U) -#define TRNG_STATUS_TF5BR0_SHIFT (8U) -#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) -#define TRNG_STATUS_TF5BR1_MASK (0x200U) -#define TRNG_STATUS_TF5BR1_SHIFT (9U) -#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) -#define TRNG_STATUS_TF6PBR0_MASK (0x400U) -#define TRNG_STATUS_TF6PBR0_SHIFT (10U) -#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) -#define TRNG_STATUS_TF6PBR1_MASK (0x800U) -#define TRNG_STATUS_TF6PBR1_SHIFT (11U) -#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) -#define TRNG_STATUS_TFSB_MASK (0x1000U) -#define TRNG_STATUS_TFSB_SHIFT (12U) -#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) -#define TRNG_STATUS_TFP_MASK (0x4000U) -#define TRNG_STATUS_TFP_SHIFT (14U) -#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) -/*! @} */ - -/*! @name ENT - Entropy Read Register */ -/*! @{ */ -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) -/*! @} */ - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (16U) - -/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ -/*! @{ */ -#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) -#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) -#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) -#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) -/*! @} */ - -/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ -/*! @{ */ -#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) -#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) -#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) -#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) -/*! @} */ - -/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ -/*! @{ */ -#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) -#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) -#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) -#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) -/*! @} */ - -/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ -/*! @{ */ -#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) -#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) -#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) -#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) -/*! @} */ - -/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ -/*! @{ */ -#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) -#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) -#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) -#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) -/*! @} */ - -/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ -/*! @{ */ -#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) -#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) -#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) -#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) -/*! @} */ - -/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ -/*! @{ */ -#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) -#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) -#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) -#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) -/*! @} */ - -/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ -/*! @{ */ -#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) -#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) -#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) -#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) -/*! @} */ - -/*! @name SEC_CFG - Security Configuration Register */ -/*! @{ */ -#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) -#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) -#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -/*! NO_PRGM - * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. - * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. - */ -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) -#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) -#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) -/*! @} */ - -/*! @name INT_CTRL - Interrupt Control Register */ -/*! @{ */ -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Corresponding bit of INT_STATUS register cleared. - * 0b1..Corresponding bit of INT_STATUS register active. - */ -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) -#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) -#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) -/*! @} */ - -/*! @name INT_MASK - Mask Register */ -/*! @{ */ -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..Corresponding interrupt of INT_STATUS is masked. - * 0b1..Corresponding bit of INT_STATUS is active. - */ -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..Same behavior as bit 0 of this register. - * 0b1..Same behavior as bit 0 of this register. - */ -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -/*! HW_ERR - * 0b0..no error - * 0b1..error detected. - */ -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -/*! ENT_VAL - * 0b0..Busy generation entropy. Any value read is invalid. - * 0b1..TRNG can be stopped and entropy is valid if read. - */ -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -/*! FRQ_CT_FAIL - * 0b0..No hardware nor self test frequency errors. - * 0b1..The frequency counter has detected a failure. - */ -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name VID1 - Version ID Register (MS) */ -/*! @{ */ -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -/*! MIN_REV - * 0b00000000..Minor revision number for TRNG. - */ -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -/*! MAJ_REV - * 0b00000001..Major revision number for TRNG. - */ -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -/*! IP_ID - * 0b0000000000110000..ID for TRNG. - */ -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name VID2 - Version ID Register (LS) */ -/*! @{ */ -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -/*! CONFIG_OPT - * 0b00000000..TRNG_CONFIG_OPT for TRNG. - */ -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -/*! ECO_REV - * 0b00000000..TRNG_ECO_REV for TRNG. - */ -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -/*! INTG_OPT - * 0b00000000..INTG_OPT for TRNG. - */ -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -/*! ERA - * 0b00000000..COMPILE_OPT for TRNG. - */ -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TRNG_Register_Masks */ - - -/* TRNG - Peripheral instance base addresses */ -/** Peripheral TRNG base address */ -#define TRNG_BASE (0x41029000u) -/** Peripheral TRNG base pointer */ -#define TRNG ((TRNG_Type *)TRNG_BASE) -/** Array initializer of TRNG peripheral base addresses */ -#define TRNG_BASE_ADDRS { TRNG_BASE } -/** Array initializer of TRNG peripheral base pointers */ -#define TRNG_BASE_PTRS { TRNG } -/** Interrupt vectors for the TRNG peripheral type */ -#define TRNG_IRQS { TRNG_IRQn } -/** Backward compatibility macros */ -#define TRNG0 TRNG - - -/*! - * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TSTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer - * @{ - */ - -/** TSTMR - Register Layout Typedef */ -typedef struct { - __I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */ - __I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */ -} TSTMR_Type; - -/* ---------------------------------------------------------------------------- - -- TSTMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSTMR_Register_Masks TSTMR Register Masks - * @{ - */ - -/*! @name L - Time Stamp Timer Register Low */ -/*! @{ */ -#define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) -#define TSTMR_L_VALUE_SHIFT (0U) -#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) -/*! @} */ - -/*! @name H - Time Stamp Timer Register High */ -/*! @{ */ -#define TSTMR_H_VALUE_MASK (0xFFFFFFU) -#define TSTMR_H_VALUE_SHIFT (0U) -#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TSTMR_Register_Masks */ - - -/* TSTMR - Peripheral instance base addresses */ -/** Peripheral TSTMRB base address */ -#define TSTMRB_BASE (0x4102C000u) -/** Peripheral TSTMRB base pointer */ -#define TSTMRB ((TSTMR_Type *)TSTMRB_BASE) -/** Array initializer of TSTMR peripheral base addresses */ -#define TSTMR_BASE_ADDRS { TSTMRB_BASE } -/** Array initializer of TSTMR peripheral base pointers */ -#define TSTMR_BASE_PTRS { TSTMRB } - -/*! - * @} - */ /* end of group TSTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ - uint8_t RESERVED_1[3]; - __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ - uint8_t RESERVED_2[3]; - __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ - uint8_t RESERVED_3[15]; - __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ - uint8_t RESERVED_4[99]; - __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ - uint8_t RESERVED_5[3]; - __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ - uint8_t RESERVED_6[3]; - __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ - uint8_t RESERVED_7[3]; - __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ - uint8_t RESERVED_8[3]; - __I uint8_t STAT; /**< Status register, offset: 0x90 */ - uint8_t RESERVED_9[3]; - __IO uint8_t CTL; /**< Control register, offset: 0x94 */ - uint8_t RESERVED_10[3]; - __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ - uint8_t RESERVED_11[3]; - __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ - uint8_t RESERVED_12[3]; - __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ - uint8_t RESERVED_13[3]; - __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ - uint8_t RESERVED_14[11]; - __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ - uint8_t RESERVED_15[3]; - __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ - uint8_t RESERVED_16[11]; - struct { /* offset: 0xC0, array step: 0x4 */ - __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_0[3]; - } ENDPOINT[16]; - __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ - uint8_t RESERVED_17[3]; - __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ - uint8_t RESERVED_18[3]; - __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ - uint8_t RESERVED_19[3]; - __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ - uint8_t RESERVED_20[23]; - __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */ - uint8_t RESERVED_21[3]; - __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */ - uint8_t RESERVED_22[3]; - __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */ - uint8_t RESERVED_23[3]; - __IO uint8_t STALL_IL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */ - uint8_t RESERVED_24[3]; - __IO uint8_t STALL_IH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */ - uint8_t RESERVED_25[3]; - __IO uint8_t STALL_OL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */ - uint8_t RESERVED_26[3]; - __IO uint8_t STALL_OH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */ - uint8_t RESERVED_27[3]; - __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ - uint8_t RESERVED_28[3]; - __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48MFIRC oscillator enable register, offset: 0x144 */ - uint8_t RESERVED_29[15]; - __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ - uint8_t RESERVED_30[7]; - __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name PERID - Peripheral ID register */ -/*! @{ */ -#define USB_PERID_ID_MASK (0x3FU) -#define USB_PERID_ID_SHIFT (0U) -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) -/*! @} */ - -/*! @name IDCOMP - Peripheral ID Complement register */ -/*! @{ */ -#define USB_IDCOMP_NID_MASK (0x3FU) -#define USB_IDCOMP_NID_SHIFT (0U) -#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) -/*! @} */ - -/*! @name REV - Peripheral Revision register */ -/*! @{ */ -#define USB_REV_REV_MASK (0xFFU) -#define USB_REV_REV_SHIFT (0U) -#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) -/*! @} */ - -/*! @name ADDINFO - Peripheral Additional Info register */ -/*! @{ */ -#define USB_ADDINFO_IEHOST_MASK (0x1U) -#define USB_ADDINFO_IEHOST_SHIFT (0U) -#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) -/*! @} */ - -/*! @name OTGCTL - OTG Control register */ -/*! @{ */ -#define USB_OTGCTL_DPHIGH_MASK (0x80U) -#define USB_OTGCTL_DPHIGH_SHIFT (7U) -/*! DPHIGH - D+ Data Line pullup resistor enable - * 0b0..D+ pullup resistor is not enabled - * 0b1..D+ pullup resistor is enabled - */ -#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) -/*! @} */ - -/*! @name ISTAT - Interrupt Status register */ -/*! @{ */ -#define USB_ISTAT_USBRST_MASK (0x1U) -#define USB_ISTAT_USBRST_SHIFT (0U) -#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) -#define USB_ISTAT_ERROR_MASK (0x2U) -#define USB_ISTAT_ERROR_SHIFT (1U) -#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) -#define USB_ISTAT_SOFTOK_MASK (0x4U) -#define USB_ISTAT_SOFTOK_SHIFT (2U) -#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) -#define USB_ISTAT_TOKDNE_MASK (0x8U) -#define USB_ISTAT_TOKDNE_SHIFT (3U) -#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) -#define USB_ISTAT_SLEEP_MASK (0x10U) -#define USB_ISTAT_SLEEP_SHIFT (4U) -#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) -#define USB_ISTAT_RESUME_MASK (0x20U) -#define USB_ISTAT_RESUME_SHIFT (5U) -#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) -#define USB_ISTAT_STALL_MASK (0x80U) -#define USB_ISTAT_STALL_SHIFT (7U) -#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) -/*! @} */ - -/*! @name INTEN - Interrupt Enable register */ -/*! @{ */ -#define USB_INTEN_USBRSTEN_MASK (0x1U) -#define USB_INTEN_USBRSTEN_SHIFT (0U) -/*! USBRSTEN - USBRST Interrupt Enable - * 0b0..Disables the USBRST interrupt. - * 0b1..Enables the USBRST interrupt. - */ -#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) -#define USB_INTEN_ERROREN_MASK (0x2U) -#define USB_INTEN_ERROREN_SHIFT (1U) -/*! ERROREN - ERROR Interrupt Enable - * 0b0..Disables the ERROR interrupt. - * 0b1..Enables the ERROR interrupt. - */ -#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) -#define USB_INTEN_SOFTOKEN_MASK (0x4U) -#define USB_INTEN_SOFTOKEN_SHIFT (2U) -/*! SOFTOKEN - SOFTOK Interrupt Enable - * 0b0..Disbles the SOFTOK interrupt. - * 0b1..Enables the SOFTOK interrupt. - */ -#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) -#define USB_INTEN_TOKDNEEN_MASK (0x8U) -#define USB_INTEN_TOKDNEEN_SHIFT (3U) -/*! TOKDNEEN - TOKDNE Interrupt Enable - * 0b0..Disables the TOKDNE interrupt. - * 0b1..Enables the TOKDNE interrupt. - */ -#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) -#define USB_INTEN_SLEEPEN_MASK (0x10U) -#define USB_INTEN_SLEEPEN_SHIFT (4U) -/*! SLEEPEN - SLEEP Interrupt Enable - * 0b0..Disables the SLEEP interrupt. - * 0b1..Enables the SLEEP interrupt. - */ -#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) -#define USB_INTEN_RESUMEEN_MASK (0x20U) -#define USB_INTEN_RESUMEEN_SHIFT (5U) -/*! RESUMEEN - RESUME Interrupt Enable - * 0b0..Disables the RESUME interrupt. - * 0b1..Enables the RESUME interrupt. - */ -#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) -#define USB_INTEN_STALLEN_MASK (0x80U) -#define USB_INTEN_STALLEN_SHIFT (7U) -/*! STALLEN - STALL Interrupt Enable - * 0b0..Diasbles the STALL interrupt. - * 0b1..Enables the STALL interrupt. - */ -#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) -/*! @} */ - -/*! @name ERRSTAT - Error Interrupt Status register */ -/*! @{ */ -#define USB_ERRSTAT_PIDERR_MASK (0x1U) -#define USB_ERRSTAT_PIDERR_SHIFT (0U) -#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) -#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) -#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) -#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) -#define USB_ERRSTAT_CRC16_MASK (0x4U) -#define USB_ERRSTAT_CRC16_SHIFT (2U) -#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) -#define USB_ERRSTAT_DFN8_MASK (0x8U) -#define USB_ERRSTAT_DFN8_SHIFT (3U) -#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) -#define USB_ERRSTAT_BTOERR_MASK (0x10U) -#define USB_ERRSTAT_BTOERR_SHIFT (4U) -#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) -#define USB_ERRSTAT_DMAERR_MASK (0x20U) -#define USB_ERRSTAT_DMAERR_SHIFT (5U) -#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) -#define USB_ERRSTAT_OWNERR_MASK (0x40U) -#define USB_ERRSTAT_OWNERR_SHIFT (6U) -#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) -#define USB_ERRSTAT_BTSERR_MASK (0x80U) -#define USB_ERRSTAT_BTSERR_SHIFT (7U) -#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) -/*! @} */ - -/*! @name ERREN - Error Interrupt Enable register */ -/*! @{ */ -#define USB_ERREN_PIDERREN_MASK (0x1U) -#define USB_ERREN_PIDERREN_SHIFT (0U) -/*! PIDERREN - PIDERR Interrupt Enable - * 0b0..Disables the PIDERR interrupt. - * 0b1..Enters the PIDERR interrupt. - */ -#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) -#define USB_ERREN_CRC5EOFEN_MASK (0x2U) -#define USB_ERREN_CRC5EOFEN_SHIFT (1U) -/*! CRC5EOFEN - CRC5/EOF Interrupt Enable - * 0b0..Disables the CRC5/EOF interrupt. - * 0b1..Enables the CRC5/EOF interrupt. - */ -#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) -#define USB_ERREN_CRC16EN_MASK (0x4U) -#define USB_ERREN_CRC16EN_SHIFT (2U) -/*! CRC16EN - CRC16 Interrupt Enable - * 0b0..Disables the CRC16 interrupt. - * 0b1..Enables the CRC16 interrupt. - */ -#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) -#define USB_ERREN_DFN8EN_MASK (0x8U) -#define USB_ERREN_DFN8EN_SHIFT (3U) -/*! DFN8EN - DFN8 Interrupt Enable - * 0b0..Disables the DFN8 interrupt. - * 0b1..Enables the DFN8 interrupt. - */ -#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) -#define USB_ERREN_BTOERREN_MASK (0x10U) -#define USB_ERREN_BTOERREN_SHIFT (4U) -/*! BTOERREN - BTOERR Interrupt Enable - * 0b0..Disables the BTOERR interrupt. - * 0b1..Enables the BTOERR interrupt. - */ -#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) -#define USB_ERREN_DMAERREN_MASK (0x20U) -#define USB_ERREN_DMAERREN_SHIFT (5U) -/*! DMAERREN - DMAERR Interrupt Enable - * 0b0..Disables the DMAERR interrupt. - * 0b1..Enables the DMAERR interrupt. - */ -#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) -#define USB_ERREN_OWNERREN_MASK (0x40U) -#define USB_ERREN_OWNERREN_SHIFT (6U) -/*! OWNERREN - OWNERR Interrupt Enable - * 0b0..Disables the OWNERR interrupt. - * 0b1..Enables the OWNERR interrupt. - */ -#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) -#define USB_ERREN_BTSERREN_MASK (0x80U) -#define USB_ERREN_BTSERREN_SHIFT (7U) -/*! BTSERREN - BTSERR Interrupt Enable - * 0b0..Disables the BTSERR interrupt. - * 0b1..Enables the BTSERR interrupt. - */ -#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) -/*! @} */ - -/*! @name STAT - Status register */ -/*! @{ */ -#define USB_STAT_ODD_MASK (0x4U) -#define USB_STAT_ODD_SHIFT (2U) -#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) -#define USB_STAT_TX_MASK (0x8U) -#define USB_STAT_TX_SHIFT (3U) -/*! TX - Transmit Indicator - * 0b0..The most recent transaction was a receive operation. - * 0b1..The most recent transaction was a transmit operation. - */ -#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) -#define USB_STAT_ENDP_MASK (0xF0U) -#define USB_STAT_ENDP_SHIFT (4U) -#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) -/*! @} */ - -/*! @name CTL - Control register */ -/*! @{ */ -#define USB_CTL_USBENSOFEN_MASK (0x1U) -#define USB_CTL_USBENSOFEN_SHIFT (0U) -/*! USBENSOFEN - USB Enable - * 0b0..Disables the USB Module. - * 0b1..Enables the USB Module. - */ -#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) -#define USB_CTL_ODDRST_MASK (0x2U) -#define USB_CTL_ODDRST_SHIFT (1U) -#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) -#define USB_CTL_RESUME_MASK (0x4U) -#define USB_CTL_RESUME_SHIFT (2U) -#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) -#define USB_CTL_HOSTMODEEN_MASK (0x8U) -#define USB_CTL_HOSTMODEEN_SHIFT (3U) -/*! HOSTMODEEN - Host mode enable - * 0b0..USB Module operates in Device mode. - * 0b1..USB Module operates in Host mode. In Host mode, the USB module performs USB transactions under the programmed control of the host processor. - */ -#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) -#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) -#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) -#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) -#define USB_CTL_SE0_MASK (0x40U) -#define USB_CTL_SE0_SHIFT (6U) -#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) -#define USB_CTL_JSTATE_MASK (0x80U) -#define USB_CTL_JSTATE_SHIFT (7U) -#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) -/*! @} */ - -/*! @name ADDR - Address register */ -/*! @{ */ -#define USB_ADDR_ADDR_MASK (0x7FU) -#define USB_ADDR_ADDR_SHIFT (0U) -#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) -/*! @} */ - -/*! @name BDTPAGE1 - BDT Page register 1 */ -/*! @{ */ -#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) -#define USB_BDTPAGE1_BDTBA_SHIFT (1U) -#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) -/*! @} */ - -/*! @name FRMNUML - Frame Number register Low */ -/*! @{ */ -#define USB_FRMNUML_FRM_MASK (0xFFU) -#define USB_FRMNUML_FRM_SHIFT (0U) -#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) -/*! @} */ - -/*! @name FRMNUMH - Frame Number register High */ -/*! @{ */ -#define USB_FRMNUMH_FRM_MASK (0x7U) -#define USB_FRMNUMH_FRM_SHIFT (0U) -#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) -/*! @} */ - -/*! @name BDTPAGE2 - BDT Page Register 2 */ -/*! @{ */ -#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE2_BDTBA_SHIFT (0U) -#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) -/*! @} */ - -/*! @name BDTPAGE3 - BDT Page Register 3 */ -/*! @{ */ -#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE3_BDTBA_SHIFT (0U) -#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) -/*! @} */ - -/*! @name ENDPT - Endpoint Control register */ -/*! @{ */ -#define USB_ENDPT_EPHSHK_MASK (0x1U) -#define USB_ENDPT_EPHSHK_SHIFT (0U) -#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) -#define USB_ENDPT_EPSTALL_MASK (0x2U) -#define USB_ENDPT_EPSTALL_SHIFT (1U) -#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) -#define USB_ENDPT_EPTXEN_MASK (0x4U) -#define USB_ENDPT_EPTXEN_SHIFT (2U) -#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) -#define USB_ENDPT_EPRXEN_MASK (0x8U) -#define USB_ENDPT_EPRXEN_SHIFT (3U) -#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) -#define USB_ENDPT_EPCTLDIS_MASK (0x10U) -#define USB_ENDPT_EPCTLDIS_SHIFT (4U) -#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) -/*! @} */ - -/* The count of USB_ENDPT */ -#define USB_ENDPT_COUNT (16U) - -/*! @name USBCTRL - USB Control register */ -/*! @{ */ -#define USB_USBCTRL_UARTSEL_MASK (0x10U) -#define USB_USBCTRL_UARTSEL_SHIFT (4U) -/*! UARTSEL - UART Select - * 0b0..USB signals are not used as UART signals. - * 0b1..USB signals are used as UART signals. - */ -#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) -#define USB_USBCTRL_UARTCHLS_MASK (0x20U) -#define USB_USBCTRL_UARTCHLS_SHIFT (5U) -/*! UARTCHLS - UART Signal Channel Select - * 0b0..USB DP/DM signals are used as UART TX/RX. - * 0b1..USB DP/DM signals are used as UART RX/TX. - */ -#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) -#define USB_USBCTRL_PDE_MASK (0x40U) -#define USB_USBCTRL_PDE_SHIFT (6U) -/*! PDE - Pulldown enable - * 0b0..Weak pulldowns are disabled on D+ and D-. - * 0b1..Weak pulldowns are enabled on D+ and D-. - */ -#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) -#define USB_USBCTRL_SUSP_MASK (0x80U) -#define USB_USBCTRL_SUSP_SHIFT (7U) -/*! SUSP - Suspend - * 0b0..USB transceiver is not in the Suspend state. - * 0b1..USB transceiver is in the Suspend state. - */ -#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) -/*! @} */ - -/*! @name OBSERVE - USB OTG Observe register */ -/*! @{ */ -#define USB_OBSERVE_DMPD_MASK (0x10U) -#define USB_OBSERVE_DMPD_SHIFT (4U) -/*! DMPD - DMPD - * 0b0..D- pulldown is disabled. - * 0b1..D- pulldown is enabled. - */ -#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) -#define USB_OBSERVE_DPPD_MASK (0x40U) -#define USB_OBSERVE_DPPD_SHIFT (6U) -/*! DPPD - DPPD - * 0b0..D+ pulldown is disabled. - * 0b1..D+ pulldown is enabled. - */ -#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) -#define USB_OBSERVE_DPPU_MASK (0x80U) -#define USB_OBSERVE_DPPU_SHIFT (7U) -/*! DPPU - DPPU - * 0b0..D+ pullup disabled. - * 0b1..D+ pullup enabled. - */ -#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) -/*! @} */ - -/*! @name CONTROL - USB OTG Control register */ -/*! @{ */ -#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) -#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) -/*! DPPULLUPNONOTG - DPPULLUPNONOTG - * 0b0..DP Pullup in non-OTG Device mode is not enabled. - * 0b1..DP Pullup in non-OTG Device mode is enabled. - */ -#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) -/*! @} */ - -/*! @name USBTRC0 - USB Transceiver Control register 0 */ -/*! @{ */ -#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) -#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) -/*! USB_RESUME_INT - USB Asynchronous Interrupt - * 0b0..No interrupt was generated. - * 0b1..Interrupt was generated because of the USB asynchronous interrupt. - */ -#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) -#define USB_USBTRC0_SYNC_DET_MASK (0x2U) -#define USB_USBTRC0_SYNC_DET_SHIFT (1U) -/*! SYNC_DET - Synchronous USB Interrupt Detect - * 0b0..Synchronous interrupt has not been detected. - * 0b1..Synchronous interrupt has been detected. - */ -#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) -#define USB_USBTRC0_VREDG_DET_MASK (0x8U) -#define USB_USBTRC0_VREDG_DET_SHIFT (3U) -/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect - * 0b0..VREGIN rising edge interrupt has not been detected. - * 0b1..VREGIN rising edge interrupt has been detected. - */ -#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) -#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) -#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) -/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect - * 0b0..VREGIN falling edge interrupt has not been detected. - * 0b1..VREGIN falling edge interrupt has been detected. - */ -#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) -#define USB_USBTRC0_USBRESMEN_MASK (0x20U) -#define USB_USBTRC0_USBRESMEN_SHIFT (5U) -/*! USBRESMEN - Asynchronous Resume Interrupt Enable - * 0b0..USB asynchronous wakeup from Suspend mode is disabled. - * 0b1..USB asynchronous wakeup from Suspend mode is enabled. - */ -#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) -#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) -#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) -#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) -#define USB_USBTRC0_USBRESET_MASK (0x80U) -#define USB_USBTRC0_USBRESET_SHIFT (7U) -/*! USBRESET - USB Reset - * 0b0..Normal USB module operation. - * 0b1..Returns the USB module to its reset state. - */ -#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) -/*! @} */ - -/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */ -/*! @{ */ -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) -#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) -/*! STOP_ACK_DLY_EN - STOP_ACK_DLY_EN - * 0b0..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. - * 0b1..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. - */ -#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) -/*! WAKE_REQ_EN - WAKE_REQ_EN - * 0b0..USB bus wakeup request is disabled - * 0b1..USB bus wakeup request is enabled - */ -#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) -/*! KEEP_ALIVE_STS - Keep Alive Status - * 0b0..USB is not in Keep Alive mode. - * 0b1..USB is in Keep Alive mode. - */ -#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) -#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) -/*! @} */ - -/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */ -/*! @{ */ -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) -/*! WAKE_ON_THIS - WAKE_ON_THIS - * 0b0001..Wake up after receiving OUT/SETUP token packet. - * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. - */ -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) -#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) -/*! @} */ - -/*! @name MISCCTRL - Miscellaneous Control register */ -/*! @{ */ -#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) -#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) -/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode - * 0b0..SOF_TOK interrupt is set when byte times SOF threshold is reached. - * 0b1..SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped. - */ -#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) -#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) -#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) -/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select - * 0b0..SOF_TOK interrupt is set according to SOF threshold value. - * 0b1..SOF_TOK interrupt is set when SOF counter reaches 0. - */ -#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) -#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) -#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) -/*! OWNERRISODIS - OWN Error Detect for ISO IN / ISO OUT Disable - * 0b0..OWN error detect for ISO IN / ISO OUT is not disabled. - * 0b1..OWN error detect for ISO IN / ISO OUT is disabled. - */ -#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) -#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) -#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) -/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable - * 0b0..VREGIN rising edge interrupt disabled. - * 0b1..VREGIN rising edge interrupt enabled. - */ -#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) -#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) -#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) -/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable - * 0b0..VREGIN falling edge interrupt disabled. - * 0b1..VREGIN falling edge interrupt enabled. - */ -#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) -#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) -#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) -/*! STL_ADJ_EN - USB Peripheral mode Stall Adjust Enable - * 0b0..If USB_ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint will be stalled - * 0b1..If USB_ENDPTn[END_STALL] = 1, the USB_STALL_xx_DIS registers control which directions for the associated endpoint will be stalled. - */ -#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) -/*! @} */ - -/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */ -/*! @{ */ -#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) -#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) -/*! STALL_I_DIS0 - STALL_I_DIS0 - * 0b0..Endpoint 0 IN direction stall is enabled. - * 0b1..Endpoint 0 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) -#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) -/*! STALL_I_DIS1 - STALL_I_DIS1 - * 0b0..Endpoint 1 IN direction stall is enabled. - * 0b1..Endpoint 1 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) -#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) -/*! STALL_I_DIS2 - STALL_I_DIS2 - * 0b0..Endpoint 2 IN direction stall is enabled. - * 0b1..Endpoint 2 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) -#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) -/*! STALL_I_DIS3 - STALL_I_DIS3 - * 0b0..Endpoint 3 IN direction stall is enabled. - * 0b1..Endpoint 3 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) -#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) -/*! STALL_I_DIS4 - STALL_I_DIS4 - * 0b0..Endpoint 4 IN direction stall is enabled. - * 0b1..Endpoint 4 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) -#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) -/*! STALL_I_DIS5 - STALL_I_DIS5 - * 0b0..Endpoint 5 IN direction stall is enabled. - * 0b1..Endpoint 5 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) -#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) -/*! STALL_I_DIS6 - STALL_I_DIS6 - * 0b0..Endpoint 6 IN direction stall is enabled. - * 0b1..Endpoint 6 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) -#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) -/*! STALL_I_DIS7 - STALL_I_DIS7 - * 0b0..Endpoint 7 IN direction stall is enabled. - * 0b1..Endpoint 7 IN direction stall is disabled. - */ -#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) -/*! @} */ - -/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */ -/*! @{ */ -#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) -#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) -/*! STALL_I_DIS8 - STALL_I_DIS8 - * 0b0..Endpoint 8 IN direction stall is enabled. - * 0b1..Endpoint 8 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) -#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) -/*! STALL_I_DIS9 - STALL_I_DIS9 - * 0b0..Endpoint 9 IN direction stall is enabled. - * 0b1..Endpoint 9 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) -#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) -/*! STALL_I_DIS10 - STALL_I_DIS10 - * 0b0..Endpoint 10 IN direction stall is enabled. - * 0b1..Endpoint 10 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) -#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) -/*! STALL_I_DIS11 - STALL_I_DIS11 - * 0b0..Endpoint 11 IN direction stall is enabled. - * 0b1..Endpoint 11 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) -#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) -/*! STALL_I_DIS12 - STALL_I_DIS12 - * 0b0..Endpoint 12 IN direction stall is enabled. - * 0b1..Endpoint 12 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) -#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) -/*! STALL_I_DIS13 - STALL_I_DIS13 - * 0b0..Endpoint 13 IN direction stall is enabled. - * 0b1..Endpoint 13 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) -#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) -/*! STALL_I_DIS14 - STALL_I_DIS14 - * 0b0..Endpoint 14 IN direction stall is enabled. - * 0b1..Endpoint 14 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) -#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) -/*! STALL_I_DIS15 - STALL_I_DIS15 - * 0b0..Endpoint 15 IN direction stall is enabled. - * 0b1..Endpoint 15 IN direction stall is disabled. - */ -#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) -/*! @} */ - -/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */ -/*! @{ */ -#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) -#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) -/*! STALL_O_DIS0 - STALL_O_DIS0 - * 0b0..Endpoint 0 OUT direction stall is enabled. - * 0b1..Endpoint 0 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) -#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) -/*! STALL_O_DIS1 - STALL_O_DIS1 - * 0b0..Endpoint 1 OUT direction stall is enabled. - * 0b1..Endpoint 1 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) -#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) -/*! STALL_O_DIS2 - STALL_O_DIS2 - * 0b0..Endpoint 2 OUT direction stall is enabled. - * 0b1..Endpoint 2 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) -#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) -/*! STALL_O_DIS3 - STALL_O_DIS3 - * 0b0..Endpoint 3 OUT direction stall is enabled. - * 0b1..Endpoint 3 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) -#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) -/*! STALL_O_DIS4 - STALL_O_DIS4 - * 0b0..Endpoint 4 OUT direction stall is enabled. - * 0b1..Endpoint 4 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) -#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) -/*! STALL_O_DIS5 - STALL_O_DIS5 - * 0b0..Endpoint 5 OUT direction stall is enabled. - * 0b1..Endpoint 5 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) -#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) -/*! STALL_O_DIS6 - STALL_O_DIS6 - * 0b0..Endpoint 6 OUT direction stall is enabled. - * 0b1..Endpoint 6 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) -#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) -/*! STALL_O_DIS7 - STALL_O_DIS7 - * 0b0..Endpoint 7 OUT direction stall is enabled. - * 0b1..Endpoint 7 OUT direction stall is disabled. - */ -#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) -/*! @} */ - -/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */ -/*! @{ */ -#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) -#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) -/*! STALL_O_DIS8 - STALL_O_DIS8 - * 0b0..Endpoint 8 OUT direction stall is enabled. - * 0b1..Endpoint 8 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) -#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) -/*! STALL_O_DIS9 - STALL_O_DIS9 - * 0b0..Endpoint 9 OUT direction stall is enabled. - * 0b1..Endpoint 9 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) -#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) -/*! STALL_O_DIS10 - STALL_O_DIS10 - * 0b0..Endpoint 10 OUT direction stall is enabled. - * 0b1..Endpoint 10 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) -#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) -/*! STALL_O_DIS11 - STALL_O_DIS11 - * 0b0..Endpoint 11 OUT direction stall is enabled. - * 0b1..Endpoint 11 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) -#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) -/*! STALL_O_DIS12 - STALL_O_DIS12 - * 0b0..Endpoint 12 OUT direction stall is enabled. - * 0b1..Endpoint 12 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) -#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) -/*! STALL_O_DIS13 - STALL_O_DIS13 - * 0b0..Endpoint 13 OUT direction stall is enabled. - * 0b1..Endpoint 13 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) -#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) -/*! STALL_O_DIS14 - STALL_O_DIS14 - * 0b0..Endpoint 14 OUT direction stall is enabled. - * 0b1..Endpoint 14 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) -#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) -/*! STALL_O_DIS15 - STALL_O_DIS15 - * 0b0..Endpoint 15 OUT direction stall is enabled. - * 0b1..Endpoint 15 OUT direction stall is disabled. - */ -#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ -/*! @{ */ -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) -/*! RESTART_IFRTRIM_EN - Restart from IFR trim value - * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default). - * 0b1..Trim fine restarts from the IFR trim value, whenever bus_reset/bus_resume is detected or module enable is desasserted. - */ -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) -/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable - * 0b0..Always works in tracking phase after the first time rough phase, to track transition (default). - * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. - */ -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) -/*! CLOCK_RECOVER_EN - Crystal-less USB enable - * 0b0..Disable clock recovery block (default) - * 0b1..Enable clock recovery block - */ -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_IRC_EN - IRC48MFIRC oscillator enable register */ -/*! @{ */ -#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) -#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) -/*! REG_EN - Regulator enable - * 0b0..IRC48M local regulator is disabled - * 0b1..IRC48M local regulator is enabled (default) - */ -#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) -/*! IRC_EN - IRC_EN - * 0b0..Disable the IRC48M module (default) - * 0b1..Enable the IRC48M module - */ -#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ -/*! @{ */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) -/*! OVF_ERROR_EN - OVF_ERROR_EN - * 0b0..The interrupt will be masked - * 0b1..The interrupt will be enabled (default) - */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) -/*! @} */ - -/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ -/*! @{ */ -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) -/*! OVF_ERROR - OVF_ERROR - * 0b0..No interrupt is reported - * 0b1..Unmasked interrupt has been generated - */ -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40045000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBVREG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBVREG_Peripheral_Access_Layer USBVREG Peripheral Access Layer - * @{ - */ - -/** USBVREG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< USB VREG Control Register, offset: 0x0 */ - __IO uint32_t CFGCTRL; /**< USB VREG Configuration Control Register, offset: 0x4 */ -} USBVREG_Type; - -/* ---------------------------------------------------------------------------- - -- USBVREG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBVREG_Register_Masks USBVREG Register Masks - * @{ - */ - -/*! @name CTRL - USB VREG Control Register */ -/*! @{ */ -#define USBVREG_CTRL_VSTBY_MASK (0x20000000U) -#define USBVREG_CTRL_VSTBY_SHIFT (29U) -/*! VSTBY - USB Voltage Regulator in Standby Mode during VLPR and VLPW modes - * 0b0..USB voltage regulator is not in standby during VLPR and VLPW modes. - * 0b1..USB voltage regulator in standby during VLPR and VLPW modes. - */ -#define USBVREG_CTRL_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_VSTBY_SHIFT)) & USBVREG_CTRL_VSTBY_MASK) -#define USBVREG_CTRL_SSTBY_MASK (0x40000000U) -#define USBVREG_CTRL_SSTBY_SHIFT (30U) -/*! SSTBY - USB Voltage Regulator in Standby Mode during Stop, VLPS, LLS and VLLS Modes - * 0b0..USB voltage regulator is not in standby during Stop,VLPS,LLS and VLLS modes. - * 0b1..USB voltage regulator is in standby during Stop,VLPS,LLS and VLLS modes. - */ -#define USBVREG_CTRL_SSTBY(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_SSTBY_SHIFT)) & USBVREG_CTRL_SSTBY_MASK) -#define USBVREG_CTRL_EN_MASK (0x80000000U) -#define USBVREG_CTRL_EN_SHIFT (31U) -/*! EN - USB Voltage Regulator Enable - * 0b0..USB voltage regulator is disabled. - * 0b1..USB voltage regulator is enabled. - */ -#define USBVREG_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_EN_SHIFT)) & USBVREG_CTRL_EN_MASK) -/*! @} */ - -/*! @name CFGCTRL - USB VREG Configuration Control Register */ -/*! @{ */ -#define USBVREG_CFGCTRL_URWE_MASK (0x1000000U) -#define USBVREG_CFGCTRL_URWE_SHIFT (24U) -/*! URWE - USB Voltage Regulator Enable Write Enable - * 0b0..CTRL[EN] can not be written. - * 0b1..CTRL[EN] can be written. - */ -#define USBVREG_CFGCTRL_URWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_URWE_SHIFT)) & USBVREG_CFGCTRL_URWE_MASK) -#define USBVREG_CFGCTRL_UVSWE_MASK (0x2000000U) -#define USBVREG_CFGCTRL_UVSWE_SHIFT (25U) -/*! UVSWE - USB Voltage Regulator VLP Standby Write Enable - * 0b0..CTRL[VSTBY] cannot be written. - * 0b1..CTRL[VSTBY] can be written. - */ -#define USBVREG_CFGCTRL_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_UVSWE_SHIFT)) & USBVREG_CFGCTRL_UVSWE_MASK) -#define USBVREG_CFGCTRL_USSWE_MASK (0x4000000U) -#define USBVREG_CFGCTRL_USSWE_SHIFT (26U) -/*! USSWE - USB Voltage Rregulator Stop Standby Write Enable - * 0b0..CTRL[SSTBY] field cannot be written. - * 0b1..CTRL[SSTBY] can be written. - */ -#define USBVREG_CFGCTRL_USSWE(x) (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_USSWE_SHIFT)) & USBVREG_CFGCTRL_USSWE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBVREG_Register_Masks */ - - -/* USBVREG - Peripheral instance base addresses */ -/** Peripheral USBVREG base address */ -#define USBVREG_BASE (0x40027000u) -/** Peripheral USBVREG base pointer */ -#define USBVREG ((USBVREG_Type *)USBVREG_BASE) -/** Array initializer of USBVREG peripheral base addresses */ -#define USBVREG_BASE_ADDRS { USBVREG_BASE } -/** Array initializer of USBVREG peripheral base pointers */ -#define USBVREG_BASE_PTRS { USBVREG } - -/*! - * @} - */ /* end of group USBVREG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USDHC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer - * @{ - */ - -/** USDHC - Register Layout Typedef */ -typedef struct { - __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ - __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ - __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ - __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ - __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ - __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ - __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ - __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ - __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ - __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ - __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ - __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ - __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ - __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ - __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ - __I uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ - __I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ - __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ - __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ - uint8_t RESERVED_0[4]; - __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ - __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ - __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ - uint8_t RESERVED_1[100]; - __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ - __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ - __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ -} USDHC_Type; - -/* ---------------------------------------------------------------------------- - -- USDHC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Register_Masks USDHC Register Masks - * @{ - */ - -/*! @name DS_ADDR - DMA System Address */ -/*! @{ */ -#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) -#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) -#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) -/*! @} */ - -/*! @name BLK_ATT - Block Attributes */ -/*! @{ */ -#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) -#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) -/*! BLKSIZE - Block Size - * 0b1000000000000..4096 Bytes - * 0b0100000000000..2048 Bytes - * 0b0001000000000..512 Bytes - * 0b0000111111111..511 Bytes - * 0b0000000000100..4 Bytes - * 0b0000000000011..3 Bytes - * 0b0000000000010..2 Bytes - * 0b0000000000001..1 Byte - * 0b0000000000000..No data transfer - */ -#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) -#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) -#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) -/*! BLKCNT - Block Count - * 0b1111111111111111..65535 blocks - * 0b0000000000000010..2 blocks - * 0b0000000000000001..1 block - * 0b0000000000000000..Stop Count - */ -#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) -/*! @} */ - -/*! @name CMD_ARG - Command Argument */ -/*! @{ */ -#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) -#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) -#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) -/*! @} */ - -/*! @name CMD_XFR_TYP - Command Transfer Type */ -/*! @{ */ -#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) -#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) -/*! RSPTYP - Response Type Select - * 0b00..No Response - * 0b01..Response Length 136 - * 0b10..Response Length 48 - * 0b11..Response Length 48, check Busy after response - */ -#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) -#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) -#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) -/*! CCCEN - Command CRC Check Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) -#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) -#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) -/*! CICEN - Command Index Check Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) -#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) -#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) -/*! DPSEL - Data Present Select - * 0b1..Data Present - * 0b0..No Data Present - */ -#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) -#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) -#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) -/*! CMDTYP - Command Type - * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR - * 0b10..Resume CMD52 for writing Function Select in CCCR - * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR - * 0b00..Normal Other commands - */ -#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) -#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) -#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) -#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) -/*! @} */ - -/*! @name CMD_RSP0 - Command Response0 */ -/*! @{ */ -#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) -#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) -/*! @} */ - -/*! @name CMD_RSP1 - Command Response1 */ -/*! @{ */ -#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) -#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) -/*! @} */ - -/*! @name CMD_RSP2 - Command Response2 */ -/*! @{ */ -#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) -#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) -/*! @} */ - -/*! @name CMD_RSP3 - Command Response3 */ -/*! @{ */ -#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) -#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) -/*! @} */ - -/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ -/*! @{ */ -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) -/*! @} */ - -/*! @name PRES_STATE - Present State */ -/*! @{ */ -#define USDHC_PRES_STATE_CIHB_MASK (0x1U) -#define USDHC_PRES_STATE_CIHB_SHIFT (0U) -/*! CIHB - Command Inhibit (CMD) - * 0b1..Cannot issue command - * 0b0..Can issue command using only CMD line - */ -#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) -#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) -#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) -/*! CDIHB - Command Inhibit (DATA) - * 0b1..Cannot issue command which uses the DATA line - * 0b0..Can issue command which uses the DATA line - */ -#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) -#define USDHC_PRES_STATE_DLA_MASK (0x4U) -#define USDHC_PRES_STATE_DLA_SHIFT (2U) -/*! DLA - Data Line Active - * 0b1..DATA Line Active - * 0b0..DATA Line Inactive - */ -#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) -#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) -#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) -/*! SDSTB - SD Clock Stable - * 0b1..Clock is stable. - * 0b0..Clock is changing frequency and not stable. - */ -#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) -#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) -#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) -/*! IPGOFF - IPG_CLK Gated Off Internally - * 0b1..IPG_CLK is gated off. - * 0b0..IPG_CLK is active. - */ -#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) -#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) -#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) -/*! HCKOFF - HCLK Gated Off Internally - * 0b1..HCLK is gated off. - * 0b0..HCLK is active. - */ -#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) -#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) -#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) -/*! PEROFF - IPG_PERCLK Gated Off Internally - * 0b1..IPG_PERCLK is gated off. - * 0b0..IPG_PERCLK is active. - */ -#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) -#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) -#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) -/*! SDOFF - SD Clock Gated Off Internally - * 0b1..SD Clock is gated off. - * 0b0..SD Clock is active. - */ -#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) -#define USDHC_PRES_STATE_WTA_MASK (0x100U) -#define USDHC_PRES_STATE_WTA_SHIFT (8U) -/*! WTA - Write Transfer Active - * 0b1..Transferring data - * 0b0..No valid data - */ -#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) -#define USDHC_PRES_STATE_RTA_MASK (0x200U) -#define USDHC_PRES_STATE_RTA_SHIFT (9U) -/*! RTA - Read Transfer Active - * 0b1..Transferring data - * 0b0..No valid data - */ -#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) -#define USDHC_PRES_STATE_BWEN_MASK (0x400U) -#define USDHC_PRES_STATE_BWEN_SHIFT (10U) -/*! BWEN - Buffer Write Enable - * 0b1..Write enable - * 0b0..Write disable - */ -#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) -#define USDHC_PRES_STATE_BREN_MASK (0x800U) -#define USDHC_PRES_STATE_BREN_SHIFT (11U) -/*! BREN - Buffer Read Enable - * 0b1..Read enable - * 0b0..Read disable - */ -#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) -#define USDHC_PRES_STATE_CINST_MASK (0x10000U) -#define USDHC_PRES_STATE_CINST_SHIFT (16U) -/*! CINST - Card Inserted - * 0b1..Card Inserted - * 0b0..Power on Reset or No Card - */ -#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) -#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) -#define USDHC_PRES_STATE_CDPL_SHIFT (18U) -/*! CDPL - Card Detect Pin Level - * 0b1..Card present (CD_B = 0) - * 0b0..No card present (CD_B = 1) - */ -#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) -#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) -#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) -/*! WPSPL - Write Protect Switch Pin Level - * 0b1..Write enabled (WP = 0) - * 0b0..Write protected (WP = 1) - */ -#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) -#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) -#define USDHC_PRES_STATE_CLSL_SHIFT (23U) -#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) -#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) -#define USDHC_PRES_STATE_DLSL_SHIFT (24U) -/*! DLSL - DATA[7:0] Line Signal Level - * 0b00000111..Data 7 line signal level - * 0b00000110..Data 6 line signal level - * 0b00000101..Data 5 line signal level - * 0b00000100..Data 4 line signal level - * 0b00000011..Data 3 line signal level - * 0b00000010..Data 2 line signal level - * 0b00000001..Data 1 line signal level - * 0b00000000..Data 0 line signal level - */ -#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) -/*! @} */ - -/*! @name PROT_CTRL - Protocol Control */ -/*! @{ */ -#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) -#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) -/*! LCTL - LED Control - * 0b1..LED on - * 0b0..LED off - */ -#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) -#define USDHC_PROT_CTRL_DTW_MASK (0x6U) -#define USDHC_PROT_CTRL_DTW_SHIFT (1U) -/*! DTW - Data Transfer Width - * 0b10..8-bit mode - * 0b01..4-bit mode - * 0b00..1-bit mode - * 0b11..Reserved - */ -#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) -#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) -#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) -/*! D3CD - DATA3 as Card Detection Pin - * 0b1..DATA3 as Card Detection Pin - * 0b0..DATA3 does not monitor Card Insertion - */ -#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) -#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) -#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) -/*! EMODE - Endian Mode - * 0b00..Big Endian Mode - * 0b01..Half Word Big Endian Mode - * 0b10..Little Endian Mode - * 0b11..Reserved - */ -#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) -#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) -#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) -/*! CDTL - Card Detect Test Level - * 0b1..Card Detect Test Level is 1, card inserted - * 0b0..Card Detect Test Level is 0, no card inserted - */ -#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) -#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) -#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) -/*! CDSS - Card Detect Signal Selection - * 0b1..Card Detection Test Level is selected (for test purpose). - * 0b0..Card Detection Level is selected (for normal purpose). - */ -#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) -#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) -#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) -/*! DMASEL - DMA Select - * 0b00..No DMA or Simple DMA is selected - * 0b01..ADMA1 is selected - * 0b10..ADMA2 is selected - * 0b11..reserved - */ -#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) -#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) -#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) -/*! SABGREQ - Stop At Block Gap Request - * 0b1..Stop - * 0b0..Transfer - */ -#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) -#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) -#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) -/*! CREQ - Continue Request - * 0b1..Restart - * 0b0..No effect - */ -#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) -#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) -#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) -/*! RWCTL - Read Wait Control - * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set - * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set - */ -#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) -#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) -#define USDHC_PROT_CTRL_IABG_SHIFT (19U) -/*! IABG - Interrupt At Block Gap - * 0b1..Enabled - * 0b0..Disabled - */ -#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) -#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) -#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) -/*! WECINT - Wakeup Event Enable On Card Interrupt - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) -#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) -#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) -/*! WECINS - Wakeup Event Enable On SD Card Insertion - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) -#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) -#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) -/*! WECRM - Wakeup Event Enable On SD Card Removal - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) -#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) -#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) -/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP - * 0bxx1..Burst length is enabled for INCR - * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 - * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP - */ -#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) -/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD - * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. - * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. - */ -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) -/*! @} */ - -/*! @name SYS_CTRL - System Control */ -/*! @{ */ -#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) -#define USDHC_SYS_CTRL_DVS_SHIFT (4U) -/*! DVS - Divisor - * 0b0000..Divide-by-1 - * 0b0001..Divide-by-2 - * 0b1110..Divide-by-15 - * 0b1111..Divide-by-16 - */ -#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) -#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) -#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) -#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) -#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) -#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) -/*! DTOCV - Data Timeout Counter Value - * 0b1111..SDCLK x 2 29 - * 0b1110..SDCLK x 2 28 - * 0b1101..SDCLK x 2 27 - * 0b0001..SDCLK x 2 15 - * 0b0000..SDCLK x 2 14 - */ -#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) -#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) -#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) -#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) -#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) -#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) -/*! RSTA - Software Reset For ALL - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) -#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) -#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) -/*! RSTC - Software Reset For CMD Line - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) -#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) -#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) -/*! RSTD - Software Reset For DATA Line - * 0b1..Reset - * 0b0..No Reset - */ -#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) -#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) -#define USDHC_SYS_CTRL_INITA_SHIFT (27U) -#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status */ -/*! @{ */ -#define USDHC_INT_STATUS_CC_MASK (0x1U) -#define USDHC_INT_STATUS_CC_SHIFT (0U) -/*! CC - Command Complete - * 0b1..Command complete - * 0b0..Command not complete - */ -#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) -#define USDHC_INT_STATUS_TC_MASK (0x2U) -#define USDHC_INT_STATUS_TC_SHIFT (1U) -/*! TC - Transfer Complete - * 0b1..Transfer complete - * 0b0..Transfer not complete - */ -#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) -#define USDHC_INT_STATUS_BGE_MASK (0x4U) -#define USDHC_INT_STATUS_BGE_SHIFT (2U) -/*! BGE - Block Gap Event - * 0b1..Transaction stopped at block gap - * 0b0..No block gap event - */ -#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) -#define USDHC_INT_STATUS_DINT_MASK (0x8U) -#define USDHC_INT_STATUS_DINT_SHIFT (3U) -/*! DINT - DMA Interrupt - * 0b1..DMA Interrupt is generated - * 0b0..No DMA Interrupt - */ -#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) -#define USDHC_INT_STATUS_BWR_MASK (0x10U) -#define USDHC_INT_STATUS_BWR_SHIFT (4U) -/*! BWR - Buffer Write Ready - * 0b1..Ready to write buffer: - * 0b0..Not ready to write buffer - */ -#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) -#define USDHC_INT_STATUS_BRR_MASK (0x20U) -#define USDHC_INT_STATUS_BRR_SHIFT (5U) -/*! BRR - Buffer Read Ready - * 0b1..Ready to read buffer - * 0b0..Not ready to read buffer - */ -#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) -#define USDHC_INT_STATUS_CINS_MASK (0x40U) -#define USDHC_INT_STATUS_CINS_SHIFT (6U) -/*! CINS - Card Insertion - * 0b1..Card inserted - * 0b0..Card state unstable or removed - */ -#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) -#define USDHC_INT_STATUS_CRM_MASK (0x80U) -#define USDHC_INT_STATUS_CRM_SHIFT (7U) -/*! CRM - Card Removal - * 0b1..Card removed - * 0b0..Card state unstable or inserted - */ -#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) -#define USDHC_INT_STATUS_CINT_MASK (0x100U) -#define USDHC_INT_STATUS_CINT_SHIFT (8U) -/*! CINT - Card Interrupt - * 0b1..Generate Card Interrupt - * 0b0..No Card Interrupt - */ -#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) -#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) -#define USDHC_INT_STATUS_CTOE_SHIFT (16U) -/*! CTOE - Command Timeout Error - * 0b1..Time out - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) -#define USDHC_INT_STATUS_CCE_MASK (0x20000U) -#define USDHC_INT_STATUS_CCE_SHIFT (17U) -/*! CCE - Command CRC Error - * 0b1..CRC Error Generated. - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) -#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) -#define USDHC_INT_STATUS_CEBE_SHIFT (18U) -/*! CEBE - Command End Bit Error - * 0b1..End Bit Error Generated - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) -#define USDHC_INT_STATUS_CIE_MASK (0x80000U) -#define USDHC_INT_STATUS_CIE_SHIFT (19U) -/*! CIE - Command Index Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) -#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) -#define USDHC_INT_STATUS_DTOE_SHIFT (20U) -/*! DTOE - Data Timeout Error - * 0b1..Time out - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) -#define USDHC_INT_STATUS_DCE_MASK (0x200000U) -#define USDHC_INT_STATUS_DCE_SHIFT (21U) -/*! DCE - Data CRC Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) -#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) -#define USDHC_INT_STATUS_DEBE_SHIFT (22U) -/*! DEBE - Data End Bit Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) -#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) -#define USDHC_INT_STATUS_AC12E_SHIFT (24U) -/*! AC12E - Auto CMD12 Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) -#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) -#define USDHC_INT_STATUS_DMAE_SHIFT (28U) -/*! DMAE - DMA Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) -/*! @} */ - -/*! @name INT_STATUS_EN - Interrupt Status Enable */ -/*! @{ */ -#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) -#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) -/*! CCSEN - Command Complete Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) -#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) -#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) -/*! TCSEN - Transfer Complete Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) -#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) -#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) -/*! BGESEN - Block Gap Event Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) -#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) -#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) -/*! DINTSEN - DMA Interrupt Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) -#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) -#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) -/*! BWRSEN - Buffer Write Ready Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) -#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) -#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) -/*! BRRSEN - Buffer Read Ready Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) -#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) -#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) -/*! CINSSEN - Card Insertion Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) -#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) -#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) -/*! CRMSEN - Card Removal Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) -#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) -#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) -/*! CINTSEN - Card Interrupt Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) -#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) -#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) -/*! CTOESEN - Command Timeout Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) -#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) -#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) -/*! CCESEN - Command CRC Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) -#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) -#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) -/*! CEBESEN - Command End Bit Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) -#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) -#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) -/*! CIESEN - Command Index Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) -#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) -#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) -/*! DTOESEN - Data Timeout Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) -#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) -#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) -/*! DCESEN - Data CRC Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) -#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) -#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) -/*! DEBESEN - Data End Bit Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) -#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) -#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) -/*! AC12ESEN - Auto CMD12 Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) -#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) -#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) -/*! DMAESEN - DMA Error Status Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) -/*! @} */ - -/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ -/*! @{ */ -#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) -#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) -/*! CCIEN - Command Complete Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) -#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) -/*! TCIEN - Transfer Complete Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) -#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) -/*! BGEIEN - Block Gap Event Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) -#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) -/*! DINTIEN - DMA Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) -#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) -/*! BWRIEN - Buffer Write Ready Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) -#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) -/*! BRRIEN - Buffer Read Ready Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) -#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) -/*! CINSIEN - Card Insertion Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) -#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) -/*! CRMIEN - Card Removal Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) -#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) -/*! CINTIEN - Card Interrupt Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) -/*! CTOEIEN - Command Timeout Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) -#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) -/*! CCEIEN - Command CRC Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) -/*! CEBEIEN - Command End Bit Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) -#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) -/*! CIEIEN - Command Index Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) -/*! DTOEIEN - Data Timeout Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) -#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) -/*! DCEIEN - Data CRC Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) -/*! DEBEIEN - Data End Bit Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) -/*! AC12EIEN - Auto CMD12 Error Interrupt Enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) -/*! DMAEIEN - DMA Error Interrupt Enable - * 0b1..Enable - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) -/*! @} */ - -/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ -/*! @{ */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) -/*! AC12NE - Auto CMD12 Not Executed - * 0b1..Not executed - * 0b0..Executed - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) -/*! AC12TOE - Auto CMD12 / 23 Timeout Error - * 0b1..Time out - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) -/*! AC12EBE - Auto CMD12 / 23 End Bit Error - * 0b1..End Bit Error Generated - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) -/*! AC12CE - Auto CMD12 / 23 CRC Error - * 0b1..CRC Error Met in Auto CMD12/23 Response - * 0b0..No CRC error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) -/*! AC12IE - Auto CMD12 / 23 Index Error - * 0b1..Error, the CMD index in response is not CMD12/23 - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) -/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error - * 0b1..Not Issued - * 0b0..No error - */ -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) -/*! @} */ - -/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ -/*! @{ */ -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) -#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) -/*! MBL - Max Block Length - * 0b000..512 bytes - * 0b001..1024 bytes - * 0b010..2048 bytes - * 0b011..4096 bytes - */ -#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) -#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) -#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) -/*! ADMAS - ADMA Support - * 0b1..Advanced DMA Supported - * 0b0..Advanced DMA Not supported - */ -#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) -#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) -#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) -/*! HSS - High Speed Support - * 0b1..High Speed Supported - * 0b0..High Speed Not Supported - */ -#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) -#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) -#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) -/*! DMAS - DMA Support - * 0b1..DMA Supported - * 0b0..DMA not supported - */ -#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) -#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) -#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) -/*! SRS - Suspend / Resume Support - * 0b1..Supported - * 0b0..Not supported - */ -#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) -#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) -#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) -/*! VS33 - Voltage Support 3.3V - * 0b1..3.3V supported - * 0b0..3.3V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) -#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) -#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) -/*! VS30 - Voltage Support 3.0 V - * 0b1..3.0V supported - * 0b0..3.0V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) -#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) -#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) -/*! VS18 - Voltage Support 1.8 V - * 0b1..1.8V supported - * 0b0..1.8V not supported - */ -#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) -/*! @} */ - -/*! @name WTMK_LVL - Watermark Level */ -/*! @{ */ -#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) -#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) -#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) -#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) -#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) -#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) -#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) -#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) -#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) -#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) -#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) -#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) -/*! @} */ - -/*! @name MIX_CTRL - Mixer Control */ -/*! @{ */ -#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) -#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) -/*! DMAEN - DMA Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) -#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) -#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) -/*! BCEN - Block Count Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) -#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) -#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) -/*! AC12EN - Auto CMD12 Enable - * 0b1..Enable - * 0b0..Disable - */ -#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) -#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) -#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) -#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) -#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) -#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) -/*! DTDSEL - Data Transfer Direction Select - * 0b1..Read (Card to Host) - * 0b0..Write (Host to Card) - */ -#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) -#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) -#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) -/*! MSBSEL - Multi / Single Block Select - * 0b1..Multiple Blocks - * 0b0..Single Block - */ -#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) -#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) -#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) -#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) -#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) -#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) -#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) -/*! @} */ - -/*! @name FORCE_EVENT - Force Event */ -/*! @{ */ -#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) -#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) -#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) -#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) -#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) -#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) -#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) -#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) -#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) -#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) -#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) -#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) -#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) -#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) -#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) -#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) -#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) -#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) -#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) -#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) -#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) -#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) -#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) -#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) -#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) -#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) -#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) -#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) -#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) -#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) -#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) -/*! @} */ - -/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ -/*! @{ */ -#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) -#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) -#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) -#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) -/*! ADMALME - ADMA Length Mismatch Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) -/*! ADMADCE - ADMA Descriptor Error - * 0b1..Error - * 0b0..No Error - */ -#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) -/*! @} */ - -/*! @name ADMA_SYS_ADDR - ADMA System Address */ -/*! @{ */ -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) -/*! @} */ - -/*! @name VEND_SPEC - Vendor Specific Register */ -/*! @{ */ -#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) -#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) -/*! VSELECT - Voltage Selection - * 0b1..Change the voltage to low voltage range, around 1.8 V - * 0b0..Change the voltage to high voltage range, around 3.0 V - */ -#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) -/*! CONFLICT_CHK_EN - Conflict check enable. - * 0b0..Conflict check disable - * 0b1..Conflict check enable - */ -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) -/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN - * 0b0..Do not check busy after auto CMD12 for write data packet - * 0b1..Check busy after auto CMD12 for write data packet - */ -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) -/*! FRC_SDCLK_ON - FRC_SDCLK_ON - * 0b0..CLK active or inactive is fully controlled by the hardware. - * 0b1..Force CLK active. - */ -#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) -/*! CRC_CHK_DIS - CRC Check Disable - * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet - * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet - */ -#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) -/*! CMD_BYTE_EN - CMD_BYTE_EN - * 0b0..Disable - * 0b1..Enable - */ -#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) -/*! @} */ - -/*! @name MMC_BOOT - MMC Boot Register */ -/*! @{ */ -#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) -#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) -/*! DTOCV_ACK - DTOCV_ACK - * 0b0000..SDCLK x 2^14 - * 0b0001..SDCLK x 2^15 - * 0b0010..SDCLK x 2^16 - * 0b0011..SDCLK x 2^17 - * 0b0100..SDCLK x 2^18 - * 0b0101..SDCLK x 2^19 - * 0b0110..SDCLK x 2^20 - * 0b0111..SDCLK x 2^21 - * 0b1110..SDCLK x 2^28 - * 0b1111..SDCLK x 2^29 - */ -#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) -#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) -/*! BOOT_ACK - BOOT_ACK - * 0b0..No ack - * 0b1..Ack - */ -#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) -#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) -/*! BOOT_MODE - BOOT_MODE - * 0b0..Normal boot - * 0b1..Alternative boot - */ -#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) -#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) -#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) -/*! BOOT_EN - BOOT_EN - * 0b0..Fast boot disable - * 0b1..Fast boot enable - */ -#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) -/*! DISABLE_TIME_OUT - Disable Time Out - * 0b0..Enable time out - * 0b1..Disable time out - */ -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) -/*! @} */ - -/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ -/*! @{ */ -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) -/*! CARD_INT_D3_TEST - Card Interrupt Detection Test - * 0b0..Check the card interrupt only when DATA3 is high. - * 0b1..Check the card interrupt by ignoring the status of DATA3. - */ -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) -/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 - * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. - * 0b0..Disable - */ -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_AHB_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_AHB_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_AHB_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USDHC_Register_Masks */ - - -/* USDHC - Peripheral instance base addresses */ -/** Peripheral USDHC0 base address */ -#define USDHC0_BASE (0x4003E000u) -/** Peripheral USDHC0 base pointer */ -#define USDHC0 ((USDHC_Type *)USDHC0_BASE) -/** Array initializer of USDHC peripheral base addresses */ -#define USDHC_BASE_ADDRS { USDHC0_BASE } -/** Array initializer of USDHC peripheral base pointers */ -#define USDHC_BASE_PTRS { USDHC0 } -/** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { USDHC0_IRQn } - -/*! - * @} - */ /* end of group USDHC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- VREF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer - * @{ - */ - -/** VREF - Register Layout Typedef */ -typedef struct { - __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ - __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ - uint8_t RESERVED_0[3]; - __IO uint8_t TRM4; /**< VREF Trim 2.1V Register, offset: 0x5 */ -} VREF_Type; - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/*! @name TRM - VREF Trim Register */ -/*! @{ */ -#define VREF_TRM_TRIM_MASK (0x3FU) -#define VREF_TRM_TRIM_SHIFT (0U) -/*! TRIM - Trim bits - * 0b000000..Min - * 0b111111..Max - */ -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) -#define VREF_TRM_CHOPEN_MASK (0x40U) -#define VREF_TRM_CHOPEN_SHIFT (6U) -/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized. - * 0b0..Chop oscillator is disabled. - * 0b1..Chop oscillator is enabled. - */ -#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) -/*! @} */ - -/*! @name SC - VREF Status and Control Register */ -/*! @{ */ -#define VREF_SC_MODE_LV_MASK (0x3U) -#define VREF_SC_MODE_LV_SHIFT (0U) -/*! MODE_LV - Buffer Mode selection - * 0b00..Bandgap on only, for stabilization and startup - * 0b01..High power buffer mode enabled - * 0b10..Low-power buffer mode enabled - * 0b11..Reserved - */ -#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) -#define VREF_SC_VREFST_MASK (0x4U) -#define VREF_SC_VREFST_SHIFT (2U) -/*! VREFST - Internal Voltage Reference stable - * 0b0..The module is disabled or not stable. - * 0b1..The module is stable. - */ -#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) -#define VREF_SC_ICOMPEN_MASK (0x20U) -#define VREF_SC_ICOMPEN_SHIFT (5U) -/*! ICOMPEN - Second order curvature compensation enable - * 0b0..Disabled - * 0b1..Enabled - */ -#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) -#define VREF_SC_REGEN_MASK (0x40U) -#define VREF_SC_REGEN_SHIFT (6U) -/*! REGEN - Regulator enable - * 0b0..Internal 1.75 V regulator is disabled. - * 0b1..Internal 1.75 V regulator is enabled. - */ -#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) -#define VREF_SC_VREFEN_MASK (0x80U) -#define VREF_SC_VREFEN_SHIFT (7U) -/*! VREFEN - Internal Voltage Reference enable - * 0b0..The module is disabled. - * 0b1..The module is enabled. - */ -#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) -/*! @} */ - -/*! @name TRM4 - VREF Trim 2.1V Register */ -/*! @{ */ -#define VREF_TRM4_TRIM2V1_MASK (0x3FU) -#define VREF_TRM4_TRIM2V1_SHIFT (0U) -/*! TRIM2V1 - VREF 2.1V Trim Bits - * 0b000000..Max - * 0b111111..Min - */ -#define VREF_TRM4_TRIM2V1(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_TRIM2V1_SHIFT)) & VREF_TRM4_TRIM2V1_MASK) -#define VREF_TRM4_VREF2V1_EN_MASK (0x80U) -#define VREF_TRM4_VREF2V1_EN_SHIFT (7U) -/*! VREF2V1_EN - Internal Voltage Reference (2.1V) Enable - * 0b0..VREF 2.1V is enabled - * 0b1..VREF 2.1V is disabled - */ -#define VREF_TRM4_VREF2V1_EN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group VREF_Register_Masks */ - - -/* VREF - Peripheral instance base addresses */ -/** Peripheral VREF base address */ -#define VREF_BASE (0x4004D000u) -/** Peripheral VREF base pointer */ -#define VREF ((VREF_Type *)VREF_BASE) -/** Array initializer of VREF peripheral base addresses */ -#define VREF_BASE_ADDRS { VREF_BASE } -/** Array initializer of VREF peripheral base pointers */ -#define VREF_BASE_PTRS { VREF } - -/*! - * @} - */ /* end of group VREF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer - * @{ - */ - -/** WDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ - __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ - __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ - __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ -} WDOG_Type; - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/*! @name CS - Watchdog Control and Status Register */ -/*! @{ */ -#define WDOG_CS_STOP_MASK (0x1U) -#define WDOG_CS_STOP_SHIFT (0U) -/*! STOP - Stop Enable - * 0b0..Watchdog disabled in chip stop mode. - * 0b1..Watchdog enabled in chip stop mode. - */ -#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) -#define WDOG_CS_WAIT_MASK (0x2U) -#define WDOG_CS_WAIT_SHIFT (1U) -/*! WAIT - Wait Enable - * 0b0..Watchdog disabled in chip wait mode. - * 0b1..Watchdog enabled in chip wait mode. - */ -#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) -#define WDOG_CS_DBG_MASK (0x4U) -#define WDOG_CS_DBG_SHIFT (2U) -/*! DBG - Debug Enable - * 0b0..Watchdog disabled in chip debug mode. - * 0b1..Watchdog enabled in chip debug mode. - */ -#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) -#define WDOG_CS_TST_MASK (0x18U) -#define WDOG_CS_TST_SHIFT (3U) -/*! TST - Watchdog Test - * 0b00..Watchdog test mode disabled. - * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. - * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. - * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. - */ -#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) -#define WDOG_CS_UPDATE_MASK (0x20U) -#define WDOG_CS_UPDATE_SHIFT (5U) -/*! UPDATE - Allow updates - * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. - * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. - */ -#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) -#define WDOG_CS_INT_MASK (0x40U) -#define WDOG_CS_INT_SHIFT (6U) -/*! INT - Watchdog Interrupt - * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. - * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. - */ -#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) -#define WDOG_CS_EN_MASK (0x80U) -#define WDOG_CS_EN_SHIFT (7U) -/*! EN - Watchdog Enable - * 0b0..Watchdog disabled. - * 0b1..Watchdog enabled. - */ -#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) -#define WDOG_CS_CLK_MASK (0x300U) -#define WDOG_CS_CLK_SHIFT (8U) -/*! CLK - Watchdog Clock - * 0b00..Bus clock - * 0b01..LPO clock - * 0b10..INTCLK (internal clock) - * 0b11..ERCLK (external reference clock) - */ -#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) -#define WDOG_CS_RCS_MASK (0x400U) -#define WDOG_CS_RCS_SHIFT (10U) -/*! RCS - Reconfiguration Success - * 0b0..Reconfiguring WDOG. - * 0b1..Reconfiguration is successful. - */ -#define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) -#define WDOG_CS_ULK_MASK (0x800U) -#define WDOG_CS_ULK_SHIFT (11U) -/*! ULK - Unlock status - * 0b0..WDOG is locked. - * 0b1..WDOG is unlocked. - */ -#define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) -#define WDOG_CS_PRES_MASK (0x1000U) -#define WDOG_CS_PRES_SHIFT (12U) -/*! PRES - Watchdog prescaler - * 0b0..256 prescaler disabled. - * 0b1..256 prescaler enabled. - */ -#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) -#define WDOG_CS_CMD32EN_MASK (0x2000U) -#define WDOG_CS_CMD32EN_SHIFT (13U) -/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words - * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. - * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. - */ -#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) -#define WDOG_CS_FLG_MASK (0x4000U) -#define WDOG_CS_FLG_SHIFT (14U) -/*! FLG - Watchdog Interrupt Flag - * 0b0..No interrupt occurred. - * 0b1..An interrupt occurred. - */ -#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) -#define WDOG_CS_WIN_MASK (0x8000U) -#define WDOG_CS_WIN_SHIFT (15U) -/*! WIN - Watchdog Window - * 0b0..Window mode disabled. - * 0b1..Window mode enabled. - */ -#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) -/*! @} */ - -/*! @name CNT - Watchdog Counter Register */ -/*! @{ */ -#define WDOG_CNT_CNTLOW_MASK (0xFFU) -#define WDOG_CNT_CNTLOW_SHIFT (0U) -#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) -#define WDOG_CNT_CNTHIGH_MASK (0xFF00U) -#define WDOG_CNT_CNTHIGH_SHIFT (8U) -#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) -/*! @} */ - -/*! @name TOVAL - Watchdog Timeout Value Register */ -/*! @{ */ -#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) -#define WDOG_TOVAL_TOVALLOW_SHIFT (0U) -#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) -#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) -#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) -#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) -/*! @} */ - -/*! @name WIN - Watchdog Window Register */ -/*! @{ */ -#define WDOG_WIN_WINLOW_MASK (0xFFU) -#define WDOG_WIN_WINLOW_SHIFT (0U) -#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) -#define WDOG_WIN_WINHIGH_MASK (0xFF00U) -#define WDOG_WIN_WINHIGH_SHIFT (8U) -#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WDOG_Register_Masks */ - - -/* WDOG - Peripheral instance base addresses */ -/** Peripheral WDOG0 base address */ -#define WDOG0_BASE (0x4002A000u) -/** Peripheral WDOG0 base pointer */ -#define WDOG0 ((WDOG_Type *)WDOG0_BASE) -/** Peripheral WDOG1 base address */ -#define WDOG1_BASE (0x41026000u) -/** Peripheral WDOG1 base pointer */ -#define WDOG1 ((WDOG_Type *)WDOG1_BASE) -/** Array initializer of WDOG peripheral base addresses */ -#define WDOG_BASE_ADDRS { WDOG0_BASE, WDOG1_BASE } -/** Array initializer of WDOG peripheral base pointers */ -#define WDOG_BASE_PTRS { WDOG0, WDOG1 } -/** Interrupt vectors for the WDOG peripheral type */ -#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn } -/* Extra definition */ -#define WDOG_UPDATE_KEY (0xD928C520U) -#define WDOG_REFRESH_KEY (0xB480A602U) - - -/*! - * @} - */ /* end of group WDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer - * @{ - */ - -/** XCVR_ANALOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t BB_LDO_1; /**< RF Analog Baseband LDO Control 1, offset: 0x0 */ - __IO uint32_t BB_LDO_2; /**< RF Analog Baseband LDO Control 2, offset: 0x4 */ - __IO uint32_t RX_ADC; /**< RF Analog ADC Control, offset: 0x8 */ - __IO uint32_t RX_BBA; /**< RF Analog BBA Control, offset: 0xC */ - __IO uint32_t RX_LNA; /**< RF Analog LNA Control, offset: 0x10 */ - __IO uint32_t RX_TZA; /**< RF Analog TZA Control, offset: 0x14 */ - __IO uint32_t RX_AUXPLL; /**< RF Analog Aux PLL Control, offset: 0x18 */ - __IO uint32_t SY_CTRL_1; /**< RF Analog Synthesizer Control 1, offset: 0x1C */ - __IO uint32_t SY_CTRL_2; /**< RF Analog Synthesizer Control 2, offset: 0x20 */ - __IO uint32_t TX_DAC_PA; /**< RF Analog TX HPM DAC and PA Control, offset: 0x24 */ - __IO uint32_t BALUN_TX; /**< RF Analog Balun TX Mode Control, offset: 0x28 */ - __IO uint32_t BALUN_RX; /**< RF Analog Balun RX Mode Control, offset: 0x2C */ - __I uint32_t DFT_OBSV_1; /**< RF Analog DFT Observation Register 1, offset: 0x30 */ - __IO uint32_t DFT_OBSV_2; /**< RF Analog DFT Observation Register 2, offset: 0x34 */ - __IO uint32_t DFT_OBSV_3; /**< RF Analog DFT Observation Register 3, offset: 0x38 */ -} XCVR_ANALOG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks - * @{ - */ - -/*! @name BB_LDO_1 - RF Analog Baseband LDO Control 1 */ -/*! @{ */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK (0x1U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT (0U) -/*! BB_LDO_ADCDAC_BYP - rmap_bb_ldo_adcdac_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK (0x2U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT (1U) -/*! BB_LDO_ADCDAC_DIAGSEL - rmap_bb_ldo_adcdac_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK (0xCU) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT (2U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK (0x70U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT (4U) -/*! BB_LDO_ADCDAC_TRIM - rmap_bb_ldo_adcdac_trim[2:0] - * 0b000..1.20 V ( Default ) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK (0x100U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT (8U) -/*! BB_LDO_BBA_BYP - rmap_bb_ldo_bba_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK (0x200U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT (9U) -/*! BB_LDO_BBA_DIAGSEL - rmap_bb_ldo_bba_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK (0xC00U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT (10U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK (0x7000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT (12U) -/*! BB_LDO_BBA_TRIM - rmap_bb_ldo_bba_trim[2:0] - * 0b000..1.20 V ( Default ) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK (0x10000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT (16U) -/*! BB_LDO_FDBK_BYP - rmap_bb_ldo_fdbk_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK (0x20000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT (17U) -/*! BB_LDO_FDBK_DIAGSEL - rmap_bb_ldo_fdbk_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK (0xC0000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT (18U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK (0x700000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT (20U) -/*! BB_LDO_FDBK_TRIM - rmap_bb_ldo_fdbk_trim[2:0] - * 0b000..1.2/1.176 V ( Default ) - * 0b001..1.138/1.115 V - * 0b010..1.085/1.066 V - * 0b011..1.04/1.025 V - * 0b100..1.28/1.25 V - * 0b101..1.4/1.35 V - * 0b110..1.55/1.4 V - * 0b111..1.78/1.4 V - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK (0x1000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT (24U) -/*! BB_LDO_HF_BYP - rmap_bb_ldo_hf_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK (0x2000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT (25U) -/*! BB_LDO_HF_DIAGSEL - rmap_bb_ldo_hf_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK (0xC000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT (26U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK (0x70000000U) -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT (28U) -/*! BB_LDO_HF_TRIM - rmap_bb_ldo_hf_trim[2:0] - * 0b000..1.20 V ( Default ) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK) -/*! @} */ - -/*! @name BB_LDO_2 - RF Analog Baseband LDO Control 2 */ -/*! @{ */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK (0x1U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT (0U) -/*! BB_LDO_PD_BYP - rmap_bb_ldo_pd_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK (0x2U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT (1U) -/*! BB_LDO_PD_DIAGSEL - rmap_bb_ldo_pd_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK (0xCU) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT (2U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK (0x70U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT (4U) -/*! BB_LDO_PD_TRIM - rmap_bb_ldo_pd_trim[2:0] - * 0b000..1.20 V ( Default ) - * 0b001..1.25 V - * 0b010..1.28 V - * 0b011..1.33 V - * 0b100..1.40 V - * 0b101..1.44 V - * 0b110..1.50 V - * 0b111..1.66 V - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK (0x300U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT (8U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK (0x400U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT (10U) -/*! BB_LDO_VCOLO_BYP - rmap_bb_ldo_vcolo_byp - * 0b0..Bypass disabled. - * 0b1..Bypass enabled - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT (11U) -/*! BB_LDO_VCOLO_DIAGSEL - rmap_bb_ldo_vcolo_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK (0x7000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT (12U) -/*! BB_LDO_VCOLO_TRIM - rmap_bb_ldo_vcolo_trim[2:0] - * 0b000..1.138/1.117 V ( Default ) - * 0b001..1.076/1.058 V - * 0b010..1.027/1.012 V - * 0b011..0.98/0.97 V - * 0b100..1.22/1.19 V - * 0b101..1.33/1.3 V - * 0b110..1.5/1.4 V - * 0b111..1.82/1.4 V - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK (0x10000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT (16U) -/*! BB_LDO_VTREF_DIAGSEL - rmap_bb_ldo_vtref_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK (0x60000U) -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT (17U) -/*! BB_LDO_VTREF_TC - rmap_bb_ldo_vtref_tc[1:0] - * 0b00..1.117/1.176 V - * 0b01..1.134/1.188 V - * 0b10..1.10/1.162 V - * 0b11..1.09/1.152 V - */ -#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK) -/*! @} */ - -/*! @name RX_ADC - RF Analog ADC Control */ -/*! @{ */ -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK (0xFFU) -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT (0U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK (0x300U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT (8U) -/*! RX_ADC_FS_SEL - rmap_rx_adc_fs_sel[1:0] - * 0b00..52MHz (2x26MHz) - * 0b01..64MHz (2x32MHz) - * 0b10..+13% of 64MHz - * 0b11..- 11% of 64MHz - */ -#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK (0x400U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT (10U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT (11U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK (0xF000U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT (12U) -#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK) -/*! @} */ - -/*! @name RX_BBA - RF Analog BBA Control */ -/*! @{ */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK (0x7U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT (0U) -/*! RX_BBA_BW_SEL - rmap_rx_bba_bw_sel[2:0] - * 0b000..1000K - * 0b001..900K - * 0b010..800K - * 0b011..700K Default - * 0b100..600K - * 0b101..500K - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK (0x8U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT (3U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK (0x10U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT (4U) -/*! RX_BBA_DIAGSEL1 - rmap_rx_bba_diagsel1 - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK (0x20U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT (5U) -/*! RX_BBA_DIAGSEL2 - rmap_rx_bba_diagsel2 - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK (0x40U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT (6U) -/*! RX_BBA_DIAGSEL3 - rmap_rx_bba_diagsel3 - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK (0x80U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT (7U) -/*! RX_BBA_DIAGSEL4 - rmap_rx_bba_diagsel4 - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK (0x3F0000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT (16U) -/*! RX_BBA_SPARE - rmap_rx_bba_spare[5:0] - * 0b000000..600mV (Default) - * 0b000001..675mV - * 0b000010..450mV - * 0b000011..525mV - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK (0x7000000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT (24U) -/*! RX_BBA2_BW_SEL - rmap_bba2_bw_sel[2:0] - * 0b000..1000K - * 0b001..900K - * 0b010..800K - * 0b011..700K Default - * 0b100..600K - * 0b101..500K - */ -#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK (0x70000000U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT (28U) -#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK) -/*! @} */ - -/*! @name RX_LNA - RF Analog LNA Control */ -/*! @{ */ -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK (0xFU) -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT (0U) -/*! RX_LNA_BUMP - rmap_rx_lna_bump[3:0] - * 0b0000..Default - * 0b0001..-25% - * 0b0010..+50% - * 0b0011..+25% - * 0b0100..CM 480mV - * 0b1000..CM 600mV - * 0b1100..CM 660mV - */ -#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK (0x10U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT (4U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK (0x20U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT (5U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK (0x40U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT (6U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK (0x300U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT (8U) -#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK (0xF0000U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT (16U) -/*! RX_MIXER_BUMP - rmap_rx_mixer_bump[3:0] - * 0b0000..825mV (Default) - * 0b0001..750mV - * 0b0010..900mV - * 0b0011..975mV - */ -#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK (0x100000U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT (20U) -#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK) -/*! @} */ - -/*! @name RX_TZA - RF Analog TZA Control */ -/*! @{ */ -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK (0x7U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT (0U) -/*! RX_TZA_BW_SEL - rmap_rx_tza_bw_sel[2:0] - * 0b000..1000K - * 0b001..900K - * 0b010..800K - * 0b011..700K Default - * 0b100..600K - * 0b101..500K - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK (0x8U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT (3U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK (0x10U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT (4U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK (0x3F0000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT (16U) -/*! RX_TZA_SPARE - rmap_rx_tza_spare[5:0] - * 0b000000..600mV (Default) - * 0b000001..675mV - * 0b000010..450mV - * 0b000011..525mV - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK (0x1000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT (24U) -/*! RX_TZA1_DIAGSEL - rmap_rx_tza1_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK (0x2000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT (25U) -/*! RX_TZA2_DIAGSEL - rmap_rx_tza2_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK (0x4000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT (26U) -/*! RX_TZA3_DIAGSEL - rmap_rx_tza3_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK) -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK (0x8000000U) -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT (27U) -/*! RX_TZA4_DIAGSEL - rmap_rx_tza4_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK) -/*! @} */ - -/*! @name RX_AUXPLL - RF Analog Aux PLL Control */ -/*! @{ */ -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK (0x7U) -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT (0U) -#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK (0x8U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT (3U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK (0x10U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT (4U) -#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK (0xE0U) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT (5U) -#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK) -#define XCVR_ANALOG_RX_AUXPLL_SPARE_MASK (0xF00U) -#define XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT (8U) -#define XCVR_ANALOG_RX_AUXPLL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_SPARE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK (0xF000U) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT (12U) -#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK (0x10000U) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT (16U) -#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK (0x300000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT (20U) -/*! RXTX_BAL_BIAST - rmap_rxtx_bal_biast[1:0] - * 0b00..0.6 - * 0b01..0.4 - * 0b10..0.9 - * 0b11..1.2 - */ -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK (0x7000000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT (24U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK (0x10000000U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT (28U) -#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK) -/*! @} */ - -/*! @name SY_CTRL_1 - RF Analog Synthesizer Control 1 */ -/*! @{ */ -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK (0x1U) -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT (0U) -#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK (0x2U) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT (1U) -#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK (0x30U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT (4U) -/*! SY_LO_BUMP_RTLO_FDBK - rmap_sy_lo_bump_rtlo_fdbk[1:0] - * 0b00..1.045 V - * 0b01..1.084 V - * 0b10..1.097 V - * 0b11..1.10 V - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK (0xC0U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT (6U) -/*! SY_LO_BUMP_RTLO_RX - rmap_sy_lo_bump_rtlo_rx[1:0] - * 0b00..1.051/1.037 V - * 0b01..1.082/1.075 V - * 0b10..1.092/1.088 V - * 0b11..1.098/1.094 V - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK (0x300U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT (8U) -/*! SY_LO_BUMP_RTLO_TX - rmap_sy_lo_bump_rtlo_tx[1:0] - * 0b00..1.071/1.065 V - * 0b01..1.092/1.090 V - * 0b10..1.099/1.098 V - * 0b11..1.10/1.1 V - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK (0x400U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT (10U) -/*! SY_LO_DIAGSEL - rmap_sy_lo_diagsel - * 0b0..Diag disable - * 0b1..Diag enable - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK (0x7000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT (12U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK (0x70000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT (16U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK (0x80000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT (19U) -#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK (0x100000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT (20U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK (0x600000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT (21U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK (0x800000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT (23U) -/*! SY_PD_PCH_SEL - rmap_sy_pd_pch_sel - * 0b0..inverter based precharge - * 0b1..resistor divider based precharge - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK (0x3000000U) -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT (24U) -/*! SY_PD_SPARE - rmap_sy_pd_spare[1:0] - * 0b00..Default ; - * 0b01..PD output is pulled down. - */ -#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK) -/*! @} */ - -/*! @name SY_CTRL_2 - RF Analog Synthesizer Control 2 */ -/*! @{ */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK (0x7U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT (0U) -/*! SY_VCO_BIAS - rmap_sy_vco_bias[2:0] - * 0b000..0.97V - * 0b001..1.033V - * 0b010..1.06V - * 0b011..1.07V - * 0b100..1.08V - * 0b101..1.085V - * 0b110..1.090V - * 0b111..1.095V - */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK (0x8U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT (3U) -/*! SY_VCO_DIAGSEL - rmap_sy_vco_diagsel - * 0b1..Diag enable - * 0b0..Diag disable - */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK (0x70U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT (4U) -/*! SY_VCO_KV - rmap_sy_vco_kv[2:0] - * 0b000..50MHz/V - * 0b001..60MHz/V - * 0b010..70MHz/V - * 0b011..80MHz/V - * 0b100..80MHz/V - * 0b101..80MHz/V - * 0b110..80MHz/V - * 0b111..80MHz/V - */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK (0x700U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT (8U) -/*! SY_VCO_KVM - rmap_sy_vco_kvm[2:0] - * 0b000..10MHz/V - * 0b001..20MHz/V - * 0b010..30MHz/V - * 0b011..40MHz/V - * 0b100..40MHz/V - * 0b101..40MHz/V - * 0b110..40MHz/V - * 0b111..40MHz/V - */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK (0x1000U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT (12U) -/*! SY_VCO_PK_DET_ON - rmap_sy_vco_pk_det_on - * 0b1..Enable - * 0b0..Disable - */ -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK (0x1C000U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT (14U) -#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK) -/*! @} */ - -/*! @name TX_DAC_PA - RF Analog TX HPM DAC and PA Control */ -/*! @{ */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK (0x3U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT (0U) -/*! TX_DAC_BUMP_CAP - rmap_tx_dac_bump_cap[1:0] - * 0b00..1pF(default) - * 0b01..1.5pF - * 0b10..1.5pF - * 0b11..2pF - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK (0x18U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT (3U) -/*! TX_DAC_BUMP_IDAC - rmap_tx_dac_bump_idac[1:0] - * 0b00..250nA(default) - * 0b01..207nA - * 0b10..312nA - * 0b11..415nA - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK (0xC0U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT (6U) -/*! TX_DAC_BUMP_RLOAD - rmap_tx_dac_bump_rload[1:0] - * 0b00..3.12 kohms(default) - * 0b01..2.34 kohms - * 0b10..3.9 kohms - * 0b11..4.6 kohms - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK (0x200U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT (9U) -/*! TX_DAC_DIAGSEL - rmap_tx_dac_diagsel - * 0b0..Disable Diag - * 0b1..Enable Diag - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK (0x400U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT (10U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK (0x800U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT (11U) -/*! TX_DAC_OPAMP_DIAGSEL - rmap_tx_dac_opamp_diagsel - * 0b0..Disable Diag - * 0b1..Enable Diag - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK (0xE000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT (13U) -#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK (0xE0000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT (17U) -/*! TX_PA_BUMP_VBIAS - rmap_tx_pa_bump_vbias[2:0] - * 0b000..0.557 - * 0b001..0.651 - * 0b010..0.741 - * 0b011..0.822 - * 0b100..0.590 - * 0b101..0.683 - * 0b110..0.771 - * 0b111..0.850 - */ -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK (0x200000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT (21U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK (0x3800000U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT (23U) -#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK) -/*! @} */ - -/*! @name BALUN_TX - RF Analog Balun TX Mode Control */ -/*! @{ */ -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK (0xFFFFFFU) -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT (0U) -#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK) -/*! @} */ - -/*! @name BALUN_RX - RF Analog Balun RX Mode Control */ -/*! @{ */ -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK (0xFFFFFFU) -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT (0U) -#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK) -/*! @} */ - -/*! @name DFT_OBSV_1 - RF Analog DFT Observation Register 1 */ -/*! @{ */ -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK (0x7FFFFU) -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT (0U) -#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK (0xFFF00000U) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT (20U) -#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK) -/*! @} */ - -/*! @name DFT_OBSV_2 - RF Analog DFT Observation Register 2 */ -/*! @{ */ -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK (0x1FFFFU) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT (0U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK (0x7F000000U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT (24U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK (0x80000000U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT (31U) -#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK) -/*! @} */ - -/*! @name DFT_OBSV_3 - RF Analog DFT Observation Register 3 */ -/*! @{ */ -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_MASK (0x7U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_SHIFT (0U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_MASK) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_MASK (0xFF00U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_SHIFT (8U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_MASK) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_MASK (0xFF0000U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_SHIFT (16U) -#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_ANALOG_Register_Masks */ - - -/* XCVR_ANALOG - Peripheral instance base addresses */ -/** Peripheral XCVR_ANA base address */ -#define XCVR_ANA_BASE (0x41030500u) -/** Peripheral XCVR_ANA base pointer */ -#define XCVR_ANA ((XCVR_ANALOG_Type *)XCVR_ANA_BASE) -/** Array initializer of XCVR_ANALOG peripheral base addresses */ -#define XCVR_ANALOG_BASE_ADDRS { XCVR_ANA_BASE } -/** Array initializer of XCVR_ANALOG peripheral base pointers */ -#define XCVR_ANALOG_BASE_PTRS { XCVR_ANA } - -/*! - * @} - */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_CTRL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_CTRL_Peripheral_Access_Layer XCVR_CTRL Peripheral Access Layer - * @{ - */ - -/** XCVR_CTRL - Register Layout Typedef */ -typedef struct { - __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x0 */ - __IO uint32_t XCVR_STATUS; /**< TRANSCEIVER STATUS, offset: 0x4 */ - __IO uint32_t BLE_ARB_CTRL; /**< BLE ARBITRATION CONTROL, offset: 0x8 */ - __IO uint32_t OVERWRITE_VER; /**< OVERWRITE VERSION, offset: 0xC */ - __IO uint32_t DTEST_CTRL; /**< DIGITAL TEST MUX CONTROL, offset: 0x10 */ - __IO uint32_t DMA_CTRL; /**< TRANSCEIVER DMA CONTROL, offset: 0x14 */ - __I uint32_t DMA_DATA; /**< TRANSCEIVER DMA DATA, offset: 0x18 */ - __IO uint32_t PACKET_RAM_CTRL; /**< PACKET RAM CONTROL, offset: 0x1C */ - __I uint32_t RAM_STOP_ADDR; /**< PACKET RAM DEBUG RAM STOP ADDRESS, offset: 0x20 */ - __IO uint32_t FAD_CTRL; /**< FAD CONTROL, offset: 0x24 */ - __IO uint32_t LPPS_CTRL; /**< LOW POWER PREAMBLE SEARCH CONTROL, offset: 0x28 */ - __IO uint32_t COEX_CTRL; /**< COEXISTENCE CONTROL, offset: 0x2C */ - __IO uint32_t CRCW_CFG; /**< CRC/WHITENER CONFIG REGISTER, offset: 0x30 */ - __I uint32_t CRC_EC_MASK; /**< CRC ERROR CORRECTION MASK, offset: 0x34 */ - __I uint32_t CRC_RES_OUT; /**< CRC RESULT, offset: 0x38 */ - __IO uint32_t CRCW_CFG2; /**< CRC/WHITENER CONFIG 2 REGISTER, offset: 0x3C */ -} XCVR_CTRL_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_CTRL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_CTRL_Register_Masks XCVR_CTRL Register Masks - * @{ - */ - -/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */ -/*! @{ */ -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK (0xFU) -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT (0U) -/*! PROTOCOL - Radio Protocol Selection - * 0b0000..BLE - * 0b0001..BLE in MBAN - * 0b0010..BLE overlap MBAN - * 0b0011..Reserved - * 0b0100..802.15.4 - * 0b0101..802.15.4j - * 0b0110..Radio Channels 0-127 selectable, FSK - * 0b0111..Radio Channels 0-127 selectable, GFSK - * 0b1000..Generic GFSK, with Gaussian Filter - * 0b1001..Generic MSK, O-QPSK encoding - * 0b1010..Generic FSK, direct +/- Fdev FSK - */ -#define XCVR_CTRL_XCVR_CTRL_PROTOCOL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK (0x70U) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT (4U) -#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK) -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK (0x300U) -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT (8U) -/*! REF_CLK_FREQ - Radio Reference Clock Frequency - * 0b00..32 MHz - * 0b01..26 MHz - * 0b10..Reserved - * 0b11..Reserved - */ -#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK (0x800U) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT (11U) -#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT)) & XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK) -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK (0x3000U) -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT (12U) -/*! DEMOD_SEL - Demodulator Selector - * 0b00..No demodulator selected - * 0b01..Use NXP Multi-standard PHY demodulator - * 0b10..Use Legacy 802.15.4 demodulator - * 0b11..Reserved - */ -#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_MASK (0xC000U) -#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_SHIFT (14U) -#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK (0x70000U) -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT (16U) -/*! RADIO0_IRQ_SEL - RADIO0_IRQ_SEL - * 0b000..Assign Radio #0 Interrupt to BLE - * 0b001..Assign Radio #0 Interrupt to 802.15.4 - * 0b010..Radio #0 Interrupt unassigned - * 0b011..Assign Radio #0 Interrupt to GENERIC_FSK - * 0b100..Radio #0 Interrupt unassigned - * 0b101..Radio #0 Interrupt unassigned - * 0b110..Radio #0 Interrupt unassigned - * 0b111..Radio #0 Interrupt unassigned - */ -#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK (0x700000U) -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT (20U) -/*! RADIO1_IRQ_SEL - RADIO1_IRQ_SEL - * 0b000..Assign Radio #1 Interrupt to BLE - * 0b001..Assign Radio #1 Interrupt to 802.15.4 - * 0b010..Radio #1 Interrupt unassigned - * 0b011..Assign Radio #1 Interrupt to GENERIC_FSK - * 0b100..Radio #1 Interrupt unassigned - * 0b101..Radio #1 Interrupt unassigned - * 0b110..Radio #1 Interrupt unassigned - * 0b111..Radio #1 Interrupt unassigned - */ -#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK) -#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_MASK (0xF000000U) -#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_SHIFT (24U) -#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_MASK) -/*! @} */ - -/*! @name XCVR_STATUS - TRANSCEIVER STATUS */ -/*! @{ */ -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK (0xFFU) -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT (0U) -#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK (0xF00U) -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT (8U) -/*! PLL_SEQ_STATE - PLL Sequence State - * 0b0000..PLL OFF - * 0b0010..CTUNE - * 0b0011..CTUNE_SETTLE - * 0b0110..HPMCAL1 - * 0b1000..HPMCAL1_SETTLE - * 0b1010..HPMCAL2 - * 0b1100..HPMCAL2_SETTLE - * 0b1111..PLLREADY - */ -#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK (0x1000U) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT (12U) -#define XCVR_CTRL_XCVR_STATUS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK (0x2000U) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT (13U) -#define XCVR_CTRL_XCVR_STATUS_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK (0x10000U) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT (16U) -#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)) & XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK (0x20000U) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT (17U) -#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK) -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK (0x40000U) -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT (18U) -/*! XTAL_READY - RF Osciallator Xtal Ready - * 0b0..Indicates that the RF Oscillator is disabled or has not completed its warmup. - * 0b1..Indicates that the RF Oscillator has completed its warmup count and is ready for use. - */ -#define XCVR_CTRL_XCVR_STATUS_XTAL_READY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT)) & XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK (0x1000000U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT (24U) -/*! TSM_IRQ0 - TSM Interrupt #0 - * 0b0..TSM Interrupt #0 is not asserted. - * 0b1..TSM Interrupt #0 is asserted. Write '1' to this bit to clear it. - */ -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK (0x2000000U) -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT (25U) -/*! TSM_IRQ1 - TSM Interrupt #1 - * 0b0..TSM Interrupt #1 is not asserted. - * 0b1..TSM Interrupt #1 is asserted. Write '1' to this bit to clear it. - */ -#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK) -/*! @} */ - -/*! @name BLE_ARB_CTRL - BLE ARBITRATION CONTROL */ -/*! @{ */ -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK (0x1U) -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT (0U) -#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK) -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK (0x2U) -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT (1U) -/*! XCVR_BUSY - Transceiver Busy Status Bit - * 0b0..RF Channel in available (TSM is idle) - * 0b1..RF Channel in use (TSM is busy) - */ -#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK) -/*! @} */ - -/*! @name OVERWRITE_VER - OVERWRITE VERSION */ -/*! @{ */ -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK (0xFFU) -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT (0U) -#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT)) & XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK) -/*! @} */ - -/*! @name DTEST_CTRL - DIGITAL TEST MUX CONTROL */ -/*! @{ */ -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK (0x3FU) -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT (0U) -/*! DTEST_PAGE - DTEST Page Selector - * 0b000000..PLLFREQCAL - * 0b000001..PLLBESTDIFF - * 0b000010..PLLRIPPLE - * 0b000011..PLLHPMCAL - * 0b000100..PLLVCOMOD - * 0b000101..PLLUNLOCK - * 0b000110..PLLCYCSLIP - * 0b000111..PLLCHAN - * 0b001000..TXWARMUP - * 0b001001..TXPOWER - * 0b001010..TXFREQWORD - * 0b001011..RXWARMUP - * 0b001100..RXADC - * 0b001101..RXDMA - * 0b001110..RXDIGIQ - * 0b001111..RXDMA2 - * 0b010000..RXINPH - * 0b010001..RSSI0 - * 0b010010..RSSI1 - * 0b010011..AGC0 - * 0b010100..AGC1 - * 0b010101..DCOC0 - * 0b010110..DCOC1 - * 0b010111..DCOC2 - * 0b011000..DCOC3 - * 0b011001..TSM - * 0b011010..MTTSMCAL - * 0b011011..MTADV - * 0b011100..MTINIT - * 0b011101..MTSCAN - * 0b011110..MTCONN - * 0b011111..MTDTM - * 0b100000..MTADVXCV - * 0b100001..MTCONXCV - * 0b100010..MTDTM2 - * 0b100011..DSM - * 0b100100..PHY_FSK_STATE - * 0b100101..PHY_CFO_EST_PD - * 0b100110..PHY_CFO_EST_PD2 - * 0b100111..PHY_EARLY_LATE - * 0b101000..PHY_FSK_DEMOD - * 0b101001..PHY_AA_SEARCH - * 0b101010..PHY_DATA_OUT - * 0b101011..PHY_SAMP_TIME - * 0b101100..CCA_ED_LQI - * 0b101101..CCA_ED_LQI2 - * 0b101110..Reserved - * 0b101111..Reserved - * 0b110000..Reserved - * 0b110001..Reserved - * 0b110010..Reserved - * 0b110011..Reserved - * 0b110100..Reserved - * 0b110101..Reserved - * 0b110110..Reserved - * 0b110111..Reserved - * 0b111000..Reserved - * 0b111001..Reserved - * 0b111010..RCCAL - * 0b111011..AUXPLLFCAL - * 0b111100..GENFSKTX - * 0b111101..GENFSKRX - * 0b111110..GENFSKSTATE - * 0b111111..GENFILTER - */ -#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK) -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (0x80U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT (7U) -/*! DTEST_EN - DTEST Enable - * 0b0..Disables DTEST. The DTEST pins assume their mission function. - * 0b1..Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the DTEST output pins. - */ -#define XCVR_CTRL_DTEST_CTRL_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK (0xF00U) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT (8U) -#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK (0xF000U) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT (12U) -#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK) -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK (0x30000U) -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT (16U) -/*! TSM_GPIO_OVLAY - TSM GPIO Overlay Pin Control - * 0b00..there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin. - * 0b01..the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear. - * 0b10..the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear. - * 0b11..the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear, and the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear. - */ -#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT)) & XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK (0x7000000U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT (24U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK) -#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_MASK (0x8000000U) -#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_SHIFT (27U) -/*! DTEST_CCA2_SEL - DTEST CCA Mode 2 Selector - * 0b0..cca2_max_or_sym[7:0] = cca2_cnt_sym[7:0] - * 0b1..cca2_max_or_sym[7:0] = cca2_cnt_max[7:0] - */ -#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_MASK) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK (0x10000000U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT (28U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK (0x20000000U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT (29U) -#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK) -/*! @} */ - -/*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */ -/*! @{ */ -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK (0xFU) -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT (0U) -/*! DMA_PAGE - Transceiver DMA Page Selector - * 0b0000..DMA Idle - * 0b0001..RX_DIG I and Q - * 0b0010..RX_DIG I Only - * 0b0011..RX_DIG Q Only - * 0b0100..RAW ADC I and Q - * 0b0101..RAW ADC I Only - * 0b0110..RAW ADC Q only - * 0b0111..DC Estimator I and Q - * 0b1000..DC Estimator I Only - * 0b1001..DC Estimator Q only - * 0b1010..RX_DIG Phase Output - * 0b1011..Reserved - * 0b1100..Demodulator Soft Decision - * 0b1101..Demodulator Data Output - * 0b1110..Demodulator CFO Phase Output - * 0b1111..Reserved - */ -#define XCVR_CTRL_DMA_CTRL_DMA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_EN_MASK (0x10U) -#define XCVR_CTRL_DMA_CTRL_DMA_EN_SHIFT (4U) -#define XCVR_CTRL_DMA_CTRL_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_EN_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_EN_MASK) -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK (0x20U) -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT (5U) -/*! BYPASS_DMA_SYNC - Bypass External DMA Synchronization - * 0b0..Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1. - * 0b1..Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0. - */ -#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT)) & XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_MASK (0x40U) -#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT (6U) -#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK (0x80U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT (7U) -/*! DMA_TIMED_OUT - DMA Transfer Timed Out - * 0b0..A DMA timeout has not occurred - * 0b1..A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared - */ -#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK (0xF00U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT (8U) -#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG_MASK (0x7000U) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG_SHIFT (12U) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_TRG_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_TRG_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_MASK (0x8000U) -#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_SHIFT (15U) -/*! DMA_START_EDGE - DMA Start Trigger Edge Selector - * 0b0..Trigger fires on a rising edge of the selected trigger source - * 0b1..Trigger fires on a falling edge of the selected trigger source - */ -#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_MASK) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_MASK (0x10000U) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_SHIFT (16U) -#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_MASK) -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK (0x20000U) -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT (17U) -/*! SINGLE_REQ_MODE - DMA Single Request Mode - * 0b0..Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer. - * 0b1..Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data - */ -#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT)) & XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK) -/*! @} */ - -/*! @name DMA_DATA - TRANSCEIVER DMA DATA */ -/*! @{ */ -#define XCVR_CTRL_DMA_DATA_DMA_DATA_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT (0U) -#define XCVR_CTRL_DMA_DATA_DMA_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT)) & XCVR_CTRL_DMA_DATA_DMA_DATA_MASK) -/*! @} */ - -/*! @name PACKET_RAM_CTRL - PACKET RAM CONTROL */ -/*! @{ */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK (0xFU) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT (0U) -/*! DBG_PAGE - Packet RAM Debug Page Selector - * 0b0000..Packet RAM Debug Mode Idle - * 0b0001..RX_DIG I and Q - * 0b0010..Reserved - * 0b0011..Reserved - * 0b0100..RAW ADC I and Q - * 0b0101..Reserved - * 0b0110..Reserved - * 0b0111..DC Estimator I and Q - * 0b1000..Reserved - * 0b1001..Reserved - * 0b1010..RX_DIG Phase Output - * 0b1011..Reserved - * 0b1100..Demodulator Soft Decision - * 0b1101..Demodulator Data Output - * 0b1110..Demodulator CFO Phase Output - * 0b1111..Reserved - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_MASK (0x10U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_SHIFT (4U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MASK (0x20U) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_SHIFT (5U) -/*! XCVR_RAM_PAGE - RAM Page Selector for XCVR Access - * 0b0..RAM0 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF - * 0b1..RAM1 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK (0x40U) -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT (6U) -/*! XCVR_RAM_ALLOW - Allow Packet RAM Transceiver Access - * 0b0..Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode) - * 0b1..Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK (0x80U) -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT (7U) -/*! ALL_PROTOCOLS_ALLOW - Allow IPS bus access to Packet RAM for any protocol at any time. - * 0b0..IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL]. - * 0b1..All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK (0x300U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT (8U) -/*! DBG_RAM_FULL - DBG_RAM_FULL[1:0] - * 0b00..Neither Packet RAM0 nor RAM1 is full - * 0bx1..Packet RAM0 has been filled to capacity. - * 0b1x..Packet RAM1 has been filled to capacity. - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_MASK (0x400U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT (10U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_MASK (0x800U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_SHIFT (11U) -/*! DBG_SOFT_INFO_SEL - Packet RAM Debug PHY Soft Info Output Selector - * 0b0..PHY output bit_valid_int is used to capture soft decision data - * 0b1..PHY output demod_vout is used to capture soft decision data - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_MASK (0x7000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_SHIFT (12U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_MASK (0x8000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_SHIFT (15U) -/*! DBG_START_EDGE - Packet RAM Debug Start Trigger Edge Selector - * 0b0..Trigger fires on a rising edge of the selected trigger source - * 0b1..Trigger fires on a falling edge of the selected trigger source - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_MASK (0xF0000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_SHIFT (16U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_MASK (0x100000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_SHIFT (20U) -/*! DBG_STOP_EDGE - Packet RAM Debug Stop Trigger Edge Selector - * 0b0..Trigger fires on a rising edge of the selected trigger source - * 0b1..Trigger fires on a falling edge of the selected trigger source - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_MASK (0x200000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_SHIFT (21U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_MASK (0x400000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT (22U) -#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x800000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (23U) -/*! PB_PROTECT - Packet Buffer Protect - * 0b0..Incoming received packets overwrite Packet Buffer RX contents (default) - * 0b1..Incoming received packets are blocked from overwriting Packet Buffer RX contents - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK (0x1000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT (24U) -/*! RAM0_CLK_ON_OVRD_EN - Override control for RAM0 Clock Gate Enable - * 0b0..Normal operation. - * 0b1..Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable. - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK (0x2000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT (25U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK (0x4000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT (26U) -/*! RAM1_CLK_ON_OVRD_EN - Override control for RAM1 Clock Gate Enable - * 0b0..Normal operation. - * 0b1..Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable. - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK (0x8000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT (27U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK (0x10000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT (28U) -/*! RAM0_CE_ON_OVRD_EN - Override control for RAM0 CE (Chip Enable) - * 0b0..Normal operation. - * 0b1..Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE. - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK (0x20000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT (29U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK (0x40000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT (30U) -/*! RAM1_CE_ON_OVRD_EN - Override control for RAM1 CE (Chip Enable) - * 0b0..Normal operation. - * 0b1..Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE. - */ -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK (0x80000000U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT (31U) -#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK) -/*! @} */ - -/*! @name RAM_STOP_ADDR - PACKET RAM DEBUG RAM STOP ADDRESS */ -/*! @{ */ -#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_MASK (0x7FFU) -#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_SHIFT (0U) -#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_SHIFT)) & XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_MASK) -#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_MASK (0x7FF0000U) -#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_SHIFT (16U) -#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_SHIFT)) & XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_MASK) -/*! @} */ - -/*! @name FAD_CTRL - FAD CONTROL */ -/*! @{ */ -#define XCVR_CTRL_FAD_CTRL_FAD_EN_MASK (0x1U) -#define XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT (0U) -/*! FAD_EN - Fast Antenna Diversity Enable - * 0b0..Fast Antenna Diversity disabled - * 0b1..Fast Antenna Diversity enabled - */ -#define XCVR_CTRL_FAD_CTRL_FAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_EN_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_MASK (0x2U) -#define XCVR_CTRL_FAD_CTRL_ANTX_SHIFT (1U) -#define XCVR_CTRL_FAD_CTRL_ANTX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_MASK (0x4U) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_SHIFT (2U) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_MASK (0x8U) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_SHIFT (3U) -#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_OVRD_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_OVRD_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK (0x30U) -#define XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT (4U) -/*! ANTX_EN - FAD Antenna Controls Enable - * 0b00..all disabled (held low) - * 0b01..only RX/TX_SWITCH enabled - * 0b10..only ANT_A/B enabled - * 0b11..all enabled - */ -#define XCVR_CTRL_FAD_CTRL_ANTX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK (0x40U) -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT (6U) -/*! ANTX_HZ - FAD PAD Tristate Control - * 0b0..ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs. - * 0b1..Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance. - */ -#define XCVR_CTRL_FAD_CTRL_ANTX_HZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK (0x80U) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT (7U) -#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK (0xF00U) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT (8U) -#define XCVR_CTRL_FAD_CTRL_ANTX_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK (0xF000U) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT (12U) -#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK) -/*! @} */ - -/*! @name LPPS_CTRL - LOW POWER PREAMBLE SEARCH CONTROL */ -/*! @{ */ -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK (0x1U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT (0U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK (0x2U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT (1U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK (0x4U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT (2U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK (0x8U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT (3U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK (0x10U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT (4U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK (0x20U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT (5U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK (0x40U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT (6U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK (0x80U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT (7U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK (0x100U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT (8U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK (0x200U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT (9U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK (0xFF0000U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT (16U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK (0xFF000000U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT (24U) -#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK) -/*! @} */ - -/*! @name COEX_CTRL - COEXISTENCE CONTROL */ -/*! @{ */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK (0xFU) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT (0U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_MASK (0x10U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT (4U) -/*! RF_NOT_ALLOWED_NO_TX - RF_NOT_ALLOWED_NO_TX - * 0b0..Assertion on RF_NOT_ALLOWED has no effect on TX - * 0b1..Assertion on RF_NOT_ALLOWED can abort TX - */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_MASK (0x20U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT (5U) -/*! RF_NOT_ALLOWED_NO_RX - RF_NOT_ALLOWED_NO_RX - * 0b0..Assertion on RF_NOT_ALLOWED has no effect on RX - * 0b1..Assertion on RF_NOT_ALLOWED can abort RX - */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x40U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (6U) -/*! RF_NOT_ALLOWED_ASSERTED - RF_NOT_ALLOWED_ASSERTED - * 0b0..Assertion on RF_NOT_ALLOWED has not occurred - * 0b1..Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared - */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK (0x80U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT (7U) -/*! RF_NOT_ALLOWED_TX_ABORT - RF_NOT_ALLOWED_TX_ABORT - * 0b0..A TX abort due to assertion on RF_NOT_ALLOWED has not occurred - * 0b1..A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared - */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK (0x100U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT (8U) -/*! RF_NOT_ALLOWED_RX_ABORT - RF_NOT_ALLOWED_RX_ABORT - * 0b0..A RX abort due to assertion on RF_NOT_ALLOWED has not occurred - * 0b1..A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared - */ -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK (0x200U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT (9U) -#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK) -#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_MASK (0xFF0000U) -#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_SHIFT (16U) -#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_SHIFT)) & XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_MASK) -/*! @} */ - -/*! @name CRCW_CFG - CRC/WHITENER CONFIG REGISTER */ -/*! @{ */ -#define XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK (0x1U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT (0U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK) -#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_MASK (0x2U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_SHIFT (1U) -#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK (0x4U) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT (2U) -#define XCVR_CTRL_CRCW_CFG_CRC_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK (0x8U) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT (3U) -#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK (0x10U) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT (4U) -#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK (0x7FF0000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT (16U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK (0x10000000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT (28U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK (0x20000000U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT (29U) -#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK) -/*! @} */ - -/*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */ -/*! @{ */ -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT (0U) -#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK) -/*! @} */ - -/*! @name CRC_RES_OUT - CRC RESULT */ -/*! @{ */ -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK (0xFFFFFFFFU) -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT (0U) -#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK) -/*! @} */ - -/*! @name CRCW_CFG2 - CRC/WHITENER CONFIG 2 REGISTER */ -/*! @{ */ -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK (0xFFU) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT (0U) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_MASK (0xF00U) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT (8U) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_MASK) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_MASK (0xF000U) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT (12U) -#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_CTRL_Register_Masks */ - - -/* XCVR_CTRL - Peripheral instance base addresses */ -/** Peripheral XCVR_MISC base address */ -#define XCVR_MISC_BASE (0x41030280u) -/** Peripheral XCVR_MISC base pointer */ -#define XCVR_MISC ((XCVR_CTRL_Type *)XCVR_MISC_BASE) -/** Array initializer of XCVR_CTRL peripheral base addresses */ -#define XCVR_CTRL_BASE_ADDRS { XCVR_MISC_BASE } -/** Array initializer of XCVR_CTRL peripheral base pointers */ -#define XCVR_CTRL_BASE_PTRS { XCVR_MISC } - -/*! - * @} - */ /* end of group XCVR_CTRL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PHY_Peripheral_Access_Layer XCVR_PHY Peripheral Access Layer - * @{ - */ - -/** XCVR_PHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PHY_FSK_PD_CFG0; /**< Preamble Detect Config 0, offset: 0x0 */ - __IO uint32_t PHY_FSK_PD_CFG1; /**< Preamble Detect Config 1, offset: 0x4 */ - __IO uint32_t PHY_FSK_CFG; /**< PHY Configuration, offset: 0x8 */ - __IO uint32_t PHY_FSK_MISC; /**< PHY Misc. Configuration, offset: 0xC */ - __IO uint32_t NTW_ADR_BSM; /**< PHY BSM Network Address, offset: 0x10 */ - __I uint32_t FSK_STAT; /**< PHY Status, offset: 0x14 */ - __IO uint32_t FSK_FAD_CTRL; /**< PHY FAD control, offset: 0x18 */ -} XCVR_PHY_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PHY_Register_Masks XCVR_PHY Register Masks - * @{ - */ - -/*! @name PHY_FSK_PD_CFG0 - Preamble Detect Config 0 */ -/*! @{ */ -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_MASK (0x1FU) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_SHIFT (0U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_MASK (0x3E0U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_SHIFT (5U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_MASK (0x7C00U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_SHIFT (10U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_MASK (0xF8000U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_SHIFT (15U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_MASK (0x1F00000U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_SHIFT (20U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_MASK (0x3E000000U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_SHIFT (25U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_MASK (0x80000000U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_SHIFT (31U) -#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_MASK) -/*! @} */ - -/*! @name PHY_FSK_PD_CFG1 - Preamble Detect Config 1 */ -/*! @{ */ -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_MASK (0x1FU) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_SHIFT (0U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_MASK (0x3E0U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_SHIFT (5U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_MASK (0x7C00U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_SHIFT (10U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_MASK (0xFF0000U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_SHIFT (16U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_MASK) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_MASK (0xFE000000U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_SHIFT (25U) -#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_MASK) -/*! @} */ - -/*! @name PHY_FSK_CFG - PHY Configuration */ -/*! @{ */ -#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_MASK (0x1U) -#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_SHIFT (0U) -/*! AA_PLAYBACK - * 0b0..PHY will only output bits after the AA. - * 0b1..PHY will output the AA, followed by the rest of the packet bits. - */ -#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_MASK) -#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_MASK (0x2U) -#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_SHIFT (1U) -/*! AA_OUT_SEL - * 0b0..When AA playback is enabled, play back desired AA. - * 0b1..When AA playback is enabled, play back received AA. - */ -#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_MASK) -#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_MASK (0x4U) -#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_SHIFT (2U) -/*! FSK_BIT_INVERT - * 0b0..Normal demodulation. - * 0b1..Invert demodulated bits. This applies at the demodulator, so it affects both AA and the data portions of the packet. - */ -#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_MASK) -#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_MASK (0x8U) -#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_SHIFT (3U) -#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_MASK) -#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_MASK (0x3F0U) -#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_SHIFT (4U) -#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_MASK (0x400U) -#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_SHIFT (10U) -#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_MASK (0x800U) -#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_SHIFT (11U) -#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_MASK (0x3F000U) -#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_SHIFT (12U) -#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_MASK (0x40000U) -#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_SHIFT (18U) -#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_MASK (0x80000U) -#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_SHIFT (19U) -#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_MASK (0x700000U) -#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_SHIFT (20U) -#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_MASK (0x7800000U) -#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_SHIFT (23U) -#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_MASK (0x8000000U) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_SHIFT (27U) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_MASK (0x30000000U) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_SHIFT (28U) -/*! PD_MODE_A - * 0b10..PD mode 2, pattern based preamble detection. - * 0b11..PD mode 3, peak based preamble detection. - */ -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_MASK) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_MASK (0xC0000000U) -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_SHIFT (30U) -/*! PD_MODE_B - * 0b10..PD mode 2, pattern based preamble detection. - * 0b11..PD mode 3, peak based preamble detection. - */ -#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_MASK) -/*! @} */ - -/*! @name PHY_FSK_MISC - PHY Misc. Configuration */ -/*! @{ */ -#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA_MASK (0x1U) -#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA_SHIFT (0U) -#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_FORCE_AA_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_FORCE_AA_MASK) -#define XCVR_PHY_PHY_FSK_MISC_EL_EN_MASK (0x2U) -#define XCVR_PHY_PHY_FSK_MISC_EL_EN_SHIFT (1U) -#define XCVR_PHY_PHY_FSK_MISC_EL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_EN_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_EN_MASK) -#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_MASK (0xF0U) -#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_SHIFT (4U) -#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_MASK) -#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_MASK (0x3F00U) -#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_SHIFT (8U) -#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_MASK) -#define XCVR_PHY_PHY_FSK_MISC_MSK_EN_MASK (0x4000U) -#define XCVR_PHY_PHY_FSK_MISC_MSK_EN_SHIFT (14U) -#define XCVR_PHY_PHY_FSK_MISC_MSK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_MSK_EN_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_MSK_EN_MASK) -#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_MASK (0xFF0000U) -#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_SHIFT (16U) -#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_MASK) -#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_MASK (0xF000000U) -#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_SHIFT (24U) -#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_MASK) -#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_MASK (0xF0000000U) -#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_SHIFT (28U) -/*! CLK_CTRL - * 0b0001..Gate off PHY clock when phy_en is not asserted. - * 0b0010..Gate off preamble detect clock when pd_enable is not asserted (internal signal). - * 0b0100..Gate off AA synchronizer clock when synchronizer is not in use. - * 0b1000..Gate off demodulator clock when demodulator is not in use. - */ -#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_MASK) -/*! @} */ - -/*! @name NTW_ADR_BSM - PHY BSM Network Address */ -/*! @{ */ -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK (0xFFFFFFFFU) -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT (0U) -#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT)) & XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK) -/*! @} */ - -/*! @name FSK_STAT - PHY Status */ -/*! @{ */ -#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_MASK (0x1U) -#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_SHIFT (0U) -#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_SHIFT)) & XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_MASK) -#define XCVR_PHY_FSK_STAT_AA_MATCHED_MASK (0x2U) -#define XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT (1U) -#define XCVR_PHY_FSK_STAT_AA_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCHED_MASK) -#define XCVR_PHY_FSK_STAT_AA_MATCH_MASK (0xF0U) -#define XCVR_PHY_FSK_STAT_AA_MATCH_SHIFT (4U) -#define XCVR_PHY_FSK_STAT_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCH_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCH_MASK) -#define XCVR_PHY_FSK_STAT_HAMM_DIST_MASK (0xF00U) -#define XCVR_PHY_FSK_STAT_HAMM_DIST_SHIFT (8U) -#define XCVR_PHY_FSK_STAT_HAMM_DIST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_HAMM_DIST_SHIFT)) & XCVR_PHY_FSK_STAT_HAMM_DIST_MASK) -#define XCVR_PHY_FSK_STAT_CFO_EST_MASK (0xFF0000U) -#define XCVR_PHY_FSK_STAT_CFO_EST_SHIFT (16U) -#define XCVR_PHY_FSK_STAT_CFO_EST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_CFO_EST_SHIFT)) & XCVR_PHY_FSK_STAT_CFO_EST_MASK) -#define XCVR_PHY_FSK_STAT_TOF_OFF_MASK (0xF000000U) -#define XCVR_PHY_FSK_STAT_TOF_OFF_SHIFT (24U) -#define XCVR_PHY_FSK_STAT_TOF_OFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_TOF_OFF_SHIFT)) & XCVR_PHY_FSK_STAT_TOF_OFF_MASK) -/*! @} */ - -/*! @name FSK_FAD_CTRL - PHY FAD control */ -/*! @{ */ -#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN_MASK (0x1U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN_SHIFT (0U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_EN_MASK) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_MASK (0x7F0U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_SHIFT (4U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_MASK) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_MASK (0x7F000U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_SHIFT (12U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_MASK) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_MASK (0xFF00000U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_SHIFT (20U) -#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_MASK) -#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_MASK (0xF0000000U) -#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_SHIFT (28U) -#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_PHY_Register_Masks */ - - -/* XCVR_PHY - Peripheral instance base addresses */ -/** Peripheral XCVR_PHY base address */ -#define XCVR_PHY_BASE (0x41030400u) -/** Peripheral XCVR_PHY base pointer */ -#define XCVR_PHY ((XCVR_PHY_Type *)XCVR_PHY_BASE) -/** Array initializer of XCVR_PHY peripheral base addresses */ -#define XCVR_PHY_BASE_ADDRS { XCVR_PHY_BASE } -/** Array initializer of XCVR_PHY peripheral base pointers */ -#define XCVR_PHY_BASE_PTRS { XCVR_PHY } - -/*! - * @} - */ /* end of group XCVR_PHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PKT_RAM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PKT_RAM_Peripheral_Access_Layer XCVR_PKT_RAM Peripheral Access Layer - * @{ - */ - -/** XCVR_PKT_RAM - Register Layout Typedef */ -typedef struct { - __IO uint16_t PACKET_RAM[1152]; /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x2 */ -} XCVR_PKT_RAM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PKT_RAM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PKT_RAM_Register_Masks XCVR_PKT_RAM Register Masks - * @{ - */ - -/*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */ -/*! @{ */ -#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE_MASK (0xFFU) -#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE_SHIFT (0U) -#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_LSBYTE_MASK) -#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE_MASK (0xFF00U) -#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE_SHIFT (8U) -#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_MSBYTE_MASK) -/*! @} */ - -/* The count of XCVR_PKT_RAM_PACKET_RAM */ -#define XCVR_PKT_RAM_PACKET_RAM_COUNT (1152U) - - -/*! - * @} - */ /* end of group XCVR_PKT_RAM_Register_Masks */ - - -/* XCVR_PKT_RAM - Peripheral instance base addresses */ -/** Peripheral XCVR_PKT_RAM base address */ -#define XCVR_PKT_RAM_BASE (0x41030700u) -/** Peripheral XCVR_PKT_RAM base pointer */ -#define XCVR_PKT_RAM ((XCVR_PKT_RAM_Type *)XCVR_PKT_RAM_BASE) -/** Array initializer of XCVR_PKT_RAM peripheral base addresses */ -#define XCVR_PKT_RAM_BASE_ADDRS { XCVR_PKT_RAM_BASE } -/** Array initializer of XCVR_PKT_RAM peripheral base pointers */ -#define XCVR_PKT_RAM_BASE_PTRS { XCVR_PKT_RAM } - -/*! - * @} - */ /* end of group XCVR_PKT_RAM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_PLL_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_PLL_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t HPM_BUMP; /**< PLL HPM Analog Bump Control, offset: 0x0 */ - __IO uint32_t MOD_CTRL; /**< PLL Modulation Control, offset: 0x4 */ - __IO uint32_t CHAN_MAP; /**< PLL Channel Mapping, offset: 0x8 */ - __IO uint32_t LOCK_DETECT; /**< PLL Lock Detect Control, offset: 0xC */ - __IO uint32_t HPM_CTRL; /**< PLL High Port Modulator Control, offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t HPM_SDM_RES; /**< PLL High Port Sigma Delta Results, offset: 0x20 */ - __IO uint32_t LPM_CTRL; /**< PLL Low Port Modulator Control, offset: 0x24 */ - __IO uint32_t LPM_SDM_CTRL1; /**< PLL Low Port Sigma Delta Control 1, offset: 0x28 */ - __IO uint32_t LPM_SDM_CTRL2; /**< PLL Low Port Sigma Delta Control 2, offset: 0x2C */ - __IO uint32_t LPM_SDM_CTRL3; /**< PLL Low Port Sigma Delta Control 3, offset: 0x30 */ - __I uint32_t LPM_SDM_RES1; /**< PLL Low Port Sigma Delta Result 1, offset: 0x34 */ - __I uint32_t LPM_SDM_RES2; /**< PLL Low Port Sigma Delta Result 2, offset: 0x38 */ - __IO uint32_t DELAY_MATCH; /**< PLL Delay Matching, offset: 0x3C */ - __IO uint32_t CTUNE_CTRL; /**< PLL Coarse Tune Control, offset: 0x40 */ - uint8_t RESERVED_1[16]; - __I uint32_t CTUNE_RES; /**< PLL Coarse Tune Results, offset: 0x54 */ -} XCVR_PLL_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_PLL_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks - * @{ - */ - -/*! @name HPM_BUMP - PLL HPM Analog Bump Control */ -/*! @{ */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK (0x7U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT (0U) -/*! HPM_VCM_TX - rfctrl_tx_dac_bump_vcm[2:0] during Transmission - * 0b000..432 mV - * 0b001..328 mV - * 0b010..456 mV - * 0b011..473 mV - * 0b100..488 mV - * 0b101..408 mV - * 0b110..392 mV - * 0b111..376 mV - */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK (0x70U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT (4U) -/*! HPM_VCM_CAL - rfctrl_tx_dac_bump_vcm[2:0] during Calibration - * 0b000..432 mV - * 0b001..328 mV - * 0b010..456 mV - * 0b011..473 mV - * 0b100..488 mV - * 0b101..408 mV - * 0b110..392 mV - * 0b111..376 mV - */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U) -/*! HPM_FDB_RES_TX - rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission - * 0b00..29 kohms - * 0b01..58 kohms(gain of 2) - * 0b10..13 kohms - * 0b11..23.7 kohms - */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U) -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U) -/*! HPM_FDB_RES_CAL - rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration - * 0b00..29 kohms - * 0b01..58 kohms(gain of 2) - * 0b10..13 kohms - * 0b11..23.7 kohms - */ -#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK) -/*! @} */ - -/*! @name MOD_CTRL - PLL Modulation Control */ -/*! @{ */ -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU) -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK) -/*! @} */ - -/*! @name CHAN_MAP - PLL Channel Mapping */ -/*! @{ */ -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK (0x7FU) -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT (0U) -#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_BOC_MASK (0x100U) -#define XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT (8U) -/*! BOC - BLE Channel Number Override - * 0b0..BLE channel number comes from the BLE Link Layer - * 0b1..BLE channel number comes from the CHANNEL_NUM register (BLE protocols 0 and 2) - */ -#define XCVR_PLL_DIG_CHAN_MAP_BOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BOC_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK (0x200U) -#define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT (9U) -/*! BMR - BLE MBAN Channel Remap - * 0b0..BLE channel 39 is mapped to BLE channel 39, 2.480 GHz - * 0b1..BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz - */ -#define XCVR_PLL_DIG_CHAN_MAP_BMR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK (0x400U) -#define XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT (10U) -/*! ZOC - 802.15.4 Channel Number Override - * 0b0..802.15.4 channel number comes from the 802.15.4 Link Layer. - * 0b1..802.15.4 channel number comes from the CHANNEL_NUM register (802.15.4 protocols 4 and 5) - */ -#define XCVR_PLL_DIG_CHAN_MAP_ZOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK (0x70000U) -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT (16U) -/*! HOP_TBL_CFG_OVRD - Hop Table Configuration Override - * 0b010..DFT_PATTERN[15:7] is signed offset to DFT_PATTERN[6:0] mapped channel number - * 0b011..DFT_PATTERN[15:1] is signed Numerator, DFT_PATTERN[0] is integer selection - */ -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK) -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK (0x80000U) -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT (19U) -#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK) -/*! @} */ - -/*! @name LOCK_DETECT - PLL Lock Detect Control */ -/*! @{ */ -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK (0x1U) -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT (0U) -#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK (0x2U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT (1U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK (0x4U) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT (2U) -#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK (0x8U) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT (3U) -#define XCVR_PLL_DIG_LOCK_DETECT_CSFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK (0x10U) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT (4U) -#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK (0x20U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT (5U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK (0x80U) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT (7U) -#define XCVR_PLL_DIG_LOCK_DETECT_TAFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U) -#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK (0x80000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT (19U) -/*! FTW_RX - RX Frequency Target Window time select - * 0b0..4 us - * 0b1..8 us - */ -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0x3F00000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (20U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK (0x8000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT (27U) -/*! FTW_TX - TX Frequency Target Window time select - * 0b0..4 us - * 0b1..8 us - */ -#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U) -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U) -/*! FREQ_COUNT_TIME - Frequency Meter Count Time - * 0b00..800 us - * 0b01..25 us - * 0b10..50 us - * 0b11..100 us - */ -#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK) -/*! @} */ - -/*! @name HPM_CTRL - PLL High Port Modulator Control */ -/*! @{ */ -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK (0x2000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT (13U) -#define XCVR_PLL_DIG_HPM_CTRL_HPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U) -/*! HPM_LFSR_SIZE - HPM LFSR Length - * 0b000..LFSR 9, tap mask 100010000 - * 0b001..LFSR 10, tap mask 1001000000 - * 0b010..LFSR 11, tap mask 11101000000 - * 0b011..LFSR 13, tap mask 1101100000000 - * 0b100..LFSR 15, tap mask 111010000000000 - * 0b101..LFSR 17, tap mask 11110000000000000 - * 0b110..Reserved - * 0b111..Reserved - */ -#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK (0x100000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT (20U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK (0x800000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT (23U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK (0x3000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT (24U) -/*! HPM_INTEGER_SCALE - High Port Modulation Integer Scale - * 0b00..No Scaling - * 0b01..Multiply by 2 - * 0b10..Divide by 2 - * 0b11..Reserved - */ -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U) -#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK) -/*! @} */ - -/*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */ -/*! @{ */ -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK (0x3FF0000U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U) -#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK) -/*! @} */ - -/*! @name LPM_CTRL - PLL Low Port Modulator Control */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x1FU) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x800U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (11U) -#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK (0x2000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT (13U) -#define XCVR_PLL_DIG_LPM_CTRL_LPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK (0x4000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT (14U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK (0xF0000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT (16U) -/*! LPM_DTH_SCL - LPM Dither Scale - * 0b0000..Reserved - * 0b0001..Reserved - * 0b0010..Reserved - * 0b0011..Reserved - * 0b0100..Reserved - * 0b0101..-128 to 96 - * 0b0110..-256 to 192 - * 0b0111..-512 to 384 - * 0b1000..-1024 to 768, this is the intended setting for normal operation. - * 0b1001..-2048 to 1536 - * 0b1010..-4096 to 3072 - * 0b1011..-8192 to 6144 - * 0b1100..Reserved - * 0b1101..Reserved - * 0b1110..Reserved - * 0b1111..Reserved - */ -#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK (0x400000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT (22U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK (0x800000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT (23U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK (0xF000000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT (24U) -/*! LPM_SCALE - LPM Scale Factor - * 0b0000..No Scaling - * 0b0001..Multiply by 2 - * 0b0010..Multiply by 4 - * 0b0011..Multiply by 8 - * 0b0100..Multiply by 16 - * 0b0101..Multiply by 32 - * 0b0110..Multiply by 64 - * 0b0111..Multiply by 128 - * 0b1000..Multiply by 256, this is the intended setting for normal operation. - * 0b1001..Multiply by 512 - * 0b1010..Multiply by 1024 - * 0b1011..Multiply by 2048 - * 0b1100..Reserved - * 0b1101..Reserved - * 0b1110..Reserved - * 0b1111..Reserved - */ -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U) -#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK) -/*! @} */ - -/*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) -/*! @} */ - -/*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK) -/*! @} */ - -/*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK) -/*! @} */ - -/*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK) -/*! @} */ - -/*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */ -/*! @{ */ -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU) -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK) -/*! @} */ - -/*! @name DELAY_MATCH - PLL Delay Matching */ -/*! @{ */ -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU) -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U) -#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U) -#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK) -/*! @} */ - -/*! @name CTUNE_CTRL - PLL Coarse Tune Control */ -/*! @{ */ -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0x7F000000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (24U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U) -#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK) -/*! @} */ - -/*! @name CTUNE_RES - PLL Coarse Tune Results */ -/*! @{ */ -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0x7FU) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0xFF00U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (8U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0xFFF0000U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (16U) -#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_PLL_DIG_Register_Masks */ - - -/* XCVR_PLL_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_PLL_DIG base address */ -#define XCVR_PLL_DIG_BASE (0x41030224u) -/** Peripheral XCVR_PLL_DIG base pointer */ -#define XCVR_PLL_DIG ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE) -/** Array initializer of XCVR_PLL_DIG peripheral base addresses */ -#define XCVR_PLL_DIG_BASE_ADDRS { XCVR_PLL_DIG_BASE } -/** Array initializer of XCVR_PLL_DIG peripheral base pointers */ -#define XCVR_PLL_DIG_BASE_PTRS { XCVR_PLL_DIG } - -/*! - * @} - */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_RX_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_RX_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t RX_DIG_CTRL; /**< RX Digital Control, offset: 0x0 */ - __IO uint32_t AGC_CTRL_0; /**< AGC Control 0, offset: 0x4 */ - __IO uint32_t AGC_CTRL_1; /**< AGC Control 1, offset: 0x8 */ - __IO uint32_t AGC_CTRL_2; /**< AGC Control 2, offset: 0xC */ - __IO uint32_t AGC_CTRL_3; /**< AGC Control 3, offset: 0x10 */ - __I uint32_t AGC_STAT; /**< AGC Status, offset: 0x14 */ - __IO uint32_t RSSI_CTRL_0; /**< RSSI Control 0, offset: 0x18 */ - __IO uint32_t RSSI_CTRL_1; /**< RSSI Control 1, offset: 0x1C */ - uint8_t RESERVED_0[4]; - __IO uint32_t DCOC_CTRL_0; /**< DCOC Control 0, offset: 0x24 */ - __IO uint32_t DCOC_CTRL_1; /**< DCOC Control 1, offset: 0x28 */ - __IO uint32_t DCOC_DAC_INIT; /**< DCOC DAC Initialization, offset: 0x2C */ - __IO uint32_t DCOC_DIG_MAN; /**< DCOC Digital Correction Manual Override, offset: 0x30 */ - __IO uint32_t DCOC_CAL_GAIN; /**< DCOC Calibration Gain, offset: 0x34 */ - __I uint32_t DCOC_STAT; /**< DCOC Status, offset: 0x38 */ - __I uint32_t DCOC_DC_EST; /**< DCOC DC Estimate, offset: 0x3C */ - __IO uint32_t DCOC_CAL_RCP; /**< DCOC Calibration Reciprocals, offset: 0x40 */ - __IO uint32_t DCOC_CTRL_2; /**< DCOC Control 2, offset: 0x44 */ - __IO uint32_t IQMC_CTRL; /**< IQMC Control, offset: 0x48 */ - __IO uint32_t IQMC_CAL; /**< IQMC Calibration, offset: 0x4C */ - __IO uint32_t LNA_GAIN_VAL_3_0; /**< LNA_GAIN Step Values 3..0, offset: 0x50 */ - __IO uint32_t LNA_GAIN_VAL_7_4; /**< LNA_GAIN Step Values 7..4, offset: 0x54 */ - __IO uint32_t LNA_GAIN_VAL_8; /**< LNA_GAIN Step Values 8, offset: 0x58 */ - __IO uint32_t BBA_RES_TUNE_VAL_7_0; /**< BBA Resistor Tune Values 7..0, offset: 0x5C */ - __IO uint32_t BBA_RES_TUNE_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x60 */ - __IO uint32_t LNA_GAIN_LIN_VAL_2_0; /**< LNA Linear Gain Values 2..0, offset: 0x64 */ - __IO uint32_t LNA_GAIN_LIN_VAL_5_3; /**< LNA Linear Gain Values 5..3, offset: 0x68 */ - __IO uint32_t LNA_GAIN_LIN_VAL_8_6; /**< LNA Linear Gain Values 8..6, offset: 0x6C */ - __IO uint32_t LNA_GAIN_LIN_VAL_9; /**< LNA Linear Gain Values 9, offset: 0x70 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_3_0; /**< BBA Resistor Tune Values 3..0, offset: 0x74 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_7_4; /**< BBA Resistor Tune Values 7..4, offset: 0x78 */ - __IO uint32_t BBA_RES_TUNE_LIN_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x7C */ - __IO uint32_t AGC_GAIN_TBL_03_00; /**< AGC Gain Tables Step 03..00, offset: 0x80 */ - __IO uint32_t AGC_GAIN_TBL_07_04; /**< AGC Gain Tables Step 07..04, offset: 0x84 */ - __IO uint32_t AGC_GAIN_TBL_11_08; /**< AGC Gain Tables Step 11..08, offset: 0x88 */ - __IO uint32_t AGC_GAIN_TBL_15_12; /**< AGC Gain Tables Step 15..12, offset: 0x8C */ - __IO uint32_t AGC_GAIN_TBL_19_16; /**< AGC Gain Tables Step 19..16, offset: 0x90 */ - __IO uint32_t AGC_GAIN_TBL_23_20; /**< AGC Gain Tables Step 23..20, offset: 0x94 */ - __IO uint32_t AGC_GAIN_TBL_26_24; /**< AGC Gain Tables Step 26..24, offset: 0x98 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DCOC_OFFSET[27]; /**< DCOC Offset, array offset: 0xA0, array step: 0x4 */ - __IO uint32_t DCOC_BBA_STEP; /**< DCOC BBA DAC Step, offset: 0x10C */ - __IO uint32_t DCOC_TZA_STEP_0; /**< DCOC TZA DAC Step 0, offset: 0x110 */ - __IO uint32_t DCOC_TZA_STEP_1; /**< DCOC TZA DAC Step 1, offset: 0x114 */ - __IO uint32_t DCOC_TZA_STEP_2; /**< DCOC TZA DAC Step 2, offset: 0x118 */ - __IO uint32_t DCOC_TZA_STEP_3; /**< DCOC TZA DAC Step 3, offset: 0x11C */ - __IO uint32_t DCOC_TZA_STEP_4; /**< DCOC TZA DAC Step 4, offset: 0x120 */ - __IO uint32_t DCOC_TZA_STEP_5; /**< DCOC TZA DAC Step 5, offset: 0x124 */ - __IO uint32_t DCOC_TZA_STEP_6; /**< DCOC TZA DAC Step 6, offset: 0x128 */ - __IO uint32_t DCOC_TZA_STEP_7; /**< DCOC TZA DAC Step 7, offset: 0x12C */ - __IO uint32_t DCOC_TZA_STEP_8; /**< DCOC TZA DAC Step 5, offset: 0x130 */ - __IO uint32_t DCOC_TZA_STEP_9; /**< DCOC TZA DAC Step 9, offset: 0x134 */ - __IO uint32_t DCOC_TZA_STEP_10; /**< DCOC TZA DAC Step 10, offset: 0x138 */ - uint8_t RESERVED_2[36]; - __IO uint32_t DCOC_CAL_FAIL_TH; /**< DCOC Calibration Fail Thresholds, offset: 0x160 */ - __IO uint32_t DCOC_CAL_PASS_TH; /**< DCOC Calibration Pass Thresholds, offset: 0x164 */ - __I uint32_t DCOC_CAL_ALPHA; /**< DCOC Calibration Alpha, offset: 0x168 */ - __I uint32_t DCOC_CAL_BETA_Q; /**< DCOC Calibration Beta Q, offset: 0x16C */ - __I uint32_t DCOC_CAL_BETA_I; /**< DCOC Calibration Beta I, offset: 0x170 */ - __I uint32_t DCOC_CAL_GAMMA; /**< DCOC Calibration Gamma, offset: 0x174 */ - __IO uint32_t DCOC_CAL_IIR; /**< DCOC Calibration IIR, offset: 0x178 */ - uint8_t RESERVED_3[4]; - __I uint32_t DCOC_CAL[3]; /**< DCOC Calibration Result, array offset: 0x180, array step: 0x4 */ - uint8_t RESERVED_4[4]; - __IO uint32_t CCA_ED_LQI_CTRL_0; /**< RX_DIG CCA ED LQI Control Register 0, offset: 0x190 */ - __IO uint32_t CCA_ED_LQI_CTRL_1; /**< RX_DIG CCA ED LQI Control Register 1, offset: 0x194 */ - __I uint32_t CCA_ED_LQI_STAT_0; /**< RX_DIG CCA ED LQI Status Register 0, offset: 0x198 */ - uint8_t RESERVED_5[4]; - __IO uint32_t RX_CHF_COEF_0; /**< Receive Channel Filter Coefficient 0, offset: 0x1A0 */ - __IO uint32_t RX_CHF_COEF_1; /**< Receive Channel Filter Coefficient 1, offset: 0x1A4 */ - __IO uint32_t RX_CHF_COEF_2; /**< Receive Channel Filter Coefficient 2, offset: 0x1A8 */ - __IO uint32_t RX_CHF_COEF_3; /**< Receive Channel Filter Coefficient 3, offset: 0x1AC */ - __IO uint32_t RX_CHF_COEF_4; /**< Receive Channel Filter Coefficient 4, offset: 0x1B0 */ - __IO uint32_t RX_CHF_COEF_5; /**< Receive Channel Filter Coefficient 5, offset: 0x1B4 */ - __IO uint32_t RX_CHF_COEF_6; /**< Receive Channel Filter Coefficient 6, offset: 0x1B8 */ - __IO uint32_t RX_CHF_COEF_7; /**< Receive Channel Filter Coefficient 7, offset: 0x1BC */ - __IO uint32_t RX_CHF_COEF_8; /**< Receive Channel Filter Coefficient 8, offset: 0x1C0 */ - __IO uint32_t RX_CHF_COEF_9; /**< Receive Channel Filter Coefficient 9, offset: 0x1C4 */ - __IO uint32_t RX_CHF_COEF_10; /**< Receive Channel Filter Coefficient 10, offset: 0x1C8 */ - __IO uint32_t RX_CHF_COEF_11; /**< Receive Channel Filter Coefficient 11, offset: 0x1CC */ - __IO uint32_t AGC_MAN_AGC_IDX; /**< AGC Manual AGC Index, offset: 0x1D0 */ - __IO uint32_t DC_RESID_CTRL; /**< DC Residual Control, offset: 0x1D4 */ - __I uint32_t DC_RESID_EST; /**< DC Residual Estimate, offset: 0x1D8 */ - __IO uint32_t RX_RCCAL_CTRL0; /**< RX RC Calibration Control0, offset: 0x1DC */ - __IO uint32_t RX_RCCAL_CTRL1; /**< RX RC Calibration Control1, offset: 0x1E0 */ - __I uint32_t RX_RCCAL_STAT; /**< RX RC Calibration Status, offset: 0x1E4 */ - __IO uint32_t AUXPLL_FCAL_CTRL; /**< Aux PLL Frequency Calibration Control, offset: 0x1E8 */ - __I uint32_t AUXPLL_FCAL_CNT6; /**< Aux PLL Frequency Calibration Count 6, offset: 0x1EC */ - __I uint32_t AUXPLL_FCAL_CNT5_4; /**< Aux PLL Frequency Calibration Count 5 and 4, offset: 0x1F0 */ - __I uint32_t AUXPLL_FCAL_CNT3_2; /**< Aux PLL Frequency Calibration Count 3 and 2, offset: 0x1F4 */ - __I uint32_t AUXPLL_FCAL_CNT1_0; /**< Aux PLL Frequency Calibration Count 1 and 0, offset: 0x1F8 */ -} XCVR_RX_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_RX_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks - * @{ - */ - -/*! @name RX_DIG_CTRL - RX Digital Control */ -/*! @{ */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK (0x1U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT (0U) -/*! RX_ADC_NEGEDGE - Receive ADC Negative Edge Selection - * 0b0..Register ADC data on positive edge of clock - * 0b1..Register ADC data on negative edge of clock - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK (0x2U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT (1U) -/*! RX_CH_FILT_BYPASS - Receive Channel Filter Bypass - * 0b0..Channel filter is enabled. - * 0b1..Disable and bypass channel filter. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK (0x8U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT (3U) -/*! RX_ADC_POL - Receive ADC Polarity - * 0b0..ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default) - * 0b1..ADC output of 1'b0 maps to +1, 1'b1 maps to -1 - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK (0xF0U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT (4U) -/*! RX_DEC_FILT_OSR - Decimation Filter Oversampling - * 0b0000..OSR 4 - * 0b0001..OSR 8 - * 0b0010..OSR 16 - * 0b0100..OSR 32 - * 0b1000..OSR 64 - * 0b0011..OSR 6 - * 0b0101..OSR 12 - * 0b0110..OSR 24 - * 0b0111..OSR 48 - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK (0x100U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT (8U) -/*! RX_FSK_ZB_SEL - FSK / 802.15.4 demodulator select - * 0b0..FSK demodulator. - * 0b1..802.15.4 demodulator. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_MASK (0x200U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_SHIFT (9U) -/*! RX_NORM_SUPP_EN - Normalizer Suppression Enable - * 0b0..Normalizer suppression is disabled. - * 0b1..Normalizer suppression is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK (0x400U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT (10U) -/*! RX_RSSI_EN - RSSI Measurement Enable - * 0b0..RSSI measurement is disabled. - * 0b1..RSSI measurement is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK (0x800U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT (11U) -/*! RX_AGC_EN - AGC Global Enable - * 0b0..AGC is disabled. - * 0b1..AGC is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK (0x1000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT (12U) -/*! RX_DCOC_EN - DCOC Enable - * 0b0..DCOC is disabled. - * 0b1..DCOC is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK (0x2000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT (13U) -/*! RX_DCOC_CAL_EN - DCOC Calibration Enable - * 0b0..DCOC calibration is disabled. - * 0b1..DCOC calibration is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK (0x4000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT (14U) -/*! RX_IQ_SWAP - RX IQ Swap - * 0b0..IQ swap is disabled. - * 0b1..IQ swap is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK (0x8000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT (15U) -/*! RX_DC_RESID_EN - DC Residual Enable - * 0b0..DC Residual block is disabled. - * 0b1..DC Residual block is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK (0x10000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT (16U) -/*! RX_SRC_EN - RX Sample Rate Converter Enable - * 0b0..SRC is disabled. - * 0b1..SRC is enabled. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK (0x20000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT (17U) -/*! RX_SRC_RATE - RX Sample Rate Converter Rate Selections - * 0b0..SRC is configured for a First Order Hold rate of 8/13. - * 0b1..SRC is configured for a Zero Order Hold rate of 12/13. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK (0x40000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT (18U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_MASK (0x80000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_SHIFT (19U) -/*! RX_DEC_FILT_LP - RX Decimator Low Power - * 0b0..Decimator operates in normal mode. - * 0b1..Decimator operates in low power mode. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT (20U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT (25U) -/*! RX_DEC_FILT_HZD_CORR_DIS - Decimator filter hazard correction disable - * 0b0..Hazard correction is enabled - * 0b1..Hazard correction is disabled - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_MASK (0x4000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_SHIFT (26U) -/*! RX_CH_FILT_LEN - RX Channel Filter Length - * 0b0..Channel filter length is 24. - * 0b1..Channel filter length is 16. Only RX_CHF_COEF_4 - RX_CHF_COEF_11 are used in this mode. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_MASK (0x8000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_SHIFT (27U) -/*! RX_NORM_SUPP_TH - Normalizer Suppression Threshold - * 0b0..Normalizer suppression threshold is 12'd7. - * 0b1..Normalizer suppression threshold is 12'd15. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK (0x10000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT (28U) -/*! RX_DEC_FILT_HAZARD - Decimator output, hazard condition detected - * 0b0..A hazard condition has not been detected - * 0b1..A hazard condition has been detected - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK (0x20000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT (29U) -/*! RX_RSSI_FILT_HAZARD - Decimator output for RSSI, hazard condition detected - * 0b0..A hazard condition has not been detected - * 0b1..A hazard condition has been detected - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK (0x40000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT (30U) -/*! RX_DEC_FILT_SAT_I - Decimator output, saturation detected for I channel - * 0b0..A saturation condition has not occurred. - * 0b1..A saturation condition has occurred. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK (0x80000000U) -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT (31U) -/*! RX_DEC_FILT_SAT_Q - Decimator output, saturation detected for Q channel - * 0b0..A saturation condition has not occurred. - * 0b1..A saturation condition has occurred. - */ -#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK) -/*! @} */ - -/*! @name AGC_CTRL_0 - AGC Control 0 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK (0x1U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK (0x6U) -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT (1U) -/*! SLOW_AGC_SRC - Slow AGC Source Selection - * 0b00..Access Address match (for active protocol) - * 0b01..Preamble Detect (for active protocol) - * 0b10..Fast AGC expire timer - * 0b11..Reserved - */ -#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK (0x8U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT (3U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_MASK (0x30U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_SHIFT (4U) -/*! AGC_FREEZE_SRC - AGC Freeze Source Selection - * 0b00..Access Address match (for active protocol) - * 0b01..Preamble Detect (for active protocol) - * 0b10..PD confirmation / Access Address match (for active protocol) - */ -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK (0x40U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT (6U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK (0x80U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT (7U) -/*! AGC_UP_SRC - AGC Up Source - * 0b0..PDET LO - * 0b1..RSSI - */ -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT (8U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT (12U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK (0xFF0000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK (0xFF000000U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK) -/*! @} */ - -/*! @name AGC_CTRL_1 - AGC Control 1 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_MASK (0xFU) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_SHIFT (4U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT (12U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK (0x100000U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT (20U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK (0x200000U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT (21U) -#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK (0x400000U) -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT (22U) -/*! PRESLOW_EN - Pre-slow Enable - * 0b0..Pre-slow is disabled. - * 0b1..Pre-slow is enabled. - */ -#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_MASK (0x800000U) -#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_SHIFT (23U) -/*! PDET_HI_SEL_HOLD - AGC HOLD hysteresis - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_MASK) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK (0xFF000000U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK) -/*! @} */ - -/*! @name AGC_CTRL_2 - AGC Control 2 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK (0x1U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK (0x2U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT (1U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK (0x4U) -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT (2U) -/*! MAN_PDET_RST - MAN PDET Reset - * 0b0..The peak detector reset signals are controlled automatically by the AGC. - * 0b1..The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals. - */ -#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK (0xFF0U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT (4U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK (0x7000U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT (12U) -/*! BBA_PDET_SEL_LO - BBA PDET Threshold Low - * 0b000..0.600V - * 0b001..0.615V - * 0b010..0.630V - * 0b011..0.645V - * 0b100..0.660V - * 0b101..0.675V - * 0b110..0.690V - * 0b111..0.705V - */ -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK (0x38000U) -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT (15U) -/*! BBA_PDET_SEL_HI - BBA PDET Threshold High - * 0b000..0.600V - * 0b001..0.795V - * 0b010..0.900V - * 0b011..0.945V - * 0b100..1.005V - * 0b101..1.050V - * 0b110..1.095V - * 0b111..1.155V - */ -#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK (0x1C0000U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT (18U) -/*! TZA_PDET_SEL_LO - TZA PDET Threshold Low - * 0b000..0.600V - * 0b001..0.615V - * 0b010..0.630V - * 0b011..0.645V - * 0b100..0.660V - * 0b101..0.675V - * 0b110..0.690V - * 0b111..0.705V - */ -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK (0xE00000U) -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT (21U) -/*! TZA_PDET_SEL_HI - TZA PDET Threshold High - * 0b000..0.600V - * 0b001..0.645V - * 0b010..0.705V - * 0b011..0.750V - * 0b100..0.795V - * 0b101..0.855V - * 0b110..0.900V - * 0b111..0.945V - */ -#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK (0x3F000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT (24U) -#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK (0x40000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT (30U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK (0x80000000U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT (31U) -#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK) -/*! @} */ - -/*! @name AGC_CTRL_3 - AGC Control 3 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK (0x1FFFU) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT (0U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK (0xE000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT (13U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK (0x7F0000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT (16U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK (0xF800000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT (23U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT (28U) -#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK) -/*! @} */ - -/*! @name AGC_STAT - AGC Status */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK (0x1U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT (0U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK (0x2U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT (1U) -#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK (0x4U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT (2U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK (0x8U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT (3U) -#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK (0x1F0U) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT (4U) -#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT)) & XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK) -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK (0x200U) -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT (9U) -/*! AGC_FROZEN - AGC Frozen Status - * 0b0..AGC is not frozen. - * 0b1..AGC is frozen. - */ -#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK) -#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_MASK (0x7C00U) -#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_SHIFT (10U) -#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_MASK) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK (0xFF0000U) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT (16U) -#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT)) & XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK) -/*! @} */ - -/*! @name RSSI_CTRL_0 - RSSI Control 0 */ -/*! @{ */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK (0x1U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT (0U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK (0x6U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT (1U) -/*! RSSI_HOLD_SRC - RSSI Hold Source Selection - * 0b00..Access Address match - * 0b01..Preamble Detect - * 0b10..Reserved - * 0b11..802.15.4 LQI done (1=freeze, 0=run AGC) - */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK (0x8U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT (3U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK (0x60U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT (5U) -/*! RSSI_IIR_CW_WEIGHT - RSSI IIR CW Weighting - * 0b00..Bypass - * 0b01..1/8 - * 0b10..1/16 - * 0b11..1/32 - */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_MASK (0x380U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_SHIFT (7U) -/*! RSSI_N_WINDOW_NB - RSSI N Window Average Narrowband - * 0b000..No averaging - * 0b001..Averaging window length is 2 samples - * 0b010..Averaging window length is 4 samples - * 0b011..Averaging window length is 8 samples - * 0b100..Averaging window length is 16 samples - * 0b101..Averaging window length is 32 samples - */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK (0xFC00U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT (10U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_MASK (0x70000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_SHIFT (16U) -/*! RSSI_IIR_WT_NB - RSSI IIR Weighting Narrowband - * 0b000..Bypass - * 0b001..1/2 - * 0b010..1/4 - * 0b011..1/8 - * 0b100..1/16 - * 0b101..1/32 - */ -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK (0x700000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT (20U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK (0xFF000000U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT (24U) -#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) -/*! @} */ - -/*! @name RSSI_CTRL_1 - RSSI Control 1 */ -/*! @{ */ -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_MASK (0x7U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_SHIFT (0U) -/*! RSSI_N_WINDOW_WB - RSSI N Window Average Wideband - * 0b000..No averaging - * 0b001..Averaging window length is 2 samples - * 0b010..Averaging window length is 4 samples - * 0b011..Averaging window length is 8 samples - * 0b100..Averaging window length is 16 samples - * 0b101..Averaging window length is 32 samples - */ -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_MASK (0x70U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_SHIFT (4U) -/*! RSSI_IIR_WT_WB - RSSI IIR Weighting Wideband - * 0b000..Bypass - * 0b001..1/2 - * 0b010..1/4 - * 0b011..1/8 - * 0b100..1/16 - * 0b101..1/32 - */ -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_MASK) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK (0xFF000000U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT (24U) -#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) -/*! @} */ - -/*! @name DCOC_CTRL_0 - DCOC Control 0 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK (0x1U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT (0U) -/*! DCOC_MIDPWR_TRK_DIS - DCOC Mid Power Tracking Disable - * 0b0..Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX. - * 0b1..Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK (0x2U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT (1U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK (0x4U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT (2U) -/*! DCOC_TRK_EST_OVR - Override for the DCOC tracking estimator - * 0b0..The tracking estimator is enabled only as needed by the corrector - * 0b1..The tracking estimator remains enabled whenever the DCOC is active - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK (0x8U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT (3U) -/*! DCOC_CORRECT_SRC - DCOC Corrector Source - * 0b0..If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset. - * 0b1..If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK (0x10U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT (4U) -/*! DCOC_CORRECT_EN - DCOC Correction Enable - * 0b0..Correction disabled. The DCOC will not correct the DC offset. - * 0b1..Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK (0x20U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT (5U) -/*! TRACK_FROM_ZERO - Track from Zero - * 0b0..Track from current I/Q sample. - * 0b1..Track from zero. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK (0x40U) -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT (6U) -/*! BBA_CORR_POL - BBA Correction Polarity - * 0b0..Normal polarity. - * 0b1..Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK (0x80U) -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT (7U) -/*! TZA_CORR_POL - TZA Correction Polarity - * 0b0..Normal polarity. - * 0b1..Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK (0x1F00U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT (8U) -/*! DCOC_CAL_DURATION - DCOC Calibration Duration - * 0b00000..Reserved - * 0b00001-0b11111..For a 32MHz reference clock, this is the calibration duration in microseconds; for other reference clock frequencies, the delay is scaled accordingly. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_MASK (0x8000U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_SHIFT (15U) -/*! DCOC_CAL_CHECK_EN - DCOC Calibration Check Enable - * 0b0..Calibration checking disabled. The DCOC_OFFSET_n registers are always updated during calibration. - * 0b1..Calibration checking enabled. The DCOC_OFFSET_n registers are updated conditionally depending on the outcome of the pass/fail threshold checks performed on the alpha-hat and beta-hat estimates during calibration. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK (0x1F0000U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT (16U) -/*! DCOC_CORR_DLY - DCOC Correction Delay - * 0b00000..Reserved - * 0b00001-0b11111..For a 32MHz reference clock, this is the wait time in microseconds; for other reference clock frequencies, the delay is scaled accordingly. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK (0x7F000000U) -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT (24U) -/*! DCOC_CORR_HOLD_TIME - DCOC Correction Hold Time - * 0b0000000..Reserved - * 0b0000001-0b1111110..For a 32MHz reference clock, this is the delay in microseconds; for other reference clock frequencies, the delay is scaled accordingly. - * 0b1111111..The DC correction is not frozen. - */ -#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK) -/*! @} */ - -/*! @name DCOC_CTRL_1 - DCOC Control 1 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK (0x3U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT (0U) -/*! DCOC_SIGN_SCALE_IDX - DCOC Sign Scaling - * 0b00..1/8 - * 0b01..1/16 - * 0b10..1/32 - * 0b11..1/64 - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK (0x1CU) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT (2U) -/*! DCOC_ALPHAC_SCALE_IDX - DCOC Alpha-C Scaling - * 0b000..1/2 - * 0b001..1/4 - * 0b010..1/8 - * 0b011..1/16 - * 0b100..1/32 - * 0b101..1/64 - * 0b110..Reserved - * 0b111..Reserved - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK (0xE0U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT (5U) -/*! DCOC_ALPHA_RADIUS_IDX - Alpha-R Scaling - * 0b000..1 - * 0b001..1/2 - * 0b010..1/4 - * 0b011..1/8 - * 0b100..1/16 - * 0b101..1/32 - * 0b110..1/64 - * 0b111..Reserved - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK (0x7000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT (12U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK (0x30000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT (16U) -/*! DCOC_SIGN_SCALE_GS_IDX - DCOC Sign Scaling for Gearshift - * 0b00..1/8 - * 0b01..1/16 - * 0b10..1/32 - * 0b11..1/64 - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK (0x1C0000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT (18U) -/*! DCOC_ALPHAC_SCALE_GS_IDX - DCOC Alpha-C Scaling for Gearshift - * 0b000..1/2 - * 0b001..1/4 - * 0b010..1/8 - * 0b011..1/16 - * 0b100..1/32 - * 0b101..1/64 - * 0b110..Reserved - * 0b111..Reserved - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK (0xE00000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT (21U) -/*! DCOC_ALPHA_RADIUS_GS_IDX - Alpha-R Scaling for Gearshift - * 0b000..1 - * 0b001..1/2 - * 0b010..1/4 - * 0b011..1/8 - * 0b100..1/16 - * 0b101..1/32 - * 0b110..1/64 - * 0b111..Reserved - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK (0x1F000000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_MASK (0x80000000U) -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_SHIFT (31U) -/*! DCOC_TRK_MIN_AGC_IDX_CFG - DCOC_TRK_MIN_AGC_IDX Configuration - * 0b0..Tracking is disabled when the AGC index is less than DCOC_TRK_MIN_AGC_IDX - * 0b1..Tracking is enabled when AGC index is less than DCOC_TRK_MIN_AGC_IDX, but DCOC_CORR_DLY_ALT and DCOC_CORR_HOLD_TIME_ALT are used instead of DCOC_CORR_DLY and DCOC_CORR_HOLD_TIME - */ -#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_MASK) -/*! @} */ - -/*! @name DCOC_DAC_INIT - DCOC DAC Initialization */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK) -/*! @} */ - -/*! @name DCOC_DIG_MAN - DCOC Digital Correction Manual Override */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK) -/*! @} */ - -/*! @name DCOC_CAL_GAIN - DCOC Calibration Gain */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK (0xF00U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK (0xF000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT (12U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK (0xF0000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK (0xF00000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT (20U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK (0xF000000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK (0xF0000000U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT (28U) -#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK) -/*! @} */ - -/*! @name DCOC_STAT - DCOC Status */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK) -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_MASK (0x80U) -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_SHIFT (7U) -/*! DCOC_CAL_GTWSR - DCOC calibration Good Table Written Since Reset - * 0b0..A Passing calibration result has not occurred since the last radio reset. - * 0b1..A Passing calibration result has occurred since the last radio reset. - */ -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_MASK) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK) -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_MASK (0xC000U) -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_SHIFT (14U) -/*! DCOC_CAL_RESULT - DCOC_CAL_RESULT - * 0b00..Calibration checks failed. DCOC_OFFSET_n tables not updated. - * 0b01..Calibration checks neither passed nor failed, DCOC_OFFSET_n tables not updated. - * 0b10..Calibration checks neither passed nor failed, DCOC_OFFSET_n tables updated since no previous Pass condition has occurred since the last radio reset. - * 0b11..Calibration checks passed. DCOC_OFFSET_n tables updated - */ -#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_MASK) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK) -/*! @} */ - -/*! @name DCOC_DC_EST - DCOC DC Estimate */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) -/*! @} */ - -/*! @name DCOC_CAL_RCP - DCOC Calibration Reciprocals */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK (0x7FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK) -/*! @} */ - -/*! @name DCOC_CTRL_2 - DCOC Control 2 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_MASK (0x1F0000U) -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_SHIFT (16U) -/*! DCOC_CORR_DLY_ALT - DCOC Correction Delay Alternate - * 0b00000..Reserved - * 0b00001-0b11111..For a 32MHz reference clock, this is the wait time in microseconds; for other reference clock frequencies, the delay is scaled accordingly. - */ -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_MASK) -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_MASK (0x7F000000U) -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_SHIFT (24U) -/*! DCOC_CORR_HOLD_TIME_ALT - DCOC Correction Hold Time Alternate - * 0b0000000..Reserved - * 0b0000001-0b1111110..For a 32MHz reference clock, this is the delay in microseconds; for other reference clock frequencies, the delay is scaled accordingly. - * 0b1111111..The DC correction is not frozen. - */ -#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_MASK) -/*! @} */ - -/*! @name IQMC_CTRL - IQMC Control */ -/*! @{ */ -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK (0x1U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT (0U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK (0xFF00U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT (8U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT (16U) -#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK) -/*! @} */ - -/*! @name IQMC_CAL - IQMC Calibration */ -/*! @{ */ -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK (0x7FFU) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT (0U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK (0xFFF0000U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT (16U) -#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK) -/*! @} */ - -/*! @name LNA_GAIN_VAL_3_0 - LNA_GAIN Step Values 3..0 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK (0xFF0000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT (16U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK (0xFF000000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT (24U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK) -/*! @} */ - -/*! @name LNA_GAIN_VAL_7_4 - LNA_GAIN Step Values 7..4 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK (0xFF0000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT (16U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK (0xFF000000U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT (24U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK) -/*! @} */ - -/*! @name LNA_GAIN_VAL_8 - LNA_GAIN Step Values 8 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK (0xFFU) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK (0xFF00U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT (8U) -#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK) -/*! @} */ - -/*! @name BBA_RES_TUNE_VAL_7_0 - BBA Resistor Tune Values 7..0 */ -/*! @{ */ -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK (0xFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK (0xF0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT (4U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK (0xF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK (0xF000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT (12U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK (0xF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK (0xF00000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT (20U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK (0xF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK (0xF0000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT (28U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK) -/*! @} */ - -/*! @name BBA_RES_TUNE_VAL_10_8 - BBA Resistor Tune Values 10..8 */ -/*! @{ */ -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK (0xFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK (0xF0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT (4U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK (0xF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK) -/*! @} */ - -/*! @name LNA_GAIN_LIN_VAL_2_0 - LNA Linear Gain Values 2..0 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK) -/*! @} */ - -/*! @name LNA_GAIN_LIN_VAL_5_3 - LNA Linear Gain Values 5..3 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK) -/*! @} */ - -/*! @name LNA_GAIN_LIN_VAL_8_6 - LNA Linear Gain Values 8..6 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK (0xFFC00U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT (10U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK (0x3FF00000U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT (20U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK) -/*! @} */ - -/*! @name LNA_GAIN_LIN_VAL_9 - LNA Linear Gain Values 9 */ -/*! @{ */ -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK (0x3FFU) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT (0U) -#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK) -/*! @} */ - -/*! @name BBA_RES_TUNE_LIN_VAL_3_0 - BBA Resistor Tune Values 3..0 */ -/*! @{ */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK (0xFFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK (0xFF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK (0xFF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK (0xFF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK) -/*! @} */ - -/*! @name BBA_RES_TUNE_LIN_VAL_7_4 - BBA Resistor Tune Values 7..4 */ -/*! @{ */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK (0xFFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK (0xFF00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT (8U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK (0xFF0000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT (16U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK (0xFF000000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT (24U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK) -/*! @} */ - -/*! @name BBA_RES_TUNE_LIN_VAL_10_8 - BBA Resistor Tune Values 10..8 */ -/*! @{ */ -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK (0x3FFU) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT (0U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK (0xFFC00U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT (10U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK (0x3FF00000U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT (20U) -#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK (0xF000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT (24U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK (0xF0000000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT (28U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK) -/*! @} */ - -/*! @name AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK (0xFU) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT (0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK (0xF0U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT (4U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK (0xF00U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT (8U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK (0xF000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT (12U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK (0xF0000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT (16U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK (0xF00000U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT (20U) -#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK) -/*! @} */ - -/*! @name DCOC_OFFSET - DCOC Offset */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK (0x3FU) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK (0x3F00U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT (8U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK (0xFF0000U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK (0xFF000000U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT (24U) -#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK) -/*! @} */ - -/* The count of XCVR_RX_DIG_DCOC_OFFSET */ -#define XCVR_RX_DIG_DCOC_OFFSET_COUNT (27U) - -/*! @name DCOC_BBA_STEP - DCOC BBA DAC Step */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK (0x1FF0000U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_0 - DCOC TZA DAC Step 0 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_1 - DCOC TZA DAC Step 1 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_2 - DCOC TZA DAC Step 2 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_3 - DCOC TZA DAC Step 3 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_4 - DCOC TZA DAC Step 4 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_5 - DCOC TZA DAC Step 5 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_6 - DCOC TZA DAC Step 6 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_7 - DCOC TZA DAC Step 7 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_8 - DCOC TZA DAC Step 5 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_9 - DCOC TZA DAC Step 9 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK (0x3FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK) -/*! @} */ - -/*! @name DCOC_TZA_STEP_10 - DCOC TZA DAC Step 10 */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK (0x1FFFU) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK (0x3FFF0000U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK) -/*! @} */ - -/*! @name DCOC_CAL_FAIL_TH - DCOC Calibration Fail Thresholds */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_MASK) -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_MASK (0x3FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_MASK) -/*! @} */ - -/*! @name DCOC_CAL_PASS_TH - DCOC Calibration Pass Thresholds */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_MASK) -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_MASK (0x3FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_MASK) -/*! @} */ - -/*! @name DCOC_CAL_ALPHA - DCOC Calibration Alpha */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK (0x7FFU) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK (0x7FF0000U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK) -/*! @} */ - -/*! @name DCOC_CAL_BETA_Q - DCOC Calibration Beta Q */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK (0x1FFFFU) -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK) -/*! @} */ - -/*! @name DCOC_CAL_BETA_I - DCOC Calibration Beta I */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK (0x1FFFFU) -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK) -/*! @} */ - -/*! @name DCOC_CAL_GAMMA - DCOC Calibration Gamma */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK (0xFFFFU) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK (0xFFFF0000U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK) -/*! @} */ - -/*! @name DCOC_CAL_IIR - DCOC Calibration IIR */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK (0x3U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT (0U) -/*! DCOC_CAL_IIR1A_IDX - DCOC Calibration IIR 1A Index - * 0b00..1/1 - * 0b01..1/4 - * 0b10..1/8 - * 0b11..1/16 - */ -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK (0xCU) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT (2U) -/*! DCOC_CAL_IIR2A_IDX - DCOC Calibration IIR 2A Index - * 0b00..1/1 - * 0b01..1/4 - * 0b10..1/8 - * 0b11..1/16 - */ -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK (0x30U) -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT (4U) -/*! DCOC_CAL_IIR3A_IDX - DCOC Calibration IIR 3A Index - * 0b00..1/4 - * 0b01..1/8 - * 0b10..1/16 - * 0b11..1/32 - */ -#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK) -/*! @} */ - -/*! @name DCOC_CAL - DCOC Calibration Result */ -/*! @{ */ -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK (0xFFFU) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT (0U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK (0xFFF0000U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT (16U) -#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK) -/*! @} */ - -/* The count of XCVR_RX_DIG_DCOC_CAL */ -#define XCVR_RX_DIG_DCOC_CAL_COUNT (3U) - -/*! @name CCA_ED_LQI_CTRL_0 - RX_DIG CCA ED LQI Control Register 0 */ -/*! @{ */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK (0xFFU) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK (0xFF00U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT (8U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK (0xFF0000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT (16U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK (0x3F000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT (24U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK) -/*! @} */ - -/*! @name CCA_ED_LQI_CTRL_1 - RX_DIG CCA ED LQI Control Register 1 */ -/*! @{ */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK (0x3FU) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK (0x1C0U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT (6U) -/*! RSSI_NOISE_AVG_FACTOR - RSSI Noise Averaging Factor - * 0b000..1 - * 0b001..64 - * 0b010..70 - * 0b011..128 - * 0b100..139 - * 0b101..256 - * 0b110..277 - * 0b111..512 - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK (0xE00U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT (9U) -/*! LQI_RSSI_WEIGHT - LQI RSSI Weight - * 0b000..2.0 - * 0b001..2.125 - * 0b010..2.25 - * 0b011..2.375 - * 0b100..2.5 - * 0b101..2.625 - * 0b110..2.75 - * 0b111..2.875 - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK (0xF000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT (12U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK (0x10000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT (16U) -/*! SNR_LQI_DIS - SNR LQI Disable - * 0b0..Normal operation. - * 0b1..The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement. - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK (0x20000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT (17U) -/*! SEL_SNR_MODE - Select SNR Mode - * 0b0..SNR estimate - * 0b1..Mapped correlation magnitude - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK (0x40000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT (18U) -/*! MEAS_TRANS_TO_IDLE - Measurement Transition to IDLE - * 0b0..Module transitions to RSSI state - * 0b1..Module transitions to IDLE state - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK (0x80000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT (19U) -/*! CCA1_ED_EN_DIS - CCA1_ED_EN Disable - * 0b0..Normal operation - * 0b1..CCA1_ED_EN input is disabled - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK (0x100000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT (20U) -/*! MAN_MEAS_COMPLETE - Manual measurement complete - * 0b0..Normal operation - * 0b1..Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug. - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_MASK (0x200000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_SHIFT (21U) -/*! NB_WB_OVRD - Narrowband Wideband Override - * 0b0..RSSI forced to be in Wideband mode if NB_WB_OVRD_EN is set - * 0b1..RSSI forced to be in Narrowband mode if NB_WB_OVRD_EN is set - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_MASK (0x400000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_SHIFT (22U) -/*! NB_WB_OVRD_EN - Narrowband Wideband Override Enable - * 0b0..Normal operation - * 0b1..RSSI narrowband/wideband selection is via NB_WB_OVRD - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK (0xF000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT (24U) -/*! SNR_LQI_WEIGHT - SNR LQI Weight - * 0b0000..0.0 - * 0b0001..1.0 - * 0b0010..1.125 - * 0b0011..1.25 - * 0b0100..1.375 - * 0b0101..1.5 - * 0b0110..1.625 - * 0b0111..1.75 - * 0b1000..1.875 - * 0b1001..2.0 - * 0b1010..2.125 - * 0b1011..2.25 - * 0b1100..2.375 - * 0b1101..2.5 - * 0b1110..2.625 - * 0b1111..2.75 - */ -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK (0xF0000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT (28U) -#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK) -/*! @} */ - -/*! @name CCA_ED_LQI_STAT_0 - RX_DIG CCA ED LQI Status Register 0 */ -/*! @{ */ -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK (0xFFU) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT (0U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK (0xFF00U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT (8U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK (0xFF0000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT (16U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK (0x1000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT (24U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK (0x2000000U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT (25U) -#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_0 - Receive Channel Filter Coefficient 0 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK (0x3FU) -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_1 - Receive Channel Filter Coefficient 1 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK (0x3FU) -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_2 - Receive Channel Filter Coefficient 2 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_3 - Receive Channel Filter Coefficient 3 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_4 - Receive Channel Filter Coefficient 4 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_5 - Receive Channel Filter Coefficient 5 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK (0x7FU) -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_6 - Receive Channel Filter Coefficient 6 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK (0xFFU) -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_7 - Receive Channel Filter Coefficient 7 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK (0xFFU) -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_8 - Receive Channel Filter Coefficient 8 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK (0x1FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_9 - Receive Channel Filter Coefficient 9 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK (0x1FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_10 - Receive Channel Filter Coefficient 10 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK (0x3FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK) -/*! @} */ - -/*! @name RX_CHF_COEF_11 - Receive Channel Filter Coefficient 11 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK (0x3FFU) -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT (0U) -#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK) -/*! @} */ - -/*! @name AGC_MAN_AGC_IDX - AGC Manual AGC Index */ -/*! @{ */ -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_MASK (0x1FU) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_SHIFT (0U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_MASK) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK (0x1F0000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT (16U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK (0x1000000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT (24U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK (0x2000000U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT (25U) -#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK) -/*! @} */ - -/*! @name DC_RESID_CTRL - DC Residual Control */ -/*! @{ */ -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U) -/*! DC_RESID_EXT_DC_EN - DC Residual External DC Enable - * 0b0..External DC disable. The DC Residual activates at a delay specified by DC_RESID_DLY after an AGC gain change pulse. The DC Residual is initialized with a DC offset of 0. - * 0b1..External DC enable. The DC residual activates after the DCOC's tracking hold timer expires. The DC Residual is initialized with the DC estimate from the DCOC tracking estimator. - */ -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U) -#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK) -/*! @} */ - -/*! @name DC_RESID_EST - DC Residual Estimate */ -/*! @{ */ -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U) -#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK) -/*! @} */ - -/*! @name RX_RCCAL_CTRL0 - RX RC Calibration Control0 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK (0xFU) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK (0x1F0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT (4U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK (0x200U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT (9U) -/*! BBA_RCCAL_DIS - BBA RC Calibration Disable - * 0b0..BBA RC Calibration is enabled - * 0b1..BBA RC Calibration is disabled - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK (0x3000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT (12U) -/*! RCCAL_SMP_DLY - RC Calibration Sample Delay - * 0b00..The comp_out signal is sampled 0 clk cycle after sample signal is deasserted - * 0b01..The comp_out signal is sampled 1 clk cycle after sample signal is deasserted - * 0b10..The comp_out signal is sampled 2 clk cycle after sample signal is deasserted - * 0b11..The comp_out signal is sampled 3 clk cycle after sample signal is deasserted - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK (0x8000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT (15U) -/*! RCCAL_COMP_INV - RC Calibration comp_out Invert - * 0b0..The comp_out signal polarity is NOT inverted - * 0b1..The comp_out signal polarity is inverted - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK (0xF0000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT (20U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT (25U) -/*! TZA_RCCAL_DIS - TZA RC Calibration Disable - * 0b0..TZA RC Calibration is enabled - * 0b1..TZA RC Calibration is disabled - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK) -/*! @} */ - -/*! @name RX_RCCAL_CTRL1 - RX RC Calibration Control1 */ -/*! @{ */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK (0xFU) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK (0x1F0U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT (4U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK (0x200U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT (9U) -/*! ADC_RCCAL_DIS - ADC RC Calibration Disable - * 0b0..ADC RC Calibration is enabled - * 0b1..ADC RC Calibration is disabled - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK (0xF0000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK (0x1F00000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT (20U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK (0x2000000U) -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT (25U) -/*! BBA2_RCCAL_DIS - BBA2 RC Calibration Disable - * 0b0..BBA2 RC Calibration is enabled - * 0b1..BBA2 RC Calibration is disabled - */ -#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK) -/*! @} */ - -/*! @name RX_RCCAL_STAT - RX RC Calibration Status */ -/*! @{ */ -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK (0x1FU) -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT (0U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK (0x3E0U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT (5U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK (0x7C00U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT (10U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK (0x1F0000U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT (16U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK (0x3E00000U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT (21U) -#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK) -/*! @} */ - -/*! @name AUXPLL_FCAL_CTRL - Aux PLL Frequency Calibration Control */ -/*! @{ */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK (0x7FU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK (0x80U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT (7U) -/*! AUXPLL_DAC_CAL_ADJUST_DIS - Aux PLL Frequency Calibration Disable - * 0b0..Calibration is enabled - * 0b1..Calibration is disabled - */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK (0x100U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT (8U) -/*! FCAL_RUN_CNT - Aux PLL Frequency Calibration Run Count - * 0b0..Run count is 256 clock cycles - * 0b1..Run count is 512 clock cycles - */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK (0x200U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT (9U) -/*! FCAL_COMP_INV - Aux PLL Frequency Calibration Comparison Invert - * 0b0..(Default) The comparison associated with the count is not inverted. - * 0b1..The comparison associated with the count is inverted - */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK (0xC00U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT (10U) -/*! FCAL_SMP_DLY - Aux PLL Frequency Calibration Sample Delay - * 0b00..The count signal is sampled 1 clk cycle after fcal_run signal is deasserted - * 0b01..The count signal is sampled 2 clk cycle after fcal_run signal is deasserted - * 0b10..The count signal is sampled 3 clk cycle after fcal_run signal is deasserted - * 0b11..The count signal is sampled 4 clk cycle after fcal_run signal is deasserted - */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK (0x7F0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK) -/*! @} */ - -/*! @name AUXPLL_FCAL_CNT6 - Aux PLL Frequency Calibration Count 6 */ -/*! @{ */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK) -/*! @} */ - -/*! @name AUXPLL_FCAL_CNT5_4 - Aux PLL Frequency Calibration Count 5 and 4 */ -/*! @{ */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK) -/*! @} */ - -/*! @name AUXPLL_FCAL_CNT3_2 - Aux PLL Frequency Calibration Count 3 and 2 */ -/*! @{ */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK) -/*! @} */ - -/*! @name AUXPLL_FCAL_CNT1_0 - Aux PLL Frequency Calibration Count 1 and 0 */ -/*! @{ */ -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK (0x3FFU) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT (0U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK (0x3FF0000U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT (16U) -#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_RX_DIG_Register_Masks */ - - -/* XCVR_RX_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_RX_DIG base address */ -#define XCVR_RX_DIG_BASE (0x41030000u) -/** Peripheral XCVR_RX_DIG base pointer */ -#define XCVR_RX_DIG ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE) -/** Array initializer of XCVR_RX_DIG peripheral base addresses */ -#define XCVR_RX_DIG_BASE_ADDRS { XCVR_RX_DIG_BASE } -/** Array initializer of XCVR_RX_DIG peripheral base pointers */ -#define XCVR_RX_DIG_BASE_PTRS { XCVR_RX_DIG } - -/*! - * @} - */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_TSM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer - * @{ - */ - -/** XCVR_TSM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< TSM CONTROL, offset: 0x0 */ - __IO uint32_t END_OF_SEQ; /**< TSM END OF SEQUENCE, offset: 0x4 */ - __IO uint32_t PA_POWER; /**< PA POWER, offset: 0x8 */ - __IO uint32_t PA_RAMP_TBL0; /**< PA RAMP TABLE 0, offset: 0xC */ - __IO uint32_t PA_RAMP_TBL1; /**< PA RAMP TABLE 1, offset: 0x10 */ - __IO uint32_t PA_RAMP_TBL2; /**< PA RAMP TABLE 2, offset: 0x14 */ - __IO uint32_t PA_RAMP_TBL3; /**< PA RAMP TABLE 3, offset: 0x18 */ - uint8_t RESERVED_0[8]; - __IO uint32_t RECYCLE_COUNT; /**< TSM RECYCLE COUNT, offset: 0x24 */ - __IO uint32_t FAST_CTRL1; /**< TSM FAST WARMUP CONTROL 1, offset: 0x28 */ - __IO uint32_t FAST_CTRL2; /**< TSM FAST WARMUP CONTROL 2, offset: 0x2C */ - __IO uint32_t TIMING00; /**< TSM_TIMING00, offset: 0x30 */ - __IO uint32_t TIMING01; /**< TSM_TIMING01, offset: 0x34 */ - __IO uint32_t TIMING02; /**< TSM_TIMING02, offset: 0x38 */ - __IO uint32_t TIMING03; /**< TSM_TIMING03, offset: 0x3C */ - __IO uint32_t TIMING04; /**< TSM_TIMING04, offset: 0x40 */ - __IO uint32_t TIMING05; /**< TSM_TIMING05, offset: 0x44 */ - __IO uint32_t TIMING06; /**< TSM_TIMING06, offset: 0x48 */ - __IO uint32_t TIMING07; /**< TSM_TIMING07, offset: 0x4C */ - __IO uint32_t TIMING08; /**< TSM_TIMING08, offset: 0x50 */ - __IO uint32_t TIMING09; /**< TSM_TIMING09, offset: 0x54 */ - __IO uint32_t TIMING10; /**< TSM_TIMING10, offset: 0x58 */ - __IO uint32_t TIMING11; /**< TSM_TIMING11, offset: 0x5C */ - __IO uint32_t TIMING12; /**< TSM_TIMING12, offset: 0x60 */ - __IO uint32_t TIMING13; /**< TSM_TIMING13, offset: 0x64 */ - __IO uint32_t TIMING14; /**< TSM_TIMING14, offset: 0x68 */ - __IO uint32_t TIMING15; /**< TSM_TIMING15, offset: 0x6C */ - __IO uint32_t TIMING16; /**< TSM_TIMING16, offset: 0x70 */ - __IO uint32_t TIMING17; /**< TSM_TIMING17, offset: 0x74 */ - __IO uint32_t TIMING18; /**< TSM_TIMING18, offset: 0x78 */ - __IO uint32_t TIMING19; /**< TSM_TIMING19, offset: 0x7C */ - __IO uint32_t TIMING20; /**< TSM_TIMING20, offset: 0x80 */ - __IO uint32_t TIMING21; /**< TSM_TIMING21, offset: 0x84 */ - __IO uint32_t TIMING22; /**< TSM_TIMING22, offset: 0x88 */ - __IO uint32_t TIMING23; /**< TSM_TIMING23, offset: 0x8C */ - __IO uint32_t TIMING24; /**< TSM_TIMING24, offset: 0x90 */ - __IO uint32_t TIMING25; /**< TSM_TIMING25, offset: 0x94 */ - __IO uint32_t TIMING26; /**< TSM_TIMING26, offset: 0x98 */ - __IO uint32_t TIMING27; /**< TSM_TIMING27, offset: 0x9C */ - __IO uint32_t TIMING28; /**< TSM_TIMING28, offset: 0xA0 */ - __IO uint32_t TIMING29; /**< TSM_TIMING29, offset: 0xA4 */ - __IO uint32_t TIMING30; /**< TSM_TIMING30, offset: 0xA8 */ - __IO uint32_t TIMING31; /**< TSM_TIMING31, offset: 0xAC */ - __IO uint32_t TIMING32; /**< TSM_TIMING32, offset: 0xB0 */ - __IO uint32_t TIMING33; /**< TSM_TIMING33, offset: 0xB4 */ - __IO uint32_t TIMING34; /**< TSM_TIMING34, offset: 0xB8 */ - __IO uint32_t TIMING35; /**< TSM_TIMING35, offset: 0xBC */ - __IO uint32_t TIMING36; /**< TSM_TIMING36, offset: 0xC0 */ - __IO uint32_t TIMING37; /**< TSM_TIMING37, offset: 0xC4 */ - __IO uint32_t TIMING38; /**< TSM_TIMING38, offset: 0xC8 */ - __IO uint32_t TIMING39; /**< TSM_TIMING39, offset: 0xCC */ - __IO uint32_t TIMING40; /**< TSM_TIMING40, offset: 0xD0 */ - __IO uint32_t TIMING41; /**< TSM_TIMING41, offset: 0xD4 */ - __IO uint32_t TIMING42; /**< TSM_TIMING42, offset: 0xD8 */ - __IO uint32_t TIMING43; /**< TSM_TIMING43, offset: 0xDC */ - __IO uint32_t TIMING44; /**< TSM_TIMING44, offset: 0xE0 */ - __IO uint32_t TIMING45; /**< TSM_TIMING45, offset: 0xE4 */ - __IO uint32_t TIMING46; /**< TSM_TIMING46, offset: 0xE8 */ - __IO uint32_t TIMING47; /**< TSM_TIMING47, offset: 0xEC */ - __IO uint32_t TIMING48; /**< TSM_TIMING48, offset: 0xF0 */ - __IO uint32_t TIMING49; /**< TSM_TIMING49, offset: 0xF4 */ - __IO uint32_t TIMING50; /**< TSM_TIMING50, offset: 0xF8 */ - __IO uint32_t TIMING51; /**< TSM_TIMING51, offset: 0xFC */ - __IO uint32_t TIMING52; /**< TSM_TIMING52, offset: 0x100 */ - __IO uint32_t TIMING53; /**< TSM_TIMING53, offset: 0x104 */ - __IO uint32_t TIMING54; /**< TSM_TIMING54, offset: 0x108 */ - __IO uint32_t TIMING55; /**< TSM_TIMING55, offset: 0x10C */ - __IO uint32_t TIMING56; /**< TSM_TIMING56, offset: 0x110 */ - __IO uint32_t TIMING57; /**< TSM_TIMING57, offset: 0x114 */ - __IO uint32_t TIMING58; /**< TSM_TIMING58, offset: 0x118 */ - __IO uint32_t OVRD0; /**< TSM OVERRIDE REGISTER 0, offset: 0x11C */ - __IO uint32_t OVRD1; /**< TSM OVERRIDE REGISTER 1, offset: 0x120 */ - __IO uint32_t OVRD2; /**< TSM OVERRIDE REGISTER 2, offset: 0x124 */ - __IO uint32_t OVRD3; /**< TSM OVERRIDE REGISTER 3, offset: 0x128 */ -} XCVR_TSM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_TSM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks - * @{ - */ - -/*! @name CTRL - TSM CONTROL */ -/*! @{ */ -#define XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK (0x2U) -#define XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT (1U) -/*! TSM_SOFT_RESET - TSM Soft Reset - * 0b0..TSM Soft Reset removed. Normal operation. - * 0b1..TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared. - */ -#define XCVR_TSM_CTRL_TSM_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT)) & XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK) -#define XCVR_TSM_CTRL_FORCE_TX_EN_MASK (0x4U) -#define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT (2U) -/*! FORCE_TX_EN - Force Transmit Enable - * 0b0..TSM Idle - * 0b1..TSM executes a TX sequence - */ -#define XCVR_TSM_CTRL_FORCE_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK) -#define XCVR_TSM_CTRL_FORCE_RX_EN_MASK (0x8U) -#define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT (3U) -/*! FORCE_RX_EN - Force Receive Enable - * 0b0..TSM Idle - * 0b1..TSM executes a RX sequence - */ -#define XCVR_TSM_CTRL_FORCE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK) -#define XCVR_TSM_CTRL_PA_RAMP_SEL_MASK (0x30U) -#define XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT (4U) -#define XCVR_TSM_CTRL_PA_RAMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK) -#define XCVR_TSM_CTRL_DATA_PADDING_EN_MASK (0xC0U) -#define XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT (6U) -/*! DATA_PADDING_EN - Data Padding Enable - * 0b00..Disable TX Data Padding - * 0b01..Enable TX Data Padding - */ -#define XCVR_TSM_CTRL_DATA_PADDING_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK) -#define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK (0x100U) -#define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT (8U) -/*! TSM_IRQ0_EN - TSM_IRQ0 Enable/Disable bit - * 0b0..TSM_IRQ0 is disabled - * 0b1..TSM_IRQ0 is enabled - */ -#define XCVR_TSM_CTRL_TSM_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK) -#define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK (0x200U) -#define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT (9U) -/*! TSM_IRQ1_EN - TSM_IRQ1 Enable/Disable bit - * 0b0..TSM_IRQ1 is disabled - * 0b1..TSM_IRQ1 is enabled - */ -#define XCVR_TSM_CTRL_TSM_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK (0xF000U) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT (12U) -#define XCVR_TSM_CTRL_RAMP_DN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT)) & XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK) -#define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK (0x10000U) -#define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT (16U) -#define XCVR_TSM_CTRL_TX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK) -#define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK (0x20000U) -#define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT (17U) -#define XCVR_TSM_CTRL_RX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK (0x40000U) -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT (18U) -/*! ABORT_ON_CTUNE - Abort On Coarse Tune Lock Detect Failure - * 0b0..don't allow TSM abort on Coarse Tune Unlock Detect - * 0b1..allow TSM abort on Coarse Tune Unlock Detect - */ -#define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK (0x80000U) -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT (19U) -/*! ABORT_ON_CYCLE_SLIP - Abort On Cycle Slip Lock Detect Failure - * 0b0..don't allow TSM abort on Cycle Slip Unlock Detect - * 0b1..allow TSM abort on Cycle Slip Unlock Detect - */ -#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK) -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK (0x100000U) -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT (20U) -/*! ABORT_ON_FREQ_TARG - Abort On Frequency Target Lock Detect Failure - * 0b0..don't allow TSM abort on Frequency Target Unlock Detect - * 0b1..allow TSM abort on Frequency Target Unlock Detect - */ -#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK) -#define XCVR_TSM_CTRL_BKPT_MASK (0xFF000000U) -#define XCVR_TSM_CTRL_BKPT_SHIFT (24U) -#define XCVR_TSM_CTRL_BKPT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK) -/*! @} */ - -/*! @name END_OF_SEQ - TSM END OF SEQUENCE */ -/*! @{ */ -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK (0xFFU) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT (0U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK (0xFF00U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT (8U) -#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK (0xFF0000U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT (16U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK (0xFF000000U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT (24U) -#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK) -/*! @} */ - -/*! @name PA_POWER - PA POWER */ -/*! @{ */ -#define XCVR_TSM_PA_POWER_PA_POWER_MASK (0x3FU) -#define XCVR_TSM_PA_POWER_PA_POWER_SHIFT (0U) -#define XCVR_TSM_PA_POWER_PA_POWER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_POWER_PA_POWER_SHIFT)) & XCVR_TSM_PA_POWER_PA_POWER_MASK) -/*! @} */ - -/*! @name PA_RAMP_TBL0 - PA RAMP TABLE 0 */ -/*! @{ */ -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK) -/*! @} */ - -/*! @name PA_RAMP_TBL1 - PA RAMP TABLE 1 */ -/*! @{ */ -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK) -/*! @} */ - -/*! @name PA_RAMP_TBL2 - PA RAMP TABLE 2 */ -/*! @{ */ -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_MASK) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_MASK) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_MASK) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_MASK) -/*! @} */ - -/*! @name PA_RAMP_TBL3 - PA RAMP TABLE 3 */ -/*! @{ */ -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_MASK (0x3FU) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_SHIFT (0U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_MASK) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_MASK (0x3F00U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_SHIFT (8U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_MASK) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_MASK (0x3F0000U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_SHIFT (16U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_MASK) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_MASK (0x3F000000U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_SHIFT (24U) -#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_MASK) -/*! @} */ - -/*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */ -/*! @{ */ -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK (0xFF0000U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT (16U) -#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK) -/*! @} */ - -/*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL 1 */ -/*! @{ */ -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK (0x1U) -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT (0U) -/*! FAST_TX_WU_EN - Fast TSM TX Warmup Enable - * 0b0..Fast TSM TX Warmups are disabled - * 0b1..Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for BLE mode, the RF channel is not an advertising channel. - */ -#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK (0x2U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT (1U) -/*! FAST_RX_WU_EN - Fast TSM RX Warmup Enable - * 0b0..Fast TSM RX Warmups are disabled - * 0b1..Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for BLE mode, the RF channel is not an advertising channel. - */ -#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK (0x4U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT (2U) -/*! FAST_RX2TX_EN - Fast TSM RX-to-TX Transition Enable - * 0b0..Disable Fast RX-to-TX transitions - * 0b1..Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by 802.15.4 ZSM) - */ -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK (0x8U) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT (3U) -#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U) -#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK) -/*! @} */ - -/*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL 2 */ -/*! @{ */ -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK (0xFFU) -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT (0U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK (0xFF00U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT (8U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK (0xFF0000U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT (16U) -#define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK (0xFF000000U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT (24U) -#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK) -/*! @} */ - -/*! @name TIMING00 - TSM_TIMING00 */ -/*! @{ */ -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING01 - TSM_TIMING01 */ -/*! @{ */ -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING02 - TSM_TIMING02 */ -/*! @{ */ -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING03 - TSM_TIMING03 */ -/*! @{ */ -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING04 - TSM_TIMING04 */ -/*! @{ */ -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING05 - TSM_TIMING05 */ -/*! @{ */ -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING06 - TSM_TIMING06 */ -/*! @{ */ -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING07 - TSM_TIMING07 */ -/*! @{ */ -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING08 - TSM_TIMING08 */ -/*! @{ */ -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING09 - TSM_TIMING09 */ -/*! @{ */ -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING10 - TSM_TIMING10 */ -/*! @{ */ -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING11 - TSM_TIMING11 */ -/*! @{ */ -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK) -/*! @} */ - -/*! @name TIMING12 - TSM_TIMING12 */ -/*! @{ */ -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING13 - TSM_TIMING13 */ -/*! @{ */ -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_MASK) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_MASK) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_MASK) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING14 - TSM_TIMING14 */ -/*! @{ */ -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING15 - TSM_TIMING15 */ -/*! @{ */ -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING16 - TSM_TIMING16 */ -/*! @{ */ -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING17 - TSM_TIMING17 */ -/*! @{ */ -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK) -/*! @} */ - -/*! @name TIMING18 - TSM_TIMING18 */ -/*! @{ */ -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING19 - TSM_TIMING19 */ -/*! @{ */ -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING20 - TSM_TIMING20 */ -/*! @{ */ -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING21 - TSM_TIMING21 */ -/*! @{ */ -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING22 - TSM_TIMING22 */ -/*! @{ */ -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING23 - TSM_TIMING23 */ -/*! @{ */ -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK) -/*! @} */ - -/*! @name TIMING24 - TSM_TIMING24 */ -/*! @{ */ -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING25 - TSM_TIMING25 */ -/*! @{ */ -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING26 - TSM_TIMING26 */ -/*! @{ */ -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK) -/*! @} */ - -/*! @name TIMING27 - TSM_TIMING27 */ -/*! @{ */ -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING28 - TSM_TIMING28 */ -/*! @{ */ -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING29 - TSM_TIMING29 */ -/*! @{ */ -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING30 - TSM_TIMING30 */ -/*! @{ */ -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING31 - TSM_TIMING31 */ -/*! @{ */ -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING32 - TSM_TIMING32 */ -/*! @{ */ -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING33 - TSM_TIMING33 */ -/*! @{ */ -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING34 - TSM_TIMING34 */ -/*! @{ */ -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING35 - TSM_TIMING35 */ -/*! @{ */ -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK) -/*! @} */ - -/*! @name TIMING36 - TSM_TIMING36 */ -/*! @{ */ -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING37 - TSM_TIMING37 */ -/*! @{ */ -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING37_RX_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING38 - TSM_TIMING38 */ -/*! @{ */ -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING39 - TSM_TIMING39 */ -/*! @{ */ -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING40 - TSM_TIMING40 */ -/*! @{ */ -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING41 - TSM_TIMING41 */ -/*! @{ */ -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING42 - TSM_TIMING42 */ -/*! @{ */ -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING43 - TSM_TIMING43 */ -/*! @{ */ -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING44 - TSM_TIMING44 */ -/*! @{ */ -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING45 - TSM_TIMING45 */ -/*! @{ */ -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING46 - TSM_TIMING46 */ -/*! @{ */ -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING47 - TSM_TIMING47 */ -/*! @{ */ -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING48 - TSM_TIMING48 */ -/*! @{ */ -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING49 - TSM_TIMING49 */ -/*! @{ */ -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING50 - TSM_TIMING50 */ -/*! @{ */ -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING51 - TSM_TIMING51 */ -/*! @{ */ -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING52 - TSM_TIMING52 */ -/*! @{ */ -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING53 - TSM_TIMING53 */ -/*! @{ */ -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING54 - TSM_TIMING54 */ -/*! @{ */ -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING55 - TSM_TIMING55 */ -/*! @{ */ -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING56 - TSM_TIMING56 */ -/*! @{ */ -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING57 - TSM_TIMING57 */ -/*! @{ */ -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK (0xFF0000U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT (16U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK (0xFF000000U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT (24U) -#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK) -/*! @} */ - -/*! @name TIMING58 - TSM_TIMING58 */ -/*! @{ */ -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK (0xFFU) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT (0U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK (0xFF00U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT (8U) -#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK) -/*! @} */ - -/*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */ -/*! @{ */ -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT (0U) -/*! BB_LDO_HF_EN_OVRD_EN - Override control for BB_LDO_HF_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_HF_EN_OVRD to override the signal "bb_ldo_hf_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT (2U) -/*! BB_LDO_ADCDAC_EN_OVRD_EN - Override control for BB_LDO_ADCDAC_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal "bb_ldo_adcdac_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT (4U) -/*! BB_LDO_BBA_EN_OVRD_EN - Override control for BB_LDO_BBA_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_BBA_EN_OVRD to override the signal "bb_ldo_bba_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT (6U) -/*! BB_LDO_PD_EN_OVRD_EN - Override control for BB_LDO_PD_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_PD_EN_OVRD to override the signal "bb_ldo_pd_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT (8U) -/*! BB_LDO_FDBK_EN_OVRD_EN - Override control for BB_LDO_FDBK_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_FDBK_EN_OVRD to override the signal "bb_ldo_fdbk_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT (10U) -/*! BB_LDO_VCOLO_EN_OVRD_EN - Override control for BB_LDO_VCOLO_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal "bb_ldo_vcolo_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT (12U) -/*! BB_LDO_VTREF_EN_OVRD_EN - Override control for BB_LDO_VTREF_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_VTREF_EN_OVRD to override the signal "bb_ldo_vtref_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT (14U) -/*! BB_LDO_FDBK_BLEED_EN_OVRD_EN - Override control for BB_LDO_FDBK_BLEED_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal "bb_ldo_fdbk_bleed_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT (16U) -/*! BB_LDO_VCOLO_BLEED_EN_OVRD_EN - Override control for BB_LDO_VCOLO_BLEED_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal "bb_ldo_vcolo_bleed_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT (18U) -/*! BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN - Override control for BB_LDO_VCOLO_FASTCHARGE_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal "bb_ldo_vcolo_fastcharge_en". - */ -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT (20U) -/*! BB_XTAL_PLL_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_PLL_REF_CLK_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_pll_ref_clk_en". - */ -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT (22U) -/*! BB_XTAL_DAC_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_DAC_REF_CLK_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal "bb_xtal_dac_ref_clk_en". - */ -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT (24U) -/*! BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_AUXPLL_REF_CLK_EN - * 0b0..Normal operation. - * 0b1..Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_auxpll_ref_clk_en". - */ -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_SHIFT (26U) -/*! PLL_LOOP_IS_OPEN_OVRD_EN - Override control for PLL_LOOP_IS_OPEN - * 0b0..Normal operation. - * 0b1..Use the state of PLL_LOOP_IS_OPEN_OVRD to override the signal "pll_loop_is_open". - */ -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_MASK) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT (28U) -/*! SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN - Override control for SY_PD_CYCLE_SLIP_LD_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal "sy_pd_cycle_slip_ld_en". - */ -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT (30U) -/*! SY_VCO_EN_OVRD_EN - Override control for SY_VCO_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_VCO_EN_OVRD to override the signal "sy_vco_en". - */ -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK) -/*! @} */ - -/*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */ -/*! @{ */ -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT (0U) -/*! SY_LO_RX_BUF_EN_OVRD_EN - Override control for SY_LO_RX_BUF_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_LO_RX_BUF_EN_OVRD to override the signal "sy_lo_rx_buf_en". - */ -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT (2U) -/*! SY_LO_TX_BUF_EN_OVRD_EN - Override control for SY_LO_TX_BUF_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_LO_TX_BUF_EN_OVRD to override the signal "sy_lo_tx_buf_en". - */ -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT (4U) -/*! SY_DIVN_EN_OVRD_EN - Override control for SY_DIVN_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_DIVN_EN_OVRD to override the signal "sy_divn_en". - */ -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT (6U) -/*! SY_PD_FILTER_CHARGE_EN_OVRD_EN - Override control for SY_PD_FILTER_CHARGE_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_PD_FILTER_CHARGE_EN_OVRD to override the signal "sy_pd_filter_charge_en". - */ -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT (8U) -/*! SY_PD_EN_OVRD_EN - Override control for SY_PD_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_PD_EN_OVRD to override the signal "sy_pd_en". - */ -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT (10U) -/*! SY_LO_DIVN_EN_OVRD_EN - Override control for SY_LO_DIVN_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_LO_DIVN_EN_OVRD to override the signal "sy_lo_divn_en". - */ -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT (12U) -/*! SY_LO_RX_EN_OVRD_EN - Override control for SY_LO_RX_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_LO_RX_EN_OVRD to override the signal "sy_lo_rx_en". - */ -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT (14U) -/*! SY_LO_TX_EN_OVRD_EN - Override control for SY_LO_TX_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_LO_TX_EN_OVRD to override the signal "sy_lo_tx_en". - */ -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT (16U) -/*! SY_DIVN_CAL_EN_OVRD_EN - Override control for SY_DIVN_CAL_EN - * 0b0..Normal operation. - * 0b1..Use the state of SY_DIVN_CAL_EN_OVRD to override the signal "sy_divn_cal_en". - */ -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT (18U) -/*! RX_MIXER_EN_OVRD_EN - Override control for RX_MIXER_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_MIXER_EN_OVRD to override the signal "rx_mixer_en". - */ -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT (20U) -/*! TX_PA_EN_OVRD_EN - Override control for TX_PA_EN - * 0b0..Normal operation. - * 0b1..Use the state of TX_PA_EN_OVRD to override the signal "tx_pa_en". - */ -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT (22U) -/*! RX_ADC_I_EN_OVRD_EN - Override control for RX_ADC_I_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_ADC_I_EN_OVRD to override the signal "rx_adc_i_en". - */ -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT (24U) -/*! RX_ADC_Q_EN_OVRD_EN - Override control for RX_ADC_Q_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_ADC_Q_EN_OVRD to override the signal "rx_adc_q_en". - */ -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT (26U) -/*! RX_ADC_RESET_EN_OVRD_EN - Override control for RX_ADC_RESET_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_ADC_RESET_EN_OVRD to override the signal "rx_adc_reset_en". - */ -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT (28U) -/*! RX_BBA_I_EN_OVRD_EN - Override control for RX_BBA_I_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_BBA_I_EN_OVRD to override the signal "rx_bba_i_en". - */ -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT (30U) -/*! RX_BBA_Q_EN_OVRD_EN - Override control for RX_BBA_Q_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_BBA_Q_EN_OVRD to override the signal "rx_bba_q_en". - */ -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK) -/*! @} */ - -/*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */ -/*! @{ */ -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT (0U) -/*! RX_BBA_PDET_EN_OVRD_EN - Override control for RX_BBA_PDET_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_BBA_PDET_EN_OVRD to override the signal "rx_bba_pdet_en". - */ -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT (2U) -/*! RX_BBA_DCOC_EN_OVRD_EN - Override control for RX_BBA_DCOC_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_BBA_DCOC_EN_OVRD to override the signal "rx_bba_dcoc_en". - */ -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT (4U) -/*! RX_LNA_EN_OVRD_EN - Override control for RX_LNA_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_LNA_EN_OVRD to override the signal "rx_lna_en". - */ -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT (6U) -/*! RX_TZA_I_EN_OVRD_EN - Override control for RX_TZA_I_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_TZA_I_EN_OVRD to override the signal "rx_tza_i_en". - */ -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT (8U) -/*! RX_TZA_Q_EN_OVRD_EN - Override control for RX_TZA_Q_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_TZA_Q_EN_OVRD to override the signal "rx_tza_q_en". - */ -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT (10U) -/*! RX_TZA_PDET_EN_OVRD_EN - Override control for RX_TZA_PDET_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_TZA_PDET_EN_OVRD to override the signal "rx_tza_pdet_en". - */ -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT (12U) -/*! RX_TZA_DCOC_EN_OVRD_EN - Override control for RX_TZA_DCOC_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". - */ -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT (13U) -/*! RX_TZA_DCOC_EN_OVRD - Override control for RX_TZA_DCOC_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en". - */ -#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT (14U) -/*! PLL_DIG_EN_OVRD_EN - Override control for PLL_DIG_EN - * 0b0..Normal operation. - * 0b1..Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en". - */ -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT (16U) -/*! TX_DIG_EN_OVRD_EN - Override control for TX_DIG_EN - * 0b0..Normal operation. - * 0b1..Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en". - */ -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT (18U) -/*! RX_DIG_EN_OVRD_EN - Override control for RX_DIG_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en". - */ -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT (20U) -/*! RX_INIT_OVRD_EN - Override control for RX_INIT - * 0b0..Normal operation. - * 0b1..Use the state of RX_INIT_OVRD to override the signal "rx_init". - */ -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD2_RX_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT (22U) -/*! SIGMA_DELTA_EN_OVRD_EN - Override control for SIGMA_DELTA_EN - * 0b0..Normal operation. - * 0b1..Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en". - */ -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT (24U) -/*! RX_PHY_EN_OVRD_EN - Override control for RX_PHY_EN - * 0b0..Normal operation. - * 0b1..Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en". - */ -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT (26U) -/*! DCOC_EN_OVRD_EN - Override control for DCOC_EN - * 0b0..Normal operation. - * 0b1..Use the state of DCOC_EN_OVRD to override the signal "dcoc_en". - */ -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD2_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT (28U) -/*! DCOC_INIT_OVRD_EN - Override control for DCOC_INIT - * 0b0..Normal operation. - * 0b1..Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init". - */ -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (30U) -/*! FREQ_TARG_LD_EN_OVRD_EN - Override control for FREQ_TARG_LD_EN - * 0b0..Normal operation. - * 0b1..Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en". - */ -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK) -/*! @} */ - -/*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */ -/*! @{ */ -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK (0x1U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT (0U) -/*! TSM_SPARE0_EN_OVRD_EN - Override control for TSM_SPARE0_EN - * 0b0..Normal operation. - * 0b1..Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en". - */ -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK (0x2U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT (1U) -#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK (0x4U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT (2U) -/*! TSM_SPARE1_EN_OVRD_EN - Override control for TSM_SPARE1_EN - * 0b0..Normal operation. - * 0b1..Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en". - */ -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK (0x8U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT (3U) -#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK (0x10U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT (4U) -/*! TSM_SPARE2_EN_OVRD_EN - Override control for TSM_SPARE2_EN - * 0b0..Normal operation. - * 0b1..Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en". - */ -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK (0x20U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT (5U) -#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK (0x40U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT (6U) -/*! TSM_SPARE3_EN_OVRD_EN - Override control for TSM_SPARE3_EN - * 0b0..Normal operation. - * 0b1..Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en". - */ -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK (0x80U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT (7U) -#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK (0x100U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT (8U) -/*! RXTX_AUXPLL_BIAS_EN_OVRD_EN - Override control for RXTX_AUXPLL_BIAS_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_BIAS_EN_OVRD to override the signal "rxtx_auxpll_bias_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK (0x200U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT (9U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK (0x400U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT (10U) -/*! RXTX_AUXPLL_VCO_EN_OVRD_EN - Override control for RXTX_AUXPLL_VCO_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_VCO_EN_OVRD to override the signal "rxtx_auxpll_vco_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK (0x800U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT (11U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK (0x1000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT (12U) -/*! RXTX_AUXPLL_FCAL_EN_OVRD_EN - Override control for RXTX_AUXPLL_FCAL_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_FCAL_EN_OVRD to override the signal "rxtx_auxpll_fcal_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK (0x2000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT (13U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK (0x4000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT (14U) -/*! RXTX_AUXPLL_LF_EN_OVRD_EN - Override control for RXTX_AUXPLL_LF_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_LF_EN_OVRD to override the signal "rxtx_auxpll_lf_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK (0x8000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT (15U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK (0x10000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT (16U) -/*! RXTX_AUXPLL_PD_EN_OVRD_EN - Override control for RXTX_AUXPLL_PD_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_PD_EN_OVRD to override the signal "rxtx_auxpll_pd_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK (0x20000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT (17U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT (18U) -/*! RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN - Override control for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD to override the signal "rxtx_auxpll_pd_lf_filter_charge_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK (0x80000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT (19U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK (0x100000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT (20U) -/*! RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN - Override control for RXTX_AUXPLL_ADC_BUF_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_ADC_BUF_EN_OVRD to override the signal "rxtx_auxpll_adc_buf_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK (0x200000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT (21U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK (0x400000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT (22U) -/*! RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN - Override control for RXTX_AUXPLL_DIG_BUF_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_AUXPLL_DIG_BUF_EN_OVRD to override the signal "rxtx_auxpll_dig_buf_en". - */ -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK (0x800000U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT (23U) -#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK (0x1000000U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT (24U) -/*! RXTX_RCCAL_EN_OVRD_EN - Override control for RXTX_RCCAL_EN - * 0b0..Normal operation. - * 0b1..Use the state of RXTX_RCCAL_EN_OVRD to override the signal "rxtx_rccal_en". - */ -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK (0x2000000U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT (25U) -#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK (0x4000000U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT (26U) -/*! TX_HPM_DAC_EN_OVRD_EN - Override control for TX_HPM_DAC_EN - * 0b0..Normal operation. - * 0b1..Use the state of TX_HPM_DAC_EN_OVRD to override the signal "tx_hpm_dac_en". - */ -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK (0x8000000U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT (27U) -#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK (0x10000000U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT (28U) -/*! TX_MODE_OVRD_EN - Override control for TX_MODE - * 0b0..Normal operation. - * 0b1..Use the state of TX_MODE_OVRD to override the signal "tx_mode". - */ -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK (0x20000000U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT (29U) -#define XCVR_TSM_OVRD3_TX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK (0x40000000U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT (30U) -/*! RX_MODE_OVRD_EN - Override control for RX_MODE - * 0b0..Normal operation. - * 0b1..Use the state of RX_MODE_OVRD to override the signal "rx_mode". - */ -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK (0x80000000U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT (31U) -#define XCVR_TSM_OVRD3_RX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_TSM_Register_Masks */ - - -/* XCVR_TSM - Peripheral instance base addresses */ -/** Peripheral XCVR_TSM base address */ -#define XCVR_TSM_BASE (0x410302C0u) -/** Peripheral XCVR_TSM base pointer */ -#define XCVR_TSM ((XCVR_TSM_Type *)XCVR_TSM_BASE) -/** Array initializer of XCVR_TSM peripheral base addresses */ -#define XCVR_TSM_BASE_ADDRS { XCVR_TSM_BASE } -/** Array initializer of XCVR_TSM peripheral base pointers */ -#define XCVR_TSM_BASE_PTRS { XCVR_TSM } - -/*! - * @} - */ /* end of group XCVR_TSM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_TX_DIG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer - * @{ - */ - -/** XCVR_TX_DIG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< TX Digital Control, offset: 0x0 */ - __IO uint32_t DATA_PADDING; /**< TX Data Padding, offset: 0x4 */ - __IO uint32_t GFSK_CTRL; /**< TX GFSK Modulator Control, offset: 0x8 */ - __IO uint32_t GFSK_COEFF2; /**< TX GFSK Filter Coefficients 2, offset: 0xC */ - __IO uint32_t GFSK_COEFF1; /**< TX GFSK Filter Coefficients 1, offset: 0x10 */ - __IO uint32_t FSK_SCALE; /**< TX FSK Modulation Levels, offset: 0x14 */ - __IO uint32_t DFT_PATTERN; /**< TX DFT Modulation Pattern, offset: 0x18 */ -} XCVR_TX_DIG_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_TX_DIG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks - * @{ - */ - -/*! @name CTRL - TX Digital Control */ -/*! @{ */ -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK (0xFU) -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT (0U) -/*! RADIO_DFT_MODE - Radio DFT Modes - * 0b0000..Normal Radio Operation, DFT not engaged. - * 0b0001..Carrier Frequency Only - * 0b0010..Pattern Register GFSK - * 0b0011..LFSR GFSK - * 0b0100..Pattern Register FSK - * 0b0101..LFSR FSK - * 0b0110..Pattern Register O-QPSK - * 0b0111..LFSR O-QPSK - * 0b1000..LFSR 802.15.4 Symbols - * 0b1001..PLL Modulation from RAM - * 0b1010..PLL Coarse Tune BIST - * 0b1011..PLL Frequency Synthesizer BIST - * 0b1100..High Port DAC BIST - * 0b1101..VCO Frequency Meter - * 0b1110..Reserved - * 0b1111..Reserved - */ -#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK) -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK (0x70U) -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT (4U) -/*! LFSR_LENGTH - LFSR Length - * 0b000..LFSR 9, tap mask 100010000 - * 0b001..LFSR 10, tap mask 1001000000 - * 0b010..LFSR 11, tap mask 11101000000 - * 0b011..LFSR 13, tap mask 1101100000000 - * 0b100..LFSR 15, tap mask 111010000000000 - * 0b101..LFSR 17, tap mask 11110000000000000 - * 0b110..Reserved - * 0b111..Reserved - */ -#define XCVR_TX_DIG_CTRL_LFSR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK) -#define XCVR_TX_DIG_CTRL_LFSR_EN_MASK (0x80U) -#define XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT (7U) -#define XCVR_TX_DIG_CTRL_LFSR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK) -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK (0x700U) -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT (8U) -/*! DFT_CLK_SEL - DFT Clock Selection - * 0b000..62.5 kHz - * 0b001..125 kHz - * 0b010..250 kHz - * 0b011..500 kHz - * 0b100..1 MHz - * 0b101..2 MHz - * 0b110..4 MHz - * 0b111..RF OSC Clock - */ -#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK (0x800U) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT (11U) -#define XCVR_TX_DIG_CTRL_TX_DFT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT)) & XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK) -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK (0x3000U) -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT (12U) -/*! SOC_TEST_SEL - Radio Clock Selector for SoC RF Clock Tests - * 0b00..No Clock Selected - * 0b01..PLL Sigma Delta Clock, divided by 2 - * 0b10..Auxiliary PLL Clock, divided by 2 - * 0b11..RF Ref Osc clock, divided by 2 - */ -#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK (0x10000U) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT (16U) -#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK) -#define XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK (0x80000U) -#define XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT (19U) -#define XCVR_TX_DIG_CTRL_ZERO_FDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT)) & XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK (0xFFC00000U) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT (22U) -#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK) -/*! @} */ - -/*! @name DATA_PADDING - TX Data Padding */ -/*! @{ */ -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK (0xFFU) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT (0U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK (0xFF00U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT (8U) -#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK (0x7FFF0000U) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT (16U) -#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK) -#define XCVR_TX_DIG_DATA_PADDING_LRM_MASK (0x80000000U) -#define XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT (31U) -#define XCVR_TX_DIG_DATA_PADDING_LRM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_LRM_MASK) -/*! @} */ - -/*! @name GFSK_CTRL - TX GFSK Modulator Control */ -/*! @{ */ -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK (0xFFFFU) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK (0x30000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT (16U) -/*! GFSK_MI - GFSK Modulation Index - * 0b00..0.32 - * 0b01..0.50 - * 0b10..0.70 - * 0b11..1.00 - */ -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK (0x100000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT (20U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK (0x200000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT (21U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK (0x7000000U) -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT (24U) -/*! GFSK_MOD_INDEX_SCALING - GFSK Modulation Index Scaling Factor - * 0b000..1 - * 0b001..1 + 1/32 - * 0b010..1 + 1/16 - * 0b011..1 + 1/8 - * 0b100..1 - 1/32 - * 0b101..1 - 1/16 - * 0b110..1 - 1/8 - * 0b111..Reserved - */ -#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK (0x10000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT (28U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK (0x20000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT (29U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK (0x40000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT (30U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK (0x80000000U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT (31U) -#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK) -/*! @} */ - -/*! @name GFSK_COEFF2 - TX GFSK Filter Coefficients 2 */ -/*! @{ */ -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK) -/*! @} */ - -/*! @name GFSK_COEFF1 - TX GFSK Filter Coefficients 1 */ -/*! @{ */ -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT (0U) -#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK) -/*! @} */ - -/*! @name FSK_SCALE - TX FSK Modulation Levels */ -/*! @{ */ -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK (0x1FFFU) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT (0U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK (0x1FFF0000U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT (16U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK) -#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_MASK (0x80000000U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_SHIFT (31U) -#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_MASK) -/*! @} */ - -/*! @name DFT_PATTERN - TX DFT Modulation Pattern */ -/*! @{ */ -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU) -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U) -#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_TX_DIG_Register_Masks */ - - -/* XCVR_TX_DIG - Peripheral instance base addresses */ -/** Peripheral XCVR_TX_DIG base address */ -#define XCVR_TX_DIG_BASE (0x41030200u) -/** Peripheral XCVR_TX_DIG base pointer */ -#define XCVR_TX_DIG ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE) -/** Array initializer of XCVR_TX_DIG peripheral base addresses */ -#define XCVR_TX_DIG_BASE_ADDRS { XCVR_TX_DIG_BASE } -/** Array initializer of XCVR_TX_DIG peripheral base pointers */ -#define XCVR_TX_DIG_BASE_PTRS { XCVR_TX_DIG } - -/*! - * @} - */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_WOR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_WOR_Peripheral_Access_Layer XCVR_WOR Peripheral Access Layer - * @{ - */ - -/** XCVR_WOR - Register Layout Typedef */ -typedef struct { - __IO uint32_t WOR_CTRL; /**< WAKE-ON-RADIO CONTROL REGISTER, offset: 0x0 */ - __IO uint32_t WOR_TIMEOUT; /**< WAKE-ON-RADIO TIMEOUT REGISTER, offset: 0x4 */ - __I uint32_t TIMESTAMP1; /**< WAKE-ON-RADIO TIMESTAMP 1, offset: 0x8 */ - __I uint32_t TIMESTAMP2; /**< WAKE-ON-RADIO TIMESTAMP 2, offset: 0xC */ - __I uint32_t TIMESTAMP3; /**< WAKE-ON-RADIO TIMESTAMP 3, offset: 0x10 */ - __I uint32_t WOR_STATUS; /**< WAKE-ON-RADIO STATUS REGISTER, offset: 0x14 */ - __IO uint32_t WW_CTRL; /**< WINDOW-WIDENING CONTROL REGISTER, offset: 0x18 */ - __IO uint32_t HOP_CTRL; /**< FREQUENCY HOP CONTROL REGISTER, offset: 0x1C */ - __IO uint32_t SLOT0_DESC0; /**< SLOT 0 DESCRIPTOR (LSB), offset: 0x20 */ - __IO uint32_t SLOT0_DESC1; /**< SLOT 0 DESCRIPTOR (MSB), offset: 0x24 */ - __IO uint32_t SLOT1_DESC0; /**< SLOT 1 DESCRIPTOR (LSB), offset: 0x28 */ - __IO uint32_t SLOT1_DESC1; /**< SLOT 1 DESCRIPTOR (MSB), offset: 0x2C */ - __IO uint32_t SLOT2_DESC0; /**< SLOT 2 DESCRIPTOR (LSB), offset: 0x30 */ - __IO uint32_t SLOT2_DESC1; /**< SLOT 2 DESCRIPTOR (MSB), offset: 0x34 */ - __IO uint32_t SLOT3_DESC0; /**< SLOT 3 DESCRIPTOR (LSB), offset: 0x38 */ - __IO uint32_t SLOT3_DESC1; /**< SLOT 3 DESCRIPTOR (MSB), offset: 0x3C */ -} XCVR_WOR_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_WOR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_WOR_Register_Masks XCVR_WOR Register Masks - * @{ - */ - -/*! @name WOR_CTRL - WAKE-ON-RADIO CONTROL REGISTER */ -/*! @{ */ -#define XCVR_WOR_WOR_CTRL_WOR_EN_MASK (0x1U) -#define XCVR_WOR_WOR_CTRL_WOR_EN_SHIFT (0U) -#define XCVR_WOR_WOR_CTRL_WOR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_EN_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_EN_MASK) -#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_MASK (0x2U) -#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_SHIFT (1U) -#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_SHIFT)) & XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_MASK) -#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_MASK (0xCU) -#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_SHIFT (2U) -#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_MASK) -#define XCVR_WOR_WOR_CTRL_SLOTS_USED_MASK (0x70U) -#define XCVR_WOR_WOR_CTRL_SLOTS_USED_SHIFT (4U) -#define XCVR_WOR_WOR_CTRL_SLOTS_USED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SLOTS_USED_SHIFT)) & XCVR_WOR_WOR_CTRL_SLOTS_USED_MASK) -#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_MASK (0x80U) -#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_SHIFT (7U) -#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_SHIFT)) & XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_MASK) -#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_MASK (0xF0000U) -#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_SHIFT (16U) -#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_SHIFT)) & XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_MASK) -#define XCVR_WOR_WOR_CTRL_WOR_RESUME_MASK (0x1000000U) -#define XCVR_WOR_WOR_CTRL_WOR_RESUME_SHIFT (24U) -#define XCVR_WOR_WOR_CTRL_WOR_RESUME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_RESUME_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_RESUME_MASK) -#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_MASK (0x2000000U) -#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_SHIFT (25U) -#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_MASK) -/*! @} */ - -/*! @name WOR_TIMEOUT - WAKE-ON-RADIO TIMEOUT REGISTER */ -/*! @{ */ -#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK (0xFFFFU) -#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT (0U) -#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK) -#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK (0xFF0000U) -#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT (16U) -#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK) -#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_MASK (0xFF000000U) -#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT (24U) -#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_MASK) -/*! @} */ - -/*! @name TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP 1 */ -/*! @{ */ -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_MASK (0xFFU) -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_SHIFT (0U) -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_MASK) -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_MASK (0xFFFFFF00U) -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_SHIFT (8U) -#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP1_TIMESTAMP1_SHIFT)) & XCVR_WOR_TIMESTAMP1_TIMESTAMP1_MASK) -/*! @} */ - -/*! @name TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP 2 */ -/*! @{ */ -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_MASK (0xFFU) -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_SHIFT (0U) -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_MASK) -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_MASK (0xFFFFFF00U) -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_SHIFT (8U) -#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP2_TIMESTAMP2_SHIFT)) & XCVR_WOR_TIMESTAMP2_TIMESTAMP2_MASK) -/*! @} */ - -/*! @name TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP 3 */ -/*! @{ */ -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_MASK (0xFFU) -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_SHIFT (0U) -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_MASK) -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_MASK (0xFFFFFF00U) -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_SHIFT (8U) -#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP3_TIMESTAMP3_SHIFT)) & XCVR_WOR_TIMESTAMP3_TIMESTAMP3_MASK) -/*! @} */ - -/*! @name WOR_STATUS - WAKE-ON-RADIO STATUS REGISTER */ -/*! @{ */ -#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_MASK (0x7U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_SHIFT (0U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_MASK) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_MASK (0x38U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_SHIFT (3U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_MASK) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_MASK (0x1C0U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_SHIFT (6U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_MASK) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_MASK (0xE00U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_SHIFT (9U) -#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_MASK) -#define XCVR_WOR_WOR_STATUS_SLOT_MASK (0x3000U) -#define XCVR_WOR_WOR_STATUS_SLOT_SHIFT (12U) -#define XCVR_WOR_WOR_STATUS_SLOT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_SLOT_SHIFT)) & XCVR_WOR_WOR_STATUS_SLOT_MASK) -#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_MASK (0x10000U) -#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_SHIFT (16U) -#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_MASK) -#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK (0x20000U) -#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT (17U) -#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK) -#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK (0x40000U) -#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT (18U) -#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK) -#define XCVR_WOR_WOR_STATUS_WOR_STATE_MASK (0xF00000U) -#define XCVR_WOR_WOR_STATUS_WOR_STATE_SHIFT (20U) -#define XCVR_WOR_WOR_STATUS_WOR_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_STATE_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_STATE_MASK) -/*! @} */ - -/*! @name WW_CTRL - WINDOW-WIDENING CONTROL REGISTER */ -/*! @{ */ -#define XCVR_WOR_WW_CTRL_WW_EN_MASK (0x1U) -#define XCVR_WOR_WW_CTRL_WW_EN_SHIFT (0U) -#define XCVR_WOR_WW_CTRL_WW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_EN_SHIFT)) & XCVR_WOR_WW_CTRL_WW_EN_MASK) -#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_MASK (0x2U) -#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT (1U) -#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT)) & XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_MASK) -#define XCVR_WOR_WW_CTRL_WW_NULL_MASK (0x4U) -#define XCVR_WOR_WW_CTRL_WW_NULL_SHIFT (2U) -#define XCVR_WOR_WW_CTRL_WW_NULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_NULL_SHIFT)) & XCVR_WOR_WW_CTRL_WW_NULL_MASK) -#define XCVR_WOR_WW_CTRL_WW_ADD_MASK (0x8U) -#define XCVR_WOR_WW_CTRL_WW_ADD_SHIFT (3U) -#define XCVR_WOR_WW_CTRL_WW_ADD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_ADD_SHIFT)) & XCVR_WOR_WW_CTRL_WW_ADD_MASK) -#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_MASK (0x1F00U) -#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT (8U) -#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT)) & XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_MASK) -#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_MASK (0x1F0000U) -#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT (16U) -#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT)) & XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_MASK) -#define XCVR_WOR_WW_CTRL_WW_INCREASE_MASK (0xFF000000U) -#define XCVR_WOR_WW_CTRL_WW_INCREASE_SHIFT (24U) -#define XCVR_WOR_WW_CTRL_WW_INCREASE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_INCREASE_SHIFT)) & XCVR_WOR_WW_CTRL_WW_INCREASE_MASK) -/*! @} */ - -/*! @name HOP_CTRL - FREQUENCY HOP CONTROL REGISTER */ -/*! @{ */ -#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_MASK (0x7U) -#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT (0U) -#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT)) & XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_MASK) -#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_MASK (0x7F00U) -#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT (8U) -#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT)) & XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_MASK) -#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK (0x8000U) -#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT (15U) -#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT)) & XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK) -#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK (0x7F0000U) -#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT (16U) -#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT)) & XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK) -/*! @} */ - -/*! @name SLOT0_DESC0 - SLOT 0 DESCRIPTOR (LSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_MASK (0xFFFFFFF0U) -#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT (4U) -#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT)) & XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_MASK) -/*! @} */ - -/*! @name SLOT0_DESC1 - SLOT 0 DESCRIPTOR (MSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_MASK (0x1FU) -#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT (0U) -#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT)) & XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_MASK) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK (0x7F00U) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT (8U) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT)) & XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK (0xFFFF0000U) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT (16U) -#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT)) & XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK) -/*! @} */ - -/*! @name SLOT1_DESC0 - SLOT 1 DESCRIPTOR (LSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_MASK (0xFFFFFFF0U) -#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT (4U) -#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT)) & XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_MASK) -/*! @} */ - -/*! @name SLOT1_DESC1 - SLOT 1 DESCRIPTOR (MSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_MASK (0x1FU) -#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT (0U) -#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT)) & XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_MASK) -/*! @} */ - -/*! @name SLOT2_DESC0 - SLOT 2 DESCRIPTOR (LSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_MASK (0xFFFFFFF0U) -#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT (4U) -#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT)) & XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_MASK) -/*! @} */ - -/*! @name SLOT2_DESC1 - SLOT 2 DESCRIPTOR (MSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_MASK (0x1FU) -#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT (0U) -#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT)) & XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_MASK) -/*! @} */ - -/*! @name SLOT3_DESC0 - SLOT 3 DESCRIPTOR (LSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_MASK (0xFFFFFFF0U) -#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT (4U) -#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT)) & XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_MASK) -/*! @} */ - -/*! @name SLOT3_DESC1 - SLOT 3 DESCRIPTOR (MSB) */ -/*! @{ */ -#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_MASK (0x1FU) -#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT (0U) -#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT)) & XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_WOR_Register_Masks */ - - -/* XCVR_WOR - Peripheral instance base addresses */ -/** Peripheral XCVR_WOR base address */ -#define XCVR_WOR_BASE (0x410304C0u) -/** Peripheral XCVR_WOR base pointer */ -#define XCVR_WOR ((XCVR_WOR_Type *)XCVR_WOR_BASE) -/** Array initializer of XCVR_WOR peripheral base addresses */ -#define XCVR_WOR_BASE_ADDRS { XCVR_WOR_BASE } -/** Array initializer of XCVR_WOR peripheral base pointers */ -#define XCVR_WOR_BASE_PTRS { XCVR_WOR } - -/*! - * @} - */ /* end of group XCVR_WOR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XCVR_ZBDEM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ZBDEM_Peripheral_Access_Layer XCVR_ZBDEM Peripheral Access Layer - * @{ - */ - -/** XCVR_ZBDEM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CORR_CTRL; /**< 802.15.4 DEMOD CORRELATOR CONTROL, offset: 0x0 */ - __IO uint32_t PN_TYPE; /**< 802.15.4 DEMOD PN TYPE, offset: 0x4 */ - __IO uint32_t PN_CODE; /**< 802.15.4 DEMOD PN CODE, offset: 0x8 */ - __IO uint32_t SYNC_CTRL; /**< 802.15.4 DEMOD SYMBOL SYNC CONTROL, offset: 0xC */ - __IO uint32_t CCA_LQI_SRC; /**< 802.15.4 CCA/LQI SOURCE, offset: 0x10 */ - __IO uint32_t FAD_LPPS_THR; /**< FAD CORRELATOR THRESHOLD, offset: 0x14 */ - __IO uint32_t ZBDEM_AFC; /**< 802.15.4 AFC STATUS, offset: 0x18 */ - __IO uint32_t CCA2_CTRL; /**< CCA MODE 2 CONTROL REGISTER, offset: 0x1C */ - __IO uint32_t CCA2_THRESH; /**< CCA MODE 2 CONTROL REGISTER, offset: 0x20 */ - __I uint32_t CCA2_STATUS; /**< CCA MODE 2 STATUS REGISTER, offset: 0x24 */ -} XCVR_ZBDEM_Type; - -/* ---------------------------------------------------------------------------- - -- XCVR_ZBDEM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XCVR_ZBDEM_Register_Masks XCVR_ZBDEM Register Masks - * @{ - */ - -/*! @name CORR_CTRL - 802.15.4 DEMOD CORRELATOR CONTROL */ -/*! @{ */ -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK (0xFFU) -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT (0U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_VT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK (0x700U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT (8U) -#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK (0x800U) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT (11U) -#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK) -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK (0x8000U) -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT (15U) -/*! ZBDEM_CLK_ON - Force 802.15.4 Demodulator Clock On - * 0b0..Normal Operation - * 0b1..Force 802.15.4 Demodulator Clock On (debug purposes only) - */ -#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK (0xFF0000U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT (16U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK (0xFF000000U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT (24U) -#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK) -/*! @} */ - -/*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */ -/*! @{ */ -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK (0x1U) -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT (0U) -#define XCVR_ZBDEM_PN_TYPE_PN_TYPE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT)) & XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK) -#define XCVR_ZBDEM_PN_TYPE_TX_INV_MASK (0x2U) -#define XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT (1U) -#define XCVR_ZBDEM_PN_TYPE_TX_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT)) & XCVR_ZBDEM_PN_TYPE_TX_INV_MASK) -/*! @} */ - -/*! @name PN_CODE - 802.15.4 DEMOD PN CODE */ -/*! @{ */ -#define XCVR_ZBDEM_PN_CODE_PN_LSB_MASK (0xFFFFU) -#define XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT (0U) -#define XCVR_ZBDEM_PN_CODE_PN_LSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_LSB_MASK) -#define XCVR_ZBDEM_PN_CODE_PN_MSB_MASK (0xFFFF0000U) -#define XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT (16U) -#define XCVR_ZBDEM_PN_CODE_PN_MSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_MSB_MASK) -/*! @} */ - -/*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */ -/*! @{ */ -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK (0x7U) -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT (0U) -#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK) -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK (0x8U) -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT (3U) -/*! TRACK_ENABLE - TRACK_ENABLE - * 0b0..symbol timing synchronization tracking disabled in Rx frontend - * 0b1..symbol timing synchronization tracking enabled in Rx frontend (default) - */ -#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK) -/*! @} */ - -/*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */ -/*! @{ */ -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK (0x1U) -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT (0U) -/*! CCA1_FROM_RX_DIG - Selects the Source of CCA1 (Clear Channel Assessment Mode 1) Information Provided to the 802.15.4 Link Layer - * 0b0..Use the CCA1 information computed internally in the 802.15.4 Demod - * 0b1..Use the CCA1 information computed by the RX Digital - */ -#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK (0x2U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT (1U) -/*! LQI_FROM_RX_DIG - Selects the Source of LQI (Link Quality Indicator) Information Provided to the 802.15.4 Link Layer - * 0b0..Use the LQI information computed internally in the 802.15.4 Demod - * 0b1..Use the LQI information computed by the RX Digital - */ -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK (0x4U) -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT (2U) -/*! LQI_START_AT_SFD - Select Start Point for LQI Computation - * 0b0..Start LQI computation at Preamble Detection (similar to previous NXP 802.15.4 products) - * 0b1..Start LQI computation at SFD (Start of Frame Delimiter) Detection - */ -#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK) -#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_MASK (0x8U) -#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_SHIFT (3U) -#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_MASK) -/*! @} */ - -/*! @name FAD_LPPS_THR - FAD CORRELATOR THRESHOLD */ -/*! @{ */ -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_MASK (0xFFU) -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_SHIFT (0U) -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_MASK) -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_MASK (0x7F00U) -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_SHIFT (8U) -#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_MASK) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_MASK (0x7F0000U) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_SHIFT (16U) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_MASK) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_MASK (0x7F000000U) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_SHIFT (24U) -#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_MASK) -/*! @} */ - -/*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */ -/*! @{ */ -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK (0x1U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT (0U) -/*! AFC_EN - AFC_EN - * 0b0..AFC is disabled - * 0b1..AFC is enabled - */ -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK) -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK (0x2U) -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT (1U) -/*! DCD_EN - DCD_EN - * 0b0..NCD Mode (default) - * 0b1..DCD Mode - */ -#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK (0x1F00U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT (8U) -#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK) -/*! @} */ - -/*! @name CCA2_CTRL - CCA MODE 2 CONTROL REGISTER */ -/*! @{ */ -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_MASK (0x3U) -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_SHIFT (0U) -/*! CCA2_INTERVAL - CCA Mode 2 Measurement Window Duration - * 0b00..64 us - * 0b01..128 us - * 0b10..256 us - * 0b11..512 us - */ -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_MASK) -#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_MASK (0x4U) -#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_SHIFT (2U) -/*! USE_DEMOD_CCA2 - Selects CCA Mode 2 Computation Engine - * 0b0..Use standalone (new) CCA Mode 2 Engine, decoupled from demodulator - * 0b1..Use 802.15.4 demodulator-based (legacy) CCA Mode 2 Engine (default) - */ -#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_MASK) -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_MASK (0xFF00U) -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_SHIFT (8U) -#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_MASK) -/*! @} */ - -/*! @name CCA2_THRESH - CCA MODE 2 CONTROL REGISTER */ -/*! @{ */ -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_MASK (0x3FFU) -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_SHIFT (0U) -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_SHIFT)) & XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_MASK) -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_MASK (0x3FF0000U) -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_SHIFT (16U) -#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_SHIFT)) & XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_MASK) -/*! @} */ - -/*! @name CCA2_STATUS - CCA MODE 2 STATUS REGISTER */ -/*! @{ */ -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_MASK (0x3FFU) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_SHIFT (0U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_MASK) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_MASK (0x400U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_SHIFT (10U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_MASK) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_MASK (0x800U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_SHIFT (11U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_MASK) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_MASK (0x3FF0000U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_SHIFT (16U) -#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XCVR_ZBDEM_Register_Masks */ - - -/* XCVR_ZBDEM - Peripheral instance base addresses */ -/** Peripheral XCVR_ZBDEM base address */ -#define XCVR_ZBDEM_BASE (0x41030480u) -/** Peripheral XCVR_ZBDEM base pointer */ -#define XCVR_ZBDEM ((XCVR_ZBDEM_Type *)XCVR_ZBDEM_BASE) -/** Array initializer of XCVR_ZBDEM peripheral base addresses */ -#define XCVR_ZBDEM_BASE_ADDRS { XCVR_ZBDEM_BASE } -/** Array initializer of XCVR_ZBDEM peripheral base pointers */ -#define XCVR_ZBDEM_BASE_PTRS { XCVR_ZBDEM } - -/*! - * @} - */ /* end of group XCVR_ZBDEM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XRDC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer - * @{ - */ - -/** XRDC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - uint8_t RESERVED_0[236]; - __I uint32_t HWCFG0; /**< Hardware Configuration Register 0, offset: 0xF0 */ - __I uint32_t HWCFG1; /**< Hardware Configuration Register 1, offset: 0xF4 */ - __I uint32_t HWCFG2; /**< Hardware Configuration Register 2, offset: 0xF8 */ - __I uint32_t HWCFG3; /**< Hardware Configuration Register 3, offset: 0xFC */ - __I uint8_t MDACFG[37]; /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ - uint8_t RESERVED_1[27]; - __I uint8_t MRCFG[2]; /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */ - uint8_t RESERVED_2[186]; - __IO uint32_t FDID; /**< Fault Domain ID, offset: 0x1FC */ - __I uint32_t DERRLOC[3]; /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_3[500]; - __IO uint32_t DERR_W[19][4]; /**< Domain Error Word0 Register..Domain Error Word3 Register, array offset: 0x400, array step: index*0x10, index2*0x4 */ - uint8_t RESERVED_4[464]; - __IO uint32_t PID[37]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ - uint8_t RESERVED_5[108]; - struct { /* offset: 0x800, array step: 0x20 */ - __IO uint32_t MDA_W[2]; /**< Master Domain Assignment, array offset: 0x800, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[24]; - } MDA[37]; - uint8_t RESERVED_6[864]; - __IO uint32_t PDAC_W[289][2]; /**< Peripheral Domain Access Control, array offset: 0x1000, array step: index*0x8, index2*0x4 */ - uint8_t RESERVED_7[1784]; - struct { /* offset: 0x2000, array step: 0x20 */ - __IO uint32_t MRGD_W[5]; /**< Memory Region Descriptor, array offset: 0x2000, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[12]; - } MRGD[24]; -} XRDC_Type; - -/* ---------------------------------------------------------------------------- - -- XRDC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XRDC_Register_Masks XRDC Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define XRDC_CR_GVLDM_MASK (0x1U) -#define XRDC_CR_GVLDM_SHIFT (0U) -/*! GVLDM - Global Valid MDACs(XRDC global enable/disable). - * 0b0..XRDC MDACs are disabled. - * 0b1..XRDC MDACs are enabled. - */ -#define XRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDM_SHIFT)) & XRDC_CR_GVLDM_MASK) -#define XRDC_CR_HRL_MASK (0x1EU) -#define XRDC_CR_HRL_SHIFT (1U) -#define XRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK) -#define XRDC_CR_VAW_MASK (0x100U) -#define XRDC_CR_VAW_SHIFT (8U) -/*! VAW - Virtualization aware - * 0b0..Implementation is not virtualization aware. - * 0b1..Implementation is virtualization aware. - */ -#define XRDC_CR_VAW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK) -#define XRDC_CR_GVLDP_MASK (0x4000U) -#define XRDC_CR_GVLDP_SHIFT (14U) -/*! GVLDP - Global Valid for PACs/MSCs - * 0b0..XRDC PACs/MSCs are disabled. - * 0b1..XRDC PACs/MSCs are enabled. - */ -#define XRDC_CR_GVLDP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDP_SHIFT)) & XRDC_CR_GVLDP_MASK) -#define XRDC_CR_GVLDC_MASK (0x8000U) -#define XRDC_CR_GVLDC_SHIFT (15U) -/*! GVLDC - Global Valid for MRCs - * 0b0..XRDC MRCs are disabled. - * 0b1..XRDC MRCs are enabled. - */ -#define XRDC_CR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDC_SHIFT)) & XRDC_CR_GVLDC_MASK) -#define XRDC_CR_LK1_MASK (0x40000000U) -#define XRDC_CR_LK1_SHIFT (30U) -/*! LK1 - 1-bit Lock - * 0b0..Register can be written by any secure privileged write. - * 0b1..Register is locked (read-only) until the next reset. - */ -#define XRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK) -/*! @} */ - -/*! @name HWCFG0 - Hardware Configuration Register 0 */ -/*! @{ */ -#define XRDC_HWCFG0_NDID_MASK (0xFFU) -#define XRDC_HWCFG0_NDID_SHIFT (0U) -#define XRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK) -#define XRDC_HWCFG0_NMSTR_MASK (0xFF00U) -#define XRDC_HWCFG0_NMSTR_SHIFT (8U) -#define XRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK) -#define XRDC_HWCFG0_NMRC_MASK (0xFF0000U) -#define XRDC_HWCFG0_NMRC_SHIFT (16U) -#define XRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK) -#define XRDC_HWCFG0_NPAC_MASK (0xF000000U) -#define XRDC_HWCFG0_NPAC_SHIFT (24U) -#define XRDC_HWCFG0_NPAC(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK) -#define XRDC_HWCFG0_MID_MASK (0xF0000000U) -#define XRDC_HWCFG0_MID_SHIFT (28U) -#define XRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK) -/*! @} */ - -/*! @name HWCFG1 - Hardware Configuration Register 1 */ -/*! @{ */ -#define XRDC_HWCFG1_DID_MASK (0xFU) -#define XRDC_HWCFG1_DID_SHIFT (0U) -#define XRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK) -/*! @} */ - -/*! @name HWCFG2 - Hardware Configuration Register 2 */ -/*! @{ */ -#define XRDC_HWCFG2_PIDP0_MASK (0x1U) -#define XRDC_HWCFG2_PIDP0_SHIFT (0U) -/*! PIDP0 - Process identifier - * 0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP0(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK) -#define XRDC_HWCFG2_PIDP1_MASK (0x2U) -#define XRDC_HWCFG2_PIDP1_SHIFT (1U) -/*! PIDP1 - Process identifier - * 0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK) -#define XRDC_HWCFG2_PIDP2_MASK (0x4U) -#define XRDC_HWCFG2_PIDP2_SHIFT (2U) -/*! PIDP2 - Process identifier - * 0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK) -#define XRDC_HWCFG2_PIDP3_MASK (0x8U) -#define XRDC_HWCFG2_PIDP3_SHIFT (3U) -/*! PIDP3 - Process identifier - * 0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP3(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK) -#define XRDC_HWCFG2_PIDP4_MASK (0x10U) -#define XRDC_HWCFG2_PIDP4_SHIFT (4U) -/*! PIDP4 - Process identifier - * 0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP4(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK) -#define XRDC_HWCFG2_PIDP5_MASK (0x20U) -#define XRDC_HWCFG2_PIDP5_SHIFT (5U) -/*! PIDP5 - Process identifier - * 0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP5(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK) -#define XRDC_HWCFG2_PIDP6_MASK (0x40U) -#define XRDC_HWCFG2_PIDP6_SHIFT (6U) -/*! PIDP6 - Process identifier - * 0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP6(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK) -#define XRDC_HWCFG2_PIDP7_MASK (0x80U) -#define XRDC_HWCFG2_PIDP7_SHIFT (7U) -/*! PIDP7 - Process identifier - * 0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP7(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK) -#define XRDC_HWCFG2_PIDP8_MASK (0x100U) -#define XRDC_HWCFG2_PIDP8_SHIFT (8U) -/*! PIDP8 - Process identifier - * 0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP8(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK) -#define XRDC_HWCFG2_PIDP9_MASK (0x200U) -#define XRDC_HWCFG2_PIDP9_SHIFT (9U) -/*! PIDP9 - Process identifier - * 0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP9(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK) -#define XRDC_HWCFG2_PIDP10_MASK (0x400U) -#define XRDC_HWCFG2_PIDP10_SHIFT (10U) -/*! PIDP10 - Process identifier - * 0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP10(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK) -#define XRDC_HWCFG2_PIDP11_MASK (0x800U) -#define XRDC_HWCFG2_PIDP11_SHIFT (11U) -/*! PIDP11 - Process identifier - * 0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP11(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK) -#define XRDC_HWCFG2_PIDP12_MASK (0x1000U) -#define XRDC_HWCFG2_PIDP12_SHIFT (12U) -/*! PIDP12 - Process identifier - * 0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP12(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK) -#define XRDC_HWCFG2_PIDP13_MASK (0x2000U) -#define XRDC_HWCFG2_PIDP13_SHIFT (13U) -/*! PIDP13 - Process identifier - * 0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP13(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK) -#define XRDC_HWCFG2_PIDP14_MASK (0x4000U) -#define XRDC_HWCFG2_PIDP14_SHIFT (14U) -/*! PIDP14 - Process identifier - * 0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP14(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK) -#define XRDC_HWCFG2_PIDP15_MASK (0x8000U) -#define XRDC_HWCFG2_PIDP15_SHIFT (15U) -/*! PIDP15 - Process identifier - * 0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP15(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK) -#define XRDC_HWCFG2_PIDP16_MASK (0x10000U) -#define XRDC_HWCFG2_PIDP16_SHIFT (16U) -/*! PIDP16 - Process identifier - * 0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP16(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK) -#define XRDC_HWCFG2_PIDP17_MASK (0x20000U) -#define XRDC_HWCFG2_PIDP17_SHIFT (17U) -/*! PIDP17 - Process identifier - * 0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP17(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK) -#define XRDC_HWCFG2_PIDP18_MASK (0x40000U) -#define XRDC_HWCFG2_PIDP18_SHIFT (18U) -/*! PIDP18 - Process identifier - * 0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP18(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK) -#define XRDC_HWCFG2_PIDP19_MASK (0x80000U) -#define XRDC_HWCFG2_PIDP19_SHIFT (19U) -/*! PIDP19 - Process identifier - * 0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP19(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK) -#define XRDC_HWCFG2_PIDP20_MASK (0x100000U) -#define XRDC_HWCFG2_PIDP20_SHIFT (20U) -/*! PIDP20 - Process identifier - * 0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP20(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK) -#define XRDC_HWCFG2_PIDP21_MASK (0x200000U) -#define XRDC_HWCFG2_PIDP21_SHIFT (21U) -/*! PIDP21 - Process identifier - * 0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP21(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK) -#define XRDC_HWCFG2_PIDP22_MASK (0x400000U) -#define XRDC_HWCFG2_PIDP22_SHIFT (22U) -/*! PIDP22 - Process identifier - * 0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP22(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK) -#define XRDC_HWCFG2_PIDP23_MASK (0x800000U) -#define XRDC_HWCFG2_PIDP23_SHIFT (23U) -/*! PIDP23 - Process identifier - * 0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP23(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK) -#define XRDC_HWCFG2_PIDP24_MASK (0x1000000U) -#define XRDC_HWCFG2_PIDP24_SHIFT (24U) -/*! PIDP24 - Process identifier - * 0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP24(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK) -#define XRDC_HWCFG2_PIDP25_MASK (0x2000000U) -#define XRDC_HWCFG2_PIDP25_SHIFT (25U) -/*! PIDP25 - Process identifier - * 0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP25(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK) -#define XRDC_HWCFG2_PIDP26_MASK (0x4000000U) -#define XRDC_HWCFG2_PIDP26_SHIFT (26U) -/*! PIDP26 - Process identifier - * 0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP26(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK) -#define XRDC_HWCFG2_PIDP27_MASK (0x8000000U) -#define XRDC_HWCFG2_PIDP27_SHIFT (27U) -/*! PIDP27 - Process identifier - * 0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP27(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK) -#define XRDC_HWCFG2_PIDP28_MASK (0x10000000U) -#define XRDC_HWCFG2_PIDP28_SHIFT (28U) -/*! PIDP28 - Process identifier - * 0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP28(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK) -#define XRDC_HWCFG2_PIDP29_MASK (0x20000000U) -#define XRDC_HWCFG2_PIDP29_SHIFT (29U) -/*! PIDP29 - Process identifier - * 0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP29(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK) -#define XRDC_HWCFG2_PIDP30_MASK (0x40000000U) -#define XRDC_HWCFG2_PIDP30_SHIFT (30U) -/*! PIDP30 - Process identifier - * 0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP30(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK) -#define XRDC_HWCFG2_PIDP31_MASK (0x80000000U) -#define XRDC_HWCFG2_PIDP31_SHIFT (31U) -/*! PIDP31 - Process identifier - * 0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. - * 0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic. - */ -#define XRDC_HWCFG2_PIDP31(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK) -/*! @} */ - -/*! @name HWCFG3 - Hardware Configuration Register 3 */ -/*! @{ */ -#define XRDC_HWCFG3_PIDPn_MASK (0xFFFFFFFFU) -#define XRDC_HWCFG3_PIDPn_SHIFT (0U) -#define XRDC_HWCFG3_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDPn_SHIFT)) & XRDC_HWCFG3_PIDPn_MASK) -/*! @} */ - -/*! @name MDACFG - Master Domain Assignment Configuration Register */ -/*! @{ */ -#define XRDC_MDACFG_NMDAR_MASK (0xFU) -#define XRDC_MDACFG_NMDAR_SHIFT (0U) -#define XRDC_MDACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK) -#define XRDC_MDACFG_NCM_MASK (0x80U) -#define XRDC_MDACFG_NCM_SHIFT (7U) -/*! NCM - Non-CPU Master - * 0b0..Bus master is a processor. - * 0b1..Bus master is a non-processor. - */ -#define XRDC_MDACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK) -/*! @} */ - -/* The count of XRDC_MDACFG */ -#define XRDC_MDACFG_COUNT (37U) - -/*! @name MRCFG - Memory Region Configuration Register */ -/*! @{ */ -#define XRDC_MRCFG_NMRGD_MASK (0x1FU) -#define XRDC_MRCFG_NMRGD_SHIFT (0U) -#define XRDC_MRCFG_NMRGD(x) (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK) -/*! @} */ - -/* The count of XRDC_MRCFG */ -#define XRDC_MRCFG_COUNT (2U) - -/*! @name FDID - Fault Domain ID */ -/*! @{ */ -#define XRDC_FDID_FDID_MASK (0xFU) -#define XRDC_FDID_FDID_SHIFT (0U) -#define XRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_FDID_FDID_SHIFT)) & XRDC_FDID_FDID_MASK) -/*! @} */ - -/*! @name DERRLOC - Domain Error Location Register */ -/*! @{ */ -#define XRDC_DERRLOC_MRCINST_MASK (0xFFFFU) -#define XRDC_DERRLOC_MRCINST_SHIFT (0U) -#define XRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK) -#define XRDC_DERRLOC_PACINST_MASK (0xF0000U) -#define XRDC_DERRLOC_PACINST_SHIFT (16U) -#define XRDC_DERRLOC_PACINST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK) -/*! @} */ - -/* The count of XRDC_DERRLOC */ -#define XRDC_DERRLOC_COUNT (3U) - -/*! @name DERR_W - Domain Error Word0 Register..Domain Error Word3 Register */ -/*! @{ */ -#define XRDC_DERR_W_EADDR_MASK (0xFFFFFFFFU) -#define XRDC_DERR_W_EADDR_SHIFT (0U) -#define XRDC_DERR_W_EADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK) -#define XRDC_DERR_W_EDID_MASK (0xFU) -#define XRDC_DERR_W_EDID_SHIFT (0U) -#define XRDC_DERR_W_EDID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK) -#define XRDC_DERR_W_EATR_MASK (0x700U) -#define XRDC_DERR_W_EATR_SHIFT (8U) -/*! EATR - Error attributes - * 0b000..Secure user mode, instruction fetch access. - * 0b001..Secure user mode, data access. - * 0b010..Secure privileged mode, instruction fetch access. - * 0b011..Secure privileged mode, data access. - * 0b100..Nonsecure user mode, instruction fetch access. - * 0b101..Nonsecure user mode, data access. - * 0b110..Nonsecure privileged mode, instruction fetch access. - * 0b111..Nonsecure privileged mode, data access. - */ -#define XRDC_DERR_W_EATR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK) -#define XRDC_DERR_W_ERW_MASK (0x800U) -#define XRDC_DERR_W_ERW_SHIFT (11U) -/*! ERW - Error read/write - * 0b0..Read access - * 0b1..Write access - */ -#define XRDC_DERR_W_ERW(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK) -#define XRDC_DERR_W_EPORT_MASK (0x7000000U) -#define XRDC_DERR_W_EPORT_SHIFT (24U) -#define XRDC_DERR_W_EPORT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK) -#define XRDC_DERR_W_EST_MASK (0xC0000000U) -#define XRDC_DERR_W_EST_SHIFT (30U) -/*! EST - Error state - * 0b00..No access violation has been detected. - * 0b01..No access violation has been detected. - * 0b10..A single access violation has been detected. - * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. - */ -#define XRDC_DERR_W_EST(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK) -#define XRDC_DERR_W_RECR_MASK (0xC0000000U) -#define XRDC_DERR_W_RECR_SHIFT (30U) -#define XRDC_DERR_W_RECR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK) -/*! @} */ - -/* The count of XRDC_DERR_W */ -#define XRDC_DERR_W_COUNT (19U) - -/* The count of XRDC_DERR_W */ -#define XRDC_DERR_W_COUNT2 (4U) - -/*! @name PID - Process Identifier */ -/*! @{ */ -#define XRDC_PID_PID_MASK (0x3FU) -#define XRDC_PID_PID_SHIFT (0U) -#define XRDC_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK) -#define XRDC_PID_SP4SM_MASK (0x8000000U) -#define XRDC_PID_SP4SM_SHIFT (27U) -#define XRDC_PID_SP4SM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_SP4SM_SHIFT)) & XRDC_PID_SP4SM_MASK) -#define XRDC_PID_TSM_MASK (0x10000000U) -#define XRDC_PID_TSM_SHIFT (28U) -#define XRDC_PID_TSM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK) -#define XRDC_PID_LK2_MASK (0x60000000U) -#define XRDC_PID_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Register can be written by any secure privileged write. - * 0b01..Register can be written by any secure privileged write. - * 0b10..Register can only be written by a secure privileged write from bus master m. - * 0b11..Register is locked (read-only) until the next reset. - */ -#define XRDC_PID_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK) -/*! @} */ - -/* The count of XRDC_PID */ -#define XRDC_PID_COUNT (37U) - -/*! @name MDA_W - Master Domain Assignment */ -/*! @{ */ -#define XRDC_MDA_W_DID_MASK (0xFU) -#define XRDC_MDA_W_DID_SHIFT (0U) -#define XRDC_MDA_W_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DID_SHIFT)) & XRDC_MDA_W_DID_MASK) -#define XRDC_MDA_W_DIDS_MASK (0x30U) -#define XRDC_MDA_W_DIDS_SHIFT (4U) -/*! DIDS - DID Select - * 0b00..Use MDAm[3:0] as the domain identifier. - * 0b01..Use the input DID as the domain identifier. - * 0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. - * 0b11..Reserved for future use. - */ -#define XRDC_MDA_W_DIDS(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDS_SHIFT)) & XRDC_MDA_W_DIDS_MASK) -#define XRDC_MDA_W_PA_MASK (0x30U) -#define XRDC_MDA_W_PA_SHIFT (4U) -/*! PA - Privileged attribute - * 0b00..Force the bus attribute for this master to user. - * 0b01..Force the bus attribute for this master to privileged. - * 0b10..Use the bus master's privileged/user attribute directly. - * 0b11..Use the bus master's privileged/user attribute directly. - */ -#define XRDC_MDA_W_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PA_SHIFT)) & XRDC_MDA_W_PA_MASK) -#define XRDC_MDA_W_PE_MASK (0xC0U) -#define XRDC_MDA_W_PE_SHIFT (6U) -/*! PE - Process identifier enable - * 0b00..No process identifier is included in the domain hit evaluation. - * 0b01..No process identifier is included in the domain hit evaluation. - * 0b10..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) - * 0b11..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) - */ -#define XRDC_MDA_W_PE(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PE_SHIFT)) & XRDC_MDA_W_PE_MASK) -#define XRDC_MDA_W_SA_MASK (0xC0U) -#define XRDC_MDA_W_SA_SHIFT (6U) -/*! SA - Secure attribute - * 0b00..Force the bus attribute for this master to secure. - * 0b01..Force the bus attribute for this master to nonsecure. - * 0b10..Use the bus master's secure/nonsecure attribute directly. - * 0b11..Use the bus master's secure/nonsecure attribute directly. - */ -#define XRDC_MDA_W_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_SA_SHIFT)) & XRDC_MDA_W_SA_MASK) -#define XRDC_MDA_W_DIDB_MASK (0x100U) -#define XRDC_MDA_W_DIDB_SHIFT (8U) -/*! DIDB - DID Bypass - * 0b0..Use MDAn[3:0] as the domain identifier. - * 0b1..Use the DID input as the domain identifier. - */ -#define XRDC_MDA_W_DIDB(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDB_SHIFT)) & XRDC_MDA_W_DIDB_MASK) -#define XRDC_MDA_W_PIDM_MASK (0x3F00U) -#define XRDC_MDA_W_PIDM_SHIFT (8U) -#define XRDC_MDA_W_PIDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PIDM_SHIFT)) & XRDC_MDA_W_PIDM_MASK) -#define XRDC_MDA_W_PID_MASK (0x3F0000U) -#define XRDC_MDA_W_PID_SHIFT (16U) -#define XRDC_MDA_W_PID(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PID_SHIFT)) & XRDC_MDA_W_PID_MASK) -#define XRDC_MDA_W_DFMT_MASK (0x20000000U) -#define XRDC_MDA_W_DFMT_SHIFT (29U) -/*! DFMT - Domain format - * 0b0..Processor-core domain assignment - * 0b1..Non-processor domain assignment - */ -#define XRDC_MDA_W_DFMT(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DFMT_SHIFT)) & XRDC_MDA_W_DFMT_MASK) -#define XRDC_MDA_W_LK1_MASK (0x40000000U) -#define XRDC_MDA_W_LK1_SHIFT (30U) -/*! LK1 - 1-bit Lock - * 0b0..Register can be written by any secure privileged write. - * 0b1..Register is locked (read-only) until the next reset. - */ -#define XRDC_MDA_W_LK1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_LK1_SHIFT)) & XRDC_MDA_W_LK1_MASK) -#define XRDC_MDA_W_VLD_MASK (0x80000000U) -#define XRDC_MDA_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The Wr domain assignment is invalid. - * 0b1..The Wr domain assignment is valid. - */ -#define XRDC_MDA_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_VLD_SHIFT)) & XRDC_MDA_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_MDA_W */ -#define XRDC_MDA_W_COUNT (37U) - -/* The count of XRDC_MDA_W */ -#define XRDC_MDA_W_COUNT2 (2U) - -/*! @name PDAC_W - Peripheral Domain Access Control */ -/*! @{ */ -#define XRDC_PDAC_W_D0ACP_MASK (0x7U) -#define XRDC_PDAC_W_D0ACP_SHIFT (0U) -#define XRDC_PDAC_W_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK) -#define XRDC_PDAC_W_D1ACP_MASK (0x38U) -#define XRDC_PDAC_W_D1ACP_SHIFT (3U) -#define XRDC_PDAC_W_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK) -#define XRDC_PDAC_W_D2ACP_MASK (0x1C0U) -#define XRDC_PDAC_W_D2ACP_SHIFT (6U) -#define XRDC_PDAC_W_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK) -#define XRDC_PDAC_W_EAL_MASK (0x3000000U) -#define XRDC_PDAC_W_EAL_SHIFT (24U) -/*! EAL - Exclusive Access Lock - * 0b00..Lock disabled - * 0b01..Lock disabled until next reset - * 0b10..Lock enabled, lock state = available - * 0b11..Lock enabled, lock state = not available - */ -#define XRDC_PDAC_W_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EAL_SHIFT)) & XRDC_PDAC_W_EAL_MASK) -#define XRDC_PDAC_W_EALO_MASK (0xF000000U) -#define XRDC_PDAC_W_EALO_SHIFT (24U) -#define XRDC_PDAC_W_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EALO_SHIFT)) & XRDC_PDAC_W_EALO_MASK) -#define XRDC_PDAC_W_LK2_MASK (0x60000000U) -#define XRDC_PDAC_W_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Entire PDACs can be written. - * 0b01..Entire PDACs can be written. - * 0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written. - * 0b11..PDACs is locked (read-only) until the next reset. - */ -#define XRDC_PDAC_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK) -#define XRDC_PDAC_W_VLD_MASK (0x80000000U) -#define XRDC_PDAC_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The PDACs assignment is invalid. - * 0b1..The PDACs assignment is valid. - */ -#define XRDC_PDAC_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_PDAC_W */ -#define XRDC_PDAC_W_COUNT (289U) - -/* The count of XRDC_PDAC_W */ -#define XRDC_PDAC_W_COUNT2 (2U) - -/*! @name MRGD_W - Memory Region Descriptor */ -/*! @{ */ -#define XRDC_MRGD_W_ACCSET1_MASK (0xFFFU) -#define XRDC_MRGD_W_ACCSET1_SHIFT (0U) -#define XRDC_MRGD_W_ACCSET1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET1_SHIFT)) & XRDC_MRGD_W_ACCSET1_MASK) -#define XRDC_MRGD_W_D0SEL_MASK (0x7U) -#define XRDC_MRGD_W_D0SEL_SHIFT (0U) -#define XRDC_MRGD_W_D0SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0SEL_SHIFT)) & XRDC_MRGD_W_D0SEL_MASK) -#define XRDC_MRGD_W_D1SEL_MASK (0x38U) -#define XRDC_MRGD_W_D1SEL_SHIFT (3U) -#define XRDC_MRGD_W_D1SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1SEL_SHIFT)) & XRDC_MRGD_W_D1SEL_MASK) -#define XRDC_MRGD_W_ENDADDR_MASK (0xFFFFFFE0U) -#define XRDC_MRGD_W_ENDADDR_SHIFT (5U) -#define XRDC_MRGD_W_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ENDADDR_SHIFT)) & XRDC_MRGD_W_ENDADDR_MASK) -#define XRDC_MRGD_W_SRTADDR_MASK (0xFFFFFFE0U) -#define XRDC_MRGD_W_SRTADDR_SHIFT (5U) -#define XRDC_MRGD_W_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRTADDR_SHIFT)) & XRDC_MRGD_W_SRTADDR_MASK) -#define XRDC_MRGD_W_D2SEL_MASK (0x1C0U) -#define XRDC_MRGD_W_D2SEL_SHIFT (6U) -#define XRDC_MRGD_W_D2SEL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2SEL_SHIFT)) & XRDC_MRGD_W_D2SEL_MASK) -#define XRDC_MRGD_W_LKAS1_MASK (0x1000U) -#define XRDC_MRGD_W_LKAS1_SHIFT (12U) -/*! LKAS1 - Lock ACCSET1 - * 0b0..Writes to ACCSET1 affect lesser modes - * 0b1..ACCSET1 cannot be modified - */ -#define XRDC_MRGD_W_LKAS1(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS1_SHIFT)) & XRDC_MRGD_W_LKAS1_MASK) -#define XRDC_MRGD_W_ACCSET2_MASK (0xFFF0000U) -#define XRDC_MRGD_W_ACCSET2_SHIFT (16U) -#define XRDC_MRGD_W_ACCSET2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET2_SHIFT)) & XRDC_MRGD_W_ACCSET2_MASK) -#define XRDC_MRGD_W_EAL_MASK (0x3000000U) -#define XRDC_MRGD_W_EAL_SHIFT (24U) -/*! EAL - Exclusive Access Lock - * 0b00..Lock disabled - * 0b01..Lock disabled until next reset - * 0b10..Lock enabled, lock state = available - * 0b11..Lock enabled, lock state = not available - */ -#define XRDC_MRGD_W_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EAL_SHIFT)) & XRDC_MRGD_W_EAL_MASK) -#define XRDC_MRGD_W_EALO_MASK (0xF000000U) -#define XRDC_MRGD_W_EALO_SHIFT (24U) -#define XRDC_MRGD_W_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EALO_SHIFT)) & XRDC_MRGD_W_EALO_MASK) -#define XRDC_MRGD_W_LKAS2_MASK (0x10000000U) -#define XRDC_MRGD_W_LKAS2_SHIFT (28U) -/*! LKAS2 - Lock ACCSET2 - * 0b0..Writes to ACCSET2 affect lesser modes - * 0b1..ACCSET2 cannot be modified - */ -#define XRDC_MRGD_W_LKAS2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS2_SHIFT)) & XRDC_MRGD_W_LKAS2_MASK) -#define XRDC_MRGD_W_LK2_MASK (0x60000000U) -#define XRDC_MRGD_W_LK2_SHIFT (29U) -/*! LK2 - Lock - * 0b00..Entire MRGDn can be written. - * 0b01..Entire MRGDn can be written. - * 0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written. - * 0b11..MRGDn is locked (read-only) until the next reset. - */ -#define XRDC_MRGD_W_LK2(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK) -#define XRDC_MRGD_W_CR_MASK (0x80000000U) -#define XRDC_MRGD_W_CR_SHIFT (31U) -#define XRDC_MRGD_W_CR(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_CR_SHIFT)) & XRDC_MRGD_W_CR_MASK) -#define XRDC_MRGD_W_VLD_MASK (0x80000000U) -#define XRDC_MRGD_W_VLD_SHIFT (31U) -/*! VLD - Valid - * 0b0..The MRGDn assignment is invalid. - * 0b1..The MRGDn assignment is valid. - */ -#define XRDC_MRGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK) -/*! @} */ - -/* The count of XRDC_MRGD_W */ -#define XRDC_MRGD_W_COUNT (24U) - -/* The count of XRDC_MRGD_W */ -#define XRDC_MRGD_W_COUNT2 (5U) - - -/*! - * @} - */ /* end of group XRDC_Register_Masks */ - - -/* XRDC - Peripheral instance base addresses */ -/** Peripheral XRDC base address */ -#define XRDC_BASE (0x40014000u) -/** Peripheral XRDC base pointer */ -#define XRDC ((XRDC_Type *)XRDC_BASE) -/** Array initializer of XRDC peripheral base addresses */ -#define XRDC_BASE_ADDRS { XRDC_BASE } -/** Array initializer of XRDC peripheral base pointers */ -#define XRDC_BASE_PTRS { XRDC } - -/*! - * @} - */ /* end of group XRDC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ZLL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ZLL_Peripheral_Access_Layer ZLL Peripheral Access Layer - * @{ - */ - -/** ZLL - Register Layout Typedef */ -typedef struct { - __IO uint32_t IRQSTS; /**< INTERRUPT REQUEST STATUS, offset: 0x0 */ - __IO uint32_t PHY_CTRL; /**< PHY CONTROL, offset: 0x4 */ - __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x8 */ - __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0xC */ - __IO uint32_t T1CMP; /**< T1 COMPARE, offset: 0x10 */ - __IO uint32_t T2CMP; /**< T2 COMPARE, offset: 0x14 */ - __IO uint32_t T2PRIMECMP; /**< T2 PRIME COMPARE, offset: 0x18 */ - __IO uint32_t T3CMP; /**< T3 COMPARE, offset: 0x1C */ - __IO uint32_t T4CMP; /**< T4 COMPARE, offset: 0x20 */ - __IO uint32_t PA_PWR; /**< PA POWER, offset: 0x24 */ - __IO uint32_t CHANNEL_NUM0; /**< CHANNEL NUMBER 0, offset: 0x28 */ - __I uint32_t LQI_AND_RSSI; /**< LQI AND RSSI, offset: 0x2C */ - __IO uint32_t MACSHORTADDRS0; /**< MAC SHORT ADDRESS 0, offset: 0x30 */ - __IO uint32_t MACLONGADDRS0_LSB; /**< MAC LONG ADDRESS 0 LSB, offset: 0x34 */ - __IO uint32_t MACLONGADDRS0_MSB; /**< MAC LONG ADDRESS 0 MSB, offset: 0x38 */ - __IO uint32_t RX_FRAME_FILTER; /**< RECEIVE FRAME FILTER, offset: 0x3C */ - __IO uint32_t CCA_LQI_CTRL; /**< CCA AND LQI CONTROL, offset: 0x40 */ - __IO uint32_t CCA2_CTRL; /**< CCA2 CONTROL, offset: 0x44 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x4C */ - __IO uint32_t BSM_CTRL; /**< BSM CONTROL, offset: 0x50 */ - __IO uint32_t MACSHORTADDRS1; /**< MAC SHORT ADDRESS FOR PAN1, offset: 0x54 */ - __IO uint32_t MACLONGADDRS1_LSB; /**< MAC LONG ADDRESS 1 LSB, offset: 0x58 */ - __IO uint32_t MACLONGADDRS1_MSB; /**< MAC LONG ADDRESS 1 MSB, offset: 0x5C */ - __IO uint32_t DUAL_PAN_CTRL; /**< DUAL PAN CONTROL, offset: 0x60 */ - __IO uint32_t CHANNEL_NUM1; /**< CHANNEL NUMBER 1, offset: 0x64 */ - __IO uint32_t SAM_CTRL; /**< SAM CONTROL, offset: 0x68 */ - __IO uint32_t SAM_TABLE; /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0x6C */ - __I uint32_t SAM_MATCH; /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0x70 */ - __I uint32_t SAM_FREE_IDX; /**< SAM FREE INDEX, offset: 0x74 */ - __IO uint32_t SEQ_CTRL_STS; /**< SEQUENCE CONTROL AND STATUS, offset: 0x78 */ - __IO uint32_t ACKDELAY; /**< ACK DELAY, offset: 0x7C */ - __IO uint32_t FILTERFAIL_CODE; /**< FILTER FAIL CODE, offset: 0x80 */ - __IO uint32_t RX_WTR_MARK; /**< RECEIVE WATER MARK, offset: 0x84 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SLOT_PRELOAD; /**< SLOT PRELOAD, offset: 0x8C */ - __I uint32_t SEQ_STATE; /**< 802.15.4 SEQUENCE STATE, offset: 0x90 */ - __IO uint32_t TMR_PRESCALE; /**< TIMER PRESCALER, offset: 0x94 */ - __IO uint32_t LENIENCY_LSB; /**< LENIENCY LSB, offset: 0x98 */ - __IO uint32_t LENIENCY_MSB; /**< LENIENCY MSB, offset: 0x9C */ - __I uint32_t PART_ID; /**< PART ID, offset: 0xA0 */ - uint8_t RESERVED_2[92]; - __IO uint16_t PKT_BUFFER_TX[64]; /**< Packet Buffer TX, array offset: 0x100, array step: 0x2 */ - __IO uint16_t PKT_BUFFER_RX[64]; /**< Packet Buffer RX, array offset: 0x180, array step: 0x2 */ -} ZLL_Type; - -/* ---------------------------------------------------------------------------- - -- ZLL Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ZLL_Register_Masks ZLL Register Masks - * @{ - */ - -/*! @name IRQSTS - INTERRUPT REQUEST STATUS */ -/*! @{ */ -#define ZLL_IRQSTS_SEQIRQ_MASK (0x1U) -#define ZLL_IRQSTS_SEQIRQ_SHIFT (0U) -/*! SEQIRQ - Sequencer IRQ - * 0b0..A Sequencer Interrupt has not occurred - * 0b1..A Sequencer Interrupt has occurred - */ -#define ZLL_IRQSTS_SEQIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SEQIRQ_SHIFT)) & ZLL_IRQSTS_SEQIRQ_MASK) -#define ZLL_IRQSTS_TXIRQ_MASK (0x2U) -#define ZLL_IRQSTS_TXIRQ_SHIFT (1U) -/*! TXIRQ - TX IRQ - * 0b0..A TX Interrupt has not occurred - * 0b1..A TX Interrupt has occurred - */ -#define ZLL_IRQSTS_TXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TXIRQ_SHIFT)) & ZLL_IRQSTS_TXIRQ_MASK) -#define ZLL_IRQSTS_RXIRQ_MASK (0x4U) -#define ZLL_IRQSTS_RXIRQ_SHIFT (2U) -/*! RXIRQ - RX IRQ - * 0b0..A RX Interrupt has not occurred - * 0b1..A RX Interrupt has occurred - */ -#define ZLL_IRQSTS_RXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXIRQ_SHIFT)) & ZLL_IRQSTS_RXIRQ_MASK) -#define ZLL_IRQSTS_CCAIRQ_MASK (0x8U) -#define ZLL_IRQSTS_CCAIRQ_SHIFT (3U) -/*! CCAIRQ - CCA IRQ - * 0b0..A CCA Interrupt has not occurred - * 0b1..A CCA Interrupt has occurred - */ -#define ZLL_IRQSTS_CCAIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCAIRQ_SHIFT)) & ZLL_IRQSTS_CCAIRQ_MASK) -#define ZLL_IRQSTS_RXWTRMRKIRQ_MASK (0x10U) -#define ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT (4U) -/*! RXWTRMRKIRQ - Receive Watermark IRQ - * 0b0..A Receive Watermark Interrupt has not occurred - * 0b1..A Receive Watermark Interrupt has occurred - */ -#define ZLL_IRQSTS_RXWTRMRKIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) -#define ZLL_IRQSTS_FILTERFAIL_IRQ_MASK (0x20U) -#define ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT (5U) -/*! FILTERFAIL_IRQ - Filter Fail IRQ - * 0b0..A Filter Fail Interrupt has not occurred - * 0b1..A Filter Fail Interrupt has occurred - */ -#define ZLL_IRQSTS_FILTERFAIL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK (0x40U) -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT (6U) -/*! PLL_UNLOCK_IRQ - PLL Unlock IRQ - * 0b0..A PLL Unlock Interrupt has not occurred - * 0b1..A PLL Unlock Interrupt has occurred - */ -#define ZLL_IRQSTS_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK) -#define ZLL_IRQSTS_RX_FRM_PEND_MASK (0x80U) -#define ZLL_IRQSTS_RX_FRM_PEND_SHIFT (7U) -#define ZLL_IRQSTS_RX_FRM_PEND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRM_PEND_SHIFT)) & ZLL_IRQSTS_RX_FRM_PEND_MASK) -#define ZLL_IRQSTS_WAKE_IRQ_MASK (0x100U) -#define ZLL_IRQSTS_WAKE_IRQ_SHIFT (8U) -/*! WAKE_IRQ - WAKE Interrupt Request - * 0b0..A Wake Interrupt has not occurred - * 0b1..A Wake Interrupt has occurred - */ -#define ZLL_IRQSTS_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_WAKE_IRQ_SHIFT)) & ZLL_IRQSTS_WAKE_IRQ_MASK) -#define ZLL_IRQSTS_TSM_IRQ_MASK (0x400U) -#define ZLL_IRQSTS_TSM_IRQ_SHIFT (10U) -/*! TSM_IRQ - TSM IRQ - * 0b0..A TSM Interrupt has not occurred - * 0b1..A TSM Interrupt has occurred - */ -#define ZLL_IRQSTS_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TSM_IRQ_SHIFT)) & ZLL_IRQSTS_TSM_IRQ_MASK) -#define ZLL_IRQSTS_ENH_PKT_STATUS_MASK (0x800U) -#define ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT (11U) -/*! ENH_PKT_STATUS - Enhanced Packet Status - * 0b0..The last packet received was neither 4e- nor 2015-compliant - * 0b1..The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits) - */ -#define ZLL_IRQSTS_ENH_PKT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT)) & ZLL_IRQSTS_ENH_PKT_STATUS_MASK) -#define ZLL_IRQSTS_PI_MASK (0x1000U) -#define ZLL_IRQSTS_PI_SHIFT (12U) -/*! PI - Poll Indication - * 0b0..the received packet was not a data request - * 0b1..the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not - */ -#define ZLL_IRQSTS_PI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PI_SHIFT)) & ZLL_IRQSTS_PI_MASK) -#define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) -#define ZLL_IRQSTS_SRCADDR_SHIFT (13U) -#define ZLL_IRQSTS_SRCADDR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK) -#define ZLL_IRQSTS_CCA_MASK (0x4000U) -#define ZLL_IRQSTS_CCA_SHIFT (14U) -/*! CCA - CCA Status - * 0b0..IDLE - * 0b1..BUSY - */ -#define ZLL_IRQSTS_CCA(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCA_SHIFT)) & ZLL_IRQSTS_CCA_MASK) -#define ZLL_IRQSTS_CRCVALID_MASK (0x8000U) -#define ZLL_IRQSTS_CRCVALID_SHIFT (15U) -/*! CRCVALID - CRC Valid Status - * 0b0..Rx FCS != calculated CRC (incorrect) - * 0b1..Rx FCS = calculated CRC (correct) - */ -#define ZLL_IRQSTS_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CRCVALID_SHIFT)) & ZLL_IRQSTS_CRCVALID_MASK) -#define ZLL_IRQSTS_TMR1IRQ_MASK (0x10000U) -#define ZLL_IRQSTS_TMR1IRQ_SHIFT (16U) -#define ZLL_IRQSTS_TMR1IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1IRQ_SHIFT)) & ZLL_IRQSTS_TMR1IRQ_MASK) -#define ZLL_IRQSTS_TMR2IRQ_MASK (0x20000U) -#define ZLL_IRQSTS_TMR2IRQ_SHIFT (17U) -#define ZLL_IRQSTS_TMR2IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2IRQ_SHIFT)) & ZLL_IRQSTS_TMR2IRQ_MASK) -#define ZLL_IRQSTS_TMR3IRQ_MASK (0x40000U) -#define ZLL_IRQSTS_TMR3IRQ_SHIFT (18U) -#define ZLL_IRQSTS_TMR3IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3IRQ_SHIFT)) & ZLL_IRQSTS_TMR3IRQ_MASK) -#define ZLL_IRQSTS_TMR4IRQ_MASK (0x80000U) -#define ZLL_IRQSTS_TMR4IRQ_SHIFT (19U) -#define ZLL_IRQSTS_TMR4IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4IRQ_SHIFT)) & ZLL_IRQSTS_TMR4IRQ_MASK) -#define ZLL_IRQSTS_TMR1MSK_MASK (0x100000U) -#define ZLL_IRQSTS_TMR1MSK_SHIFT (20U) -/*! TMR1MSK - Timer Comperator 1 Interrupt Mask bit - * 0b0..allows interrupt when comparator matches event timer count - * 0b1..Interrupt generation is disabled, but a TMR1IRQ flag can be set - */ -#define ZLL_IRQSTS_TMR1MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1MSK_SHIFT)) & ZLL_IRQSTS_TMR1MSK_MASK) -#define ZLL_IRQSTS_TMR2MSK_MASK (0x200000U) -#define ZLL_IRQSTS_TMR2MSK_SHIFT (21U) -/*! TMR2MSK - Timer Comperator 2 Interrupt Mask bit - * 0b0..allows interrupt when comparator matches event timer count - * 0b1..Interrupt generation is disabled, but a TMR2IRQ flag can be set - */ -#define ZLL_IRQSTS_TMR2MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2MSK_SHIFT)) & ZLL_IRQSTS_TMR2MSK_MASK) -#define ZLL_IRQSTS_TMR3MSK_MASK (0x400000U) -#define ZLL_IRQSTS_TMR3MSK_SHIFT (22U) -/*! TMR3MSK - Timer Comperator 3 Interrupt Mask bit - * 0b0..allows interrupt when comparator matches event timer count - * 0b1..Interrupt generation is disabled, but a TMR3IRQ flag can be set - */ -#define ZLL_IRQSTS_TMR3MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3MSK_SHIFT)) & ZLL_IRQSTS_TMR3MSK_MASK) -#define ZLL_IRQSTS_TMR4MSK_MASK (0x800000U) -#define ZLL_IRQSTS_TMR4MSK_SHIFT (23U) -/*! TMR4MSK - Timer Comperator 4 Interrupt Mask bit - * 0b0..allows interrupt when comparator matches event timer count - * 0b1..Interrupt generation is disabled, but a TMR4IRQ flag can be set - */ -#define ZLL_IRQSTS_TMR4MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4MSK_SHIFT)) & ZLL_IRQSTS_TMR4MSK_MASK) -#define ZLL_IRQSTS_RX_FRAME_LENGTH_MASK (0x7F000000U) -#define ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT (24U) -#define ZLL_IRQSTS_RX_FRAME_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) -/*! @} */ - -/*! @name PHY_CTRL - PHY CONTROL */ -/*! @{ */ -#define ZLL_PHY_CTRL_XCVSEQ_MASK (0x7U) -#define ZLL_PHY_CTRL_XCVSEQ_SHIFT (0U) -/*! XCVSEQ - 802.15.4 Transceiver Sequence Selector - * 0b000..I (IDLE) - * 0b001..R (RECEIVE) - * 0b010..T (TRANSMIT) - * 0b011..C (CCA) - * 0b100..TR (TRANSMIT/RECEIVE) - * 0b101..CCCA (CONTINUOUS CCA) - * 0b110..Reserved - * 0b111..Reserved - */ -#define ZLL_PHY_CTRL_XCVSEQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_XCVSEQ_SHIFT)) & ZLL_PHY_CTRL_XCVSEQ_MASK) -#define ZLL_PHY_CTRL_AUTOACK_MASK (0x8U) -#define ZLL_PHY_CTRL_AUTOACK_SHIFT (3U) -/*! AUTOACK - Auto Acknowledge Enable - * 0b0..sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. - * 0b1..sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. - */ -#define ZLL_PHY_CTRL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_AUTOACK_SHIFT)) & ZLL_PHY_CTRL_AUTOACK_MASK) -#define ZLL_PHY_CTRL_RXACKRQD_MASK (0x10U) -#define ZLL_PHY_CTRL_RXACKRQD_SHIFT (4U) -/*! RXACKRQD - Receive Acknowledge Frame required - * 0b0..An ordinary receive frame (any type of frame) follows the transmit frame. - * 0b1..A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). - */ -#define ZLL_PHY_CTRL_RXACKRQD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXACKRQD_SHIFT)) & ZLL_PHY_CTRL_RXACKRQD_MASK) -#define ZLL_PHY_CTRL_CCABFRTX_MASK (0x20U) -#define ZLL_PHY_CTRL_CCABFRTX_SHIFT (5U) -/*! CCABFRTX - CCA Before TX - * 0b0..no CCA required, transmit operation begins immediately. - * 0b1..at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). - */ -#define ZLL_PHY_CTRL_CCABFRTX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCABFRTX_SHIFT)) & ZLL_PHY_CTRL_CCABFRTX_MASK) -#define ZLL_PHY_CTRL_SLOTTED_MASK (0x40U) -#define ZLL_PHY_CTRL_SLOTTED_SHIFT (6U) -#define ZLL_PHY_CTRL_SLOTTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SLOTTED_SHIFT)) & ZLL_PHY_CTRL_SLOTTED_MASK) -#define ZLL_PHY_CTRL_TMRTRIGEN_MASK (0x80U) -#define ZLL_PHY_CTRL_TMRTRIGEN_SHIFT (7U) -/*! TMRTRIGEN - Timer2 Trigger Enable - * 0b0..programmed sequence initiates immediately upon write to XCVSEQ. - * 0b1..allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register). - */ -#define ZLL_PHY_CTRL_TMRTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)) & ZLL_PHY_CTRL_TMRTRIGEN_MASK) -#define ZLL_PHY_CTRL_SEQMSK_MASK (0x100U) -#define ZLL_PHY_CTRL_SEQMSK_SHIFT (8U) -/*! SEQMSK - Sequencer Interrupt Mask - * 0b0..allows completion of an autosequence to generate a zigbee interrupt - * 0b1..Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_SEQMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SEQMSK_SHIFT)) & ZLL_PHY_CTRL_SEQMSK_MASK) -#define ZLL_PHY_CTRL_TXMSK_MASK (0x200U) -#define ZLL_PHY_CTRL_TXMSK_SHIFT (9U) -/*! TXMSK - TX Interrupt Mask - * 0b0..allows completion of a TX operation to generate a zigbee interrupt - * 0b1..Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TXMSK_SHIFT)) & ZLL_PHY_CTRL_TXMSK_MASK) -#define ZLL_PHY_CTRL_RXMSK_MASK (0x400U) -#define ZLL_PHY_CTRL_RXMSK_SHIFT (10U) -/*! RXMSK - RX Interrupt Mask - * 0b0..allows completion of a RX operation to generate a zigbee interrupt - * 0b1..Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXMSK_SHIFT)) & ZLL_PHY_CTRL_RXMSK_MASK) -#define ZLL_PHY_CTRL_CCAMSK_MASK (0x800U) -#define ZLL_PHY_CTRL_CCAMSK_SHIFT (11U) -/*! CCAMSK - CCA Interrupt Mask - * 0b0..allows completion of a CCA operation to generate a zigbee interrupt - * 0b1..Completion of a CCA operation will set the CCA status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_CCAMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCAMSK_SHIFT)) & ZLL_PHY_CTRL_CCAMSK_MASK) -#define ZLL_PHY_CTRL_RX_WMRK_MSK_MASK (0x1000U) -#define ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT (12U) -/*! RX_WMRK_MSK - RX Watermark Interrupt Mask - * 0b0..allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt - * 0b1..A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_RX_WMRK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK) -#define ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK (0x2000U) -#define ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT (13U) -/*! FILTERFAIL_MSK - FilterFail Interrupt Mask - * 0b0..allows Packet Processor Filtering Failure to generate a zigbee interrupt - * 0b1..A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_FILTERFAIL_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK) -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK (0x4000U) -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT (14U) -/*! PLL_UNLOCK_MSK - PLL Unlock Interrupt Mask - * 0b0..allows PLL unlock event to generate a zigbee interrupt - * 0b1..A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK) -#define ZLL_PHY_CTRL_CRC_MSK_MASK (0x8000U) -#define ZLL_PHY_CTRL_CRC_MSK_SHIFT (15U) -/*! CRC_MSK - CRC Mask - * 0b0..sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received. - * 0b1..sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received. - */ -#define ZLL_PHY_CTRL_CRC_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CRC_MSK_SHIFT)) & ZLL_PHY_CTRL_CRC_MSK_MASK) -#define ZLL_PHY_CTRL_WAKE_MSK_MASK (0x10000U) -#define ZLL_PHY_CTRL_WAKE_MSK_SHIFT (16U) -/*! WAKE_MSK - * 0b0..Allows a wakeup from DSM to generate a zigbee interrupt - * 0b1..Wakeup from DSM will set the WAKE_IRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_WAKE_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_WAKE_MSK_SHIFT)) & ZLL_PHY_CTRL_WAKE_MSK_MASK) -#define ZLL_PHY_CTRL_TSM_MSK_MASK (0x40000U) -#define ZLL_PHY_CTRL_TSM_MSK_SHIFT (18U) -/*! TSM_MSK - * 0b0..allows assertion of a TSM interrupt to generate a zigbee interrupt - * 0b1..Assertion of a TSM interrupt will set the TSM_IRQ status bit, but a zigbee interrupt is not generated - */ -#define ZLL_PHY_CTRL_TSM_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TSM_MSK_SHIFT)) & ZLL_PHY_CTRL_TSM_MSK_MASK) -#define ZLL_PHY_CTRL_TMR1CMP_EN_MASK (0x100000U) -#define ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT (20U) -/*! TMR1CMP_EN - Timer 1 Compare Enable - * 0b0..Don't allow an Event Timer Match to T1CMP to set TMR1IRQ - * 0b1..Allow an Event Timer Match to T1CMP to set TMR1IRQ - */ -#define ZLL_PHY_CTRL_TMR1CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR2CMP_EN_MASK (0x200000U) -#define ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT (21U) -/*! TMR2CMP_EN - Timer 2 Compare Enable - * 0b0..Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ - * 0b1..Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ - */ -#define ZLL_PHY_CTRL_TMR2CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR3CMP_EN_MASK (0x400000U) -#define ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT (22U) -/*! TMR3CMP_EN - Timer 3 Compare Enable - * 0b0..Don't allow an Event Timer Match to T3CMP to set TMR3IRQ - * 0b1..Allow an Event Timer Match to T3CMP to set TMR3IRQ - */ -#define ZLL_PHY_CTRL_TMR3CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK) -#define ZLL_PHY_CTRL_TMR4CMP_EN_MASK (0x800000U) -#define ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT (23U) -/*! TMR4CMP_EN - Timer 4 Compare Enable - * 0b0..Don't allow an Event Timer Match to T4CMP to set TMR4IRQ - * 0b1..Allow an Event Timer Match to T4CMP to set TMR4IRQ - */ -#define ZLL_PHY_CTRL_TMR4CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK) -#define ZLL_PHY_CTRL_TC2PRIME_EN_MASK (0x1000000U) -#define ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT (24U) -/*! TC2PRIME_EN - Timer 2 Prime Compare Enable - * 0b0..Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ - * 0b1..Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ - */ -#define ZLL_PHY_CTRL_TC2PRIME_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK) -#define ZLL_PHY_CTRL_PROMISCUOUS_MASK (0x2000000U) -#define ZLL_PHY_CTRL_PROMISCUOUS_SHIFT (25U) -/*! PROMISCUOUS - Promiscuous Mode Enable - * 0b0..normal mode - * 0b1..all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed. - */ -#define ZLL_PHY_CTRL_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)) & ZLL_PHY_CTRL_PROMISCUOUS_MASK) -#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_MASK (0x4000000U) -#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_SHIFT (26U) -/*! TC3_POSTPONE_ON_SFD - Postpone TC3 Timeout On SFD Enable - * 0b0..TC3 Abort will occur on TMR3 timeout, regardless of rx_sfd_detect - * 0b1..TC3 Abort will be deferred on TMR3 timeout if rx_sfd_detect is asserted; otherwise the TC3 Abort will occur immediately - */ -#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_SHIFT)) & ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_MASK) -#define ZLL_PHY_CTRL_CCATYPE_MASK (0x18000000U) -#define ZLL_PHY_CTRL_CCATYPE_SHIFT (27U) -/*! CCATYPE - Clear Channel Assessment Type - * 0b00..ENERGY DETECT - * 0b01..CCA MODE 1 - * 0b10..CCA MODE 2 - * 0b11..CCA MODE 3 - */ -#define ZLL_PHY_CTRL_CCATYPE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCATYPE_SHIFT)) & ZLL_PHY_CTRL_CCATYPE_MASK) -#define ZLL_PHY_CTRL_PANCORDNTR0_MASK (0x20000000U) -#define ZLL_PHY_CTRL_PANCORDNTR0_SHIFT (29U) -#define ZLL_PHY_CTRL_PANCORDNTR0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)) & ZLL_PHY_CTRL_PANCORDNTR0_MASK) -#define ZLL_PHY_CTRL_TC3TMOUT_MASK (0x40000000U) -#define ZLL_PHY_CTRL_TC3TMOUT_SHIFT (30U) -/*! TC3TMOUT - TMR3 Timeout Enable - * 0b0..TMR3 is a software timer only - * 0b1..Enable TMR3 to abort Rx or CCCA operations. - */ -#define ZLL_PHY_CTRL_TC3TMOUT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT)) & ZLL_PHY_CTRL_TC3TMOUT_MASK) -#define ZLL_PHY_CTRL_TRCV_MSK_MASK (0x80000000U) -#define ZLL_PHY_CTRL_TRCV_MSK_SHIFT (31U) -/*! TRCV_MSK - Transceiver Global Interrupt Mask - * 0b0..Enable any unmasked interrupt source to assert zigbee interrupt - * 0b1..Mask all interrupt sources from asserting zigbee interrupt - */ -#define ZLL_PHY_CTRL_TRCV_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT)) & ZLL_PHY_CTRL_TRCV_MSK_MASK) -/*! @} */ - -/*! @name EVENT_TMR - EVENT TIMER */ -/*! @{ */ -#define ZLL_EVENT_TMR_EVENT_TMR_LD_MASK (0x1U) -#define ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT (0U) -#define ZLL_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_LD_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2U) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT (1U) -#define ZLL_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK (0xF0U) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT (4U) -#define ZLL_EVENT_TMR_EVENT_TMR_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK) -#define ZLL_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFF00U) -#define ZLL_EVENT_TMR_EVENT_TMR_SHIFT (8U) -#define ZLL_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_MASK) -/*! @} */ - -/*! @name TIMESTAMP - TIMESTAMP */ -/*! @{ */ -#define ZLL_TIMESTAMP_TIMESTAMP_FRAC_MASK (0xF0U) -#define ZLL_TIMESTAMP_TIMESTAMP_FRAC_SHIFT (4U) -#define ZLL_TIMESTAMP_TIMESTAMP_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_FRAC_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_FRAC_MASK) -#define ZLL_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFF00U) -#define ZLL_TIMESTAMP_TIMESTAMP_SHIFT (8U) -#define ZLL_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_MASK) -/*! @} */ - -/*! @name T1CMP - T1 COMPARE */ -/*! @{ */ -#define ZLL_T1CMP_T1CMP_MASK (0xFFFFFFU) -#define ZLL_T1CMP_T1CMP_SHIFT (0U) -#define ZLL_T1CMP_T1CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T1CMP_T1CMP_SHIFT)) & ZLL_T1CMP_T1CMP_MASK) -/*! @} */ - -/*! @name T2CMP - T2 COMPARE */ -/*! @{ */ -#define ZLL_T2CMP_T2CMP_MASK (0xFFFFFFU) -#define ZLL_T2CMP_T2CMP_SHIFT (0U) -#define ZLL_T2CMP_T2CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2CMP_T2CMP_SHIFT)) & ZLL_T2CMP_T2CMP_MASK) -/*! @} */ - -/*! @name T2PRIMECMP - T2 PRIME COMPARE */ -/*! @{ */ -#define ZLL_T2PRIMECMP_T2PRIMECMP_MASK (0xFFFFU) -#define ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT (0U) -#define ZLL_T2PRIMECMP_T2PRIMECMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK) -/*! @} */ - -/*! @name T3CMP - T3 COMPARE */ -/*! @{ */ -#define ZLL_T3CMP_T3CMP_MASK (0xFFFFFFU) -#define ZLL_T3CMP_T3CMP_SHIFT (0U) -#define ZLL_T3CMP_T3CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T3CMP_T3CMP_SHIFT)) & ZLL_T3CMP_T3CMP_MASK) -/*! @} */ - -/*! @name T4CMP - T4 COMPARE */ -/*! @{ */ -#define ZLL_T4CMP_T4CMP_MASK (0xFFFFFFU) -#define ZLL_T4CMP_T4CMP_SHIFT (0U) -#define ZLL_T4CMP_T4CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T4CMP_T4CMP_SHIFT)) & ZLL_T4CMP_T4CMP_MASK) -/*! @} */ - -/*! @name PA_PWR - PA POWER */ -/*! @{ */ -#define ZLL_PA_PWR_PA_PWR_MASK (0x3FU) -#define ZLL_PA_PWR_PA_PWR_SHIFT (0U) -#define ZLL_PA_PWR_PA_PWR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PA_PWR_PA_PWR_SHIFT)) & ZLL_PA_PWR_PA_PWR_MASK) -/*! @} */ - -/*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */ -/*! @{ */ -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK (0x7FU) -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT (0U) -#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK) -/*! @} */ - -/*! @name LQI_AND_RSSI - LQI AND RSSI */ -/*! @{ */ -#define ZLL_LQI_AND_RSSI_LQI_VALUE_MASK (0xFFU) -#define ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT (0U) -#define ZLL_LQI_AND_RSSI_LQI_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) -#define ZLL_LQI_AND_RSSI_RSSI_MASK (0xFF00U) -#define ZLL_LQI_AND_RSSI_RSSI_SHIFT (8U) -#define ZLL_LQI_AND_RSSI_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_RSSI_SHIFT)) & ZLL_LQI_AND_RSSI_RSSI_MASK) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK (0xFF0000U) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT (16U) -#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) -/*! @} */ - -/*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */ -/*! @{ */ -#define ZLL_MACSHORTADDRS0_MACPANID0_MASK (0xFFFFU) -#define ZLL_MACSHORTADDRS0_MACPANID0_SHIFT (0U) -#define ZLL_MACSHORTADDRS0_MACPANID0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)) & ZLL_MACSHORTADDRS0_MACPANID0_MASK) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK (0xFFFF0000U) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT (16U) -#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) -/*! @} */ - -/*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */ -/*! @{ */ -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U) -#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK) -/*! @} */ - -/*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */ -/*! @{ */ -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U) -#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK) -/*! @} */ - -/*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */ -/*! @{ */ -#define ZLL_RX_FRAME_FILTER_BEACON_FT_MASK (0x1U) -#define ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT (0U) -/*! BEACON_FT - Beacon Frame Type Enable - * 0b0..reject all Beacon frames - * 0b1..Beacon frame type enabled. - */ -#define ZLL_RX_FRAME_FILTER_BEACON_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK) -#define ZLL_RX_FRAME_FILTER_DATA_FT_MASK (0x2U) -#define ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT (1U) -/*! DATA_FT - Data Frame Type Enable - * 0b0..reject all Beacon frames - * 0b1..Data frame type enabled. - */ -#define ZLL_RX_FRAME_FILTER_DATA_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK) -#define ZLL_RX_FRAME_FILTER_ACK_FT_MASK (0x4U) -#define ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT (2U) -/*! ACK_FT - Ack Frame Type Enable - * 0b0..reject all Acknowledge frames - * 0b1..Acknowledge frame type enabled. - */ -#define ZLL_RX_FRAME_FILTER_ACK_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK) -#define ZLL_RX_FRAME_FILTER_CMD_FT_MASK (0x8U) -#define ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT (3U) -/*! CMD_FT - MAC Command Frame Type Enable - * 0b0..reject all MAC Command frames - * 0b1..MAC Command frame type enabled. - */ -#define ZLL_RX_FRAME_FILTER_CMD_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK) -#define ZLL_RX_FRAME_FILTER_LLDN_FT_MASK (0x10U) -#define ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT (4U) -/*! LLDN_FT - LLDN Frame Type Enable - * 0b0..reject all LLDN frames - * 0b1..LLDN frame type enabled (Frame Type 4). - */ -#define ZLL_RX_FRAME_FILTER_LLDN_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_FT_MASK) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U) -/*! MULTIPURPOSE_FT - Multipurpose Frame Type Enable - * 0b0..reject all Multipurpose frames - * 0b1..Multipurpose frame type enabled (Frame Type 5). - */ -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK) -#define ZLL_RX_FRAME_FILTER_NS_FT_MASK (0x40U) -#define ZLL_RX_FRAME_FILTER_NS_FT_SHIFT (6U) -/*! NS_FT - "Not Specified" Frame Type Enable - * 0b0..reject all "Not Specified" frames - * 0b1..Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type - */ -#define ZLL_RX_FRAME_FILTER_NS_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_NS_FT_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK (0x80U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT (7U) -/*! EXTENDED_FT - Extended Frame Type Enable - * 0b0..reject all Extended frames - * 0b1..Extended frame type enabled (Frame Type 7). - */ -#define ZLL_RX_FRAME_FILTER_EXTENDED_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK (0xF00U) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (8U) -#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK) -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK (0x4000U) -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT (14U) -/*! ACTIVE_PROMISCUOUS - Active Promiscuous - * 0b0..normal operation - * 0b1..Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode - */ -#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U) -/*! EXTENDED_FCS_CHK - Verify FCS on Frame Type Extended - * 0b0..Packet Processor will not check FCS for Frame Type EXTENDED (default) - * 0b1..Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED - */ -#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U) -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U) -/*! FV2_BEACON_RECD - Frame Version 2 Beacon Packet Received - * 0b0..The last packet received was not Frame Type Beacon with Frame Version 2 - * 0b1..The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets - */ -#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK (0x20000U) -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT (17U) -/*! FV2_DATA_RECD - Frame Version 2 Data Packet Received - * 0b0..The last packet received was not Frame Type Data with Frame Version 2 - * 0b1..The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets - */ -#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK (0x40000U) -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT (18U) -/*! FV2_ACK_RECD - Frame Version 2 Acknowledge Packet Received - * 0b0..The last packet received was not Frame Type Ack with Frame Version 2 - * 0b1..The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets - */ -#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK (0x80000U) -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT (19U) -/*! FV2_CMD_RECD - Frame Version 2 MAC Command Packet Received - * 0b0..The last packet received was not Frame Type MAC Command with Frame Version 2 - * 0b1..The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets - */ -#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK (0x100000U) -#define ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT (20U) -/*! LLDN_RECD - LLDN Packet Received - * 0b0..The last packet received was not Frame Type LLDN - * 0b1..The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets. - */ -#define ZLL_RX_FRAME_FILTER_LLDN_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U) -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U) -/*! MULTIPURPOSE_RECD - Multipurpose Packet Received - * 0b0..last packet received was not Frame Type MULTIPURPOSE - * 0b1..The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets. - */ -#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK) -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK (0x800000U) -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT (23U) -/*! EXTENDED_RECD - Extended Packet Received - * 0b0..The last packet received was not Frame Type EXTENDED - * 0b1..The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets. - */ -#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK) -/*! @} */ - -/*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */ -/*! @{ */ -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK (0xFFU) -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT (0U) -#define ZLL_CCA_LQI_CTRL_CCA1_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK (0xFF0000U) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT (16U) -#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) -#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK (0x1000000U) -#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT (24U) -/*! SIMUL_CCA_RX - Simultaneous CCA and Receive Enable - * 0b0..Packets can't be received during CCA measurement - * 0b1..Packet reception is enabled during CCA measurement if preamble and SFD are detected - */ -#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT)) & ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK) -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK (0x8000000U) -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT (27U) -/*! CCA3_AND_NOT_OR - CCA Mode 3 AND not OR - * 0b0..CCA1 or CCA2 - * 0b1..CCA1 and CCA2 - */ -#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK) -/*! @} */ - -/*! @name CCA2_CTRL - CCA2 CONTROL */ -/*! @{ */ -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK (0xFU) -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT (0U) -#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK (0x70U) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT (4U) -#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK (0xFF00U) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT (8U) -#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK) -/*! @} */ - -/*! @name DSM_CTRL - DSM CONTROL */ -/*! @{ */ -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_MASK (0x1U) -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_SHIFT (0U) -#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_SHIFT)) & ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_MASK) -/*! @} */ - -/*! @name BSM_CTRL - BSM CONTROL */ -/*! @{ */ -#define ZLL_BSM_CTRL_BSM_EN_MASK (0x1U) -#define ZLL_BSM_CTRL_BSM_EN_SHIFT (0U) -/*! BSM_EN - BSM Enable - * 0b0..802.15.4 Bit Streaming Mode Disabled - * 0b1..802.15.4 Bit Streaming Mode Enabled - */ -#define ZLL_BSM_CTRL_BSM_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_BSM_CTRL_BSM_EN_SHIFT)) & ZLL_BSM_CTRL_BSM_EN_MASK) -/*! @} */ - -/*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */ -/*! @{ */ -#define ZLL_MACSHORTADDRS1_MACPANID1_MASK (0xFFFFU) -#define ZLL_MACSHORTADDRS1_MACPANID1_SHIFT (0U) -#define ZLL_MACSHORTADDRS1_MACPANID1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)) & ZLL_MACSHORTADDRS1_MACPANID1_MASK) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK (0xFFFF0000U) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT (16U) -#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK) -/*! @} */ - -/*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */ -/*! @{ */ -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U) -#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK) -/*! @} */ - -/*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */ -/*! @{ */ -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU) -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U) -#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK) -/*! @} */ - -/*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */ -/*! @{ */ -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK (0x1U) -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT (0U) -/*! ACTIVE_NETWORK - Active Network Selector - * 0b0..Select PAN0 - * 0b1..Select PAN1 - */ -#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK (0x2U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT (1U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK (0x4U) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT (2U) -#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK) -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK (0x8U) -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT (3U) -/*! CURRENT_NETWORK - Indicates which PAN is currently selected by hardware - * 0b0..PAN0 is selected - * 0b1..PAN1 is selected - */ -#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK (0x10U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT (4U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK (0x20U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT (5U) -#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK (0xFF00U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT (8U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK (0x3F0000U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT (16U) -#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK (0x400000U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT (22U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK (0x800000U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT (23U) -#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK) -/*! @} */ - -/*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */ -/*! @{ */ -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK (0x7FU) -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT (0U) -#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK) -/*! @} */ - -/*! @name SAM_CTRL - SAM CONTROL */ -/*! @{ */ -#define ZLL_SAM_CTRL_SAP0_EN_MASK (0x1U) -#define ZLL_SAM_CTRL_SAP0_EN_SHIFT (0U) -/*! SAP0_EN - Enables SAP0 Partition of the SAM Table - * 0b0..Disables SAP0 Partition - * 0b1..Enables SAP0 Partition - */ -#define ZLL_SAM_CTRL_SAP0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP0_EN_SHIFT)) & ZLL_SAM_CTRL_SAP0_EN_MASK) -#define ZLL_SAM_CTRL_SAA0_EN_MASK (0x2U) -#define ZLL_SAM_CTRL_SAA0_EN_SHIFT (1U) -/*! SAA0_EN - Enables SAA0 Partition of the SAM Table - * 0b0..Disables SAA0 Partition - * 0b1..Enables SAA0 Partition - */ -#define ZLL_SAM_CTRL_SAA0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_EN_SHIFT)) & ZLL_SAM_CTRL_SAA0_EN_MASK) -#define ZLL_SAM_CTRL_SAP1_EN_MASK (0x4U) -#define ZLL_SAM_CTRL_SAP1_EN_SHIFT (2U) -/*! SAP1_EN - Enables SAP1 Partition of the SAM Table - * 0b0..Disables SAP1 Partition - * 0b1..Enables SAP1 Partition - */ -#define ZLL_SAM_CTRL_SAP1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_EN_SHIFT)) & ZLL_SAM_CTRL_SAP1_EN_MASK) -#define ZLL_SAM_CTRL_SAA1_EN_MASK (0x8U) -#define ZLL_SAM_CTRL_SAA1_EN_SHIFT (3U) -/*! SAA1_EN - Enables SAA1 Partition of the SAM Table - * 0b0..Disables SAA1 Partition - * 0b1..Enables SAA1 Partition - */ -#define ZLL_SAM_CTRL_SAA1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_EN_SHIFT)) & ZLL_SAM_CTRL_SAA1_EN_MASK) -#define ZLL_SAM_CTRL_SAA0_START_MASK (0xFF00U) -#define ZLL_SAM_CTRL_SAA0_START_SHIFT (8U) -#define ZLL_SAM_CTRL_SAA0_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_START_SHIFT)) & ZLL_SAM_CTRL_SAA0_START_MASK) -#define ZLL_SAM_CTRL_SAP1_START_MASK (0xFF0000U) -#define ZLL_SAM_CTRL_SAP1_START_SHIFT (16U) -#define ZLL_SAM_CTRL_SAP1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_START_SHIFT)) & ZLL_SAM_CTRL_SAP1_START_MASK) -#define ZLL_SAM_CTRL_SAA1_START_MASK (0xFF000000U) -#define ZLL_SAM_CTRL_SAA1_START_SHIFT (24U) -#define ZLL_SAM_CTRL_SAA1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_START_SHIFT)) & ZLL_SAM_CTRL_SAA1_START_MASK) -/*! @} */ - -/*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */ -/*! @{ */ -#define ZLL_SAM_TABLE_SAM_INDEX_MASK (0x7FU) -#define ZLL_SAM_TABLE_SAM_INDEX_SHIFT (0U) -#define ZLL_SAM_TABLE_SAM_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_WR_MASK (0x80U) -#define ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT (7U) -#define ZLL_SAM_TABLE_SAM_INDEX_WR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_WR_MASK) -#define ZLL_SAM_TABLE_SAM_CHECKSUM_MASK (0xFFFF00U) -#define ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT (8U) -#define ZLL_SAM_TABLE_SAM_CHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_INV_MASK (0x1000000U) -#define ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT (24U) -#define ZLL_SAM_TABLE_SAM_INDEX_INV(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_INV_MASK) -#define ZLL_SAM_TABLE_SAM_INDEX_EN_MASK (0x2000000U) -#define ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT (25U) -#define ZLL_SAM_TABLE_SAM_INDEX_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_EN_MASK) -#define ZLL_SAM_TABLE_ACK_FRM_PND_MASK (0x4000000U) -#define ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT (26U) -#define ZLL_SAM_TABLE_ACK_FRM_PND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK) -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK (0x8000000U) -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT (27U) -/*! ACK_FRM_PND_CTRL - Manual Control for AutoTxAck FramePending field - * 0b0..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware - * 0b1..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND - */ -#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK) -#define ZLL_SAM_TABLE_FIND_FREE_IDX_MASK (0x10000000U) -#define ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT (28U) -#define ZLL_SAM_TABLE_FIND_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & ZLL_SAM_TABLE_FIND_FREE_IDX_MASK) -#define ZLL_SAM_TABLE_INVALIDATE_ALL_MASK (0x20000000U) -#define ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT (29U) -#define ZLL_SAM_TABLE_INVALIDATE_ALL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & ZLL_SAM_TABLE_INVALIDATE_ALL_MASK) -#define ZLL_SAM_TABLE_SAM_BUSY_MASK (0x80000000U) -#define ZLL_SAM_TABLE_SAM_BUSY_SHIFT (31U) -#define ZLL_SAM_TABLE_SAM_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_BUSY_SHIFT)) & ZLL_SAM_TABLE_SAM_BUSY_MASK) -/*! @} */ - -/*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */ -/*! @{ */ -#define ZLL_SAM_MATCH_SAP0_MATCH_MASK (0x7FU) -#define ZLL_SAM_MATCH_SAP0_MATCH_SHIFT (0U) -#define ZLL_SAM_MATCH_SAP0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP0_MATCH_MASK) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK (0x80U) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT (7U) -#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK) -#define ZLL_SAM_MATCH_SAA0_MATCH_MASK (0x7F00U) -#define ZLL_SAM_MATCH_SAA0_MATCH_SHIFT (8U) -#define ZLL_SAM_MATCH_SAA0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA0_MATCH_MASK) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK (0x8000U) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT (15U) -#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK) -#define ZLL_SAM_MATCH_SAP1_MATCH_MASK (0x7F0000U) -#define ZLL_SAM_MATCH_SAP1_MATCH_SHIFT (16U) -#define ZLL_SAM_MATCH_SAP1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP1_MATCH_MASK) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK (0x800000U) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT (23U) -#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK) -#define ZLL_SAM_MATCH_SAA1_MATCH_MASK (0x7F000000U) -#define ZLL_SAM_MATCH_SAA1_MATCH_SHIFT (24U) -#define ZLL_SAM_MATCH_SAA1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA1_MATCH_MASK) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (0x80000000U) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT (31U) -#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK) -/*! @} */ - -/*! @name SAM_FREE_IDX - SAM FREE INDEX */ -/*! @{ */ -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK (0xFFU) -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U) -#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK (0xFF00U) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U) -#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK (0xFF0000U) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U) -#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK (0xFF000000U) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U) -#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK) -/*! @} */ - -/*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */ -/*! @{ */ -#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_MASK (0x2U) -#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_SHIFT (1U) -/*! FORCE_CLK_ON - Force On 802.15.4 phy_gck - * 0b0..Allow TSM to control 802.15.4 phy_gck, for minimum power consumption (default) - * 0b1..Force on 802.15.4 phy_gclk at all times, for debug purposes only - */ -#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_MASK) -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK (0x4U) -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT (2U) -#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK (0x8U) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT (3U) -#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK) -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK (0x10U) -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT (4U) -/*! LATCH_PREAMBLE - Stickiness Control for Preamble Detection - * 0b0..Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect - * 0b1..Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence - */ -#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK (0x20U) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT (5U) -#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK) -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK (0x40U) -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT (6U) -/*! FORCE_CRC_ERROR - Induce a CRC Error in Transmitted Packets - * 0b0..normal operation - * 0b1..Force the next transmitted packet to have a CRC error - */ -#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK) -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK (0x80U) -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT (7U) -/*! CONTINUOUS_EN - Enable Continuous TX or RX Mode - * 0b0..normal operation - * 0b1..Continuous TX or RX mode is enabled (depending on XCVSEQ setting). - */ -#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK (0x700U) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT (8U) -#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK (0x800U) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT (11U) -#define ZLL_SEQ_CTRL_STS_SEQ_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK (0x1000U) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT (12U) -#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK (0x2000U) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT (13U) -#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK) -#define ZLL_SEQ_CTRL_STS_RX_MODE_MASK (0x4000U) -#define ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT (14U) -#define ZLL_SEQ_CTRL_STS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK (0x8000U) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT (15U) -#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK (0x3F0000U) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT (16U) -#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK (0x1000000U) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT (24U) -#define ZLL_SEQ_CTRL_STS_SW_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK (0x2000000U) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT (25U) -#define ZLL_SEQ_CTRL_STS_TC3_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK (0x4000000U) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT (26U) -#define ZLL_SEQ_CTRL_STS_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) -#define ZLL_SEQ_CTRL_STS_EXT_ABORTED_MASK (0x8000000U) -#define ZLL_SEQ_CTRL_STS_EXT_ABORTED_SHIFT (27U) -#define ZLL_SEQ_CTRL_STS_EXT_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EXT_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_EXT_ABORTED_MASK) -/*! @} */ - -/*! @name ACKDELAY - ACK DELAY */ -/*! @{ */ -#define ZLL_ACKDELAY_ACKDELAY_MASK (0x3FU) -#define ZLL_ACKDELAY_ACKDELAY_SHIFT (0U) -#define ZLL_ACKDELAY_ACKDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_ACKDELAY_SHIFT)) & ZLL_ACKDELAY_ACKDELAY_MASK) -#define ZLL_ACKDELAY_TXDELAY_MASK (0x3F00U) -#define ZLL_ACKDELAY_TXDELAY_SHIFT (8U) -#define ZLL_ACKDELAY_TXDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_TXDELAY_SHIFT)) & ZLL_ACKDELAY_TXDELAY_MASK) -/*! @} */ - -/*! @name FILTERFAIL_CODE - FILTER FAIL CODE */ -/*! @{ */ -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK (0x3FFU) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT (0U) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x8000U) -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (15U) -/*! FILTERFAIL_PAN_SEL - PAN Selector for Filter Fail Code - * 0b0..FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0 - * 0b1..FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1 - */ -#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK) -/*! @} */ - -/*! @name RX_WTR_MARK - RECEIVE WATER MARK */ -/*! @{ */ -#define ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK (0xFFU) -#define ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT (0U) -#define ZLL_RX_WTR_MARK_RX_WTR_MARK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK) -/*! @} */ - -/*! @name SLOT_PRELOAD - SLOT PRELOAD */ -/*! @{ */ -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK (0xFFU) -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT (0U) -#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK) -/*! @} */ - -/*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */ -/*! @{ */ -#define ZLL_SEQ_STATE_SEQ_STATE_MASK (0x1FU) -#define ZLL_SEQ_STATE_SEQ_STATE_SHIFT (0U) -#define ZLL_SEQ_STATE_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SEQ_STATE_SHIFT)) & ZLL_SEQ_STATE_SEQ_STATE_MASK) -#define ZLL_SEQ_STATE_PREAMBLE_DET_MASK (0x100U) -#define ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT (8U) -#define ZLL_SEQ_STATE_PREAMBLE_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK) -#define ZLL_SEQ_STATE_SFD_DET_MASK (0x200U) -#define ZLL_SEQ_STATE_SFD_DET_SHIFT (9U) -#define ZLL_SEQ_STATE_SFD_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SFD_DET_SHIFT)) & ZLL_SEQ_STATE_SFD_DET_MASK) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK (0x400U) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT (10U) -#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK) -#define ZLL_SEQ_STATE_CRCVALID_MASK (0x800U) -#define ZLL_SEQ_STATE_CRCVALID_SHIFT (11U) -/*! CRCVALID - CRC Valid Indicator - * 0b0..Rx FCS != calculated CRC (incorrect) - * 0b1..Rx FCS = calculated CRC (correct) - */ -#define ZLL_SEQ_STATE_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CRCVALID_SHIFT)) & ZLL_SEQ_STATE_CRCVALID_MASK) -#define ZLL_SEQ_STATE_PLL_ABORT_MASK (0x1000U) -#define ZLL_SEQ_STATE_PLL_ABORT_SHIFT (12U) -#define ZLL_SEQ_STATE_PLL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORT_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORT_MASK) -#define ZLL_SEQ_STATE_PLL_ABORTED_MASK (0x2000U) -#define ZLL_SEQ_STATE_PLL_ABORTED_SHIFT (13U) -#define ZLL_SEQ_STATE_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORTED_MASK) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK (0xFF0000U) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT (16U) -#define ZLL_SEQ_STATE_RX_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK (0x3F000000U) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT (24U) -#define ZLL_SEQ_STATE_CCCA_BUSY_CNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK) -/*! @} */ - -/*! @name TMR_PRESCALE - TIMER PRESCALER */ -/*! @{ */ -#define ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK (0x7U) -#define ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT (0U) -/*! TMR_PRESCALE - Timer Prescaler - * 0b000..Reserved - * 0b001..Reserved - * 0b010..500kHz (33.55 S) - * 0b011..250kHz (67.11 S) - * 0b100..125kHz (134.22 S) - * 0b101..62.5kHz (268.44 S) -- default - * 0b110..31.25kHz (536.87 S) - * 0b111..15.625kHz (1073.74 S) - */ -#define ZLL_TMR_PRESCALE_TMR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) -/*! @} */ - -/*! @name LENIENCY_LSB - LENIENCY LSB */ -/*! @{ */ -#define ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK (0xFFFFFFFFU) -#define ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT (0U) -#define ZLL_LENIENCY_LSB_LENIENCY_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK) -/*! @} */ - -/*! @name LENIENCY_MSB - LENIENCY MSB */ -/*! @{ */ -#define ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK (0xFFU) -#define ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT (0U) -#define ZLL_LENIENCY_MSB_LENIENCY_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK) -/*! @} */ - -/*! @name PART_ID - PART ID */ -/*! @{ */ -#define ZLL_PART_ID_PART_ID_MASK (0xFFU) -#define ZLL_PART_ID_PART_ID_SHIFT (0U) -#define ZLL_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PART_ID_PART_ID_SHIFT)) & ZLL_PART_ID_PART_ID_MASK) -/*! @} */ - -/*! @name PKT_BUFFER_TX - Packet Buffer TX */ -/*! @{ */ -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK (0xFFFFU) -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT (0U) -#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT)) & ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK) -/*! @} */ - -/* The count of ZLL_PKT_BUFFER_TX */ -#define ZLL_PKT_BUFFER_TX_COUNT (64U) - -/*! @name PKT_BUFFER_RX - Packet Buffer RX */ -/*! @{ */ -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK (0xFFFFU) -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT (0U) -#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT)) & ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK) -/*! @} */ - -/* The count of ZLL_PKT_BUFFER_RX */ -#define ZLL_PKT_BUFFER_RX_COUNT (64U) - - -/*! - * @} - */ /* end of group ZLL_Register_Masks */ - - -/* ZLL - Peripheral instance base addresses */ -/** Peripheral ZLL base address */ -#define ZLL_BASE (0x41034000u) -/** Peripheral ZLL base pointer */ -#define ZLL ((ZLL_Type *)ZLL_BASE) -/** Array initializer of ZLL peripheral base addresses */ -#define ZLL_BASE_ADDRS { ZLL_BASE } -/** Array initializer of ZLL peripheral base pointers */ -#define ZLL_BASE_PTRS { ZLL } - -/*! - * @} - */ /* end of group ZLL_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -#define EVENT_UNIT EVENT1 -#define INTMUX INTMUX1 - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _RV32M1_ZERO_RISCY_H_ */ - diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h deleted file mode 100644 index e66424ca3046853cff627b7e717d2cfffd577011..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h +++ /dev/null @@ -1,1582 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2018-10-02 -** Build: b180815 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _RV32M1_zero_riscy_FEATURES_H_ -#define _RV32M1_zero_riscy_FEATURES_H_ - -/* SOC module features */ - -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (1) -/* @brief EVENT availability on the SoC. */ -#define FSL_FEATURE_SOC_EVENT_COUNT (1) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (1) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (1) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (1) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (5) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (1) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (1) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (2) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (1) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (2) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (1) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (2) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (3) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (4) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (1) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (1) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (1) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (2) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (5) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (1) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (2) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (2) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (1) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (4) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (2) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (1) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (1) -/* @brief USDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_USDHC_COUNT (1) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (1) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (1) - -/* LPADC module features */ - -/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) -/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ -#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) -/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1) -/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1) -/* @brief Has calibration (bitfield CFG[CALOFS]). */ -#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1) -/* @brief Has offset trim (register OFSTRIM). */ -#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) - -/* CRC module features */ - -/* @brief Has data register with name CRC */ -#define FSL_FEATURE_CRC_HAS_CRC_REG (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 8) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) -/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ -#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) - -/* EWM module features */ - -/* @brief Has clock select (register CLKCTRL). */ -#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) -/* @brief Has clock prescaler (register CLKPRESCALER). */ -#define FSL_FEATURE_EWM_HAS_PRESCALER (1) - -/* FB module features */ - -/* No feature definitions */ - -/* FLEXIO module features */ - -/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ -#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) -/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) -/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) -/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) -/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) -/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) -/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ -#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) -/* @brief Reset value of the FLEXIO_VERID register */ -#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) -/* @brief Reset value of the FLEXIO_PARAM register */ -#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808) - -/* FLASH module features */ - -/* @brief Current core ID. */ -#define FSL_FEATURE_FLASH_CURRENT_CORE_ID (1) -/* @brief Is of type FTFA. */ -#define FSL_FEATURE_FLASH_IS_FTFA (0) -/* @brief Is of type FTFE. */ -#define FSL_FEATURE_FLASH_IS_FTFE (1) -/* @brief Is of type FTFL. */ -#define FSL_FEATURE_FLASH_IS_FTFL (0) -/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) -/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) -/* @brief Has EEPROM region protection (register FEPROT). */ -#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) -/* @brief Has data flash region protection (register FDPROT). */ -#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) -/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ -#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) -/* @brief Has flash cache control in FMC module. */ -#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) -/* @brief Has flash cache control in MCM module. */ -#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) -/* @brief Has flash cache control in MSCM module. */ -#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1) -/* @brief Has prefetch speculation control in flash, such as kv5x. */ -#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) -/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for RV32M1 */ -#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1) -/* @brief P-Flash start address. */ -#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x01000000) -/* @brief P-Flash block count. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) -/* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) -/* @brief P-Flash sector size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) -/* @brief P-Flash write unit size. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) -/* @brief P-Flash data path width. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) -/* @brief P-Flash block swap feature. */ -#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) -/* @brief P-Flash protection region count. */ -#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16) -/* @brief Has multiple flash. */ -#define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1) -/* @brief Flash memory count. */ -#define FSL_FEATURE_FLASH_MEMORY_COUNT (2) -/* @brief P-Flash start address. */ -#define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x00000000) -/* @brief P-Flash block count. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (2) -/* @brief P-Flash block size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (524288) -/* @brief P-Flash sector size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (4096) -/* @brief P-Flash write unit size. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8) -/* @brief P-Flash data path width. */ -#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (16) -/* @brief P-Flash protection region count. */ -#define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (64) -/* @brief P-Flash block swap feature. */ -#define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (1) -/* @brief Has FlexNVM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) -/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) -/* @brief FlexNVM block count. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) -/* @brief FlexNVM block size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) -/* @brief FlexNVM sector size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) -/* @brief FlexNVM write unit size. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) -/* @brief FlexNVM data path width. */ -#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) -/* @brief Has FlexRAM memory. */ -#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) -/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ -#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000) -/* @brief FlexRAM size. */ -#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) -/* @brief Has 0x00 Read 1s Block command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) -/* @brief Flash 1 has 0x00 Read 1s Block command. */ -#define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (1) -/* @brief Has 0x01 Read 1s Section command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) -/* @brief Has 0x02 Program Check command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) -/* @brief Has 0x03 Read Resource command. */ -#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0) -/* @brief Has 0x06 Program Longword command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) -/* @brief Has 0x07 Program Phrase command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) -/* @brief Has 0x08 Erase Flash Block command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) -/* @brief Flash 1 has 0x08 Erase Flash Block command. */ -#define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (1) -/* @brief Has 0x09 Erase Flash Sector command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) -/* @brief Has 0x0B Program Section command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) -/* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */ -#define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1) -/* @brief Has 0x40 Read 1s All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) -/* @brief Has 0x41 Read Once command. */ -#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) -/* @brief Has 0x43 Program Once command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) -/* @brief Has 0x44 Erase All Blocks command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) -/* @brief Has 0x45 Verify Backdoor Access Key command. */ -#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) -/* @brief Has 0x46 Swap Control command. */ -#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) -/* @brief Flash 1 has 0x46 Swap Control command. */ -#define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (1) -/* @brief Has 0x49 Erase All Blocks Unsecure command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) -/* @brief Has 0x4A Read 1s All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x4B Erase All Execute-only Segments command. */ -#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) -/* @brief Has 0x80 Program Partition command. */ -#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) -/* @brief Has 0x81 Set FlexRAM Function command. */ -#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) -/* @brief P-Flash Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Program/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Program/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (16) -/* @brief P-Flash Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) -/* @brief P-Flash Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) -/* @brief P-Flash 1 Program check command address alignment. */ -#define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) -/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Erase sector command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Rrogram/Verify section command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Read resource command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM Program check command address alignment. */ -#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) -/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) -/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) -/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) -/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) -/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) -/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) -/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) -/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) -/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) -/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) -/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) -/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) -/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) -/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) -/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) -/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) -/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) -/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ -#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* SAI module features */ - -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ -#define FSL_FEATURE_SAI_FIFO_COUNT (8) -/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ -#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ -#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ -#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ -#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ -#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Interrupt source number */ -#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) -/* @brief Has register of MCR. */ -#define FSL_FEATURE_SAI_HAS_MCR (0) -/* @brief Has bit field MICS of the MCR register. */ -#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) -/* @brief Has register of MDR */ -#define FSL_FEATURE_SAI_HAS_MDR (0) -/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ -#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) - -/* INTMUX module features */ - -/* @brief Number of INTMUX channels (related to number of register CHn_CSR). */ -#define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8) -/* @brief Number of INTMUX IRQ source. */ -#define FSL_FEATURE_INTMUX_IRQ_COUNT (32) -/* @brief The start IRQ index of first INTMUX source IRQ. */ -#define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32) -/* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */ -#define FSL_FEATURE_INTMUX_DIRECTION_OUT (0) -/* @brief The total number of level1 interrupt vectors. */ -#define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32) - -/* LLWU module features */ - -/* @brief Maximum number of pins connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32) -/* @brief Maximum number of internal modules connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) -/* @brief Number of digital filters. */ -#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) -/* @brief Has MF register. */ -#define FSL_FEATURE_LLWU_HAS_MF (0) -/* @brief Has PF register. */ -#define FSL_FEATURE_LLWU_HAS_PF (1) -/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ -#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -/* @brief Has no internal module wakeup flag register. */ -#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1) -/* @brief Has external pin 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) -/* @brief Has external pin 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) -/* @brief Has external pin 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22) -/* @brief Has external pin 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30) -/* @brief Has external pin 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1) -/* @brief Has external pin 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2) -/* @brief Has external pin 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4) -/* @brief Has external pin 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6) -/* @brief Has external pin 8 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7) -/* @brief Has external pin 9 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8) -/* @brief Has external pin 10 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16) -/* @brief Has external pin 11 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20) -/* @brief Has external pin 12 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22) -/* @brief Has external pin 13 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25) -/* @brief Has external pin 14 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28) -/* @brief Has external pin 15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) -/* @brief Has external pin 16 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9) -/* @brief Has external pin 17 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11) -/* @brief Has external pin 18 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12) -/* @brief Has external pin 19 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8) -/* @brief Has external pin 20 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10) -/* @brief Has external pin 21 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1) -/* @brief Has external pin 22 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3) -/* @brief Has external pin 23 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8) -/* @brief Has external pin 24 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9) -/* @brief Has external pin 25 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10) -/* @brief Has external pin 26 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12) -/* @brief Has external pin 27 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) -/* @brief Has external pin 28 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) -/* @brief Has external pin 29 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) -/* @brief Has external pin 30 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) -/* @brief Has external pin 31 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) -/* @brief Has internal module 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) -/* @brief Has internal module 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) -/* @brief Has internal module 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) -/* @brief Has internal module 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) -/* @brief Has internal module 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) -/* @brief Has internal module 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) -/* @brief Has internal module 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1) -/* @brief Has internal module 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) -/* @brief Has LLWU_VERID. */ -#define FSL_FEATURE_LLWU_HAS_VERID (1) -/* @brief Has LLWU_PARAM. */ -#define FSL_FEATURE_LLWU_HAS_PARAM (1) -/* @brief LLWU register bit width. */ -#define FSL_FEATURE_LLWU_REG_BITWIDTH (32) -/* @brief Has DMA Enable register LLWU_DE. */ -#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1) - -/* LPDAC module features */ - -/* @brief FIFO size. */ -#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) - -/* LPI2C module features */ - -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) - -/* LPIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_LPIT_TIMER_COUNT (4) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_LPIT_HAS_CHAIN_MODE (0) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0) - -/* LPSPI module features */ - -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) - -/* LPUART module features */ - -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (1) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (1) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (1) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (1) - -/* MCM module features */ - -/* @brief Has L1 cache. */ -#define FSL_FEATURE_HAS_L1CACHE (1) - -/* MSCM module features */ - -/* @brief Number of configuration information for processors. */ -#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2) -/* @brief Has data cache. */ -#define FSL_FEATURE_MSCM_HAS_DATACACHE (0) - -/* MU module features */ - -/* @brief MU side for current core */ -#define FSL_FEATURE_MU_SIDE_B (1) -/* @brief MU Has register CCR */ -#define FSL_FEATURE_MU_HAS_CCR (1) -/* @brief MU Has register SR[RS], BSR[ARS] */ -#define FSL_FEATURE_MU_HAS_SR_RS (0) -/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ -#define FSL_FEATURE_MU_HAS_RESET_INT (1) -/* @brief MU Has register SR[MURIP] */ -#define FSL_FEATURE_MU_HAS_SR_MURIP (1) -/* @brief brief MU Has register SR[HRIP] */ -#define FSL_FEATURE_MU_HAS_SR_HRIP (1) -/* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ -#define FSL_FEATURE_MU_NO_CLKE (0) -/* @brief brief MU does not support NMI, CR[NMI]. */ -#define FSL_FEATURE_MU_NO_NMI (0) -/* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ -#define FSL_FEATURE_MU_NO_RSTH (0) -/* @brief brief MU does not supports MU reset, CR[MUR]. */ -#define FSL_FEATURE_MU_NO_MUR (0) -/* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ -#define FSL_FEATURE_MU_NO_HR (0) -/* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ -#define FSL_FEATURE_MU_HAS_HRM (1) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PCC module features */ - -/* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */ -#define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) -/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has independent interrupt control(register ICR). */ -#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1) - -/* RADIO module features */ - -/* @brief Zigbee availability. */ -#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) -/* @brief Bluetooth availability. */ -#define FSL_FEATURE_RADIO_HAS_BLE (1) -/* @brief ANT availability */ -#define FSL_FEATURE_RADIO_HAS_ANT (0) -/* @brief Generic FSK module availability */ -#define FSL_FEATURE_RADIO_HAS_GENFSK (1) -/* @brief Major version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MAJOR (3) -/* @brief Minor version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MINOR (0) - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (1) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (1) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (1) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (1) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) -/* @brief Has Tamper Interrupt Register (register TIR). */ -#define FSL_FEATURE_RTC_HAS_TIR (1) -/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_TPIE (1) -/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_SIE (1) -/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ -#define FSL_FEATURE_RTC_HAS_TIR_LCIE (1) -/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ -#define FSL_FEATURE_RTC_HAS_SR_TIDF (1) -/* @brief Has Tamper Detect Register (register TDR). */ -#define FSL_FEATURE_RTC_HAS_TDR (1) -/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_TPF (1) -/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_STF (1) -/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ -#define FSL_FEATURE_RTC_HAS_TDR_LCTF (1) -/* @brief Has Tamper Time Seconds Register (register TTSR). */ -#define FSL_FEATURE_RTC_HAS_TTSR (1) -/* @brief Has Pin Configuration Register (register PCR). */ -#define FSL_FEATURE_RTC_HAS_PCR (1) -/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ -#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0) - -/* SCG module features */ - -/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ -#define FSL_FEATURE_SCG_HAS_DIVPLAT (0) -/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ -#define FSL_FEATURE_SCG_HAS_DIVBUS (1) -/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ -#define FSL_FEATURE_SCG_HAS_DIVEXT (1) -/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ -#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) -/* @brief Has SOSCCSR[SOSCERCLKEN]. */ -#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0) -/* @brief Has OSC freq range SOSCCFG[RANGE]. */ -#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0) -/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ -#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) -/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1) -/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1) -/* @brief Has SCG_SIRCCSR[LPOPO]. */ -#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) -/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ -#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1) -/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ -#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) -/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ -#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) -/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ -#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) -/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ -#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) -/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ -#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) -/* @brief Has SCG_SPLLCFG[PLLS]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) -/* @brief Has SCG_SPLLCFG[BYPASS]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) -/* @brief Has SCG_SPLLCFG[PFDSEL]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) -/* @brief Has SCG_SPLLCSR[SPLLCM]. */ -#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) -/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ -#define FSL_FEATURE_SCG_HAS_FLLDIV3 (1) -/* @brief Has low power FLL, SCG_LPFLLCSR. */ -#define FSL_FEATURE_SCG_HAS_LPFLL (1) -/* @brief Has system PLL, SCG_SPLLCSR. */ -#define FSL_FEATURE_SCG_HAS_SPLL (0) -/* @brief Has system PLL PFD, SCG_SPLLPFD. */ -#define FSL_FEATURE_SCG_HAS_SPLLPFD (0) -/* @brief Has auxiliary PLL, SCG_APLLCSR. */ -#define FSL_FEATURE_SCG_HAS_APLL (0) -/* @brief Has RTC OSC control, SCG_ROSCCSR. */ -#define FSL_FEATURE_SCG_HAS_ROSC (1) -/* @brief Has RTC OSC clock source. */ -#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1) -/* @brief Has RTC OSC clock out select. */ -#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1) -/* @brief Has EXTERNAL clock out select. */ -#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1) -/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1) -/* @brief Has no SCG_SOSCCSR[SOSCEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (0) -/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (0) -/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */ -#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (0) -/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */ -#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0) -/* @brief Has FIRC trim source USB0 Start of Frame. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) -/* @brief Has FIRC trim source USB1 Start of Frame. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) -/* @brief Has FIRC trim source system OSC. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) -/* @brief Has FIRC trim source RTC OSC. */ -#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1) - -/* SEMA42 module features */ - -/* @brief Gate counts */ -#define FSL_FEATURE_SEMA42_GATE_COUNT (16) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0) -/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */ -#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1) -/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1) -/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1) -/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (0) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) -/* @brief Has MISCCTRL reg. */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL (0) -/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0) -/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0) -/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0) -/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0) -/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */ -#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0) -/* @brief Has SECKEY0 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY0 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */ -#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0) -/* @brief Has SECKEY1 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY1 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */ -#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0) -/* @brief Has SECKEY2 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY2 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */ -#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0) -/* @brief Has SECKEY3 reg. */ -#define FSL_FEATURE_SIM_HAS_SECKEY3 (0) -/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */ -#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0) -/* @brief Has no SDID reg. */ -#define FSL_FEATURE_SIM_HAS_NO_SDID (0) -/* @brief Has no UID reg. */ -#define FSL_FEATURE_SIM_HAS_NO_UID (0) -/* @brief Has RFADDRL and RFADDRH registers. */ -#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (1) -/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */ -#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1) -/* @brief Has UIDM registers. */ -#define FSL_FEATURE_SIM_HAS_UIDM (1) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (0) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (0) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (1) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (1) -/* @brief Has SMC_CSRE. */ -#define FSL_FEATURE_SMC_HAS_CSRE (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) -/* @brief Has security violation reset (register bit SRS[VBAT]). */ -#define FSL_FEATURE_SMC_HAS_SRS_VBAT (0) -/* @brief Has security violation reset (register bit SRS[CORE0]). */ -#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1) -/* @brief Has security violation reset (register bit SRS[CORE1]). */ -#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1) -/* @brief Has security violation reset (register bit SRIE[VBAT]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0) -/* @brief Has security violation reset (register bit SRIE[CORE0]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1) -/* @brief Has security violation reset (register bit SRIE[CORE1]). */ -#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (6) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (6) : \ - ((x) == TPM3 ? (2) : (-1))))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (1) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (1) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (1) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (1) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) - -/* TRGMUX module features */ - -/* No feature definitions */ - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSTMR module features */ - -/* @brief TSTMR clock frequency is 1MHZ. */ -#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1) - -/* USB module features */ - -/* @brief KHCI module instance count */ -#define FSL_FEATURE_USB_KHCI_COUNT (1) -/* @brief HOST mode enabled */ -#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) -/* @brief OTG mode enabled */ -#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_KHCI_USB_RAM (2048) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088) -/* @brief Has KEEP_ALIVE_CTRL register */ -#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1) -/* @brief Mode control of the USB Keep Alive */ -#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) -/* @brief Has the Dynamic SOF threshold compare support */ -#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) -/* @brief Has the VBUS detect support */ -#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) -/* @brief Has the IRC48M module clock support */ -#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) -/* @brief Number of endpoints supported */ -#define FSL_FEATURE_USB_ENDPT_COUNT (16) -/* @brief Has STALL_IL/OL_DIS registers */ -#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) -/* @brief Has STALL_IH/OH_DIS registers */ -#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) - -/* USDHC module features */ - -/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ -#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) -/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ -#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) -/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0) -/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (1) - -/* WDOG module features */ - -/* @brief Watchdog is available. */ -#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) -/* @brief WDOG_CNT can be 32-bit written. */ -#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) - -/* XRDC module features */ - -/* @brief Does not have global valid (register bit CR[GVLD]). */ -#define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1) -/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */ -#define FSL_FEATURE_XRDC_HAS_FDID (1) -/* @brief Has special 4-state model option (register bit PID[SP4SM]). */ -#define FSL_FEATURE_XRDC_PID_SP4SM (1) -/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */ -#define FSL_FEATURE_XRDC_NO_MDA_LPID (1) -/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */ -#define FSL_FEATURE_XRDC_NO_MDA_LPE (1) -/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */ -#define FSL_FEATURE_XRDC_NO_PDAC_SE (1) -/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */ -#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1) -/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */ -#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1) -/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */ -#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1) -/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1) -/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SE (1) -/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1) -/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1) -/* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SZ (1) -/* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_SRD (1) -/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1) -/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1) -/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1) -/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1) -/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */ -#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1) -/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_CR (1) -/* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1) -/* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1) -/* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1) -/* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */ -#define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1) -/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */ -#define FSL_FEATURE_XRDC_DOMAIN_COUNT (3) - -#endif /* _RV32M1_zero_riscy_FEATURES_H_ */ - diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/CMakeLists.txt b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/CMakeLists.txt deleted file mode 100644 index b62e097788e36035792a88acd2c98ceb5942ea7e..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -zephyr_include_directories(.) - -zephyr_sources(fsl_clock.c) -zephyr_sources_ifdef(CONFIG_UART_RV32M1_LPUART fsl_lpuart.c) -zephyr_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C fsl_lpi2c.c) -zephyr_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 fsl_flash.c) diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.c deleted file mode 100644 index 0324be4efdc3e418a32abc37caeede9845fd53d9..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.c +++ /dev/null @@ -1,4037 +0,0 @@ -/* - * Copyright 2017-2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_cau3.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cau3" -#endif - -/*! Compile time sizeof() check */ -#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -#define CAU3_SR_TKCS_INITRUN 0x00000000U -#define CAU3_SR_TKCS_RUN 0x00000100U -#define CAU3_SR_TKCS_DBGHALT 0x00000200U -#define CAU3_SR_TKCS_STOPNOERR 0x00000900U -#define CAU3_SR_TKCS_STOPERROR 0x00000A00U -#define CAU3_SR_TKCS_SECV 0x00000E00U -#define CAU3_SR_TKCS_EXTSECV 0x00000F00U - -#define CAU3_DMEM_STK_BASE 0xfff003f8U -#define CAU3_DMEM_AES_RCON 0xfff00A00U - -#define CAU3_TASK_SECV_INIT 0x00 * 4 -#define CAU3_TASK_STOPERROR 0x01 * 4 -#define CAU3_TASK_STOPNOERR 0x02 * 4 -#define CAU3_TASK_NULL 0x02 * 4 -#define CAU3_TASK_BLKLD_DMEM 0x03 * 4 -#define CAU3_TASK_LD_KEYCTX 0x04 * 4 -#define CAU3_TASK_LD_SP_KEYCTX 0x05 * 4 -#define CAU3_TASK_CLR_KEYCTX 0x06 * 4 -#define CAU3_TASK_LD_KEY 0x07 * 4 -#define CAU3_TASK_LD_KEK 0x08 * 4 -#define CAU3_TASK_LD_IV 0x09 * 4 -#define CAU3_TASK_AES_KEY_SCH 0x0A * 4 -#define CAU3_TASK_AES_ENCRYPT 0x0B * 4 -#define CAU3_TASK_AES_DECRYPT 0x0C * 4 -#define CAU3_TASK_AES128_ENCRYPT 0x0D * 4 -#define CAU3_TASK_AES128_DECRYPT 0x0E * 4 -#define CAU3_TASK_AES128_CMAC 0x0F * 4 -#define CAU3_TASK_SHA256_INIT_STATE 0x10 * 4 -#define CAU3_TASK_SHA256_UPDATE 0x11 * 4 -#define CAU3_TASK_KEY_BLOB_UNWRAP 0x12 * 4 -#define CAU3_TASK_SHA1_HASH 0x13 * 4 -#define CAU3_TASK_SHA1_INIT_STATE 0x14 * 4 -#define CAU3_TASK_SHA512_INIT_STATE 0x15 * 4 -#define CAU3_TASK_SHA512_UPDATE 0x16 * 4 -#define CAU3_TASK_3DES_CHECK_PARITY 0x17 * 4 -#define CAU3_TASK_3DES_ENCRYPT 0x18 * 4 -#define CAU3_TASK_3DES_DECRYPT 0x19 * 4 -#define CAU3_TASK_CHA_POLY_ENCRYPT 0x1A * 4 -#define CAU3_TASK_CHA_POLY_DECRYPT 0x1B * 4 - -#define CAU3_SEMA4_LOCK 0x80000000U -#define CAU3_SEMA4_RELEASE 0x00000000U -#define CAU3_SMOWNR_OWNED_BY_ME 0x00000001U -#define CAU3_SMOWNR_UNLOCKED 0x80000000U - -/*! @brief keyContext structure in the CAU3's DataMemory */ -typedef struct _cau3_key_context -{ - uint32_t keySize; /*!< key size in bytes, 0 = invalid context */ - uint32_t streamSize; /*!< rfu-firmware; stream length in bytes */ - uint32_t *keySched; /*!< rfu-firmware; ptr to expanded key schedule */ - uint32_t zeroFill; /*!< zero (unused) to keep 0-mod-4 alignment */ - uint8_t iv[16]; /*!< initialization vector */ - uint8_t key[32]; /*!< key for 3des, aes[128,192,256] */ -} cau3_key_context_t; - -typedef enum _cau3_crypt { - kCAU3_Encrypt = 0, - kCAU3_Decrypt = 1, -} cau3_crypt_t; - -#define cau3_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _cau3_hash_algo_state { - kCAU3_StateHashInit = 1u, /*!< Init state. */ - kCAU3_StateHashUpdate, /*!< Update state. */ -} cau3_hash_algo_state_t; - -/*! multiple of 64-byte block represented as byte array of 32-bit words */ -typedef union _cau3_hash_block { - uint32_t w[CAU3_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[CAU3_HASH_BLOCK_SIZE]; /*!< byte array */ -} cau3_hash_block_t; - -/*! internal cau3_hash context structure */ -typedef struct _cau3_hash_ctx_internal -{ - cau3_hash_block_t blk; /*!< memory buffer. only full blocks are written to CAU3 during hash/cmac updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - cau3_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - cau3_hash_algo_state_t state; /*!< finite machine state of the hash software process */ - size_t fullMessageSize; /*!< track message size during CAU3_HASH_Update(). The value is used for padding. */ - uint32_t runningHash[8]; -} cau3_hash_ctx_internal_t; - -/*!< SHA-1/SHA-2 digest length in bytes */ -enum _cau3_hash_digest_len -{ - kCAU3_OutLenSha1 = 20u, - kCAU3_OutLenSha256 = 32u, -}; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _cau3_sha_block { - uint32_t w[64 / 4]; /*!< array of 32-bit words */ - uint8_t b[64]; /*!< byte array */ -} cau3_sha_block_t; - -/*! Full word representing the actual bit values for the CAU3 1.0 mode register. */ -typedef uint32_t cau3_mode_t; - -#define CAU3_MDPK_ALG_PKHA (0x80U) /*!< Bit field value for CAU3_MDPK_ALG: PKHA */ -#define CAU3_MD_ALG_SHIFT 16 - -typedef enum _cau3_algorithm { - kCAU3_AlgorithmPKHA = CAU3_MDPK_ALG_PKHA << CAU3_MD_ALG_SHIFT, -} cau3_algorithm_t; - -/*! @brief CAU3 status flags */ -enum _cau3_status_flag -{ - kCAU3_StatusPkhaBusy = 1U << CAU3_STA_PB_SHIFT, - kCAU3_StatusDoneIsr = 1U << CAU3_STA_DI_SHIFT, - kCAU3_StatusErrorIsr = 1U << CAU3_STA_EI_SHIFT, - kCAU3_StatusPublicKeyPrime = 1U << CAU3_STA_PKP_SHIFT, - kCAU3_StatusPublicKeyOpOne = 1U << CAU3_STA_PKO_SHIFT, - kCAU3_StatusPublicKeyOpZero = 1U << CAU3_STA_PKZ_SHIFT, - kCAU3_StatusAll = 0 | kCAU3_StatusDoneIsr | kCAU3_StatusErrorIsr | kCAU3_StatusPkhaBusy | - kCAU3_StatusPublicKeyPrime | kCAU3_StatusPublicKeyOpOne | kCAU3_StatusPublicKeyOpZero -}; - -/*! @brief CAU3 clear register */ -typedef enum _cau3_clear_written { - kCAU3_ClearMode = 1U << 0, - kCAU3_ClearDataSize = 1U << 2, - kCAU3_ClearPkhaSizeA = 1U << 12, - kCAU3_ClearPkhaSizeB = 1U << 13, - kCAU3_ClearPkhaSizeN = 1U << 14, - kCAU3_ClearPkhaSizeE = 1U << 15, - kCAU3_ClearAllSize = (int)kCAU3_ClearPkhaSizeA | kCAU3_ClearPkhaSizeB | kCAU3_ClearPkhaSizeN | kCAU3_ClearPkhaSizeE, - kCAU3_ClearAll = (int)(kCAU3_ClearMode | kCAU3_ClearDataSize | kCAU3_ClearAllSize | 0) -} cau3_clear_written_t; - -/*! @brief PKHA functions - arithmetic, copy/clear memory. */ -typedef enum _cau3_pkha_func_t { - kCAU3_PKHA_ClearMem = 1U, - kCAU3_PKHA_ArithModAdd = 2U, /*!< (A + B) mod N */ - kCAU3_PKHA_ArithModSub1 = 3U, /*!< (A - B) mod N */ - kCAU3_PKHA_ArithModSub2 = 4U, /*!< (B - A) mod N */ - kCAU3_PKHA_ArithModMul = 5U, /*!< (A x B) mod N */ - kCAU3_PKHA_ArithModExp = 6U, /*!< (A^E) mod N */ - kCAU3_PKHA_ArithModRed = 7U, /*!< (A) mod N */ - kCAU3_PKHA_ArithModInv = 8U, /*!< (A^-1) mod N */ - kCAU3_PKHA_ArithEccAdd = 9U, /*!< (P1 + P2) */ - kCAU3_PKHA_ArithEccDouble = 10U, /*!< (P2 + P2) */ - kCAU3_PKHA_ArithEccMul = 11U, /*!< (E x P(A0,A1) */ - kCAU3_PKHA_ArithModR2 = 12U, /*!< (R^2 mod N) */ - kCAU3_PKHA_ArithModRR = 13U, /*!< (RERP mod N) */ - kCAU3_PKHA_ArithGcd = 14U, /*!< GCD (A, N) */ - kCAU3_PKHA_ArithPrimalityTest = 15U, /*!< Miller-Rabin */ - kCAU3_PKHA_CopyMemSizeN = 16U, - kCAU3_PKHA_CopyMemSizeSrc = 17U, - kCAU3_PKHA_ArithModSqrt = 0x17U, /*!< (B0 x B0) mod N = A mod N */ - kCAU3_PKHA_ArithEcmMul = 0x4B, /*!< (E x P[A0]) */ - kCAU3_PKHA_ArithEctAdd = 0x89, /*!< (P[A0,A1] + P[B1,B2]) */ - kCAU3_PKHA_ArithEctMul = 0x8B, /*!< (E x P[A0,A1]) */ -} cau3_pkha_func_t; - -/*! @brief Register areas for PKHA clear memory operations. */ -typedef enum _cau3_pkha_reg_area { - kCAU3_PKHA_RegA = 8U, - kCAU3_PKHA_RegB = 4U, - kCAU3_PKHA_RegE = 2U, - kCAU3_PKHA_RegN = 1U, - kCAU3_PKHA_RegAll = kCAU3_PKHA_RegA | kCAU3_PKHA_RegB | kCAU3_PKHA_RegE | kCAU3_PKHA_RegN, -} cau3_pkha_reg_area_t; - -/*! @brief Quadrant areas for 2048-bit registers for PKHA copy memory - * operations. */ -typedef enum _cau3_pkha_quad_area_t { - kCAU3_PKHA_Quad0 = 0U, - kCAU3_PKHA_Quad1 = 1U, - kCAU3_PKHA_Quad2 = 2U, - kCAU3_PKHA_Quad3 = 3U, -} cau3_pkha_quad_area_t; - -/*! @brief User-supplied (R^2 mod N) input or CAU3 should calculate. */ -typedef enum _cau3_pkha_r2_t { - kCAU3_PKHA_CalcR2 = 0U, /*!< Calculate (R^2 mod N) */ - kCAU3_PKHA_InputR2 = 1U /*!< (R^2 mod N) supplied as input */ -} cau3_pkha_r2_t; - -/*! @brief CAU3 PKHA parameters */ -typedef struct _cau3_pkha_mode_params_t -{ - cau3_pkha_func_t func; - cau3_pkha_f2m_t arithType; - cau3_pkha_montgomery_form_t montFormIn; - cau3_pkha_montgomery_form_t montFormOut; - cau3_pkha_reg_area_t srcReg; - cau3_pkha_quad_area_t srcQuad; - cau3_pkha_reg_area_t dstReg; - cau3_pkha_quad_area_t dstQuad; - cau3_pkha_timing_t equalTime; - cau3_pkha_r2_t r2modn; -} cau3_pkha_mode_params_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ -/******************************************************************************* - * CAU3 Read-Only Data Constants and CryptoCore Code Image - ******************************************************************************/ - -/* in the cau3's private, local data memory, there is a section for read-only */ -/* constants associated with AES, SHA-1, SHA-256, SHA-384 and SHA-512. */ -/* the memory organization and layout of this section is defined as: */ -/* */ -/* description size dmem_base description */ -/* cau_dmem_aes_rcon 48 FFF00800 RO aes constants 10 x 32b */ -/* cau_dmem_sha1_k 16 FFF00830 RO sha1 initial "k" 4 x 32b */ -/* cau_dmem_sha1_init_h 32 FFF00840 RO sha1 initial state 5 x 32b */ -/* cau_dmem_sha224_init_h 32 FFF00860 RO sha224 initial state 8 x 32b */ -/* cau_dmem_sha256_init_h 32 FFF00880 RO sha256 initial state 8 x 32b */ -/* cau_dmem_sha256_k 256 FFF008A0 RO sha256 initial "k" 64 x 32b */ -/* cau_dmem_sha384_init_h 64 FFF009A0 RO sha384 initial state 16 x 32b */ -/* cau_dmem_sha512_init_h 64 FFF009E0 RO sha512 initial state 16 x 32b */ -/* cau_dmem_sha512_k 640 FFF00A20 RO sha512 initial "k" 160 x 32b */ -/* */ -/* data size allocation are rounded up to be modulo 16 bytes as required. */ -/* */ - -static const uint32_t s_cau3ReadOnlyConstants[] __attribute__((aligned(16))) = { - /* AES RCON[] */ - 0x01000000U, 0x02000000U, 0x04000000U, 0x08000000U, 0x10000000U, 0x20000000U, 0x40000000U, 0x80000000U, 0x1b000000U, - 0x36000000U, 0x00000000U, 0x00000000U, /* zero fill for 0-mod-16 alignment */ - - /* SHA1_K[] */ - 0x5a827999U, 0x6ed9eba1U, 0x8f1bbcdcU, 0xca62c1d6U, - - /* SHA1_INIT_H[] */ - 0x67452301U, 0xefcdab89U, 0x98badcfeU, 0x10325476U, 0xc3d2e1f0U, 0x00000000U, 0x00000000U, - 0x00000000U, /* zero fill for 0-mod-16 alignemnt */ - - /* SHA224_INIT_H[] */ - 0xc1059ed8U, 0x367cd507U, 0x3070dd17U, 0xf70e5939U, 0xffc00b31U, 0x68581511U, 0x64f98fa7U, 0xbefa4fa4U, - - /* SHA256_INIT_H[] */ - /* As described in FIPS PUB 180-4 "Secure Hash Standard", the initial hash value */ - /* for SHA-256 is obtained by taking the first thirty-two bits of the fractional */ - /* parts of the square roots of the first eight prime numbers. */ - 0x6a09e667U, 0xbb67ae85U, 0x3c6ef372U, 0xa54ff53aU, 0x510e527fU, 0x9b05688cU, 0x1f83d9abU, 0x5be0cd19U, - - /* SHA256_K[], also used as SHA224_K[] */ - /* As described in FIPS PUB 180-4 "Secure Hash Standard", SHA-224 & SHA-256 use */ - /* the same sequence of sixty-four constant 32-bit words (K[]), where the words */ - /* represent the first thirty-two bits of the fractional parts of the cube roots */ - /* of the first sixty-four prime numbers. */ - - 0x428a2f98U, 0x71374491U, 0xb5c0fbcfU, 0xe9b5dba5U, 0x3956c25bU, 0x59f111f1U, 0x923f82a4U, 0xab1c5ed5U, 0xd807aa98U, - 0x12835b01U, 0x243185beU, 0x550c7dc3U, 0x72be5d74U, 0x80deb1feU, 0x9bdc06a7U, 0xc19bf174U, 0xe49b69c1U, 0xefbe4786U, - 0x0fc19dc6U, 0x240ca1ccU, 0x2de92c6fU, 0x4a7484aaU, 0x5cb0a9dcU, 0x76f988daU, 0x983e5152U, 0xa831c66dU, 0xb00327c8U, - 0xbf597fc7U, 0xc6e00bf3U, 0xd5a79147U, 0x06ca6351U, 0x14292967U, 0x27b70a85U, 0x2e1b2138U, 0x4d2c6dfcU, 0x53380d13U, - 0x650a7354U, 0x766a0abbU, 0x81c2c92eU, 0x92722c85U, 0xa2bfe8a1U, 0xa81a664bU, 0xc24b8b70U, 0xc76c51a3U, 0xd192e819U, - 0xd6990624U, 0xf40e3585U, 0x106aa070U, 0x19a4c116U, 0x1e376c08U, 0x2748774cU, 0x34b0bcb5U, 0x391c0cb3U, 0x4ed8aa4aU, - 0x5b9cca4fU, 0x682e6ff3U, 0x748f82eeU, 0x78a5636fU, 0x84c87814U, 0x8cc70208U, 0x90befffaU, 0xa4506cebU, 0xbef9a3f7U, - 0xc67178f2U, - - /* SHA384_INIT_H[] */ - /* 8 x 64-bit words in little-endian format */ - 0xc1059ed8U, 0xcbbb9d5dU, 0x367cd507U, 0x629a292aU, 0x3070dd17U, 0x9159015aU, 0xf70e5939U, 0x152fecd8U, 0xffc00b31U, - 0x67332667U, 0x68581511U, 0x8eb44a87U, 0x64f98fa7U, 0xdb0c2e0dU, 0xbefa4fa4U, 0x47b5481dU, - - /* SHA512_INIT_H[] */ - /* 8 x 64-bit words in little-endian format */ - 0xf3bcc908U, 0x6a09e667U, 0x84caa73bU, 0xbb67ae85U, 0xfe94f82bU, 0x3c6ef372U, 0x5f1d36f1U, 0xa54ff53aU, 0xade682d1U, - 0x510e527fU, 0x2b3e6c1fU, 0x9b05688cU, 0xfb41bd6bU, 0x1f83d9abU, 0x137e2179U, 0x5be0cd19U, - - /* SHA512_K[] */ - /* 80 x 64-bit words in little-endian format */ - 0xd728ae22U, 0x428a2f98U, 0x23ef65cdU, 0x71374491U, 0xec4d3b2fU, 0xb5c0fbcfU, 0x8189dbbcU, 0xe9b5dba5U, 0xf348b538U, - 0x3956c25bU, 0xb605d019U, 0x59f111f1U, 0xaf194f9bU, 0x923f82a4U, 0xda6d8118U, 0xab1c5ed5U, 0xa3030242U, 0xd807aa98U, - 0x45706fbeU, 0x12835b01U, 0x4ee4b28cU, 0x243185beU, 0xd5ffb4e2U, 0x550c7dc3U, 0xf27b896fU, 0x72be5d74U, 0x3b1696b1U, - 0x80deb1feU, 0x25c71235U, 0x9bdc06a7U, 0xcf692694U, 0xc19bf174U, 0x9ef14ad2U, 0xe49b69c1U, 0x384f25e3U, 0xefbe4786U, - 0x8b8cd5b5U, 0x0fc19dc6U, 0x77ac9c65U, 0x240ca1ccU, 0x592b0275U, 0x2de92c6fU, 0x6ea6e483U, 0x4a7484aaU, 0xbd41fbd4U, - 0x5cb0a9dcU, 0x831153b5U, 0x76f988daU, 0xee66dfabU, 0x983e5152U, 0x2db43210U, 0xa831c66dU, 0x98fb213fU, 0xb00327c8U, - 0xbeef0ee4U, 0xbf597fc7U, 0x3da88fc2U, 0xc6e00bf3U, 0x930aa725U, 0xd5a79147U, 0xe003826fU, 0x06ca6351U, 0x0a0e6e70U, - 0x14292967U, 0x46d22ffcU, 0x27b70a85U, 0x5c26c926U, 0x2e1b2138U, 0x5ac42aedU, 0x4d2c6dfcU, 0x9d95b3dfU, 0x53380d13U, - 0x8baf63deU, 0x650a7354U, 0x3c77b2a8U, 0x766a0abbU, 0x47edaee6U, 0x81c2c92eU, 0x1482353bU, 0x92722c85U, 0x4cf10364U, - 0xa2bfe8a1U, 0xbc423001U, 0xa81a664bU, 0xd0f89791U, 0xc24b8b70U, 0x0654be30U, 0xc76c51a3U, 0xd6ef5218U, 0xd192e819U, - 0x5565a910U, 0xd6990624U, 0x5771202aU, 0xf40e3585U, 0x32bbd1b8U, 0x106aa070U, 0xb8d2d0c8U, 0x19a4c116U, 0x5141ab53U, - 0x1e376c08U, 0xdf8eeb99U, 0x2748774cU, 0xe19b48a8U, 0x34b0bcb5U, 0xc5c95a63U, 0x391c0cb3U, 0xe3418acbU, 0x4ed8aa4aU, - 0x7763e373U, 0x5b9cca4fU, 0xd6b2b8a3U, 0x682e6ff3U, 0x5defb2fcU, 0x748f82eeU, 0x43172f60U, 0x78a5636fU, 0xa1f0ab72U, - 0x84c87814U, 0x1a6439ecU, 0x8cc70208U, 0x23631e28U, 0x90befffaU, 0xde82bde9U, 0xa4506cebU, 0xb2c67915U, 0xbef9a3f7U, - 0xe372532bU, 0xc67178f2U, 0xea26619cU, 0xca273eceU, 0x21c0c207U, 0xd186b8c7U, 0xcde0eb1eU, 0xeada7dd6U, 0xee6ed178U, - 0xf57d4f7fU, 0x72176fbaU, 0x06f067aaU, 0xa2c898a6U, 0x0a637dc5U, 0xbef90daeU, 0x113f9804U, 0x131c471bU, 0x1b710b35U, - 0x23047d84U, 0x28db77f5U, 0x40c72493U, 0x32caab7bU, 0x15c9bebcU, 0x3c9ebe0aU, 0x9c100d4cU, 0x431d67c4U, 0xcb3e42b6U, - 0x4cc5d4beU, 0xfc657e2aU, 0x597f299cU, 0x3ad6faecU, 0x5fcb6fabU, 0x4a475817U, 0x6c44198cU, - /* CHACHA_K[] */ - 0x61707865U, 0x3320646eU, 0x79622d32U, 0x6b206574U}; - -static const uint32_t s_cau3ReadOnlyConstantsBytes = sizeof(s_cau3ReadOnlyConstants); - -static const uint32_t s_cau3ImemImage[] __attribute__((aligned(16))) = { - 0x60C00000U, 0x54000040U, 0x54000020U, 0x60812760U, 0x608128C0U, 0x60812F00U, 0x60813640U, 0x608138C0U, 0x54000040U, - 0x60813C20U, 0x60813F40U, 0x60802060U, 0x60803BC0U, 0x60805780U, 0x54000040U, 0x60806800U, 0x60808AA0U, 0x60808D00U, - 0x60814120U, 0x6080C100U, 0x6080BF60U, 0x54000040U, 0x54000040U, 0x6080FB60U, 0x6080FE20U, 0x608112C0U, 0x608150C0U, - 0x60815700U, 0x54000040U, 0x54000040U, 0x54000040U, 0x54000040U, 0x86000280U, 0x86002282U, 0x08C82236U, 0x2000C011U, - 0x101FFE11U, 0x00405A31U, 0x20014015U, 0x101FFE15U, 0x00800004U, 0x00800425U, 0x00800846U, 0x00800C67U, 0xCE002220U, - 0xCE002222U, 0x3C000192U, 0x66801420U, 0x63801400U, 0x86004284U, 0x86006286U, 0xCE002224U, 0xCE002226U, 0x08D020E8U, - 0x01800108U, 0xAC0012A8U, 0x008C2000U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x01800068U, - 0x008C2084U, 0x008C10A5U, 0x008C14C6U, 0x008C18E7U, 0xCE002224U, 0xCE002226U, 0x08D020E8U, 0x01800108U, 0xAC0012A8U, - 0x008C2000U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x01800068U, 0x008C2084U, 0x008C10A5U, - 0x008C14C6U, 0x008C18E7U, 0xCE002224U, 0xCE002226U, 0x08D020E8U, 0x01800108U, 0xAC0012A8U, 0x008C2000U, 0x008C0021U, - 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x01800068U, 0x008C2084U, 0x008C10A5U, 0x008C14C6U, 0x008C18E7U, - 0xCE002224U, 0xCE002226U, 0x08D020E8U, 0x01800108U, 0xAC0012A8U, 0x008C2000U, 0x008C0021U, 0x008C0442U, 0x008C0863U, - 0xCE002220U, 0xCE002222U, 0x01800068U, 0x008C2084U, 0x008C10A5U, 0x008C14C6U, 0x008C18E7U, 0xCE002224U, 0xCE002226U, - 0x08D020E8U, 0x01800108U, 0xAC0012A8U, 0x008C2000U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, - 0x01800068U, 0x008C2084U, 0x008C10A5U, 0x008C14C6U, 0x008C18E7U, 0xCE002224U, 0xCE002226U, 0x08D020E8U, 0x01800108U, - 0xAC0012A8U, 0x008C2000U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x01800068U, 0x008C2084U, - 0x008C10A5U, 0x008C14C6U, 0x008C18E7U, 0xCE002224U, 0xCE002226U, 0x08D020E8U, 0x01800108U, 0xAC0012A8U, 0x008C2000U, - 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x29FFE211U, 0x60801F80U, 0x54000040U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x08D02067U, - 0x018000E7U, 0xAC0012A7U, 0x008C1C00U, 0x008C0021U, 0x008C0442U, 0x008C0863U, 0xCE002220U, 0xCE002222U, 0x29FFEA11U, - 0x04807FFFU, 0xC4FFA291U, 0x63802000U, 0x7080001FU, 0x5C1FFFE0U, 0x581FFFE0U, 0x54000020U, 0x08800E31U, 0x08C81A20U, - 0x2000A012U, 0x101FFE12U, 0x80000252U, 0x3C000312U, 0x668021A0U, 0x63802180U, 0x08501A52U, 0x08501A52U, 0x08501A52U, - 0x08C82236U, 0x2000C011U, 0x101FFE11U, 0x00405A31U, 0x0C800E04U, 0x638029C0U, 0x3C000024U, 0x63802780U, 0x3C000044U, - 0x63802540U, 0x94FFF605U, 0x08C860A0U, 0x94000605U, 0x08CC20A6U, 0x00881800U, 0x08C860A1U, 0x94001605U, 0x08CC20A6U, - 0x00881821U, 0x08C860A2U, 0x94002605U, 0x08CC20A6U, 0x00881842U, 0x08C860A3U, 0x94003605U, 0x08CC20A6U, 0x00881863U, - 0x60802A40U, 0x94FFFA05U, 0x08C840A0U, 0x94000A05U, 0x08CC40A6U, 0x00881800U, 0x08C840A1U, 0x94001A05U, 0x08CC40A6U, - 0x00881821U, 0x08C840A2U, 0x94002A05U, 0x08CC40A6U, 0x00881842U, 0x08C840A3U, 0x94003A05U, 0x08CC40A6U, 0x00881863U, - 0x60802A40U, 0x94FFFE05U, 0x08C820A0U, 0x94000E05U, 0x08CC60A6U, 0x00881800U, 0x08C820A1U, 0x94001E05U, 0x08CC60A6U, - 0x00881821U, 0x08C820A2U, 0x94002E05U, 0x08CC60A6U, 0x00881842U, 0x08C820A3U, 0x94003E05U, 0x08CC60A6U, 0x00881863U, - 0x60802A40U, 0x94000200U, 0x94001201U, 0x94002202U, 0x94003203U, 0xAC001220U, 0xAC001221U, 0xAC001222U, 0xAC001223U, - 0x08500A48U, 0x08CC0508U, 0x01800000U, 0x01800021U, 0x01800042U, 0x01800063U, 0x01900000U, 0x8E002224U, 0x8E002226U, - 0x01881000U, 0x01881421U, 0x01881842U, 0x01881C63U, 0x01800000U, 0x01800021U, 0x01800042U, 0x01800063U, 0x01900000U, - 0x8E002224U, 0x8E002226U, 0x01881000U, 0x01881421U, 0x01881842U, 0x01881C63U, 0x60002B08U, 0x01800000U, 0x01800021U, - 0x01800042U, 0x01800063U, 0x01900000U, 0x8E002224U, 0x8E002226U, 0x01881000U, 0x01881421U, 0x01881842U, 0x01881C63U, - 0x01800000U, 0x01800021U, 0x01800042U, 0x01800063U, 0x01900000U, 0xAC001220U, 0xAC001221U, 0xAC001222U, 0xAC001223U, - 0x0C800E64U, 0x63803A80U, 0x3C000024U, 0x63803760U, 0x3C000044U, 0x63803440U, 0x94FFF664U, 0x08CC2084U, 0x08C82084U, - 0x08CC6005U, 0x008810A5U, 0xD4FFF665U, 0x08C82005U, 0x08CC6024U, 0x008810A5U, 0xD4000665U, 0x08C82025U, 0x08CC6044U, - 0x008810A5U, 0xD4001665U, 0x08C82045U, 0x08CC6064U, 0x008810A5U, 0xD4002665U, 0x94003664U, 0x08C86084U, 0x08CC6084U, - 0x08C82065U, 0x008810A5U, 0xD4003665U, 0x60803B00U, 0x94FFFA64U, 0x08CC4084U, 0x08C84084U, 0x08CC4005U, 0x008810A5U, - 0xD4FFFA65U, 0x08C84005U, 0x08CC4024U, 0x008810A5U, 0xD4000A65U, 0x08C84025U, 0x08CC4044U, 0x008810A5U, 0xD4001A65U, - 0x08C84045U, 0x08CC4064U, 0x008810A5U, 0xD4002A65U, 0x94003A64U, 0x08C84084U, 0x08CC4084U, 0x08C84065U, 0x008810A5U, - 0xD4003A65U, 0x60803B00U, 0x94FFFE64U, 0x08CC6084U, 0x08C86084U, 0x08CC2005U, 0x008810A5U, 0xD4FFFE65U, 0x08C86005U, - 0x08CC2024U, 0x008810A5U, 0xD4000E65U, 0x08C86025U, 0x08CC2044U, 0x008810A5U, 0xD4001E65U, 0x08C86045U, 0x08CC2064U, - 0x008810A5U, 0xD4002E65U, 0x94003E64U, 0x08C82084U, 0x08CC2084U, 0x08C86065U, 0x008810A5U, 0xD4003E65U, 0x60803B00U, - 0xD4000260U, 0xD4001261U, 0xD4002262U, 0xD4003263U, 0x04807FFFU, 0x63803B60U, 0x7080001FU, 0x5C1FFFE0U, 0x581FFFE0U, - 0x54000020U, 0x08800E31U, 0x08C81A20U, 0x2000A012U, 0x101FFE12U, 0x80000252U, 0x3C000312U, 0x66803D00U, 0x63803CE0U, - 0x08501A52U, 0x08501A52U, 0x08501A52U, 0x08C82236U, 0x2000C011U, 0x101FFE11U, 0x00405A31U, 0x0C800E04U, 0x63804520U, - 0x3C000024U, 0x638042E0U, 0x3C000044U, 0x638040A0U, 0x94FFF605U, 0x08C860A0U, 0x94000605U, 0x08CC20A6U, 0x00881800U, - 0x08C860A1U, 0x94001605U, 0x08CC20A6U, 0x00881821U, 0x08C860A2U, 0x94002605U, 0x08CC20A6U, 0x00881842U, 0x08C860A3U, - 0x94003605U, 0x08CC20A6U, 0x00881863U, 0x608045A0U, 0x94FFFA05U, 0x08C840A0U, 0x94000A05U, 0x08CC40A6U, 0x00881800U, - 0x08C840A1U, 0x94001A05U, 0x08CC40A6U, 0x00881821U, 0x08C840A2U, 0x94002A05U, 0x08CC40A6U, 0x00881842U, 0x08C840A3U, - 0x94003A05U, 0x08CC40A6U, 0x00881863U, 0x608045A0U, 0x94FFFE05U, 0x08C820A0U, 0x94000E05U, 0x08CC60A6U, 0x00881800U, - 0x08C820A1U, 0x94001E05U, 0x08CC60A6U, 0x00881821U, 0x08C820A2U, 0x94002E05U, 0x08CC60A6U, 0x00881842U, 0x08C820A3U, - 0x94003E05U, 0x08CC60A6U, 0x00881863U, 0x608045A0U, 0x94000200U, 0x94001201U, 0x94002202U, 0x94003203U, 0x08C81259U, - 0x00406631U, 0xA8003223U, 0xA8FFF222U, 0xA8FFF221U, 0xA8FFF220U, 0x08500A59U, 0x08CC0739U, 0x01940000U, 0x01840063U, - 0x01840042U, 0x01840021U, 0x01840000U, 0x8AFFE23CU, 0x8AFFE23AU, 0x018C7463U, 0x018C7042U, 0x018C6C21U, 0x018C6800U, - 0x01940000U, 0x01840063U, 0x01840042U, 0x01840021U, 0x01840000U, 0x8AFFE23CU, 0x8AFFE23AU, 0x018C7463U, 0x018C7042U, - 0x018C6C21U, 0x018C6800U, 0x600046B9U, 0x01940000U, 0x01840063U, 0x01840042U, 0x01840021U, 0x01840000U, 0x8AFFE23CU, - 0x8AFFE23AU, 0x018C7463U, 0x018C7042U, 0x018C6C21U, 0x018C6800U, 0x01940000U, 0x01840063U, 0x01840042U, 0x01840021U, - 0x01840000U, 0xA8FFF223U, 0xA8FFF222U, 0xA8FFF221U, 0xA8FFF220U, 0x0C800E79U, 0x63805620U, 0x3C000039U, 0x63805300U, - 0x3C000059U, 0x63804FE0U, 0x94FFF664U, 0x08CC2084U, 0x08C82084U, 0x08CC6005U, 0x008810A5U, 0xD4FFF665U, 0x08C82005U, - 0x08CC6024U, 0x008810A5U, 0xD4000665U, 0x08C82025U, 0x08CC6044U, 0x008810A5U, 0xD4001665U, 0x08C82045U, 0x08CC6064U, - 0x008810A5U, 0xD4002665U, 0x94003664U, 0x08C86084U, 0x08CC6084U, 0x08C82065U, 0x008810A5U, 0xD4003665U, 0x608056A0U, - 0x94FFFA64U, 0x08CC4084U, 0x08C84084U, 0x08CC4005U, 0x008810A5U, 0xD4FFFA65U, 0x08C84005U, 0x08CC4024U, 0x008810A5U, - 0xD4000A65U, 0x08C84025U, 0x08CC4044U, 0x008810A5U, 0xD4001A65U, 0x08C84045U, 0x08CC4064U, 0x008810A5U, 0xD4002A65U, - 0x94003A64U, 0x08C84084U, 0x08CC4084U, 0x08C84065U, 0x008810A5U, 0xD4003A65U, 0x608056A0U, 0x94FFFE64U, 0x08CC6084U, - 0x08C86084U, 0x08CC2005U, 0x008810A5U, 0xD4FFFE65U, 0x08C86005U, 0x08CC2024U, 0x008810A5U, 0xD4000E65U, 0x08C86025U, - 0x08CC2044U, 0x008810A5U, 0xD4001E65U, 0x08C86045U, 0x08CC2064U, 0x008810A5U, 0xD4002E65U, 0x94003E64U, 0x08C82084U, - 0x08CC2084U, 0x08C86065U, 0x008810A5U, 0xD4003E65U, 0x608056A0U, 0xD4003263U, 0xD4002262U, 0xD4001261U, 0xD4000260U, - 0x04807FFFU, 0x63805700U, 0x7080001FU, 0x5C1FFFE0U, 0x581FFFE0U, 0x54000020U, 0x7080001FU, 0x08800E31U, 0x08C82236U, - 0x2000C011U, 0x101FFE11U, 0x00405A31U, 0x94000200U, 0x94001201U, 0x94002202U, 0x94003203U, 0xAC001220U, 0xAC001221U, - 0xAC001222U, 0xAC001223U, 0x01800000U, 0x01800021U, 0x01800042U, 0x01800063U, 0x01900000U, 0x8E002224U, 0x8E002226U, - 0x01881000U, 0x01881421U, 0x01881842U, 0x01881C63U, 0x01800000U, 0x01800021U, 0x01800042U, 0x01800063U, 0x01900000U, - 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0x0044077BU, 0xC60183DAU, 0x008C2040U, 0x08C47C00U, 0x008C0041U, 0x08CC7C00U, 0x00400021U, 0x03042020U, 0x0080001AU, - 0x0080043BU, 0x008C1C60U, 0x08C47C00U, 0x008C0061U, 0x08CC7C00U, 0x00400021U, 0x03041C20U, 0x0440035AU, 0x0044077BU, - 0x008C1880U, 0x08C47C00U, 0x008C0081U, 0x08CC7C00U, 0x00400021U, 0x03041820U, 0x0440035AU, 0x0044077BU, 0x008C3CA0U, - 0x08C47C00U, 0x008C00A1U, 0x08CC7C00U, 0x00400021U, 0x03043C20U, 0x0440035AU, 0x0044077BU, 0x008C3940U, 0x08C47C00U, - 0x008C0141U, 0x08CC7C00U, 0x00400021U, 0x03043820U, 0x0440035AU, 0x0044077BU, 0xC601A3DAU, 0x008C2440U, 0x08C47C00U, - 0x008C0041U, 0x08CC7C00U, 0x00400021U, 0x03042420U, 0x0080001AU, 0x0080043BU, 0x008C2060U, 0x08C47C00U, 0x008C0061U, - 0x08CC7C00U, 0x00400021U, 0x03042020U, 0x0440035AU, 0x0044077BU, 0x008C1C80U, 0x08C47C00U, 0x008C0081U, 0x08CC7C00U, - 0x00400021U, 0x03041C20U, 0x0440035AU, 0x0044077BU, 0x008C18A0U, 0x08C47C00U, 0x008C00A1U, 0x08CC7C00U, 0x00400021U, - 0x03041820U, 0x0440035AU, 0x0044077BU, 0x008C3D40U, 0x08C47C00U, 0x008C0141U, 0x08CC7C00U, 0x00400021U, 0x03043C20U, - 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0x08CC194AU, 0x08C8081AU, 0x00406842U, 0x00400042U, 0x08CC6840U, 0x08C81842U, 0x08CC1842U, 0x00400063U, 0x6001C3F8U, - 0x3C000010U, 0x6381E8A0U, 0x0C803E73U, 0x6381F2A0U, 0xC4FFF3DFU, 0xC8FFE3DEU, 0x7001F37FU, 0x840013DFU, 0x840003DEU, - 0x20000010U, 0x20000038U, 0x6081C3E0U, 0x08CC6860U, 0x08C81863U, 0x08CC1863U, 0x00400084U, 0x08CC6880U, 0x08C81884U, - 0x08CC1884U, 0x004000A5U, 0x08CC68A0U, 0x08C818A5U, 0x08CC18A5U, 0x0040014AU, 0x08CC6940U, 0x08C8194AU, 0x08CC194AU, - 0x00400042U, 0x08C8081AU, 0x00406842U, 0x08CC6840U, 0x08C81842U, 0x08CC1842U, 0x00400063U, 0x00800846U, 0x280000A6U, - 0x08CC68C0U, 0x08C818C6U, 0x08CC18C6U, 0x00400067U, 0x08CC68E0U, 0x08C818E7U, 0x08CC18E7U, 0x00400088U, 0x08CC6900U, - 0x08C81908U, 0x08CC1908U, 0x004000A9U, 0x08CC6920U, 0x08C81929U, 0x08CC1929U, 0x0040014BU, 0x2000003AU, 0x08C86B5AU, - 0x0050696BU, 0x08CC7D7AU, 0x0850075AU, 0x008068C6U, 0x008068E7U, 0x00806908U, 0x00806929U, 0x0080696BU, 0x2000001BU, - 0x00506B7AU, 0x0850075AU, 0x00806842U, 0x00881842U, 0x00806863U, 0x00881C63U, 0x00806884U, 0x00882084U, 0x008068A5U, - 0x008824A5U, 0x0080694AU, 0x00882D4AU, 0x08C8687BU, 0x00886C42U, 0x08CC1863U, 0x08C8509BU, 0x00886C63U, 0x08CC3084U, - 0x08C838BBU, 0x00886C84U, 0x08CC48A5U, 0x08C8215BU, 0x00886CA5U, 0x860063DAU, 0x860083DCU, 0x04406842U, 0x04446C63U, - 0x04447084U, 0x004474A5U, 0xC600A3C2U, 0xC600C3C4U, 0xC400E3CAU, 0x840263D0U, 0x860283C0U, 0x7080001FU, 0x20000020U, - 0x0CCC0400U, 0x6081F3E0U, 0x04500000U, 0x8E00225AU, 0x8EFFE25CU, 0x08803E61U, 0x20000000U, 0x00500400U, 0x08C47C01U, - 0x0080075AU, 0x28000080U, 0x08C47C01U, 0x0080077BU, 0x28000080U, 0x08C47C01U, 0x0080079CU, 0x28000080U, 0x08C47C01U, - 0x008007BDU, 0xCE00225AU, 0xCEFFE25CU, 0x08800E7AU, 0x08C80F5AU, 0x20000000U, 0x08440000U, 0x00C86800U, 0x2000001CU, - 0x00506B9AU, 0x00806B5CU, 0x08C47F9CU, 0x2800041AU, 0x00CC6B9CU, 0x0880327BU, 0x00404B7BU, 0x8400037DU, 0x008073BDU, - 0x008803BDU, 0xC400037DU, 0x7080001FU, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, - 0x00000000U}; - -static const uint32_t s_cau3ImemBytes = sizeof(s_cau3ImemImage); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static status_t cau3_initialize_inst_memory(CAU3_Type *base, const uint32_t *cau3ImemImage, size_t cau3ImemBytes); -static status_t cau3_initialize_data_memory(CAU3_Type *base, cau3_task_done_t taskDone); -static status_t cau3_initialize_read_only_data_memory(CAU3_Type *base, - const uint32_t *cau3ReadOnlyConstants, - size_t cau3ReadOnlyConstantsBytes, - cau3_task_done_t taskDone); -static status_t cau3_load_key_context(CAU3_Type *base, - cau3_key_context_t *cauKeyContext, - cau3_key_slot_t keySlot, - cau3_task_done_t taskDone); -static status_t cau3_load_key( - CAU3_Type *base, const uint8_t *key, size_t keySize, uint32_t keySlot, cau3_task_done_t taskDone); -static status_t cau3_pkha_clear_regabne(CAU3_Type *base, bool A, bool B, bool N, bool E); - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) -static status_t cau3_execute_null_task(CAU3_Type *base, cau3_task_done_t taskDone); -static status_t cau3_lock_semaphore(CAU3_Type *base); -static void cau3_release_semaphore(CAU3_Type *base); -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -static status_t cau3_process_task_completion(CAU3_Type *base, cau3_task_done_t taskDone) -{ - status_t taskCompletionStatus; - - taskCompletionStatus = kStatus_Fail; /* assume an error completion status */ - switch (((uint32_t)taskDone >> 16U) & 7U) - { - uint32_t tkcs; - - case 0: /* poll the cau3 status register */ - tkcs = base->SR & CAU3_SR_TKCS_MASK; - while (tkcs == CAU3_SR_TKCS_RUN) - { - tkcs = base->SR & CAU3_SR_TKCS_MASK; - }; - - /* check the task completion status*/ - if (tkcs == CAU3_SR_TKCS_STOPNOERR) - { - taskCompletionStatus = kStatus_Success; /* signal error-free completion status */ - } - - break; - - case 2: /* task completion signaled by event_done */ - do - { - __WFE(); /* cpu is waiting for cau3 event_done */ - tkcs = base->SR & CAU3_SR_TKCS_MASK; - } while (tkcs == CAU3_SR_TKCS_RUN); - - /* check the task completion status */ - if (tkcs == CAU3_SR_TKCS_STOPNOERR) - { - taskCompletionStatus = kStatus_Success; /* signal error-free completion status */ - } - break; - - case 1: /* task completion signaled by irq */ - /* TEMP FIX - for boot ROM with IRQ task completion, simply return */ - case 4: /* task completion signaled by dma_req */ - /* processing here is complete */ - taskCompletionStatus = kStatus_Success; /* signal error-free completion status */ - break; - - default: /* undefined taskDone specifier defaults to kStatus_Fail */ - break; - } /* end - switch (taskDone & 7U) */ - - return (taskCompletionStatus); -} - -/*! - * @brief Initialize the CAU3's Instruction Memory - * - * Initializes the CAU3, including configuring it to enable the execution of - * crypto tasks, loading the CryptoCore's firmware image into the CAU3's - * instruction memory, and then performing a simple read-verify of its contents. - * NOTE: All the operations for this function are executed on the host processor. - * - * cau3_initialize_inst_memory - * @param cau3ImemImage - binary firmware image for CryptoCore - * @param cau3ImemBytes - size of the firmware image in bytes - * - * @retval status from the readVerify check: CAU_[OK (=0), ERROR (!0)] - * if an error is signaled, the retval is 0xbad10000UU + i, where i is - * the first miscompare word index location - */ -static status_t cau3_initialize_inst_memory(CAU3_Type *base, const uint32_t *cau3ImemImage, size_t cau3ImemBytes) -{ - uint32_t i; - - /* enable the cau3 */ - base->CR = 0U; - - /* poll if/while the cau3 is running initialization */ - while ((base->SR & CAU3_SR_TKCS_MASK) == CAU3_SR_TKCS_INITRUN) - { - }; - - /* check for error-free stop state */ - if ((base->SR & CAU3_SR_TKCS_MASK) != CAU3_SR_TKCS_STOPNOERR) - { - return (0xbad00000U + (base->SR & CAU3_SR_TKCS_MASK)); /* exit with error */ - } - - base->SR = CAU3_SR_TCIRQ_MASK; /* clear the TCIRQ interrupt flag */ - - /* write the code hex image into the cau3's imem - * initialize the memory cmd and address registers */ - base->DBGMCMD = 0xac000000U; /* wt=1, ia=1, imem=0 */ - base->DBGMADR = 0U; /* imem starting address */ - for (i = 0; i < cau3ImemBytes / 4; i++) - { - base->DBGMDR = cau3ImemImage[i]; /* indirect write into cau3Imem */ - } - - /* read-verify the cau3 imem code image - * initialize the memory cmd and address registers */ - base->DBGMCMD = 0x8c000000U; /* wt=0, ia=1, imem=0 */ - base->DBGMADR = 0U; /* imem starting address */ - for (i = 0; i < cau3ImemBytes / 4; i++) - { - if (base->DBGMDR != cau3ImemImage[i]) /* indirect read from cau3Imem */ - { - return (0xbad10000U + i); /* exit on miscompare */ - } - } - - /* this function does *not* disable reads/writes of the cau3 local memories - * but, this operation is needed to "secure" (i.e., make private) the cau3 - * local memories */ - - return 0U; -} - -/*! - * @brief Initializes the CAU3's entire private Data Memory - * - * Initialize the CAU3's data memory, and then perform a read-verify versus a - * precalculated "pseudo-hash" value. - * - * cau3_initialize_data_memory - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status from the readVerify check: CAU_[OK, ERROR] - */ -static status_t cau3_initialize_data_memory(CAU3_Type *base, cau3_task_done_t taskDone) -{ - status_t completionStatus; - - /* execute the cau3 "security violation + data initialization" task */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_SECV_INIT; /* call cau_secv_init() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); - return (completionStatus); -} - -/*! - * @brief Copies read-only constants from sysMemory to CAU3's DataMemory - * - * Initialize the read-only constants in the CAU3's data memory. This includes - * the AES constants (RCON) and most of the constants used in the hash functions. - * The constants associated with SHA-512 are NOT included and must be loaded - * separately. - * - * cau3_initialize_read_only_data_memory - * @param cauReadOnlyConstants - sysMemory table of constants needed by CAU3 - * @param cauReadOnlyConstantsSize - size of read-only constants in bytes - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ -static status_t cau3_initialize_read_only_data_memory(CAU3_Type *base, - const uint32_t *cau3ReadOnlyConstants, - size_t cau3ReadOnlyConstantsBytes, - cau3_task_done_t taskDone) -{ - status_t completionStatus; - - /* execute the cau3 "initialize dmem read-only constants" task */ - base->CC_R[16] = (uint32_t)s_cau3ReadOnlyConstants; /* pReadOnlyConstants */ - base->CC_R[17] = s_cau3ReadOnlyConstantsBytes; /* byte count (0-mod-16) */ - base->CC_R[18] = CAU3_DMEM_AES_RCON; /* pDMEM_AES_RCON constants base */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_BLKLD_DMEM; /* call cau_block_load_dmem task */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); - return (completionStatus); -} - -status_t CAU3_MakeMemsPrivate(CAU3_Type *base, cau3_task_done_t taskDone) -{ -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - uint32_t completionStatus; - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif /* FSL_CAU3_USE_HW_SEMA */ - - /* making the xMEMs private involves setting DBGCSR[DDBGMC] = 1 */ - base->DBGCSR = CAU3_DBGCSR_DDBGMC_MASK; /* set DBGCSR[DDBGMC] */ - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return kStatus_Success; -} - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) -/*! - * @brief Execute a CAU3 null task to "establish ownership" by host processor - * - * Execute a null task to claim ownership of the CAU3 by the host processor. - * This is required for correct IRQ, EVT and DMA_REQ signaling by subsequent - * PKHA operations. The CryptoCore task executes one instruction - a "stop". - * - * cau3_execute_null_task - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ -static status_t cau3_execute_null_task(CAU3_Type *base, cau3_task_done_t taskDone) -{ - status_t completionStatus; - - /* execute the cau3 null task */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_NULL; /* call cau_null() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); - return (completionStatus); -} -#endif /* FSL_CAU3_USE_HW_SEMA */ - -/*! - * @brief Load a key into a key context - * - * Loads up to 32-byte key into the specified key slot. - * There is support for a maximum of 4 key slots. - * This does not do AES key expansion (as in cau3_load_key_context() case) so we use this one for loading TDES keys. - * - * @param key is the key pointer, ALIGNED ON A 0-MOD-4 ADDRESS - * @param keySize is the size in bytes of the key - * @param keySlot is the destination key context - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ -static status_t cau3_load_key( - CAU3_Type *base, const uint8_t *key, size_t keySize, uint32_t keySlot, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "load initialization vector into key context" task */ - base->CC_R[16] = (uintptr_t)key; /* pKey */ - base->CC_R[17] = keySize; /* IV size */ - base->CC_R[18] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_LD_KEY; /* call cau_load_key() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_AES_Encrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t plaintext[16], uint8_t ciphertext[16]) -{ - status_t completionStatus; - cau3_task_done_t taskDone; - - taskDone = handle->taskDone; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "aes_encrypt_ecb" task */ - base->CC_R[16] = (uint32_t)plaintext; /* pPlainText */ - base->CC_R[17] = handle->keySlot; /* keySlot */ - base->CC_R[19] = (uint32_t)ciphertext; /* pCipherText */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_AES_ENCRYPT; /* call cau_aes_encrypt() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_AES_Decrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t ciphertext[16], uint8_t plaintext[16]) -{ - status_t completionStatus; - cau3_task_done_t taskDone; - - taskDone = handle->taskDone; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "aes_decrypt_ecb" task */ - base->CC_R[16] = (uint32_t)ciphertext; /* pCipherText */ - base->CC_R[17] = handle->keySlot; /* keySlot */ - base->CC_R[19] = (uint32_t)plaintext; /* pPlainText */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_AES_DECRYPT; /* call cau_aes_decrypt() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -void CAU3_Init(CAU3_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* ungate clock */ - CLOCK_EnableClock(kCLOCK_Cau3); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - CLOCK_EnableClock(FSL_CAU3_SEMA42_CLOCK_NAME); -#endif /* FSL_CAU3_USE_HW_SEMA */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - base->CR = CAU3_CR_RSTSM4(1); - base->CR = CAU3_CR_RSTSM4(2); - cau3_initialize_inst_memory(base, s_cau3ImemImage, s_cau3ImemBytes); - cau3_initialize_data_memory(base, kCAU3_TaskDonePoll); - cau3_initialize_read_only_data_memory(base, s_cau3ReadOnlyConstants, s_cau3ReadOnlyConstantsBytes, - kCAU3_TaskDonePoll); - cau3_pkha_clear_regabne(base, true, true, true, true); -} - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) -static status_t cau3_lock_semaphore(CAU3_Type *base) -{ - uint32_t processorNumber = 0; - - /* cm4 will be 1, cm0+ will be 2 */ - /* For next SoC, the processor number shall be defined in the SoC header file */ -#if __CORTEX_M == 0U - processorNumber++; -#endif - processorNumber++; - - while (processorNumber != SEMA42_GATEn(FSL_CAU3_SEMA42_BASE, 1)) - { - /* Wait for unlocked status. */ - while (SEMA42_GATEn(FSL_CAU3_SEMA42_BASE, FSL_CAU3_SEMA42_GATE)) - { - } - - /* Lock the gate. */ - SEMA42_GATEn(FSL_CAU3_SEMA42_BASE, FSL_CAU3_SEMA42_GATE) = processorNumber; - } - - return cau3_execute_null_task(base, kCAU3_TaskDonePoll); -} -#endif /* FSL_CAU3_USE_HW_SEMA */ - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) -static void cau3_release_semaphore(CAU3_Type *base) -{ - /* unlock the semaphore */ - SEMA42_GATEn(FSL_CAU3_SEMA42_BASE, FSL_CAU3_SEMA42_GATE) = 0; -} -#endif /* FSL_CAU3_USE_HW_SEMA */ - -/*! - * @brief Load a 64-byte "key context" into the CAU3's private data memory - * - * Load the key context into the private DMEM. This includes size and config - * information, a 16-byte initialization vector and a key of size [8,16,24,32] - * bytes (for DES or AES-[128,192,256]). There is support for 4 "key slots" with - * slot 0 typically used for the system key encryption key (KEK). - * - * See the GENERAL COMMENTS for more information on the keyContext structure. - * - * NOTE: This function also performs an AES key expansion if a keySize > 8 - * is specified. - * - * cau3_load_key_context - * @param cauKeyContext is pointer to key structure in sysMemory - * @param keySlot is the destination key slot number [0-3] - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @return status check from task completion: CAU_[OK, ERROR] - */ -static status_t cau3_load_key_context(CAU3_Type *base, - cau3_key_context_t *cauKeyContext, - cau3_key_slot_t keySlot, - cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "load key context" task */ - base->CC_R[16] = (uint32_t)cauKeyContext; /* pKeyContext */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_LD_KEYCTX; /* call cau_load_key_context() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_ForceError(CAU3_Type *base, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 null task */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_STOPERROR; - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_LoadSpecialKeyContext(CAU3_Type *base, size_t keySize, cau3_key_slot_t keySlot, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "load special key context" task */ - base->CC_R[16] = keySize; /* keySize [8,16,24,32] */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_LD_SP_KEYCTX; /* call cau_load_special_key_context() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_ClearKeyContext(CAU3_Type *base, cau3_key_slot_t keySlot, cau3_task_done_t taskDone) -{ - uint32_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "clear key context" task */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_CLR_KEYCTX; /* call cau_clear_key_context() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_LoadKeyInitVector(CAU3_Type *base, const uint8_t *iv, cau3_key_slot_t keySlot, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "load initialization vector into key context" task */ - base->CC_R[16] = (uintptr_t)iv; /* pIv */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_LD_IV; /* call cau_load_iv() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_AES_KeyExpansion(CAU3_Type *base, cau3_key_slot_t keySlot, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "aes_key_expansion" task */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_AES_KEY_SCH; /* call cau_aes_key_sched() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_AES_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize) -{ - cau3_key_context_t cau3KeyCtx = {0}; - - /* only work with aligned key[] */ - if (0x3U & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - /* keySize must be 16 or 32. initial CAU3 firmware doesn't support 24 bytes. */ - if ((keySize != 16U) && (keySize != 32U)) - { - return kStatus_InvalidArgument; - } - - cau3KeyCtx.keySize = keySize; - - /* move the key by 32-bit words */ - int i = 0; - while (keySize) - { - keySize -= sizeof(uint32_t); - ((uint32_t *)((uintptr_t)cau3KeyCtx.key))[i] = ((uint32_t *)(uintptr_t)key)[i]; - i++; - } - - return cau3_load_key_context(base, &cau3KeyCtx, handle->keySlot, handle->taskDone); -} - -status_t CAU3_AES_Cmac(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *message, size_t size, uint8_t *mac) -{ - status_t completionStatus; - - /* mac must be 0-mod-4 aligned */ - if (0x3U & (uintptr_t)mac) - { - return kStatus_InvalidArgument; - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "aes_cmac" task */ - base->CC_R[16] = (uintptr_t)message; /* pMessage */ - base->CC_R[17] = handle->keySlot; /* keySlot */ - base->CC_R[18] = size; /* messageSize */ - base->CC_R[19] = (uintptr_t)mac; /* pMac */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_AES128_CMAC; /* call cau_aes128_cmac() */ - base->CC_CMD = handle->taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, handle->taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t cau3_hash_check_input_alg(cau3_hash_algo_t algo) -{ - if ((algo != kCAU3_Sha256) && (algo != kCAU3_Sha1)) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base CAU3 peripheral base address. - * @param ctx Memory buffer given by user application where the CAU3_HASH_Init/CAU3_HASH_Update/CAU3_HASH_Finish store - * context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t cau3_hash_check_input_args(CAU3_Type *base, cau3_hash_ctx_t *ctx, cau3_hash_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != cau3_hash_check_input_alg(algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @param message Input message address. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t cau3_hash_check_context(cau3_hash_ctx_internal_t *ctxInternal, const uint8_t *message) -{ - if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != cau3_hash_check_input_alg(ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Initialize message digest output state for SHA-1 hash - * - * Initializes the message digest output state for a SHA-1 hash. - * - * @param sha1State is message digest output in sysMemory in BE format - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ - -static status_t CAU3_Sha1InitializeOutput(CAU3_Type *base, uint32_t *sha1State, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "sha1_init_output" task */ - base->CC_R[29] = (uintptr_t)sha1State; /* pSha1State */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_SHA1_INIT_STATE; /* call cau_sha1_init_state() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -/*! - * @brief Perform a SHA-1 hash function over a message of "n" 64-byte blocks - * - * Perform a SHA-1 hash function over a message of "n" 64-byte data blocks, - * returning an 8-word message digest (aka "state"). The input message must - * be padded appropriately as defined by the SHA-1 algorithm. - * - * @param message is the uint8_t input message, any alignment - * @param numberOfBlocks is the message length as multiple of 64-byte blocks - * @param sha1State is uint32_t message digest output (state) in BE format - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ - -static status_t CAU3_Sha1Update( - CAU3_Type *base, const uint8_t *message, uint32_t numberOfBlocks, uint32_t *sha1State, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "sha1_update" task */ - base->CC_R[27] = (uintptr_t)message; /* pMessage */ - base->CC_R[28] = numberOfBlocks; /* n blocks */ - base->CC_R[29] = (uintptr_t)sha1State; /* output */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_SHA1_HASH; /* call cau_sha1_hash_n() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -/*! - * @brief Initialize message digest output state for SHA-256 hash - * - * Initializes the message digest output state for a SHA-256 hash. - * - * CAU3_Sha256InitializeOutput - * @param sha256State is message digest output in sysMemory in BE format - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ - -status_t CAU3_Sha256InitializeOutput(CAU3_Type *base, uint32_t *sha256State, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "sha256_init_output" task */ - base->CC_R[29] = (uint32_t)sha256State; /* pSha256State */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_SHA256_INIT_STATE; /* call cau_sha256_init_state() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -/*! - * @brief Perform a SHA-256 hash function over a message of "n" 64-byte blocks - * - * Perform a SHA-256 hash function over a message of "n" 64-byte data blocks, - * returning an 8-word message digest (aka "state"). The input message must - * be padded appropriately as defined by the SHA-256 algorithm. - * - * CAU_Sha256Update - * @param message is the uint8_t input message, LE, ANY ALIGNMENT - * @param numberOfBlocks is the message length as multiple of 64-byte blocks - * @param sha256State is uint32_t message digest output (state) in BE format - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ - -status_t CAU3_Sha256Update( - CAU3_Type *base, const uint8_t *message, uint32_t numberOfBlocks, uint32_t *sha256State, cau3_task_done_t taskDone) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "sha256_update" task */ - base->CC_R[27] = (uint32_t)message; /* pMessage */ - base->CC_R[28] = numberOfBlocks; /* = (64*numberOfBlocks) bytes */ - base->CC_R[29] = (uint32_t)sha256State; /* pSha256State */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_SHA256_UPDATE; /* call cau_sha256_update() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -/*! - * @brief Initialize the SHA engine for new hash. - * - * This function sets NEW and MODE fields in SHA Control register to start new hash. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - */ -static status_t cau3_hash_engine_init(CAU3_Type *base, cau3_hash_ctx_internal_t *ctxInternal) -{ - status_t status; - - status = kStatus_InvalidArgument; - - if (kCAU3_Sha256 == ctxInternal->algo) - { - status = CAU3_Sha256InitializeOutput(base, ctxInternal->runningHash, kCAU3_TaskDonePoll); - } - - if (kCAU3_Sha1 == ctxInternal->algo) - { - status = CAU3_Sha1InitializeOutput(base, ctxInternal->runningHash, kCAU3_TaskDonePoll); - } - - return status; -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base CAU3 peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t cau3_hash_process_message_data(CAU3_Type *base, - cau3_hash_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - status_t status; - status_t (*funcUpdate)(CAU3_Type * cau3base, const uint8_t *msg, uint32_t numberOfBlocks, uint32_t *shaState, - cau3_task_done_t taskDone); - - /* first fill the internal buffer to full block */ - size_t toCopy = CAU3_HASH_BLOCK_SIZE - ctxInternal->blksz; - cau3_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - status = kStatus_InvalidArgument; - funcUpdate = NULL; - - switch (ctxInternal->algo) - { - case kCAU3_Sha256: - funcUpdate = CAU3_Sha256Update; - break; - - case kCAU3_Sha1: - funcUpdate = CAU3_Sha1Update; - break; - - default: - break; - } - - if (NULL != funcUpdate) - { - /* process full internal block */ - status = funcUpdate(base, &ctxInternal->blk.b[0], CAU3_HASH_BLOCK_SIZE / 64u, ctxInternal->runningHash, - kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - - /* process all full blocks in message[] */ - while (messageSize >= CAU3_HASH_BLOCK_SIZE) - { - status = - funcUpdate(base, message, CAU3_HASH_BLOCK_SIZE / 64u, ctxInternal->runningHash, kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - message += CAU3_HASH_BLOCK_SIZE; - messageSize -= CAU3_HASH_BLOCK_SIZE; - } - - /* copy last incomplete message bytes into internal block */ - cau3_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - } - - return status; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t cau3_hash_finalize(CAU3_Type *base, cau3_hash_ctx_internal_t *ctxInternal) -{ - cau3_sha_block_t lastBlock; - status_t status; - status_t (*funcUpdate)(CAU3_Type * cau3base, const uint8_t *msg, uint32_t numberOfBlocks, uint32_t *shaState, - cau3_task_done_t taskDone); - - status = kStatus_InvalidArgument; - funcUpdate = NULL; - - switch (ctxInternal->algo) - { - case kCAU3_Sha256: - funcUpdate = CAU3_Sha256Update; - break; - - case kCAU3_Sha1: - funcUpdate = CAU3_Sha1Update; - break; - - default: - break; - } - - if (NULL == funcUpdate) - { - return kStatus_InvalidArgument; - } - - memset(&lastBlock, 0, sizeof(cau3_sha_block_t)); - status = kStatus_Success; - - while (ctxInternal->blksz >= 64u) - { - status = funcUpdate(base, &ctxInternal->blk.b[0], 1, ctxInternal->runningHash, kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - ctxInternal->blksz -= 64u; - cau3_memcpy(&ctxInternal->blk.b[0], &ctxInternal->blk.b[64], ctxInternal->blksz); - } - - /* this is last call, so need to flush buffered message bytes along with padding */ - if (ctxInternal->blksz <= 55u) - { - /* last data is 440 bits or less. */ - cau3_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[15] = __REV(8u * ctxInternal->fullMessageSize); - status = funcUpdate(base, &lastBlock.b[0], 1, ctxInternal->runningHash, kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - } - else - { - if (ctxInternal->blksz < 64u) - { - ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; - for (uint32_t i = ctxInternal->blksz + 1u; i < 64u; i++) - { - ctxInternal->blk.b[i] = 0; - } - } - else - { - lastBlock.b[0] = (uint8_t)0x80U; - } - - status = funcUpdate(base, &ctxInternal->blk.b[0], 1, ctxInternal->runningHash, kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - lastBlock.w[15] = __REV(8u * ctxInternal->fullMessageSize); - status = funcUpdate(base, &lastBlock.b[0], 1, ctxInternal->runningHash, kCAU3_TaskDonePoll); - if (kStatus_Success != status) - { - return status; - } - } - return status; -} - -status_t CAU3_HASH_Init(CAU3_Type *base, cau3_hash_ctx_t *ctx, cau3_hash_algo_t algo) -{ - status_t status; - - cau3_hash_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSURE(sizeof(cau3_hash_ctx_t) >= sizeof(cau3_hash_ctx_internal_t), cau3_hash_ctx_t_size); - uint32_t i; - - status = cau3_hash_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (cau3_hash_ctx_internal_t *)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; - for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[0] = 0u; - } - ctxInternal->state = kCAU3_StateHashInit; - ctxInternal->fullMessageSize = 0; - - return status; -} - -status_t CAU3_HASH_Update(CAU3_Type *base, cau3_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - cau3_hash_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0) - { - return kStatus_Success; - } - - ctxInternal = (cau3_hash_ctx_internal_t *)ctx; - status = cau3_hash_check_context(ctxInternal, input); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize += inputSize; - blockSize = CAU3_HASH_BLOCK_SIZE; - /* if we are still less than CAU3_HASH_BLOCK_SIZE bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - cau3_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return status; - } - else - { - isUpdateState = ctxInternal->state == kCAU3_StateHashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - status = cau3_hash_engine_init(base, ctxInternal); - if (status != kStatus_Success) - { - return status; - } - ctxInternal->state = kCAU3_StateHashUpdate; - } - } - - /* process input data */ - status = cau3_hash_process_message_data(base, ctxInternal, input, inputSize); - return status; -} - -status_t CAU3_HASH_Finish(CAU3_Type *base, cau3_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - cau3_hash_ctx_internal_t *ctxInternal; - - ctxInternal = (cau3_hash_ctx_internal_t *)ctx; - status = cau3_hash_check_context(ctxInternal, output); - if (kStatus_Success != status) - { - return status; - } - - if (ctxInternal->state == kCAU3_StateHashInit) - { - status = cau3_hash_engine_init(base, ctxInternal); - if (status != kStatus_Success) - { - return status; - } - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kCAU3_Sha256: - outSize = kCAU3_OutLenSha256; - break; - case kCAU3_Sha1: - outSize = kCAU3_OutLenSha1; - break; - default: - break; - } - algOutSize = outSize; - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = cau3_hash_finalize(base, ctxInternal); - - if (outputSize) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - cau3_memcpy(&output[0], ctxInternal->runningHash, algOutSize); - - memset(ctx, 0, sizeof(cau3_hash_ctx_t)); - return status; -} - -status_t CAU3_HASH( - CAU3_Type *base, cau3_hash_algo_t algo, const uint8_t *input, size_t inputSize, uint8_t *output, size_t *outputSize) -{ - cau3_hash_ctx_t hashCtx; - status_t status; - - status = CAU3_HASH_Init(base, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = CAU3_HASH_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = CAU3_HASH_Finish(base, &hashCtx, output, outputSize); - - return status; -} - -/*! @brief CAU3 driver wait mechanism. */ -status_t cau3_wait(CAU3_Type *base) -{ - status_t status; - - bool error = false; - bool done = false; - - /* Wait for 'done' or 'error' flag. */ - while ((!error) && (!done)) - { - uint32_t temp32 = base->STA; - error = temp32 & kCAU3_StatusErrorIsr; - done = temp32 & kCAU3_StatusDoneIsr; - } - - if (error) - { - base->COM = CAU3_COM_ALL_MASK; /* Reset all engine to clear the error flag */ - status = kStatus_Fail; - } - else /* 'done' */ - { - status = kStatus_Success; - - base->CW = kCAU3_ClearDataSize; - /* Clear 'done' interrupt status. This also clears the mode register. */ - base->STA = kCAU3_StatusDoneIsr; - } - - return status; -} - -/*! - * @brief Clears the CAU3 module. - * This function can be used to clear all sensitive data from theCAU3 module, such as private keys. It is called - * internally by the CAU3 driver in case of an error or operation complete. - * @param base CAU3 peripheral base address - * @param pkha Include CAU3 PKHA register clear. If there is no PKHA, the argument is ignored. - */ -void cau3_clear_all(CAU3_Type *base, bool addPKHA) -{ - base->CW = (uint32_t)kCAU3_ClearAll; - if (addPKHA) - { - cau3_pkha_clear_regabne(base, true, true, true, true); - } -} - -/*! - * @brief Reads an unaligned word. - * - * This function creates a 32-bit word from an input array of four bytes. - * - * @param src Input array of four bytes. The array can start at any address in memory. - * @return 32-bit unsigned int created from the input byte array. - */ -static inline uint32_t cau3_get_word_from_unaligned(const uint8_t *srcAddr) -{ -#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) - register const uint8_t *src = srcAddr; - /* Cortex M0 does not support misaligned loads */ - if ((uint32_t)src & 0x3u) - { - union _align_bytes_t { - uint32_t word; - uint8_t byte[sizeof(uint32_t)]; - } my_bytes; - - my_bytes.byte[0] = *src; - my_bytes.byte[1] = *(src + 1); - my_bytes.byte[2] = *(src + 2); - my_bytes.byte[3] = *(src + 3); - return my_bytes.word; - } - else - { - /* addr aligned to 0-modulo-4 so it is safe to type cast */ - return *((const uint32_t *)src); - } -#elif defined(__CC_ARM) - /* -O3 optimization in Keil Compiler 5 uses LDM instruction here (LDM r4!, {r0}) - * which is wrong, because srcAddr might be unaligned. - * LDM on unaligned address causes hard-fault. so use memcpy() */ - uint32_t ret; - memcpy(&ret, srcAddr, sizeof(uint32_t)); - return ret; -#else - return *((const uint32_t *)srcAddr); -#endif -} - -/******************************************************************************* - * PKHA Code static - ******************************************************************************/ - -static status_t cau3_pkha_clear_regabne(CAU3_Type *base, bool A, bool B, bool N, bool E) -{ - cau3_mode_t mode; - - /* Set the PKHA algorithm and the appropriate function. */ - mode = (uint32_t)kCAU3_AlgorithmPKHA | 1U; - - /* Set ram area to clear. Clear all. */ - if (A) - { - mode |= 1U << 19U; - } - if (B) - { - mode |= 1U << 18U; - } - if (N) - { - mode |= 1U << 16U; - } - if (E) - { - mode |= 1U << 17U; - } - - /* Write the mode register to the hardware. - * NOTE: This will begin the operation. */ - base->MDPK = mode; - - /* Wait for 'done' */ - return cau3_wait(base); -} - -static void cau3_pkha_default_parms(cau3_pkha_mode_params_t *params) -{ - params->func = (cau3_pkha_func_t)0; - params->arithType = kCAU3_PKHA_IntegerArith; - params->montFormIn = kCAU3_PKHA_NormalValue; - params->montFormOut = kCAU3_PKHA_NormalValue; - params->srcReg = kCAU3_PKHA_RegAll; - params->srcQuad = kCAU3_PKHA_Quad0; - params->dstReg = kCAU3_PKHA_RegAll; - params->dstQuad = kCAU3_PKHA_Quad0; - params->equalTime = kCAU3_PKHA_NoTimingEqualized; - params->r2modn = kCAU3_PKHA_CalcR2; -} - -static void cau3_pkha_write_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index, uint32_t data) -{ - __IO uint32_t *pka = base->PKA0; - __IO uint32_t *pkb = base->PKB0; - __IO uint32_t *pkn = base->PKN0; - - switch (reg) - { - case kCAU3_PKHA_RegA: - pka[index] = data; - break; - - case kCAU3_PKHA_RegB: - pkb[index] = data; - break; - - case kCAU3_PKHA_RegN: - pkn[index] = data; - break; - - case kCAU3_PKHA_RegE: - base->PKE[index] = data; - break; - - default: - break; - } -} - -static uint32_t cau3_pkha_read_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index) -{ - uint32_t retval; - __IO uint32_t *pka = base->PKA0; - __IO uint32_t *pkb = base->PKB0; - __IO uint32_t *pkn = base->PKN0; - - switch (reg) - { - case kCAU3_PKHA_RegA: - retval = pka[index]; - break; - - case kCAU3_PKHA_RegB: - retval = pkb[index]; - break; - - case kCAU3_PKHA_RegN: - retval = pkn[index]; - break; - - default: - retval = 0; - break; - } - return retval; -} - -static status_t cau3_pkha_write_reg( - CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, const uint8_t *data, size_t dataSize) -{ - /* Select the word-based start index for each quadrant of 128 bytes. */ - uint8_t startIndex = (quad * 32u); - uint32_t outWord; - - while (dataSize > 0) - { - if (dataSize >= sizeof(uint32_t)) - { - cau3_pkha_write_word(base, reg, startIndex++, cau3_get_word_from_unaligned(data)); - dataSize -= sizeof(uint32_t); - data += sizeof(uint32_t); - } - else /* (dataSize > 0) && (dataSize < 4) */ - { - outWord = 0; - cau3_memcpy(&outWord, data, dataSize); - cau3_pkha_write_word(base, reg, startIndex, outWord); - dataSize = 0; - } - } - - return kStatus_Success; -} - -static void cau3_pkha_read_reg(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, uint8_t *data, size_t dataSize) -{ - /* Select the word-based start index for each quadrant of 128 bytes. */ - uint8_t startIndex = (quad * 32u); - size_t calcSize; - uint32_t word; - - while (dataSize > 0) - { - word = cau3_pkha_read_word(base, reg, startIndex++); - - calcSize = (dataSize >= sizeof(uint32_t)) ? sizeof(uint32_t) : dataSize; - cau3_memcpy(data, &word, calcSize); - - data += calcSize; - dataSize -= calcSize; - } -} - -static void cau3_pkha_init_data(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - const uint8_t *E, - size_t sizeE) -{ - uint32_t clearMask = kCAU3_ClearMode; /* clear Mode Register */ - - /* Clear internal register states. */ - if (sizeA) - { - clearMask |= kCAU3_ClearPkhaSizeA; - } - if (sizeB) - { - clearMask |= kCAU3_ClearPkhaSizeB; - } - if (sizeN) - { - clearMask |= kCAU3_ClearPkhaSizeN; - } - if (sizeE) - { - clearMask |= kCAU3_ClearPkhaSizeE; - } - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, A, B, N, E); - - /* Write register sizes. */ - /* Write modulus (N) and A and B register arguments. */ - if (sizeN) - { - base->PKNSZ = sizeN; - if (N) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, sizeN); - } - } - - if (sizeA) - { - base->PKASZ = sizeA; - if (A) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, A, sizeA); - } - } - - if (sizeB) - { - base->PKBSZ = sizeB; - if (B) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, B, sizeB); - } - } - - if (sizeE) - { - base->PKESZ = sizeE; - if (E) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegE, 0, E, sizeE); - } - } -} - -static void cau3_pkha_mode_set_src_reg_copy(cau3_mode_t *outMode, cau3_pkha_reg_area_t reg) -{ - int i = 0; - - do - { - reg = (cau3_pkha_reg_area_t)(((uint32_t)reg) >> 1u); - i++; - } while (reg); - - i = 4 - i; - /* Source register must not be E. */ - if (i != 2) - { - *outMode |= ((uint32_t)i << 17u); - } -} - -static void cau3_pkha_mode_set_dst_reg_copy(cau3_mode_t *outMode, cau3_pkha_reg_area_t reg) -{ - int i = 0; - - do - { - reg = (cau3_pkha_reg_area_t)(((uint32_t)reg) >> 1u); - i++; - } while (reg); - - i = 4 - i; - *outMode |= ((uint32_t)i << 10u); -} - -static void cau3_pkha_mode_set_src_seg_copy(cau3_mode_t *outMode, const cau3_pkha_quad_area_t quad) -{ - *outMode |= ((uint32_t)quad << 8u); -} - -static void cau3_pkha_mode_set_dst_seg_copy(cau3_mode_t *outMode, const cau3_pkha_quad_area_t quad) -{ - *outMode |= ((uint32_t)quad << 6u); -} - -/*! - * @brief Starts the PKHA operation. - * - * This function starts an operation configured by the params parameter. - * - * @param base CAU3 peripheral base address - * @param params Configuration structure containing all settings required for PKHA operation. - */ -static status_t cau3_pkha_init_mode(CAU3_Type *base, const cau3_pkha_mode_params_t *params) -{ - cau3_mode_t modeReg; - status_t retval; - - /* Set the PKHA algorithm and the appropriate function. */ - modeReg = kCAU3_AlgorithmPKHA; - modeReg |= (uint32_t)params->func; - - if ((params->func == kCAU3_PKHA_CopyMemSizeN) || (params->func == kCAU3_PKHA_CopyMemSizeSrc)) - { - /* Set source and destination registers and quads. */ - cau3_pkha_mode_set_src_reg_copy(&modeReg, params->srcReg); - cau3_pkha_mode_set_dst_reg_copy(&modeReg, params->dstReg); - cau3_pkha_mode_set_src_seg_copy(&modeReg, params->srcQuad); - cau3_pkha_mode_set_dst_seg_copy(&modeReg, params->dstQuad); - } - else - { - /* Set the arithmetic type - integer or binary polynomial (F2m). */ - modeReg |= ((uint32_t)params->arithType << 17u); - - /* Set to use Montgomery form of inputs and/or outputs. */ - modeReg |= ((uint32_t)params->montFormIn << 19u); - modeReg |= ((uint32_t)params->montFormOut << 18u); - - /* Set to use pre-computed R2modN */ - modeReg |= ((uint32_t)params->r2modn << 16u); - } - - modeReg |= ((uint32_t)params->equalTime << 10u); - - /* Write the mode register to the hardware. - * NOTE: This will begin the operation. */ - base->MDPK = modeReg; - - retval = cau3_wait(base); - return (retval); -} - -static status_t cau3_pkha_modR2( - CAU3_Type *base, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, cau3_pkha_f2m_t arithType) -{ - status_t status; - cau3_pkha_mode_params_t params; - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModR2; - params.arithType = arithType; - - cau3_pkha_init_data(base, NULL, 0, NULL, 0, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - return status; -} - -static status_t cau3_pkha_modmul(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType, - cau3_pkha_montgomery_form_t montIn, - cau3_pkha_montgomery_form_t montOut, - cau3_pkha_timing_t equalTime) -{ - cau3_pkha_mode_params_t params; - status_t status; - - if (arithType == kCAU3_PKHA_IntegerArith) - { - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (CAU3_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModMul; - params.arithType = arithType; - params.montFormIn = montIn; - params.montFormOut = montOut; - params.equalTime = equalTime; - - cau3_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - return status; -} - -/******************************************************************************* - * PKHA Code public - ******************************************************************************/ -int CAU3_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB) -{ - int retval = 0; - - /* skip zero msbytes - integer a */ - while ((sizeA) && (0u == a[sizeA - 1])) - { - sizeA--; - } - - /* skip zero msbytes - integer b */ - while ((sizeB) && (0u == b[sizeB - 1])) - { - sizeB--; - } - - if (sizeA > sizeB) - { - retval = 1; - } /* int a has more non-zero bytes, thus it is bigger than b */ - else if (sizeA < sizeB) - { - retval = -1; - } /* int b has more non-zero bytes, thus it is bigger than a */ - else if (sizeA == 0) - { - retval = 0; - } /* sizeA = sizeB = 0 */ - else - { - int n; - int i; - int val; - uint32_t equal; - - n = sizeA - 1; - i = 0; - equal = 0; - - while (n >= 0) - { - uint32_t chXor = a[i] ^ b[i]; - - equal |= chXor; - val = (int)chXor * (a[i] - b[i]); - - if (val < 0) - { - retval = -1; - } - - if (val > 0) - { - retval = 1; - } - - if (val == 0) - { - val = 1; - } - - if (val) - { - i++; - n--; - } - } - - if (0 == equal) - { - retval = 0; - } - } - return (retval); -} - -status_t CAU3_PKHA_NormalToMontgomery(CAU3_Type *base, - const uint8_t *N, - size_t sizeN, - uint8_t *A, - size_t *sizeA, - uint8_t *B, - size_t *sizeB, - uint8_t *R2, - size_t *sizeR2, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType) -{ - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - /* need to convert our Integer inputs into Montgomery format */ - if (N && sizeN && R2 && sizeR2) - { - /* 1. R2 = MOD_R2(N) */ - status = cau3_pkha_modR2(base, N, sizeN, R2, sizeR2, arithType); - if (status != kStatus_Success) - { -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; - } - - /* 2. A(Montgomery) = MOD_MUL_IM_OM(A, R2, N) */ - if (A && sizeA) - { - status = cau3_pkha_modmul(base, A, *sizeA, R2, *sizeR2, N, sizeN, A, sizeA, arithType, - kCAU3_PKHA_MontgomeryFormat, kCAU3_PKHA_MontgomeryFormat, equalTime); - if (status != kStatus_Success) - { -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; - } - } - - /* 2. B(Montgomery) = MOD_MUL_IM_OM(B, R2, N) */ - if (B && sizeB) - { - status = cau3_pkha_modmul(base, B, *sizeB, R2, *sizeR2, N, sizeN, B, sizeB, arithType, - kCAU3_PKHA_MontgomeryFormat, kCAU3_PKHA_MontgomeryFormat, equalTime); - if (status != kStatus_Success) - { -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; - } - } - - cau3_clear_all(base, true); - } - else - { - status = kStatus_InvalidArgument; - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_MontgomeryToNormal(CAU3_Type *base, - const uint8_t *N, - size_t sizeN, - uint8_t *A, - size_t *sizeA, - uint8_t *B, - size_t *sizeB, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType) -{ - uint8_t one = 1; - status_t status = kStatus_InvalidArgument; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - /* A = MOD_MUL_IM_OM(A(Montgomery), 1, N) */ - if (A && sizeA) - { - status = cau3_pkha_modmul(base, A, *sizeA, &one, sizeof(one), N, sizeN, A, sizeA, arithType, - kCAU3_PKHA_MontgomeryFormat, kCAU3_PKHA_MontgomeryFormat, equalTime); - if (kStatus_Success != status) - { -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; - } - } - - /* B = MOD_MUL_IM_OM(B(Montgomery), 1, N) */ - if (B && sizeB) - { - status = cau3_pkha_modmul(base, B, *sizeB, &one, sizeof(one), N, sizeN, B, sizeB, arithType, - kCAU3_PKHA_MontgomeryFormat, kCAU3_PKHA_MontgomeryFormat, equalTime); - if (kStatus_Success != status) - { -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModAdd(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType) -{ - cau3_pkha_mode_params_t params; - status_t status; - - if (arithType == kCAU3_PKHA_IntegerArith) - { - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (CAU3_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModAdd; - params.arithType = arithType; - - cau3_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModSub1(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize) -{ - cau3_pkha_mode_params_t params; - status_t status; - - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - - if (CAU3_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModSub1; - cau3_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModSub2(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize) -{ - cau3_pkha_mode_params_t params; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModSub2; - - cau3_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModMul(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType, - cau3_pkha_montgomery_form_t montIn, - cau3_pkha_montgomery_form_t montOut, - cau3_pkha_timing_t equalTime) -{ - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - status = - cau3_pkha_modmul(base, A, sizeA, B, sizeB, N, sizeN, result, resultSize, arithType, montIn, montOut, equalTime); - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModExp(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - const uint8_t *E, - size_t sizeE, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType, - cau3_pkha_montgomery_form_t montIn, - cau3_pkha_timing_t equalTime) -{ - cau3_pkha_mode_params_t params; - status_t status; - - if (arithType == kCAU3_PKHA_IntegerArith) - { - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModExp; - params.arithType = arithType; - params.montFormIn = montIn; - params.equalTime = equalTime; - - cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, E, sizeE); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModSqrt(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize) -{ - cau3_pkha_mode_params_t params; - status_t status; - - /* A < N */ - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModSqrt; - - cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModRed(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType) -{ - cau3_pkha_mode_params_t params; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModRed; - params.arithType = arithType; - - cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModInv(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType) -{ - cau3_pkha_mode_params_t params; - status_t status; - - /* A must be less than N -> CAU3_PKHA_CompareBigNum() must return -1 */ - if (arithType == kCAU3_PKHA_IntegerArith) - { - if (CAU3_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0) - { - return (kStatus_InvalidArgument); - } - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModInv; - params.arithType = arithType; - - cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModR2( - CAU3_Type *base, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, cau3_pkha_f2m_t arithType) -{ - status_t status; -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - status = cau3_pkha_modR2(base, N, sizeN, result, resultSize, arithType); - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModRR( - CAU3_Type *base, const uint8_t *P, size_t sizeP, size_t sizeE, uint8_t *result, size_t *resultSize) -{ - status_t status; - cau3_pkha_mode_params_t params; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithModRR; - - cau3_pkha_init_data(base, NULL, 0, NULL, 0, P, sizeP, NULL, sizeE); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ModGcd(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType) -{ - cau3_pkha_mode_params_t params; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithGcd; - params.arithType = arithType; - - cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the result and size from register B0. */ - if (resultSize && result) - { - *resultSize = base->PKBSZ; - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, result, *resultSize); - } - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_PrimalityTest(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - bool *res) -{ - uint8_t result; - cau3_pkha_mode_params_t params; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithPrimalityTest; - cau3_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 0, &result, 1); - - *res = (bool)result; - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECC_PointAdd(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEccAdd; - params.arithType = arithType; - params.r2modn = R2modN ? kCAU3_PKHA_InputR2 : kCAU3_PKHA_CalcR2; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, false); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, A->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 1, A->Y, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, bCurveParam, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, B->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 2, B->Y, size); - if (R2modN) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 3, R2modN, size); - } - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, result->X, size); - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 2, result->Y, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECC_PointDouble(CAU3_Type *base, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEccDouble; - params.arithType = arithType; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, false); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, bCurveParam, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, B->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 2, B->Y, size); - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, result->X, size); - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 2, result->Y, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECC_PointMul(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const uint8_t *E, - size_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEccMul; - params.equalTime = equalTime; - params.arithType = arithType; - params.r2modn = R2modN ? kCAU3_PKHA_InputR2 : kCAU3_PKHA_CalcR2; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, true); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKESZ = sizeE; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegE, 0, E, sizeE); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, A->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 1, A->Y, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, bCurveParam, size); - if (R2modN) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, R2modN, size); - } - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, result->X, size); - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 2, result->Y, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECM_PointMul(CAU3_Type *base, - const uint8_t *E, - size_t sizeE, - const uint8_t *inputCoordinate, - const uint8_t *A24, - const uint8_t *N, - const uint8_t *R2modN, - size_t size, - cau3_pkha_timing_t equalTime, - uint8_t *outputCoordinate) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEcmMul; - params.equalTime = equalTime; - params.r2modn = R2modN ? kCAU3_PKHA_InputR2 : kCAU3_PKHA_CalcR2; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, true); - - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKESZ = sizeE; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegE, 0, E, sizeE); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, inputCoordinate, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, A24, size); - - if (R2modN) - { - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, R2modN, size); - } - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, outputCoordinate, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECT_PointMul(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const uint8_t *E, - size_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *dCurveParam, - size_t size, - cau3_pkha_timing_t equalTime, - cau3_pkha_ecc_point_t *result) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEctMul; - params.equalTime = equalTime; - params.r2modn = R2modN ? kCAU3_PKHA_InputR2 : kCAU3_PKHA_CalcR2; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, true); - - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKESZ = sizeE; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegE, 0, E, sizeE); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, A->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 1, A->Y, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, dCurveParam, size); - if (R2modN) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, R2modN, size); - } - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, result->X, size); - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 2, result->Y, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_PKHA_ECT_PointAdd(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *dCurveParam, - size_t size, - cau3_pkha_ecc_point_t *result) -{ - cau3_pkha_mode_params_t params; - uint32_t clearMask; - status_t status; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - status = cau3_lock_semaphore(base); - if (kStatus_Success != status) - { - cau3_release_semaphore(base); - return status; - } -#endif - - cau3_pkha_default_parms(¶ms); - params.func = kCAU3_PKHA_ArithEctAdd; - params.r2modn = R2modN ? kCAU3_PKHA_InputR2 : kCAU3_PKHA_CalcR2; - - clearMask = kCAU3_ClearMode; - - /* Clear internal register states. */ - clearMask |= kCAU3_ClearPkhaSizeA; - clearMask |= kCAU3_ClearPkhaSizeB; - clearMask |= kCAU3_ClearPkhaSizeN; - clearMask |= kCAU3_ClearPkhaSizeE; - - base->CW = clearMask; - base->STA = kCAU3_StatusDoneIsr; - cau3_pkha_clear_regabne(base, true, true, true, false); - - /* sizeN should be less than 64 bytes. */ - base->PKNSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegN, 0, N, size); - - base->PKASZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 0, A->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 1, A->Y, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegA, 3, aCurveParam, size); - - base->PKBSZ = size; - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 0, dCurveParam, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 1, B->X, size); - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 2, B->Y, size); - if (R2modN) - { - cau3_pkha_write_reg(base, kCAU3_PKHA_RegB, 3, R2modN, size); - } - - status = cau3_pkha_init_mode(base, ¶ms); - - if (status == kStatus_Success) - { - /* Read the data from the result register into place. */ - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 1, result->X, size); - cau3_pkha_read_reg(base, kCAU3_PKHA_RegB, 2, result->Y, size); - } - - cau3_clear_all(base, true); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return status; -} - -status_t CAU3_TDES_CheckParity(CAU3_Type *base, cau3_key_slot_t keySlot) -{ - status_t completionStatus; - cau3_task_done_t taskDone; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - taskDone = kCAU3_TaskDonePoll; - - /* execute the cau3 "3des_check_parity" task */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_3DES_CHECK_PARITY; /* call cau_3des_chk_parity() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_TDES_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize) -{ - /* only work with aligned key[] */ - if (0x3U & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - /* keySize must be 24. */ - if (keySize != 24U) - { - return kStatus_InvalidArgument; - } - - return cau3_load_key(base, key, keySize, handle->keySlot, handle->taskDone); -} - -status_t CAU3_TDES_Encrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "3des_encrypt_ecb" task */ - base->CC_R[16] = (uintptr_t)plaintext; /* pPlainText */ - base->CC_R[17] = handle->keySlot; /* keySlot */ - base->CC_R[19] = (uintptr_t)ciphertext; /* pCipherText */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_3DES_ENCRYPT; /* call cau_3des_encrypt() */ - base->CC_CMD = handle->taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, handle->taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_TDES_Decrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext) -{ - status_t completionStatus; - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - /* execute the cau3 "3des_decrypt_ecb" task */ - base->CC_R[16] = (uintptr_t)ciphertext; /* pCipherText */ - base->CC_R[17] = handle->keySlot; /* keySlot */ - base->CC_R[19] = (uintptr_t)plaintext; /* pPlainText */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_3DES_DECRYPT; /* call cau_3des_decrypt() */ - base->CC_CMD = handle->taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, handle->taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_CHACHA20_POLY1305_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize) -{ - /* only work with aligned key[] */ - if (0x3U & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - /* keySize must be 32. */ - if (keySize != 32U) - { - return kStatus_InvalidArgument; - } - - union { - uint8_t b[32]; - uint32_t w[8]; - } tempKey; - - for (int i = 0; i < ARRAY_SIZE(tempKey.w); i++) - { - tempKey.w[i] = __REV(((const uint32_t *)(uintptr_t)key)[i]); - } - - return cau3_load_key(base, tempKey.b, keySize, handle->keySlot, handle->taskDone); -} - -static status_t cau3_load_nonce(CAU3_Type *base, const uint8_t *nonce, cau3_key_slot_t keySlot) -{ - union { - uint8_t b[16]; - uint32_t w[4]; - } tempIv; - - memset(&tempIv, 0, sizeof(tempIv)); - - /* set nonce to keySlot */ - memcpy(tempIv.b, nonce, 12); - /* swap bytes */ - tempIv.w[0] = __REV(tempIv.w[0]); - tempIv.w[1] = __REV(tempIv.w[1]); - tempIv.w[2] = __REV(tempIv.w[2]); - - return CAU3_LoadKeyInitVector(base, tempIv.b, keySlot, kCAU3_TaskDonePoll); -} - -status_t CAU3_CHACHA20_POLY1305_Encrypt(CAU3_Type *base, - cau3_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t *aad, - size_t aadLen, - const uint8_t *nonce, - uint8_t *tag) -{ - status_t completionStatus; - - completionStatus = cau3_load_nonce(base, nonce, handle->keySlot); - if (kStatus_Success != completionStatus) - { - return completionStatus; - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - base->CC_R[17] = handle->keySlot; /* key/iv slot */ - base->CC_R[18] = (uintptr_t)aad; /* AAD pointer */ - base->CC_R[19] = aadLen; /* AAD length (bytes) */ - base->CC_R[20] = (uintptr_t)plaintext; /* Plaintext pointer */ - base->CC_R[21] = size; /* Plaintext length */ - base->CC_R[22] = (uintptr_t)ciphertext; /* Ciphertext pointer */ - base->CC_R[23] = (uintptr_t)tag; /* Tag pointer */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_CHA_POLY_ENCRYPT; /* ChaChaPoly encrypt vector */ - base->CC_CMD = handle->taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, handle->taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_CHACHA20_POLY1305_Decrypt(CAU3_Type *base, - cau3_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t *aad, - size_t aadLen, - const uint8_t *nonce, - const uint8_t *tag) -{ - status_t completionStatus; - - completionStatus = cau3_load_nonce(base, nonce, handle->keySlot); - if (kStatus_Success != completionStatus) - { - return completionStatus; - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - base->CC_R[17] = handle->keySlot; /* key/iv slot */ - base->CC_R[18] = (uintptr_t)aad; /* AAD pointer */ - base->CC_R[19] = aadLen; /* AAD length (bytes) */ - base->CC_R[20] = (uintptr_t)ciphertext; /* Ciphertext pointer */ - base->CC_R[21] = size; /* Cyphertext length */ - base->CC_R[22] = (uintptr_t)plaintext; /* Plaintext pointer */ - base->CC_R[23] = (uintptr_t)tag; /* Tag pointer */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_CHA_POLY_DECRYPT; /* ChaChaPoly decrypt vector */ - base->CC_CMD = handle->taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, handle->taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} - -status_t CAU3_KeyBlobUnwrap(CAU3_Type *base, - cau3_key_slot_t keySlot, - const uint8_t *keyBlob, - uint32_t numberOfBlocks, - cau3_key_slot_t dstContext) -{ - status_t completionStatus; - cau3_task_done_t taskDone; - - if (0x3U & (uintptr_t)keyBlob) - { - return kStatus_InvalidArgument; - } - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - completionStatus = cau3_lock_semaphore(base); - if (kStatus_Success != completionStatus) - { - cau3_release_semaphore(base); - return completionStatus; - } -#endif - - taskDone = kCAU3_TaskDonePoll; - - /* execute the cau3 "key blob unwrap" task */ - base->CC_R[16] = (uintptr_t)keyBlob; /* pKeyBlob */ - base->CC_R[17] = keySlot; /* keySlot */ - base->CC_R[18] = numberOfBlocks; /* numberOfBlocks */ - base->CC_R[19] = dstContext; /* destination key context */ - base->CC_R30 = CAU3_DMEM_STK_BASE; /* initialize stack pointer (sp) */ - base->CC_R31 = 0U; /* set LR = 0 to signal a host task */ - base->CC_PC = CAU3_TASK_KEY_BLOB_UNWRAP; /* call cau_key_blob_unwrap() */ - base->CC_CMD = taskDone; /* trigger cau3 execution */ - - /* process the cau3 task completion signal specified by taskDone */ - completionStatus = cau3_process_task_completion(base, taskDone); -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) - cau3_release_semaphore(base); -#endif - return (completionStatus); -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.h deleted file mode 100644 index ce61df9e80724d0f13e4a525d0433b6e4c63268d..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_cau3.h +++ /dev/null @@ -1,1245 +0,0 @@ -/* - * Copyright (c) 2017-2018, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CAU3_H_ -#define _FSL_CAU3_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup cau3_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief CAU3 driver version. Version 2.0.2. - * - * Current version: 2.0.2 - * - * Change log: - * - Version 2.0.0 - * - Initial version - * - Version 2.0.1 - * - Replace static cau3_make_mems_private() with public CAU3_MakeMemsPrivate(). - * - Remove the cau3_make_mems_private() from CAU3_Init to allow loading multiple images. - * - Version 2.0.2 - * - Add FSL_CAU3_USE_HW_SEMA compile time macro. When enabled, all CAU3 API functions - * lock hw semaphore on function entry and release the hw semaphore on function return. - */ -#define FSL_CAU3_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief Hardware semaphore usage by driver functions. - * This macro can be enabled for mutual exclusive calls to CAU3 APIs - * from multiple CPUs. Note this does not lock against calls from multiple threads on one CPU. - */ - -/* #define FSL_CAU3_USE_HW_SEMA 1 */ - -#if defined(FSL_CAU3_USE_HW_SEMA) && (FSL_CAU3_USE_HW_SEMA > 0) -/* Using SEMA42 hardware semaphore for multiprocessor locking. - * Currently supporting only SEMA42 hardware semaphore. - */ -#if defined(FSL_FEATURE_SOC_SEMA42_COUNT) && (FSL_FEATURE_SOC_SEMA42_COUNT > 0) -#include "fsl_sema42.h" -#define FSL_CAU3_SEMA42_BASE SEMA420 -#define FSL_CAU3_SEMA42_GATE (1) -#define FSL_CAU3_SEMA42_CLOCK_NAME kCLOCK_Sema420 -#else -#error FSL_CAU3_USE_HW_SEMA requires SEMA42 semaphore. -#endif -#endif - -/*! @brief CAU3 key slot selection. Current CryptoCore firmware supports 4 key slots inside CryptoCore's Private DMEM. - * - */ -typedef enum _cau3_key_slot { - kCAU3_KeySlot0 = 0x0U, /*!< CAU3 key slot 0. */ - kCAU3_KeySlotNone = 0x0U, /*!< No key. */ - kCAU3_KeySlot1 = 0x1U, /*!< CAU3 key slot 1. */ - kCAU3_KeySlot2 = 0x2U, /*!< CAU3 key slot 2.*/ - kCAU3_KeySlot3 = 0x3U, /*!< CAU3 key slot 3. */ -} cau3_key_slot_t; - -/*! @brief CAU3 task done selection. */ -typedef enum _cau3_task_done { - kCAU3_TaskDoneNull = 0x00000000U, /*!< */ - kCAU3_TaskDonePoll = 0x00000000U, /*!< Poll CAU3 status flag. */ - kCAU3_TaskDoneIrq = 0x00010000U, /*!< Start operation and return. CAU3 asserts interrupt request when done. */ - kCAU3_TaskDoneEvent = 0x00020000U, /*!< Call Wait-for-event opcode until CAU3 completes processing. */ - kCAU3_TaskDoneDmaRequest = 0x00040000, /*!< Start operation and return. CAU3 asserts DMA request when done. */ -} cau3_task_done_t; - -/*! @brief Specify CAU3's key resource and signalling to be used for an operation. */ -typedef struct _cau3_handle -{ - cau3_task_done_t taskDone; /*!< Specify CAU3 task done signalling to Host CPU. */ - cau3_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify CAU3 key slot. */ -} cau3_handle_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup cau3_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define CAU3_AES_BLOCK_SIZE 16 - -/*! - *@} - */ /* end of cau3_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup cau3_driver_hash - * @{ - */ - -/*! @brief Supported cryptographic block cipher functions for HASH creation */ -typedef enum _cau3_hash_algo_t { - kCAU3_Sha1, /*!< SHA_1 */ - kCAU3_Sha256, /*!< SHA_256 */ -} cau3_hash_algo_t; - -/*! @brief CAU3 HASH Context size. */ -#define CAU3_SHA_BLOCK_SIZE 128 /*!< internal buffer block size */ -#define CAU3_HASH_BLOCK_SIZE CAU3_SHA_BLOCK_SIZE /*!< CAU3 hash block size */ - -/*! @brief CAU3 HASH Context size. */ -#define CAU3_HASH_CTX_SIZE 58 - -/*! @brief Storage type used to save hash context. */ -typedef struct _cau3_hash_ctx_t -{ - uint32_t x[CAU3_HASH_CTX_SIZE]; -} cau3_hash_ctx_t; - -/*! - *@} - */ /* end of cau3_driver_hash */ - -/******************************************************************************* - * PKHA Definitions - ******************************************************************************/ -/*! - * @addtogroup cau3_driver_pkha - * @{ - */ - -/*! PKHA ECC point structure */ -typedef struct _cau3_pkha_ecc_point_t -{ - uint8_t *X; /*!< X coordinate (affine) */ - uint8_t *Y; /*!< Y coordinate (affine) */ -} cau3_pkha_ecc_point_t; - -/*! @brief Use of timing equalized version of a PKHA function. */ -typedef enum _cau3_pkha_timing_t { - kCAU3_PKHA_NoTimingEqualized = 0U, /*!< Normal version of a PKHA operation */ - kCAU3_PKHA_TimingEqualized = 1U /*!< Timing-equalized version of a PKHA operation */ -} cau3_pkha_timing_t; - -/*! @brief Integer vs binary polynomial arithmetic selection. */ -typedef enum _cau3_pkha_f2m_t { - kCAU3_PKHA_IntegerArith = 0U, /*!< Use integer arithmetic */ - kCAU3_PKHA_F2mArith = 1U /*!< Use binary polynomial arithmetic */ -} cau3_pkha_f2m_t; - -/*! @brief Montgomery or normal PKHA input format. */ -typedef enum _cau3_pkha_montgomery_form_t { - kCAU3_PKHA_NormalValue = 0U, /*!< PKHA number is normal integer */ - kCAU3_PKHA_MontgomeryFormat = 1U /*!< PKHA number is in montgomery format */ -} cau3_pkha_montgomery_form_t; - -/*! - *@} - */ /* cau3_driver_pkha */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup cau3_driver - * @{ - */ - -/*! - * @brief Enables clock for CAU3 and loads image to memory - * - * Enable CAU3 clock and loads image to CryptoCore. - * - * @param base CAU3 base address - */ -void CAU3_Init(CAU3_Type *base); - -/*! - * @brief Execute a CAU3 null task to signal error termination - * - * Execute a null task to signal error termination. - * The CryptoCore task executes one instruction - a "stop with error". - * - * @param base CAU3 base address - * @param taskDone indicates completion signal - * - * @return status check from task completion - */ -status_t CAU3_ForceError(CAU3_Type *base, cau3_task_done_t taskDone); - -/*! - * @brief Load special hardware "key context" into the CAU3's data memory - * - * Load the special hardware key context into the private DMEM. This only - * includes the complete 256-bit key which is then specified with a size of - * [8,16,24,32] bytes (for DES or AES-[128,256]). It also loads the - * default IV value specified in NIST/RFC2294 IV=0xa6a6a6a6a6a6a6a6. This operation typically - * loads keySlot 0, which, by convention, is used for the system key encryption - * key. - * - * See the GENERAL COMMENTS for more information on the keyContext structure. - * - * NOTE: This function also performs an AES key expansion if a keySize > 8 - * is specified. - * - * @param base CAU3 base address - * @param keySize is the logical key size in bytes [8,16,24,32] - * @param keySlot is the destination key slot number [0-3] - * @param taskDone indicates completion signal. - * - * @return status check from task completion - */ -status_t CAU3_LoadSpecialKeyContext(CAU3_Type *base, - size_t keySize, - cau3_key_slot_t keySlot, - cau3_task_done_t taskDone); - -/*! - * @brief Invalidate a 64-byte "key context" in the CAU3's private data memory - * - * Clears the key context in the private DMEM. There is support for four "key - * slots" with slot 0 typically used for the system key encryption key. - * - * @param base CAU3 base address - * @param keySlot is the key slot number [0-3] to invalidate - * @param taskDone indicates completion signal * - * @return status check from task completion - */ -status_t CAU3_ClearKeyContext(CAU3_Type *base, cau3_key_slot_t keySlot, cau3_task_done_t taskDone); - -/*! - * @brief Load an initialization vector into a key context - * - * Loads a 16-byte initialization vector (iv) into the specified key slot. - * There is support for a maximum of 4 key slots. - * The function is used internally for loading AEAD_CHACHA20_POY1305 nonce. - * It can be also used for Alternative Initial Values for A[0] in RFC 3394. - * - * @param base CAU3 base address - * @param iv The initialization vector, ALIGNED ON A 0-MOD-4 ADDRESS. - * @param keySlot is the destination key context - * @param taskDone indicates completion signal - * - * @return status check from task completion - */ -status_t CAU3_LoadKeyInitVector(CAU3_Type *base, const uint8_t *iv, cau3_key_slot_t keySlot, cau3_task_done_t taskDone); - -/*! - * @brief Make the CAU3's local memories private - * - * Modify the CAU3's internal configuration so the local memories are private - * and only accessible to the CAU3. This operation is typically performed after - * the CAU_InitializeInstMemory(), - * CAU_InitializeDataMemory(), and - * CAU_InitializeReadOnlyDataMemory() functions have been performed. - * - * This configuration remains in effect until the next hardware reset. - * - * @param taskDone indicates completion signal: CAU_[POLL, IRQ, EVENT, DMAREQ] - * - * @retval status check from task completion: CAU_[OK, ERROR] - */ -status_t CAU3_MakeMemsPrivate(CAU3_Type *base, cau3_task_done_t taskDone); - -/*! - *@} - */ /* end of cau3_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup cau3_driver_aes - * @{ - */ - -/*! - * @brief Load AES key into CAU3 key slot. - * - * Load the key context into the private DMEM. This function also performs an AES key expansion. - * For CAU3 AES encryption/decryption/cmac, users only need to call one of @ref CAU3_AES_SetKey and @ref - * CAU3_LoadSpecialKeyContext. - * - * CAU3_AES_SetKey - * @param base CAU3 peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16 or 32. - * @return status from set key operation - */ -status_t CAU3_AES_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one 128-bit block. - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base CAU3 peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @return Status from encrypt operation - */ -status_t CAU3_AES_Encrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t plaintext[16], uint8_t ciphertext[16]); - -/*! - * @brief Decrypts AES on one 128-bit block. - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base CAU3 peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @return Status from decrypt operation - */ -status_t CAU3_AES_Decrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t ciphertext[16], uint8_t plaintext[16]); - -/*! - * @brief Perform an AES-128 cipher-based authentication code (CMAC) - * - * Performs an AES-128 cipher-based authentication code (CMAC) on a - * message. RFC 4493. - * - * @param base CAU3 peripheral base address - * @param handle Handle used for this request. - * @param message is source uint8_t array of data bytes, any alignment - * @param size Number of bytes in the message. - * @param mac is the output 16 bytes MAC, must be a 0-mod-4 aligned address - * @return status check from task completion - */ -status_t CAU3_AES_Cmac(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *message, size_t size, uint8_t *mac); - -/*! - * @brief Perform an AES key expansion for specified key slot - * - * Performs an AES key expansion (aka schedule) on the specified key slot. It - * uses the keySize information in the context to determine whether the key - * expansion applies to a 128- or 256-bit AES key. - * This function is primarily intended to be called after - * key blob has been unwrapped by @ref CAU3_KeyBlobUnwrap to destination key slot, so that the unwrapped key - * can be used for AES encryption. - * - * @param base CAU3 base address - * @param keySlot is the key context - * @param taskDone indicates completion signal - * @return status check from task completion - */ -status_t CAU3_AES_KeyExpansion(CAU3_Type *base, cau3_key_slot_t keySlot, cau3_task_done_t taskDone); - -/*! - *@} - */ /* end of cau3_driver_aes */ - -/******************************************************************************* - * DES API - ******************************************************************************/ -/*! - * @addtogroup cau3_driver_des - * @{ - */ - -/*! - * @brief Perform a 3DES key parity check - * - * Performs a 3DES key parity check on three 8-byte keys. - * The function is blocking. - * - * @param base CAU3 peripheral base address - * @param keySlot defines the key context to be used in the parity check - * - * @return status check from task completion - */ -status_t CAU3_TDES_CheckParity(CAU3_Type *base, cau3_key_slot_t keySlot); - -/*! - * @brief Load DES key into CAU3 key slot. - * - * Load the key context into the private DMEM. - * - * @param base CAU3 peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to 3DES key. - * @param keySize 3DES key size in bytes. Shall equal 24. - * @return status from set key operation - */ -status_t CAU3_TDES_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Perform a 3DES encryption - * - * Performs a 3DES "electronic code book" encryption on one 8-byte data block. - * The source plaintext and destination ciphertext can overlap in system memory. - * Supports both blocking and non-blocking task completion. - * - * @param base CAU3 peripheral base address. - * @param handle Handle used for this request. - * @param plaintext is source uint8_t array of data bytes, any alignment - * @param ciphertext is destination uint8_t array of data byte, any alignment - * - * @return status check from task completion - */ -status_t CAU3_TDES_Encrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext); - -/*! - * @brief Perform a 3DES decryption - * - * Performs a 3DES "electronic code book" decryption on one 8-byte data block. - * The source ciphertext and destination plaintext can overlap in sysMemory. - * Supports both blocking and non-blocking task completion. - * - * @param base CAU3 peripheral base address. - * @param handle Handle used for this request. - * @param ciphertext is destination uint8_t array of data byte, any alignment - * @param plaintext is source uint8_t array of data bytes, any alignment - * @return status check from task completion - */ -status_t CAU3_TDES_Decrypt(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext); - -/*! - *@} - */ /* end of cau3_driver_des */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup cau3_driver_hash - * @{ - */ -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * For blocking CAU3 HASH API, the HASH context contains all information required for context switch, - * such as running hash. - * - * @param base CAU3 peripheral base address - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t CAU3_HASH_Init(CAU3_Type *base, cau3_hash_ctx_t *ctx, cau3_hash_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash or mac - * has been updated (CAU3 has processed the input data), so the memory at @ref input pointer - * can be released back to system. The context is updated with the running hash or mac - * and with all necessary information to support possible context switch. - * - * @param base CAU3 peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t CAU3_HASH_Update(CAU3_Type *base, cau3_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by CAU3_HASH_Update()) and erases the context. - * - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the hash finish operation - */ -status_t CAU3_HASH_Finish(CAU3_Type *base, cau3_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA in one function call. The function is blocking. - * - * @param base CAU3 peripheral base address - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t CAU3_HASH(CAU3_Type *base, - cau3_hash_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - *@} - */ /* end of cau3_driver_hash */ - -/******************************************************************************* - * AEAD API - ******************************************************************************/ - -/*! - * @addtogroup cau3_driver_chacha_poly - * @{ - */ - -/*! - * @brief Load 256-bit key into CAU3 key context (in key slot). - * - * Load the key context into the private DMEM for CHACHA20_POLY1305 AEAD. - * - * @param base CAU3 peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to CHACHA20_POLY1305 256-bit key. - * @param keySize Size of the key in bytes. Shall be 32. - * @return status from set key operation - */ -status_t CAU3_CHACHA20_POLY1305_SetKey(CAU3_Type *base, cau3_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Perform ChaCha-Poly encryption/authentication - * - * Perform ChaCha encryption over a message of "n" bytes, and authentication - * over the encrypted data plus an additional authenticated data, - * returning encrypted data + a message digest. - * - * @param base CAU3 peripheral base address - * @param handle Handle used for this request. The keySlot member specifies key context with key and IV. - * @param plaintext The uint8_t source message to be encrypted, any alignment - * @param[out] ciphertext is a pointer to the output encrypted message, any aligment - * @param size The length of the plaintext and ciphertext in bytes - * @param aad A pointer to the additional authenticated data, any alignment - * @param aadLen Length of additional authenticated data in bytes - * @param nonce 0-mod-4 aligned pointer to CHACHA20_POLY1305 96-bit nonce. - * @param[out] tag A pointer to the 128-bit message digest output, any alignment - * - * @return status check from task completion - */ -status_t CAU3_CHACHA20_POLY1305_Encrypt(CAU3_Type *base, - cau3_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t *aad, - size_t aadLen, - const uint8_t *nonce, - uint8_t *tag); - -/*! - * @brief Perform ChaCha-Poly decryption/authentication check - * - * Perform ChaCha decryption over a message of "n" bytes, and checks - * authentication over the encrypted data plus an additional authenticated data, - * returning decrypted data. IF the tag authentication fails, the task terminates with error and - * the output is forced to zero. - * - * @param base CAU3 peripheral base address - * @param handle Handle used for this request. The keySlot member specifies key context with key and IV. - * @param ciphertext The uint8_t source msg to be decrypted, any alignment - * @param[out] plaintext A pointer to the output decrypted message, any alignment - * @param size Length of the plaintext and ciphertext in bytes - * @param aad A pointer to the additional authenticated data, any alignment - * @param aadLen Length of additional authenticated data in bytes - * @param nonce 0-mod-4 aligned pointer to CHACHA20_POLY1305 96-bit nonce. - * @param tag A pointer to the 128-bit msg digest input to be checked, any alignment - * - * @return status check from task completion - * - */ -status_t CAU3_CHACHA20_POLY1305_Decrypt(CAU3_Type *base, - cau3_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t *aad, - size_t aadLen, - const uint8_t *nonce, - const uint8_t *tag); - -/*! - *@} - */ /* end of cau3_driver_chacha_poly */ - -/******************************************************************************* - * BLOB API - ******************************************************************************/ - -/*! - * @addtogroup cau3_driver_blob - * @{ - */ - -/*! - * @brief Perform an RFC3394 key blob unwrap - * - * Perform an RFC3394 unwrap of an AES encrypted key blob. The unwrapped - * key blob is loaded into the specified key slot [1-3]. The initial - * special hardware KEK contained in key slot 0 is typically used for the - * unwrapping operation. The destination context number must be different than - * the keySlot used for unwrapping. - * Implements the algorithm at RFC 3394 to AES key unwrap. The - * current implementation allows to unwrap up to 512 bits, - * with the restriction of nblocks=2 or =4 or n=8(means it - * unwraps only 128bits, 256bits or two 256 bits keys (512)). It - * is allowed input key of 128 and 256bits only (passed using - * the keyslot). The function also assumes the - * @ref CAU3_LoadSpecialKeyContext was called before. - * It returns error and clear the destination context in case - * parameters are not inside aceptable values. - * In case n>4 && n!=8 it clears both destination contexts (the - * dstContext and the adjacent/next context) - * In case of n=8, the first unwraped key will be stored in the - * dstContext slot, and the second key will be saved in the next - * context (E.g: if dstContext=1, then first key goes to slot 1 - * and second key to slot 2. If dstContext=3 then first key goes - * to slot 3 and second key goes to slot 1). - * Examples of n usage. - * E.g.: n = 2 means a unwraped key of 128 bits (2 * 64) - * E.g.: n = 4 means a unwraped key of 256 bits (4 * 64) - * E.g.: n = 8 means two unwraped keys of 256 bits (8 * 64) - * - * The function is blocking, it uses the polling task done signaling. - * - * @param base CAU3 peripheral base address - * @param keySlot is the key used to unwrap the key blob [0-3] - * @param keyBlob 0-mod-4 aligned pointer is the RFC3394 wrapped key blob. - * @param numberOfBlocks is the unwrapped keyBlob length as multiple of 64-bit blocks - * @param dstContext is the destination key context for unwrapped blob [0-3] - * @retval status check from task completion - */ -status_t CAU3_KeyBlobUnwrap(CAU3_Type *base, - cau3_key_slot_t keySlot, - const uint8_t *keyBlob, - uint32_t numberOfBlocks, - cau3_key_slot_t dstContext); - -/*! - *@} - */ /* end of cau3_driver_blob */ - -/******************************************************************************* - * PKHA API - ******************************************************************************/ - -/*! - * @addtogroup cau3_driver_pkha - * @{ - */ - -int CAU3_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB); - -/*! - * @brief Converts from integer to Montgomery format. - * - * This function computes R2 mod N and optionally converts A or B into Montgomery format of A or B. - * - * @param base CAU3 peripheral base address - * @param N modulus - * @param sizeN size of N in bytes - * @param[in,out] A The first input in non-Montgomery format. Output Montgomery format of the first input. - * @param[in,out] sizeA pointer to size variable. On input it holds size of input A in bytes. On output it holds size of - * Montgomery format of A in bytes. - * @param[in,out] B Second input in non-Montgomery format. Output Montgomery format of the second input. - * @param[in,out] sizeB pointer to size variable. On input it holds size of input B in bytes. On output it holds size of - * Montgomery format of B in bytes. - * @param[out] R2 Output Montgomery factor R2 mod N. - * @param[out] sizeR2 pointer to size variable. On output it holds size of Montgomery factor R2 mod N in bytes. - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_NormalToMontgomery(CAU3_Type *base, - const uint8_t *N, - size_t sizeN, - uint8_t *A, - size_t *sizeA, - uint8_t *B, - size_t *sizeB, - uint8_t *R2, - size_t *sizeR2, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Converts from Montgomery format to int. - * - * This function converts Montgomery format of A or B into int A or B. - * - * @param base CAU3 peripheral base address - * @param N modulus. - * @param sizeN size of N modulus in bytes. - * @param[in,out] A Input first number in Montgomery format. Output is non-Montgomery format. - * @param[in,out] sizeA pointer to size variable. On input it holds size of the input A in bytes. On output it holds - * size of non-Montgomery A in bytes. - * @param[in,out] B Input first number in Montgomery format. Output is non-Montgomery format. - * @param[in,out] sizeB pointer to size variable. On input it holds size of the input B in bytes. On output it holds - * size of non-Montgomery B in bytes. - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_MontgomeryToNormal(CAU3_Type *base, - const uint8_t *N, - size_t sizeN, - uint8_t *A, - size_t *sizeA, - uint8_t *B, - size_t *sizeB, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Performs modular addition - (A + B) mod N. - * - * This function performs modular addition of (A + B) mod N, with either - * integer or binary polynomial (F2m) inputs. In the F2m form, this function is - * equivalent to a bitwise XOR and it is functionally the same as subtraction. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus. - * @param sizeN Size of N in bytes. - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_ModAdd(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Performs modular subtraction - (A - B) mod N. - * - * This function performs modular subtraction of (A - B) mod N with - * integer inputs. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t CAU3_PKHA_ModSub1(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize); - -/*! - * @brief Performs modular subtraction - (B - A) mod N. - * - * This function performs modular subtraction of (B - A) mod N, - * with integer inputs. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t CAU3_PKHA_ModSub2(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize); - -/*! - * @brief Performs modular multiplication - (A x B) mod N. - * - * This function performs modular multiplication with either integer or - * binary polynomial (F2m) inputs. It can optionally specify whether inputs - * and/or outputs will be in Montgomery form or not. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param B second addend (integer or binary polynomial) - * @param sizeB Size of B in bytes - * @param N modulus. - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param montIn Format of inputs - * @param montOut Format of output - * @param equalTime Run the function time equalized or no timing equalization. This argument is ignored for F2m modular - * multiplication. - * @return Operation status. - */ -status_t CAU3_PKHA_ModMul(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType, - cau3_pkha_montgomery_form_t montIn, - cau3_pkha_montgomery_form_t montOut, - cau3_pkha_timing_t equalTime); - -/*! - * @brief Performs modular exponentiation - (A^E) mod N. - * - * This function performs modular exponentiation with either integer or - * binary polynomial (F2m) inputs. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param E exponent - * @param sizeE Size of E in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param montIn Format of A input (normal or Montgomery) - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param equalTime Run the function time equalized or no timing equalization. - * @return Operation status. - */ -status_t CAU3_PKHA_ModExp(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - const uint8_t *E, - size_t sizeE, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType, - cau3_pkha_montgomery_form_t montIn, - cau3_pkha_timing_t equalTime); - -/*! - * @brief Performs Modular Square Root. - * - * This function performs modular square root with integer inputs. - * The modular square root function computes output result B, such that ( B x B ) mod N = input A. - * If no such B result exists, the result will be set to 0 and the PKHA "prime" flag - * will be set. Input values A and B are limited to a maximum size of 128 bytes. Note that - * two such square root values may exist. This algorithm will find either one of them, if any - * exist. The second possible square root (B') can be found by calculating B' = N - B. - * - * @param base CAU3 peripheral base address - * @param A input value, for which a square root is to be calculated - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t CAU3_PKHA_ModSqrt(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize); - -/*! - * @brief Performs modular reduction - (A) mod N. - * - * This function performs modular reduction with either integer or - * binary polynomial (F2m) inputs. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_ModRed(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Performs modular inversion - (A^-1) mod N. - * - * This function performs modular inversion with either integer or - * binary polynomial (F2m) inputs. - * - * @param base CAU3 peripheral base address - * @param A first addend (integer or binary polynomial) - * @param sizeA Size of A in bytes - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_ModInv(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Computes integer Montgomery factor R^2 mod N. - * - * This function computes a constant to assist in converting operands - * into the Montgomery residue system representation. - * - * @param base CAU3 peripheral base address - * @param N modulus - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_ModR2( - CAU3_Type *base, const uint8_t *N, size_t sizeN, uint8_t *result, size_t *resultSize, cau3_pkha_f2m_t arithType); - -/*! - * @brief Performs Integer RERP mod P. - * - * This function is used to compute a constant to assist in converting operands into the - * Montgomery residue system representation specifically for Chinese Remainder Theorem - * while performing RSA with a CRT implementation where a modulus E=P x Q, and P and - * Q are prime numbers. Although labeled RERP mod P, this routine (function) can also - * compute RERQ mod Q. - * - * @param base CAU3 peripheral base address - * @param P modulus P or Q of CRT, an odd integer - * @param sizeP Size of P in bytes - * @param sizeE Number of bytes of E = P x Q (this size must be given, though content of E itself is not used). - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @return Operation status. - */ -status_t CAU3_PKHA_ModRR( - CAU3_Type *base, const uint8_t *P, size_t sizeP, size_t sizeE, uint8_t *result, size_t *resultSize); - -/*! - * @brief Calculates the greatest common divisor - GCD (A, N). - * - * This function calculates the greatest common divisor of two inputs with - * either integer or binary polynomial (F2m) inputs. - * - * @param base CAU3 peripheral base address - * @param A first value (must be smaller than or equal to N) - * @param sizeA Size of A in bytes - * @param N second value (must be non-zero) - * @param sizeN Size of N in bytes - * @param[out] result Output array to store result of operation - * @param[out] resultSize Output size of operation in bytes - * @param arithType Type of arithmetic to perform (integer or F2m) - * @return Operation status. - */ -status_t CAU3_PKHA_ModGcd(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *N, - size_t sizeN, - uint8_t *result, - size_t *resultSize, - cau3_pkha_f2m_t arithType); - -/*! - * @brief Executes Miller-Rabin primality test. - * - * This function calculates whether or not a candidate prime number is likely - * to be a prime. - * - * @param base CAU3 peripheral base address - * @param A initial random seed - * @param sizeA Size of A in bytes - * @param B number of trial runs - * @param sizeB Size of B in bytes - * @param N candidate prime integer - * @param sizeN Size of N in bytes - * @param[out] res True if the value is likely prime or false otherwise - * @return Operation status. - */ -status_t CAU3_PKHA_PrimalityTest(CAU3_Type *base, - const uint8_t *A, - size_t sizeA, - const uint8_t *B, - size_t sizeB, - const uint8_t *N, - size_t sizeN, - bool *res); - -/*! - * @brief Adds elliptic curve points - A + B. - * - * This function performs ECC point addition over a prime field (Fp) or binary field (F2m) using - * affine coordinates. - * - * @param base CAU3 peripheral base address - * @param A Left-hand point - * @param B Right-hand point - * @param N Prime modulus of the field - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * CAU3_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (constant) - * @param size Size in bytes of curve points and parameters - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @return Operation status. - */ -status_t CAU3_PKHA_ECC_PointAdd(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result); - -/*! - * @brief Doubles elliptic curve points - B + B. - * - * This function performs ECC point doubling over a prime field (Fp) or binary field (F2m) using - * affine coordinates. - * - * @param base CAU3 peripheral base address - * @param B Point to double - * @param N Prime modulus of the field - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (constant) - * @param size Size in bytes of curve points and parameters - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @return Operation status. - */ -status_t CAU3_PKHA_ECC_PointDouble(CAU3_Type *base, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result); - -/*! - * @brief Multiplies an elliptic curve point by a scalar - E x (A0, A1). - * - * This function performs ECC point multiplication to multiply an ECC point by - * a scalar integer multiplier over a prime field (Fp) or a binary field (F2m). - * - * @param base CAU3 peripheral base address - * @param A Point as multiplicand - * @param E Scalar multiple - * @param sizeE The size of E, in bytes - * @param N Modulus, a prime number for the Fp field or Irreducible polynomial for F2m field. - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * CAU3_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param bCurveParam B parameter from curve equation (C parameter for operation over F2m). - * @param size Size in bytes of curve points and parameters - * @param equalTime Run the function time equalized or no timing equalization. - * @param arithType Type of arithmetic to perform (integer or F2m) - * @param[out] result Result point - * @return Operation status. - */ -status_t CAU3_PKHA_ECC_PointMul(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const uint8_t *E, - size_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *bCurveParam, - size_t size, - cau3_pkha_timing_t equalTime, - cau3_pkha_f2m_t arithType, - cau3_pkha_ecc_point_t *result); - -/*! - * @brief Computes scalar multiplication of a point on an elliptic curve in Montgomery form. - * - * This function computes the scalar multiplication of a point on an elliptic curve in - * Montgomery form. The input and output are just the x coordinates of the points. - * The points on a curve are defined by the equation E: B*y^2 = x^3 + A*x^2 + x mod p - * This function computes a point multiplication on a Montgomery curve, using - * Montgomery values, by means of a Montgomery ladder. At the end of the ladder, P2 = P3 + P1, - * where P1 is the input and P3 is the result. - * - * @param base CAU3 peripheral base address - * @param E Scalar multiplier, any integer - * @param sizeE The size of E, in bytes - * @param inputCoordinate Point as multiplicand, an input point's affine x coordinate - * @param A24 elliptic curve a24 parameter, that is, (A+2)/4 - * @param N Modulus, a prime number. - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * @ref CAU3_PKHA_ModR2() function). - * @param size Size in bytes of curve points and parameters - * @param equalTime Run the function time equalized or no timing equalization. - * @param[out] outputCoordinate Resulting poin's x affine coordinate. - * @return Operation status. - */ -status_t CAU3_PKHA_ECM_PointMul(CAU3_Type *base, - const uint8_t *E, - size_t sizeE, - const uint8_t *inputCoordinate, - const uint8_t *A24, - const uint8_t *N, - const uint8_t *R2modN, - size_t size, - cau3_pkha_timing_t equalTime, - uint8_t *outputCoordinate); - -/*! - * @brief Multiplies an Edwards-form elliptic curve point by a scalar - E x (A0, A1). - * - * This function performs scalar multiplication of an Edwards-form elliptic curve point - * in affine coordinates. - * The points on a curve are defined by the equation E: a*X^2 + d^2 = 1 + D^2*X^2*Y^2 mod N - * - * @param base CAU3 peripheral base address - * @param A Point as multiplicand - * @param E Scalar multiple - * @param sizeE The size of E, in bytes - * @param N Modulus, a prime number for the Fp field. - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * @ref CAU3_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param dCurveParam D parameter from curve equation. - * @param size Size in bytes of curve points and parameters - * @param equalTime Run the function time equalized or no timing equalization. - * @param[out] result Result point - * @return Operation status. - */ -status_t CAU3_PKHA_ECT_PointMul(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const uint8_t *E, - size_t sizeE, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *dCurveParam, - size_t size, - cau3_pkha_timing_t equalTime, - cau3_pkha_ecc_point_t *result); - -/*! - * @brief Adds an Edwards-form elliptic curve points - A + B. - * - * This function performs Edwards-form elliptic curve point addition over a prime field (Fp) using affine coordinates. - * The points on a curve are defined by the equation E: a*X^2 + Y^2 = 1 + d^2*X^2*Y^2 mod N - * - * @param base CAU3 peripheral base address - * @param A Left-hand point - * @param B Right-hand point - * @param N Prime modulus of the field - * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from - * @ref CAU3_PKHA_ModR2() function). - * @param aCurveParam A parameter from curve equation - * @param dCurveParam D parameter from curve equation - * @param size Size in bytes of curve points and parameters - * @param[out] result Result point - * @return Operation status. - */ -status_t CAU3_PKHA_ECT_PointAdd(CAU3_Type *base, - const cau3_pkha_ecc_point_t *A, - const cau3_pkha_ecc_point_t *B, - const uint8_t *N, - const uint8_t *R2modN, - const uint8_t *aCurveParam, - const uint8_t *dCurveParam, - size_t size, - cau3_pkha_ecc_point_t *result); - -/*! - *@} - */ /* end of cau3_driver_pkha */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CAU3_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c deleted file mode 100644 index 8cd4fcfd5f377620bc88991986b2bd249fa15908..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define SCG_SIRC_LOW_RANGE_FREQ 2000000U /* Slow IRC low range clock frequency. */ -#define SCG_SIRC_HIGH_RANGE_FREQ 8000000U /* Slow IRC high range clock frequency. */ - -#define SCG_FIRC_FREQ0 48000000U /* Fast IRC trimed clock frequency(48MHz). */ -#define SCG_FIRC_FREQ1 52000000U /* Fast IRC trimed clock frequency(52MHz). */ -#define SCG_FIRC_FREQ2 56000000U /* Fast IRC trimed clock frequency(56MHz). */ -#define SCG_FIRC_FREQ3 60000000U /* Fast IRC trimed clock frequency(60MHz). */ - -#define SCG_LPFLL_FREQ0 48000000U /* LPFLL trimed clock frequency(48MHz). */ -#define SCG_LPFLL_FREQ1 72000000U /* LPFLL trimed clock frequency(72MHz). */ -#define SCG_LPFLL_FREQ2 96000000U /* LPFLL trimed clock frequency(96MHz). */ -#define SCG_LPFLL_FREQ3 120000000U /* LPFLL trimed clock frequency(120MHz). */ - -#define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) -#define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT) -#define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT) -#define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV3_SHIFT) -#define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT) -#define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT) -#define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV3_SHIFT) -#define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT) -#define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT) -#define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV3_SHIFT) - -#define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_LPFLLDIV1_SHIFT) -#define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_LPFLLDIV2_SHIFT) -#define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_LPFLLDIV3_SHIFT) - -#define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) -#define SCG_FIRCCFG_RANGE_VAL ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) - -#define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) - -/* Get the value of each field in PCC register. */ -#define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) -#define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) -#define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* External XTAL0 (OSC0) clock frequency. */ -uint32_t g_xtal0Freq; -/* External XTAL32K clock frequency. */ -uint32_t g_xtal32Freq; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t CLOCK_GetOsc32kClkFreq(void) -{ - assert(g_xtal32Freq); - return g_xtal32Freq; -} - -uint32_t CLOCK_GetFlashClkFreq(void) -{ - return CLOCK_GetSysClkFreq(kSCG_SysClkSlow); -} - -uint32_t CLOCK_GetBusClkFreq(void) -{ - return CLOCK_GetSysClkFreq(kSCG_SysClkSlow); -} - -uint32_t CLOCK_GetPlatClkFreq(void) -{ - return CLOCK_GetSysClkFreq(kSCG_SysClkCore); -} - -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - return CLOCK_GetSysClkFreq(kSCG_SysClkCore); -} - -uint32_t CLOCK_GetExtClkFreq(void) -{ - return CLOCK_GetSysClkFreq(kSCG_SysClkExt); -} - -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - - switch (clockName) - { - /* System layer clock. */ - case kCLOCK_CoreSysClk: - case kCLOCK_PlatClk: - freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus); - break; - case kCLOCK_FlashClk: - freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow); - break; - case kCLOCK_ExtClk: - freq = CLOCK_GetSysClkFreq(kSCG_SysClkExt); - break; - /* Original clock source. */ - case kCLOCK_ScgSysOscClk: - freq = CLOCK_GetSysOscFreq(); - break; - case kCLOCK_ScgSircClk: - freq = CLOCK_GetSircFreq(); - break; - case kCLOCK_ScgFircClk: - freq = CLOCK_GetFircFreq(); - break; - case kCLOCK_ScgLpFllClk: - freq = CLOCK_GetLpFllFreq(); - break; - - /* SOSC div clock. */ - case kCLOCK_ScgSysOscAsyncDiv1Clk: - freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk); - break; - case kCLOCK_ScgSysOscAsyncDiv2Clk: - freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk); - break; - case kCLOCK_ScgSysOscAsyncDiv3Clk: - freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv3Clk); - break; - - /* SIRC div clock. */ - case kCLOCK_ScgSircAsyncDiv1Clk: - freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk); - break; - case kCLOCK_ScgSircAsyncDiv2Clk: - freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk); - break; - case kCLOCK_ScgSircAsyncDiv3Clk: - freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv3Clk); - break; - - /* FIRC div clock. */ - case kCLOCK_ScgFircAsyncDiv1Clk: - freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk); - break; - case kCLOCK_ScgFircAsyncDiv2Clk: - freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk); - break; - case kCLOCK_ScgFircAsyncDiv3Clk: - freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv3Clk); - break; - - /* LPFLL div clock. */ - case kCLOCK_ScgSysLpFllAsyncDiv1Clk: - freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv1Clk); - break; - case kCLOCK_ScgSysLpFllAsyncDiv2Clk: - freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv2Clk); - break; - case kCLOCK_ScgSysLpFllAsyncDiv3Clk: - freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv3Clk); - break; - - /* Other clocks. */ - case kCLOCK_LpoClk: - freq = CLOCK_GetLpoClkFreq(); - break; - case kCLOCK_Osc32kClk: - freq = CLOCK_GetOsc32kClkFreq(); - break; - default: - freq = 0U; - break; - } - return freq; -} - -uint32_t CLOCK_GetIpFreq(clock_ip_name_t name) -{ - uint32_t reg = (*(volatile uint32_t *)name); - - scg_async_clk_t asycClk; - uint32_t freq; - - assert(reg & PCC_CLKCFG_PR_MASK); - - switch (name) - { - case kCLOCK_Lpit0: - case kCLOCK_Lpit1: - asycClk = kSCG_AsyncDiv3Clk; - break; - case kCLOCK_Sdhc0: - case kCLOCK_Usb0: - asycClk = kSCG_AsyncDiv1Clk; - break; - default: - asycClk = kSCG_AsyncDiv2Clk; - break; - } - - switch (PCC_PCS_VAL(reg)) - { - case kCLOCK_IpSrcSysOscAsync: - freq = CLOCK_GetSysOscAsyncFreq(asycClk); - break; - case kCLOCK_IpSrcSircAsync: - freq = CLOCK_GetSircAsyncFreq(asycClk); - break; - case kCLOCK_IpSrcFircAsync: - freq = CLOCK_GetFircAsyncFreq(asycClk); - break; - case kCLOCK_IpSrcLpFllAsync: - freq = CLOCK_GetLpFllAsyncFreq(asycClk); - break; - default: /* kCLOCK_IpSrcNoneOrExt. */ - freq = 0U; - break; - } - - if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK))) - { - return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U); - } - else - { - return freq; - } -} - -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_SetIpSrc(kCLOCK_Usb0, kCLOCK_IpSrcFircAsync); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock gate. */ - CLOCK_EnableClock(kCLOCK_Usb0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - USBVREG->CTRL |= USBVREG_CTRL_EN_MASK; - USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; - - if (kCLOCK_UsbSrcIrc48M == src) - { - USB0->CLK_RECOVER_IRC_EN = 0x03U; - USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; - USB0->CLK_RECOVER_INT_EN = 0x00U; - } - return ret; -} - -uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type) -{ - uint32_t freq; - - scg_sys_clk_config_t sysClkConfig; - - CLOCK_GetCurSysClkConfig(&sysClkConfig); /* Get the main clock for SoC platform. */ - - switch (sysClkConfig.src) - { - case kSCG_SysClkSrcSysOsc: - freq = CLOCK_GetSysOscFreq(); - break; - case kSCG_SysClkSrcSirc: - freq = CLOCK_GetSircFreq(); - break; - case kSCG_SysClkSrcFirc: - freq = CLOCK_GetFircFreq(); - break; - case kSCG_SysClkSrcRosc: - freq = CLOCK_GetRtcOscFreq(); - break; - case kSCG_SysClkSrcLpFll: - freq = CLOCK_GetLpFllFreq(); - break; - default: - freq = 0U; - break; - } - - freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */ - - if (kSCG_SysClkSlow == type) - { - freq /= (sysClkConfig.divSlow + 1U); - } - else if (kSCG_SysClkBus == type) - { - freq /= (sysClkConfig.divBus + 1U); - } - else if (kSCG_SysClkExt == type) - { - freq /= (sysClkConfig.divExt + 1U); - } - else - { - } - - return freq; -} - -status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config) -{ - assert(config); - status_t status; - uint8_t tmp8; - - /* De-init the SOSC first. */ - status = CLOCK_DeinitSysOsc(); - - if (kStatus_Success != status) - { - return status; - } - - /* Now start to set up OSC clock. */ - /* Step 1. Setup dividers. */ - SCG->SOSCDIV = - SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3); - - /* Step 2. Set OSC configuration. */ - - /* Step 3. Enable clock. */ - /* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */ - tmp8 = config->enableMode; - tmp8 |= SCG_SOSCCSR_SOSCEN_MASK; - SCG->SOSCCSR = tmp8; - - /* Step 4. Wait for OSC clock to be valid. */ - while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) - { - } - - /* Step 5. Enabe monitor. */ - SCG->SOSCCSR |= (uint32_t)config->monitorMode; - - return kStatus_Success; -} - -status_t CLOCK_DeinitSysOsc(void) -{ - uint32_t reg = SCG->SOSCCSR; - - /* If clock is used by system, return error. */ - if (reg & SCG_SOSCCSR_SOSCSEL_MASK) - { - return kStatus_SCG_Busy; - } - - /* If configure register is locked, return error. */ - if (reg & SCG_SOSCCSR_LK_MASK) - { - return kStatus_ReadOnly; - } - - SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; - - return kStatus_Success; -} - -uint32_t CLOCK_GetSysOscFreq(void) -{ - if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */ - { - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(g_xtal0Freq); - return g_xtal0Freq; - } - else - { - return 0U; - } -} - -uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type) -{ - uint32_t oscFreq = CLOCK_GetSysOscFreq(); - uint32_t divider = 0U; - - /* Get divider. */ - if (oscFreq) - { - switch (type) - { - case kSCG_AsyncDiv3Clk: /* SOSCDIV3_CLK. */ - divider = SCG_SOSCDIV_SOSCDIV3_VAL; - break; - case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */ - divider = SCG_SOSCDIV_SOSCDIV2_VAL; - break; - case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */ - divider = SCG_SOSCDIV_SOSCDIV1_VAL; - break; - default: - break; - } - } - if (divider) - { - return oscFreq >> (divider - 1U); - } - else /* Output disabled. */ - { - return 0U; - } -} - -status_t CLOCK_InitSirc(const scg_sirc_config_t *config) -{ - assert(config); - - status_t status; - - /* De-init the SIRC first. */ - status = CLOCK_DeinitSirc(); - - if (kStatus_Success != status) - { - return status; - } - - /* Now start to set up SIRC clock. */ - /* Step 1. Setup dividers. */ - SCG->SIRCDIV = - SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3); - - /* Step 2. Set SIRC configuration. */ - SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range); - - /* Step 3. Enable clock. */ - SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode; - - /* Step 4. Wait for SIRC clock to be valid. */ - while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK)) - { - } - - return kStatus_Success; -} - -status_t CLOCK_DeinitSirc(void) -{ - uint32_t reg = SCG->SIRCCSR; - - /* If clock is used by system, return error. */ - if (reg & SCG_SIRCCSR_SIRCSEL_MASK) - { - return kStatus_SCG_Busy; - } - - /* If configure register is locked, return error. */ - if (reg & SCG_SIRCCSR_LK_MASK) - { - return kStatus_ReadOnly; - } - - SCG->SIRCCSR = 0U; - - return kStatus_Success; -} - -uint32_t CLOCK_GetSircFreq(void) -{ - static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ}; - - if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */ - { - return sircFreq[SCG_SIRCCFG_RANGE_VAL]; - } - else - { - return 0U; - } -} - -uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type) -{ - uint32_t sircFreq = CLOCK_GetSircFreq(); - uint32_t divider = 0U; - - /* Get divider. */ - if (sircFreq) - { - switch (type) - { - case kSCG_AsyncDiv3Clk: /* SIRCDIV3_CLK. */ - divider = SCG_SIRCDIV_SIRCDIV3_VAL; - break; - case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */ - divider = SCG_SIRCDIV_SIRCDIV2_VAL; - break; - case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */ - divider = SCG_SIRCDIV_SIRCDIV1_VAL; - break; - default: - break; - } - } - if (divider) - { - return sircFreq >> (divider - 1U); - } - else /* Output disabled. */ - { - return 0U; - } -} - -status_t CLOCK_InitFirc(const scg_firc_config_t *config) -{ - assert(config); - - status_t status; - - /* De-init the FIRC first. */ - status = CLOCK_DeinitFirc(); - - if (kStatus_Success != status) - { - return status; - } - - /* Now start to set up FIRC clock. */ - /* Step 1. Setup dividers. */ - SCG->FIRCDIV = - SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3); - - /* Step 2. Set FIRC configuration. */ - SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range); - - /* Step 3. Set trimming configuration. */ - if (config->trimConfig) - { - SCG->FIRCTCFG = - SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc); - - /* TODO: Write FIRCSTAT cause bus error: TKT266932. */ - if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode) - { - SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) | - SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine); - } - - /* trim mode. */ - SCG->FIRCCSR = config->trimConfig->trimMode; - - if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) - { - return kStatus_Fail; - } - } - - /* Step 4. Enable clock. */ - SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode); - - /* Step 5. Wait for FIRC clock to be valid. */ - while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)) - { - } - - return kStatus_Success; -} - -status_t CLOCK_DeinitFirc(void) -{ - uint32_t reg = SCG->FIRCCSR; - - /* If clock is used by system, return error. */ - if (reg & SCG_FIRCCSR_FIRCSEL_MASK) - { - return kStatus_SCG_Busy; - } - - /* If configure register is locked, return error. */ - if (reg & SCG_FIRCCSR_LK_MASK) - { - return kStatus_ReadOnly; - } - - SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; - - return kStatus_Success; -} - -uint32_t CLOCK_GetFircFreq(void) -{ - static const uint32_t fircFreq[] = { - SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3, - }; - - if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */ - { - return fircFreq[SCG_FIRCCFG_RANGE_VAL]; - } - else - { - return 0U; - } -} - -uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type) -{ - uint32_t fircFreq = CLOCK_GetFircFreq(); - uint32_t divider = 0U; - - /* Get divider. */ - if (fircFreq) - { - switch (type) - { - case kSCG_AsyncDiv3Clk: /* FIRCDIV3_CLK. */ - divider = SCG_FIRCDIV_FIRCDIV3_VAL; - break; - case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */ - divider = SCG_FIRCDIV_FIRCDIV2_VAL; - break; - case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */ - divider = SCG_FIRCDIV_FIRCDIV1_VAL; - break; - default: - break; - } - } - if (divider) - { - return fircFreq >> (divider - 1U); - } - else /* Output disabled. */ - { - return 0U; - } -} - -uint32_t CLOCK_GetRtcOscFreq(void) -{ - if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */ - { - /* Please call CLOCK_SetXtal32Freq base on board setting before using RTC OSC clock. */ - assert(g_xtal32Freq); - return g_xtal32Freq; - } - else - { - return 0U; - } -} - -status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config) -{ - assert(config); - - status_t status; - - /* De-init the LPFLL first. */ - status = CLOCK_DeinitLpFll(); - - if (kStatus_Success != status) - { - return status; - } - - /* Now start to set up LPFLL clock. */ - /* Step 1. Setup dividers. */ - SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | - SCG_LPFLLDIV_LPFLLDIV3(config->div3); - - /* Step 2. Set LPFLL configuration. */ - SCG->LPFLLCFG = SCG_LPFLLCFG_FSEL(config->range); - - /* Step 3. Set trimming configuration. */ - if (config->trimConfig) - { - SCG->LPFLLTCFG = SCG_LPFLLTCFG_TRIMDIV(config->trimConfig->trimDiv) | - SCG_LPFLLTCFG_TRIMSRC(config->trimConfig->trimSrc) | - SCG_LPFLLTCFG_LOCKW2LSB(config->trimConfig->lockMode); - - if (kSCG_LpFllTrimNonUpdate == config->trimConfig->trimMode) - { - SCG->LPFLLSTAT = config->trimConfig->trimValue; - } - - /* Trim mode. */ - SCG->LPFLLCSR = config->trimConfig->trimMode; - - if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) - { - return kStatus_Fail; - } - } - - /* Step 4. Enable clock. */ - SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); - - /* Step 5. Wait for LPFLL clock to be valid. */ - while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) - { - } - - /* Step 6. Wait for LPFLL trim lock. */ - if ((config->trimConfig) && (kSCG_LpFllTrimUpdate == config->trimConfig->trimMode)) - { - while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) - { - } - } - - return kStatus_Success; -} - -status_t CLOCK_DeinitLpFll(void) -{ - uint32_t reg = SCG->LPFLLCSR; - - /* If clock is used by system, return error. */ - if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK) - { - return kStatus_SCG_Busy; - } - - /* If configure register is locked, return error. */ - if (reg & SCG_LPFLLCSR_LK_MASK) - { - return kStatus_ReadOnly; - } - - SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; - - return kStatus_Success; -} - -uint32_t CLOCK_GetLpFllFreq(void) -{ - static const uint32_t lpfllFreq[] = { - SCG_LPFLL_FREQ0, SCG_LPFLL_FREQ1, SCG_LPFLL_FREQ2, SCG_LPFLL_FREQ3, - }; - - if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */ - { - return lpfllFreq[SCG_LPFLLCFG_FSEL_VAL]; - } - else - { - return 0U; - } -} - -uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type) -{ - uint32_t lpfllFreq = CLOCK_GetLpFllFreq(); - uint32_t divider = 0U; - - /* Get divider. */ - if (lpfllFreq) - { - switch (type) - { - case kSCG_AsyncDiv2Clk: /* LPFLLDIV2_CLK. */ - divider = SCG_LPFLLDIV_LPFLLDIV2_VAL; - break; - case kSCG_AsyncDiv1Clk: /* LPFLLDIV1_CLK. */ - divider = SCG_LPFLLDIV_LPFLLDIV1_VAL; - break; - default: - break; - } - } - if (divider) - { - return lpfllFreq >> (divider - 1U); - } - else /* Output disabled. */ - { - return 0U; - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h deleted file mode 100644 index 8fa75c380a7c49e7ff196cd8292beff451421d0c..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h +++ /dev/null @@ -1,1582 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.1.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief External XTAL0 (OSC0/SYSOSC) clock frequency. - * - * The XTAL0/EXTAL0 (OSC0/SYSOSC) clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, - * if XTAL0 is 8 MHz: - * @code - * CLOCK_InitSysOsc(...); // Set up the OSC0/SYSOSC - * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value in the clock driver. - * @endcode - * - * This is important for the multicore platforms where only one core needs to set up the - * OSC0/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtal0Freq - * to get a valid clock frequency. - */ -extern uint32_t g_xtal0Freq; - -/*! @brief External XTAL32/EXTAL32 clock frequency. - * - * The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the - * function CLOCK_SetXtal32Freq to set the value in the clock driver. - * - * This is important for the multicore platforms where only one core needs to set up - * the clock. All other cores need to call the CLOCK_SetXtal32Freq - * to get a valid clock frequency. - */ -extern uint32_t g_xtal32Freq; - -/*! @brief Clock ip name array for MAX. */ -#define MAX_CLOCKS \ - { \ - kCLOCK_Max0 \ - } - -/*! @brief Clock ip name array for EDMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Edma0, kCLOCK_Edma1 \ - } - -/*! @brief Clock ip name array for FLEXBUS. */ -#define FLEXBUS_CLOCKS \ - { \ - kCLOCK_Flexbus \ - } - -/*! @brief XRDC clock gate number. */ -#define FSL_CLOCK_XRDC_GATE_COUNT (5U) - -/*! @brief Clock ip name array for XRDC. */ -#define XRDC_CLOCKS \ - { \ - kCLOCK_Xrdc0Mgr, kCLOCK_Xrdc0Pac, kCLOCK_Xrdc0Mrc, kCLOCK_Xrdc0PacB, kCLOCK_Xrdc0MrcB \ - } - -/*! @brief Clock ip name array for SEMA42. */ -#define SEMA42_CLOCKS \ - { \ - kCLOCK_Sema420, kCLOCK_Sema421 \ - } - -/*! @brief Clock ip name array for DMAMUX. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dmamux0, kCLOCK_Dmamux1 \ - } - -/*! @brief Clock ip name array for MU. */ -#if (defined(RV32M1_cm0plus_SERIES) || defined(RV32M1_zero_riscy_SERIES)) -#define MU_CLOCKS \ - { \ - kCLOCK_MuB \ - } -#else -#define MU_CLOCKS \ - { \ - kCLOCK_MuA \ - } -#endif - -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc0 \ - } - -/*! @brief Clock ip name array for LPIT. */ -#define LPIT_CLOCKS \ - { \ - kCLOCK_Lpit0, kCLOCK_Lpit1 \ - } - -/*! @brief Clock ip name array for TPM. */ -#define TPM_CLOCKS \ - { \ - kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3 \ - } - -/*! @brief Clock ip name array for TRNG. */ -#define TRNG_CLOCKS \ - { \ - kCLOCK_Trng \ - } - -/*! @brief Clock ip name array for SMVSIM. */ -#define EMVSIM_CLOCKS \ - { \ - kCLOCK_Emvsim0 \ - } - -/*! @brief Clock ip name array for EWM. */ -#define EWM_CLOCKS \ - { \ - kCLOCK_Ewm0 \ - } - -/*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ - kCLOCK_Flexio0 \ - } - -/*! @brief Clock ip name array for LPI2C0. */ -#define LPI2C_CLOCKS \ - { \ - kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3 \ - } - -/*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ - kCLOCK_Sai0 \ - } - -/*! @brief Clock ip name array for SDHC. */ -#define USDHC_CLOCKS \ - { \ - kCLOCK_Sdhc0 \ - } - -/*! @brief Clock ip name array for LPSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3 \ - } - -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3 \ - } - -/*! @brief Clock ip name array for USB. */ -#define USB_CLOCKS \ - { \ - kCLOCK_Usb0 \ - } - -/*! @brief Clock ip name array for PORT. */ -#define PORT_CLOCKS \ - { \ - kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ - } - -/*! @brief Clock ip name array for LPADC. */ -#define LPADC_CLOCKS \ - { \ - kCLOCK_Lpadc0 \ - } - -/*! @brief Clock ip name array for DAC. */ -#define LPDAC_CLOCKS \ - { \ - kCLOCK_Dac0 \ - } - -/*! @brief Clock ip name array for INTMUX. */ -#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES)) -#define INTMUX_CLOCKS \ - { \ - kCLOCK_Intmux0, kCLOCK_Intmux1 \ - } -#else -#define INTMUX_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Intmux0 \ - } -#endif - -/*! @brief Clock ip name array for EXT. */ -#define EXT_CLOCKS \ - { \ - kCLOCK_Ext0, kCLOCK_Ext1 \ - } - -/*! @brief Clock ip name array for VREF. */ -#define VREF_CLOCKS \ - { \ - kCLOCK_Vref \ - } - -/*! @brief Clock ip name array for FGPIO. */ -#define FGPIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Rgpio1 \ - } - -/*! @brief Clock name used to get clock frequency. - * - * These clocks source would be generated from SCG module. - */ -typedef enum _clock_name -{ - /* ----------------------------- System layer clock -------------------------------*/ - kCLOCK_CoreSysClk, /*!< Core 0/1 clock. */ - kCLOCK_SlowClk, /*!< SLOW_CLK with DIVSLOW. */ - kCLOCK_PlatClk, /*!< PLAT_CLK. */ - kCLOCK_SysClk, /*!< SYS_CLK. */ - kCLOCK_BusClk, /*!< BUS_CLK with DIVBUS. */ - kCLOCK_ExtClk, /*!< One clock selection of CLKOUT from main clock after DIVCORE and DIVEXT divider.*/ - - /* ------------------------------------ SCG clock ---------------------------------*/ - kCLOCK_ScgSysLpFllAsyncDiv1Clk, /*!< LPFLL_DIV1_CLK. */ - kCLOCK_ScgSysLpFllAsyncDiv2Clk, /*!< LPFLL_DIV1_CLK. */ - kCLOCK_ScgSysLpFllAsyncDiv3Clk, /*!< LPFLL_DIV1_CLK. */ - - kCLOCK_ScgSircAsyncDiv1Clk, /*!< SIRCDIV1_CLK. */ - kCLOCK_ScgSircAsyncDiv2Clk, /*!< SIRCDIV2_CLK. */ - kCLOCK_ScgSircAsyncDiv3Clk, /*!< SIRCDIV3_CLK. */ - - kCLOCK_ScgFircAsyncDiv1Clk, /*!< FIRCDIV1_CLK. */ - kCLOCK_ScgFircAsyncDiv2Clk, /*!< FIRCDIV2_CLK. */ - kCLOCK_ScgFircAsyncDiv3Clk, /*!< FIRCDIV3_CLK. */ - - kCLOCK_ScgSysOscAsyncDiv1Clk, /*!< SOSCDIV1_CLK. */ - kCLOCK_ScgSysOscAsyncDiv2Clk, /*!< SOSCDIV2_CLK. */ - kCLOCK_ScgSysOscAsyncDiv3Clk, /*!< SOSCDIV3_CLK. */ - - /* For SCG_CLKOUT output */ - /* kCLOCK_ExtClk, */ - kCLOCK_ScgSysOscClk, /*!< SCG system OSC clock. (SYSOSC) */ - kCLOCK_ScgSircClk, /*!< SCG SIRC clock. */ - kCLOCK_ScgFircClk, /*!< SCG FIRC clock. */ - kCLOCK_RtcOscClk, /*!< RTC OSC clock. */ - kCLOCK_ScgLpFllClk, /*!< SCG Low-power FLL clock. (LPFLL) */ - - /* --------------------------------- Other clock ----------------------------------*/ - kCLOCK_LpoClk, /*!< LPO clock */ - kCLOCK_Osc32kClk, /*!< External OSC 32K clock (OSC32KCLK) */ -} clock_name_t; - -#define kCLOCK_FlashClk kCLOCK_SlowClk -#define kCLOCK_RfClk kCLOCK_ScgSysOscClk -#define LPO_CLK_FREQ 1000U - -/*! - * @brief Clock source for peripherals that support various clock selections. - * - * These options are for PCC->CLKCFG[PCS]. - */ -typedef enum _clock_ip_src -{ - kCLOCK_IpSrcNoneOrExt = 0U, /*!< Clock is off or external clock is used. */ - kCLOCK_IpSrcSysOscAsync = 1U, /*!< System Oscillator async clock. */ - kCLOCK_IpSrcSircAsync = 2U, /*!< Slow IRC async clock. */ - kCLOCK_IpSrcFircAsync = 3U, /*!< Fast IRC async clock. */ - kCLOCK_IpSrcLpFllAsync = 6U /*!< System LPFLL async clock. */ -} clock_ip_src_t; - -/*! - * @brief Peripheral clock name difinition used for clock gate, clock source - * and clock divider setting. It is defined as the corresponding register address. - */ -#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset)) -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - /* PCC 0 */ - kCLOCK_Mscm = MAKE_PCC_REGADDR(PCC0_BASE, 0x4), - kCLOCK_Syspm = MAKE_PCC_REGADDR(PCC0_BASE, 0xC), - kCLOCK_Max0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x10), - kCLOCK_Edma0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x20), - kCLOCK_Flexbus = MAKE_PCC_REGADDR(PCC0_BASE, 0x30), - kCLOCK_Xrdc0Mgr = MAKE_PCC_REGADDR(PCC0_BASE, 0x50), - kCLOCK_Xrdc0Pac = MAKE_PCC_REGADDR(PCC0_BASE, 0x58), - kCLOCK_Xrdc0Mrc = MAKE_PCC_REGADDR(PCC0_BASE, 0x5C), - kCLOCK_Sema420 = MAKE_PCC_REGADDR(PCC0_BASE, 0x6C), - kCLOCK_Dmamux0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x84), - kCLOCK_Ewm0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x88), - kCLOCK_MuA = MAKE_PCC_REGADDR(PCC0_BASE, 0x94), - kCLOCK_Crc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xBC), - kCLOCK_Lpit0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xC0), - kCLOCK_Tpm0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xD4), - kCLOCK_Tpm1 = MAKE_PCC_REGADDR(PCC0_BASE, 0xD8), - kCLOCK_Tpm2 = MAKE_PCC_REGADDR(PCC0_BASE, 0xDC), - kCLOCK_Emvsim0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE0), - kCLOCK_Flexio0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE4), - kCLOCK_Lpi2c0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE8), - kCLOCK_Lpi2c1 = MAKE_PCC_REGADDR(PCC0_BASE, 0xEC), - kCLOCK_Lpi2c2 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF0), - kCLOCK_Sai0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF4), - kCLOCK_Sdhc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF8), - kCLOCK_Lpspi0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xFC), - kCLOCK_Lpspi1 = MAKE_PCC_REGADDR(PCC0_BASE, 0x100), - kCLOCK_Lpspi2 = MAKE_PCC_REGADDR(PCC0_BASE, 0x104), - kCLOCK_Lpuart0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x108), - kCLOCK_Lpuart1 = MAKE_PCC_REGADDR(PCC0_BASE, 0x10C), - kCLOCK_Lpuart2 = MAKE_PCC_REGADDR(PCC0_BASE, 0x110), - kCLOCK_Usb0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x114), - kCLOCK_PortA = MAKE_PCC_REGADDR(PCC0_BASE, 0x118), - kCLOCK_PortB = MAKE_PCC_REGADDR(PCC0_BASE, 0x11C), - kCLOCK_PortC = MAKE_PCC_REGADDR(PCC0_BASE, 0x120), - kCLOCK_PortD = MAKE_PCC_REGADDR(PCC0_BASE, 0x124), - kCLOCK_Lpadc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x128), - kCLOCK_Dac0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x130), - kCLOCK_Vref = MAKE_PCC_REGADDR(PCC0_BASE, 0x134), - kCLOCK_Atx = MAKE_PCC_REGADDR(PCC0_BASE, 0x138), -#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES)) - kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x13C), -#endif - kCLOCK_Trace = MAKE_PCC_REGADDR(PCC0_BASE, 0x200), - /* PCC1. */ - kCLOCK_Edma1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x20), - kCLOCK_Rgpio1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x3C), - kCLOCK_Xrdc0PacB = MAKE_PCC_REGADDR(PCC1_BASE, 0x58), - kCLOCK_Xrdc0MrcB = MAKE_PCC_REGADDR(PCC1_BASE, 0x5C), - kCLOCK_Sema421 = MAKE_PCC_REGADDR(PCC1_BASE, 0x6C), - kCLOCK_Dmamux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x84), -#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES)) - kCLOCK_Intmux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88), -#else - kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88), -#endif - kCLOCK_MuB = MAKE_PCC_REGADDR(PCC1_BASE, 0x90), - kCLOCK_Cau3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA0), - kCLOCK_Trng = MAKE_PCC_REGADDR(PCC1_BASE, 0xA4), - kCLOCK_Lpit1 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA8), - kCLOCK_Tpm3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xB4), - kCLOCK_Lpi2c3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xB8), - kCLOCK_Lpspi3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xD4), - kCLOCK_Lpuart3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xD8), - kCLOCK_PortE = MAKE_PCC_REGADDR(PCC1_BASE, 0xDC), - kCLOCK_Ext0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x200), - kCLOCK_Ext1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x204), -} clock_ip_name_t; - -/*! - * @brief USB clock source definition. - */ -typedef enum _clock_usb_src -{ - kCLOCK_UsbSrcIrc48M = 1, /*!< Use IRC48M. */ - kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not - care the clock source. */ -} clock_usb_src_t; - -/*! - * @brief SCG status return codes. - */ -enum _scg_status -{ - kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ - kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ -}; - -/*! - * @brief SCG system clock type. - */ -typedef enum _scg_sys_clk -{ - kSCG_SysClkSlow, /*!< System slow clock. */ - kSCG_SysClkBus, /*!< Bus clock. */ - kSCG_SysClkExt, /*!< External clock. */ - kSCG_SysClkCore, /*!< Core clock. */ -} scg_sys_clk_t; - -/*! - * @brief SCG system clock source. - */ -typedef enum _scg_sys_clk_src -{ - kSCG_SysClkSrcSysOsc = 1U, /*!< System OSC. */ - kSCG_SysClkSrcSirc = 2U, /*!< Slow IRC. */ - kSCG_SysClkSrcFirc = 3U, /*!< Fast IRC. */ - kSCG_SysClkSrcRosc = 4U, /*!< RTC OSC. */ - kSCG_SysClkSrcLpFll = 5U, /*!< Low power FLL. */ -} scg_sys_clk_src_t; - -/*! - * @brief SCG system clock divider value. - */ -typedef enum _scg_sys_clk_div -{ - kSCG_SysClkDivBy1 = 0U, /*!< Divided by 1. */ - kSCG_SysClkDivBy2 = 1U, /*!< Divided by 2. */ - kSCG_SysClkDivBy3 = 2U, /*!< Divided by 3. */ - kSCG_SysClkDivBy4 = 3U, /*!< Divided by 4. */ - kSCG_SysClkDivBy5 = 4U, /*!< Divided by 5. */ - kSCG_SysClkDivBy6 = 5U, /*!< Divided by 6. */ - kSCG_SysClkDivBy7 = 6U, /*!< Divided by 7. */ - kSCG_SysClkDivBy8 = 7U, /*!< Divided by 8. */ - kSCG_SysClkDivBy9 = 8U, /*!< Divided by 9. */ - kSCG_SysClkDivBy10 = 9U, /*!< Divided by 10. */ - kSCG_SysClkDivBy11 = 10U, /*!< Divided by 11. */ - kSCG_SysClkDivBy12 = 11U, /*!< Divided by 12. */ - kSCG_SysClkDivBy13 = 12U, /*!< Divided by 13. */ - kSCG_SysClkDivBy14 = 13U, /*!< Divided by 14. */ - kSCG_SysClkDivBy15 = 14U, /*!< Divided by 15. */ - kSCG_SysClkDivBy16 = 15U /*!< Divided by 16. */ -} scg_sys_clk_div_t; - -/*! - * @brief SCG system clock configuration. - */ -typedef struct _scg_sys_clk_config -{ - uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ - uint32_t divBus : 4; /*!< Bus clock divider, see @ref scg_sys_clk_div_t. */ - uint32_t divExt : 4; /*!< External clock divider, see @ref scg_sys_clk_div_t. */ - uint32_t : 4; /*!< Reserved. */ - uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ - uint32_t : 4; /*!< Reserved. */ - uint32_t src : 4; /*!< System clock source, see @ref scg_sys_clk_src_t. */ - uint32_t : 4; /*!< reserved. */ -} scg_sys_clk_config_t; - -/*! - * @brief SCG clock out configuration (CLKOUTSEL). - */ -typedef enum _clock_clkout_src -{ - kClockClkoutSelScgExt = 0U, /*!< SCG external clock. */ - kClockClkoutSelSysOsc = 1U, /*!< System OSC. */ - kClockClkoutSelSirc = 2U, /*!< Slow IRC. */ - kClockClkoutSelFirc = 3U, /*!< Fast IRC. */ - kClockClkoutSelScgRtcOsc = 4U, /*!< SCG RTC OSC clock. */ - kClockClkoutSelLpFll = 5U, /*!< Low power FLL. */ -} clock_clkout_src_t; - -/*! - * @brief SCG asynchronous clock type. - */ -typedef enum _scg_async_clk -{ - kSCG_AsyncDiv1Clk, /*!< The async clock by DIV1, e.g. SOSCDIV1_CLK, SIRCDIV1_CLK. */ - kSCG_AsyncDiv2Clk, /*!< The async clock by DIV2, e.g. SOSCDIV2_CLK, SIRCDIV2_CLK. */ - kSCG_AsyncDiv3Clk /*!< The async clock by DIV3, e.g. SOSCDIV3_CLK, SIRCDIV3_CLK. */ -} scg_async_clk_t; - -/*! - * @brief SCG asynchronous clock divider value. - */ -typedef enum scg_async_clk_div -{ - kSCG_AsyncClkDisable = 0U, /*!< Clock output is disabled. */ - kSCG_AsyncClkDivBy1 = 1U, /*!< Divided by 1. */ - kSCG_AsyncClkDivBy2 = 2U, /*!< Divided by 2. */ - kSCG_AsyncClkDivBy4 = 3U, /*!< Divided by 4. */ - kSCG_AsyncClkDivBy8 = 4U, /*!< Divided by 8. */ - kSCG_AsyncClkDivBy16 = 5U, /*!< Divided by 16. */ - kSCG_AsyncClkDivBy32 = 6U, /*!< Divided by 32. */ - kSCG_AsyncClkDivBy64 = 7U /*!< Divided by 64. */ -} scg_async_clk_div_t; - -/*! - * @brief SCG system OSC monitor mode. - */ -typedef enum _scg_sosc_monitor_mode -{ - kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ - kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the system OSC error is detected. */ - kSCG_SysOscMonitorReset = - SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the system OSC error is detected. */ -} scg_sosc_monitor_mode_t; - -/*! @brief OSC enable mode. */ -enum _scg_sosc_enable_mode -{ - kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK, /*!< Enable OSC clock. */ - kSCG_SysOscEnableInStop = SCG_SOSCCSR_SOSCSTEN_MASK, /*!< Enable OSC in stop mode. */ - kSCG_SysOscEnableInLowPower = SCG_SOSCCSR_SOSCLPEN_MASK, /*!< Enable OSC in low power mode. */ -}; - -/*! - * @brief SCG system OSC configuration. - */ -typedef struct _scg_sosc_config -{ - uint32_t freq; /*!< System OSC frequency. */ - scg_sosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected. */ - uint8_t enableMode; /*!< Enable mode, OR'ed value of _scg_sosc_enable_mode. */ - - scg_async_clk_div_t div1; /*!< SOSCDIV1 value. */ - scg_async_clk_div_t div2; /*!< SOSCDIV2 value. */ - scg_async_clk_div_t div3; /*!< SOSCDIV3 value. */ - -} scg_sosc_config_t; - -/*! - * @brief SCG slow IRC clock frequency range. - */ -typedef enum _scg_sirc_range -{ - kSCG_SircRangeLow, /*!< Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP). */ - kSCG_SircRangeHigh /*!< Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP). */ -} scg_sirc_range_t; - -/*! @brief SIRC enable mode. */ -enum _scg_sirc_enable_mode -{ - kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK, /*!< Enable SIRC clock. */ - kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK, /*!< Enable SIRC in stop mode. */ - kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK /*!< Enable SIRC in low power mode. */ -}; - -/*! - * @brief SCG slow IRC clock configuration. - */ -typedef struct _scg_sirc_config -{ - uint32_t enableMode; /*!< Enable mode, OR'ed value of _scg_sirc_enable_mode. */ - scg_async_clk_div_t div1; /*!< SIRCDIV1 value. */ - scg_async_clk_div_t div2; /*!< SIRCDIV2 value. */ - scg_async_clk_div_t div3; /*!< SIRCDIV3 value. */ - - scg_sirc_range_t range; /*!< Slow IRC frequency range. */ -} scg_sirc_config_t; - -/*! - * @brief SCG fast IRC trim mode. - */ -typedef enum _scg_firc_trim_mode -{ - kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, - /*!< FIRC trim enable but not enable trim value update. In this mode, the - trim value is fixed to the initialized value which is defined by - trimCoar and trimFine in configure structure \ref scg_firc_trim_config_t.*/ - - kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK - /*!< FIRC trim enable and trim value update enable. In this mode, the trim - value is auto update. */ - -} scg_firc_trim_mode_t; - -/*! - * @brief SCG fast IRC trim predivided value for system OSC. - */ -typedef enum _scg_firc_trim_div -{ - kSCG_FircTrimDivBy1, /*!< Divided by 1. */ - kSCG_FircTrimDivBy128, /*!< Divided by 128. */ - kSCG_FircTrimDivBy256, /*!< Divided by 256. */ - kSCG_FircTrimDivBy512, /*!< Divided by 512. */ - kSCG_FircTrimDivBy1024, /*!< Divided by 1024. */ - kSCG_FircTrimDivBy2048 /*!< Divided by 2048. */ -} scg_firc_trim_div_t; - -/*! - * @brief SCG fast IRC trim source. - */ -typedef enum _scg_firc_trim_src -{ - kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */ - kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ -} scg_firc_trim_src_t; - -/*! - * @brief SCG fast IRC clock trim configuration. - */ -typedef struct _scg_firc_trim_config -{ - scg_firc_trim_mode_t trimMode; /*!< FIRC trim mode. */ - scg_firc_trim_src_t trimSrc; /*!< Trim source. */ - scg_firc_trim_div_t trimDiv; /*!< Trim predivided value for the system OSC. */ - - uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_FircTrimUpdate. */ - uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_FircTrimUpdate. */ -} scg_firc_trim_config_t; - -/*! - * @brief SCG fast IRC clock frequency range. - */ -typedef enum _scg_firc_range -{ - kSCG_FircRange48M, /*!< Fast IRC is trimmed to 48 MHz. */ - kSCG_FircRange52M, /*!< Fast IRC is trimmed to 52 MHz. */ - kSCG_FircRange56M, /*!< Fast IRC is trimmed to 56 MHz. */ - kSCG_FircRange60M /*!< Fast IRC is trimmed to 60 MHz. */ -} scg_firc_range_t; - -/*! @brief FIRC enable mode. */ -enum _scg_firc_enable_mode -{ - kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK, /*!< Enable FIRC clock. */ - kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK, /*!< Enable FIRC in stop mode. */ - kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK, /*!< Enable FIRC in low power mode. */ - kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK /*!< Disable regulator. */ -}; - -/*! - * @brief SCG fast IRC clock configuration. - */ -typedef struct _scg_firc_config_t -{ - uint32_t enableMode; /*!< Enable mode, OR'ed value of _scg_firc_enable_mode. */ - - scg_async_clk_div_t div1; /*!< FIRCDIV1 value. */ - scg_async_clk_div_t div2; /*!< FIRCDIV2 value. */ - scg_async_clk_div_t div3; /*!< FIRCDIV3 value. */ - - scg_firc_range_t range; /*!< Fast IRC frequency range. */ - - const scg_firc_trim_config_t *trimConfig; /*!< Pointer to the FIRC trim configuration; set NULL to disable trim. */ -} scg_firc_config_t; - -/*! @brief LPFLL enable mode. */ -enum _scg_lpfll_enable_mode -{ - kSCG_LpFllEnable = SCG_LPFLLCSR_LPFLLEN_MASK, /*!< Enable LPFLL clock. */ -}; - -/*! - * @brief SCG LPFLL clock frequency range. - */ -typedef enum _scg_lpfll_range -{ - kSCG_LpFllRange48M, /*!< LPFLL is trimmed to 48MHz. */ - kSCG_LpFllRange72M, /*!< LPFLL is trimmed to 72MHz. */ - kSCG_LpFllRange96M, /*!< LPFLL is trimmed to 96MHz. */ - kSCG_LpFllRange120M /*!< LPFLL is trimmed to 120MHz. */ -} scg_lpfll_range_t; - -/*! - * @brief SCG LPFLL trim mode. - */ -typedef enum _scg_lpfll_trim_mode -{ - kSCG_LpFllTrimNonUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK, - /*!< LPFLL trim is enabled but the trim value update is not enabled. In this mode, the - trim value is fixed to the initialized value, which is defined by the @ref trimValue - in the structure @ref scg_lpfll_trim_config_t.*/ - - kSCG_LpFllTrimUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK | SCG_LPFLLCSR_LPFLLTRUP_MASK - /*!< FIRC trim is enabled and trim value update is enabled. In this mode, the trim - value is automatically updated. */ -} scg_lpfll_trim_mode_t; - -/*! - * @brief SCG LPFLL trim source. - */ -typedef enum _scg_lpfll_trim_src -{ - kSCG_LpFllTrimSrcSirc = 0U, /*!< SIRC. */ - kSCG_LpFllTrimSrcFirc = 1U, /*!< FIRC. */ - kSCG_LpFllTrimSrcSysOsc = 2U, /*!< System OSC. */ - kSCG_LpFllTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ -} scg_lpfll_trim_src_t; - -/*! - * @brief SCG LPFLL lock mode. - */ -typedef enum _scg_lpfll_lock_mode -{ - kSCG_LpFllLock1Lsb = 0U, /*!< Lock with 1 LSB. */ - kSCG_LpFllLock2Lsb = 1U /*!< Lock with 2 LSB. */ -} scg_lpfll_lock_mode_t; - -/*! - * @brief SCG LPFLL clock trim configuration. - */ -typedef struct _scg_lpfll_trim_config -{ - scg_lpfll_trim_mode_t trimMode; /*!< Trim mode. */ - scg_lpfll_lock_mode_t lockMode; /*!< Lock mode; Irrelevant if the trimMode is kSCG_LpFllTrimNonUpdate. */ - - scg_lpfll_trim_src_t trimSrc; /*!< Trim source. */ - uint8_t trimDiv; /*!< Trim predivideds value, which can be 0 ~ 31. - [ Trim source frequency / (trimDiv + 1) ] must be 2 MHz or 32768 Hz. */ - - uint8_t trimValue; /*!< Trim value; Irrelevant if trimMode is the kSCG_LpFllTrimUpdate. */ -} scg_lpfll_trim_config_t; - -/*! - * @brief SCG low power FLL configuration. - */ -typedef struct _scg_lpfll_config -{ - uint8_t enableMode; /*!< Enable mode, OR'ed value of _scg_lpfll_enable_mode */ - - scg_async_clk_div_t div1; /*!< LPFLLDIV1 value. */ - scg_async_clk_div_t div2; /*!< LPFLLDIV2 value. */ - scg_async_clk_div_t div3; /*!< LPFLLDIV3 value. */ - - scg_lpfll_range_t range; /*!< LPFLL frequency range. */ - - const scg_lpfll_trim_config_t *trimConfig; /*!< Trim configuration; set NULL to disable trim. */ -} scg_lpfll_config_t; - -/*! - * @brief SCG RTC OSC monitor mode. - */ -typedef enum _scg_rosc_monitor_mode -{ - kSCG_rtcOscMonitorDisable = 0U, /*!< Monitor disable. */ - kSCG_rtcOscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ - kSCG_rtcOscMonitorReset = - SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */ -} scg_rosc_monitor_mode_t; - -/*! - * @brief SCG RTC OSC configuration. - */ -typedef struct _scg_rosc_config -{ - scg_rosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected. */ -} scg_rosc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Enable the clock for specific IP. - * - * @param name Which clock to enable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_EnableClock(clock_ip_name_t name) -{ - assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK); - - (*(volatile uint32_t *)name) |= PCC_CLKCFG_CGC_MASK; -} - -/*! - * @brief Disable the clock for specific IP. - * - * @param name Which clock to disable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_DisableClock(clock_ip_name_t name) -{ - assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK); - - (*(volatile uint32_t *)name) &= ~PCC_CLKCFG_CGC_MASK; -} - -/*! - * @brief Check whether the clock is already enabled and configured by - * any other core. - * - * @param name Which peripheral to check, see \ref clock_ip_name_t. - * @return True if clock is already enabled, otherwise false. - */ -static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name) -{ - assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK); - - return ((*(volatile uint32_t *)name) & PCC_CLKCFG_INUSE_MASK) ? true : false; -} - -/*! - * @brief Set the clock source for specific IP module. - * - * Set the clock source for specific IP, not all modules need to set the - * clock source, should only use this function for the modules need source - * setting. - * - * @param name Which peripheral to check, see \ref clock_ip_name_t. - * @param src Clock source to set. - */ -static inline void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src) -{ - uint32_t reg = (*(volatile uint32_t *)name); - - assert(reg & PCC_CLKCFG_PR_MASK); - assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other core. */ - - reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); - - /* - * If clock is already enabled, first disable it, then set the clock - * source and re-enable it. - */ - (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK; - (*(volatile uint32_t *)name) = reg; -} - -/*! - * @brief Set the clock source and divider for specific IP module. - * - * Set the clock source and divider for specific IP, not all modules need to - * set the clock source and divider, should only use this function for the - * modules need source and divider setting. - * - * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]). - * - * @param name Which peripheral to check, see \ref clock_ip_name_t. - * @param src Clock source to set. - * @param divValue The divider value. - * @param fracValue The fraction multiply value. - */ -static inline void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue) -{ - uint32_t reg = (*(volatile uint32_t *)name); - - assert(reg & PCC_CLKCFG_PR_MASK); - assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other core. */ - - reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS(src) | - PCC_CLKCFG_PCD(divValue) | PCC_CLKCFG_FRAC(fracValue); - - /* - * If clock is already enabled, first disable it, then set the clock - * source and re-enable it. - */ - (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK; - (*(volatile uint32_t *)name) = reg; -} - -/*! - * @brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_name_t. - * - * @param clockName Clock names defined in clock_name_t - * @return Clock frequency value in hertz - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); - -/*! - * @brief Get the core clock or system clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); - -/*! - * @brief Get the platform clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetPlatClkFreq(void); - -/*! - * @brief Get the bus clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetBusClkFreq(void); - -/*! - * @brief Get the flash clock frequency. - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetFlashClkFreq(void); - -/*! - * @brief Get the OSC 32K clock frequency (OSC32KCLK). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetOsc32kClkFreq(void); - -/*! - * @brief Get the external clock frequency (EXTCLK). - * - * @return Clock frequency in Hz. - */ -uint32_t CLOCK_GetExtClkFreq(void); - -/*! - * @brief Get the LPO clock frequency. - * - * @return Clock frequency in Hz. - */ -static inline uint32_t CLOCK_GetLpoClkFreq(void) -{ - return LPO_CLK_FREQ; /* 1k Hz. */ -} - -/*! - * @brief Gets the functional clock frequency for a specific IP module. - * - * This function gets the IP module's functional clock frequency based on PCC - * registers. It is only used for the IP modules which could select clock source - * by PCC[PCS]. - * - * @param name Which peripheral to get, see \ref clock_ip_name_t. - * @return Clock frequency value in Hz - */ -uint32_t CLOCK_GetIpFreq(clock_ip_name_t name); - -/*! -* @brief Enable the RTC Oscillator. -* -* This function enables the Oscillator for RTC external crystal. -* -* @param enable Enable the Oscillator or not. -*/ -static inline void CLOCK_EnableRtcOsc(bool enable) -{ - if (enable) - { - RTC->CR |= RTC_CR_OSCE_MASK; - } - else - { - RTC->CR &= ~RTC_CR_OSCE_MASK; - } -} - -/*! -* @brief Enable the RSIM Run Regulator Request. -* -* When this function is enabled, the RSIM will request the SPM Run Regulator to be turned on and the -* RSIM will then stop requesting Stop after the Run Regulator Acknowledge signal is received from -* the SPM module. -* The RF OSC would be only available while this function is enabled. -* -* @param enable Enable the function or not. -*/ -static inline void CLOCK_EnableRSIMRunRequest(bool enable) -{ - if (enable) - { - RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; - } - else - { - RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; - } -} - -/*! @brief Enable USB FS clock. - * - * @param src USB FS clock source. - * @param freq The frequency specified by src. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB FS clock. - */ -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Disable USB FS clock. - * - * Disable USB FS clock. - */ -static inline void CLOCK_DisableUsbfs0Clock(void) -{ - CLOCK_DisableClock(kCLOCK_Usb0); -} - -/*! - * @name MCU System Clock. - * @{ - */ - -/*! - * @brief Gets the SCG system clock frequency. - * - * This function gets the SCG system clock frequency. These clocks are used for - * core, platform, external, and bus clock domains. - * - * @param type Which type of clock to get, core clock or slow clock. - * @return Clock frequency. - */ -uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type); - -/*! - * @brief Sets the system clock configuration for VLPR mode. - * - * This function sets the system clock configuration for VLPR mode. - * - * @param config Pointer to the configuration. - */ -static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *config) -{ - assert(config); - - SCG->VCCR = *(const uint32_t *)config; -} - -/*! - * @brief Sets the system clock configuration for RUN mode. - * - * This function sets the system clock configuration for RUN mode. - * - * @param config Pointer to the configuration. - */ -static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *config) -{ - assert(config); - - SCG->RCCR = *(const uint32_t *)config; -} - -/*! - * @brief Sets the system clock configuration for HSRUN mode. - * - * This function sets the system clock configuration for HSRUN mode. - * - * @param config Pointer to the configuration. - */ -static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *config) -{ - assert(config); - - SCG->HCCR = *(const uint32_t *)config; -} - -/*! - * @brief Gets the system clock configuration in the current power mode. - * - * This function gets the system configuration in the current power mode. - * - * @param config Pointer to the configuration. - */ -static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config) -{ - assert(config); - - *(uint32_t *)config = SCG->CSR; -} - -/*! - * @brief Sets the clock out selection. - * - * This function sets the clock out selection (CLKOUTSEL). - * - * @param setting The selection to set. - * @return The current clock out selection. - */ -static inline void CLOCK_SetClkOutSel(clock_clkout_src_t setting) -{ - SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting); -} -/* @} */ - -/*! - * @name SCG System OSC Clock. - * @{ - */ - -/*! - * @brief Initializes the SCG system OSC. - * - * This function enables the SCG system OSC clock according to the - * configuration. - * - * @param config Pointer to the configuration structure. - * @retval kStatus_Success System OSC is initialized. - * @retval kStatus_SCG_Busy System OSC has been enabled and is used by the system clock. - * @retval kStatus_ReadOnly System OSC control register is locked. - * - * @note This function can't detect whether the system OSC has been enabled and - * used by an IP. - */ -status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config); - -/*! - * @brief De-initializes the SCG system OSC. - * - * This function disables the SCG system OSC clock. - * - * @retval kStatus_Success System OSC is deinitialized. - * @retval kStatus_SCG_Busy System OSC is used by the system clock. - * @retval kStatus_ReadOnly System OSC control register is locked. - * - * @note This function can't detect whether the system OSC is used by an IP. - */ -status_t CLOCK_DeinitSysOsc(void); - -/*! - * @brief Set the asynchronous clock divider. - * - * @param asyncClk Which asynchronous clock to configure. - * @param divider The divider value to set. - * - * @note There might be glitch when changing the asynchronous divider, so make sure - * the asynchronous clock is not used while changing divider. - */ -static inline void CLOCK_SetSysOscAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) -{ - uint32_t reg = SCG->SOSCDIV; - - switch (asyncClk) - { - case kSCG_AsyncDiv3Clk: - reg = (reg & ~SCG_SOSCDIV_SOSCDIV3_MASK) | SCG_SOSCDIV_SOSCDIV3(divider); - break; - case kSCG_AsyncDiv2Clk: - reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider); - break; - default: - reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); - break; - } - - SCG->SOSCDIV = reg; -} - -/*! - * @brief Gets the SCG system OSC clock frequency (SYSOSC). - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetSysOscFreq(void); - -/*! - * @brief Gets the SCG asynchronous clock frequency from the system OSC. - * - * @param type The asynchronous clock type. - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type); - -/*! - * @brief Checks whether the system OSC clock error occurs. - * - * @return True if the error occurs, false if not. - */ -static inline bool CLOCK_IsSysOscErr(void) -{ - return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCERR_MASK); -} - -/*! - * @brief Clears the system OSC clock error. - */ -static inline void CLOCK_ClearSysOscErr(void) -{ - SCG->SOSCCSR |= SCG_SOSCCSR_SOSCERR_MASK; -} - -/*! - * @brief Sets the system OSC monitor mode. - * - * This function sets the system OSC monitor mode. The mode can be disabled, - * it can generate an interrupt when the error is disabled, or reset when the error is detected. - * - * @param mode Monitor mode to set. - */ -static inline void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) -{ - uint32_t reg = SCG->SOSCCSR; - - reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); - - reg |= (uint32_t)mode; - - SCG->SOSCCSR = reg; -} - -/*! - * @brief Checks whether the system OSC clock is valid. - * - * @return True if clock is valid, false if not. - */ -static inline bool CLOCK_IsSysOscValid(void) -{ - return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK); -} -/* @} */ - -/*! - * @name SCG Slow IRC Clock. - * @{ - */ - -/*! - * @brief Initializes the SCG slow IRC clock. - * - * This function enables the SCG slow IRC clock according to the - * configuration. - * - * @param config Pointer to the configuration structure. - * @retval kStatus_Success SIRC is initialized. - * @retval kStatus_SCG_Busy SIRC has been enabled and is used by system clock. - * @retval kStatus_ReadOnly SIRC control register is locked. - * - * @note This function can't detect whether the system OSC has been enabled and - * used by an IP. - */ -status_t CLOCK_InitSirc(const scg_sirc_config_t *config); - -/*! - * @brief De-initializes the SCG slow IRC. - * - * This function disables the SCG slow IRC. - * - * @retval kStatus_Success SIRC is deinitialized. - * @retval kStatus_SCG_Busy SIRC is used by system clock. - * @retval kStatus_ReadOnly SIRC control register is locked. - * - * @note This function can't detect whether the SIRC is used by an IP. - */ -status_t CLOCK_DeinitSirc(void); - -/*! - * @brief Set the asynchronous clock divider. - * - * @param asyncClk Which asynchronous clock to configure. - * @param divider The divider value to set. - * - * @note There might be glitch when changing the asynchronous divider, so make sure - * the asynchronous clock is not used while changing divider. - */ -static inline void CLOCK_SetSircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) -{ - uint32_t reg = SCG->SIRCDIV; - - switch (asyncClk) - { - case kSCG_AsyncDiv3Clk: - reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider); - break; - case kSCG_AsyncDiv2Clk: - reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider); - break; - default: - reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider); - break; - } - - SCG->SIRCDIV = reg; -} - -/*! - * @brief Gets the SCG SIRC clock frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetSircFreq(void); - -/*! - * @brief Gets the SCG asynchronous clock frequency from the SIRC. - * - * @param type The asynchronous clock type. - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type); - -/*! - * @brief Checks whether the SIRC clock is valid. - * - * @return True if clock is valid, false if not. - */ -static inline bool CLOCK_IsSircValid(void) -{ - return (bool)(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK); -} -/* @} */ - -/*! - * @name SCG Fast IRC Clock. - * @{ - */ - -/*! - * @brief Initializes the SCG fast IRC clock. - * - * This function enables the SCG fast IRC clock according to the configuration. - * - * @param config Pointer to the configuration structure. - * @retval kStatus_Success FIRC is initialized. - * @retval kStatus_SCG_Busy FIRC has been enabled and is used by the system clock. - * @retval kStatus_ReadOnly FIRC control register is locked. - * - * @note This function can't detect whether the FIRC has been enabled and - * used by an IP. - */ -status_t CLOCK_InitFirc(const scg_firc_config_t *config); - -/*! - * @brief De-initializes the SCG fast IRC. - * - * This function disables the SCG fast IRC. - * - * @retval kStatus_Success FIRC is deinitialized. - * @retval kStatus_SCG_Busy FIRC is used by the system clock. - * @retval kStatus_ReadOnly FIRC control register is locked. - * - * @note This function can't detect whether the FIRC is used by an IP. - */ -status_t CLOCK_DeinitFirc(void); - -/*! - * @brief Set the asynchronous clock divider. - * - * @param asyncClk Which asynchronous clock to configure. - * @param divider The divider value to set. - * - * @note There might be glitch when changing the asynchronous divider, so make sure - * the asynchronous clock is not used while changing divider. - */ -static inline void CLOCK_SetFircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) -{ - uint32_t reg = SCG->FIRCDIV; - - switch (asyncClk) - { - case kSCG_AsyncDiv3Clk: - reg = (reg & ~SCG_FIRCDIV_FIRCDIV3_MASK) | SCG_FIRCDIV_FIRCDIV3(divider); - break; - case kSCG_AsyncDiv2Clk: - reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider); - break; - default: - reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider); - break; - } - - SCG->FIRCDIV = reg; -} - -/*! - * @brief Gets the SCG FIRC clock frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetFircFreq(void); - -/*! - * @brief Gets the SCG asynchronous clock frequency from the FIRC. - * - * @param type The asynchronous clock type. - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type); - -/*! - * @brief Checks whether the FIRC clock error occurs. - * - * @return True if the error occurs, false if not. - */ -static inline bool CLOCK_IsFircErr(void) -{ - return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK); -} - -/*! - * @brief Clears the FIRC clock error. - */ -static inline void CLOCK_ClearFircErr(void) -{ - SCG->FIRCCSR |= SCG_FIRCCSR_FIRCERR_MASK; -} - -/*! - * @brief Checks whether the FIRC clock is valid. - * - * @return True if clock is valid, false if not. - */ -static inline bool CLOCK_IsFircValid(void) -{ - return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK); -} -/* @} */ - -/*! - * @brief Gets the SCG RTC OSC clock frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetRtcOscFreq(void); - -/*! - * @brief Checks whether the RTC OSC clock error occurs. - * - * @return True if error occurs, false if not. - */ -static inline bool CLOCK_IsRtcOscErr(void) -{ - return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCERR_MASK); -} - -/*! - * @brief Clears the RTC OSC clock error. - */ -static inline void CLOCK_ClearRtcOscErr(void) -{ - SCG->ROSCCSR |= SCG_ROSCCSR_ROSCERR_MASK; -} - -/*! - * @brief Sets the RTC OSC monitor mode. - * - * This function sets the RTC OSC monitor mode. The mode can be disabled. - * It can generate an interrupt when the error is disabled, or reset when the error is detected. - * - * @param mode Monitor mode to set. - */ -static inline void CLOCK_SetRtcOscMonitorMode(scg_rosc_monitor_mode_t mode) -{ - uint32_t reg = SCG->ROSCCSR; - - reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK); - - reg |= (uint32_t)mode; - - SCG->ROSCCSR = reg; -} - -/*! - * @brief Checks whether the RTC OSC clock is valid. - * - * @return True if the clock is valid, false if not. - */ -static inline bool CLOCK_IsRtcOscValid(void) -{ - return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK); -} -/* @} */ - -/*! - * @name SCG Low Power FLL Clock. - * @{ - */ -/*! - * @brief Initializes the SCG LPFLL clock. - * - * This function enables the SCG LPFLL clock according to the configuration. - * - * @param config Pointer to the configuration structure. - * @retval kStatus_Success LPFLL is initialized. - * @retval kStatus_SCG_Busy LPFLL has been enabled and is used by the system clock. - * @retval kStatus_ReadOnly LPFLL control register is locked. - * - * @note This function can't detect whether the LPFLL has been enabled and - * used by an IP. - */ -status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config); - -/*! - * @brief De-initializes the SCG LPFLL. - * - * This function disables the SCG LPFLL. - * - * @retval kStatus_Success LPFLL is deinitialized. - * @retval kStatus_SCG_Busy LPFLL is used by the system clock. - * @retval kStatus_ReadOnly LPFLL control register is locked. - * - * @note This function can't detect whether the LPFLL is used by an IP. - */ -status_t CLOCK_DeinitLpFll(void); - -/*! - * @brief Set the asynchronous clock divider. - * - * @param asyncClk Which asynchronous clock to configure. - * @param divider The divider value to set. - * - * @note There might be glitch when changing the asynchronous divider, so make sure - * the asynchronous clock is not used while changing divider. - */ -static inline void CLOCK_SetLpFllAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) -{ - uint32_t reg = SCG->LPFLLDIV; - - switch (asyncClk) - { - case kSCG_AsyncDiv2Clk: - reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider); - break; - default: - reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV1_MASK) | SCG_LPFLLDIV_LPFLLDIV1(divider); - break; - } - - SCG->LPFLLDIV = reg; -} - -/*! - * @brief Gets the SCG LPFLL clock frequency. - * - * @return Clock frequency in Hz; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetLpFllFreq(void); - -/*! - * @brief Gets the SCG asynchronous clock frequency from the LPFLL. - * - * @param type The asynchronous clock type. - * @return Clock frequency in Hz; If the clock is invalid, returns 0. - */ -uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type); - -/*! - * @brief Checks whether the LPFLL clock is valid. - * - * @return True if the clock is valid, false if not. - */ -static inline bool CLOCK_IsLpFllValid(void) -{ - return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); -} -/* @} */ - -/*! - * @name External clock frequency - * @{ - */ - -/*! - * @brief Sets the XTAL0 frequency based on board settings. - * - * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal0Freq(uint32_t freq) -{ - g_xtal0Freq = freq; -} - -/*! - * @brief Sets the XTAL32 frequency based on board settings. - * - * @param freq The XTAL32/EXTAL32 input clock frequency in Hz. - */ -static inline void CLOCK_SetXtal32Freq(uint32_t freq) -{ - g_xtal32Freq = freq; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.c deleted file mode 100644 index be4ce2ad8c45ef31ab3499006e9d3745f4acde29..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.c +++ /dev/null @@ -1,117 +0,0 @@ -/* -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP -* All rights reserved. -* -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -#include "fsl_common.h" -#include "fsl_debug_console.h" - -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif(defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ -#endif /* NDEBUG */ - -#ifndef __GIC_PRIO_BITS -#ifndef __riscv -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - - return ret; -} -#endif -#endif - -#ifndef QN908XC_SERIES -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t index = 0; - uint32_t intNumber = (uint32_t)interrupt; - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#endif /* QN908XC_SERIES */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.h deleted file mode 100644 index 3aea4993c4d7d4bda39f1a89e8e836530c19ddb3..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_common.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__CC_ARM) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__CC_ARM)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#endif -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ -static inline status_t EnableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0) - EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt); - /* Read back to make sure write finished. */ - (void)EVENT_UNIT->INTPTEN; -#else -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif -#endif - return kStatus_Success; -} - -/*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ -static inline status_t DisableIRQ(IRQn_Type interrupt) -{ - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0) - EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt); - /* Read back to make sure write finished. */ - (void)EVENT_UNIT->INTPTEN; -#else -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif -#endif - return kStatus_Success; -} - -/*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ -static inline uint32_t DisableGlobalIRQ(void) -{ -#ifndef __riscv -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -#else - uint32_t mstatus; - - __ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus)); - - return mstatus; -#endif -} - -/*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ -static inline void EnableGlobalIRQ(uint32_t primask) -{ -#ifndef __riscv -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -#else - __ASM volatile ("csrw mstatus, %0" : : "r"(primask)); -#endif -} - -/*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -/*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void EnableDeepSleepIRQ(IRQn_Type interrupt); - -/*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ -void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.c deleted file mode 100644 index 640a2e7abc0a182d08f0d6b2d98da44ab79d1fda..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @internal @brief Has data register with name CRC. */ -#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG -#define DATA CRC -#define DATALL CRCLL -#endif - -#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT -/* @brief Default user configuration structure for CRC-16-CCITT */ -#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U -/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ -#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU -/*< Default initial checksum */ -#define CRC_DRIVER_DEFAULT_REFLECT_IN false -/*< Default is no transpose */ -#define CRC_DRIVER_DEFAULT_REFLECT_OUT false -/*< Default is transpose bytes */ -#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false -/*< Default is without complement of CRC data register read data */ -#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 -/*< Default is 16-bit CRC protocol */ -#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum -/*< Default is resutl type is final checksum */ -#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ - -/*! @brief CRC type of transpose of read write data */ -typedef enum _crc_transpose_type -{ - kCrcTransposeNone = 0U, /*! No transpose */ - kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ - kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ - kCrcTransposeBytes = 3U, /*! Transpose bytes */ -} crc_transpose_type_t; - -/*! -* @brief CRC module configuration. -* -* This structure holds the configuration for the CRC module. -*/ -typedef struct _crc_module_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ - crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ -} crc_module_config_t; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns transpose type for CRC protocol reflect in parameter. - * - * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. - */ -static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); -} - -/*! - * @brief Returns transpose type for CRC protocol reflect out parameter. - * - * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. - * - * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. - */ -static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) -{ - return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); -} - -/*! - * @brief Starts checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts the checksum computation by writing the seed value - * - * @param base CRC peripheral address. - * @param config Pointer to protocol configuration structure. - */ -static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) -{ - uint32_t crcControl; - - /* pre-compute value for CRC control registger based on user configuraton without WAS field */ - crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | - CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); - - /* make sure the control register is clear - WAS is deasserted, and protocol is set */ - base->CTRL = crcControl; - - /* write polynomial register */ - base->GPOLY = config->polynomial; - - /* write pre-computed control register value along with WAS to start checksum computation */ - base->CTRL = crcControl | CRC_CTRL_WAS(true); - - /* write seed (initial checksum) */ - base->DATA = config->seed; - - /* deassert WAS by writing pre-computed CRC control register value */ - base->CTRL = crcControl; -} - -/*! - * @brief Starts final checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts final checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum - * (output reflection and xor functions are applied). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); - moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = protocolConfig->complementChecksum; - moduleConfig.crcBits = protocolConfig->crcBits; - - CRC_ConfigureAndStart(base, &moduleConfig); -} - -/*! - * @brief Starts intermediate checksum computation. - * - * Configures the CRC module for the specified CRC protocol. @n - * Starts intermediate checksum computation by writing the seed value. - * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). - * - * @param base CRC peripheral address. - * @param protocolConfig Pointer to protocol configuration structure. - */ -static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) -{ - crc_module_config_t moduleConfig; - /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ - moduleConfig.polynomial = protocolConfig->polynomial; - moduleConfig.seed = protocolConfig->seed; - moduleConfig.readTranspose = - kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ - moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); - moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ - moduleConfig.crcBits = protocolConfig->crcBits; - - CRC_ConfigureAndStart(base, &moduleConfig); -} - -void CRC_Init(CRC_Type *base, const crc_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* ungate clock */ - CLOCK_EnableClock(kCLOCK_Crc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* configure CRC module and write the seed */ - if (config->crcResult == kCrcFinalChecksum) - { - CRC_SetProtocolConfig(base, config); - } - else - { - CRC_SetRawProtocolConfig(base, config); - } -} - -void CRC_GetDefaultConfig(crc_config_t *config) -{ - static const crc_config_t crc16ccit = { - CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, - CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, - CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, - CRC_DRIVER_DEFAULT_CRC_RESULT, - }; - - *config = crc16ccit; -} - -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) -{ - const uint32_t *data32; - - /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } - - /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; - while (dataSize >= sizeof(uint32_t)) - { - base->DATA = *data32; - data32++; - dataSize -= sizeof(uint32_t); - } - - data = (const uint8_t *)data32; - - /* 8-bit reads and writes till end of data buffer */ - while (dataSize) - { - base->ACCESS8BIT.DATALL = *data; - data++; - dataSize--; - } -} - -uint32_t CRC_Get32bitResult(CRC_Type *base) -{ - return base->DATA; -} - -uint16_t CRC_Get16bitResult(CRC_Type *base) -{ - uint32_t retval; - uint32_t totr; /* type of transpose read bitfield */ - - retval = base->DATA; - totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; - - /* check transpose type to get 16-bit out of 32-bit register */ - if (totr >= 2U) - { - /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ - retval &= 0xFFFF0000U; - retval = retval >> 16U; - } - else - { - /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ - retval &= 0x0000FFFFU; - } - return (uint16_t)retval; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.h deleted file mode 100644 index f8907d363b21b408f9d37e146fdf82d9a794ee36..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_crc.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CRC_H_ -#define _FSL_CRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup crc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CRC driver version. Version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.1 - * - move DATA and DATALL macro definition from header file to source file - */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#ifndef CRC_DRIVER_CUSTOM_DEFAULTS -/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ -#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 -#endif - -/*! @brief CRC bit width */ -typedef enum _crc_bits -{ - kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ - kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ -} crc_bits_t; - -/*! @brief CRC result type */ -typedef enum _crc_result -{ - kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. - Reflect out and final xor protocol features are applied. */ - kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). - Reflect out and final xor protocol feature are not applied. - Intermediate checksum can be used as a seed for CRC_Init() - to continue adding data to this checksum. */ -} crc_result_t; - -/*! -* @brief CRC protocol configuration. -* -* This structure holds the configuration for the CRC protocol. -* -*/ -typedef struct _crc_config -{ - uint32_t polynomial; /*!< CRC Polynomial, MSBit first. - Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ - uint32_t seed; /*!< Starting checksum value */ - bool reflectIn; /*!< Reflect bits on input. */ - bool reflectOut; /*!< Reflect bits on output. */ - bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ - crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ - crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or - CRC_Get32bitResult() */ -} crc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Enables and configures the CRC peripheral module. - * - * This function enables the clock gate in the SIM module for the CRC peripheral. - * It also configures the CRC module and starts a checksum computation by writing the seed. - * - * @param base CRC peripheral address. - * @param config CRC module configuration structure. - */ -void CRC_Init(CRC_Type *base, const crc_config_t *config); - -/*! - * @brief Disables the CRC peripheral module. - * - * This function disables the clock gate in the SIM module for the CRC peripheral. - * - * @param base CRC peripheral address. - */ -static inline void CRC_Deinit(CRC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* gate clock */ - CLOCK_DisableClock(kCLOCK_Crc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Loads default values to the CRC protocol configuration structure. - * - * Loads default values to the CRC protocol configuration structure. The default values are as follows. - * @code - * config->polynomial = 0x1021; - * config->seed = 0xFFFF; - * config->reflectIn = false; - * config->reflectOut = false; - * config->complementChecksum = false; - * config->crcBits = kCrcBits16; - * config->crcResult = kCrcFinalChecksum; - * @endcode - * - * @param config CRC protocol configuration structure. - */ -void CRC_GetDefaultConfig(crc_config_t *config); - -/*! - * @brief Writes data to the CRC module. - * - * Writes input data buffer bytes to the CRC data register. - * The configured type of transpose is applied. - * - * @param base CRC peripheral address. - * @param data Input data stream, MSByte in data[0]. - * @param dataSize Size in bytes of the input data buffer. - */ -void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); - -/*! - * @brief Reads the 32-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * @param base CRC peripheral address. - * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. - */ -uint32_t CRC_Get32bitResult(CRC_Type *base); - -/*! - * @brief Reads a 16-bit checksum from the CRC module. - * - * Reads the CRC data register (either an intermediate or the final checksum). - * The configured type of transpose and complement is applied. - * - * @param base CRC peripheral address. - * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. - */ -uint16_t CRC_Get16bitResult(CRC_Type *base); - -#if defined(__cplusplus) -} -#endif - -/*! - *@} - */ - -#endif /* _FSL_CRC_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.c deleted file mode 100644 index 9f95b98e8120728e751ddf49da3b341b6d121e75..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dac.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for DAC module. - * - * @param base DAC peripheral base address - */ -static uint32_t DAC_GetInstance(LPDAC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to DAC bases for each instance. */ -static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS; - -/*! @brief Pointers to DAC clocks for each instance. */ -static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DAC_GetInstance(LPDAC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) - { - if (s_dacBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dacBases)); - - return instance; -} - -void DAC_Init(LPDAC_Type *base, const dac_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0U; - - /* Enable the clock. */ - CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); - - /* Reset the logic. */ - DAC_SetReset(base, kDAC_ResetLogic); - DAC_ClearReset(base, kDAC_ResetLogic); - - /* Reset the FIFO. */ - DAC_SetReset(base, kDAC_ResetFIFO); - DAC_ClearReset(base, kDAC_ResetFIFO); - - /* Configuration. */ - if (kDAC_FIFOTriggerBySoftwareMode == config->fifoTriggerMode) - { - tmp32 |= LPDAC_GCR_TRGSEL_MASK; /* Software trigger. */ - } - switch (config->fifoWorkMode) - { - case kDAC_FIFOWorkAsNormalMode: /* Normal FIFO. */ - tmp32 |= LPDAC_GCR_FIFOEN_MASK; - break; - case kDAC_FIFOWorkAsSwingMode: - tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_SWMD_MASK; /* Enable swing mode. */ - break; - default: /* kDAC_FIFODisabled. */ - break; - } - if (config->enableLowPowerMode) - { - tmp32 |= LPDAC_GCR_LPEN_MASK; /* Enable low power. */ - } - if (kDAC_ReferenceVoltageSourceAlt2 == config->referenceVoltageSource) - { - tmp32 |= LPDAC_GCR_DACRFS_MASK; - } - base->GCR = tmp32; - base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); - - /* Now, the DAC is disabled. It needs to be enabled in application. */ -} - -void DAC_GetDefaultConfig(dac_config_t *config) -{ - assert(config != NULL); - - config->fifoWatermarkLevel = 0U; - config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; - config->fifoWorkMode = kDAC_FIFODisabled; - config->enableLowPowerMode = false; - config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; -} - -void DAC_Deinit(LPDAC_Type *base) -{ - /* Disable the module. */ - DAC_Enable(base, false); - - /* Disable the clock. */ - CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.h deleted file mode 100644 index a387e4fa26a9ab98e2a949557515424d7442da7c..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dac.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DAC_H_ -#define _FSL_DAC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dac - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DAC driver version 2.0.0. */ -#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief DAC reset control. - */ -enum _dac_reset_control -{ - kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */ - kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */ -}; - -/*! - * @brief DAC interrupts. - */ -enum _dac_interrupt_enable -{ - kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */ - kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */ - kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */ - kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */ - kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */ - kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */ -}; - -/*! - * @brief DAC DMA switchers. - */ -enum _dac_dma_enable -{ - kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */ - kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */ -}; - -/*! - * @brief DAC status flags. - */ -enum _dac_status_flags -{ - kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is -empty. The FIFO read pointer will not -increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1 -to it. */ - - kDAC_FIFOOverflowFlag = LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the -buffer is full. The writer pointer will -not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it. -*/ - - kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of -conversion in swing back mode. It means -that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For -example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the -read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is -cleared by writing a 1 to it. */ - - kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or equal -to the setting value of wartermark. By writing data into -FIFO by DMA or CPU, this flag is cleared automatically when the data in FIFO is more than the setting value of -watermark. */ - - kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */ - kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */ -}; - -/*! - * @brief DAC FIFO trigger mode. - */ -typedef enum _dac_fifo_trigger_mode -{ - kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ - kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ -} dac_fifo_trigger_mode_t; - -/*! - * @brief DAC FIFO work mode. - */ -typedef enum _dac_fifo_work_mode -{ - kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes - to buffer then goes to conversion. */ - kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to - conversion. */ - kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That - is, the trigger increases the read pointer till reach the writer pointer and - decreases the read pointer till zero, and so on. The FIFO empty/full/watermark - flag will not update during swing back mode. */ -} dac_fifo_work_mode_t; - -/*! - * @brief DAC reference voltage source. - */ -typedef enum _dac_reference_voltage_source -{ - kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */ - kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */ -} dac_reference_voltage_source_t; - -/*! - * @brief DAC configuration structure. - */ -typedef struct _dac_config -{ - uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ - dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */ - dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */ - bool enableLowPowerMode; /*!< Enable the low power mode. */ - dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ -} dac_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and de-initialization - * @{ - */ - -/*! - * @brief Initialize the DAC module with common configuartion. - * - * The clock will be enabled in this function. - * - * @param base DAC peripheral base address. - * @param config Pointer to configuration structure. - */ -void DAC_Init(LPDAC_Type *base, const dac_config_t *config); - -/*! - * @brief Get the default settings for initialization's configuration. - * - * This function initializes the user configuration structure to a default value. The default values are: - * @code - * config->fifoWatermarkLevel = 0U; - * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; - * config->fifoWorkMode = kDAC_FIFODisabled; - * config->enableLowPowerMode = false; - * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; - * @endcode - * - * @param config Pointer to configuration structure. - * @param - */ -void DAC_GetDefaultConfig(dac_config_t *config); - -/*! - * @brief De-initialize the DAC module. - * - * The clock will be disabled in this function. - * - * @param base DAC peripheral base address. - * @param - */ -void DAC_Deinit(LPDAC_Type *base); - -/*! - * @brief Assert the reset control to part hardware. - * - * This fucntion is to assert the reset control to part hardware. Responding part hardware would remain reset untill - * cleared by software. - * - * @param base DAC peripheral base address. - * @param mask The reset control mask, see to #_dac_reset_control_t. - */ -static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask) -{ - base->RCR |= mask; -} - -/*! - * @brief Clear the reset control to part hardware. - * - * This fucntion is to clear the reset control to part hardware. Responding part hardware would work after the reset - * control is cleared by software. - * - * @param base DAC peripheral base address. - * @param mask The reset control mask, see to #_dac_reset_control_t. - */ -static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask) -{ - base->RCR &= ~mask; -} - -/*! - * @brief Enable the DAC hardware system or not. - * - * This function is to start the Programmable Reference Generator operation or not. - * - * @param base DAC peripheral base address. - * @param enable Assertion of indicated event. - */ -static inline void DAC_Enable(LPDAC_Type *base, bool enable) -{ - if (enable) - { - base->GCR |= LPDAC_GCR_DACEN_MASK; - } - else - { - base->GCR &= ~LPDAC_GCR_DACEN_MASK; - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable the interrupts. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated interrupt events. See to #_dac_interrupt_enable. - */ -static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disable the interrupts. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated interrupt events. See to #_dac_interrupt_enable. - */ -static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/* @} */ - -/*! - * @name DMA control - * @{ - */ - -/*! - * @brief Enable the DMA switchers or not. - * - * @param base DAC peripheral base address. - * @param mask Mask value of indicated DMA requeset. See to #_dac_dma_enable. - * @param enable Enable the DMA or not. - */ -static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->DER |= mask; - } - else - { - base->DER &= ~mask; - } -} - -/* @} */ - -/*! - * @name Status flags - * @{ - */ - -/*! - * @brief Get status flags of DAC module. - * - * @param base DAC peripheral base address. - * @return Mask value of status flags. See to #_dac_status_flags. - */ -static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base) -{ - return base->FSR; -} - -/*! - * @brief Clear status flags of DAC module. - * - * @param base DAC peripheral base address. - * @param flags Mask value of status flags to be cleared. See to #_dac_status_flags. - */ -static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags) -{ - base->FSR = flags; -} - -/* @} */ - -/*! - * @name Functional feature - * @{ - */ - -/*! - * @brief Set data into the entry of FIFO buffer. - * - * @param base DAC peripheral base address. - * @param value Setting value into FIFO buffer. - */ -static inline void DAC_SetData(LPDAC_Type *base, uint32_t value) -{ - base->DATA = LPDAC_DATA_DATA(value); -} - -/*! - * @brief Get the value of the FIFO write pointer. - * - * @param base DAC peripheral base address. - * @return Current value of the FIFO write pointer. - */ - -static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base) -{ - return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT; -} - -/*! - * @brief Get the value of the FIFO read pointer. - * - * @param base DAC peripheral base address. - * @return Current value of the FIFO read pointer. - */ - -static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base) -{ - return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT; -} - -/*! - * @brief Do software trigger to FIFO when in software mode. - * - * @param base DAC peripheral base address. - */ - -static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) -{ - base->TCR = LPDAC_TCR_SWTRG_MASK; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _FSL_DAC12_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.c deleted file mode 100644 index 37fbc01006dbc91cecf9d3c5cb71280760fcf7ff..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMAMUX. - * - * @param base DMAMUX peripheral base address. - */ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMAMUX instance number to base pointer. */ -static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMAMUX instance number to clock name. */ -static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) - { - if (s_dmamuxBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmamuxBases)); - - return instance; -} - -void DMAMUX_Init(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DMAMUX_Deinit(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.h deleted file mode 100644 index f458f8de2d6a7842eedb0c7f66cc0ca85ca282c5..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_dmamux.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DMAMUX_H_ -#define _FSL_DMAMUX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmamux - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMAMUX driver version 2.0.2. */ -#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMAMUX Initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the DMAMUX peripheral. - * - * This function ungates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - * - */ -void DMAMUX_Init(DMAMUX_Type *base); - -/*! - * @brief Deinitializes the DMAMUX peripheral. - * - * This function gates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - */ -void DMAMUX_Deinit(DMAMUX_Type *base); - -/* @} */ -/*! - * @name DMAMUX Channel Operation - * @{ - */ - -/*! - * @brief Enables the DMAMUX channel. - * - * This function enables the DMAMUX channel. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Disables the DMAMUX channel. - * - * This function disables the DMAMUX channel. - * - * @note The user must disable the DMAMUX channel before configuring it. - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Configures the DMAMUX channel source. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param source Channel source, which is used to trigger the DMA transfer. - */ -static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); -} - -#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U -/*! - * @brief Enables the DMAMUX period trigger. - * - * This function enables the DMAMUX period trigger feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; -} - -/*! - * @brief Disables the DMAMUX period trigger. - * - * This function disables the DMAMUX period trigger. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; -} -#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ - -#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) -/*! - * @brief Enables the DMA channel to be always ON. - * - * This function enables the DMAMUX channel always ON feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. - */ -static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - if (enable) - { - base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; - } - else - { - base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; - } -} -#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /* _FSL_DMAMUX_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.c deleted file mode 100644 index ecc86db0833f50850d7f64abcb6ac4e10300b3b1..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.c +++ /dev/null @@ -1,1886 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define EDMA_TRANSFER_ENABLED_MASK 0x80U - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for EDMA. - * - * @param base EDMA peripheral base address. - */ -static uint32_t EDMA_GetInstance(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map EDMA instance number to base pointer. */ -static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map EDMA instance number to clock name. */ -static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Array to map EDMA instance number to IRQ number. */ -static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; - -/*! @brief Pointers to transfer handle for each EDMA channel. */ -static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t EDMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) - { - if (s_edmaBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_edmaBases)); - - return instance; -} - -void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Push tcd into hardware TCD register */ - base->TCD[channel].SADDR = tcd->SADDR; - base->TCD[channel].SOFF = tcd->SOFF; - base->TCD[channel].ATTR = tcd->ATTR; - base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; - base->TCD[channel].SLAST = tcd->SLAST; - base->TCD[channel].DADDR = tcd->DADDR; - base->TCD[channel].DOFF = tcd->DOFF; - base->TCD[channel].CITER_ELINKNO = tcd->CITER; - base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; - /* Clear DONE bit first, otherwise ESG cannot be set */ - base->TCD[channel].CSR = 0; - base->TCD[channel].CSR = tcd->CSR; - base->TCD[channel].BITER_ELINKNO = tcd->BITER; -} - -void EDMA_Init(DMA_Type *base, const edma_config_t *config) -{ - assert(config != NULL); - - uint32_t tmpreg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate EDMA periphral clock */ - CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Configure EDMA peripheral according to the configuration structure. */ - tmpreg = base->CR; - tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); - tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | - DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); - base->CR = tmpreg; -} - -void EDMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate EDMA periphral clock */ - CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void EDMA_GetDefaultConfig(edma_config_t *config) -{ - assert(config != NULL); - - config->enableRoundRobinArbitration = false; - config->enableHaltOnError = true; - config->enableContinuousLinkMode = false; - config->enableDebugMode = false; -} - -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); -} - -void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); -} - -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].NBYTES_MLOFFYES; - tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - base->TCD[channel].NBYTES_MLOFFYES = tmpreg; -} - -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); -} - -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Enable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI |= (0x1U << channel); - } - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Disable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI &= ~(0x1U << channel); - } - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdReset(edma_tcd_t *tcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; - tcd->DLAST_SGA = 0U; - /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); - tcd->BITER = 0U; -} - -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - /* source address */ - tcd->SADDR = config->srcAddr; - /* destination address */ - tcd->DADDR = config->destAddr; - /* Source data and destination data transfer size */ - tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); - /* Source address signed offset */ - tcd->SOFF = config->srcOffset; - /* Destination address signed offset */ - tcd->DOFF = config->destOffset; - /* Minor byte transfer count */ - tcd->NBYTES = config->minorLoopBytes; - /* Current major iteration count */ - tcd->CITER = config->majorLoopCounts; - /* Starting major iteration count */ - tcd->BITER = config->majorLoopCounts; - /* Enable scatter/gather processing */ - if (nextTcd != NULL) - { - tcd->DLAST_SGA = (uint32_t)nextTcd; - /* - Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, - user must call EDMA_TcdReset or EDMA_ResetChannel which will set - DREQ, so must use "|" or "&" rather than "=". - - Clear the DREQ bit because scatter gather has been enabled, so the - previous transfer is not the last transfer, and channel request should - be enabled at the next transfer(the next TCD). - */ - tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - } -} - -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->NBYTES & - ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - tcd->NBYTES = tmpreg; -} - -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (type == kEDMA_MinorLink) /* Minor link config */ - { - uint32_t tmpreg; - - /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; - /* Set likned channel */ - tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); - tcd->BITER = tmpreg; - } - else if (type == kEDMA_MajorLink) /* Major link config */ - { - uint32_t tmpreg; - - /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; - /* Set major linked channel */ - tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); - } - else /* Link none */ - { - tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; - } -} - -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t remainingCount = 0; - - if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) - { - remainingCount = 0; - } - else - { - /* Calculate the unfinished bytes */ - if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) - { - remainingCount = - (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; - } - else - { - remainingCount = - (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; - } - } - - return remainingCount; -} - -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t retval = 0; - - /* Get DONE bit flag */ - retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); - /* Get ERROR bit flag */ - retval |= (((base->ERR >> channel) & 0x1U) << 1U); - /* Get INT bit flag */ - retval |= (((base->INT >> channel) & 0x1U) << 2U); - - return retval; -} - -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Clear DONE bit flag */ - if (mask & kEDMA_DoneFlag) - { - base->CDNE = channel; - } - /* Clear ERROR bit flag */ - if (mask & kEDMA_ErrorFlag) - { - base->CERR = channel; - } - /* Clear INT bit flag */ - if (mask & kEDMA_InterruptFlag) - { - base->CINT = channel; - } -} - -static uint8_t Get_StartInstance(void) -{ - static uint8_t StartInstanceNum; - -#if defined(DMA0) - StartInstanceNum = EDMA_GetInstance(DMA0); -#elif defined(DMA1) - StartInstanceNum = EDMA_GetInstance(DMA1); -#elif defined(DMA2) - StartInstanceNum = EDMA_GetInstance(DMA2); -#elif defined(DMA3) - StartInstanceNum = EDMA_GetInstance(DMA3); -#endif - - return StartInstanceNum; -} - -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(handle != NULL); - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t edmaInstance; - uint32_t channelIndex; - uint8_t StartInstance; - edma_tcd_t *tcdRegs; - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - handle->base = base; - handle->channel = channel; - /* Get the DMA instance number */ - edmaInstance = EDMA_GetInstance(base); - StartInstance = Get_StartInstance(); - channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; - s_EDMAHandle[channelIndex] = handle; - - /* Enable NVIC interrupt */ - EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); - - /* - Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), - CSR will be 0. Because in order to suit EDMA busy check mechanism in - EDMA_SubmitTransfer, CSR must be set 0. - */ - tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; - tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; -} - -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) -{ - assert(handle != NULL); - assert(((uint32_t)tcdPool & 0x1FU) == 0); - - /* Initialize tcd queue attibute. */ - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - handle->tcdSize = tcdSize; - handle->flags = 0; - handle->tcdPool = tcdPool; -} - -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type) -{ - assert(config != NULL); - assert(srcAddr != NULL); - assert(destAddr != NULL); - assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); - assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); - assert(transferBytes % bytesEachRequest == 0); - - config->destAddr = (uint32_t)destAddr; - config->srcAddr = (uint32_t)srcAddr; - config->minorLoopBytes = bytesEachRequest; - config->majorLoopCounts = transferBytes / bytesEachRequest; - switch (srcWidth) - { - case 1U: - config->srcTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->srcTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->srcTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->srcTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->srcTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (destWidth) - { - case 1U: - config->destTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->destTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->destTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->destTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->destTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (type) - { - case kEDMA_MemoryToMemory: - config->destOffset = destWidth; - config->srcOffset = srcWidth; - break; - case kEDMA_MemoryToPeripheral: - config->destOffset = 0U; - config->srcOffset = srcWidth; - break; - case kEDMA_PeripheralToMemory: - config->destOffset = destWidth; - config->srcOffset = 0U; - break; - default: - break; - } -} - -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) -{ - assert(handle != NULL); - assert(config != NULL); - - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - if (handle->tcdPool == NULL) - { - /* - Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because - if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit - this check mechanism, EDMA_CreatHandle will clear CSR register. - */ - if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) - { - return kStatus_EDMA_Busy; - } - else - { - EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); - /* Enable auto disable request feature */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; - /* Enable major interrupt */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; - - return kStatus_Success; - } - } - else /* Use the TCD queue. */ - { - uint32_t primask; - uint32_t csr; - int8_t currentTcd; - int8_t previousTcd; - int8_t nextTcd; - - /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) - { - EnableGlobalIRQ(primask); - - return kStatus_EDMA_QueueFull; - } - currentTcd = handle->tail; - handle->tcdUsed++; - /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; - if (nextTcd == handle->tcdSize) - { - nextTcd = 0U; - } - /* Advance queue tail index */ - handle->tail = nextTcd; - EnableGlobalIRQ(primask); - /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; - /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); - /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; - /* Link current TCD with next TCD for identification of current TCD */ - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; - /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ - if (currentTcd != previousTcd) - { - /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - handle->tcdPool[previousTcd].CSR = csr; - /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It - is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to - link the TCD register in case link the current TCD with the dead chain when TCD loading occurs - before link the previous TCD block. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) - { - /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; - /* - It is very important to check the ESG bit! - Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can - be used to check if the dynamic TCD link operation is successful. If ESG bit is not set - and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and - the current TCD block has been loaded into TCD registers), it means transfer finished - and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic - link succeed. - */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) - { - return kStatus_Success; - } - /* - Check whether the current TCD block is already loaded in the TCD registers. It is another - condition when ESG bit is not set: it means the dynamic TCD link succeed and the current - TCD block has been loaded into TCD registers. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) - { - return kStatus_Success; - } - /* - If go to this, means the previous transfer finished, and the DONE bit is set. - So shall configure TCD registers. - */ - } - else if (tcdRegs->DLAST_SGA != 0) - { - /* The current TCD block has been linked successfully. */ - return kStatus_Success; - } - else - { - /* - DLAST_SGA is 0 and it means the first submit transfer, so shall configure - TCD registers. - */ - } - } - /* There is no live chain, TCD block need to be installed in TCD registers. */ - EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); - /* Enable channel request again. */ - if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - - return kStatus_Success; - } -} - -void EDMA_StartTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - if (handle->tcdPool == NULL) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - else /* Use the TCD queue. */ - { - uint32_t primask; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - handle->flags |= EDMA_TRANSFER_ENABLED_MASK; - - /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ - if (tcdRegs->DLAST_SGA != 0U) - { - primask = DisableGlobalIRQ(); - /* Check if channel request is actually disable. */ - if ((handle->base->ERQ & (1U << handle->channel)) == 0U) - { - /* Check if transfer is paused. */ - if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) - { - /* - Re-enable channel request must be as soon as possible, so must put it into - critical section to avoid task switching or interrupt service routine. - */ - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - } - EnableGlobalIRQ(primask); - } - } -} - -void EDMA_StopTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); -} - -void EDMA_AbortTransfer(edma_handle_t *handle) -{ - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); - /* - Clear CSR to release channel. Because if the given channel started transfer, - CSR will be not zero. Because if it is the last transfer, DREQ will be set. - If not, ESG will be set. - */ - handle->base->TCD[handle->channel].CSR = 0; - /* Cancel all next TCD transfer. */ - handle->base->TCD[handle->channel].DLAST_SGA = 0; - - /* Handle the tcd */ - if (handle->tcdPool != NULL) - { - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - } -} - -void EDMA_HandleIRQ(edma_handle_t *handle) -{ - assert(handle != NULL); - - /* Clear EDMA interrupt flag */ - handle->base->CINT = handle->channel; - if ((handle->tcdPool == NULL) && (handle->callback != NULL)) - { - (handle->callback)(handle, handle->userData, true, 0); - } - else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ - { - uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; - uint32_t sga_index; - int32_t tcds_done; - uint8_t new_header; - bool transfer_done; - - /* Check if transfer is already finished. */ - transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); - /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga -= (uint32_t)handle->tcdPool; - /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga_index = sga / sizeof(edma_tcd_t); - /* Adjust header positions. */ - if (transfer_done) - { - /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = sga_index; - } - else - { - /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; - } - /* Calculate the number of finished TCDs */ - if (new_header == handle->header) - { - if (handle->tcdUsed == handle->tcdSize) - { - tcds_done = handle->tcdUsed; - } - else - { - /* No TCD in the memory are going to be loaded or internal error occurs. */ - tcds_done = 0; - } - } - else - { - tcds_done = new_header - handle->header; - if (tcds_done < 0) - { - tcds_done += handle->tcdSize; - } - } - /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ - handle->header = new_header; - /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ - handle->tcdUsed -= tcds_done; - /* Invoke callback function. */ - if (handle->callback) - { - (handle->callback)(handle, handle->userData, transfer_done, tcds_done); - } - } -} - -/* 8 channels (Shared): kl28 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U - -#if defined(DMA0) -void DMA0_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} -#endif - -#if defined(DMA1) - -#if defined(DMA0) -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -#else -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} -#endif -#endif -#endif /* 8 channels (Shared) */ - -/* 16 channels (Shared): K32H844P */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U - -void DMA0_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } -} - -void DMA0_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } -} - -void DMA0_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } -} - -void DMA0_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } -} - -void DMA0_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -#if defined(DMA1) -void DMA1_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA1_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA1_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA1_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA1_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA1_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA1_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA1_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif -#endif /* 16 channels (Shared) */ - -/* 32 channels (Shared): k80 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_DMA16_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } -} - -void DMA1_DMA17_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } -} - -void DMA2_DMA18_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } -} - -void DMA3_DMA19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } -} - -void DMA4_DMA20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA5_DMA21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA6_DMA22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA7_DMA23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA8_DMA24_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } -} - -void DMA9_DMA25_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } -} - -void DMA10_DMA26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } -} - -void DMA11_DMA27_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } -} - -void DMA12_DMA28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA13_DMA29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA14_DMA30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA15_DMA31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared) */ - -/* 32 channels (Shared): MCIMX7U5_M4 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_0_4_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } -} - -void DMA0_1_5_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } -} - -void DMA0_2_6_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } -} - -void DMA0_3_7_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } -} - -void DMA0_8_12_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_9_13_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_10_14_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_11_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} - -void DMA0_16_20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } -} - -void DMA0_17_21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } -} - -void DMA0_18_22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } -} - -void DMA0_19_23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } -} - -void DMA0_24_28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } -} - -void DMA0_25_29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } -} - -void DMA0_26_30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } -} - -void DMA0_27_31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } -} -#endif /* 32 channels (Shared): MCIMX7U5 */ - -/* 4 channels (No Shared): kv10 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 - -void DMA0_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[0]); -} - -void DMA1_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[1]); -} - -void DMA2_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[2]); -} - -void DMA3_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[3]); -} - -/* 8 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U - -void DMA4_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[4]); -} - -void DMA5_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[5]); -} - -void DMA6_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[6]); -} - -void DMA7_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[7]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ - -/* 16 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U - -void DMA8_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[8]); -} - -void DMA9_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[9]); -} - -void DMA10_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[10]); -} - -void DMA11_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[11]); -} - -void DMA12_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[12]); -} - -void DMA13_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[13]); -} - -void DMA14_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[14]); -} - -void DMA15_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[15]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ - -/* 32 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U - -void DMA16_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[16]); -} - -void DMA17_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[17]); -} - -void DMA18_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[18]); -} - -void DMA19_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[19]); -} - -void DMA20_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[20]); -} - -void DMA21_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[21]); -} - -void DMA22_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[22]); -} - -void DMA23_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[23]); -} - -void DMA24_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[24]); -} - -void DMA25_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[25]); -} - -void DMA26_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[26]); -} - -void DMA27_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[27]); -} - -void DMA28_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[28]); -} - -void DMA29_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[29]); -} - -void DMA30_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[30]); -} - -void DMA31_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[31]); -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ - -#endif /* 4/8/16/32 channels (No Shared) */ - -#if defined(DMA0) -void DMA0_0_4_8_12_IRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } -} - -void DMA0_1_5_9_13_IRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } -} - -void DMA0_2_6_10_14_IRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } -} - -void DMA0_3_7_11_15_IRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } -} -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.h deleted file mode 100644 index 1ca8384b7b6c14a6c766e62c95c6849ac532bc1e..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_edma.h +++ /dev/null @@ -1,897 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_EDMA_H_ -#define _FSL_EDMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ -/*@}*/ - -/*! @brief Compute the offset unit from DCHPRI3 */ -#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) - -/*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] - -/*! @brief eDMA transfer configuration */ -typedef enum _edma_transfer_size -{ - kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ - kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ - kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ - kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ -} edma_transfer_size_t; - -/*! @brief eDMA modulo configuration */ -typedef enum _edma_modulo -{ - kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ - kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ - kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ - kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ - kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ - kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ - kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ - kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ - kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ - kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ - kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ - kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ - kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ - kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ - kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ - kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ - kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ - kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ - kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ - kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ - kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ - kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ - kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ - kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ - kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ - kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ - kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ - kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ - kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ - kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ - kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ - kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ -} edma_modulo_t; - -/*! @brief Bandwidth control */ -typedef enum _edma_bandwidth -{ - kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ - kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ - kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ -} edma_bandwidth_t; - -/*! @brief Channel link type */ -typedef enum _edma_channel_link_type -{ - kEDMA_LinkNone = 0x0U, /*!< No channel link */ - kEDMA_MinorLink, /*!< Channel link after each minor loop */ - kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ -} edma_channel_link_type_t; - -/*!@brief eDMA channel status flags. */ -enum _edma_channel_status_flags -{ - kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ - kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ - kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ -}; - -/*! @brief eDMA channel error status flags. */ -enum _edma_error_status_flags -{ - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ - kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ - kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ -#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 - kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ -#endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ -}; - -/*! @brief eDMA interrupt source */ -typedef enum _edma_interrupt_enable -{ - kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ - kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ - kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ -} edma_interrupt_enable_t; - -/*! @brief eDMA transfer type */ -typedef enum _edma_transfer_type -{ - kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ - kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ - kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ -} edma_transfer_type_t; - -/*! @brief eDMA transfer status */ -enum _edma_transfer_status -{ - kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ - kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief eDMA global configuration structure.*/ -typedef struct _edma_config -{ - bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel - activates again if that channel has a minor loop channel link enabled and - the link channel is itself. */ - bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. - Subsequently, all service requests are ignored until the HALT bit is cleared.*/ - bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority - arbitration is used for channel selection */ - bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of - a new channel. Executing channels are allowed to complete. */ -} edma_config_t; - -/*! - * @brief eDMA transfer configuration - * - * This structure configures the source/destination transfer attribute. - */ -typedef struct _edma_transfer_config -{ - uint32_t srcAddr; /*!< Source data address. */ - uint32_t destAddr; /*!< Destination data address. */ - edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ - edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ - int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to - form the next-state value as each source read is completed. */ - int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to - form the next-state value as each destination write is completed. */ - uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ - uint32_t majorLoopCounts; /*!< Major loop iteration count. */ -} edma_transfer_config_t; - -/*! @brief eDMA channel priority configuration */ -typedef struct _edma_channel_Preemption_config -{ - bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ - bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ - uint8_t channelPriority; /*!< Channel priority */ -} edma_channel_Preemption_config_t; - -/*! @brief eDMA minor offset configuration */ -typedef struct _edma_minor_offset_config -{ - bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ - bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ - uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ -} edma_minor_offset_config_t; - -/*! - * @brief eDMA TCD. - * - * This structure is same as TCD register which is described in reference manual, - * and is used to configure the scatter/gather feature as a next hardware TCD. - */ -typedef struct _edma_tcd -{ - __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ - __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ - __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ - __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ - __IO uint32_t SLAST; /*!< SLAST register */ - __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ - __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ - __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ - __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ - __IO uint16_t CSR; /*!< CSR register, for TCD control status */ - __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ -} edma_tcd_t; - -/*! @brief Callback for eDMA */ -struct _edma_handle; - -/*! @brief Define callback function for eDMA. */ -typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @brief eDMA transfer handle structure */ -typedef struct _edma_handle -{ - edma_callback callback; /*!< Callback function for major count exhausted. */ - void *userData; /*!< Callback function parameter. */ - DMA_Type *base; /*!< eDMA peripheral base address. */ - edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ - uint8_t channel; /*!< eDMA channel number. */ - volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ - volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ - volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in - the memory. */ - volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ - uint8_t flags; /*!< The status of the current channel. */ -} edma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name eDMA initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the eDMA peripheral. - * - * This function ungates the eDMA clock and configures the eDMA peripheral according - * to the configuration structure. - * - * @param base eDMA peripheral base address. - * @param config A pointer to the configuration structure, see "edma_config_t". - * @note This function enables the minor loop map feature. - */ -void EDMA_Init(DMA_Type *base, const edma_config_t *config); - -/*! - * @brief Deinitializes the eDMA peripheral. - * - * This function gates the eDMA clock. - * - * @param base eDMA peripheral base address. - */ -void EDMA_Deinit(DMA_Type *base); - -/*! - * @brief Push content of TCD structure into hardware TCD register. - * - * @param base EDMA peripheral base address. - * @param channel EDMA channel number. - * @param tcd Point to TCD structure. - */ -void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd); - -/*! - * @brief Gets the eDMA default configuration structure. - * - * This function sets the configuration structure to default values. - * The default configuration is set to the following values. - * @code - * config.enableContinuousLinkMode = false; - * config.enableHaltOnError = true; - * config.enableRoundRobinArbitration = false; - * config.enableDebugMode = false; - * @endcode - * - * @param config A pointer to the eDMA configuration structure. - */ -void EDMA_GetDefaultConfig(edma_config_t *config); - -/* @} */ -/*! - * @name eDMA Channel Operation - * @{ - */ - -/*! - * @brief Sets all TCD registers to default values. - * - * This function sets TCD registers for this channel to default values. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @note This function must not be called while the channel transfer is ongoing - * or it causes unpredictable results. - * @note This function enables the auto stop request feature. - */ -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); - -/*! - * @brief Configures the eDMA transfer attribute. - * - * This function configures the transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the TCD address. - * Example: - * @code - * edma_transfer_t config; - * edma_tcd_t tcd; - * config.srcAddr = ..; - * config.destAddr = ..; - * ... - * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); - * @endcode - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Point to TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note If nextTcd is not NULL, it means scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the eDMA_ResetChannel. - */ -void EDMA_SetTransferConfig(DMA_Type *base, - uint32_t channel, - const edma_transfer_config_t *config, - edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA minor offset feature. - * - * The minor offset means that the signed-extended value is added to the source address or destination - * address after each minor loop. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); - -/*! - * @brief Configures the eDMA channel preemption feature. - * - * This function configures the channel preemption attribute and the priority of the channel. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number - * @param config A pointer to the channel preemption configuration structure. - */ -static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, - uint32_t channel, - const edma_channel_Preemption_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - DMA_DCHPRIn(base, channel) = - (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | - DMA_DCHPRI0_CHPRI(config->channelPriority)); -} - -/*! - * @brief Sets the channel link for the eDMA transfer. - * - * This function configures either the minor link or the major link mode. The minor link means that the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param type A channel link type, which can be one of the following: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA transfer. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA transfer. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT -/*! - * @brief Enables an async request for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); -} -#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ - -/*! - * @brief Enables an auto stop request for the eDMA transfer. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of the interrupt source to be set. Use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/* @} */ -/*! - * @name eDMA TCD Operation - * @{ - */ - -/*! - * @brief Sets all fields to default values for the TCD structure. - * - * This function sets all fields for this TCD structure to default value. - * - * @param tcd Pointer to the TCD structure. - * @note This function enables the auto stop request feature. - */ -void EDMA_TcdReset(edma_tcd_t *tcd); - -/*! - * @brief Configures the eDMA TCD transfer attribute. - * - * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. - * This function configures the TCD transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the next TCD address. - * Example: - * @code - * edma_transfer_t config = { - * ... - * } - * edma_tcd_t tcd __aligned(32); - * edma_tcd_t nextTcd __aligned(32); - * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); - * @endcode - * - * @param tcd Pointer to the TCD structure. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Pointer to the next TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note TCD address should be 32 bytes aligned or it causes an eDMA error. - * @note If the nextTcd is not NULL, the scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the EDMA_TcdReset. - */ -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA TCD minor offset feature. - * - * A minor offset is a signed-extended value added to the source address or a destination - * address after each minor loop. - * - * @param tcd A point to the TCD structure. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); - -/*! - * @brief Sets the channel link for the eDMA TCD. - * - * This function configures either a minor link or a major link. The minor link means the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - * @param tcd Point to the TCD structure. - * @param type Channel link type, it can be one of: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA TCD. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * @param tcd A pointer to the TCD structure. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA TCD. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param tcd A pointer to the TCD structure. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -/*! - * @brief Sets the auto stop request for the eDMA TCD. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param tcd A pointer to the TCD structure. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Channel Transfer Operation - * @{ - */ - -/*! - * @brief Enables the eDMA hardware channel request. - * - * This function enables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SERQ = DMA_SERQ_SERQ(channel); -} - -/*! - * @brief Disables the eDMA hardware channel request. - * - * This function disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CERQ = DMA_CERQ_CERQ(channel); -} - -/*! - * @brief Starts the eDMA transfer by using the software trigger. - * - * This function starts a minor loop transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SSRT = DMA_SSRT_SSRT(channel); -} - -/*! @} */ -/*! - * @name eDMA Channel Status Operation - * @{ - */ - -/*! - * @brief Gets the remaining major loop count from the eDMA current channel TCD. - * - * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the the number of major loop count that has not finished. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return Major loop count which has not been transferred yet for the current TCD. - * @note 1. This function can only be used to get unfinished major loop count of transfer without - * the next TCD, or it might be inaccuracy. - * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while - * the channel is running. - * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO - * register is needed while the eDMA IP does not support getting it while a channel is active. - * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine - * is working with while a channel is running. - * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example - * copied before enabling the channel) is needed. The formula to calculate it is shown below: - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) - */ -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); - -/*! - * @brief Gets the eDMA channel error status flags. - * - * @param base eDMA peripheral base address. - * @return The mask of error status flags. Users need to use the -* _edma_error_status_flags type to decode the return variables. - */ -static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) -{ - return base->ES; -} - -/*! - * @brief Gets the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return The mask of channel status flags. Users need to use the - * _edma_channel_status_flags type to decode the return variables. - */ -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); - -/*! - * @brief Clears the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of channel status to be cleared. Users need to use - * the defined _edma_channel_status_flags type. - */ -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Transactional Operation - */ - -/*! - * @brief Creates the eDMA handle. - * - * This function is called if using the transactional API for eDMA. This function - * initializes the internal state of the eDMA handle. - * - * @param handle eDMA handle pointer. The eDMA handle stores callback function and - * parameters. - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs the TCDs memory pool into the eDMA handle. - * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. - * - * @param handle eDMA handle pointer. - * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. - * @param tcdSize The number of TCD slots. - */ -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); - -/*! - * @brief Installs a callback function for the eDMA transfer. - * - * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. - * - * @param handle eDMA handle pointer. - * @param callback eDMA callback function pointer. - * @param userData A parameter for the callback function. - */ -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); - -/*! - * @brief Prepares the eDMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type edma_transfer_t. - * @param srcAddr eDMA transfer source address. - * @param srcWidth eDMA transfer source address width(bytes). - * @param destAddr eDMA transfer destination address. - * @param destWidth eDMA transfer destination address width(bytes). - * @param bytesEachRequest eDMA transfer bytes per channel request. - * @param transferBytes eDMA transfer bytes to be transferred. - * @param type eDMA transfer type. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, the source address must be 4 bytes aligned, or it results in - * source address error (SAE). - */ -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type); - -/*! - * @brief Submits the eDMA transfer request. - * - * This function submits the eDMA transfer request according to the transfer configuration structure. - * If submitting the transfer request repeatedly, this function packs an unprocessed request as - * a TCD and enables scatter/gather feature to process it in the next time. - * - * @param handle eDMA handle pointer. - * @param config Pointer to eDMA transfer configuration structure. - * @retval kStatus_EDMA_Success It means submit transfer request succeed. - * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); - -/*! - * @brief eDMA starts transfer. - * - * This function enables the channel request. Users can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StartTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA stops transfer. - * - * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() - * again to resume the transfer. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StopTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA aborts transfer. - * - * This function disables the channel request and clear transfer status bits. - * Users can submit another transfer after calling this API. - * - * @param handle DMA handle pointer. - */ -void EDMA_AbortTransfer(edma_handle_t *handle); - -/*! - * @brief Get unused TCD slot number. - * - * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. - * - * @param handle DMA handle pointer. - * @return The unused tcd slot number. - */ -static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) -{ - return (handle->tcdSize - handle->tcdUsed); -} - -/*! - * @brief eDMA IRQ handler for the current major loop transfer completion. - * - * This function clears the channel major interrupt flag and calls - * the callback function if it is not NULL. - * - * Note: - * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. - * These include the final address adjustments and reloading of the BITER field into the CITER. - * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from - * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). - * - * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. - * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index - * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be - * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have - * been loaded into the eDMA engine at this point already.). - * - * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not - * load a new TCD) from the memory pool to the eDMA engine when major loop completes. - * Therefore, ensure that the header and tcdUsed updated are identical for them. - * tcdUsed are both 0 in this case as no TCD to be loaded. - * - * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for - * further details. - * - * @param handle eDMA handle pointer. - */ -void EDMA_HandleIRQ(edma_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_EDMA_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.c deleted file mode 100644 index a574b5a9072883dbddd9c0cb65359b818bc2eaf3..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ewm.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -void EWM_Init(EWM_Type *base, const ewm_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - -#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Ewm0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif - value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | - EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - base->CLKPRESCALER = config->prescaler; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - base->CLKCTRL = config->clockSource; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ - - base->CMPL = config->compareLowValue; - base->CMPH = config->compareHighValue; - base->CTRL = value; -} - -void EWM_Deinit(EWM_Type *base) -{ - EWM_DisableInterrupts(base, kEWM_InterruptEnable); -#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Ewm0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ -} - -void EWM_GetDefaultConfig(ewm_config_t *config) -{ - assert(config); - - config->enableEwm = true; - config->enableEwmInput = false; - config->setInputAssertLogic = false; - config->enableInterrupt = false; -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - config->clockSource = kEWM_LpoClockSource0; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - config->prescaler = 0U; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - config->compareLowValue = 0U; - config->compareHighValue = 0xFEU; -} - -void EWM_Refresh(EWM_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->SERV = (uint8_t)0xB4U; - base->SERV = (uint8_t)0x2CU; - EnableGlobalIRQ(primaskValue); -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.h deleted file mode 100644 index 15a9e61d25232fdacd153c54b7828009fb30fb05..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_ewm.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_EWM_H_ -#define _FSL_EWM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ewm - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief EWM driver version 2.0.1. */ -#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Describes EWM clock source. */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT -typedef enum _ewm_lpo_clock_source -{ - kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ - kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ - kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ - kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ -} ewm_lpo_clock_source_t; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ - -/*! -* @brief Data structure for EWM configuration. -* -* This structure is used to configure the EWM. -*/ -typedef struct _ewm_config -{ - bool enableEwm; /*!< Enable EWM module */ - bool enableEwmInput; /*!< Enable EWM_in input */ - bool setInputAssertLogic; /*!< EWM_in signal assertion state */ - bool enableInterrupt; /*!< Enable EWM interrupt */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - uint8_t prescaler; /*!< Clock prescaler value */ -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - uint8_t compareLowValue; /*!< Compare low-register value */ - uint8_t compareHighValue; /*!< Compare high-register value */ -} ewm_config_t; - -/*! - * @brief EWM interrupt configuration structure with default settings all disabled. - * - * This structure contains the settings for all of EWM interrupt configurations. - */ -enum _ewm_interrupt_enable_t -{ - kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ -}; - -/*! - * @brief EWM status flags. - * - * This structure contains the constants for the EWM status flags for use in the EWM functions. - */ -enum _ewm_status_flags_t -{ - kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name EWM initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the EWM peripheral. - * - * This function is used to initialize the EWM. After calling, the EWM - * runs immediately according to the configuration. - * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a - * CPU reset. Modifying them more than once generates a bus transfer error. - * - * This is an example. - * @code - * ewm_config_t config; - * EWM_GetDefaultConfig(&config); - * config.compareHighValue = 0xAAU; - * EWM_Init(ewm_base,&config); - * @endcode - * - * @param base EWM peripheral base address - * @param config The configuration of the EWM -*/ -void EWM_Init(EWM_Type *base, const ewm_config_t *config); - -/*! - * @brief Deinitializes the EWM peripheral. - * - * This function is used to shut down the EWM. - * - * @param base EWM peripheral base address -*/ -void EWM_Deinit(EWM_Type *base); - -/*! - * @brief Initializes the EWM configuration structure. - * - * This function initializes the EWM configuration structure to default values. The default - * values are as follows. - * @code - * ewmConfig->enableEwm = true; - * ewmConfig->enableEwmInput = false; - * ewmConfig->setInputAssertLogic = false; - * ewmConfig->enableInterrupt = false; - * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; - * ewmConfig->prescaler = 0; - * ewmConfig->compareLowValue = 0; - * ewmConfig->compareHighValue = 0xFEU; - * @endcode - * - * @param config Pointer to the EWM configuration structure. - * @see ewm_config_t - */ -void EWM_GetDefaultConfig(ewm_config_t *config); - -/* @} */ - -/*! - * @name EWM functional Operation - * @{ - */ - -/*! - * @brief Enables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to enable - * The parameter can be combination of the following source if defined - * @arg kEWM_InterruptEnable - */ -static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL |= mask; -} - -/*! - * @brief Disables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to disable - * The parameter can be combination of the following source if defined - * @arg kEWM_InterruptEnable - */ -static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL &= ~mask; -} - -/*! - * @brief Gets all status flags. - * - * This function gets all status flags. - * - * This is an example for getting the running flag. - * @code - * uint32_t status; - * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; - * @endcode - * @param base EWM peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t - * - True: a related status flag has been set. - * - False: a related status flag is not set. - */ -static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) -{ - return (base->CTRL & EWM_CTRL_EWMEN_MASK); -} - -/*! - * @brief Services the EWM. - * - * This function resets the EWM counter to zero. - * - * @param base EWM peripheral base address -*/ -void EWM_Refresh(EWM_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_EWM_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.c deleted file mode 100644 index 6b603cc2110a46441ed05bc040c8ab346bce8daf..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.c +++ /dev/null @@ -1,3546 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flash.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @name Misc utility defines - * @{ - */ -/*! @brief Alignment utility. */ -#ifndef ALIGN_DOWN -#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) -#endif -#ifndef ALIGN_UP -#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) -#endif - -/*! @brief Join bytes to word utility. */ -#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24) -#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16) -#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8) -#define B1P1(b) ((uint32_t)(b)&0xFFU) -#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16) -#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8) -#define B2P1(b) ((uint32_t)(b)&0xFFFFU) -#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8) -#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU) -#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y)) -#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y)) -#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y)) -#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z)) -#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z)) -#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w)) -/*@}*/ - -/*! - * @name Secondary flash configuration - * @{ - */ -/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0) -#endif - -/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1) -#else -#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0) -#endif -/*@}*/ - -/*! - * @name Dual core/flash configuration - * @{ - */ -/*! @brief Redefines some flash features. */ -#if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) -#if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u) -#define MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT -#define SECONDARY_FLASH_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT -#define SECONDARY_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT -#define SECONDARY_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT -#elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u) -#define MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT -#define SECONDARY_FLASH_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE -#define SECONDARY_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT -#define SECONDARY_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT -#define SECONDARY_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT -#endif -#else -#define MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE -#define MAIN_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT -#define MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT -#endif -/*@}*/ - -/*! - * @name Flash cache and speculation control defines - * @{ - */ -#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) -#endif -#if defined(MCM_PLACR_DFCS_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) -#endif -#if defined(MSCM_OCMDR_OCMC1_MASK) || defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR0_OCM1_MASK) || \ - defined(MSCM_OCMDR1_OCM1_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) -#endif -#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \ - defined(FMC_PFB01CR_S_B_INV_MASK) -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) -#else -#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) -#endif - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC || \ - FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_FMC -#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (1) -#else -#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (0) -#endif -/*@}*/ - -/*! @brief Data flash IFR map Field*/ -#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ -#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U -#endif - -/*! - * @name Reserved FlexNVM size (For a variety of purposes) defines - * @{ - */ -#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU -#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU -/*@}*/ - -/*! - * @name Flash Program Once Field defines - * @{ - */ -#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA -/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ - 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ - 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE -/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 -#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL -/* FTFL parts(eg. K20) only support 4-bytes unit size */ -#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 -#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 -#endif -/*@}*/ - -/*! - * @name Flash security status defines - * @{ - */ -#define FLASH_SECURITY_STATE_KEYEN 0x80U -#define FLASH_SECURITY_STATE_UNSECURED 0x02U -#define FLASH_NOT_SECURE 0x01U -#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U -#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U -/*@}*/ - -/*! - * @name Flash controller command numbers - * @{ - */ -#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ -#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ -#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ -#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ -#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ -#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ -#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ -#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ -#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ -#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ -#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ -#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ -#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ -#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ -#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ -#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ -#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ -#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ -#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ -#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ -#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ - /*@}*/ - -/*! - * @name Common flash register info defines - * @{ - */ -#if defined(FTFA) -#define FTFx FTFA -#define FTFx_BASE FTFA_BASE -#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFE) -#define FTFx FTFE -#define FTFx_BASE FTFE_BASE -#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#elif defined(FTFL) -#define FTFx FTFL -#define FTFx_BASE FTFL_BASE -#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK -#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK -#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK -#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK -#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK -#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK -#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM -#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ -#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM -#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK -#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ -#else -#error "Unknown flash controller" -#endif -/*@}*/ - -/*! - * @name Common flash register access info defines - * @{ - */ -#define FTFx_FCCOB3_REG (FTFx->FCCOB3) -#define FTFx_FCCOB5_REG (FTFx->FCCOB5) -#define FTFx_FCCOB6_REG (FTFx->FCCOB6) -#define FTFx_FCCOB7_REG (FTFx->FCCOB7) - -#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) -#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) -#define FTFx_FPROTH3_REG (FTFx->FPROTH3) -#define FTFx_FPROTH2_REG (FTFx->FPROTH2) -#define FTFx_FPROTH1_REG (FTFx->FPROTH1) -#define FTFx_FPROTH0_REG (FTFx->FPROTH0) -#endif - -#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) -#define FTFx_FPROTL3_REG (FTFx->FPROTL3) -#define FTFx_FPROTL2_REG (FTFx->FPROTL2) -#define FTFx_FPROTL1_REG (FTFx->FPROTL1) -#define FTFx_FPROTL0_REG (FTFx->FPROTL0) -#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) -#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) -#define FTFx_FPROTL3_REG (FTFx->FPROT3) -#define FTFx_FPROTL2_REG (FTFx->FPROT2) -#define FTFx_FPROTL1_REG (FTFx->FPROT1) -#define FTFx_FPROTL0_REG (FTFx->FPROT0) -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -#define FTFx_FPROTSH_REG (FTFx->FPROTSH) -#define FTFx_FPROTSL_REG (FTFx->FPROTSL) -#endif - -#define FTFx_XACCH3_REG (FTFx->XACCH3) -#define FTFx_XACCL3_REG (FTFx->XACCL3) - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER -#define FTFx_XACCSH_REG (FTFx->XACCSH) -#define FTFx_XACCSL_REG (FTFx->XACCSL) -#endif -/*@}*/ - -/*! - * @brief Enumeration for access segment property. - */ -enum _flash_access_segment_property -{ - kFLASH_AccessSegmentBase = 256UL, -}; - -/*! - * @brief Enumeration for flash config area. - */ -enum _flash_config_area_range -{ - kFLASH_ConfigAreaStart = 0x400U, - kFLASH_ConfigAreaEnd = 0x40FU -}; - -/*! - * @name Flash register access type defines - * @{ - */ -#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * -#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * -/*@}*/ - -/*! - * @brief MCM cache register access info defines. - */ -#if defined(MCM_PLACR_CFCC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT -#if defined(MCM0) -#define MCM0_CACHE_REG MCM0->PLACR -#elif defined(MCM) && (!defined(MCM1)) -#define MCM0_CACHE_REG MCM->PLACR -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->PLACR -#elif defined(MCM) && (!defined(MCM0)) -#define MCM1_CACHE_REG MCM->PLACR -#endif -#elif defined(MCM_CPCR2_CCBC_MASK) -#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK -#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT -#if defined(MCM0) -#define MCM0_CACHE_REG MCM0->CPCR2 -#elif defined(MCM) && (!defined(MCM1)) -#define MCM0_CACHE_REG MCM->CPCR2 -#endif -#if defined(MCM1) -#define MCM1_CACHE_REG MCM1->CPCR2 -#elif defined(MCM) && (!defined(MCM0)) -#define MCM1_CACHE_REG MCM->CPCR2 -#endif -#endif - -/*! - * @brief Enumeration for ARM core part number. - */ -enum _arm_core_part_number -{ - kARM_CorePartNumber_CM0 = 0xc20U, - kARM_CorePartNumber_CM0P = 0xc60U, - kARM_CorePartNumber_CM1 = 0xc21U, - kARM_CorePartNumber_CM3 = 0xc23U, - kARM_CorePartNumber_CM4 = 0xc24U, - kARM_CorePartNumber_CM7 = 0xc27U, - kARM_CorePartNumber_CM23 = 0xd20U, - kARM_CorePartNumber_CM33 = 0xd21U, - - kARM_CorePartNumber_Invalid = 0xFFFFU, -}; - -#if defined(BL_TARGET_ROM) && defined(MCM0_CACHE_REG) && defined(MCM1_CACHE_REG) && \ - defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) -FTFx_REG32_ACCESS_TYPE const s_mcmModuleAccessTypeArray[] = { - (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG, - (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG -}; - -static const uint16_t s_armCorePartNumberArray[] = { - kARM_CorePartNumber_CM0P, - kARM_CorePartNumber_CM1, - kARM_CorePartNumber_Invalid, - kARM_CorePartNumber_CM3, - kARM_CorePartNumber_CM4, - kARM_CorePartNumber_Invalid, - kARM_CorePartNumber_Invalid, - kARM_CorePartNumber_CM7 -}; -#endif - -/*! - * @brief MSCM cache register access info defines. - */ -#if defined(MSCM_OCMDR_OCM1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x) -#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR0_OCM1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR0_OCM1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR0_OCM1(x) -#elif defined(MSCM_OCMDR_OCMC1_MASK) -#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK -#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT -#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x) -#endif - -#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) -#define MSCM_OCMDR0_REG MSCM->OCMDR[0] -#define MSCM_OCMDR1_REG MSCM->OCMDR[1] -#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) -#define MSCM_OCMDR0_REG MSCM->OCMDR0 -#define MSCM_OCMDR1_REG MSCM->OCMDR1 -#endif - -/*! - * @brief MSCM prefetch speculation defines. - */ -#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) -#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) - -#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) -#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Copy flash_run_command() to RAM*/ -static void copy_flash_run_command(uint32_t *flashRunCommand); -#if FLASH_IS_CACHE_INVALIDATION_AVAILABLE -/*! @brief Copy flash_cache_clear_command() to RAM*/ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation); -#endif -/*! @brief Check whether flash execute-in-ram functions are ready*/ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ -static status_t flash_command_sequence(flash_config_t *config); - -/*! @brief Perform the cache clear to the flash*/ -void flash_cache_clear(flash_config_t *config); - -/*! @brief Process the cache to the flash*/ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process); - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline); -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info); -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info); - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info); -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(void); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void); -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(uint32_t flashIndex, bool enable); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void); -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Access to FTFx->FCCOB */ -volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; -/*! @brief Access to FTFx->FPROT */ -volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; -#if defined(FTFx_FPROT_HIGH_REG) -volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER -volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; -volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief A function pointer used to point to relocated flash_run_command() */ -static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); - -/*! - * @brief Position independent code of flash_run_command() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) - * { - * // clear CCIF bit - * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; - * - * // Check CCIF bit of the flash status register, wait till it is set. - * // IP team indicates that this loop will always complete. - * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) - * { - * } - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -#if defined(__riscv) -/* Build with zero riscy core configuration. */ -static const uint16_t s_flashRunCommandFunctionCode[] = { - 0x0793, 0xf800, /* li a5,-128 */ - 0x0023, 0x00f5, /* sb a5,0(a0) */ - 0x4783, 0x0005, /* lbu a5,0(a0) */ - 0x07e2, /* slli a5,a5,0x18 */ - 0x87e1, /* srai a5,a5,0x18 */ - 0xdce3, 0xfe07, /* bgez a5, */ - 0x8082 /* ret */ -}; -#else -static const uint16_t s_flashRunCommandFunctionCode[] = { - 0x2180, /* MOVS R1, #128 ; 0x80 */ - 0x7001, /* STRB R1, [R0] */ - /* @4: */ - 0x7802, /* LDRB R2, [R0] */ - 0x420a, /* TST R2, R1 */ - 0xd0fc, /* BEQ.N @4 */ - 0x4770 /* BX LR */ -}; -#endif - -#if FLASH_IS_CACHE_INVALIDATION_AVAILABLE -/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */ -static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base, - uint32_t bitMask, - uint32_t bitShift, - uint32_t bitValue); - -/*! - * @brief Position independent code of flash_common_bit_operation() - * - * Note1: The prototype of C function is shown as below: - * @code - * void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t - * bitValue) - * { - * if (bitMask) - * { - * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); - * *base = (*base & (~bitMask)) | value; - * } - * - * __ISB(); - * __DSB(); - * } - * @endcode - * Note2: The binary code is generated by IAR 7.70.1 - */ -#if defined(__riscv) -/* Build with zero riscy core configuration. */ -static const uint16_t s_flashCommonBitOperationFunctionCode[] = { - 0xc981, /* beqz a1, */ - 0x411c, /* lw a5,0(a0) */ - 0x96b3, 0x00c6, /* sll a3,a3,a2 */ - 0x8ebd, /* xor a3,a3,a5 */ - 0x8df5, /* and a1,a1,a3 */ - 0x8dbd, /* xor a1,a1,a5 */ - 0xc10c, /* sw a1,0(a0) */ - 0x0001, /* nop */ - 0x0001, /* nop */ - 0x8082, /* ret */ -}; -#else -static const uint16_t s_flashCommonBitOperationFunctionCode[] = { - 0xb510, /* PUSH {R4, LR} */ - 0x2900, /* CMP R1, #0 */ - 0xd005, /* BEQ.N @12 */ - 0x6804, /* LDR R4, [R0] */ - 0x438c, /* BICS R4, R4, R1 */ - 0x4093, /* LSLS R3, R3, R2 */ - 0x4019, /* ANDS R1, R1, R3 */ - 0x4321, /* ORRS R1, R1, R4 */ - 0x6001, /* STR R1, [R0] */ - /* @12: */ - 0xf3bf, 0x8f6f, /* ISB */ - 0xf3bf, 0x8f4f, /* DSB */ - 0xbd10 /* POP {R4, PC} */ -}; -#endif -#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE */ -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -/*! @brief A static buffer used to hold flash_run_command() */ -static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -#if FLASH_IS_CACHE_INVALIDATION_AVAILABLE -/*! @brief A static buffer used to hold flash_common_bit_operation() */ -static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; -#endif -/*! @brief Flash execute-in-ram function information */ -static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; -#endif - -/*! - * @brief Table of pflash sizes. - * - * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. - * - * The values in this table have been right shifted 10 bits so that they will all fit within - * an 16-bit integer. To get the actual flash density, you must left shift the looked up value - * by 10 bits. - * - * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is - * reserved. - * - * Code to use the table: - * @code - * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; - * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - * @endcode - */ -#if defined(FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION) && (FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION == 1) -const uint16_t kPFlashDensities[] = { - 0, /* 0x0 - undefined */ - 0, /* 0x1 - undefined */ - 0, /* 0x2 - undefined */ - 0, /* 0x3 - undefined */ - 0, /* 0x4 - undefined */ - 0, /* 0x5 - undefined */ - 0, /* 0x6 - undefined */ - 0, /* 0x7 - undefined */ - 0, /* 0x8 - undefined */ - 0, /* 0x9 - undefined */ - 256, /* 0xa - 262144, 256KB */ - 0, /* 0xb - undefined */ - 1024, /* 0xc - 1048576, 1MB */ - 0, /* 0xd - undefined */ - 0, /* 0xe - undefined */ - 0, /* 0xf - undefined */ -}; -#else -const uint16_t kPFlashDensities[] = { - 8, /* 0x0 - 8192, 8KB */ - 16, /* 0x1 - 16384, 16KB */ - 24, /* 0x2 - 24576, 24KB */ - 32, /* 0x3 - 32768, 32KB */ - 48, /* 0x4 - 49152, 48KB */ - 64, /* 0x5 - 65536, 64KB */ - 96, /* 0x6 - 98304, 96KB */ - 128, /* 0x7 - 131072, 128KB */ - 192, /* 0x8 - 196608, 192KB */ - 256, /* 0x9 - 262144, 256KB */ - 384, /* 0xa - 393216, 384KB */ - 512, /* 0xb - 524288, 512KB */ - 768, /* 0xc - 786432, 768KB */ - 1024, /* 0xd - 1048576, 1MB */ - 1536, /* 0xe - 1572864, 1.5MB */ - /* 2048, 0xf - 2097152, 2MB */ -}; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t FLASH_Init(flash_config_t *config) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) - uint32_t flashDensity; - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT; - if (pfsize == 0xf) - { - flashDensity = SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_COUNT * SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - config->PFlashTotalSize = flashDensity; -#else - /* Unused code to solve MISRA-C issue*/ - config->PFlashBlockBase = kPFlashDensities[0]; - config->PFlashTotalSize = SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_COUNT * SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SIZE; -#endif - config->PFlashBlockBase = SECONDARY_FLASH_FEATURE_PFLASH_START_ADDRESS; - config->PFlashBlockCount = SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_COUNT; - config->PFlashSectorSize = SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - uint32_t flashDensity; - -/* calculate the flash density from SIM_FCFG1.PFSIZE */ -#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT; -#elif defined(SIM_FCFG1_PFSIZE_MASK) - uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; -#else -#error "Unknown flash size" -#endif - /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. - * We just use the pre-defined flash size in feature file here to support pre-production parts */ - if (pfsize == 0xf) - { - flashDensity = MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT * MAIN_FLASH_FEATURE_PFLASH_BLOCK_SIZE; - } - else - { - flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; - } - - /* fill out a few of the structure members */ - config->PFlashBlockBase = MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS; - config->PFlashTotalSize = flashDensity; - config->PFlashBlockCount = MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT; - config->PFlashSectorSize = MAIN_FLASH_FEATURE_PFLASH_BLOCK_SECTOR_SIZE; - } - - { -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS; - config->PFlashAccessSegmentCount = FTFx->FACSNS; - } - else -#endif - { - config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS; - config->PFlashAccessSegmentCount = FTFx->FACSN; - } -#else - config->PFlashAccessSegmentSize = 0; - config->PFlashAccessSegmentCount = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - } - -/* copy required flash commands to RAM */ -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) - if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) - { - s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; - s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; -#if FLASH_IS_CACHE_INVALIDATION_AVAILABLE - s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation; -#endif - config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; - FLASH_PrepareExecuteInRamFunctions(config); - } -#endif - - config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; - config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - { - status_t returnCode; - config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; - returnCode = flash_update_flexnvm_memory_partition_status(config); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - } -#endif - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if ((config == NULL) || (config->flashExecuteInRamFunctionInfo == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); -#if FLASH_IS_CACHE_INVALIDATION_AVAILABLE - copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation); -#endif - flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all flash blocks */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} - -status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) -{ - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; - uint32_t endAddress; /* storing end address */ - uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - - /* calculating Flash end address */ - endAddress = start + lengthInBytes - 1; - - /* re-calculate the endAddress and align it to the start of the next sector - * which will be used in the comparison below */ - if (endAddress % sectorSize) - { - numberOfSectors = endAddress / sectorSize + 1; - endAddress = numberOfSectors * sectorSize - 1; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* the start address will increment to the next sector address - * until it reaches the endAdddress */ - while (start <= endAddress) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* Increment to the next sector */ - start += sectorSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD -status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Prepare passing parameter to erase all flash blocks (unsecure). */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be erased by erase all unsecure command, so we need to - * update FlexNVM memory partition status synchronously */ - if (returnCode == kStatus_FLASH_Success) - { - returnCode = flash_update_flexnvm_memory_partition_status(config); - } -#endif - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ - -status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to erase all execute-only segments - * 1st element for the FCCOB register */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); - - /* Validate the user key */ - returnCode = flash_check_user_key(key); - if (returnCode) - { - return returnCode; - } - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* preparing passing parameter to program the flash block */ - kFCCOBx[1] = *src++; - if (4 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); - } - else if (8 == flashOperationInfo.blockWriteUnitSize) - { - kFCCOBx[2] = *src++; - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - break; - } - else - { - /* update start address for next iteration */ - start += flashOperationInfo.blockWriteUnitSize; - - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.blockWriteUnitSize; - } - } - - flash_cache_clear(config); - - return (returnCode); -} - -status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (src == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); - - kFCCOBx[1] = *src; - -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - kFCCOBx[2] = *(src + 1); - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - - return returnCode; -} - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD -status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - uint32_t sectorSize; - flash_operation_config_t flashOperationInfo; -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - bool needSwitchFlexRamMode = false; -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - if (src == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - sectorSize = flashOperationInfo.activeSectorSize; - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsRamError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - while (lengthInBytes > 0) - { - /* Make sure the write operation doesn't span two sectors */ - uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); - uint32_t lengthTobeProgrammedOfCurrentSector; - uint32_t currentOffset = 0; - - if (endAddressOfCurrentSector == start) - { - endAddressOfCurrentSector += sectorSize; - } - - if (lengthInBytes + start > endAddressOfCurrentSector) - { - lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; - } - else - { - lengthTobeProgrammedOfCurrentSector = lengthInBytes; - } - - /* Program Current Sector */ - while (lengthTobeProgrammedOfCurrentSector > 0) - { - /* Make sure the program size doesn't exceeds Acceleration RAM size */ - uint32_t programSizeOfCurrentPass; - uint32_t numberOfPhases; - - if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize) - { - programSizeOfCurrentPass = kFLASH_AccelerationRamSize; - } - else - { - programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; - } - - /* Copy data to FlexRAM */ - memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); - /* Set start address of the data to be programmed */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); - /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ - numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment; - - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); - - /* Peform command sequence */ - returnCode = flash_command_sequence(config); - - if (returnCode != kStatus_FLASH_Success) - { - flash_cache_clear(config); - return returnCode; - } - - lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; - currentOffset += programSizeOfCurrentPass; - } - - src += currentOffset / 4; - start += currentOffset; - lengthInBytes -= currentOffset; - } - - flash_cache_clear(config); - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD - /* Restore function of FlexRAM if needed. */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsEepromError; - } - } -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -{ - status_t returnCode; - bool needSwitchFlexRamMode = false; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Validates the range of the given address */ - if ((start < config->FlexRAMBlockBase) || - ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) - { - return kStatus_FLASH_AddressError; - } - - returnCode = kStatus_FLASH_Success; - - /* Switch function of FlexRAM if needed */ - if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - needSwitchFlexRamMode = true; - - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_SetFlexramAsEepromError; - } - } - - /* Write data to FlexRAM when it is used as EEPROM emulator */ - while (lengthInBytes > 0) - { - if ((!(start & 0x3U)) && (lengthInBytes >= 4)) - { - *(uint32_t *)start = *(uint32_t *)src; - start += 4; - src += 4; - lengthInBytes -= 4; - } - else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) - { - *(uint16_t *)start = *(uint16_t *)src; - start += 2; - src += 2; - lengthInBytes -= 2; - } - else - { - *(uint8_t *)start = *src; - start += 1; - src += 1; - lengthInBytes -= 1; - } - /* Wait till EEERDY bit is set */ - while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) - { - } - - /* Check for protection violation error */ - if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - } - - /* Switch function of FlexRAM if needed */ - if (needSwitchFlexRamMode) - { - returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_RecoverFlexramAsRamError; - } - } - - return returnCode; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -status_t FLASH_ReadResource( - flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - /* Check the supplied address range. */ - returnCode = - flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - while (lengthInBytes > 0) - { - /* preparing passing parameter */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); - if (flashOperationInfo.resourceCmdAddressAligment == 4) - { - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - } - else - { - } - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success != returnCode) - { - break; - } - - /* fetch data */ - *dst++ = kFCCOBx[1]; - if (flashOperationInfo.resourceCmdAddressAligment == 8) - { - *dst++ = kFCCOBx[2]; - } - /* update start address for next iteration */ - start += flashOperationInfo.resourceCmdAddressAligment; - /* update lengthInBytes for next iteration */ - lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment; - } - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) -{ - status_t returnCode; - - if ((config == NULL) || (dst == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* pass paramters to FTFx */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - if (kStatus_FLASH_Success == returnCode) - { - *dst = kFCCOBx[1]; -/* Note: Have to seperate the first index from the rest if it equals 0 - * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT - if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || - /* Range check */ - ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && - (lengthInBytes == 8)) -#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ - { - *(dst + 1) = kFCCOBx[2]; - } -#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ - } - - return returnCode; -} - -status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) -{ - /* store data read from flash register */ - uint8_t registerValue; - - if ((config == NULL) || (state == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* check the status of the flash security bits in the security register */ - if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) - { - /* Flash in unsecured state */ - *state = kFLASH_SecurityStateNotSecure; - } - else - { - /* Flash in secured state - * check for backdoor key security enable bit */ - if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) - { - /* Backdoor key security enabled */ - *state = kFLASH_SecurityStateBackdoorEnabled; - } - else - { - /* Backdoor key security disabled */ - *state = kFLASH_SecurityStateBackdoorDisabled; - } - } - - return (kStatus_FLASH_Success); -} - -status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) -{ - uint8_t registerValue; /* registerValue */ - status_t returnCode; /* return code variable */ - - if ((config == NULL) || (backdoorKey == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* set the default return code as kStatus_Success */ - returnCode = kStatus_FLASH_Success; - - /* Get flash security register value */ - registerValue = FTFx->FSEC; - - /* Check to see if flash is in secure state (any state other than 0x2) - * If not, then skip this since flash is not secure */ - if (0x02 != (registerValue & 0x03)) - { - /* preparing passing parameter to erase a flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); - kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) -{ - /* Check arguments. */ - uint32_t blockSize; - flash_operation_config_t flashOperationInfo; - uint32_t nextBlockStartAddress; - uint32_t remainingBytes; - status_t returnCode; - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - start = flashOperationInfo.convertedAddress; - blockSize = flashOperationInfo.activeBlockSize; - - nextBlockStartAddress = ALIGN_UP(start, blockSize); - if (nextBlockStartAddress == start) - { - nextBlockStartAddress += blockSize; - } - - remainingBytes = lengthInBytes; - - while (remainingBytes) - { - uint32_t numberOfPhrases; - uint32_t verifyLength = nextBlockStartAddress - start; - if (verifyLength > remainingBytes) - { - verifyLength = remainingBytes; - } - - numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment; - - /* Fill in verify section command parameters. */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - if (returnCode) - { - return returnCode; - } - - remainingBytes -= verifyLength; - start += verifyLength; - nextBlockStartAddress += blockSize; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_VerifyProgram(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint32_t *expectedData, - flash_margin_value_t margin, - uint32_t *failedAddress, - uint32_t *failedData) -{ - status_t returnCode; - flash_operation_config_t flashOperationInfo; - - if (expectedData == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flash_get_matched_operation_info(config, start, &flashOperationInfo); - - returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment); - if (returnCode) - { - return returnCode; - } - - start = flashOperationInfo.convertedAddress; - - while (lengthInBytes) - { - /* preparing passing parameter to program check the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); - kFCCOBx[2] = *expectedData; - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - /* checking for the success of command execution */ - if (kStatus_FLASH_Success != returnCode) - { - if (failedAddress) - { - *failedAddress = start; - } - if (failedData) - { - *failedData = 0; - } - break; - } - - lengthInBytes -= flashOperationInfo.checkCmdAddressAligment; - expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData); - start += flashOperationInfo.checkCmdAddressAligment; - } - - return (returnCode); -} - -status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* preparing passing parameter to verify erase all execute-only segments command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} - -status_t FLASH_IsProtected(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_protection_state_t *protection_state) -{ - uint32_t endAddress; /* end address for protection check */ - uint32_t regionCheckedCounter; /* increments each time the flash address was checked for - * protection status */ - uint32_t regionCounter; /* incrementing variable used to increment through the flash - * protection regions */ - uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ - - uint8_t flashRegionProtectStatus[MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection - * status for each - * protection region */ - uint32_t flashRegionAddress[MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT + - 1]; /* array of the start addresses for each flash - * protection region. Note this is REGION_COUNT+1 - * due to requiring the next start address after - * the end of flash for loop-check purposes below */ - flash_protection_config_t flashProtectionInfo; /* flash protection information */ - status_t returnCode; - - if (protection_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - - /* Get necessary flash protection information. */ - returnCode = flash_get_protection_info(config, &flashProtectionInfo); - if (returnCode) - { - return returnCode; - } - - /* calculating Flash end address */ - endAddress = start + lengthInBytes; - - /* populate the flashRegionAddress array with the start address of each flash region */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - - /* populate up to 33rd element of array, this is the next address after end of flash array */ - while (regionCounter <= flashProtectionInfo.regionCount) - { - flashRegionAddress[regionCounter] = - flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter; - regionCounter++; - } - - /* populate flashRegionProtectStatus array with status information - * Protection status for each region is stored in the FPROT[3:0] registers - * Each bit represents one region of flash - * 4 registers * 8-bits-per-register = 32-bits (32-regions) - * The convention is: - * FPROT3[bit 0] is the first protection region (start of flash memory) - * FPROT0[bit 7] is the last protection region (end of flash memory) - * regionCounter is used to determine which FPROT[3:0] register to check for protection status - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - while (regionCounter < flashProtectionInfo.regionCount) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); - } - else - { - break; - } - } - else -#endif - { - /* Note: So far protection region count may be 16/20/24/32/64 */ - if (regionCounter < 8) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); - } - else if ((regionCounter >= 8) && (regionCounter < 16)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); - } -#if defined(MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT) && (MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT > 16) -#if (MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT == 20) - else if ((regionCounter >= 16) && (regionCounter < 20)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#else - else if ((regionCounter >= 16) && (regionCounter < 24)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); - } -#endif /* (MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT == 20) */ -#endif -#if defined(MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT) && (MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT > 24) - else if ((regionCounter >= 24) && (regionCounter < 32)) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); - } -#endif -#if defined(MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT) && \ - (MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT == 64) - else if (regionCounter < 40) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); - } - else if (regionCounter < 48) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); - } - else if (regionCounter < 56) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); - } - else if (regionCounter < 64) - { - flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); - } -#endif - else - { - break; - } - } - - regionCounter++; - } - - /* loop through the flash regions and check - * desired flash address range for protection status - * loop stops when it is detected that start has exceeded the endAddress */ - regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ - regionCheckedCounter = 0; - protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ - while (start < endAddress) - { - /* check to see if the address falls within this protection region - * Note that if the entire flash is to be checked, the last protection - * region checked would consist of the last protection start address and - * the start address following the end of flash */ - if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) - { - /* increment regionCheckedCounter to indicate this region was checked */ - regionCheckedCounter++; - - /* check the protection status of this region - * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ - if (!flashRegionProtectStatus[regionCounter]) - { - /* increment protectStatusCounter to indicate this region is protected */ - protectStatusCounter++; - } - start += flashProtectionInfo.regionSize; /* increment to an address within the next region */ - } - regionCounter++; /* increment regionCounter to check for the next flash protection region */ - } - - /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ - if (protectStatusCounter == 0) - { - *protection_state = kFLASH_ProtectionStateUnprotected; - } - /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ - else if (protectStatusCounter == regionCheckedCounter) - { - *protection_state = kFLASH_ProtectionStateProtected; - } - /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed - * In other words, some regions are protected while others are unprotected */ - else - { - *protection_state = kFLASH_ProtectionStateMixed; - } - - return (returnCode); -} - -status_t FLASH_IsExecuteOnly(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - flash_execute_only_access_state_t *access_state) -{ -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - flash_access_config_t flashAccessInfo; /* flash Execute-Only information */ -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - status_t returnCode; - - if (access_state == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Check the supplied address range. */ - returnCode = flash_check_range(config, start, lengthInBytes, MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE); - if (returnCode) - { - return returnCode; - } - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL - /* Get necessary flash Execute-Only information. */ - returnCode = flash_get_access_info(config, &flashAccessInfo); - if (returnCode) - { - return returnCode; - } - - { - uint32_t executeOnlySegmentCounter = 0; - - /* calculating end address */ - uint32_t endAddress = start + lengthInBytes; - - /* Aligning start address and end address */ - uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize); - uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize); - - uint32_t segmentIndex = 0; - uint32_t maxSupportedExecuteOnlySegmentCount = - (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize; - - while (start < endAddress) - { - uint32_t xacc; - bool isInvalidSegmentIndex = false; - - segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize; - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. - */ - if (segmentIndex < 8) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; - segmentIndex -= 8; - } - else - { - isInvalidSegmentIndex = true; - } - } - else -#endif - { - /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. - */ - if (segmentIndex < 32) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; - } - else if (segmentIndex < flashAccessInfo.SegmentCount) - { - xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; - segmentIndex -= 32; - } - else - { - isInvalidSegmentIndex = true; - } - } - - if (isInvalidSegmentIndex) - { - break; - } - - /* Determine if this address range is in a execute-only protection flash segment. */ - if ((~xacc) & (1u << segmentIndex)) - { - executeOnlySegmentCounter++; - } - - start += flashAccessInfo.SegmentSize; - } - - if (executeOnlySegmentCounter < 1u) - { - *access_state = kFLASH_AccessStateUnLimited; - } - else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) - { - *access_state = kFLASH_AccessStateMixed; - } - else - { - *access_state = kFLASH_AccessStateExecuteOnly; - } - } -#else - *access_state = kFLASH_AccessStateUnLimited; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - - return (returnCode); -} - -status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -{ - if ((config == NULL) || (value == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { - case kFLASH_PropertyPflashSectorSize: - *value = config->PFlashSectorSize; - break; - - case kFLASH_PropertyPflashTotalSize: - *value = config->PFlashTotalSize; - break; - - case kFLASH_PropertyPflashBlockSize: - *value = config->PFlashTotalSize / (uint32_t)config->PFlashBlockCount; - break; - - case kFLASH_PropertyPflashBlockCount: - *value = (uint32_t)config->PFlashBlockCount; - break; - - case kFLASH_PropertyPflashBlockBaseAddr: - *value = config->PFlashBlockBase; - break; - - case kFLASH_PropertyPflashFacSupport: -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) - *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; -#else - *value = 0; -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ - break; - - case kFLASH_PropertyPflashAccessSegmentSize: - *value = config->PFlashAccessSegmentSize; - break; - - case kFLASH_PropertyPflashAccessSegmentCount: - *value = config->PFlashAccessSegmentCount; - break; - - case kFLASH_PropertyFlexRamBlockBaseAddr: - *value = config->FlexRAMBlockBase; - break; - - case kFLASH_PropertyFlexRamTotalSize: - *value = config->FlexRAMTotalSize; - break; - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - break; - case kFLASH_PropertyDflashTotalSize: - *value = config->DFlashTotalSize; - break; - case kFLASH_PropertyDflashBlockSize: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; - break; - case kFLASH_PropertyDflashBlockCount: - *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - break; - case kFLASH_PropertyDflashBlockBaseAddr: - *value = config->DFlashBlockBase; - break; - case kFLASH_PropertyEepromTotalSize: - *value = config->EEpromTotalSize; - break; -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - - default: /* catch inputs that are not recognized */ - return kStatus_FLASH_UnknownProperty; - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value) -{ - status_t status = kStatus_FLASH_Success; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - switch (whichProperty) - { -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - case kFLASH_PropertyFlashMemoryIndex: - if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) && - (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash)) - { - return kStatus_FLASH_InvalidPropertyValue; - } - config->FlashMemoryIndex = (uint8_t)value; - break; -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - - case kFLASH_PropertyPflashSectorSize: - case kFLASH_PropertyPflashTotalSize: - case kFLASH_PropertyPflashBlockSize: - case kFLASH_PropertyPflashBlockCount: - case kFLASH_PropertyPflashBlockBaseAddr: - case kFLASH_PropertyPflashFacSupport: - case kFLASH_PropertyPflashAccessSegmentSize: - case kFLASH_PropertyPflashAccessSegmentCount: - case kFLASH_PropertyFlexRamBlockBaseAddr: - case kFLASH_PropertyFlexRamTotalSize: -#if FLASH_SSD_IS_FLEXNVM_ENABLED - case kFLASH_PropertyDflashSectorSize: - case kFLASH_PropertyDflashTotalSize: - case kFLASH_PropertyDflashBlockSize: - case kFLASH_PropertyDflashBlockCount: - case kFLASH_PropertyDflashBlockBaseAddr: - case kFLASH_PropertyEepromTotalSize: -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - status = kStatus_FLASH_ReadOnlyProperty; - break; - default: /* catch inputs that are not recognized */ - status = kStatus_FLASH_UnknownProperty; - break; - } - - return status; -} - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) -{ - status_t status; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - status = flasn_check_flexram_function_option_range(option); - if (status != kStatus_FLASH_Success) - { - return status; - } - - /* preparing passing parameter to verify all block command */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); - - /* calling flash command sequence function to execute the command */ - return flash_command_sequence(config); -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -status_t FLASH_SwapControl(flash_config_t *config, - uint32_t address, - flash_swap_control_option_t option, - flash_swap_state_config_t *returnInfo) -{ - status_t returnCode; - - if ((config == NULL) || (returnInfo == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) - { - return kStatus_FLASH_AlignmentError; - } - - /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ - if ((address >= (config->PFlashTotalSize / 2)) || - ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd))) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - /* Check the option. */ - returnCode = flash_check_swap_control_option(option); - if (returnCode) - { - return returnCode; - } - - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); - - returnCode = flash_command_sequence(config); - - returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG; - returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG; - returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG; - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) -{ - flash_swap_state_config_t returnInfo; - status_t returnCode; - - memset(&returnInfo, 0xFFU, sizeof(returnInfo)); - - do - { - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - - if (kFLASH_SwapFunctionOptionDisable == option) - { - if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled) - { - return kStatus_FLASH_Success; - } - else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized) - { - /* The swap system changed to the DISABLED state with Program flash block 0 - * located at relative flash address 0x0_0000 */ - returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo); - } - else - { - /* Swap disable should be requested only when swap system is in the uninitialized state */ - return kStatus_FLASH_SwapSystemNotInUninitialized; - } - } - else - { - /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, - * the swap procedure should be Uninitialized -> Update-Erased -> Complete. - * After the first swap has been completed, the flash swap inidicator address cannot be modified - * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> - * Complete. */ - switch (returnInfo.flashSwapState) - { - case kFLASH_SwapStateUninitialized: - /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo); - break; - case kFLASH_SwapStateReady: - /* Validate whether the address provided to the swap system is matched to - * swap indicator address in the IFR */ - returnCode = flash_validate_swap_indicator_address(config, address); - if (returnCode == kStatus_FLASH_Success) - { - /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo); - } - break; - case kFLASH_SwapStateUpdate: - /* If current swap mode is Update, Erase indicator sector in non active block - * to proceed swap system to update-erased state */ - returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), - FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey); - break; - case kFLASH_SwapStateUpdateErased: - /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ - returnCode = - FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo); - break; - case kFLASH_SwapStateComplete: - break; - case kFLASH_SwapStateDisabled: - /* When swap system is in disabled state, We need to clear swap system back to uninitialized - * by issuing EraseAllBlocks command */ - returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; - break; - default: - returnCode = kStatus_FLASH_InvalidArgument; - break; - } - } - if (returnCode != kStatus_FLASH_Success) - { - break; - } - } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option))); - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD -status_t FLASH_ProgramPartition(flash_config_t *config, - flash_partition_flexram_load_option_t option, - uint32_t eepromDataSizeCode, - uint32_t flexnvmPartitionCode) -{ - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 - * or it will cause access error. */ - /* eepromDataSizeCode &= 0x3FU; */ - /* flexnvmPartitionCode &= 0x0FU; */ - - /* preparing passing parameter to program the flash block */ - kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); - kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); - - flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); - - /* calling flash command sequence function to execute the command */ - returnCode = flash_command_sequence(config); - - flash_cache_clear(config); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - /* Data flash IFR will be updated by program partition command during reset sequence, - * so we just set reserved values for partitioned FlexNVM size here */ - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif - - return (returnCode); -} -#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ - -status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl; - if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL) - { - return kStatus_FLASH_CommandFailure; - } - - *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh; - if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH) - { - return kStatus_FLASH_CommandFailure; - } - } - else -#endif - { - *kFPROTL = protectStatus->valueLow32b.protl32b; - if (protectStatus->valueLow32b.protl32b != *kFPROTL) - { - return kStatus_FLASH_CommandFailure; - } - -#if defined(FTFx_FPROT_HIGH_REG) - *kFPROTH = protectStatus->valueHigh32b.proth32b; - if (protectStatus->valueHigh32b.proth32b != *kFPROTH) - { - return kStatus_FLASH_CommandFailure; - } -#endif - } - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL; - protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH; - } - else -#endif - { - protectStatus->valueLow32b.protl32b = *kFPROTL; -#if defined(FTFx_FPROT_HIGH_REG) - protectStatus->valueHigh32b.proth32b = *kFPROTH; -#endif - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FDPROT = protectStatus; - - if (FTFx->FDPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FDPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - FTFx->FEPROT = protectStatus; - - if (FTFx->FEPROT != protectStatus) - { - return kStatus_FLASH_CommandFailure; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) -{ - if ((config == NULL) || (protectStatus == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) - { - return kStatus_FLASH_CommandNotSupported; - } - - *protectStatus = FTFx->FEPROT; - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - FTFx_REG32_ACCESS_TYPE regBase; -#if defined(MCM) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; -#elif defined(MCM0) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { - *regBase |= MCM_PLACR_DFCS_MASK; - } - } - else - { - *regBase &= ~MCM_PLACR_DFCS_MASK; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= MCM_PLACR_EFDS_MASK; - } - else - { - *regBase &= ~MCM_PLACR_EFDS_MASK; - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= b0ipeMask; - } - else - { - *regBase &= ~b0ipeMask; - } - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase |= b0dpeMask; - } - else - { - *regBase &= ~b0dpeMask; - } - -/* Invalidate Prefetch Speculation Buffer */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#endif - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - FTFx_REG32_ACCESS_TYPE regBase; - uint32_t flashSpeculationMask, dataPrefetchMask; - regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) - { - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - return kStatus_FLASH_InvalidSpeculationOption; - } - else - { - *regBase |= flashSpeculationMask; - } - } - else - { - *regBase &= ~flashSpeculationMask; - if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) - { - *regBase &= ~dataPrefetchMask; - } - else - { - *regBase |= dataPrefetchMask; - } - } - } -#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ - - return kStatus_FLASH_Success; -} - -status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) -{ - memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t)); - - /* Assuming that all speculation options are enabled. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable; - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM - { - uint32_t value; -#if defined(MCM) - value = MCM->PLACR; -#elif defined(MCM0) - value = MCM0->PLACR; -#endif - if (value & MCM_PLACR_DFCS_MASK) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (!(value & MCM_PLACR_EFDS_MASK)) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - { - uint32_t value; - uint32_t b0dpeMask, b0ipeMask; -#if defined(FMC_PFB01CR_B0DPE_MASK) - value = FMC->PFB01CR; - b0dpeMask = FMC_PFB01CR_B0DPE_MASK; - b0ipeMask = FMC_PFB01CR_B0IPE_MASK; -#elif defined(FMC_PFB0CR_B0DPE_MASK) - value = FMC->PFB0CR; - b0dpeMask = FMC_PFB0CR_B0DPE_MASK; - b0ipeMask = FMC_PFB0CR_B0IPE_MASK; -#endif - if (!(value & b0dpeMask)) - { - /* Do not prefetch in response to data references. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - if (!(value & b0ipeMask)) - { - /* Do not prefetch in response to instruction fetches. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - } - } -#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - { - uint32_t value; - uint32_t flashSpeculationMask, dataPrefetchMask; - value = MSCM_OCMDR0_REG; - flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; - dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; - - if (value & flashSpeculationMask) - { - /* Speculation buffer is off. */ - speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - else - { - /* Speculation buffer is on for instruction. */ - if (value & dataPrefetchMask) - { - /* Speculation buffer is off for data. */ - speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; - } - } - } -#endif - - return kStatus_FLASH_Success; -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! - * @brief Copy PIC of flash_run_command() to RAM - */ -static void copy_flash_run_command(uint32_t *flashRunCommand) -{ - assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode)); - callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! - * @brief Flash Command Sequence - * - * This function is used to perform the command write sequence to the flash. - * - * @param driver Pointer to storage for the driver runtime state. - * @return An error code or kStatus_FLASH_Success - */ -static status_t flash_command_sequence(flash_config_t *config) -{ - uint8_t registerValue; - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return returnCode; - } - - /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using - * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() - * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ - callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); -#else - /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ - FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; - - /* clear CCIF bit */ - FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; - - /* Check CCIF bit of the flash status register, wait till it is set. - * IP team indicates that this loop will always complete. */ - while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) - { - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* Check error bits */ - /* Get flash status register value */ - registerValue = FTFx->FSTAT; - - /* checking access error */ - if (registerValue & FTFx_FSTAT_ACCERR_MASK) - { - return kStatus_FLASH_AccessError; - } - /* checking protection error */ - else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) - { - return kStatus_FLASH_ProtectionViolation; - } - /* checking MGSTAT0 non-correctable error */ - else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) - { - return kStatus_FLASH_CommandFailure; - } - else - { - return kStatus_FLASH_Success; - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE -/*! - * @brief Copy PIC of flash_common_bit_operation() to RAM - * - */ -static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation) -{ - assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why +1 operation exist. */ - memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode, - sizeof(s_flashCommonBitOperationFunctionCode)); - callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, - uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1); -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM -/*! @brief Performs the cache clear to the flash by MCM.*/ -void mcm_flash_cache_clear(void) -{ - FTFx_REG32_ACCESS_TYPE regBase; - -#if defined(BL_TARGET_ROM) && defined(MCM0_CACHE_REG) && defined(MCM1_CACHE_REG) && \ - defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) - { - uint16_t armPartNumber = (uint16_t)((SCB->CPUID & SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); - uint32_t cortexVersion = __CORTEX_M; - uint32_t coreId = FSL_FEATURE_FLASH_CURRENT_CORE_ID; -#if (__CORTEX_M <= 7) - /* Note: Below code only apply to dual core device */ - if (s_armCorePartNumberArray[cortexVersion] != armPartNumber) - { - coreId ^= 0x1; - } - regBase = s_mcmModuleAccessTypeArray[coreId]; -#else - #error "Inapplicable ARM Cortext Version!" -#endif - } -#elif defined(MCM0_CACHE_REG) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; -#elif defined(MCM1_CACHE_REG) - regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; -#endif - -#if FLASH_DRIVER_IS_FLASH_RESIDENT - callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - *regBase |= MCM_CACHE_CLEAR_MASK; - - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ - -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC -/*! @brief Performs the cache clear to the flash by FMC.*/ -void fmc_flash_cache_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU); -#else - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB01CR_CINV_WAY_MASK) - FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); -#else - FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM -/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ -void mscm_flash_prefetch_speculation_enable(uint32_t flashIndex, bool enable) -{ - uint8_t setValue; - if (enable) - { - setValue = 0x0U; - } - else - { - setValue = 0x3U; - } - -/* The OCMDR[0] is always used to prefetch main Pflash*/ -/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. - * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - switch (flashIndex) - { -#if FLASH_SSD_IS_FLEXNVM_ENABLED || FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - case kFLASH_MemoryIndexSecondaryFlash: - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); - break; -#endif - case kFLASH_MemoryIndexPrimaryFlash: - default: - callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_SPECULATION_DISABLE_MASK, - MSCM_SPECULATION_DISABLE_SHIFT, setValue); - break; - } -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ - switch (flashIndex) - { -#if FLASH_SSD_IS_FLEXNVM_ENABLED || FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - case kFLASH_MemoryIndexSecondaryFlash: - MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_SPECULATION_DISABLE_MASK)) | MSCM_SPECULATION_DISABLE(setValue); - /* Each cahce clear instaruction should be followed by below code*/ - __ISB(); - __DSB(); - break; -#endif - case kFLASH_MemoryIndexPrimaryFlash: - default: - MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_SPECULATION_DISABLE_MASK)) | MSCM_SPECULATION_DISABLE(setValue); - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); - break; - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ - -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC -/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ -void fmc_flash_prefetch_speculation_clear(void) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; -#if defined(FMC_PFB01CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; - callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_B_INV_MASK, FMC_PFB01CR_S_B_INV_SHIFT, 1U); -#elif defined(FMC_PFB0CR_S_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U); -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; - callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U); -#endif -#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ -#if defined(FMC_PFB01CR_S_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; -#elif defined(FMC_PFB01CR_S_B_INV_MASK) - FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; -#elif defined(FMC_PFB0CR_S_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; -#elif defined(FMC_PFB0CR_S_B_INV_MASK) - FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; -#endif - /* Memory barriers for good measure. - * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ - __ISB(); - __DSB(); -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ -} -#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ - -/*! - * @brief Flash Cache Clear - * - * This function is used to perform the cache and prefetch speculation clear to the flash. - */ -void flash_cache_clear(flash_config_t *config) -{ - flash_cache_clear_process(config, kFLASH_CacheClearProcessPost); -} - -/*! - * @brief Flash Cache Clear Process - * - * This function is used to perform the cache and prefetch speculation clear process to the flash. - */ -static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process) -{ -#if FLASH_DRIVER_IS_FLASH_RESIDENT - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return; - } -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - - /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using - * pre-processed MACROs or a global variable in flash_common_bit_operation() - * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */ - if (process == kFLASH_CacheClearProcessPost) - { -#if FLASH_CACHE_IS_CONTROLLED_BY_MCM - mcm_flash_cache_clear(); -#endif -#if FLASH_CACHE_IS_CONTROLLED_BY_FMC - fmc_flash_cache_clear(); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(config->FlashMemoryIndex, true); -#endif -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC - fmc_flash_prefetch_speculation_clear(); -#endif - } - if (process == kFLASH_CacheClearProcessPre) - { -#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM - mscm_flash_prefetch_speculation_enable(config->FlashMemoryIndex, false); -#endif - } -} - -#if FLASH_DRIVER_IS_FLASH_RESIDENT -/*! @brief Check whether flash execute-in-ram functions are ready */ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - if ((config->flashExecuteInRamFunctionInfo) && - (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_ExecuteInRamFunctionNotReady; -} -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -/*! @brief Validates the range and alignment of the given address range.*/ -static status_t flash_check_range(flash_config_t *config, - uint32_t startAddress, - uint32_t lengthInBytes, - uint32_t alignmentBaseline) -{ - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Verify the start and length are alignmentBaseline aligned. */ - if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - /* check for valid range of the target addresses */ - if ( -#if FLASH_SSD_IS_FLEXNVM_ENABLED - ((startAddress >= config->DFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) || -#endif - ((startAddress >= config->PFlashBlockBase) && - ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize)))) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_AddressError; -} - -/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ -static status_t flash_get_matched_operation_info(flash_config_t *config, - uint32_t address, - flash_operation_config_t *info) -{ - if ((config == NULL) || (info == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_operation_config_t)); - -#if FLASH_SSD_IS_FLEXNVM_ENABLED - if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) - { - /* When required by the command, address bit 23 selects between program flash memory - * (=0) and data flash memory (=1).*/ - info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; - info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; - info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; - - info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; - } - else -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - { - info->convertedAddress = address - config->PFlashBlockBase; - info->activeSectorSize = config->PFlashSectorSize; - info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { -#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER - /* When required by the command, address bit 23 selects between main flash memory - * (=0) and secondary flash memory (=1).*/ - info->convertedAddress += 0x800000U; -#endif - info->blockWriteUnitSize = SECONDARY_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = SECONDARY_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = SECONDARY_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; - } - else -#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ - { - info->blockWriteUnitSize = MAIN_FLASH_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE; - info->sectorCmdAddressAligment = MAIN_FLASH_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; - info->sectionCmdAddressAligment = MAIN_FLASH_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; - } - - info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; - info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; - } - - return kStatus_FLASH_Success; -} - -/*! @brief Validates the given user key for flash erase APIs.*/ -static status_t flash_check_user_key(uint32_t key) -{ - /* Validate the user key */ - if (key != kFLASH_ApiEraseKey) - { - return kStatus_FLASH_EraseKeyError; - } - - return kStatus_FLASH_Success; -} - -#if FLASH_SSD_IS_FLEXNVM_ENABLED -/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) -{ - struct - { - uint32_t reserved0; - uint8_t FlexNVMPartitionCode; - uint8_t EEPROMDataSetSize; - uint16_t reserved1; - } dataIFRReadOut; - status_t returnCode; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - /* Get FlexNVM memory partition info from data flash IFR */ - returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, - sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr); - if (returnCode != kStatus_FLASH_Success) - { - return kStatus_FLASH_PartitionStatusUpdateFailure; - } -#else -#error "Cannot get FlexNVM memory partition info" -#endif - - /* Fill out partitioned EEPROM size */ - dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; - switch (dataIFRReadOut.EEPROMDataSetSize) - { - case 0x00U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; - break; - case 0x01U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; - break; - case 0x02U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; - break; - case 0x03U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; - break; - case 0x04U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; - break; - case 0x05U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; - break; - case 0x06U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; - break; - case 0x07U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; - break; - case 0x08U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; - break; - case 0x09U: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; - break; - case 0x0AU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; - break; - case 0x0BU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; - break; - case 0x0CU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; - break; - case 0x0DU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; - break; - case 0x0EU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; - break; - case 0x0FU: - config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; - break; - default: - config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; - break; - } - - /* Fill out partitioned DFlash size */ - dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; - switch (dataIFRReadOut.FlexNVMPartitionCode) - { - case 0x00U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ - break; - case 0x01U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ - break; - case 0x02U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ - break; - case 0x03U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ - break; - case 0x04U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ - break; - case 0x05U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ - break; - case 0x06U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ - break; - case 0x07U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ - break; - case 0x08U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ - break; - case 0x09U: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ - break; - case 0x0AU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ - break; - case 0x0BU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ - break; - case 0x0CU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ - break; - case 0x0DU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ - break; - case 0x0EU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ - break; - case 0x0FU: -#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) - config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; -#else - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ - break; - default: - config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; - break; - } - - return kStatus_FLASH_Success; -} -#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -/*! @brief Validates the range of the given resource address.*/ -static status_t flash_check_resource_range(uint32_t start, - uint32_t lengthInBytes, - uint32_t alignmentBaseline, - flash_read_resource_option_t option) -{ - status_t status; - uint32_t maxReadbleAddress; - - if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) - { - return kStatus_FLASH_AlignmentError; - } - - status = kStatus_FLASH_Success; - - maxReadbleAddress = start + lengthInBytes - 1; - if (option == kFLASH_ResourceOptionVersionId) - { - if ((start != kFLASH_ResourceRangeVersionIdStart) || - ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd)) - { - status = kStatus_FLASH_InvalidArgument; - } - } - else if (option == kFLASH_ResourceOptionFlashIfr) - { - if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes) - { - } -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP - else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd)) - { - } -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - else if ((start >= kFLASH_ResourceRangeDflashIfrStart) && - (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd)) - { - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - } - else - { - status = kStatus_FLASH_InvalidArgument; - } - - return status; -} -#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -/*! @brief Validates the gived swap control option.*/ -static status_t flash_check_swap_control_option(flash_swap_control_option_t option) -{ - if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) || - (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) || - (option == kFLASH_SwapControlOptionDisableSystem)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_InvalidArgument; -} -#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ - -#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) -{ - flash_swap_ifr_field_data_t flashSwapIfrFieldData; - uint32_t swapIndicatorAddress; - - status_t returnCode; -#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD - returnCode = - FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData, - sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr); - - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } -#else - { - /* From RM, the actual info are stored in FCCOB6,7 */ - uint32_t returnValue[2]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0]; - returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4); - if (returnCode != kStatus_FLASH_Success) - { - return returnCode; - } - flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0]; - } -#endif - - /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, - * the low severval bit value of Swap Indicator Address is always 1'b0 */ - swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress * - FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; - if (address != swapIndicatorAddress) - { - return kStatus_FLASH_SwapIndicatorAddressError; - } - - return returnCode; -} -#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ - -#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -/*! @brief Validates the gived flexram function option.*/ -static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) -{ - if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) && - (option != kFLASH_FlexramFunctionOptionAvailableForEeprom)) - { - return kStatus_FLASH_InvalidArgument; - } - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - -/*! @brief Gets the flash protection information (region size, region count).*/ -static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info) -{ - uint32_t pflashTotalSize; - - if ((config == NULL) || (info == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_protection_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER) - pflashTotalSize = MAIN_FLASH_FEATURE_PFLASH_BLOCK_COUNT * MAIN_FLASH_FEATURE_PFLASH_BLOCK_SIZE + - FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; - info->regionBase = MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS; -#else - pflashTotalSize = config->PFlashTotalSize; - info->regionBase = config->PFlashBlockBase; -#endif - -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER - if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) - { - info->regionCount = SECONDARY_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT; - } - else -#endif - { - info->regionCount = MAIN_FLASH_FEATURE_PFLASH_PROTECTION_REGION_COUNT; - } - - /* Calculate the size of the flash protection region - * If the flash density is > 32KB, then protection region is 1/32 of total flash density - * Else if flash density is < 32KB, then flash protection region is set to 1KB */ - if (pflashTotalSize > info->regionCount * 1024) - { - info->regionSize = (pflashTotalSize) / info->regionCount; - } - else - { - info->regionSize = 1024; - } - - return kStatus_FLASH_Success; -} - -#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ -static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info) -{ - if ((config == NULL) || (info == NULL)) - { - return kStatus_FLASH_InvalidArgument; - } - - /* Clean up info Structure*/ - memset(info, 0, sizeof(flash_access_config_t)); - -/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/ -#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER) - info->SegmentBase = MAIN_FLASH_FEATURE_PFLASH_START_ADDRESS; -#else - info->SegmentBase = config->PFlashBlockBase; -#endif - info->SegmentSize = config->PFlashAccessSegmentSize; - info->SegmentCount = config->PFlashAccessSegmentCount; - - return kStatus_FLASH_Success; -} -#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.h deleted file mode 100644 index c39cc9b43fc027177f72bf8a305aba477046573d..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flash.h +++ /dev/null @@ -1,1348 +0,0 @@ -/* - * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_FLASH_H_ -#define _FSL_FLASH_H_ - -#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) -#include -#include -#include "fsl_device_registers.h" -#include "bootloader_common.h" -#else -#include "fsl_common.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup flash_driver - * @{ - */ - -/*! - * @name Flash version - * @{ - */ -/*! @brief Constructs the version number for drivers. */ -#if !defined(MAKE_VERSION) -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) -#endif - -/*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) /*!< Version 2.4.1. */ - -/*! @brief Flash driver version for ROM*/ -enum _flash_driver_version_constants -{ - kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ - kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 4, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ -}; -/*@}*/ - -/*! - * @name Flash configuration - * @{ - */ -/*! @brief Indicates whether to support FlexNVM in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */ -#endif - -/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */ -#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) - -/*! @brief Indicates whether to support Secondary flash in the Flash driver */ -#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */ -#endif - -/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ -#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) -#else -#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0) -#endif - -/*! @brief Flash driver location. */ -#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) -#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) -#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ -#else -#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ -#endif -#endif - -/*! @brief Flash Driver Export option */ -#if !defined(FLASH_DRIVER_IS_EXPORTED) -#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) -#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ -#else -#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */ -#endif -#endif -/*@}*/ - -/*! - * @name Flash status - * @{ - */ -/*! @brief Flash driver status group. */ -#if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FlashDriver -#elif defined(kStatusGroup_FLASH) -#define kStatusGroupGeneric kStatusGroup_Generic -#define kStatusGroupFlashDriver kStatusGroup_FLASH -#else -#define kStatusGroupGeneric 0 -#define kStatusGroupFlashDriver 1 -#endif - -/*! @brief Constructs a status code value from a group and a code number. */ -#if !defined(MAKE_STATUS) -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) -#endif - -/*! - * @brief Flash driver status codes. - */ -enum _flash_status -{ - kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ - kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ - kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ - kStatus_FLASH_AlignmentError = - MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ - kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ - kStatus_FLASH_AccessError = - MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ - kStatus_FLASH_ProtectionViolation = MAKE_STATUS( - kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ - kStatus_FLASH_CommandFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ - kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ - kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ - kStatus_FLASH_RegionExecuteOnly = - MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ - kStatus_FLASH_ExecuteInRamFunctionNotReady = - MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ - kStatus_FLASH_PartitionStatusUpdateFailure = - MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ - kStatus_FLASH_SetFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ - kStatus_FLASH_RecoverFlexramAsRamError = - MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ - kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ - kStatus_FLASH_RecoverFlexramAsEepromError = - MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ - kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/ - kStatus_FLASH_SwapSystemNotInUninitialized = - MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ - kStatus_FLASH_SwapIndicatorAddressError = - MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/ - kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/ - kStatus_FLASH_InvalidPropertyValue = - MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/ - kStatus_FLASH_InvalidSpeculationOption = - MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ -}; -/*@}*/ - -/*! - * @name Flash API key - * @{ - */ -/*! @brief Constructs the four character code for the Flash driver API key. */ -#if !defined(FOUR_CHAR_CODE) -#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) -#endif - -/*! - * @brief Enumeration for Flash driver API keys. - * - * @note The resulting value is built with a byte order such that the string - * being readable in expected order when viewed in a hex editor, if the value - * is treated as a 32-bit little endian value. - */ -enum _flash_driver_api_keys -{ - kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ -}; -/*@}*/ - -/*! - * @brief Enumeration for supported flash margin levels. - */ -typedef enum _flash_margin_value -{ - kFLASH_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ - kFLASH_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ - kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ - kFLASH_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ -} flash_margin_value_t; - -/*! - * @brief Enumeration for the three possible flash security states. - */ -typedef enum _flash_security_state -{ - kFLASH_SecurityStateNotSecure = 0xc33cc33cU, /*!< Flash is not secure.*/ - kFLASH_SecurityStateBackdoorEnabled = 0x5aa55aa5U, /*!< Flash backdoor is enabled.*/ - kFLASH_SecurityStateBackdoorDisabled = 0x5ac33ca5U /*!< Flash backdoor is disabled.*/ -} flash_security_state_t; - -/*! - * @brief Enumeration for the three possible flash protection levels. - */ -typedef enum _flash_protection_state -{ - kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ - kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ - kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ -} flash_protection_state_t; - -/*! - * @brief Enumeration for the three possible flash execute access levels. - */ -typedef enum _flash_execute_only_access_state -{ - kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ - kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ - kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ -} flash_execute_only_access_state_t; - -/*! - * @brief Enumeration for various flash properties. - */ -typedef enum _flash_property_tag -{ - kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ - kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ - kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ - kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ - kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ - kFLASH_PropertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ - kFLASH_PropertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ - kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ - kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ - kFLASH_PropertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ - kFLASH_PropertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ - kFLASH_PropertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ - kFLASH_PropertyDflashBlockSize = 0x12U, /*!< Dflash block size property.*/ - kFLASH_PropertyDflashBlockCount = 0x13U, /*!< Dflash block count property.*/ - kFLASH_PropertyDflashBlockBaseAddr = 0x14U, /*!< Dflash block base address property.*/ - kFLASH_PropertyEepromTotalSize = 0x15U, /*!< EEPROM total size property.*/ - kFLASH_PropertyFlashMemoryIndex = 0x20U /*!< Flash memory index property.*/ -} flash_property_tag_t; - -/*! - * @brief Constants for execute-in-RAM flash function. - */ -enum _flash_execute_in_ram_function_constants -{ - kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ - kFLASH_ExecuteInRamFunctionTotalNum = 2U /*!< Total number of execute-in-RAM functions.*/ -}; - -/*! - * @brief Flash execute-in-RAM function information. - */ -typedef struct _flash_execute_in_ram_function_config -{ - uint32_t activeFunctionCount; /*!< Number of available execute-in-RAM functions.*/ - uint32_t *flashRunCommand; /*!< Execute-in-RAM function: flash_run_command.*/ - uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/ -} flash_execute_in_ram_function_config_t; - -/*! - * @brief Enumeration for the two possible options of flash read resource command. - */ -typedef enum _flash_read_resource_option -{ - kFLASH_ResourceOptionFlashIfr = - 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ - kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ -} flash_read_resource_option_t; - -/*! - * @brief Enumeration for the range of special-purpose flash resource - */ -enum _flash_read_resource_range -{ -#if (FSL_FEATURE_FLASH_IS_FTFE == 1) - kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ - kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/ -#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ - kFLASH_ResourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ - kFLASH_ResourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ - kFLASH_ResourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ -#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/ -#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/ -#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) - kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/ -#else - kFLASH_ResourceRangePflashSwapIfrStart = 0, -#endif - kFLASH_ResourceRangePflashSwapIfrEnd = - (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/ -#endif - kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ - kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ -}; - -/*! - * @brief Enumeration for the index of read/program once record - */ -enum _k3_flash_read_once_index -{ - kFLASH_RecordIndexSwapAddr = 0xA1U, /*!< Index of Swap indicator address.*/ - kFLASH_RecordIndexSwapEnable = 0xA2U, /*!< Index of Swap system enable.*/ - kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/ -}; - -/*! - * @brief Enumeration for the two possilbe options of set FlexRAM function command. - */ -typedef enum _flash_flexram_function_option -{ - kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ - kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ -} flash_flexram_function_option_t; - -/*! - * @brief Enumeration for acceleration RAM property. - */ -enum _flash_acceleration_ram_property -{ - kFLASH_AccelerationRamSize = 0x400U -}; - -/*! - * @brief Enumeration for the possible options of Swap function - */ -typedef enum _flash_swap_function_option -{ - kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */ - kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */ -} flash_swap_function_option_t; - -/*! - * @brief Enumeration for the possible options of Swap control commands - */ -typedef enum _flash_swap_control_option -{ - kFLASH_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ - kFLASH_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ - kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ - kFLASH_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ - kFLASH_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ -} flash_swap_control_option_t; - -/*! - * @brief Enumeration for the possible flash Swap status. - */ -typedef enum _flash_swap_state -{ - kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ - kFLASH_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ - kFLASH_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ - kFLASH_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ - kFLASH_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ - kFLASH_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ -} flash_swap_state_t; - -/*! - * @breif Enumeration for the possible flash Swap block status - */ -typedef enum _flash_swap_block_status -{ - kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero = - 0x00U, /*!< Swap block status is that lower half program block at zero.*/ - kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero = - 0x01U, /*!< Swap block status is that upper half program block at zero.*/ -} flash_swap_block_status_t; - -/*! - * @brief Flash Swap information - */ -typedef struct _flash_swap_state_config -{ - flash_swap_state_t flashSwapState; /*!CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); - if (!userConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->CTRL = ctrlReg; -} - -void FLEXIO_Deinit(FLEXIO_Type *base) -{ - FLEXIO_Enable(base, false); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) -{ - assert(userConfig); - - userConfig->enableFlexio = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; - userConfig->enableFastAccess = false; -} - -void FLEXIO_Reset(FLEXIO_Type *base) -{ - /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ - base->CTRL |= FLEXIO_CTRL_SWRST_MASK; - base->CTRL = 0; -} - -uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) -{ - assert(index < FLEXIO_SHIFTBUF_COUNT); - - uint32_t address = 0; - - switch (type) - { - case kFLEXIO_ShifterBuffer: - address = (uint32_t) & (base->SHIFTBUF[index]); - break; - - case kFLEXIO_ShifterBufferBitSwapped: - address = (uint32_t) & (base->SHIFTBUFBIS[index]); - break; - - case kFLEXIO_ShifterBufferByteSwapped: - address = (uint32_t) & (base->SHIFTBUFBYS[index]); - break; - - case kFLEXIO_ShifterBufferBitByteSwapped: - address = (uint32_t) & (base->SHIFTBUFBBS[index]); - break; - -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP - case kFLEXIO_ShifterBufferNibbleByteSwapped: - address = (uint32_t) & (base->SHIFTBUFNBS[index]); - break; - -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP - case kFLEXIO_ShifterBufferHalfWordSwapped: - address = (uint32_t) & (base->SHIFTBUFHWS[index]); - break; - -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP - case kFLEXIO_ShifterBufferNibbleSwapped: - address = (uint32_t) & (base->SHIFTBUFNIS[index]); - break; - -#endif - default: - break; - } - return address; -} - -void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) -{ - base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) -#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH - | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) -#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ - | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | - FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); - - base->SHIFTCTL[index] = - FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | - FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | - FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); -} - -void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) -{ - base->TIMCFG[index] = - FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | - FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | - FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | - FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); - - base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); - - base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | - FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | - FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | - FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | - FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); -} - -status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) -{ - assert(base); - assert(handle); - assert(isr); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioHandle[index] == NULL) - { - /* Register FLEXIO simulated driver base, handle and isr. */ - s_flexioType[index] = base; - s_flexioHandle[index] = handle; - s_flexioIsr[index] = isr; - break; - } - } - - if (index == FLEXIO_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - else - { - return kStatus_Success; - } -} - -status_t FLEXIO_UnregisterHandleIRQ(void *base) -{ - assert(base); - - uint8_t index = 0; - - /* Find the index from base address mappings. */ - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioType[index] == base) - { - /* Unregister FLEXIO simulated driver handle and isr. */ - s_flexioType[index] = NULL; - s_flexioHandle[index] = NULL; - s_flexioIsr[index] = NULL; - break; - } - } - - if (index == FLEXIO_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - else - { - return kStatus_Success; - } -} - -void FLEXIO_CommonIRQHandler(void) -{ - uint8_t index; - - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioHandle[index]) - { - s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); - } - } -} - -void FLEXIO_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void FLEXIO0_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void FLEXIO1_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void UART2_FLEXIO_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio.h deleted file mode 100644 index 79a87f62467d1c36d734d096b87720a8eefce98b..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio.h +++ /dev/null @@ -1,683 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXIO_H_ -#define _FSL_FLEXIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexio_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO driver version 2.0.1. */ -#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Calculate FlexIO timer trigger.*/ -#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) -#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) -#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) - -/*! @brief Define time of timer trigger polarity.*/ -typedef enum _flexio_timer_trigger_polarity -{ - kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ -} flexio_timer_trigger_polarity_t; - -/*! @brief Define type of timer trigger source.*/ -typedef enum _flexio_timer_trigger_source -{ - kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ - kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ -} flexio_timer_trigger_source_t; - -/*! @brief Define type of timer/shifter pin configuration.*/ -typedef enum _flexio_pin_config -{ - kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ - kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ - kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ - kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ -} flexio_pin_config_t; - -/*! @brief Definition of pin polarity.*/ -typedef enum _flexio_pin_polarity -{ - kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ -} flexio_pin_polarity_t; - -/*! @brief Define type of timer work mode.*/ -typedef enum _flexio_timer_mode -{ - kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ - kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ - kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ - kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ -} flexio_timer_mode_t; - -/*! @brief Define type of timer initial output or timer reset condition.*/ -typedef enum _flexio_timer_output -{ - kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer - reset. */ - kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer - reset. */ - kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ - kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ -} flexio_timer_output_t; - -/*! @brief Define type of timer decrement.*/ -typedef enum _flexio_timer_decrement_source -{ - kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock - equals Timer output. */ - kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), - Shift clock equals Timer output. */ - kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), - Shift clock equals Pin input. */ - kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), - Shift clock equals Trigger input. */ -} flexio_timer_decrement_source_t; - -/*! @brief Define type of timer reset condition.*/ -typedef enum _flexio_timer_reset_condition -{ - kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ - kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ - kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to - Timer Output. */ - kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ - kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ - kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ -} flexio_timer_reset_condition_t; - -/*! @brief Define type of timer disable condition.*/ -typedef enum _flexio_timer_disable_condition -{ - kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ - kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ - kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ - kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ - kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ - kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided - Trigger is high. */ - kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ -} flexio_timer_disable_condition_t; - -/*! @brief Define type of timer enable condition.*/ -typedef enum _flexio_timer_enable_condition -{ - kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ - kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ - kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ - kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ - kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ - kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ - kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ - kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ -} flexio_timer_enable_condition_t; - -/*! @brief Define type of timer stop bit generate condition.*/ -typedef enum _flexio_timer_stop_bit_condition -{ - kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ - kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ - kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ - kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer - disable. */ -} flexio_timer_stop_bit_condition_t; - -/*! @brief Define type of timer start bit generate condition.*/ -typedef enum _flexio_timer_start_bit_condition -{ - kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ - kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ -} flexio_timer_start_bit_condition_t; - -/*! @brief Define type of timer polarity for shifter control. */ -typedef enum _flexio_shifter_timer_polarity -{ - kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */ - kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */ -} flexio_shifter_timer_polarity_t; - -/*! @brief Define type of shifter working mode.*/ -typedef enum _flexio_shifter_mode -{ - kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ - kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ - kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ - kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ - kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ -#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE - kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing - programmable state attributes. */ -#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ -#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE - kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing - programmable logic look up table. */ -#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ -} flexio_shifter_mode_t; - -/*! @brief Define type of shifter input source.*/ -typedef enum _flexio_shifter_input_source -{ - kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ - kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ -} flexio_shifter_input_source_t; - -/*! @brief Define of STOP bit configuration.*/ -typedef enum _flexio_shifter_stop_bit -{ - kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ - kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ - kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ -} flexio_shifter_stop_bit_t; - -/*! @brief Define type of START bit configuration.*/ -typedef enum _flexio_shifter_start_bit -{ - kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads - data on enable. */ - kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads - data on first shift. */ - kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ - kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ -} flexio_shifter_start_bit_t; - -/*! @brief Define FlexIO shifter buffer type*/ -typedef enum _flexio_shifter_buffer_type -{ - kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ - kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ - kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ - kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP - kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ -#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP - kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP - kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ -#endif -} flexio_shifter_buffer_type_t; - -/*! @brief Define FlexIO user configuration structure. */ -typedef struct _flexio_config_ -{ - bool enableFlexio; /*!< Enable/disable FlexIO module */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires - the FlexIO clock to be at least twice the frequency of the bus clock. */ -} flexio_config_t; - -/*! @brief Define FlexIO timer configuration structure. */ -typedef struct _flexio_timer_config -{ - /* Trigger. */ - uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ - flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ - flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ - /* Pin. */ - flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ - uint32_t pinSelect; /*!< Timer Pin number Select. */ - flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ - /* Timer. */ - flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ - flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and - whether it is affected by the Timer reset. */ - flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the - source of the Shift clock. */ - flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter - (and optionally the timer output) to be reset. */ - flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be - disabled and stop decrementing. */ - flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be - enabled and start decrementing. */ - flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ - flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ - uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ -} flexio_timer_config_t; - -/*! @brief Define FlexIO shifter configuration structure. */ -typedef struct _flexio_shifter_config -{ - /* Timer. */ - uint32_t timerSelect; /*!< Selects which Timer is used for controlling the - logic/shift register and generating the Shift clock. */ - flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ - /* Pin. */ - flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ - uint32_t pinSelect; /*!< Shifter Pin number Select. */ - flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ - /* Shifter. */ - flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ -#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH - uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ -#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ - flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ - flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ - flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ -} flexio_shifter_config_t; - -/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ -typedef void (*flexio_isr_t)(void *base, void *handle); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name FlexIO Initialization and De-initialization - * @{ - */ - -/*! - * @brief Gets the default configuration to configure the FlexIO module. The configuration - * can used directly to call the FLEXIO_Configure(). - * - * Example: - @code - flexio_config_t config; - FLEXIO_GetDefaultConfig(&config); - @endcode - * - * @param userConfig pointer to flexio_config_t structure -*/ -void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); - -/*! - * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure - * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). - * - * Example - @code - flexio_config_t config = { - .enableFlexio = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false - }; - FLEXIO_Configure(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param userConfig pointer to flexio_config_t structure -*/ -void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); - -/*! - * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. - * - * @note After calling this API, call the FLEXO_Init to use the FlexIO module. - * - * @param base FlexIO peripheral base address -*/ -void FLEXIO_Deinit(FLEXIO_Type *base); - -/* @} */ - -/*! - * @name FlexIO Basic Operation - * @{ - */ - -/*! - * @brief Resets the FlexIO module. - * - * @param base FlexIO peripheral base address -*/ -void FLEXIO_Reset(FLEXIO_Type *base); - -/*! - * @brief Enables the FlexIO module operation. - * - * @param base FlexIO peripheral base address - * @param enable true to enable, false to disable. -*/ -static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS -/*! - * @brief Reads the input data on each of the FlexIO pins. - * - * @param base FlexIO peripheral base address - * @return FlexIO pin input data -*/ -static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) -{ - return base->PIN; -} -#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ - -#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE -/*! - * @brief Gets the current state pointer for state mode use. - * - * @param base FlexIO peripheral base address - * @return current State pointer -*/ -static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) -{ - return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); -} -#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ - -/*! - * @brief Configures the shifter with the shifter configuration. The configuration structure - * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper - * mode, select which timer controls the shifter to shift, whether to generate start bit/stop - * bit, and the polarity of start bit and stop bit. - * - * Example - @code - flexio_shifter_config_t config = { - .timerSelect = 0, - .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, - .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, - .pinPolarity = kFLEXIO_PinActiveLow, - .shifterMode = kFLEXIO_ShifterModeTransmit, - .inputSource = kFLEXIO_ShifterInputFromPin, - .shifterStop = kFLEXIO_ShifterStopBitHigh, - .shifterStart = kFLEXIO_ShifterStartBitLow - }; - FLEXIO_SetShifterConfig(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param index Shifter index - * @param shifterConfig Pointer to flexio_shifter_config_t structure -*/ -void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); -/*! - * @brief Configures the timer with the timer configuration. The configuration structure - * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper - * mode, select trigger source for timer and the timer pin output and the timing for timer. - * - * Example - @code - flexio_timer_config_t config = { - .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), - .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, - .triggerSource = kFLEXIO_TimerTriggerSourceInternal, - .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, - .pinSelect = 0, - .pinPolarity = kFLEXIO_PinActiveHigh, - .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, - .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, - .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, - .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, - .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, - .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, - .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, - .timerStart = kFLEXIO_TimerStartBitEnabled - }; - FLEXIO_SetTimerConfig(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param index Timer index - * @param timerConfig Pointer to the flexio_timer_config_t structure -*/ -void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); - -/* @} */ - -/*! - * @name FlexIO Interrupt Operation - * @{ - */ - -/*! - * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSIEN |= mask; -} - -/*! - * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSIEN &= ~mask; -} - -/*! - * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTEIEN |= mask; -} - -/*! - * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTEIEN &= ~mask; -} - -/*! - * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMIEN |= mask; -} - -/*! - * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMIEN &= ~mask; -} - -/* @} */ - -/*! - * @name FlexIO Status Operation - * @{ - */ - -/*! - * @brief Gets the shifter status flags. - * - * @param base FlexIO peripheral base address - * @return Shifter status flags -*/ -static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) -{ - return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); -} - -/*! - * @brief Clears the shifter status flags. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSTAT = mask; -} - -/*! - * @brief Gets the shifter error flags. - * - * @param base FlexIO peripheral base address - * @return Shifter error flags -*/ -static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) -{ - return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); -} - -/*! - * @brief Clears the shifter error flags. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTERR = mask; -} - -/*! - * @brief Gets the timer status flags. - * - * @param base FlexIO peripheral base address - * @return Timer status flags -*/ -static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) -{ - return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); -} - -/*! - * @brief Clears the timer status flags. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMSTAT = mask; -} - -/* @} */ - -/*! - * @name FlexIO DMA Operation - * @{ - */ - -/*! - * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. - * - * @note For multiple shifter status DMA enables, for example, calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @param enable True to enable, false to disable. -*/ -static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->SHIFTSDEN |= mask; - } - else - { - base->SHIFTSDEN &= ~mask; - } -} - -/*! - * @brief Gets the shifter buffer address for the DMA transfer usage. - * - * @param base FlexIO peripheral base address - * @param type Shifter type of flexio_shifter_buffer_type_t - * @param index Shifter index - * @return Corresponding shifter buffer index -*/ -uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); - -/*! - * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. - * - * @param base Pointer to the FlexIO simulated peripheral type. - * @param handle Pointer to the handler for FlexIO simulated peripheral. - * @param isr FlexIO simulated peripheral interrupt handler. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ -status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); - -/*! - * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. - * - * @param base Pointer to the FlexIO simulated peripheral type. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ -status_t FLEXIO_UnregisterHandleIRQ(void *base); -/* @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.c deleted file mode 100644 index 659329034772820abda0ccac85925c15516ee72f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.c +++ /dev/null @@ -1,781 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexio_i2c_master.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief FLEXIO I2C transfer state */ -enum _flexio_i2c_master_transfer_states -{ - kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ - kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ - kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ - kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ - kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ - kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ -}; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -extern const clock_ip_name_t s_flexioClocks[]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -extern FLEXIO_Type *const s_flexioBases[]; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); - -/*! - * @brief Set up master transfer, send slave address and decide the initial - * transfer state. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param transfer pointer to flexio_i2c_master_transfer_t structure - */ -static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer); - -/*! - * @brief Master run transfer state machine to perform a byte of transfer. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param statusFlags flexio i2c hardware status - * @retval kStatus_Success Successfully run state machine - * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer - */ -static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - uint32_t statusFlags); - -/*! - * @brief Complete transfer, disable interrupt and call callback. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param status flexio transfer status - */ -static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status); - -/******************************************************************************* - * Codes - ******************************************************************************/ - -uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) -{ - return FLEXIO_GetInstance(base->flexioBase); -} - -static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer) -{ - bool needRestart; - uint32_t byteCount; - - /* Init the handle member. */ - handle->transfer.slaveAddress = xfer->slaveAddress; - handle->transfer.direction = xfer->direction; - handle->transfer.subaddress = xfer->subaddress; - handle->transfer.subaddressSize = xfer->subaddressSize; - handle->transfer.data = xfer->data; - handle->transfer.dataSize = xfer->dataSize; - handle->transfer.flags = xfer->flags; - handle->transferSize = xfer->dataSize; - - /* Initial state, i2c check address state. */ - handle->state = kFLEXIO_I2C_CheckAddress; - - /* Clear all status before transfer. */ - FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag); - - /* Calculate whether need to send re-start. */ - needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read); - - /* Calculate total byte count in a frame. */ - byteCount = 1; - - if (!needRestart) - { - byteCount += handle->transfer.dataSize; - } - - if (handle->transfer.subaddressSize != 0) - { - byteCount += handle->transfer.subaddressSize; - /* Next state, send command byte. */ - handle->state = kFLEXIO_I2C_SendCommand; - } - - /* Configure data count. */ - if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success) - { - return kStatus_InvalidArgument; - } - - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - - /* Send address byte first. */ - if (needRestart) - { - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); - } - else - { - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); - } - - return kStatus_Success; -} - -static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - uint32_t statusFlags) -{ - if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag) - { - /* Clear receive nak flag. */ - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - - if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && - (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) && - (handle->transfer.dataSize == 1U)))) - { - FLEXIO_I2C_MasterReadByte(base); - - FLEXIO_I2C_MasterAbortStop(base); - - handle->state = kFLEXIO_I2C_Idle; - - return kStatus_FLEXIO_I2C_Nak; - } - } - - if (handle->state == kFLEXIO_I2C_CheckAddress) - { - if (handle->transfer.direction == kFLEXIO_I2C_Write) - { - /* Next state, send data. */ - handle->state = kFLEXIO_I2C_SendData; - } - else - { - /* Next state, receive data begin. */ - handle->state = kFLEXIO_I2C_ReceiveDataBegin; - } - } - - if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData)) - { - FLEXIO_I2C_MasterReadByte(base); - } - - switch (handle->state) - { - case kFLEXIO_I2C_SendCommand: - if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - if (handle->transfer.subaddressSize > 0) - { - handle->transfer.subaddressSize--; - FLEXIO_I2C_MasterWriteByte( - base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize))); - - if (handle->transfer.subaddressSize == 0) - { - /* Load re-start in advance. */ - if (handle->transfer.direction == kFLEXIO_I2C_Read) - { - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterRepeatedStart(base); - } - } - } - else - { - if (handle->transfer.direction == kFLEXIO_I2C_Write) - { - /* Next state, send data. */ - handle->state = kFLEXIO_I2C_SendData; - - /* Send first byte of data. */ - if (handle->transfer.dataSize > 0) - { - FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); - - handle->transfer.data++; - handle->transfer.dataSize--; - } - } - else - { - FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1)); - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); - - /* Next state, receive data begin. */ - handle->state = kFLEXIO_I2C_ReceiveDataBegin; - } - } - } - break; - - /* Send command byte. */ - case kFLEXIO_I2C_SendData: - if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - /* Send one byte of data. */ - if (handle->transfer.dataSize > 0) - { - FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); - - handle->transfer.data++; - handle->transfer.dataSize--; - } - else - { - FLEXIO_I2C_MasterStop(base); - - while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) - { - } - FLEXIO_I2C_MasterReadByte(base); - - handle->state = kFLEXIO_I2C_Idle; - } - } - break; - - case kFLEXIO_I2C_ReceiveDataBegin: - if (statusFlags & kFLEXIO_I2C_RxFullFlag) - { - handle->state = kFLEXIO_I2C_ReceiveData; - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - FLEXIO_I2C_MasterEnableAck(base, false); - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterStop(base); - } - else - { - FLEXIO_I2C_MasterEnableAck(base, true); - } - } - else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - /* Read one byte of data. */ - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); - } - else - { - } - break; - - case kFLEXIO_I2C_ReceiveData: - if (statusFlags & kFLEXIO_I2C_RxFullFlag) - { - *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); - handle->transfer.data++; - if (handle->transfer.dataSize--) - { - if (handle->transfer.dataSize == 0) - { - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable); - handle->state = kFLEXIO_I2C_Idle; - } - - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - FLEXIO_I2C_MasterEnableAck(base, false); - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterStop(base); - } - } - } - else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - if (handle->transfer.dataSize > 1) - { - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); - } - } - else - { - } - break; - - default: - break; - } - - return kStatus_Success; -} - -static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status) -{ - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - if (handle->completionCallback) - { - handle->completionCallback(base, handle, status, handle->userData); - } -} - -status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(base && masterConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t controlVal = 0; - uint16_t timerDiv = 0; - status_t result = kStatus_Success; - - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - FLEXIO_Reset(base->flexioBase); - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for generating bit clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ - timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; - - if (timerDiv > 0xFFU) - { - result = kStatus_InvalidArgument; - return result; - } - - timerConfig.timerCompare = timerDiv; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 4. Configure the timer 1 for controlling shifters. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ - timerConfig.timerCompare = 8 * 2 - 1; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); - - /* Configure FLEXIO I2C Master. */ - controlVal = base->flexioBase->CTRL; - controlVal &= - ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); - if (!masterConfig->enableInDoze) - { - controlVal |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = controlVal; - return result; -} - -void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) -{ - FLEXIO_Deinit(base->flexioBase); -} - -void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; - masterConfig->enableFastAccess = false; - - /* Default baud rate at 100kbps. */ - masterConfig->baudRate_Bps = 100000U; -} - -uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) -{ - uint32_t status = 0; - - status = - ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= - (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 1U); - status |= - (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 2U); - - return status; -} - -void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - - if (mask & kFLEXIO_I2C_RxFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } - - if (mask & kFLEXIO_I2C_ReceiveNakFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_I2C_RxFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_I2C_RxFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ - timerDiv = srcClock_Hz / baudRate_Bps; - timerDiv = timerDiv / 2 - 1U; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0xFF00; - timerCmp |= timerDiv; - - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; -} - -status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) -{ - if (count > 14U) - { - return kStatus_InvalidArgument; - } - - uint16_t timerCmp = 0; - uint32_t timerConfig = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0x00FFU; - timerCmp |= (count * 18 + 1U) << 8U; - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; - timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; - timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; - timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); - flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; - - return kStatus_Success; -} - -void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) -{ - uint32_t data; - - data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); - - FLEXIO_I2C_MasterWriteByte(base, data); -} - -void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) -{ - /* Prepare for RESTART condition, no stop.*/ - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); -} - -void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) -{ - /* Prepare normal stop. */ - FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); - FLEXIO_I2C_MasterWriteByte(base, 0x0U); -} - -void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) -{ - uint32_t tmpConfig; - - /* Prepare abort stop. */ - tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; - tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; - tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); - base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; -} - -void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) -{ - uint32_t tmpConfig = 0; - - tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; - tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; - if (enable) - { - tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); - } - else - { - tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); - } - base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; -} - -status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) -{ - assert(txBuff); - assert(txSize); - - uint32_t status; - - while (txSize--) - { - FLEXIO_I2C_MasterWriteByte(base, *txBuff++); - - /* Wait until data transfer complete. */ - while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag)) - { - } - - if (status & kFLEXIO_I2C_ReceiveNakFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - return kStatus_FLEXIO_I2C_Nak; - } - } - return kStatus_Success; -} - -void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) -{ - assert(rxBuff); - assert(rxSize); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) - { - } - - *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); - } -} - -status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) -{ - assert(xfer); - - flexio_i2c_master_handle_t tmpHandle; - uint32_t statusFlags; - uint32_t result = kStatus_Success; - - /* Zero the handle. */ - memset(&tmpHandle, 0, sizeof(tmpHandle)); - - /* Set up transfer machine. */ - FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); - - do - { - /* Wait either tx empty or rx full flag is asserted. */ - while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & - (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag))) - { - } - - result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); - - } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success)); - - return result; -} - -status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); -} - -status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - if (handle->state != kFLEXIO_I2C_Idle) - { - return kStatus_FLEXIO_I2C_Busy; - } - else - { - /* Set up transfer machine. */ - FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); - - /* Enable both tx empty and rxfull interrupt. */ - FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - return kStatus_Success; - } -} - -void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupts. */ - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - /* Reset to idle state. */ - handle->state = kFLEXIO_I2C_Idle; -} - -status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) -{ - if (!count) - { - return kStatus_InvalidArgument; - } - - *count = handle->transferSize - handle->transfer.dataSize; - - return kStatus_Success; -} - -void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) -{ - FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; - flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; - uint32_t statusFlags; - status_t result; - - statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); - - result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); - - if (handle->state == kFLEXIO_I2C_Idle) - { - FLEXIO_I2C_MasterTransferComplete(base, handle, result); - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.h deleted file mode 100644 index b59f250dcb5606898eabe2394c567b8f78d8dd6a..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_i2c_master.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXIO_I2C_MASTER_H_ -#define _FSL_FLEXIO_I2C_MASTER_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_i2c_master - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO I2C master driver version 2.1.2. */ -#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -/*! @brief FlexIO I2C transfer status*/ -enum _flexio_i2c_status -{ - kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ - kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ - kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ -}; - -/*! @brief Define FlexIO I2C master interrupt mask. */ -enum _flexio_i2c_master_interrupt -{ - kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ - kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO I2C master status mask. */ -enum _flexio_i2c_master_status_flags -{ - kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ - kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ - kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ -}; - -/*! @brief Direction of master transfer.*/ -typedef enum _flexio_i2c_direction -{ - kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ - kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ -} flexio_i2c_direction_t; - -/*! @brief Define FlexIO I2C master access structure typedef. */ -typedef struct _flexio_i2c_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ - uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO I2C. */ -} FLEXIO_I2C_Type; - -/*! @brief Define FlexIO I2C master user configuration structure. */ -typedef struct _flexio_i2c_master_config -{ - bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires - the FlexIO clock to be at least twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ -} flexio_i2c_master_config_t; - -/*! @brief Define FlexIO I2C master transfer structure. */ -typedef struct _flexio_i2c_master_transfer -{ - uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ - uint8_t slaveAddress; /*!< 7-bit slave address. */ - flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - uint8_t subaddressSize; /*!< Size of command buffer. */ - uint8_t volatile *data; /*!< Transfer buffer. */ - volatile size_t dataSize; /*!< Transfer size. */ -} flexio_i2c_master_transfer_t; - -/*! @brief FlexIO I2C master handle typedef. */ -typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; - -/*! @brief FlexIO I2C master transfer callback typedef. */ -typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FlexIO I2C master handle structure. */ -struct _flexio_i2c_master_handle -{ - flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t state; /*!< Transfer state maintained during transfer. */ - flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ - /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C - * hardware configuration. - * - * Example - @code - FLEXIO_I2C_Type base = { - .flexioBase = FLEXIO, - .SDAPinIndex = 0, - .SCLPinIndex = 1, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_i2c_master_config_t config = { - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 100000 - }; - FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param masterConfig Pointer to flexio_i2c_master_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. - * @retval kStatus_Success Initialization successful - * @retval kStatus_InvalidArgument The source clock exceed upper range limitation -*/ -status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief De-initializes the FlexIO I2C master peripheral. Calling this API gates the FlexIO clock - * and the FlexIO I2C master module can't work unless the FLEXIO_I2C_MasterInit is called. - * - * @param base pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO module. The configuration - * can be used directly for calling the FLEXIO_I2C_MasterInit(). - * - * Example: - @code - flexio_i2c_master_config_t config; - FLEXIO_I2C_MasterGetDefaultConfig(&config); - @endcode - * @param masterConfig Pointer to flexio_i2c_master_config_t structure. -*/ -void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); - -/*! - * @brief Enables/disables the FlexIO module operation. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param enable Pass true to enable module, false to disable module. -*/ -static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexIO I2C master status flags. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. -*/ - -uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); - -/*! - * @brief Clears the FlexIO I2C master status flags. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Status flag. - * The parameter can be any combination of the following values: - * @arg kFLEXIO_I2C_RxFullFlag - * @arg kFLEXIO_I2C_ReceiveNakFlag -*/ - -void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO i2c master interrupt requests. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Interrupt source. - * Currently only one interrupt request source: - * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable - */ -void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO I2C master interrupt requests. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Sets the FlexIO I2C master transfer baudrate. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param baudRate_Bps the baud rate value in HZ - * @param srcClock_Hz source clock in HZ - */ -void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sends START + 7-bit address to the bus. - * - * @note This API should be called when the transfer configuration is ready to send a START signal - * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address - * is put into the data register but the address transfer is not finished on the bus. Ensure that - * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param address 7-bit address. - * @param direction transfer direction. - * This parameter is one of the values in flexio_i2c_direction_t: - * @arg kFLEXIO_I2C_Write: Transmit - * @arg kFLEXIO_I2C_Read: Receive - */ - -void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); - -/*! - * @brief Sends the stop signal on the bus. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); - -/*! - * @brief Sends the repeated start signal on the bus. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); - -/*! - * @brief Sends the stop signal when transfer is still on-going. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); - -/*! - * @brief Configures the sent ACK/NAK for the following byte. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param enable True to configure send ACK, false configure to send NAK. - */ -void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); - -/*! - * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. - * - * @note Call this API before a transfer begins because the timer generates a number of clocks according - * to the number of bytes that need to be transferred. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal - * @retval kStatus_Success Successfully configured the count. - * @retval kStatus_InvalidArgument Input argument is invalid. -*/ -status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); - -/*! - * @brief Writes one byte of data to the I2C bus. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register but the data transfer is not finished on the bus. Ensure that - * the TxEmptyFlag is asserted before calling this API. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param data a byte of data. - */ -static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) -{ - base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; -} - -/*! - * @brief Reads one byte of data from the I2C bus. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the data is ready in the register. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @return data byte read. - */ -static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) -{ - return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; -} - -/*! - * @brief Sends a buffer of data in bytes. - * - * @note This function blocks via polling until all bytes have been sent. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param txBuff The data bytes to send. - * @param txSize The number of data bytes to send. - * @retval kStatus_Success Successfully write data. - * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. - */ -status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks via polling until all bytes have been received. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param rxBuff The buffer to store the received bytes. - * @param rxSize The number of data bytes to be received. - */ -void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to receiving NAK. - * - * @param base pointer to FLEXIO_I2C_Type structure. - * @param xfer pointer to flexio_i2c_master_transfer_t structure. - * @return status of status_t. - */ -status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); -/*@}*/ - -/*Transactional APIs*/ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. - * @param callback Pointer to user callback function. - * @param userData User param passed to the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. - */ -status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a master interrupt non-blocking transfer on the I2C bus. - * - * @note The API returns immediately after the transfer initiates. - * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer - * is finished. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param xfer pointer to flexio_i2c_master_transfer_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. - */ -status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state - */ -void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param i2cType Pointer to FLEXIO_I2C_Type structure - * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure - */ -void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.c deleted file mode 100644 index a4eeb33a432dd3f262ff68aa908c9d4ec59a7f71..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.c +++ /dev/null @@ -1,978 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexio_spi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ -enum _flexio_spi_transfer_states -{ - kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ - kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ -}; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -extern const clock_ip_name_t s_flexioClocks[]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -extern FLEXIO_Type *const s_flexioBases[]; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); - -/*! - * @brief Send a piece of data for SPI. - * - * This function computes the number of data to be written into D register or Tx FIFO, - * and write the data into it. At the same time, this function updates the values in - * master handle structure. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param handle Pointer to SPI master handle structure. - */ -static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/*! - * @brief Receive a piece of data for SPI master. - * - * This function computes the number of data to receive from D register or Rx FIFO, - * and write the data to destination address. At the same time, this function updates - * the values in master handle structure. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param handle Pointer to SPI master handle structure. - */ -static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Codes - ******************************************************************************/ - -uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) -{ - return FLEXIO_GetInstance(base->flexioBase); -} - -static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - if (handle->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (handle->bytePerFrame == 1U) - { - tmpData = *(handle->txData); - handle->txData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; - } - else - { - tmpData = (uint32_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; - } - handle->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - handle->txRemainingBytes -= handle->bytePerFrame; - - FLEXIO_SPI_WriteData(base, handle->direction, tmpData); - - if (!handle->txRemainingBytes) - { - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - } -} - -static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - uint16_t tmpData; - - tmpData = FLEXIO_SPI_ReadData(base, handle->direction); - - if (handle->rxData != NULL) - { - if (handle->bytePerFrame == 1U) - { - *handle->rxData = tmpData; - handle->rxData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - *((uint16_t *)(handle->rxData)) = tmpData; - } - else - { - *((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); - } - handle->rxData += 2U; - } - } - handle->rxRemainingBytes -= handle->bytePerFrame; -} - -void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(base); - assert(masterConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure FLEXIO SPI Master */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); - if (!masterConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for SCK. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; - timerDiv = timerDiv / 2 - 1; - - timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U; - timerCmp |= timerDiv; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 4. Configure the timer 1 for CSn. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->CSnPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - - timerConfig.timerCompare = 0xFFFFU; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); -} - -void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) -{ - /* Disable FLEXIO SPI module. */ - FLEXIO_SPI_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate flexio clock. */ - CLOCK_DisableClock(kCLOCK_Flexio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; - masterConfig->enableFastAccess = false; - /* Default baud rate 500kbps. */ - masterConfig->baudRate_Bps = 500000U; - /* Default CPHA = 0. */ - masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; - /* Default bit count at 8. */ - masterConfig->dataMode = kFLEXIO_SPI_8BitMode; -} - -void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) -{ - assert(base && slaveConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(kCLOCK_Flexio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure FLEXIO SPI Slave */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); - if (!slaveConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for shift clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous - PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - } - else - { - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - } - - timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); -} - -void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) -{ - FLEXIO_SPI_MasterDeinit(base); -} - -void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - slaveConfig->enableSlave = true; - slaveConfig->enableInDoze = false; - slaveConfig->enableInDebug = true; - slaveConfig->enableFastAccess = false; - /* Default CPHA = 0. */ - slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; - /* Default bit count at 8. */ - slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; -} - -void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) -{ - if (mask & kFLEXIO_SPI_TxDmaEnable) - { - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable); - } - - if (mask & kFLEXIO_SPI_RxDmaEnable) - { - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable); - } -} - -uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) -{ - uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); - uint32_t status = 0; - - status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); - - return status; -} - -void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxBufferFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) -{ - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ - timerDiv = srcClockHz / baudRate_Bps; - timerDiv = timerDiv / 2 - 1U; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0xFF00U; - timerCmp |= timerDiv; - - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; -} - -void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - const uint8_t *buffer, - size_t size) -{ - assert(buffer); - assert(size); - - while (size--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) - { - } - FLEXIO_SPI_WriteData(base, direction, *buffer++); - } -} - -void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - uint8_t *buffer, - size_t size) -{ - assert(buffer); - assert(size); - - while (size--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) - { - } - *buffer++ = FLEXIO_SPI_ReadData(base, direction); - } -} - -void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) -{ - flexio_spi_shift_direction_t direction; - uint8_t bytesPerFrame; - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - timerCmp &= 0x00FFU; - /* Configure the values in handle. */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - break; - - case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; - break; - - case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; - bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; - break; - - case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; - bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; - break; - - default: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - dataMode |= timerCmp; - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - while (xfer->dataSize) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) - { - } - if (xfer->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (bytesPerFrame == 1U) - { - tmpData = *(xfer->txData); - xfer->txData++; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(xfer->txData[0]) << 8U; - tmpData += xfer->txData[1]; - } - else - { - tmpData = (uint32_t)(xfer->txData[1]) << 8U; - tmpData += xfer->txData[0]; - } - xfer->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - xfer->dataSize -= bytesPerFrame; - - FLEXIO_SPI_WriteData(base, direction, tmpData); - - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) - { - } - tmpData = FLEXIO_SPI_ReadData(base, direction); - - if (xfer->rxData != NULL) - { - if (bytesPerFrame == 1U) - { - *xfer->rxData = tmpData; - xfer->rxData++; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - *((uint16_t *)(xfer->rxData)) = tmpData; - } - else - { - *((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); - } - xfer->rxData += 2U; - } - } - } -} - -status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); -} - -status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - timerCmp &= 0x00FFU; - - /* Check if SPI is busy. */ - if (handle->state == kFLEXIO_SPI_Busy) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if the argument is legal. */ - if ((xfer->txData == NULL) && (xfer->rxData == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Configure the values in handle */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - default: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - dataMode |= timerCmp; - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - handle->rxRemainingBytes = xfer->dataSize; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Send first byte of data to trigger the rx interrupt. */ - if (handle->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (handle->bytePerFrame == 1U) - { - tmpData = *(handle->txData); - handle->txData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; - } - else - { - tmpData = (uint32_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; - } - handle->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; - - FLEXIO_SPI_WriteData(base, handle->direction, tmpData); - - /* Enable transmit and receive interrupt to handle rx. */ - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Return remaing bytes in different cases. */ - if (handle->rxData) - { - *count = handle->transferSize - handle->rxRemainingBytes; - } - else - { - *count = handle->transferSize - handle->txRemainingBytes; - } - - return kStatus_Success; -} - -void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - assert(handle); - - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - - /* Transfer finished, set the state to idle. */ - handle->state = kFLEXIO_SPI_Idle; - - /* Clear the internal state. */ - handle->rxRemainingBytes = 0; - handle->txRemainingBytes = 0; -} - -void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) -{ - assert(spiHandle); - - flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; - FLEXIO_SPI_Type *base; - uint32_t status; - - if (handle->state == kFLEXIO_SPI_Idle) - { - return; - } - - base = (FLEXIO_SPI_Type *)spiType; - status = FLEXIO_SPI_GetStatusFlags(base); - - /* Handle rx. */ - if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) - { - FLEXIO_SPI_TransferReceiveTransaction(base, handle); - } - - /* Handle tx. */ - if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) - { - FLEXIO_SPI_TransferSendTransaction(base, handle); - } - - /* All the transfer finished. */ - if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) - { - FLEXIO_SPI_MasterTransferAbort(base, handle); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); - } - } -} - -status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); -} - -status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - - /* Check if SPI is busy. */ - if (handle->state == kFLEXIO_SPI_Busy) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if the argument is legal. */ - if ((xfer->txData == NULL) && (xfer->rxData == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Configure the values in handle */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - dataMode = 16 * 2 - 1U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - dataMode = 16 * 2 - 1U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - default: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - handle->txRemainingBytes = xfer->dataSize; - handle->rxRemainingBytes = xfer->dataSize; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Enable transmit and receive interrupt to handle tx and rx. */ - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - - return kStatus_Success; -} - -void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) -{ - assert(spiHandle); - - flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; - FLEXIO_SPI_Type *base; - uint32_t status; - - if (handle->state == kFLEXIO_SPI_Idle) - { - return; - } - - base = (FLEXIO_SPI_Type *)spiType; - status = FLEXIO_SPI_GetStatusFlags(base); - - /* Handle tx. */ - if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) - { - FLEXIO_SPI_TransferSendTransaction(base, handle); - } - - /* Handle rx. */ - if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) - { - FLEXIO_SPI_TransferReceiveTransaction(base, handle); - } - - /* All the transfer finished. */ - if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) - { - FLEXIO_SPI_SlaveTransferAbort(base, handle); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); - } - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.h deleted file mode 100644 index 5cb59ffa82dc3028ff43ca6b80eda3590c4f0998..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi.h +++ /dev/null @@ -1,685 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_FLEXIO_SPI_H_ -#define _FSL_FLEXIO_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_spi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO SPI driver version 2.1.1. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -#ifndef FLEXIO_SPI_DUMMYDATA -/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ -#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) -#endif - -/*! @brief Error codes for the FlexIO SPI driver. */ -enum _flexio_spi_status -{ - kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ - kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ - kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ -}; - -/*! @brief FlexIO SPI clock phase configuration. */ -typedef enum _flexio_spi_clock_phase -{ - kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first - * cycle of a data transfer. */ - kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the - * first cycle of a data transfer. */ -} flexio_spi_clock_phase_t; - -/*! @brief FlexIO SPI data shifter direction options. */ -typedef enum _flexio_spi_shift_direction -{ - kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ - kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ -} flexio_spi_shift_direction_t; - -/*! @brief FlexIO SPI data length mode options. */ -typedef enum _flexio_spi_data_bitcount_mode -{ - kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ - kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ -} flexio_spi_data_bitcount_mode_t; - -/*! @brief Define FlexIO SPI interrupt mask. */ -enum _flexio_spi_interrupt_enable -{ - kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO SPI status mask. */ -enum _flexio_spi_status_flags -{ - kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ -}; - -/*! @brief Define FlexIO SPI DMA mask. */ -enum _flexio_spi_dma_enable -{ - kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ - kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ - kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ -}; - -/*! @brief Define FlexIO SPI transfer flags. */ -enum _flexio_spi_transfer_flags -{ - kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ - kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ - kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ - kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ -}; - -/*! @brief Define FlexIO SPI access structure typedef. */ -typedef struct _flexio_spi_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t SDOPinIndex; /*!< Pin select for data output. */ - uint8_t SDIPinIndex; /*!< Pin select for data input. */ - uint8_t SCKPinIndex; /*!< Pin select for clock. */ - uint8_t CSnPinIndex; /*!< Pin select for enable. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ -} FLEXIO_SPI_Type; - -/*! @brief Define FlexIO SPI master configuration structure. */ -typedef struct _flexio_spi_master_config -{ - bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ - flexio_spi_clock_phase_t phase; /*!< Clock phase. */ - flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ -} flexio_spi_master_config_t; - -/*! @brief Define FlexIO SPI slave configuration structure. */ -typedef struct _flexio_spi_slave_config -{ - bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - flexio_spi_clock_phase_t phase; /*!< Clock phase. */ - flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ -} flexio_spi_slave_config_t; - -/*! @brief Define FlexIO SPI transfer structure. */ -typedef struct _flexio_spi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - size_t dataSize; /*!< Transfer bytes. */ - uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ -} flexio_spi_transfer_t; - -/*! @brief typedef for flexio_spi_master_handle_t in advance. */ -typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; - -/*! @brief Slave handle is the same with master handle. */ -typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; - -/*! @brief FlexIO SPI master callback for finished transmit */ -typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI slave callback for finished transmit */ -typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FlexIO SPI handle structure. */ -struct _flexio_spi_master_handle -{ - uint8_t *txData; /*!< Transfer buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ - volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ - volatile uint32_t state; /*!< FlexIO SPI internal state. */ - uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ - flexio_spi_shift_direction_t direction; /*!< Shift direction. */ - flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ - void *userData; /*!< Callback parameter. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name FlexIO SPI Configuration - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, - * and configures the FlexIO SPI with FlexIO SPI master configuration. The - * configuration structure can be filled by the user, or be set with default values - * by the FLEXIO_SPI_MasterGetDefaultConfig(). - * - * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low. - * - * Example - @code - FLEXIO_SPI_Type spiDev = { - .flexioBase = FLEXIO, - .SDOPinIndex = 0, - .SDIPinIndex = 1, - .SCKPinIndex = 2, - .CSnPinIndex = 3, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_spi_master_config_t config = { - .enableMaster = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 500000, - .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, - .direction = kFLEXIO_SPI_MsbFirst, - .dataMode = kFLEXIO_SPI_8BitMode - }; - FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param masterConfig Pointer to the flexio_spi_master_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. -*/ -void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Gates the FlexIO clock. - * - * @param base Pointer to the FLEXIO_SPI_Type. -*/ -void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration - * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). - * Example: - @code - flexio_spi_master_config_t masterConfig; - FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); - @endcode - * @param masterConfig Pointer to the flexio_spi_master_config_t structure. -*/ -void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware - * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The - * configuration structure can be filled by the user, or be set with default values - * by the FLEXIO_SPI_SlaveGetDefaultConfig(). - * - * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. - * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. - * Example - @code - FLEXIO_SPI_Type spiDev = { - .flexioBase = FLEXIO, - .SDOPinIndex = 0, - .SDIPinIndex = 1, - .SCKPinIndex = 2, - .CSnPinIndex = 3, - .shifterIndex = {0,1}, - .timerIndex = {0} - }; - flexio_spi_slave_config_t config = { - .enableSlave = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, - .direction = kFLEXIO_SPI_MsbFirst, - .dataMode = kFLEXIO_SPI_8BitMode - }; - FLEXIO_SPI_SlaveInit(&spiDev, &config); - @endcode - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. -*/ -void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); - -/*! - * @brief Gates the FlexIO clock. - * - * @param base Pointer to the FLEXIO_SPI_Type. -*/ -void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration - * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). - * Example: - @code - flexio_spi_slave_config_t slaveConfig; - FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); - @endcode - * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. -*/ -void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); - -/*@}*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets FlexIO SPI status flags. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @return status flag; Use the status flag to AND the following flag mask and get the status. - * @arg kFLEXIO_SPI_TxEmptyFlag - * @arg kFLEXIO_SPI_RxEmptyFlag -*/ - -uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); - -/*! - * @brief Clears FlexIO SPI status flags. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask status flag - * The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_TxEmptyFlag - * @arg kFLEXIO_SPI_RxEmptyFlag -*/ - -void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO SPI interrupt. - * - * This function enables the FlexIO SPI interrupt. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask interrupt source. The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_RxFullInterruptEnable - * @arg kFLEXIO_SPI_TxEmptyInterruptEnable - */ -void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO SPI interrupt. - * - * This function disables the FlexIO SPI interrupt. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask interrupt source The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_RxFullInterruptEnable - * @arg kFLEXIO_SPI_TxEmptyInterruptEnable - */ -void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, - * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask SPI DMA source. - * @param enable True means enable DMA, false means disable DMA. - */ -void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); - -/*! - * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. - * - * This function returns the SPI data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return FlexIO SPI transmit data register address. - */ -static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, - base->shifterIndex[0]) + - 3U; - } - else - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); - } -} - -/*! - * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. - * - * This function returns the SPI data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return FlexIO SPI receive data register address. - */ -static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); - } - else - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; - } -} - -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO SPI module operation. - * - * @param base Pointer to the FLEXIO_SPI_Type. - * @param enable True to enable, false to disable. -*/ -static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/*! - * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param baudRate_Bps Baud Rate needed in Hz. - * @param srcClockHz SPI source clock frequency in Hz. - */ -void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); - -/*! - * @brief Writes one byte of data, which is sent using the MSB method. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register but the data transfer is not finished on the bus. Ensure that - * the TxEmptyFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param data 8 bit/16 bit data. - */ -static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; - } - else - { - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; - } -} - -/*! - * @brief Reads 8 bit/16 bit data. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the RxFullFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return 8 bit/16 bit data received. - */ -static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; - } - else - { - return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - } -} - -/*! - * @brief Sends a buffer of data bytes. - * - * @note This function blocks using the polling method until all bytes have been sent. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param buffer The data bytes to send. - * @param size The number of data bytes to send. - */ -void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - const uint8_t *buffer, - size_t size); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks using the polling method until all bytes have been received. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param buffer The buffer to store the received bytes. - * @param size The number of data bytes to be received. - * @param direction Shift direction of MSB first or LSB first. - */ -void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - uint8_t *buffer, - size_t size); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks via polling until all bytes have been received. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. - */ -void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); - -/*Transactional APIs*/ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Master transfer data using IRQ. - * - * This function sends data using IRQ. This is a non-blocking function, which returns - * right away. When all data is sent out/received, the callback function is called. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts the master data transfer, which used IRQ. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/*! - * @brief Gets the data transfer status which used IRQ. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); - -/*! - * @brief FlexIO SPI master IRQ handler function. - * - * @param spiType Pointer to the FLEXIO_SPI_Type structure. - * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); - -/*! - * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Slave transfer data using IRQ. - * - * This function sends data using IRQ. This is a non-blocking function, which returns - * right away. When all data is sent out/received, the callback function is called. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. - */ -status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts the slave data transfer which used IRQ, share same API with master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - */ -static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) -{ - FLEXIO_SPI_MasterTransferAbort(base, handle); -} -/*! - * @brief Gets the data transfer status which used IRQ, share same API with master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - size_t *count) -{ - return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); -} - -/*! - * @brief FlexIO SPI slave IRQ handler function. - * - * @param spiType Pointer to the FLEXIO_SPI_Type structure. - * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_SPI_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.c deleted file mode 100644 index 407462e7996c2793de7cf0d5f3cc9729ce12065f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexio_spi_edma.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/*base, kFLEXIO_SPI_TxDmaEnable, false); - - /* change the state */ - spiPrivateHandle->handle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) - { - if (spiPrivateHandle->handle->callback) - { - (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, - spiPrivateHandle->handle->userData); - } - } - } -} - -static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - tcds = tcds; - flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; - - if (transferDone) - { - /* Disable Rx dma */ - FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false); - - /* change the state */ - spiPrivateHandle->handle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) - { - if (spiPrivateHandle->handle->callback) - { - (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, - spiPrivateHandle->handle->userData); - } - } - } -} - -static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - edma_transfer_config_t xferConfig; - flexio_spi_shift_direction_t direction; - uint8_t bytesPerFrame; - - /* Configure the values in handle. */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; - break; - default: - bytesPerFrame = 1U; - direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Configure tx transfer EDMA. */ - xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); - xferConfig.destOffset = 0; - if (bytesPerFrame == 1U) - { - xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - xferConfig.minorLoopBytes = 1; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - xferConfig.destAddr -= 1U; - } - xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; - xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - xferConfig.minorLoopBytes = 2; - } - - /* Configure DMA channel. */ - if (xfer->txData) - { - xferConfig.srcOffset = bytesPerFrame; - xferConfig.srcAddr = (uint32_t)(xfer->txData); - } - else - { - /* Disable the source increasement and source set to dummyData. */ - xferConfig.srcOffset = 0; - xferConfig.srcAddr = (uint32_t)(&s_dummyData); - } - - xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ - handle->nbytes = xferConfig.minorLoopBytes; - - if (handle->txHandle) - { - EDMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - - /* Configure tx transfer EDMA. */ - if (xfer->rxData) - { - xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); - if (bytesPerFrame == 2U) - { - if (direction == kFLEXIO_SPI_LsbFirst) - { - xferConfig.srcAddr -= 1U; - } - } - xferConfig.srcOffset = 0; - xferConfig.destAddr = (uint32_t)(xfer->rxData); - xferConfig.destOffset = bytesPerFrame; - EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true); - EDMA_StartTransfer(handle->rxHandle); - } - - /* Always start Tx transfer. */ - if (handle->txHandle) - { - handle->txInProgress = true; - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true); - EDMA_StartTransfer(handle->txHandle); - } -} - -status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle) -{ - assert(handle); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++) - { - if (s_edmaPrivateHandle[index].base == NULL) - { - s_edmaPrivateHandle[index].base = base; - s_edmaPrivateHandle[index].handle = handle; - break; - } - } - - if (index == FLEXIO_SPI_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - - /* Set spi base to handle. */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle. */ - handle->txInProgress = false; - handle->rxInProgress = false; - - /* Install callback for Tx/Rx dma channel. */ - if (handle->txHandle) - { - EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); - } - if (handle->rxHandle) - { - EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); - } - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - - timerCmp &= 0x00FFU; - - /* Check if the device is busy. */ - if ((handle->txInProgress) || (handle->rxInProgress)) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if input parameter invalid. */ - if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - /* configure data mode. */ - if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) - { - dataMode = (8 * 2 - 1U) << 8U; - } - else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) - { - dataMode = (16 * 2 - 1U) << 8U; - } - else - { - dataMode = 8 * 2 - 1U; - } - - dataMode |= timerCmp; - - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->rxInProgress) - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel)); - } - else - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel)); - } - - return kStatus_Success; -} - -void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma. */ - EDMA_StopTransfer(handle->txHandle); - EDMA_StopTransfer(handle->rxHandle); - - /* Disable DMA enable bit. */ - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false); - - /* Set the handle state. */ - handle->txInProgress = false; - handle->rxInProgress = false; -} - -status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - - /* Check if the device is busy. */ - if ((handle->txInProgress) || (handle->rxInProgress)) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if input parameter invalid. */ - if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - /* configure data mode. */ - if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) - { - dataMode = 8 * 2 - 1U; - } - else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) - { - dataMode = 16 * 2 - 1U; - } - else - { - dataMode = 8 * 2 - 1U; - } - - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.h deleted file mode 100644 index bea2ce7e6c9bf60da3ef8a8173ff8930c283db24..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_spi_edma.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXIO_SPI_EDMA_H_ -#define _FSL_FLEXIO_SPI_EDMA_H_ - -#include "fsl_flexio_spi.h" -#include "fsl_edma.h" - -/*! - * @addtogroup flexio_edma_spi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ -typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; - -/*! @brief Slave handle is the same with master handle. */ -typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; - -/*! @brief FlexIO SPI master callback for finished transmit */ -typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI slave callback for finished transmit */ -typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ -struct _flexio_spi_master_edma_handle -{ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - bool txInProgress; /*!< Send transfer in progress */ - bool rxInProgress; /*!< Receive transfer in progress */ - edma_handle_t *txHandle; /*!< DMA handler for SPI send */ - edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO SPI master eDMA handle. - * - * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional - * APIs. - * For a specified FlexIO SPI instance, call this API once to get the initialized handle. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. - * @param callback SPI callback, NULL means no callback. - * @param userData callback function parameter. - * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. - * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. - */ -status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle); - -/*! - * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. - * - * @note This interface returns immediately after transfer initiates. Call - * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check - * whether the FlexIO SPI transfer is finished. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. - * @param xfer Pointer to FlexIO SPI transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts a FlexIO SPI transfer using eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - */ -void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); - -/*! - * @brief Gets the remaining bytes for FlexIO SPI eDMA transfer. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - size_t *count); - -/*! - * @brief Initializes the FlexIO SPI slave eDMA handle. - * - * This function initializes the FlexIO SPI slave eDMA handle. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - * @param callback SPI callback, NULL means no callback. - * @param userData callback function parameter. - * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. - * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. - */ -static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle) -{ - FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. - * - * @note This interface returns immediately after transfer initiates. Call - * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and - * check whether the FlexIO SPI transfer is finished. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - * @param xfer Pointer to FlexIO SPI transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts a FlexIO SPI transfer using eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - */ -static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) -{ - FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); -} - -/*! - * @brief Gets the remaining bytes to be transferred for FlexIO SPI eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - size_t *count) -{ - return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.c deleted file mode 100644 index 1dc136889e8d8a5e8c34aac503941c4e0017d803..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.c +++ /dev/null @@ -1,700 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexio_uart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*flexioBase); -} - -static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) -{ - size_t size; - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) -{ - bool full; - - if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - - return full; -} - -status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) -{ - assert(base && userConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - status_t result = kStatus_Success; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset FLEXIO before configuration. */ - FLEXIO_Reset(base->flexioBase); - - /* Configure FLEXIO UART */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); - if (!userConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->TxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /*2. Configure the timer 0 for tx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->TxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerDiv = srcClock_Hz / userConfig->baudRate_Bps; - timerDiv = timerDiv / 2 - 1; - - if (timerDiv > 0xFFU) - { - result = kStatus_InvalidArgument; - } - - timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U; - timerCmp |= timerDiv; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 3. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->RxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /* 4. Configure the timer 1 for rx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->RxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); - - return result; -} - -void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) -{ - /* Disable FLEXIO UART module. */ - FLEXIO_UART_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate flexio clock. */ - CLOCK_DisableClock(kCLOCK_Flexio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) -{ - assert(userConfig); - - userConfig->enableUart = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; - userConfig->enableFastAccess = false; - /* Default baud rate 115200. */ - userConfig->baudRate_Bps = 115200U; - /* Default bit count at 8. */ - userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; -} - -void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) -{ - uint32_t status = 0; - status = - ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= - (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 1U); - status |= - (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 2U); - return status; -} - -void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } - if (mask & kFLEXIO_UART_RxOverRunFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) -{ - assert(txData); - assert(txSize); - - while (txSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))) - { - } - - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; - } -} - -void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) -{ - assert(rxData); - assert(rxSize); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag)) - { - } - - *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - } -} - -status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the TX/RX state. */ - handle->rxState = kFLEXIO_UART_RxIdle; - handle->txState = kFLEXIO_UART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); -} - -void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize) -{ - assert(handle); - - /* Setup the ringbuffer address */ - if (ringBuffer) - { - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } -} - -void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kFLEXIO_UART_RxIdle) - { - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kFLEXIO_UART_TxBusy == handle->txState) - { - status = kStatus_FLEXIO_UART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kFLEXIO_UART_TxBusy; - - /* Enable transmiter interrupt. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - /* Disable the transmitter and disable the interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kFLEXIO_UART_TxIdle; -} - -status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) -{ - assert(handle); - assert(count); - - if (kFLEXIO_UART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kFLEXIO_UART_RxBusy == handle->rxState) - { - status = kStatus_FLEXIO_UART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; - } - - /* Enable FLEXIO_UART RX IRQ if previously enabled. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; - - /* Enable RX interrupt. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kFLEXIO_UART_RxIdle; -} - -status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) -{ - assert(handle); - assert(count); - - if (kFLEXIO_UART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) -{ - uint8_t count = 1; - FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; - flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; - - /* Read the status back. */ - uint8_t status = FLEXIO_UART_GetStatusFlags(base); - - /* If RX overrun. */ - if (kFLEXIO_UART_RxOverRunFlag & status) - { - /* Clear Overrun flag. */ - FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); - } - } - - /* Receive data register full */ - if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1]))) - { - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - if (handle->rxDataSize) - { - /* Using non block API to read the data from the registers. */ - FLEXIO_UART_ReadByte(base, handle->rxData); - handle->rxDataSize--; - handle->rxData++; - count--; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kFLEXIO_UART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); - } - } - } - - if (handle->rxRingBuffer) - { - if (count) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0]))) - { - if (handle->txDataSize) - { - /* Using non block API to write the data to the registers. */ - FLEXIO_UART_WriteByte(base, handle->txData); - handle->txData++; - handle->txDataSize--; - count--; - - /* If all the data are written to data register, TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kFLEXIO_UART_TxIdle; - - /* Disable TX register empty interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); - } - } - } - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.h deleted file mode 100644 index 2d23ea34778ec1437d4cfa4a94a63df28c6df695..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_FLEXIO_UART_H_ -#define _FSL_FLEXIO_UART_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_uart - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO UART driver version 2.1.2. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -/*! @brief Error codes for the UART driver. */ -enum _flexio_uart_status -{ - kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ - kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ - kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ - kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ - kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ - kStatus_FLEXIO_UART_RxRingBufferOverrun = - MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ - kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ -}; - -/*! @brief FlexIO UART bit count per char. */ -typedef enum _flexio_uart_bit_count_per_char -{ - kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ - kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ - kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ -} flexio_uart_bit_count_per_char_t; - -/*! @brief Define FlexIO UART interrupt mask. */ -enum _flexio_uart_interrupt_enable -{ - kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO UART status mask. */ -enum _flexio_uart_status_flags -{ - kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ - kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ -}; - -/*! @brief Define FlexIO UART access structure typedef. */ -typedef struct _flexio_uart_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ - uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ -} FLEXIO_UART_Type; - -/*! @brief Define FlexIO UART user configuration structure. */ -typedef struct _flexio_uart_config -{ - bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ - flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ -} flexio_uart_config_t; - -/*! @brief Define FlexIO UART transfer structure. */ -typedef struct _flexio_uart_transfer -{ - uint8_t *data; /*!< Transfer buffer*/ - size_t dataSize; /*!< Transfer size*/ -} flexio_uart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _flexio_uart_handle flexio_uart_handle_t; - -/*! @brief FlexIO UART transfer callback function. */ -typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FLEXIO UART handle structure*/ -struct _flexio_uart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t txDataSizeAll; /*!< Total bytes to be sent. */ - size_t rxDataSizeAll; /*!< Total bytes to be received. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - flexio_uart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART - * hardware, and configures the FlexIO UART with FlexIO UART configuration. - * The configuration structure can be filled by the user or be set with - * default values by FLEXIO_UART_GetDefaultConfig(). - * - * Example - @code - FLEXIO_UART_Type base = { - .flexioBase = FLEXIO, - .TxPinIndex = 0, - .RxPinIndex = 1, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_uart_config_t config = { - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 115200U, - .bitCountPerChar = 8 - }; - FLEXIO_UART_Init(base, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param userConfig Pointer to the flexio_uart_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. - * @retval kStatus_Success Configuration success - * @retval kStatus_InvalidArgument Buadrate configuration out of range -*/ -status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); - -/*! - * @brief Disables the FlexIO UART and gates the FlexIO clock. - * - * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. - * - * @param base Pointer to FLEXIO_UART_Type structure -*/ -void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO UART. The configuration - * can be used directly for calling the FLEXIO_UART_Init(). - * Example: - @code - flexio_uart_config_t config; - FLEXIO_UART_GetDefaultConfig(&userConfig); - @endcode - * @param userConfig Pointer to the flexio_uart_config_t structure. -*/ -void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexIO UART status flags. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART status flags. -*/ - -uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); - -/*! - * @brief Gets the FlexIO UART status flags. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Status flag. - * The parameter can be any combination of the following values: - * @arg kFLEXIO_UART_TxDataRegEmptyFlag - * @arg kFLEXIO_UART_RxEmptyFlag - * @arg kFLEXIO_UART_RxOverRunFlag -*/ - -void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO UART interrupt. - * - * This function enables the FlexIO UART interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO UART interrupt. - * - * This function disables the FlexIO UART interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Gets the FlexIO UARt transmit data register address. - * - * This function returns the UART data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART transmit data register address. - */ -static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); -} - -/*! - * @brief Gets the FlexIO UART receive data register address. - * - * This function returns the UART data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART receive data register address. - */ -static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); -} - -/*! - * @brief Enables/disables the FlexIO UART transmit DMA. - * This function enables/disables the FlexIO UART Tx DMA, - * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param enable True to enable, false to disable. - */ -static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable); -} - -/*! - * @brief Enables/disables the FlexIO UART receive DMA. - * This function enables/disables the FlexIO UART Rx DMA, - * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param enable True to enable, false to disable. - */ -static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable); -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO UART module operation. - * - * @param base Pointer to the FLEXIO_UART_Type. - * @param enable True to enable, false to disable. -*/ -static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/*! - * @brief Writes one byte of data. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register. Ensure that the TxEmptyFlag is asserted before calling - * this API. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param buffer The data bytes to send. - */ -static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) -{ - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; -} - -/*! - * @brief Reads one byte of data. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the RxFullFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param buffer The buffer to store the received bytes. - */ -static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) -{ - *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; -} - -/*! - * @brief Sends a buffer of data bytes. - * - * @note This function blocks using the polling method until all bytes have been sent. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param txData The data bytes to send. - * @param txSize The number of data bytes to send. - */ -void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks using the polling method until all bytes have been received. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param rxData The buffer to store the received bytes. - * @param rxSize The number of data bytes to be received. - */ -void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle. - * - * This function initializes the FlexIO UART handle, which can be used for other FlexIO - * UART transactional APIs. Call this API once to get the - * initialized handle. - * - * The UART driver supports the "background" receiving, which means that users can set up - * a RX ring buffer optionally. Data received is stored into the ring buffer even when - * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data - * received in the ring buffer, users can get the received data from the ring buffer - * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. - * - * @param base to FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received is stored into the ring buffer even when - * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received - * in the ring buffer, users can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize Size of the ring buffer. - */ -void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, - * which returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback - * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. - * - * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However, it does not ensure that all data is sent out. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. - * @retval kStatus_Success Successfully starts the data transmission. - * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. - */ -status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt-driven data sending. Get the remainBytes to find out - * how many bytes are still not sent out. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Gets the number of bytes sent. - * - * This function gets the number of bytes sent driven by interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param count Number of bytes sent so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); - -/*! - * @brief Receives a buffer of data using the interrupt method. - * - * This function receives data using the interrupt method. This is a non-blocking function, - * which returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in ring buffer is not enough to read, the receive - * request is saved by the UART driver. When new data arrives, the receive request - * is serviced first. When all data is received, the UART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. - * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, - * the 5 bytes are copied to xfer->data. This function returns with the - * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to xfer->data. When all data is received, the upper layer is notified. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param xfer UART transfer structure. See #flexio_uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into the transmit queue. - * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. - */ -status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the receive data which was using IRQ. - * - * This function aborts the receive data which was using IRQ. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Gets the number of bytes received. - * - * This function gets the number of bytes received driven by interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param count Number of bytes received so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); - -/*! - * @brief FlexIO UART IRQ handler function. - * - * This function processes the FlexIO UART transmit and receives the IRQ request. - * - * @param uartType Pointer to the FLEXIO_UART_Type structure. - * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_UART_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.c deleted file mode 100644 index 22997b7bc527f82647d832d6a196a29b13d4975f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexio_uart_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*handle); - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, - kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); - } - } -} - -static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, - void *param, - bool transferDone, - uint32_t tcds) -{ - flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; - - assert(uartPrivateHandle->handle); - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, - kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); - } - } -} - -status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++) - { - if (s_edmaPrivateHandle[index].base == NULL) - { - s_edmaPrivateHandle[index].base = base; - s_edmaPrivateHandle[index].handle = handle; - break; - } - } - - if (index == FLEXIO_UART_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kFLEXIO_UART_RxIdle; - handle->txState = kFLEXIO_UART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); - } - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - assert(handle->txEdmaHandle); - - edma_transfer_config_t xferConfig; - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* If previous TX not finished. */ - if (kFLEXIO_UART_TxBusy == handle->txState) - { - status = kStatus_FLEXIO_UART_TxBusy; - } - else - { - handle->txState = kFLEXIO_UART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), - (void *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), - xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable UART TX EDMA. */ - FLEXIO_UART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - assert(handle->rxEdmaHandle); - - edma_transfer_config_t xferConfig; - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* If previous RX not finished. */ - if (kFLEXIO_UART_RxBusy == handle->rxState) - { - status = kStatus_FLEXIO_UART_RxBusy; - } - else - { - handle->rxState = kFLEXIO_UART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), - xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable UART RX EDMA. */ - FLEXIO_UART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) -{ - assert(handle->txEdmaHandle); - - /* Disable UART TX EDMA. */ - FLEXIO_UART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_StopTransfer(handle->txEdmaHandle); - - handle->txState = kFLEXIO_UART_TxIdle; -} - -void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) -{ - assert(handle->rxEdmaHandle); - - /* Disable UART RX EDMA. */ - FLEXIO_UART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_StopTransfer(handle->rxEdmaHandle); - - handle->rxState = kFLEXIO_UART_RxIdle; -} - -status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - size_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kFLEXIO_UART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kFLEXIO_UART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.h deleted file mode 100644 index a552e3114184adab833ba8ff329fcb9a86b41751..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_flexio_uart_edma.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXIO_UART_EDMA_H_ -#define _FSL_FLEXIO_UART_EDMA_H_ - -#include "fsl_flexio_uart.h" -#include "fsl_edma.h" - -/*! - * @addtogroup flexio_edma_uart - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Forward declaration of the handle typedef. */ -typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART eDMA handle -*/ -struct _flexio_uart_edma_handle -{ - flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - - size_t txDataSizeAll; /*!< Total bytes to be sent. */ - size_t rxDataSizeAll; /*!< Total bytes to be received. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle which is used in transactional functions. - * - * @param base Pointer to FLEXIO_UART_Type. - * @param handle Pointer to flexio_uart_edma_handle_t structure. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. - * @param txEdmaHandle User requested DMA handle for TX DMA transfer. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. - */ -status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent out, the send callback function is called. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle UART handle pointer. - * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. - */ -status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_UART_RxBusy Previous transfer on going. - */ -status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data which using eDMA. - * - * This function aborts sent data which using eDMA. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - */ -void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); - -/*! - * @brief Aborts the receive data which using eDMA. - * - * This function aborts the receive data which using eDMA. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - */ -void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes sent out. - * - * This function gets the number of bytes sent out. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param count Number of bytes sent so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); - -/*! - * @brief Gets the number of bytes received. - * - * This function gets the number of bytes received. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param count Number of bytes received so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - size_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UART_EDMA_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c deleted file mode 100644 index 1fa8cc4b67d9da3153ef4c1c1b4e487a9a9774a2..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ -static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; -static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! -* @brief Gets the GPIO instance according to the GPIO base -* -* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval GPIO instance -*/ -static uint32_t GPIO_GetInstance(GPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GPIO_GetInstance(GPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) - { - if (s_gpioBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gpioBases)); - - return instance; -} - -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) -{ - assert(config); - - if (config->pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - GPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - PORT_Type *portBase; - instance = GPIO_GetInstance(base); - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) -{ - base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | - ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); -} -#endif - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/******************************************************************************* - * Variables - ******************************************************************************/ -static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; - -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! -* @brief Gets the FGPIO instance according to the GPIO base -* -* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval FGPIO instance -*/ -static uint32_t FGPIO_GetInstance(FGPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t FGPIO_GetInstance(FGPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) - { - if (s_fgpioBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_fgpioBases)); - - return instance; -} - -#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL -void FGPIO_Init(FGPIO_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate FGPIO periphral clock */ - CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} -#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ - -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) -{ - assert(config); - - if (config->pinDirection == kGPIO_DigitalInput) - { - base->PDDR &= ~(1U << pin); - } - else - { - FGPIO_WritePinOutput(base, pin, config->outputLogic); - base->PDDR |= (1U << pin); - } -} - -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - return portBase->ISFR; -} - -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) -{ - uint8_t instance; - instance = FGPIO_GetInstance(base); - PORT_Type *portBase; - portBase = s_portBases[instance]; - portBase->ISFR = mask; -} - -#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER -void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) -{ - base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | - (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); -} -#endif - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h deleted file mode 100644 index 6d2d6f1357c5ed20434dd09598162eb9d784f75d..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpio - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief GPIO driver version 2.2.0. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! @brief GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! @brief GPIO checker attribute */ -typedef enum _gpio_checker_attribute -{ - kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = - 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = - 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = - 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = - 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = - 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = - 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = - 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ - kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = - 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ - kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ -} gpio_checker_attribute_t; -#endif - -/*! - * @brief The GPIO pin configuration structure. - * - * Each pin can only be configured as either an output pin or an input pin at a time. - * If configured as an input pin, leave the outputConfig unused. - * Note that in some use cases, the corresponding port property should be configured in advance - * with the PORT_SetPinConfig(). - */ -typedef struct z_gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations; ignore if configured as an input pin */ - uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ -} gpio_pin_config_t; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup gpio_driver - * @{ - */ - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or an output pin configuration. - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO port pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1U << pin; - } - else - { - base->PSOR = 1U << pin; - } -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses the current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO port. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name GPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads the GPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); - -/*! - * @brief Clears multiple GPIO pin interrupt status flags. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! - * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit - * words. Each 32-bit data port includes a GACR register, which defines the byte-level - * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data - * bytes in the GACR follow a standard little endian - * data convention. - * - * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) - * @param mask GPIO pin number macro - */ -void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); -#endif - -/*@}*/ -/*! @} */ - -/*! - * @addtogroup fgpio_driver - * @{ - */ - -/* - * Introduces the FGPIO feature. - * - * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT - * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and - * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. - */ - -#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT - -/*! @name FGPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the FGPIO peripheral. - * - * This function ungates the FGPIO clock. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - */ - void FGPIO_Init(FGPIO_Type *base); - -/*! - * @brief Initializes a FGPIO pin used by the board. - * - * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. - * Then, call the FGPIO_PinInit() function. - * - * This is an example to define an input pin or an output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO port pin number - * @param config FGPIO pin configuration pointer - */ -void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name FGPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO pin number - * @param output FGPIOpin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) -{ - if (output == 0U) - { - base->PCOR = 1 << pin; - } - else - { - base->PSOR = 1 << pin; - } -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 1. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PSOR = mask; -} - -/*! - * @brief Sets the output level of the multiple FGPIO pins to the logic 0. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PCOR = mask; -} - -/*! - * @brief Reverses the current output logic of the multiple FGPIO pins. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) -{ - base->PTOR = mask; -} -/*@}*/ - -/*! @name FGPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the FGPIO port. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param pin FGPIO pin number - * @retval FGPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) -{ - return (((base->PDIR) >> pin) & 0x01U); -} -/*@}*/ - -/*! @name FGPIO Interrupt */ -/*@{*/ - -/*! - * @brief Reads the FGPIO port interrupt status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level-sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 17 have the interrupt. - */ -uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); - -/*! - * @brief Clears the multiple FGPIO pin interrupt status flag. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); - -#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER -/*! - * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit - * words. Each 32-bit data port includes a GACR register, which defines the byte-level - * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data - * bytes in the GACR follow a standard little endian - * data convention. - * - * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) - * @param mask FGPIO pin number macro - */ -void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); -#endif - -/*@}*/ - -#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_GPIO_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.c deleted file mode 100644 index 315dc5e714938a0a8a8885ab12dbf9b4fee25388..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_intmux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for INTMUX. - * - * @param base INTMUX peripheral base address. - */ -static uint32_t INTMUX_GetInstance(INTMUX_Type *base); - -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) -/*! - * @brief Handle INTMUX all channels IRQ. - * - * The handler reads the INTMUX channel's active vector register. This returns the offset - * from the start of the vector table to the vector for the INTMUX channel's highest priority - * pending source interrupt. After a check for spurious interrupts (an offset of 0), the - * function address at the vector offset is read and jumped to. - * - * @param base INTMUX peripheral base address. - * @param channel INTMUX channel number. - */ -static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel); -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map INTMUX instance number to base pointer. */ -static INTMUX_Type *const s_intmuxBases[] = INTMUX_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map INTMUX instance number to clock name. */ -static const clock_ip_name_t s_intmuxClockName[] = INTMUX_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) -/*! @brief Array to map INTMUX instance number to IRQ number. */ -static const IRQn_Type s_intmuxIRQNumber[][FSL_FEATURE_INTMUX_CHANNEL_COUNT] = INTMUX_IRQS; -#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t INTMUX_GetInstance(INTMUX_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_intmuxBases); instance++) - { - if (s_intmuxBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_intmuxBases)); - - return instance; -} - -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) -static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel) -{ - uint32_t pendingIrqOffset; - - pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC; - - if (pendingIrqOffset) - { -#if defined(__riscv) - extern uint32_t __user_vector[]; - uint32_t isr = __user_vector[pendingIrqOffset / 4 - 48 + 32]; -#else - uint32_t isr = *(uint32_t *)(SCB->VTOR + pendingIrqOffset); -#endif - ((void (*)(void))isr)(); - } -} -#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */ - -void INTMUX_Init(INTMUX_Type *base) -{ - uint32_t channel; - uint32_t instance = INTMUX_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable clock gate. */ - CLOCK_EnableClock(s_intmuxClockName[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset all channels and enable NVIC vectors for all INTMUX channels. */ - for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++) - { - INTMUX_ResetChannel(base, channel); -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) - EnableIRQ(s_intmuxIRQNumber[instance][channel]); -#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */ - } -} - -void INTMUX_Deinit(INTMUX_Type *base) -{ - uint32_t channel; - uint32_t instance = INTMUX_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable clock gate. */ - CLOCK_DisableClock(s_intmuxClockName[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Disable NVIC vectors for all of the INTMUX channels. */ - for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++) - { -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) - DisableIRQ(s_intmuxIRQNumber[instance][channel]); -#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */ - } -} - -#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT) -#if defined(INTMUX0) -void INTMUX0_0_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 0); -} - -void INTMUX0_1_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 1); -} - -void INTMUX0_2_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 2); -} - -void INTMUX0_3_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 3); -} - -#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U) -void INTMUX0_4_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 4); -} - -void INTMUX0_5_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 5); -} - -void INTMUX0_6_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 6); -} - -void INTMUX0_7_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX0, 7); -} -#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */ - -#endif - -#if defined(INTMUX1) -void INTMUX1_0_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 0); -} - -void INTMUX1_1_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 1); -} - -void INTMUX1_2_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 2); -} - -void INTMUX1_3_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 3); -} - -#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U) -void INTMUX1_4_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 4); -} - -void INTMUX1_5_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 5); -} - -void INTMUX1_6_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 6); -} - -void INTMUX1_7_DriverIRQHandler(void) -{ - INTMUX_CommonIRQHandler(INTMUX1, 7); -} -#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */ -#endif /* INTMUX1 */ -#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.h deleted file mode 100644 index 59a6f17cf4411b219693bf17f3e5414a841e5a5a..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_intmux.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_INTMUX_H_ -#define _FSL_INTMUX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup intmux - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*!< Version 2.0.1. */ -#define FSL_INTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief INTMUX channel logic mode. */ -typedef enum _intmux_channel_logic_mode -{ - kINTMUX_ChannelLogicOR = 0x0U, /*!< Logic OR all enabled interrupt inputs */ - kINTMUX_ChannelLogicAND, /*!< Logic AND all enabled interrupt inputs */ -} intmux_channel_logic_mode_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Initializes the INTMUX module. - * - * This function enables the clock gate for the specified INTMUX. It then resets all channels, so that no - * interrupt sources are routed and the logic mode is set to default of #kINTMUX_ChannelLogicOR. - * Finally, the NVIC vectors for all the INTMUX output channels are enabled. - * - * @param base INTMUX peripheral base address. - */ -void INTMUX_Init(INTMUX_Type *base); - -/*! - * @brief Deinitializes an INTMUX instance for operation. - * - * The clock gate for the specified INTMUX is disabled and the NVIC vectors for all channels are disabled. - * - * @param base INTMUX peripheral base address. - */ -void INTMUX_Deinit(INTMUX_Type *base); - -/*! - * @brief Resets an INTMUX channel. - * - * Sets all register values in the specified channel to their reset value. This function disables all interrupt - * sources for the channel. - * - * @param base INTMUX peripheral base address. - * @param channel The INTMUX channel number. - */ -static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); - - base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK; -} - -/*! - * @brief Sets the logic mode for an INTMUX channel. - * - * INTMUX channels can be configured to use one of the two logic modes that control how pending interrupt sources - * on the channel trigger the output interrupt. - * - #kINTMUX_ChannelLogicOR means any source pending triggers the output interrupt. - * - #kINTMUX_ChannelLogicAND means all selected sources on the channel must be pending before the channel - * output interrupt triggers. - * - * @param base INTMUX peripheral base address. - * @param channel The INTMUX channel number. - * @param logic The INTMUX channel logic mode. - */ -static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_mode_t logic) -{ - assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); - - base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic); -} - -/*@}*/ -/*! @name Sources */ -/*@{*/ - -/*! - * @brief Enables an interrupt source on an INTMUX channel. - * - * @param base INTMUX peripheral base address. - * @param channel Index of the INTMUX channel on which the specified interrupt is enabled. - * @param irq Interrupt to route to the specified INTMUX channel. The interrupt must be an INTMUX source. - */ -static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq) -{ - assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); - assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX); - - base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX)); -} - -/*! - * @brief Disables an interrupt source on an INTMUX channel. - * - * @param base INTMUX peripheral base address. - * @param channel Index of the INTMUX channel on which the specified interrupt is disabled. - * @param irq Interrupt number. The interrupt must be an INTMUX source. - */ -static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq) -{ - assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); - assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX); - - base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX)); -} - -/*@}*/ -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets INTMUX pending interrupt sources for a specific channel. - * - * @param base INTMUX peripheral base address. - * @param channel The INTMUX channel number. - * @return The mask of pending interrupt bits. Bit[n] set means INTMUX source n is pending. - */ -static inline uint32_t INTMUX_GetChannelPendingSources(INTMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); - - return base->CHANNEL[channel].CHn_IPR_31_0; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_INTMUX_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.c deleted file mode 100644 index 7ef26535d821aa0a32500b2e391346de214d7d02..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_llwu.h" - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - volatile uint32_t *regBase; - uint32_t regOffset; - uint32_t reg; - - switch (pinIndex >> 4U) - { - case 0U: - regBase = &base->PE1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 1U: - regBase = &base->PE2; - break; -#endif - default: - regBase = NULL; - break; - } -#else - volatile uint8_t *regBase; - uint8_t regOffset; - uint8_t reg; - switch (pinIndex >> 2U) - { - case 0U: - regBase = &base->PE1; - break; - case 1U: - regBase = &base->PE2; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 2U: - regBase = &base->PE3; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) - case 3U: - regBase = &base->PE4; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 4U: - regBase = &base->PE5; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) - case 5U: - regBase = &base->PE6; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 6U: - regBase = &base->PE7; - break; -#endif -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) - case 7U: - regBase = &base->PE8; - break; -#endif - default: - regBase = NULL; - break; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ - - if (regBase) - { - reg = *regBase; -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - regOffset = ((pinIndex & 0x0FU) << 1U); -#else - regOffset = ((pinIndex & 0x03U) << 1U); -#endif - reg &= ~(0x3U << regOffset); - reg |= ((uint32_t)pinMode << regOffset); - *regBase = reg; - } -} - -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->PF & (1U << pinIndex)); -#else - volatile uint8_t *regBase; - - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - return (bool)(*regBase & (1U << pinIndex % 8)); - } - else - { - return false; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - base->PF = (1U << pinIndex); -#else - volatile uint8_t *regBase; - switch (pinIndex >> 3U) - { -#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) - case 0U: - regBase = &base->PF1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->PF2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->PF3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->PF4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#else - case 0U: - regBase = &base->F1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) - case 1U: - regBase = &base->F2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) - case 2U: - regBase = &base->F3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) - case 3U: - regBase = &base->F4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ -#endif /* FSL_FEATURE_LLWU_HAS_PF */ - default: - regBase = NULL; - break; - } - if (regBase) - { - *regBase = (1U << pinIndex % 8U); - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - base->FILT = ((base->FILT) & ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << ((filterIndex - 1U) * 8U))) | - ((LLWU_FILT_FILTSEL1(filterMode.pinIndex) | LLWU_FILT_FILTE1(filterMode.filterMode)) - << ((filterIndex - 1U) * 8U)) | - LLWU_FILT_FILTF1_MASK /* W1C to clear the FILTF flag bit. */ - ; -#else - volatile uint8_t *regBase; - - switch (filterIndex) - { - case 1U: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2U: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3U: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4U: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (NULL != regBase) - { - *regBase = (*regBase & ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK)) | - LLWU_FILT1_FILTSEL(filterMode.pinIndex) | LLWU_FILT1_FILTE(filterMode.filterMode) | - LLWU_FILT1_FILTF_MASK /* W1C to clear the FILTF flag bit. */ - ; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); -#else - bool status = false; - - switch (filterIndex) - { - case 1: - status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - break; - } - - return status; -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} - -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) -{ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) - uint32_t reg; - - reg = base->FILT; - switch (filterIndex) - { - case 1: - reg |= LLWU_FILT_FILTF1_MASK; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - reg |= LLWU_FILT_FILTF2_MASK; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1 */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - reg |= LLWU_FILT_FILTF3_MASK; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2 */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - reg |= LLWU_FILT_FILTF4_MASK; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3 */ - default: - break; - } - base->FILT = reg; -#else - volatile uint8_t *regBase; - uint8_t reg; - - switch (filterIndex) - { - case 1: - regBase = &base->FILT1; - break; -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) - case 2: - regBase = &base->FILT2; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) - case 3: - regBase = &base->FILT3; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) - case 4: - regBase = &base->FILT4; - break; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - default: - regBase = NULL; - break; - } - - if (regBase) - { - reg = *regBase; - reg |= LLWU_FILT1_FILTF_MASK; - *regBase = reg; - } -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ -} -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) -{ - uint8_t reg; - - reg = base->RST; - reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); - reg |= - (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); - base->RST = reg; -} -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.h deleted file mode 100644 index 47a4bee117245b07d931e40f6dacbba8d2cd8e78..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_llwu.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LLWU_H_ -#define _FSL_LLWU_H_ - -#include "fsl_common.h" - -/*! @addtogroup llwu */ -/*! @{ */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LLWU driver version 2.0.1. */ -#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief External input pin control modes - */ -typedef enum _llwu_external_pin_mode -{ - kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as a wakeup input. */ - kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with the rising edge detection. */ - kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/ - kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ -} llwu_external_pin_mode_t; - -/*! - * @brief Digital filter control modes - */ -typedef enum _llwu_pin_filter_mode -{ - kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ - kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ - kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ - kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ -} llwu_pin_filter_mode_t; - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief IP version ID definition. - */ -typedef struct _llwu_version_id -{ - uint16_t feature; /*!< A feature specification number. */ - uint8_t minor; /*!< The minor version number. */ - uint8_t major; /*!< The major version number. */ -} llwu_version_id_t; -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief IP parameter definition. - */ -typedef struct _llwu_param -{ - uint8_t filters; /*!< A number of the pin filter. */ - uint8_t dmas; /*!< A number of the wakeup DMA. */ - uint8_t modules; /*!< A number of the wakeup module. */ - uint8_t pins; /*!< A number of the wake up pin. */ -} llwu_param_t; -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief An external input pin filter control structure - */ -typedef struct _llwu_external_pin_filter_mode -{ - uint32_t pinIndex; /*!< A pin number */ - llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ -} llwu_external_pin_filter_mode_t; -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Low-Leakage Wakeup Unit Control APIs - * @{ - */ - -#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) -/*! - * @brief Gets the LLWU version ID. - * - * This function gets the LLWU version ID, including the major version number, - * the minor version number, and the feature specification number. - * - * @param base LLWU peripheral base address. - * @param versionId A pointer to the version ID structure. - */ -static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} -#endif /* FSL_FEATURE_LLWU_HAS_VERID */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) -/*! - * @brief Gets the LLWU parameter. - * - * This function gets the LLWU parameter, including a wakeup pin number, a module - * number, a DMA number, and a pin filter number. - * - * @param base LLWU peripheral base address. - * @param param A pointer to the LLWU parameter structure. - */ -static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) -{ - *((uint32_t *)param) = base->PARAM; -} -#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ - -#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) -/*! - * @brief Sets the external input pin source mode. - * - * This function sets the external input pin source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1. - * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. - */ -void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the MCU is - * woken up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index, which starts from 1. - * @return True if the specific pin is a wakeup source. - */ -bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); - -/*! - * @brief Clears the external wakeup source flag. - * - * This function clears the external wakeup source flag for a specific pin. - * - * @param base LLWU peripheral base address. - * @param pinIndex A pin index, which starts from 1. - */ -void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); -#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ - -#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) -/*! - * @brief Enables/disables the internal module source. - * - * This function enables/disables the internal module source mode that is used - * as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex A module index to be enabled as an internal wakeup source starting from 1. - * @param enable An enable or a disable setting - */ -static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->ME |= 1U << moduleIndex; - } - else - { - base->ME &= ~(1U << moduleIndex); - } -} - -#if (!(defined(FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG) && \ - FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG)) -/* Re-define the register which includes the internal wakeup module flag. */ -#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) /* 32-bit LLWU. */ -#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) -#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF -#else -#error "Unsupported internal module flag register." -#endif -#else /* 8-bit LLUW. */ -#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) -#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF5 -#elif(defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) -#define INTERNAL_WAKEUP_MODULE_FLAG_REG PF3 -#elif(!(defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))) -#define INTERNAL_WAKEUP_MODULE_FLAG_REG F3 -#else -#error "Unsupported internal module flag register." -#endif -#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ - -/*! - * @brief Gets the external wakeup source flag. - * - * This function checks the external pin flag to detect whether the system is - * woken up by the specific pin. - * - * @param base LLWU peripheral base address. - * @param moduleIndex A module index, which starts from 1. - * @return True if the specific pin is a wake up source. - */ -static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) -{ - return ((1U << moduleIndex) == (base->INTERNAL_WAKEUP_MODULE_FLAG_REG & (1U << moduleIndex))); -} -#endif /* FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG */ -#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ - -#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) -/*! - * @brief Enables/disables the internal module DMA wakeup source. - * - * This function enables/disables the internal DMA that is used as a wake up source. - * - * @param base LLWU peripheral base address. - * @param moduleIndex An internal module index which is used as a DMA request source, starting from 1. - * @param enable Enable or disable the DMA request source - */ -static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) -{ - if (enable) - { - base->DE |= 1U << moduleIndex; - } - else - { - base->DE &= ~(1U << moduleIndex); - } -} -#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ - -#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) -/*! - * @brief Sets the pin filter configuration. - * - * This function sets the pin filter configuration. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. - * @param filterMode A filter mode configuration - */ -void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); - -/*! - * @brief Gets the pin filter configuration. - * - * This function gets the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index, which starts from 1. - * @return True if the flag is a source of the existing low-leakage power mode. - */ -bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -/*! - * @brief Clears the pin filter configuration. - * - * This function clears the pin filter flag. - * - * @param base LLWU peripheral base address. - * @param filterIndex A pin filter index to clear the flag, starting from 1. - */ -void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); - -#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ - -#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) -/*! - * @brief Sets the reset pin mode. - * - * This function determines how the reset pin is used as a low leakage mode exit source. - * - * @param pinEnable Enable reset the pin filter - * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. - */ -void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); -#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ -#endif /* _FSL_LLWU_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.c deleted file mode 100644 index 9ce603bec955506ed3c1ecd33a40c0df517da559..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpadc.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for LPADC module. - * - * @param base LPADC peripheral base address - */ -static uint32_t LPADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to LPADC bases for each instance. */ -static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to LPADC clocks for each instance. */ -static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t LPADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) - { - if (s_lpadcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpadcBases)); - - return instance; -} - -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) -{ - /* Check if the pointer is available. */ - assert(config != NULL); - - uint32_t tmp32 = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock for LPADC instance. */ - CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the module. */ - LPADC_DoResetConfig(base); - LPADC_DoResetFIFO(base); - - /* Disable the module before setting configuration. */ - LPADC_Enable(base, false); - - /* Configure the module generally. */ - if (config->enableInDozeMode) - { - base->CTRL &= ~ADC_CTRL_DOZEN_MASK; - } - else - { - base->CTRL |= ADC_CTRL_DOZEN_MASK; - } - -/* ADCx_CFG. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - if (config->enableInternalClock) - { - tmp32 |= ADC_CFG_ADCKEN_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - if (config->enableVref1LowVoltage) - { - tmp32 |= ADC_CFG_VREF1RNG_MASK; - } -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - if (config->enableAnalogPreliminary) - { - tmp32 |= ADC_CFG_PWREN_MASK; - } - tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ - | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ - | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */ - base->CFG = tmp32; - - /* ADCx_PAUSE. */ - if (config->enableConvPause) - { - base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); - } - else - { - base->PAUSE = 0U; - } - - /* ADCx_FCTRL. */ - base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); - - /* Enable the module after setting configuration. */ - LPADC_Enable(base, true); -} - -void LPADC_GetDefaultConfig(lpadc_config_t *config) -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - config->enableInternalClock = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - config->enableVref1LowVoltage = false; -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - config->enableInDozeMode = true; - config->enableAnalogPreliminary = false; - config->powerUpDelay = 0x80; - config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; - config->enableConvPause = false; - config->convPauseDelay = 0U; - config->FIFOWatermark = 0U; -} - -void LPADC_Deinit(ADC_Type *base) -{ - /* Disable the module. */ - LPADC_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the clock. */ - CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) -{ - assert(result != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = base->RESFIFO; - - if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) - { - return false; /* FIFO is empty. Discard any read from RESFIFO. */ - } - - result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; - result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; - result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; - result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); - - return true; -} - -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) -{ - assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ - | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ - | ADC_TCTRL_TPRI(config->priority); /* Trigger priority setting. */ - if (config->enableHardwareTrigger) - { - tmp32 |= ADC_TCTRL_HTEN_MASK; - } - - base->TCTRL[triggerId] = tmp32; -} - -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - - config->targetCommandId = 0U; - config->delayPower = 0U; - config->priority = 0U; - config->enableHardwareTrigger = false; -} - -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) -{ - assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ - assert(config != NULL); /* Check if the input pointer is available. */ - - uint32_t tmp32; - - commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ - - /* ADCx_CMDL. */ - tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - switch (config->sampleChannelMode) /* Sample input. */ - { - case kLPADC_SampleChannelSingleEndSideB: - tmp32 |= ADC_CMDL_ABSEL_MASK; - break; -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - case kLPADC_SampleChannelDiffBothSideAB: - tmp32 |= ADC_CMDL_DIFF_MASK; - break; - case kLPADC_SampleChannelDiffBothSideBA: - tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; - break; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ - default: /* kLPADC_SampleChannelSingleEndSideA. */ - break; - } - base->CMD[commandId].CMDL = tmp32; - - /* ADCx_CMDH. */ - tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ - | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ - | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ - | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ - | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ - if (config->enableAutoChannelIncrement) - { - tmp32 |= ADC_CMDH_LWI_MASK; - } - base->CMD[commandId].CMDH = tmp32; - - /* Hardware compare settings. - * Not all Command Buffers have an associated Compare Value register. The compare function is only available on - * Command Buffers that have a corresponding Compare Value register. - */ - if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) - { - /* Check if the hardware compare feature is available for indicated command buffer. */ - assert(commandId < ADC_CV_COUNT); - - /* Set CV register. */ - base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ - | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ - } -} - -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) -{ - assert(config != NULL); /* Check if the input pointer is available. */ - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - config->sampleScaleMode = kLPADC_SampleFullScale; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; - config->channelNumber = 0U; - config->chainedNextCommandNumber = 0U; /* No next command defined. */ - config->enableAutoChannelIncrement = false; - config->loopCount = 0U; - config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - config->sampleTimeMode = kLPADC_SampleTimeADCK3; - config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - config->hardwareCompareValueHigh = 0U; /* No used. */ - config->hardwareCompareValueLow = 0U; /* No used. */ -} - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -void LPADC_EnableCalibration(ADC_Type *base, bool enable) -{ - LPADC_Enable(base, false); - if (enable) - { - base->CFG |= ADC_CFG_CALOFS_MASK; - } - else - { - base->CFG &= ~ADC_CFG_CALOFS_MASK; - } - LPADC_Enable(base, true); -} - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -void LPADC_DoAutoCalibration(ADC_Type *base) -{ - assert(0u == LPADC_GetConvResultCount(base)); - - uint32_t mLpadcCMDL; - uint32_t mLpadcCMDH; - uint32_t mLpadcTrigger; - lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; - lpadc_conv_command_config_t mLpadcCommandConfigStruct; - lpadc_conv_result_t mLpadcResultConfigStruct; - - /* Enable the calibration function. */ - LPADC_EnableCalibration(base, true); - - /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ - mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ - mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ - mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ - - /* Set trigger0 configuration - for software trigger. */ - LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); - mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ - LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ - - /* Set conversion CMD configuration. */ - LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); - mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; - LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ - - /* Do calibration. */ - LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ - while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) - { - } - /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U); - /* Disable the calibration function. */ - LPADC_EnableCalibration(base, false); - - /* restore CMD and TRG registers. */ - base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ - base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ - base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.h deleted file mode 100644 index 7a136d5dd93a43ff53c8d443b1abd78872672dee..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpadc.h +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.0.0. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single end/differential, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -} lpadc_trigger_priority_policy_t; - -/*! - * @beief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to - #lpadc_trigger_priority_policy_mode_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ - -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} - -/* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @bool enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! -* @brief Do auto calibration. -* -* Calibration function should be executed before using converter in application. It used the software trigger and a -* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including: -* -LPADC_EnableCalibration(...) -* -LPADC_LPADC_SetOffsetValue(...) -* -LPADC_SetConvCommandConfig(...) -* -LPADC_SetConvTriggerConfig(...) -* -* @param base LPADC peripheral base address. -*/ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.c deleted file mode 100644 index a3e877246231d7795b4f293e0f5b889ca66470fe..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpcmp.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(LPCMP_CLOCKS) -/*! - * @brief Get instance number for LPCMP module. - * - * @param base LPCMP peripheral base address - */ -static uint32_t LPCMP_GetInstance(LPCMP_Type *base); -#endif /* LPCMP_CLOCKS */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if defined(LPCMP_CLOCKS) -/*! @brief Pointers to LPCMP bases for each instance. */ -static LPCMP_Type *const s_lpcmpBases[] = LPCMP_BASE_PTRS; -/*! @brief Pointers to LPCMP clocks for each instance. */ -static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS; -#endif /* LPCMP_CLOCKS */ - -/******************************************************************************* - * Codes - ******************************************************************************/ -#if defined(LPCMP_CLOCKS) -static uint32_t LPCMP_GetInstance(LPCMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpcmpBases); instance++) - { - if (s_lpcmpBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpcmpBases)); - - return instance; -} -#endif /* LPCMP_CLOCKS */ - -void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - -#if defined(LPCMP_CLOCKS) - /* Enable LPCMP clock. */ - CLOCK_EnableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); -#endif /* LPCMP_CLOCKS */ - - /* Configure. */ - LPCMP_Enable(base, false); - /* CCR0 register. */ - if (config->enableStopMode) - { - base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; - } - else - { - base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; - } - /* CCR1 register. */ - tmp32 = base->CCR1 & ~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK); - if (config->enableOutputPin) - { - tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; - } - if (config->useUnfilteredOutput) - { - tmp32 |= LPCMP_CCR1_COUT_SEL_MASK; - } - if (config->enableInvertOutput) - { - tmp32 |= LPCMP_CCR1_COUT_INV_MASK; - } - base->CCR1 = tmp32; - /* CCR2 register. */ - tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK); - tmp32 |= LPCMP_CCR2_HYSTCTR(config->hysteresisMode); - tmp32 |= ((uint32_t)(config->powerMode) << LPCMP_CCR2_CMP_HPMD_SHIFT); - base->CCR2 = tmp32; - - LPCMP_Enable(base, true); /* Enable the LPCMP module. */ -} - -void LPCMP_Deinit(LPCMP_Type *base) -{ - /* Disable the LPCMP module. */ - LPCMP_Enable(base, false); -#if defined(LPCMP_CLOCKS) - /* Disable the clock for LPCMP. */ - CLOCK_DisableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); -#endif /* LPCMP_CLOCKS */ -} - -void LPCMP_GetDefaultConfig(lpcmp_config_t *config) -{ - config->enableStopMode = false; - config->enableOutputPin = false; - config->useUnfilteredOutput = false; - config->enableInvertOutput = false; - config->hysteresisMode = kLPCMP_HysteresisLevel0; - config->powerMode = kLPCMP_LowSpeedPowerMode; -} - -void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) -{ - uint32_t tmp32; - - tmp32 = base->CCR2 & ~(LPCMP_CCR2_PSEL_MASK | LPCMP_CCR2_MSEL_MASK); - tmp32 |= LPCMP_CCR2_PSEL(positiveChannel) | LPCMP_CCR2_MSEL(negativeChannel); - base->CCR2 = tmp32; -} - -void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config) -{ - assert(config != NULL); - - uint32_t tmp32; - - tmp32 = base->CCR1 & ~(LPCMP_CCR1_FILT_PER_MASK | LPCMP_CCR1_FILT_CNT_MASK | LPCMP_CCR1_SAMPLE_EN_MASK); - if (config->enableSample) - { - tmp32 |= LPCMP_CCR1_SAMPLE_EN_MASK; - } - tmp32 |= LPCMP_CCR1_FILT_PER(config->filterSamplePeriod) | LPCMP_CCR1_FILT_CNT(config->filterSampleCount); - base->CCR1 = tmp32; -} - -void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config) -{ - uint32_t tmp32; - if (config == NULL) - { - tmp32 = 0U; /* Disable internal DAC. */ - } - else - { - tmp32 = LPCMP_DCR_VRSEL(config->referenceVoltageSource) | LPCMP_DCR_DAC_DATA(config->DACValue); - if (config->enableLowPowerMode) - { - tmp32 |= LPCMP_DCR_DAC_HPMD_MASK; - } - tmp32 |= LPCMP_DCR_DAC_EN_MASK; - } - base->DCR = tmp32; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.h deleted file mode 100644 index bfc41fab418764e1b3f3d89e6f474af808856e47..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpcmp.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_LPCMP_H_ -#define _FSL_LPCMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpcmp - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPCMP driver version 2.0.0. */ -#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! -* @brief LPCMP status falgs mask. -*/ -enum _lpcmp_status_flags -{ - kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. - The flag does not support W1C. */ -}; - -/*! -* @brief LPCMP interrupt enable/disable mask. -*/ -enum _lpcmp_interrupt_enable -{ - kLPCMP_OutputRisingInterruptEnable = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ - kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ -}; -/*! -* @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis -* value with each level -*/ -typedef enum _lpcmp_hysteresis_mode -{ - kLPCMP_HysteresisLevel0 = 0U, /*!< The hard block output has level 0 hysteresis internally. */ - kLPCMP_HysteresisLevel1 = 1U, /*!< The hard block output has level 1 hysteresis internally. */ - kLPCMP_HysteresisLevel2 = 2U, /*!< The hard block output has level 2 hysteresis internally. */ - kLPCMP_HysteresisLevel3 = 3U, /*!< The hard block output has level 3 hysteresis internally. */ -} lpcmp_hysteresis_mode_t; - -/*! -* @brief LPCMP nano mode. -*/ -typedef enum _lpcmp_power_mode -{ - kLPCMP_LowSpeedPowerMode = 0U, /*!< Low speed comparison mode is selected. */ - kLPCMP_HighSpeedPowerMode = 1U, /*!< High speed comparison mode is selected. */ - kLPCMP_NanoPowerMode = 2U, /*!< Nano power comparator is enabled. */ -} lpcmp_power_mode_t; - -/*! -* @brief Internal DAC reference voltage source. -*/ -typedef enum _lpcmp_dac_reference_voltage_source -{ - kLPCMP_VrefSourceVin1 = 0U, /*!< vrefh_int is selected as resistor ladder network supply reference Vin. */ - kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ -} lpcmp_dac_reference_voltage_source_t; - -/*! -* @brief Configure the filter. -*/ -typedef struct _lpcmp_filter_config -{ - bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ - uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ - uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The - sampling clock must be at least 4 times slower than the system clock to the comparator. - So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ -} lpcmp_filter_config_t; - -/*! -* @brief configure the internal DAC. -*/ -typedef struct _lpcmp_dac_config -{ - bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ - lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ -} lpcmp_dac_config_t; - -/*! -* @brief Configures the comparator. -*/ -typedef struct _lpcmp_config -{ - bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ - bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ - bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ - bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ - lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ - lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ -} lpcmp_config_t; -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! -* @brief Initialize the LPCMP -* -* This function initializes the LPCMP module. The operations included are: -* - Enabling the clock for LPCMP module. -* - Configuring the comparator. -* - Enabling the LPCMP module. -* Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for -* any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP. -* -* @param base LPCMP peripheral base address. -* @param config Pointer to "lpcmp_config_t" structure. -*/ -void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config); - -/*! - * @brief De-initializes the LPCMP module. - * - * This function de-initializes the LPCMP module. The operations included are: - * - Disabling the LPCMP module. - * - Disabling the clock for LPCMP module. - * - * This function disables the clock for the LPCMP. - * Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the - * clock for the LPCMP, ensure that all the LPCMP instances are not used. - * - * @param base LPCMP peripheral base address. - */ -void LPCMP_Deinit(LPCMP_Type *base); - -/*! -* @brief Gets an available pre-defined settings for the comparator's configuration. -* -* This function initializes the comparator configuration structure to these default values: -* @code -* config->enableStopMode = false; -* config->enableOutputPin = false; -* config->useUnfilteredOutput = false; -* config->enableInvertOutput = false; -* config->hysteresisMode = kLPCMP_HysteresisLevel0; -* config->powerMode = kLPCMP_LowSpeedPowerMode; -* @endcode -* @param config Pointer to "lpcmp_config_t" structure. -*/ -void LPCMP_GetDefaultConfig(lpcmp_config_t *config); - -/*! -* @brief Enable/Disable LPCMP module. -* -* @param base LPCMP peripheral base address. -* @param enable "true" means enable the module, and "false" means disable the module. -*/ -static inline void LPCMP_Enable(LPCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR0 |= LPCMP_CCR0_CMP_EN_MASK; - } - else - { - base->CCR0 &= ~LPCMP_CCR0_CMP_EN_MASK; - } -} - -/*! -* @brief Select the input channels for LPCMP. This function determines which input -* is selected for the negative and positive mux. -* -* @param base LPCMP peripheral base address. -* @param positiveChannel Positive side input channel number. Available range is 0-7. -* @param negativeChannel Negative side input channel number. Available range is 0-7. -*/ -void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel); - -/*! -* @brief Enables/disables the DMA request for rising/falling events. -* Normally, the LPCMP generates a CPU interrupt if there is a rising/falling event. When -* DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling -* event forces a DMA transfer request rather than a CPU interrupt instead. -* -* @param base LPCMP peripheral base address. -* @param enable "true" means enable DMA support, and "false" means disable DMA support. -*/ -static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= LPCMP_CCR1_DMA_EN_MASK; - } - else - { - base->CCR1 &= ~LPCMP_CCR1_DMA_EN_MASK; - } -} - -/*! -* @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by -* the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. -* The optionally inverted comparator output COUT_RAW is sampled on every bus clock -* when WINDOW=1 to generate COUTA. -* -* @param base LPCMP peripheral base address. -* @param enable "true" means enable window mode, and "false" means disable window mode. -*/ -static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) -{ - if (enable) - { - base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; - } - else - { - base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; - } -} - -/*! -* @brief Configures the filter. -* -* @param base LPCMP peripheral base address. -* @param config Pointer to "lpcmp_filter_config_t" structure. -*/ -void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config); - -/*! -* @brief Configure the internal DAC module. -* -* @param base LPCMP peripheral base address. -* @param config Pointer to "lpcmp_dac_config_t" structure. If config is "NULL", disable internal DAC. -*/ -void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config); - -/*! -* @brief Enable the interrupts. -* -* @param base LPCMP peripheral base address. -* @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". -*/ -static inline void LPCMP_EnableInterrupts(LPCMP_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! -* @brief Disable the interrupts. -* -* @param base LPCMP peripheral base address. -* @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". -*/ -static inline void LPCMP_DisableInterrupts(LPCMP_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! -* @brief Get the LPCMP status flags. -* -* @param LPCMP peripheral base address. -* -* @return Mask value for the asserted flags. See "_lpcmp_status_flags". -*/ -static inline uint32_t LPCMP_GetStatusFlags(LPCMP_Type *base) -{ - return base->CSR; -} - -/*! -* @brief Clear the LPCMP status flags -* -* @param base LPCMP peripheral base address. -* @param mask Mask value for the flags. See "_lpcmp_status_flags". -*/ -static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) -{ - base->CSR = mask; -} - -#endif /* _FSL_LPCMP_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.c deleted file mode 100644 index 31fd90aacc71123254388fb2987c59e3ee33ffa9..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.c +++ /dev/null @@ -1,1672 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpi2c.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Common sets of flags used by the driver. */ -enum _lpi2c_flag_constants -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | - kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterDataMatchFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | - kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterFifoErrFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | - kLPI2C_MasterPinLowTimeoutFlag, - - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveFifoErrFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | - kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, -}; - -/* ! @brief LPI2C master fifo commands. */ -enum _lpi2c_master_fifo_cmd -{ - kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ - kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ -}; - -/*! - * @brief Default watermark values. - * - * The default watermarks are set to zero. - */ -enum _lpi2c_default_watermarks -{ - kDefaultTxWatermark = 0, - kDefaultRxWatermark = 0, -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _lpi2c_transfer_states -{ - kIdleState = 0, - kSendCommandState, - kIssueReadCommandState, - kTransferDataState, - kStopState, - kWaitForCompletionState, -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -uint32_t LPI2C_GetInstance(LPI2C_Type *base); - -static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, - uint32_t width_ns, - uint32_t maxCycles, - uint32_t prescaler); - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); - -static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); - -static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); - -static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); - -static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); - -static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map LPI2C instance number to base pointer. */ -static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; - -/*! @brief Array to map LPI2C instance number to IRQ number. */ -static IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map LPI2C instance number to clock gate enum. */ -static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; - -#if defined(LPI2C_PERIPH_CLOCKS) -/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ -static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointer to master IRQ handler for each instance. */ -static lpi2c_master_isr_t s_lpi2cMasterIsr; - -/*! @brief Pointers to master handles for each instance. */ -static lpi2c_master_handle_t *s_lpi2cMasterHandle[FSL_FEATURE_SOC_LPI2C_COUNT]; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static lpi2c_slave_isr_t s_lpi2cSlaveIsr; - -/*! @brief Pointers to slave handles for each instance. */ -static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[FSL_FEATURE_SOC_LPI2C_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The LPI2C peripheral base address. - * @return LPI2C instance number starting from 0. - */ -uint32_t LPI2C_GetInstance(LPI2C_Type *base) -{ - uint32_t instance; - for (instance = 0; instance < ARRAY_SIZE(kLpi2cBases); ++instance) - { - if (kLpi2cBases[instance] == base) - { - return instance; - } - } - - assert(false); - return 0; -} - -/*! - * @brief Computes a cycle count for a given time in nanoseconds. - * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. - * @param width_ns Desired with in nanoseconds. - * @param maxCycles Maximum cycle count, determined by the number of bits wide the cycle count field is. - * @param prescaler LPI2C prescaler setting. Pass 1 if the prescaler should not be used, as for slave glitch widths. - */ -static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, - uint32_t width_ns, - uint32_t maxCycles, - uint32_t prescaler) -{ - uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); - uint32_t cycles = 0; - - /* Search for the cycle count just below the desired glitch width. */ - while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles)) - { - ++cycles; - } - - /* If we end up with zero cycles, then set the filter to a single cycle unless the */ - /* bus clock is greater than 10x the desired glitch width. */ - if ((cycles == 0) && (busCycle_ns <= (width_ns * 10))) - { - cycles = 1; - } - - return cycles; -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The LPI2C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. These errors cause a stop to automatically be sent. We must */ - /* clear the errors before a new transfer can start. */ - status &= kMasterErrorFlags; - if (status) - { - /* Select the correct error code. Ordered by severity, with bus issues first. */ - if (status & kLPI2C_MasterPinLowTimeoutFlag) - { - result = kStatus_LPI2C_PinLowTimeout; - } - else if (status & kLPI2C_MasterArbitrationLostFlag) - { - result = kStatus_LPI2C_ArbitrationLost; - } - else if (status & kLPI2C_MasterNackDetectFlag) - { - result = kStatus_LPI2C_Nak; - } - else if (status & kLPI2C_MasterFifoErrFlag) - { - result = kStatus_LPI2C_FifoError; - } - else - { - assert(false); - } - - /* Clear the flags. */ - LPI2C_MasterClearStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - } - - return result; -} - -/*! - * @brief Wait until there is room in the tx fifo. - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) -{ - uint32_t status; - size_t txCount; - size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); - do - { - status_t result; - - /* Get the number of words in the tx fifo and compute empty slots. */ - LPI2C_MasterGetFifoCounts(base, NULL, &txCount); - txCount = txFifoSize - txCount; - - /* Check for error flags. */ - status = LPI2C_MasterGetStatusFlags(base); - result = LPI2C_MasterCheckAndClearError(base, status); - if (result) - { - return result; - } - } while (!txCount); - - return kStatus_Success; -} - -/*! - * @brief Make sure the bus isn't already busy. - * - * A busy bus is allowed if we are the one driving it. - * - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_Busy - */ -status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) -{ - uint32_t status = LPI2C_MasterGetStatusFlags(base); - if ((status & kLPI2C_MasterBusBusyFlag) && (!(status & kLPI2C_MasterBusyFlag))) - { - return kStatus_LPI2C_Busy; - } - - return kStatus_Success; -} - -void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) -{ - masterConfig->enableMaster = true; - masterConfig->debugEnable = false; - masterConfig->enableDoze = true; - masterConfig->ignoreAck = false; - masterConfig->pinConfig = kLPI2C_2PinOpenDrain; - masterConfig->baudRate_Hz = 100000U; - masterConfig->busIdleTimeout_ns = 0; - masterConfig->pinLowTimeout_ns = 0; - masterConfig->sdaGlitchFilterWidth_ns = 0; - masterConfig->sclGlitchFilterWidth_ns = 0; - masterConfig->hostRequest.enable = false; - masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; - masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; -} - -void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) -{ - uint32_t prescaler; - uint32_t cycles; - uint32_t cfgr2; - uint32_t value; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Ungate the functional clock in initialize function. */ - CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset peripheral before configuring it. */ - LPI2C_MasterReset(base); - - /* Doze bit: 0 is enable, 1 is disable */ - base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); - - /* host request */ - value = base->MCFGR0; - value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); - value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | - LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | - LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); - base->MCFGR0 = value; - - /* pin config and ignore ack */ - value = base->MCFGR1; - value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); - value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); - value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); - base->MCFGR1 = value; - - LPI2C_MasterSetWatermarks(base, kDefaultTxWatermark, kDefaultRxWatermark); - - LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); - - /* Configure glitch filters and bus idle and pin low timeouts. */ - prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; - cfgr2 = base->MCFGR2; - if (masterConfig->busIdleTimeout_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, - (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); - cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; - cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); - } - if (masterConfig->sdaGlitchFilterWidth_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, - (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 1); - cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; - cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); - } - if (masterConfig->sclGlitchFilterWidth_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, - (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 1); - cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; - cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); - } - base->MCFGR2 = cfgr2; - if (masterConfig->pinLowTimeout_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, - (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); - base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); - } - - LPI2C_MasterEnable(base, masterConfig->enableMaster); -} - -void LPI2C_MasterDeinit(LPI2C_Type *base) -{ - /* Restore to reset state. */ - LPI2C_MasterReset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Gate clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Gate the functional clock. */ - CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) -{ - /* Disable master mode. */ - bool wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; - LPI2C_MasterEnable(base, false); - - base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); - base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); - base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); - - /* Restore master mode. */ - if (wasEnabled) - { - LPI2C_MasterEnable(base, true); - } -} - -void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) -{ - uint32_t prescale = 0; - uint32_t bestPre = 0; - uint32_t bestClkHi = 0; - uint32_t absError = 0; - uint32_t bestError = 0xffffffffu; - uint32_t value; - uint32_t clkHiCycle; - uint32_t computedRate; - int i; - bool wasEnabled; - - /* Disable master mode. */ - wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; - LPI2C_MasterEnable(base, false); - - /* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */ - /* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */ - for (prescale = 1; (prescale <= 128) && (bestError != 0); prescale = 2 * prescale) - { - for (clkHiCycle = 1; clkHiCycle < 32; clkHiCycle++) - { - if (clkHiCycle == 1) - { - computedRate = (sourceClock_Hz / prescale) / (1 + 3 + 2 + 2 / prescale); - } - else - { - computedRate = (sourceClock_Hz / prescale) / (3 * clkHiCycle + 2 + 2 / prescale); - } - - absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; - - if (absError < bestError) - { - bestPre = prescale; - bestClkHi = clkHiCycle; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Standard, fast, fast mode plus and ultra-fast transfers. */ - value = LPI2C_MCCR0_CLKHI(bestClkHi); - - if (bestClkHi < 2) - { - value |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); - } - else - { - value |= LPI2C_MCCR0_CLKLO(2 * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2); - } - - base->MCCR0 = value; - - for (i = 0; i < 8; i++) - { - if (bestPre == (1U << i)) - { - bestPre = i; - break; - } - } - base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); - - /* Restore master mode. */ - if (wasEnabled) - { - LPI2C_MasterEnable(base, true); - } -} - -status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) -{ - /* Return an error if the bus is already in use not by us. */ - status_t result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Turn off auto-stop option. */ - base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; - - /* Wait until there is room in the fifo. */ - result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Issue start command. */ - base->MTDR = kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); - - return kStatus_Success; -} - -status_t LPI2C_MasterStop(LPI2C_Type *base) -{ - /* Wait until there is room in the fifo. */ - status_t result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Send the STOP signal */ - base->MTDR = kStopCmd; - - /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ - /* Also check for errors while waiting. */ - while (result == kStatus_Success) - { - uint32_t status = LPI2C_MasterGetStatusFlags(base); - - /* Check for error flags. */ - result = LPI2C_MasterCheckAndClearError(base, status); - - /* Check if the stop was sent successfully. */ - if (status & kLPI2C_MasterStopDetectFlag) - { - LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag); - break; - } - } - - return result; -} - -status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) -{ - status_t result; - uint8_t *buf; - - assert(rxBuff); - - /* Handle empty read. */ - if (!rxSize) - { - return kStatus_Success; - } - - /* Wait until there is room in the command fifo. */ - result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Issue command to receive data. */ - base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(rxSize - 1); - - /* Receive data */ - buf = (uint8_t *)rxBuff; - while (rxSize--) - { - /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ - /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ - /* using a single register read. */ - uint32_t value; - do - { - /* Check for errors. */ - result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); - if (result) - { - return result; - } - - value = base->MRDR; - } while (value & LPI2C_MRDR_RXEMPTY_MASK); - - *buf++ = value & LPI2C_MRDR_DATA_MASK; - } - - return kStatus_Success; -} - -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) -{ - uint8_t *buf = (uint8_t *)((void *)txBuff); - - assert(txBuff); - - /* Send data buffer */ - while (txSize--) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - status_t result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Write byte into LPI2C master data register. */ - base->MTDR = *buf++; - } - - return kStatus_Success; -} - -void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = LPI2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_lpi2cMasterHandle[instance] = handle; - - /* Set irq handler. */ - s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - EnableIRQ(kLpi2cIrqs[instance]); -} - -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - status_t result = kStatus_Success; - lpi2c_master_transfer_t *xfer; - size_t txCount; - size_t rxCount; - size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); - bool state_complete = false; - - /* Set default isDone return value. */ - *isDone = false; - - /* Check for errors. */ - status = LPI2C_MasterGetStatusFlags(base); - result = LPI2C_MasterCheckAndClearError(base, status); - if (result) - { - return result; - } - - /* Get pointer to private data. */ - xfer = &handle->transfer; - - /* Get fifo counts and compute room in tx fifo. */ - LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); - txCount = txFifoSize - txCount; - - while (!state_complete) - { - /* Execute the state. */ - switch (handle->state) - { - case kSendCommandState: - { - /* Make sure there is room in the tx fifo for the next command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ - base->MTDR = *(uint16_t *)handle->buf; - handle->buf += sizeof(uint16_t); - - /* Count down until all commands are sent. */ - if (--handle->remainingBytes == 0) - { - /* Choose next state and set up buffer pointer and count. */ - if (xfer->dataSize) - { - /* Either a send or receive transfer is next. */ - handle->state = kTransferDataState; - handle->buf = (uint8_t *)xfer->data; - handle->remainingBytes = xfer->dataSize; - if (xfer->direction == kLPI2C_Read) - { - /* Disable TX interrupt */ - LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); - } - } - else - { - /* No transfer, so move to stop state. */ - handle->state = kStopState; - } - } - break; - } - - case kIssueReadCommandState: - /* Make sure there is room in the tx fifo for the read command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - - /* Move to transfer state. */ - handle->state = kTransferDataState; - if (xfer->direction == kLPI2C_Read) - { - /* Disable TX interrupt */ - LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); - } - break; - - case kTransferDataState: - if (xfer->direction == kLPI2C_Write) - { - /* Make sure there is room in the tx fifo. */ - if (!txCount--) - { - state_complete = true; - break; - } - - /* Put byte to send in fifo. */ - base->MTDR = *(handle->buf)++; - } - else - { - /* XXX handle receive sizes > 256, use kIssueReadCommandState */ - /* Make sure there is data in the rx fifo. */ - if (!rxCount--) - { - state_complete = true; - break; - } - - /* Read byte from fifo. */ - *(handle->buf)++ = base->MRDR & LPI2C_MRDR_DATA_MASK; - } - - /* Move to stop when the transfer is done. */ - if (--handle->remainingBytes == 0) - { - handle->state = kStopState; - } - break; - - case kStopState: - /* Only issue a stop transition if the caller requested it. */ - if ((xfer->flags & kLPI2C_TransferNoStopFlag) == 0) - { - /* Make sure there is room in the tx fifo for the stop command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - base->MTDR = kStopCmd; - } - else - { - /* Caller doesn't want to send a stop, so we're done now. */ - *isDone = true; - state_complete = true; - break; - } - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - /* We stay in this state until the stop state is detected. */ - if (status & kLPI2C_MasterStopDetectFlag) - { - *isDone = true; - } - state_complete = true; - break; - default: - assert(false); - break; - } - } - return result; -} - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ -static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) -{ - lpi2c_master_transfer_t *xfer = &handle->transfer; - - /* Handle no start option. */ - if (xfer->flags & kLPI2C_TransferNoStartFlag) - { - if (xfer->direction == kLPI2C_Read) - { - /* Need to issue read command first. */ - handle->state = kIssueReadCommandState; - } - else - { - /* Start immediately in the data transfer state. */ - handle->state = kTransferDataState; - } - - handle->buf = (uint8_t *)xfer->data; - handle->remainingBytes = xfer->dataSize; - } - else - { - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; - uint32_t cmdCount = 0; - - /* Initial direction depends on whether a subaddress was provided, and of course the actual */ - /* data transfer direction. */ - lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; - - /* Start command. */ - cmd[cmdCount++] = - (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); - - /* Subaddress, MSB first. */ - if (xfer->subaddressSize) - { - uint32_t subaddressRemaining = xfer->subaddressSize; - while (subaddressRemaining--) - { - uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; - } - } - - /* Reads need special handling. */ - if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) - { - /* Need to send repeated start if switching directions to read. */ - if (direction == kLPI2C_Write) - { - cmd[cmdCount++] = (uint16_t)kStartCmd | - (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); - } - - /* Read command. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - - /* Set up state machine for transferring the commands. */ - handle->state = kSendCommandState; - handle->remainingBytes = cmdCount; - handle->buf = (uint8_t *)&handle->commandBuffer; - } -} - -status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_t *transfer) -{ - status_t result; - - assert(handle); - assert(transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Save transfer into handle. */ - handle->transfer = *transfer; - - /* Generate commands to send. */ - LPI2C_InitTransferStateMachine(handle); - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Turn off auto-stop option. */ - base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; - - /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_MasterEnableInterrupts(base, kMasterIrqFlags); - - return result; -} - -status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - uint8_t state; - uint16_t remainingBytes; - uint32_t dataSize; - - /* Cache some fields with IRQs disabled. This ensures all field values */ - /* are synchronized with each other during an ongoing transfer. */ - uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); - LPI2C_MasterDisableInterrupts(base, irqs); - state = handle->state; - remainingBytes = handle->remainingBytes; - dataSize = handle->transfer.dataSize; - LPI2C_MasterEnableInterrupts(base, irqs); - - /* Get transfer count based on current transfer state. */ - switch (state) - { - case kIdleState: - case kSendCommandState: - case kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ - *count = 0; - break; - - case kTransferDataState: - *count = dataSize - remainingBytes; - break; - - case kStopState: - case kWaitForCompletionState: - default: - *count = dataSize; - break; - } - - return kStatus_Success; -} - -void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) -{ - if (handle->state != kIdleState) - { - /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Reset fifos. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - - /* Send a stop command to finalize the transfer. */ - base->MTDR = kStopCmd; - - /* Reset handle. */ - handle->state = kIdleState; - } -} - -void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - if (handle->state == kIdleState) - { - return; - } - - result = LPI2C_RunTransferStateMachine(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* XXX need to handle data that may be in rx fifo below watermark level? */ - - /* XXX handle error, terminate xfer */ - - /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Set handle to idle state. */ - handle->state = kIdleState; - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) -{ - slaveConfig->enableSlave = true; - slaveConfig->address0 = 0U; - slaveConfig->address1 = 0U; - slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; - slaveConfig->filterDozeEnable = true; - slaveConfig->filterEnable = true; - slaveConfig->enableGeneralCall = false; - slaveConfig->sclStall.enableAck = false; - slaveConfig->sclStall.enableTx = true; - slaveConfig->sclStall.enableRx = true; - slaveConfig->sclStall.enableAddress = false; - slaveConfig->ignoreAck = false; - slaveConfig->enableReceivedAddressRead = false; - slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ - slaveConfig->sclGlitchFilterWidth_ns = 0; - slaveConfig->dataValidDelay_ns = 0; - slaveConfig->clockHoldTime_ns = 0; -} - -void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Ungate the functional clock in initialize function. */ - CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Restore to reset conditions. */ - LPI2C_SlaveReset(base); - - /* Configure peripheral. */ - base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); - - base->SCFGR1 = - LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | - LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | - LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | - LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | - LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); - - base->SCFGR2 = - LPI2C_SCFGR2_FILTSDA(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, - (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT), 1)) | - LPI2C_SCFGR2_FILTSCL(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, - (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT), 1)) | - LPI2C_SCFGR2_DATAVD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, - (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 1)) | - LPI2C_SCFGR2_CLKHOLD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, - (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT), 1)); - - /* Save SCR to last so we don't enable slave until it is configured */ - base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | - LPI2C_SCR_SEN(slaveConfig->enableSlave); -} - -void LPI2C_SlaveDeinit(LPI2C_Type *base) -{ - LPI2C_SlaveReset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Gate the clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); - -#if defined(LPI2C_PERIPH_CLOCKS) - /* Gate the functional clock. */ - CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The LPI2C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_BitError - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) -{ - status_t result = kStatus_Success; - - flags &= kSlaveErrorFlags; - if (flags) - { - if (flags & kLPI2C_SlaveBitErrFlag) - { - result = kStatus_LPI2C_BitError; - } - else if (flags & kLPI2C_SlaveFifoErrFlag) - { - result = kStatus_LPI2C_FifoError; - } - else - { - assert(false); - } - - /* Clear the errors. */ - LPI2C_SlaveClearStatusFlags(base, flags); - } - - return result; -} - -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize) -{ - uint8_t *buf = (uint8_t *)((void *)txBuff); - size_t remaining = txSize; - - assert(txBuff); - - while (remaining) - { - uint32_t flags; - status_t result; - - /* Wait until we can transmit. */ - do - { - /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); - result = LPI2C_SlaveCheckAndClearError(base, flags); - if (result) - { - if (actualTxSize) - { - *actualTxSize = txSize - remaining; - } - return result; - } - } while ( - !(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); - - /* Send a byte. */ - if (flags & kLPI2C_SlaveTxReadyFlag) - { - base->STDR = *buf++; - --remaining; - } - - /* Exit loop if we see a stop or restart */ - if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) - { - LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); - break; - } - } - - if (actualTxSize) - { - *actualTxSize = txSize - remaining; - } - - return kStatus_Success; -} - -status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) -{ - uint8_t *buf = (uint8_t *)rxBuff; - size_t remaining = rxSize; - - assert(rxBuff); - - while (remaining) - { - uint32_t flags; - status_t result; - - /* Wait until we can receive. */ - do - { - /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); - result = LPI2C_SlaveCheckAndClearError(base, flags); - if (result) - { - if (actualRxSize) - { - *actualRxSize = rxSize - remaining; - } - return result; - } - } while ( - !(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); - - /* Receive a byte. */ - if (flags & kLPI2C_SlaveRxReadyFlag) - { - *buf++ = base->SRDR & LPI2C_SRDR_DATA_MASK; - --remaining; - } - - /* Exit loop if we see a stop or restart */ - if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) - { - LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); - break; - } - } - - if (actualRxSize) - { - *actualRxSize = rxSize - remaining; - } - - return kStatus_Success; -} - -void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, - lpi2c_slave_handle_t *handle, - lpi2c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = LPI2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_lpi2cSlaveHandle[instance] = handle; - - /* Set irq handler. */ - s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - EnableIRQ(kLpi2cIrqs[instance]); - - /* Nack by default. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; -} - -status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) -{ - uint32_t status; - - assert(handle); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - status = LPI2C_SlaveGetStatusFlags(base); - if ((status & kLPI2C_SlaveBusBusyFlag) && (!(status & kLPI2C_SlaveBusyFlag))) - { - return kStatus_LPI2C_Busy; - } - - /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - - /* Clear transfer in handle. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Record that we're busy. */ - handle->isBusy = true; - - /* Set up event mask. tx and rx are always enabled. */ - handle->eventMask = eventMask | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent; - - /* Ack by default. */ - base->STAR = 0; - - /* Clear all flags. */ - LPI2C_SlaveClearStatusFlags(base, kSlaveClearFlags); - - /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_SlaveEnableInterrupts(base, kSlaveIrqFlags); - - return kStatus_Success; -} - -status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transferredCount; - - return kStatus_Success; -} - -void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) -{ - assert(handle); - - /* Return idle if no transaction is in progress. */ - if (handle->isBusy) - { - /* Disable LPI2C IRQ sources. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - - /* Nack by default. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; - - /* Reset transfer info. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* We're no longer busy. */ - handle->isBusy = false; - } -} - -void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) -{ - uint32_t flags; - lpi2c_slave_transfer_t *xfer; - - /* Check for a valid handle in case of a spurious interrupt. */ - if (!handle) - { - return; - } - - xfer = &handle->transfer; - - /* Get status flags. */ - flags = LPI2C_SlaveGetStatusFlags(base); - - if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag)) - { - xfer->event = kLPI2C_SlaveCompletionEvent; - xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); - - if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - return; - } - if (flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)) - { - xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent : - kLPI2C_SlaveCompletionEvent; - xfer->receivedAddress = 0; - xfer->completionStatus = kStatus_Success; - xfer->transferredCount = handle->transferredCount; - - if (xfer->event == kLPI2C_SlaveCompletionEvent) - { - handle->isBusy = false; - } - - if (handle->wasTransmit) - { - /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ - /* tx flag before it sees the nack from the master-receiver, thus causing one more */ - /* count that the master actually receives. */ - --xfer->transferredCount; - handle->wasTransmit = false; - } - - /* Clear the flag. */ - LPI2C_SlaveClearStatusFlags(base, flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)); - - /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ - base->STAR = 0; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clean up transfer info on completion, after the callback has been invoked. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - } - if (flags & kLPI2C_SlaveAddressValidFlag) - { - xfer->event = kLPI2C_SlaveAddressMatchEvent; - xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK; - - if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - if (flags & kLPI2C_SlaveTransmitAckFlag) - { - xfer->event = kLPI2C_SlaveTransmitAckEvent; - - if ((handle->eventMask & kLPI2C_SlaveTransmitAckEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - /* Handle transmit and receive. */ - if (flags & kLPI2C_SlaveTxReadyFlag) - { - handle->wasTransmit = true; - - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kLPI2C_SlaveTransmitEvent; - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - handle->transferredCount = 0; - } - - /* Transmit a byte. */ - if ((xfer->data) && (xfer->dataSize)) - { - base->STDR = *xfer->data++; - --xfer->dataSize; - ++handle->transferredCount; - } - } - if (flags & kLPI2C_SlaveRxReadyFlag) - { - /* If we're out of room in the buffer, invoke callback to get another. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kLPI2C_SlaveReceiveEvent; - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - handle->transferredCount = 0; - } - - /* Receive a byte. */ - if ((xfer->data) && (xfer->dataSize)) - { - *xfer->data++ = base->SRDR; - --xfer->dataSize; - ++handle->transferredCount; - } - else - { - /* We don't have any room to receive more data, so send a nack. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; - } - } -} - -/*! - * @brief Shared IRQ handler that can call both master and slave ISRs. - * - * The master and slave ISRs are called through function pointers in order to decouple - * this code from the ISR functions. Without this, the linker would always pull in both - * ISRs and every function they call, even if only the functional API was used. - * - * @param base The LPI2C peripheral base address. - * @param instance The LPI2C peripheral instance number. - */ -static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) -{ - /* Check for master IRQ. */ - if ((base->MCR & LPI2C_MCR_MEN_MASK) && s_lpi2cMasterIsr) - { - /* Master mode. */ - s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]); - } - - /* Check for slave IRQ. */ - if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr) - { - /* Slave mode. */ - s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]); - } -} - -#if defined(LPI2C0) -/* Implementation of LPI2C0 handler named in startup code. */ -void LPI2C0_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C0, 0); -} -#endif - -#if defined(LPI2C1) -/* Implementation of LPI2C1 handler named in startup code. */ -void LPI2C1_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C1, 1); -} -#endif - -#if defined(LPI2C2) -/* Implementation of LPI2C2 handler named in startup code. */ -void LPI2C2_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C2, 2); -} -#endif - -#if defined(LPI2C3) -/* Implementation of LPI2C3 handler named in startup code. */ -void LPI2C3_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C3, 3); -} -#endif - -#if defined(CM4_0_LPI2C) -/* Implementation of CM4_0_LPI2C handler named in startup code. */ -void M4_0_LPI2C_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(CM4_0_LPI2C, LPI2C_GetInstance(CM4_0_LPI2C)); -} -#endif - -#if defined(CM4_1_LPI2C) -/* Implementation of CM4_1_LPI2C handler named in startup code. */ -void M4_1_LPI2C_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(CM4_1_LPI2C, LPI2C_GetInstance(CM4_1_LPI2C)); -} -#endif - -#if defined(DMA_LPI2C0) -/* Implementation of DMA_LPI2C0 handler named in startup code. */ -void DMA_I2C0_INT_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA_LPI2C0, LPI2C_GetInstance(DMA_LPI2C0)); -} -#endif - -#if defined(DMA_LPI2C1) -/* Implementation of DMA_LPI2C1 handler named in startup code. */ -void DMA_I2C1_INT_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA_LPI2C1, LPI2C_GetInstance(DMA_LPI2C1)); -} -#endif - -#if defined(DMA_LPI2C2) -/* Implementation of DMA_LPI2C2 handler named in startup code. */ -void DMA_I2C2_INT_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA_LPI2C2, LPI2C_GetInstance(DMA_LPI2C2)); -} -#endif - -#if defined(DMA_LPI2C3) -/* Implementation of DMA_LPI2C3 handler named in startup code. */ -void DMA_I2C3_INT_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA_LPI2C3, LPI2C_GetInstance(DMA_LPI2C3)); -} -#endif - -#if defined(DMA_LPI2C4) -/* Implementation of DMA_LPI2C3 handler named in startup code. */ -void DMA_I2C4_INT_IRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA_LPI2C4, LPI2C_GetInstance(DMA_LPI2C4)); -} -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.h deleted file mode 100644 index 616646b4aae44cb552f521d3f970800508a7c3ed..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c.h +++ /dev/null @@ -1,1225 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPI2C_H_ -#define _FSL_LPI2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup lpi2c - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPI2C driver version 2.1.2. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) -/*@}*/ - -/*! @brief LPI2C status return codes. */ -enum _lpi2c_status -{ - kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ - kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ - kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ - kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ - kStatus_LPI2C_PinLowTimeout = - MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ - kStatus_LPI2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< DMA request failed. */ -}; - -/*! @} */ - -/*! - * @addtogroup lpi2c_master_driver - * @{ - */ - -/*! - * @brief LPI2C master peripheral flags. - * - * The following status register flags can be cleared: - * - #kLPI2C_MasterEndOfPacketFlag - * - #kLPI2C_MasterStopDetectFlag - * - #kLPI2C_MasterNackDetectFlag - * - #kLPI2C_MasterArbitrationLostFlag - * - #kLPI2C_MasterFifoErrFlag - * - #kLPI2C_MasterPinLowTimeoutFlag - * - #kLPI2C_MasterDataMatchFlag - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _lpi2c_master_flags -{ - kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ - kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ - kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ - kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ - kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ - kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ - kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ -}; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _lpi2c_direction -{ - kLPI2C_Write = 0U, /*!< Master transmit. */ - kLPI2C_Read = 1U /*!< Master receive. */ -} lpi2c_direction_t; - -/*! @brief LPI2C pin configuration. */ -typedef enum _lpi2c_master_pin_config -{ - kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ - kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ - kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ - kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ - kLPI2C_2PinOpenDrainWithSeparateSlave = - 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ - kLPI2C_2PinOutputOnlyWithSeparateSlave = - 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ - kLPI2C_2PinPushPullWithSeparateSlave = - 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ - kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ -} lpi2c_master_pin_config_t; - -/*! @brief LPI2C master host request selection. */ -typedef enum _lpi2c_host_request_source -{ - kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ - kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ -} lpi2c_host_request_source_t; - -/*! @brief LPI2C master host request pin polarity configuration. */ -typedef enum _lpi2c_host_request_polarity -{ - kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ - kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ -} lpi2c_host_request_polarity_t; - -/*! - * @brief Structure with settings to initialize the LPI2C master module. - * - * This structure holds configuration settings for the LPI2C peripheral. To initialize this - * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _lpi2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - bool enableDoze; /*!< Whether master is enabled in doze mode. */ - bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ - bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ - lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ - uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ - uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ - uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ - uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ - uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ - struct - { - bool enable; /*!< Enable host request. */ - lpi2c_host_request_source_t source; /*!< Host request source. */ - lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ - } hostRequest; /*!< Host request options. */ -} lpi2c_master_config_t; - -/*! @brief LPI2C master data match configuration modes. */ -typedef enum _lpi2c_data_match_config_mode -{ - kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ - kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ - kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ - kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = - 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ - kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = - 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ - kLPI2C_1stWordAndM1EqualsM0AndM1 = - 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ - kLPI2C_AnyWordAndM1EqualsM0AndM1 = - 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ -} lpi2c_data_match_config_mode_t; - -/*! @brief LPI2C master data match configuration structure. */ -typedef struct _lpi2c_match_config -{ - lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ - bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ - uint32_t match0; /*!< Match value 0. */ - uint32_t match1; /*!< Match value 1. */ -} lpi2c_data_match_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; -typedef struct _lpi2c_master_handle lpi2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to LPI2C_MasterTransferCreateHandle(). - * - * @param base The LPI2C peripheral base address. - * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_lpi2c_master_transfer::flags field. - */ -enum _lpi2c_master_transfer_flags -{ - kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. - */ -struct _lpi2c_master_transfer -{ - uint32_t - flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for available - options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ - lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint16_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ - lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup lpi2c_slave_driver - * @{ - */ - -/*! - * @brief LPI2C slave peripheral flags. - * - * The following status register flags can be cleared: - * - #kLPI2C_SlaveRepeatedStartDetectFlag - * - #kLPI2C_SlaveStopDetectFlag - * - #kLPI2C_SlaveBitErrFlag - * - #kLPI2C_SlaveFifoErrFlag - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @note These enumerations are meant to be OR'd together to form a bit mask. - */ -enum _lpi2c_slave_flags -{ - kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ - kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ - kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ - kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ - kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ - kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ - kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ - kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ - kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ -}; - -/*! @brief LPI2C slave address match options. */ -typedef enum _lpi2c_slave_address_match -{ - kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ - kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ - kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ -} lpi2c_slave_address_match_t; - -/*! - * @brief Structure with settings to initialize the LPI2C slave module. - * - * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this - * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _lpi2c_slave_config -{ - bool enableSlave; /*!< Enable slave mode. */ - uint8_t address0; /*!< Slave's 7-bit address. */ - uint8_t address1; /*!< Alternate slave 7-bit address. */ - lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ - bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ - bool filterEnable; /*!< Enable digital glitch filter. */ - bool enableGeneralCall; /*!< Enable general call address matching. */ - struct - { - bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) - and slave-receiver address and data byte(s) to allow software to - write the Transmit ACK Register before the ACK or NACK is transmitted. - Clock stretching occurs when transmitting the 9th bit. When - enableAckSCLStall is enabled, there is no need to set either - enableRxDataSCLStall or enableAddressSCLStall. */ - bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set - during a slave-transmit transfer. */ - bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during - a slave-receive transfer. */ - bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ - } sclStall; - bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ - bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ - uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ - uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ - uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ - uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ -} lpi2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _lpi2c_slave_transfer_event -{ - kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ - kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ - kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ - - /*! Bit mask of all available events. */ - kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | - kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, -} lpi2c_slave_transfer_event_t; - -/*! @brief LPI2C slave transfer structure */ -typedef struct _lpi2c_slave_transfer -{ - lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. */ - uint8_t *data; /*!< Transfer buffer */ - size_t dataSize; /*!< Transfer size */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kLPI2C_SlaveCompletionEvent. */ - size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ -} lpi2c_slave_transfer_t; - -/* Forward declaration. */ -typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the LPI2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the LPI2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief LPI2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_slave_handle -{ - lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ - bool isBusy; /*!< Whether transfer is busy. */ - bool wasTransmit; /*!< Whether the last transfer was a transmit. */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint32_t transferredCount; /*!< Count of bytes transferred. */ - lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup lpi2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the LPI2C master peripheral. - * - * This function provides the following default configuration for the LPI2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->debugEnable = false; - * masterConfig->ignoreAck = false; - * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; - * masterConfig->baudRate_Hz = 100000U; - * masterConfig->busIdleTimeout_ns = 0; - * masterConfig->pinLowTimeout_ns = 0; - * masterConfig->sdaGlitchFilterWidth_ns = 0; - * masterConfig->sclGlitchFilterWidth_ns = 0; - * masterConfig->hostRequest.enable = false; - * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; - * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with LPI2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. - */ -void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the LPI2C master peripheral. - * - * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The LPI2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); - -/*! -* @brief Deinitializes the LPI2C master peripheral. -* - * This function disables the LPI2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -void LPI2C_MasterDeinit(LPI2C_Type *base); - -/*! - * @brief Configures LPI2C master data match feature. - * - * @param base The LPI2C peripheral base address. - * @param config Settings for the data match feature. - */ -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); - -/*! - * @brief Performs a software reset. - * - * Restores the LPI2C master peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -static inline void LPI2C_MasterReset(LPI2C_Type *base) -{ - base->MCR = LPI2C_MCR_RST_MASK; - base->MCR = 0; -} - -/*! - * @brief Enables or disables the LPI2C module as master. - * - * @param base The LPI2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified LPI2C as master. - */ -static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) -{ - base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the LPI2C master status flags. - * - * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _lpi2c_master_flags - */ -static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) -{ - return base->MSR; -} - -/*! - * @brief Clears the LPI2C master status flag state. - * - * The following status register flags can be cleared: - * - #kLPI2C_MasterEndOfPacketFlag - * - #kLPI2C_MasterStopDetectFlag - * - #kLPI2C_MasterNackDetectFlag - * - #kLPI2C_MasterArbitrationLostFlag - * - #kLPI2C_MasterFifoErrFlag - * - #kLPI2C_MasterPinLowTimeoutFlag - * - #kLPI2C_MasterDataMatchFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The LPI2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * LPI2C_MasterGetStatusFlags(). - * @see _lpi2c_master_flags. - */ -static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) -{ - base->MSR = statusMask; -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the LPI2C master interrupt requests. - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->MIER |= interruptMask; -} - -/*! - * @brief Disables the LPI2C master interrupt requests. - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->MIER &= ~interruptMask; -} - -/*! - * @brief Returns the set of currently enabled LPI2C master interrupt requests. - * - * @param base The LPI2C peripheral base address. - * @return A bitmask composed of #_lpi2c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) -{ - return base->MIER; -} - -/*@}*/ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables LPI2C master DMA requests. - * - * @param base The LPI2C peripheral base address. - * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. - * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. - */ -static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) -{ - base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); -} - -/*! - * @brief Gets LPI2C master transmit data register address for DMA transfer. - * - * @param base The LPI2C peripheral base address. - * @return The LPI2C Master Transmit Data Register address. - */ -static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) -{ - return (uint32_t)&base->MTDR; -} - -/*! - * @brief Gets LPI2C master receive data register address for DMA transfer. - * - * @param base The LPI2C peripheral base address. - * @return The LPI2C Master Receive Data Register address. - */ -static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) -{ - return (uint32_t)&base->MRDR; -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! - * @brief Sets the watermarks for LPI2C master FIFOs. - * - * @param base The LPI2C peripheral base address. - * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever - * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or - * greater than the FIFO size is truncated. - * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever - * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater - * than the FIFO size is truncated. - */ -static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) -{ - base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); -} - -/*! - * @brief Gets the current number of words in the LPI2C master FIFOs. - * - * @param base The LPI2C peripheral base address. - * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) -{ - if (txCount) - { - *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; - } - if (rxCount) - { - *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; - } -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @param base The LPI2C peripheral base address. - * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. - * @param baudRate_Hz Requested bus frequency in Hertz. - */ -void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The LPI2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) -{ - return (base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT; -} - -/*! - * @brief Sends a START signal and slave address on the I2C bus. - * - * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure - * that another master is not occupying the bus. Then a START signal is transmitted, followed by the - * 7-bit address specified in the @a address parameter. Note that this function does not actually wait - * until the START and address are successfully sent on the bus before returning. - * - * @param base The LPI2C peripheral base address. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - */ -status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); - -/*! - * @brief Sends a repeated START signal and slave address on the I2C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * LPI2C_MasterStart(), it also sends the specified 7-bit address. - * - * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * @param base The LPI2C peripheral base address. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - */ -static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) -{ - return LPI2C_MasterStart(base, address, dir); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_LPI2C_Nak. - * - * @param base The LPI2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @retval #kStatus_Success Data was sent successfully. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @retval #kStatus_Success Data was received successfully. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * This function does not return until the STOP signal is seen on the bus, or an error occurs. - * - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterStop(LPI2C_Type *base); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the LPI2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. - * - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param transfer The pointer to the transfer descriptor. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_t *transfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking LPI2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * LPI2C peripheral's IRQ priority. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @retval #kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. - */ -void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - */ -void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ - -/*! - * @addtogroup lpi2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the LPI2C slave peripheral. - * - * This function provides the following default configuration for the LPI2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0 = 0U; - * slaveConfig->address1 = 0U; - * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; - * slaveConfig->filterDozeEnable = true; - * slaveConfig->filterEnable = true; - * slaveConfig->enableGeneralCall = false; - * slaveConfig->sclStall.enableAck = false; - * slaveConfig->sclStall.enableTx = true; - * slaveConfig->sclStall.enableRx = true; - * slaveConfig->sclStall.enableAddress = true; - * slaveConfig->ignoreAck = false; - * slaveConfig->enableReceivedAddressRead = false; - * slaveConfig->sdaGlitchFilterWidth_ns = 0; // TODO determine default width values - * slaveConfig->sclGlitchFilterWidth_ns = 0; - * slaveConfig->dataValidDelay_ns = 0; - * slaveConfig->clockHoldTime_ns = 0; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a - * address0 member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #lpi2c_slave_config_t. - */ -void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the LPI2C slave peripheral. - * - * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user - * provided configuration. - * - * @param base The LPI2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, - * data valid delay, and clock hold time. - */ -void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); - -/*! -* @brief Deinitializes the LPI2C slave peripheral. -* - * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -void LPI2C_SlaveDeinit(LPI2C_Type *base); - -/*! - * @brief Performs a software reset of the LPI2C slave peripheral. - * - * @param base The LPI2C peripheral base address. - */ -static inline void LPI2C_SlaveReset(LPI2C_Type *base) -{ - base->SCR = LPI2C_SCR_RST_MASK; - base->SCR = 0; -} - -/*! - * @brief Enables or disables the LPI2C module as slave. - * - * @param base The LPI2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified LPI2C as slave. - */ -static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) -{ - base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); -} - -/*@}*/ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Gets the LPI2C slave status flags. - * - * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _lpi2c_slave_flags - */ -static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) -{ - return base->SSR; -} - -/*! - * @brief Clears the LPI2C status flag state. - * - * The following status register flags can be cleared: - * - #kLPI2C_SlaveRepeatedStartDetectFlag - * - #kLPI2C_SlaveStopDetectFlag - * - #kLPI2C_SlaveBitErrFlag - * - #kLPI2C_SlaveFifoErrFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The LPI2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * LPI2C_SlaveGetStatusFlags(). - * @see _lpi2c_slave_flags. - */ -static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) -{ - base->SSR = statusMask; -} - -/*@}*/ - -/*! @name Slave interrupts */ -/*@{*/ - -/*! - * @brief Enables the LPI2C slave interrupt requests. - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->SIER |= interruptMask; -} - -/*! - * @brief Disables the LPI2C slave interrupt requests. - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->SIER &= ~interruptMask; -} - -/*! - * @brief Returns the set of currently enabled LPI2C slave interrupt requests. - * @param base The LPI2C peripheral base address. - * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) -{ - return base->SIER; -} - -/*@}*/ - -/*! @name Slave DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables the LPI2C slave peripheral DMA requests. - * - * @param base The LPI2C peripheral base address. - * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. - * The address valid DMA request is shared with the receive data DMA request. - * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. - * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. - */ -static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) -{ - base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | - LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); -} - -/*@}*/ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the slave mode to be enabled. - * - * @param base The LPI2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) -{ - return (base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT; -} - -/*! - * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. - * - * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This - * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration - * structure used to initialize the slave peripheral. - * - * @param base The LPI2C peripheral base address. - * @param ackOrNack Pass true for an ACK or false for a NAK. - */ -static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) -{ - base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); -} - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) -{ - return base->SASR & LPI2C_SASR_RADDR_MASK; -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param[out] actualTxSize - * @return Error or success status returned by API. - */ -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param[out] actualRxSize - * @return Error or success status returned by API. - */ -status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); - -/*@}*/ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the LPI2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. - * - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, - lpi2c_slave_handle_t *handle, - lpi2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. - */ -status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Gets the slave transfer status during a non-blocking transfer. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure. - * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not - * required. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress - */ -status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_Idle - */ -void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/*@}*/ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - */ -void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/*@}*/ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_LPI2C_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.c deleted file mode 100644 index e5b0068867a27c69012acf6a5ce893a16cf3f519..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpi2c_edma.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* @brief Mask to align an address to 32 bytes. */ -#define ALIGN_32_MASK (0x1fU) - -/*! @brief Common sets of flags used by the driver. */ -enum _lpi2c_flag_constants -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | - kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterDataMatchFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | - kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterFifoErrFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | - kLPI2C_MasterPinLowTimeoutFlag, - - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveFifoErrFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | - kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, -}; - -/* ! @brief LPI2C master fifo commands. */ -enum _lpi2c_master_fifo_cmd -{ - kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ - kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _lpi2c_transfer_states -{ - kIdleState = 0, - kSendCommandState, - kIssueReadCommandState, - kTransferDataState, - kStopState, - kWaitForCompletionState, -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Defined in fsl_lpi2c.c. */ -extern status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); - -/* Defined in fsl_lpi2c.c. */ -extern status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); - -static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); - -static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); - -/******************************************************************************* - * Code - ******************************************************************************/ - -void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - edma_handle_t *rxDmaHandle, - edma_handle_t *txDmaHandle, - lpi2c_master_edma_transfer_callback_t callback, - void *userData) -{ - assert(handle); - assert(rxDmaHandle); - assert(txDmaHandle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ - /* in order to make the transfer API code simpler. */ - handle->base = base; - handle->completionCallback = callback; - handle->userData = userData; - handle->rx = rxDmaHandle; - handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; - - /* Set DMA channel completion callbacks. */ - EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); - } -} - -/*! - * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. - * @param handle Master DMA driver handle. - * @return Number of command words. - */ -static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) -{ - lpi2c_master_transfer_t *xfer = &handle->transfer; - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; - uint32_t cmdCount = 0; - - /* Handle no start option. */ - if (xfer->flags & kLPI2C_TransferNoStartFlag) - { - if (xfer->direction == kLPI2C_Read) - { - /* Need to issue read command first. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - } - else - { - /* - * Initial direction depends on whether a subaddress was provided, and of course the actual - * data transfer direction. - */ - lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; - - /* Start command. */ - cmd[cmdCount++] = - (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); - - /* Subaddress, MSB first. */ - if (xfer->subaddressSize) - { - uint32_t subaddressRemaining = xfer->subaddressSize; - while (subaddressRemaining--) - { - uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; - } - } - - /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ - if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) - { - /* Need to send repeated start if switching directions to read. */ - if (direction == kLPI2C_Write) - { - cmd[cmdCount++] = (uint16_t)kStartCmd | - (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); - } - - /* Read command. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - } - - return cmdCount; -} - -status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - lpi2c_master_transfer_t *transfer) -{ - status_t result; - - assert(handle); - assert(transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* We're now busy. */ - handle->isBusy = true; - - /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - LPI2C_MasterEnableDMA(base, false, false); - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Save transfer into handle. */ - handle->transfer = *transfer; - - /* Generate commands to send. */ - uint32_t commandCount = LPI2C_GenerateCommands(handle); - - /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ - if ((!commandCount) && (transfer->dataSize == 0)) - { - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_Success, handle->userData); - } - return kStatus_Success; - } - - /* Reset DMA channels. */ - EDMA_ResetChannel(handle->rx->base, handle->rx->channel); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_ResetChannel(handle->tx->base, handle->tx->channel); - } - - /* Get a 32-byte aligned TCD pointer. */ - edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); - - bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); - bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize); - - edma_transfer_config_t transferConfig; - edma_tcd_t *linkTcd = NULL; - - /* Set up data transmit. */ - if (hasSendData) - { - transferConfig.srcAddr = (uint32_t)transfer->data; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = sizeof(uint8_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; - - /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ - handle->nbytes = transferConfig.minorLoopBytes; - - if (commandCount) - { - /* Create a software TCD, which will be chained after the commands. */ - EDMA_TcdReset(tcd); - EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); - EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); - linkTcd = tcd; - } - else - { - /* User is only transmitting data with no required commands, so this transfer can stand alone. */ - EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); - EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); - } - } - else if (hasReceiveData) - { - /* Set up data receive. */ - transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); - transferConfig.destAddr = (uint32_t)transfer->data; - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = 0; - transferConfig.destOffset = sizeof(uint8_t); - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; - - /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ - handle->nbytes = transferConfig.minorLoopBytes; - - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) || (!commandCount)) - { - /* We can put this receive transfer on its own DMA channel. */ - EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); - EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, kEDMA_MajorInterruptEnable); - } - else - { - /* For shared rx/tx DMA requests when there are commands, create a software TCD which will be */ - /* chained onto the commands transfer. */ - EDMA_TcdReset(tcd); - EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); - EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); - linkTcd = tcd; - } - } - else - { - /* No data to send */ - } - - /* Set up commands transfer. */ - if (commandCount) - { - transferConfig.srcAddr = (uint32_t)handle->commandBuffer; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfig.srcOffset = sizeof(uint16_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = commandCount; - - EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); - } - - /* Start DMA transfer. */ - if (hasReceiveData || !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_StartTransfer(handle->rx); - } - if ((hasSendData || commandCount) && FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_StartTransfer(handle->tx); - } - - /* Enable DMA in both directions. This actually kicks of the transfer. */ - LPI2C_MasterEnableDMA(base, true, true); - - return result; -} - -status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - uint32_t remaining = handle->transfer.dataSize; - - /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ - /* we do nothing and return the number of transferred bytes as zero. */ - if (handle->tx->base->TCD[handle->tx->channel].DLAST_SGA == 0) - { - if (handle->transfer.direction == kLPI2C_Write) - { - remaining = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); - } - else - { - remaining = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); - } - } - - *count = handle->transfer.dataSize - remaining; - - return kStatus_Success; -} - -status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) -{ - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - return kStatus_LPI2C_Idle; - } - - /* Terminate DMA transfers. */ - EDMA_AbortTransfer(handle->rx); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_AbortTransfer(handle->tx); - } - - /* Reset fifos. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - - /* Send a stop command to finalize the transfer. */ - base->MTDR = kStopCmd; - - /* Reset handle. */ - handle->isBusy = false; - - return kStatus_Success; -} - -/*! - * @brief DMA completion callback. - * @param dmaHandle DMA channel handle for the channel that completed. - * @param userData User data associated with the channel handle. For this callback, the user data is the - * LPI2C DMA driver handle. - * @param isTransferDone Whether the DMA transfer has completed. - * @param tcds Number of TCDs that completed. - */ -static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) -{ - lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; - if (!handle) - { - return; - } - - /* Check for errors. */ - status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); - - /* Done with this transaction. */ - handle->isBusy = false; - - if (!(handle->transfer.flags & kLPI2C_TransferNoStopFlag)) - { - /* Send a stop command to finalize the transfer. */ - handle->base->MTDR = kStopCmd; - } - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(handle->base, handle, result, handle->userData); - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.h deleted file mode 100644 index 6d791cf5cc157c224617f2a54507707b3e505110..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpi2c_edma.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPI2C_EDMA_H_ -#define _FSL_LPI2C_EDMA_H_ - -#include "fsl_lpi2c.h" -#include "fsl_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup lpi2c_master_edma_driver - * @{ - */ - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; - -/*! - * @brief Master DMA completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to LPI2C_MasterCreateEDMAHandle(). - * - * @param base The LPI2C peripheral base address. - * @param handle Handle associated with the completed transfer. - * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Driver handle for master DMA APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_master_edma_handle -{ - LPI2C_Type *base; /*!< LPI2C base pointer. */ - bool isBusy; /*!< Transfer state machine current state. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ - lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ - edma_handle_t *rx; /*!< Handle for receive DMA channel. */ - edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ - edma_tcd_t tcds[2]; /*!< Software TCD. Two are allocated to provide enough room to align to 32-bytes. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup lpi2c_master_edma_driver - * @{ - */ - -/*! @name Master DMA */ -/*@{*/ - -/*! - * @brief Create a new handle for the LPI2C master DMA APIs. - * - * The creation of a handle is for use with the DMA APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. - * - * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle - * parameter is ignored and may be set to NULL. - * - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C master driver handle. - * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. - * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - edma_handle_t *rxDmaHandle, - edma_handle_t *txDmaHandle, - lpi2c_master_edma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking DMA-based transaction on the I2C bus. - * - * The callback specified when the @a handle was created is invoked when the transaction has - * completed. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param transfer The pointer to the transfer descriptor. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA - * transaction is already in progress. - */ -status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - lpi2c_master_transfer_t *transfer); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. - */ -status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking LPI2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * eDMA peripheral's IRQ priority. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @retval #kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. - */ -status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); - -/*@}*/ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_LPI2C_EDMA_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.c deleted file mode 100644 index 5c853065849c671891cb0fcd12aa7a6788b37940..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpit.h" - -/******************************************************************************* -* Variables -******************************************************************************/ - -/*! @brief Array to map LPIT instance number to base pointer. */ -static LPIT_Type* const s_lpitBases[] = LPIT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clock array name */ -static const clock_ip_name_t s_lpitClock[] = LPIT_CLOCKS; - -#if defined(LPIT_PERIPH_CLOCKS) -/* Array of LPIT functional clock name. */ -static const clock_ip_name_t s_lpitPeriphClocks[] = LPIT_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the instance for LPIT module. - * - * @param base LPIT base address - */ -uint32_t LPIT_GetInstance(LPIT_Type* base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t LPIT_GetInstance(LPIT_Type* base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpitBases); instance++) - { - if (s_lpitBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpitBases)); - - return instance; -} - -void LPIT_Init(LPIT_Type* base, const lpit_config_t* config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPIT_GetInstance(base); - - /* Enable the clock */ - CLOCK_EnableClock(s_lpitClock[instance]); -#if defined(LPIT_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lpitPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the timer channels and registers except the MCR register */ - LPIT_Reset(base); - - /* Setup timer operation in debug and doze modes and enable the module */ - base->MCR = - (LPIT_MCR_DBG_EN(config->enableRunInDebug) | LPIT_MCR_DOZE_EN(config->enableRunInDoze) | LPIT_MCR_M_CEN_MASK); -} - -void LPIT_Deinit(LPIT_Type* base) -{ - /* Disable the module */ - base->MCR &= ~LPIT_MCR_M_CEN_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPIT_GetInstance(base); - - /* Disable the clock */ - CLOCK_DisableClock(s_lpitClock[instance]); -#if defined(LPIT_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lpitPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPIT_GetDefaultConfig(lpit_config_t* config) -{ - assert(config); - - /* Timers are stopped in debug mode */ - config->enableRunInDebug = false; - /* Timers are stopped in doze mode */ - config->enableRunInDoze = false; -} - -status_t LPIT_SetupChannel(LPIT_Type* base, lpit_chnl_t channel, const lpit_chnl_params_t* chnlSetup) -{ - assert(chnlSetup); - - uint32_t reg = 0; - - /* Cannot assert the chain bit for channel 0 */ - if ((channel == kLPIT_Chnl_0) && (chnlSetup->chainChannel == true)) - { - return kStatus_Fail; - } - - /* Setup the channel counters operation mode, trigger operation, chain mode */ - reg = (LPIT_TCTRL_MODE(chnlSetup->timerMode) | LPIT_TCTRL_TRG_SRC(chnlSetup->triggerSource) | - LPIT_TCTRL_TRG_SEL(chnlSetup->triggerSelect) | LPIT_TCTRL_TROT(chnlSetup->enableReloadOnTrigger) | - LPIT_TCTRL_TSOI(chnlSetup->enableStopOnTimeout) | LPIT_TCTRL_TSOT(chnlSetup->enableStartOnTrigger) | - LPIT_TCTRL_CHAIN(chnlSetup->chainChannel)); - - base->CHANNEL[channel].TCTRL = reg; - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.h deleted file mode 100644 index d2810aaa977538329d656c60ccd0b245dbf6737f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpit.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPIT_H_ -#define _FSL_LPIT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpit - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_LPIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ - /*@{*/ - -/*! - * @brief List of LPIT channels - * @note Actual number of available channels is SoC-dependent - */ -typedef enum _lpit_chnl -{ - kLPIT_Chnl_0 = 0U, /*!< LPIT channel number 0*/ - kLPIT_Chnl_1, /*!< LPIT channel number 1 */ - kLPIT_Chnl_2, /*!< LPIT channel number 2 */ - kLPIT_Chnl_3, /*!< LPIT channel number 3 */ -} lpit_chnl_t; - -/*! @brief Mode options available for the LPIT timer. */ -typedef enum _lpit_timer_modes -{ - kLPIT_PeriodicCounter = 0U, /*!< Use the all 32-bits, counter loads and decrements to zero */ - kLPIT_DualPeriodicCounter, /*!< Counter loads, lower 16-bits decrement to zero, then - upper 16-bits decrement */ - kLPIT_TriggerAccumulator, /*!< Counter loads on first trigger and decrements on each trigger */ - kLPIT_InputCapture /*!< Counter loads with 0xFFFFFFFF, decrements to zero. It stores - the inverse of the current value when a input trigger is detected */ -} lpit_timer_modes_t; - -/*! - * @brief Trigger options available. - * - * This is used for both internal and external trigger sources. The actual trigger options - * available is SoC-specific, user should refer to the reference manual. - */ -typedef enum _lpit_trigger_select -{ - kLPIT_Trigger_TimerChn0 = 0U, /*!< Channel 0 is selected as a trigger source */ - kLPIT_Trigger_TimerChn1, /*!< Channel 1 is selected as a trigger source */ - kLPIT_Trigger_TimerChn2, /*!< Channel 2 is selected as a trigger source */ - kLPIT_Trigger_TimerChn3, /*!< Channel 3 is selected as a trigger source */ - kLPIT_Trigger_TimerChn4, /*!< Channel 4 is selected as a trigger source */ - kLPIT_Trigger_TimerChn5, /*!< Channel 5 is selected as a trigger source */ - kLPIT_Trigger_TimerChn6, /*!< Channel 6 is selected as a trigger source */ - kLPIT_Trigger_TimerChn7, /*!< Channel 7 is selected as a trigger source */ - kLPIT_Trigger_TimerChn8, /*!< Channel 8 is selected as a trigger source */ - kLPIT_Trigger_TimerChn9, /*!< Channel 9 is selected as a trigger source */ - kLPIT_Trigger_TimerChn10, /*!< Channel 10 is selected as a trigger source */ - kLPIT_Trigger_TimerChn11, /*!< Channel 11 is selected as a trigger source */ - kLPIT_Trigger_TimerChn12, /*!< Channel 12 is selected as a trigger source */ - kLPIT_Trigger_TimerChn13, /*!< Channel 13 is selected as a trigger source */ - kLPIT_Trigger_TimerChn14, /*!< Channel 14 is selected as a trigger source */ - kLPIT_Trigger_TimerChn15 /*!< Channel 15 is selected as a trigger source */ -} lpit_trigger_select_t; - -/*! @brief Trigger source options available */ -typedef enum _lpit_trigger_source -{ - kLPIT_TriggerSource_External = 0U, /*!< Use external trigger input */ - kLPIT_TriggerSource_Internal /*!< Use internal trigger */ -} lpit_trigger_source_t; - -/*! - * @brief List of LPIT interrupts. - * - * @note Number of timer channels are SoC-specific. See the SoC Reference Manual. - */ -typedef enum _lpit_interrupt_enable -{ - kLPIT_Channel0TimerInterruptEnable = (1U << 0), /*!< Channel 0 Timer interrupt */ - kLPIT_Channel1TimerInterruptEnable = (1U << 1), /*!< Channel 1 Timer interrupt */ - kLPIT_Channel2TimerInterruptEnable = (1U << 2), /*!< Channel 2 Timer interrupt */ - kLPIT_Channel3TimerInterruptEnable = (1U << 3), /*!< Channel 3 Timer interrupt */ -} lpit_interrupt_enable_t; - -/*! - * @brief List of LPIT status flags - * - * @note Number of timer channels are SoC-specific. See the SoC Reference Manual. - */ -typedef enum _lpit_status_flags -{ - kLPIT_Channel0TimerFlag = (1U << 0), /*!< Channel 0 Timer interrupt flag */ - kLPIT_Channel1TimerFlag = (1U << 1), /*!< Channel 1 Timer interrupt flag */ - kLPIT_Channel2TimerFlag = (1U << 2), /*!< Channel 2 Timer interrupt flag */ - kLPIT_Channel3TimerFlag = (1U << 3), /*!< Channel 3 Timer interrupt flag */ -} lpit_status_flags_t; - -/*! @brief Structure to configure the channel timer. */ -typedef struct _lpit_chnl_params -{ - bool chainChannel; /*!< true: Timer chained to previous timer; - false: Timer not chained */ - lpit_timer_modes_t timerMode; /*!< Timers mode of operation. */ - lpit_trigger_select_t triggerSelect; /*!< Trigger selection for the timer */ - lpit_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ - bool enableReloadOnTrigger; /*!< true: Timer reloads when a trigger is detected; - false: No effect */ - bool enableStopOnTimeout; /*!< true: Timer will stop after timeout; - false: does not stop after timeout */ - bool enableStartOnTrigger; /*!< true: Timer starts when a trigger is detected; - false: decrement immediately */ -} lpit_chnl_params_t; - -/*! - * @brief LPIT configuration structure - * - * This structure holds the configuration settings for the LPIT peripheral. To initialize this - * structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _lpit_config -{ - bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ - bool enableRunInDoze; /*!< true: Timers run in doze mode; false: Timers stop in doze mode */ -} lpit_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the LPIT clock and configures the peripheral for a basic operation. - * - * This function issues a software reset to reset all channels and registers except the Module - * Control register. - * - * @note This API should be called at the beginning of the application using the LPIT driver. - * - * @param base LPIT peripheral base address. - * @param config Pointer to the user configuration structure. - */ -void LPIT_Init(LPIT_Type* base, const lpit_config_t* config); - -/*! - * @brief Disables the module and gates the LPIT clock. - * - * @param base LPIT peripheral base address. - */ -void LPIT_Deinit(LPIT_Type* base); - -/*! - * @brief Fills in the LPIT configuration structure with default settings. - * - * The default values are: - * @code - * config->enableRunInDebug = false; - * config->enableRunInDoze = false; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void LPIT_GetDefaultConfig(lpit_config_t* config); - -/*! - * @brief Sets up an LPIT channel based on the user's preference. - * - * This function sets up the operation mode to one of the options available in the - * enumeration ::lpit_timer_modes_t. It sets the trigger source as either internal or external, - * trigger selection and the timers behaviour when a timeout occurs. It also chains - * the timer if a prior timer if requested by the user. - * - * @param base LPIT peripheral base address. - * @param channel Channel that is being configured. - * @param chnlSetup Configuration parameters. - */ -status_t LPIT_SetupChannel(LPIT_Type* base, lpit_chnl_t channel, const lpit_chnl_params_t* chnlSetup); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected PIT interrupts. - * - * @param base LPIT peripheral base address. - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::lpit_interrupt_enable_t - */ -static inline void LPIT_EnableInterrupts(LPIT_Type* base, uint32_t mask) -{ - base->MIER |= mask; -} - -/*! - * @brief Disables the selected PIT interrupts. - * - * @param base LPIT peripheral base address. - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::lpit_interrupt_enable_t - */ -static inline void LPIT_DisableInterrupts(LPIT_Type* base, uint32_t mask) -{ - base->MIER &= ~mask; -} - -/*! - * @brief Gets the enabled LPIT interrupts. - * - * @param base LPIT peripheral base address. - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::lpit_interrupt_enable_t - */ -static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type* base) -{ - return base->MIER; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the LPIT status flags. - * - * @param base LPIT peripheral base address. - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::lpit_status_flags_t - */ -static inline uint32_t LPIT_GetStatusFlags(LPIT_Type* base) -{ - return base->MSR; -} - -/*! - * @brief Clears the LPIT status flags. - * - * @param base LPIT peripheral base address. - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::lpit_status_flags_t - */ -static inline void LPIT_ClearStatusFlags(LPIT_Type* base, uint32_t mask) -{ - /* Writing a 1 to the status bit will clear the flag */ - base->MSR = mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting down from the value set by this function until it reaches 0, at which point - * it generates an interrupt and loads this register value again. - * Writing a new value to this register does not restart the timer. Instead, the value - * is loaded after the timer expires. - * - * @note User can call the utility macros provided in fsl_common.h to convert to ticks. - * - * @param base LPIT peripheral base address. - * @param channel Timer channel number. - * @param ticks Timer period in units of ticks. - */ -static inline void LPIT_SetTimerPeriod(LPIT_Type* base, lpit_chnl_t channel, uint32_t ticks) -{ - base->CHANNEL[channel].TVAL = ticks; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds. - * - * @param base LPIT peripheral base address. - * @param channel Timer channel number. - * - * @return Current timer counting value in ticks. - */ -static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type* base, lpit_chnl_t channel) -{ - return base->CHANNEL[channel].CVAL; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load the period value and count down to 0. When the timer - * reaches 0, it generates a trigger pulse and sets the timeout interrupt flag. - * - * @param base LPIT peripheral base address. - * @param channel Timer channel number. - */ -static inline void LPIT_StartTimer(LPIT_Type* base, lpit_chnl_t channel) -{ - base->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << channel); -} - -/*! - * @brief Stops the timer counting. - * - * @param base LPIT peripheral base address. - * @param channel Timer channel number. - */ -static inline void LPIT_StopTimer(LPIT_Type* base, lpit_chnl_t channel) -{ - base->CLRTEN |= (LPIT_CLRTEN_CLR_T_EN_0_MASK << channel); -} - -/*! @}*/ - -/*! - * @brief Performs a software reset on the LPIT module. - * - * This resets all channels and registers except the Module Control Register. - * - * @param base LPIT peripheral base address. - */ -static inline void LPIT_Reset(LPIT_Type* base) -{ - base->MCR |= LPIT_MCR_SW_RST_MASK; - base->MCR &= ~LPIT_MCR_SW_RST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* __FSL_LPIT_H__ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.c deleted file mode 100644 index b7b6ac1ea7e035ea0d99399982bd201fd4ddd015..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.c +++ /dev/null @@ -1,1744 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpspi.h" - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! - * @brief Default watermark values. - * - * The default watermarks are set to zero. - */ -enum _lpspi_default_watermarks -{ - kLpspiDefaultTxWatermark = 0, - kLpspiDefaultRxWatermark = 0, -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! -* @brief Get instance number for LPSPI module. -* -* @param base LPSPI peripheral base address. -*/ -uint32_t LPSPI_GetInstance(LPSPI_Type *base); - -/*! -* @brief Configures the LPSPI peripheral chip select polarity. -* -* This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and -* configures the Pcs signal to operate with the desired characteristic. -* -* @param base LPSPI peripheral address. -* @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to -* apply the active high or active low characteristic. -* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of -* type lpspi_pcs_polarity_config_t. -*/ -static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, - lpspi_which_pcs_t pcs, - lpspi_pcs_polarity_config_t activeLowOrHigh); - -/*! -* @brief Combine the write data for 1 byte to 4 bytes. -* This is not a public API. -*/ -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap); - -/*! -* @brief Separate the read data for 1 byte to 4 bytes. -* This is not a public API. -*/ -static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); - -/*! -* @brief Master fill up the TX FIFO with data. -* This is not a public API. -*/ -static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! -* @brief Master finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ -static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! -* @brief Slave fill up the TX FIFO with data. -* This is not a public API. -*/ -static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! -* @brief Slave finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ -static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! -* @brief Check the argument for transfer . -* This is not a public API. Not static because lpspi_edma.c will use this API. -*/ -bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); - -/*! -* @brief LPSPI common interrupt handler. -* -* @param handle pointer to s_lpspiHandle which stores the transfer state. -*/ -static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param); - -/******************************************************************************* -* Variables -******************************************************************************/ - -/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ -static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; - -/*! @brief Pointers to lpspi bases for each instance. */ -static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; - -/*! @brief Pointers to lpspi IRQ number for each instance. */ -static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to lpspi clocks for each instance. */ -static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; - -#if defined(LPSPI_PERIPH_CLOCKS) -static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to lpspi handles for each instance. */ -static void *s_lpspiHandle[FSL_FEATURE_SOC_LPSPI_COUNT] = {NULL}; - -/*! @brief Pointer to master IRQ handler for each instance. */ -static lpspi_master_isr_t s_lpspiMasterIsr; -/*! @brief Pointer to slave IRQ handler for each instance. */ -static lpspi_slave_isr_t s_lpspiSlaveIsr; -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t s_dummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; -/********************************************************************************************************************** -* Code -*********************************************************************************************************************/ -uint32_t LPSPI_GetInstance(LPSPI_Type *base) -{ - uint8_t instance = 0; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) - { - if (s_lpspiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpspiBases)); - - return instance; -} - -void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = LPSPI_GetInstance(base); - s_dummyData[instance] = dummyData; -} - -void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(masterConfig); - - uint32_t tcrPrescaleValue = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_EnableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset to known status */ - LPSPI_Reset(base); - - /* Set LPSPI to master */ - LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); - - /* Set specific PCS to active high or low */ - LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); - - /* Set Configuration Register 1 related setting.*/ - base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) | - LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | - LPSPI_CFGR1_NOSTALL(0); - - /* Set baudrate and delay times*/ - LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); - - /* Set default watermarks */ - LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); - - /* Set Transmit Command Register*/ - base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | - LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1) | - LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); - - LPSPI_Enable(base, true); - - LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); - LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); - LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, srcClock_Hz); - - LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); -} - -void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->baudRate = 500000; - masterConfig->bitsPerFrame = 8; - masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; - masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; - masterConfig->direction = kLPSPI_MsbFirst; - - masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - - masterConfig->whichPcs = kLPSPI_Pcs0; - masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; - - masterConfig->pinCfg = kLPSPI_SdiInSdoOut; - masterConfig->dataOutConfig = kLpspiDataOutRetained; -} - -void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_EnableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset to known status */ - LPSPI_Reset(base); - - LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); - - LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); - - base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | - LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); - - LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); - - base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | - LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1) | LPSPI_TCR_PCS(slaveConfig->whichPcs); - - /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ - LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); - - LPSPI_Enable(base, true); -} - -void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ - slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ - slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ - slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ - - slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ - slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ - - slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; - slaveConfig->dataOutConfig = kLpspiDataOutRetained; -} - -void LPSPI_Reset(LPSPI_Type *base) -{ - /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ - base->CR |= LPSPI_CR_RST_MASK; - - /* Software reset doesn't reset the CR, so manual reset the FIFOs */ - base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; - - /* Master logic is not reset and module is disabled.*/ - base->CR = 0x00U; -} - -void LPSPI_Deinit(LPSPI_Type *base) -{ - /* Reset to default value */ - LPSPI_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_DisableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, - lpspi_which_pcs_t pcs, - lpspi_pcs_polarity_config_t activeLowOrHigh) -{ - uint32_t cfgr1Value = 0; - /* Clear the PCS polarity bit */ - cfgr1Value = base->CFGR1 & ~(1U << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); - - /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ - base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); -} - -uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz, - uint32_t *tcrPrescaleValue) -{ - assert(tcrPrescaleValue); - - /* For master mode configuration only, if slave mode detected, return 0. - * Also, the LPSPI module needs to be disabled first, if enabled, return 0 - */ - if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t realBaudrate, bestBaudrate; - uint32_t diff, min_diff; - uint32_t desiredBaudrate = baudRate_Bps; - - /* find combination of prescaler and scaler resulting in baudrate closest to the - * requested value - */ - min_diff = 0xFFFFFFFFU; - - /* Set to maximum divisor value bit settings so that if baud rate passed in is less - * than the minimum possible baud rate, then the SPI will be configured to the lowest - * possible baud rate - */ - bestPrescaler = 7; - bestScaler = 255; - - bestBaudrate = 0; /* required to avoid compilation warning */ - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 256) && min_diff; scaler++) - { - realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); - - /* calculate the baud rate difference based on the conditional statement - * that states that the calculated baud rate must not exceed the desired baud rate - */ - if (desiredBaudrate >= realBaudrate) - { - diff = desiredBaudrate - realBaudrate; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; - } - } - } - } - - /* Write the best baud rate scalar to the CCR. - * Note, no need to check for error since we've already checked to make sure the module is - * disabled and in master mode. Also, there is a limit on the maximum divider so we will not - * exceed this. - */ - base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); - - /* return the best prescaler value for user to use later */ - *tcrPrescaleValue = bestPrescaler; - - /* return the actual calculated baud rate */ - return bestBaudrate; -} - -void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) -{ - /*These settings are only relevant in master mode */ - switch (whichDelay) - { - case kLPSPI_PcsToSck: - base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); - - break; - case kLPSPI_LastSckToPcs: - base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); - - break; - case kLPSPI_BetweenTransfer: - base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); - - break; - default: - assert(false); - break; - } -} - -uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, - uint32_t delayTimeInNanoSec, - lpspi_delay_type_t whichDelay, - uint32_t srcClock_Hz) -{ - uint64_t realDelay, bestDelay; - uint32_t scaler, bestScaler; - uint32_t diff, min_diff; - uint64_t initialDelayNanoSec; - uint32_t clockDividedPrescaler; - - /* For delay between transfer, an additional scaler value is needed */ - uint32_t additionalScaler = 0; - - /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between - * transfers.*/ - clockDividedPrescaler = - srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; - - /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ - min_diff = 0xFFFFFFFFU; - - /* Initialize scaler to max value to generate the max delay */ - bestScaler = 0xFFU; - - /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as - * the delay divisors are slightly different based on which delay we are configuring. - */ - if (whichDelay == kLPSPI_BetweenTransfer) - { - /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of - calculated values (uint64_t), we need to break up the calculation into several steps to ensure - accurate calculated results - */ - initialDelayNanoSec = 1000000000U; - initialDelayNanoSec *= 2U; - initialDelayNanoSec /= clockDividedPrescaler; - - /* Calculate the maximum delay */ - bestDelay = 1000000000U; - bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ - bestDelay /= clockDividedPrescaler; - - additionalScaler = 1U; - } - else - { - /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated - values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated - results. - */ - initialDelayNanoSec = 1000000000U; - initialDelayNanoSec /= clockDividedPrescaler; - - /* Calculate the maximum delay */ - bestDelay = 1000000000U; - bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ - bestDelay /= clockDividedPrescaler; - - additionalScaler = 0; - } - - /* If the initial, default delay is already greater than the desired delay, then - * set the delay to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ - if (initialDelayNanoSec >= delayTimeInNanoSec) - { - LPSPI_MasterSetDelayScaler(base, 0, whichDelay); - return initialDelayNanoSec; - } - - /* If min_diff = 0, the exit for loop */ - for (scaler = 0; (scaler < 256U) && min_diff; scaler++) - { - /* Calculate the real delay value as we cycle through the scaler values. - Due to large size of calculated values (uint64_t), we need to break up the - calculation into several steps to ensure accurate calculated results - */ - realDelay = 1000000000U; - realDelay *= (scaler + 1 + additionalScaler); - realDelay /= clockDividedPrescaler; - - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ - if (realDelay >= delayTimeInNanoSec) - { - diff = realDelay - delayTimeInNanoSec; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestScaler = scaler; - bestDelay = realDelay; - } - } - } - - /* write the best scaler value for the delay */ - LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); - - /* return the actual calculated delay value (in ns) */ - return bestDelay; -} - -/*Transactional APIs -- Master*/ - -void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, - lpspi_master_handle_t *handle, - lpspi_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - s_lpspiHandle[LPSPI_GetInstance(base)] = handle; - - /* Set irq handler. */ - s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; - - handle->callback = callback; - handle->userData = userData; -} - -bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) -{ - assert(transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0) - { - return false; - } - - /* If both send buffer and receive buffer is null */ - if ((!(transfer->txData)) && (!(transfer->rxData))) - { - return false; - } - - /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . - *For bytesPerFrame greater than 4 situation: - *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , - *otherwise , the transfer data size can be integer multiples of bytesPerFrame. - */ - if (bytesPerFrame <= 4) - { - if ((transfer->dataSize % bytesPerFrame) != 0) - { - return false; - } - } - else - { - if ((bytesPerFrame % 4U) != 0) - { - if (transfer->dataSize != bytesPerFrame) - { - return false; - } - } - else - { - if ((transfer->dataSize % bytesPerFrame) != 0) - { - return false; - } - } - } - - return true; -} - -status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) -{ - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that LPSPI is not busy.*/ - if (LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag) - { - return kStatus_LPSPI_Busy; - } - - uint8_t *txData = transfer->txData; - uint8_t *rxData = transfer->rxData; - uint32_t txRemainingByteCount = transfer->dataSize; - uint32_t rxRemainingByteCount = transfer->dataSize; - - uint8_t bytesEachWrite; - uint8_t bytesEachRead; - - uint32_t readData = 0; - uint32_t wordToSend = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - uint32_t fifoSize = LPSPI_GetRxFifoSize(base); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - bool isRxMask = false; - bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - - if (!rxData) - { - isRxMask = true; - } - - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - LPSPI_Enable(base, true); - - base->TCR = - (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_PCS(whichPcs); - - if (bytesPerFrame <= 4) - { - bytesEachWrite = bytesPerFrame; - bytesEachRead = bytesPerFrame; - } - else - { - bytesEachWrite = 4; - bytesEachRead = 4; - } - - /*Write the TX data until txRemainingByteCount is equal to 0 */ - while (txRemainingByteCount > 0) - { - if (txRemainingByteCount < bytesEachWrite) - { - bytesEachWrite = txRemainingByteCount; - } - - /*Wait until TX FIFO is not full*/ - while (LPSPI_GetTxFifoCount(base) == fifoSize) - { - } - - if (txData) - { - wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); - txData += bytesEachWrite; - } - - LPSPI_WriteData(base, wordToSend); - txRemainingByteCount -= bytesEachWrite; - - /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/ - if (rxData) - { - while (LPSPI_GetRxFifoCount(base)) - { - readData = LPSPI_ReadData(base); - if (rxRemainingByteCount < bytesEachRead) - { - bytesEachRead = rxRemainingByteCount; - } - - LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); - rxData += bytesEachRead; - - rxRemainingByteCount -= bytesEachRead; - } - } - } - - /* After write all the data in TX FIFO , should write the TCR_CONTC to 0 to de-assert the PCS. Note that TCR - * register also use the TX FIFO. - */ - while ((LPSPI_GetTxFifoCount(base) == fifoSize)) - { - } - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - - /*Read out the RX data in FIFO*/ - if (rxData) - { - while (rxRemainingByteCount > 0) - { - while (LPSPI_GetRxFifoCount(base)) - { - readData = LPSPI_ReadData(base); - - if (rxRemainingByteCount < bytesEachRead) - { - bytesEachRead = rxRemainingByteCount; - } - - LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); - rxData += bytesEachRead; - - rxRemainingByteCount -= bytesEachRead; - } - } - } - else - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ - while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag)) - { - } - } - - return kStatus_Success; -} - -status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - bool isRxMask = false; - - uint8_t txWatermark; - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeTcrInIsr = false; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - /*Set the RX and TX watermarks to reduce the ISR times.*/ - if (handle->fifoSize > 1) - { - txWatermark = 1; - handle->rxWatermark = handle->fifoSize - 2; - } - else - { - txWatermark = 0; - handle->rxWatermark = 0; - } - - LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - LPSPI_Enable(base, true); - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO). - * For master transfer , we'd better not masked the transmit data in TCR since the transfer flow is hard to - * controlled by software.*/ - if (handle->rxData == NULL) - { - isRxMask = true; - handle->rxRemainingByteCount = 0; - } - - base->TCR = - (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | - LPSPI_TCR_PCS(whichPcs); - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - } - - /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , - * and you should also enable the INTMUX interupt in your application. - */ - EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); - - /*TCR is also shared the FIFO , so wait for TCR written.*/ - while (LPSPI_GetTxFifoCount(base) != 0) - { - } - /*Fill up the TX data in FIFO */ - LPSPI_MasterTransferFillUpTxFifo(base, handle); - - /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - if (handle->rxData) - { - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= handle->rxWatermark) - { - base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); - } - - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); - } - - return kStatus_Success; -} - -static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - uint32_t wordToSend = 0; - - /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth - * and that the number of TX FIFO entries does not exceed the FIFO depth. - * But no need to make the protection if there is no rxData. - */ - while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) && - (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) || - (handle->rxData == NULL))) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - if (handle->txData) - { - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - } - else - { - wordToSend = handle->txBuffIfNull; - } - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - - /*Decrease the write TX register times.*/ - --handle->writeRegRemainingTimes; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - if (handle->txRemainingByteCount == 0) - { - /* If PCS is continuous, update TCR to de-assert PCS */ - if (handle->isPcsContinuous) - { - /* Only write to the TCR if the FIFO has room */ - if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) - { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - handle->writeTcrInIsr = false; - } - /* Else, set a global flag to tell the ISR to do write to the TCR */ - else - { - handle->writeTcrInIsr = true; - } - } - break; - } - } -} - -static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - handle->state = kLPSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_Success, handle->userData); - } -} - -status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - if (handle->rxData) - { - remainingByte = handle->rxRemainingByteCount; - } - else - { - remainingByte = handle->txRemainingByteCount; - } - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - LPSPI_Reset(base); - - handle->state = kLPSPI_Idle; - handle->txRemainingByteCount = 0; - handle->rxRemainingByteCount = 0; -} - -void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - uint32_t readData; - - if (handle->rxData != NULL) - { - if (handle->rxRemainingByteCount) - { - /* First, disable the interrupts to avoid potentially triggering another interrupt - * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll - * re-enable the interrupts based on the LPSPI state after reading out the FIFO. - */ - LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable); - - while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount)) - { - /*Read out the data*/ - readData = LPSPI_ReadData(base); - - /*Decrease the read RX register times.*/ - --handle->readRegRemainingTimes; - - if (handle->rxRemainingByteCount < handle->bytesEachRead) - { - handle->bytesEachRead = handle->rxRemainingByteCount; - } - - LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); - handle->rxData += handle->bytesEachRead; - - /*Decrease the remaining RX byte count.*/ - handle->rxRemainingByteCount -= handle->bytesEachRead; - } - - /* Re-enable the interrupts only if rxCount indicates there is more data to receive, - * else we may get a spurious interrupt. - * */ - if (handle->rxRemainingByteCount) - { - /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - } - - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) - { - base->FCR = - (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | - LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); - } - } - - if (handle->txRemainingByteCount) - { - LPSPI_MasterTransferFillUpTxFifo(base, handle); - } - else - { - if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) - { - if ((handle->isPcsContinuous) && (handle->writeTcrInIsr)) - { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - handle->writeTcrInIsr = false; - } - } - } - - if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0) && (!handle->writeTcrInIsr)) - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ - if (handle->rxData == NULL) - { - if (LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag) - { - /* Complete the transfer and disable the interrupts */ - LPSPI_MasterTransferComplete(base, handle); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TransferCompleteInterruptEnable); - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - } - } - else - { - /* Complete the transfer and disable the interrupts */ - LPSPI_MasterTransferComplete(base, handle); - } - } -} - -/*Transactional APIs -- Slave*/ -void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - lpspi_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - s_lpspiHandle[LPSPI_GetInstance(base)] = handle; - - /* Set irq handler. */ - s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; - - handle->callback = callback; - handle->userData = userData; -} - -status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - handle->state = kLPSPI_Busy; - - bool isRxMask = false; - bool isTxMask = false; - - uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_SlaveByteSwap); - - /*Set the RX and TX watermarks to reduce the ISR times.*/ - uint8_t txWatermark; - if (handle->fifoSize > 1) - { - txWatermark = 1; - handle->rxWatermark = handle->fifoSize - 2; - } - else - { - txWatermark = 0; - handle->rxWatermark = 0; - } - LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/ - if (handle->rxData == NULL) - { - isRxMask = true; - handle->rxRemainingByteCount = 0; - } - - /*If there is not txData , can mask the transmit data (no data is loaded from transmit FIFO and output pin - * is tristated). - */ - if (handle->txData == NULL) - { - isTxMask = true; - handle->txRemainingByteCount = 0; - } - - base->TCR = (base->TCR & - ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK | - LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | - LPSPI_TCR_PCS(whichPcs); - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - } - - /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , - * and you should also enable the INTMUX interupt in your application. - */ - EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); - - /*TCR is also shared the FIFO , so wait for TCR written.*/ - while (LPSPI_GetTxFifoCount(base) != 0) - { - } - - /*Fill up the TX data in FIFO */ - if (handle->txData) - { - LPSPI_SlaveTransferFillUpTxFifo(base, handle); - } - - /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - if (handle->rxData) - { - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= handle->rxWatermark) - { - base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); - } - - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); - } - - if (handle->rxData) - { - /* RX FIFO overflow request enable */ - LPSPI_EnableInterrupts(base, kLPSPI_ReceiveErrorInterruptEnable); - } - if (handle->txData) - { - /* TX FIFO underflow request enable */ - LPSPI_EnableInterrupts(base, kLPSPI_TransmitErrorInterruptEnable); - } - - return kStatus_Success; -} - -static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - uint32_t wordToSend = 0; - - while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - - if (handle->txRemainingByteCount == 0) - { - break; - } - } -} - -static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - status_t status = 0; - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - if (handle->state == kLPSPI_Error) - { - status = kStatus_LPSPI_Error; - } - else - { - status = kStatus_Success; - } - - handle->state = kLPSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, status, handle->userData); - } -} - -status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - if (handle->rxData) - { - remainingByte = handle->rxRemainingByteCount; - } - else - { - remainingByte = handle->txRemainingByteCount; - } - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - - LPSPI_Reset(base); - - handle->state = kLPSPI_Idle; - handle->txRemainingByteCount = 0; - handle->rxRemainingByteCount = 0; -} - -void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - uint32_t readData; /* variable to store word read from RX FIFO */ - uint32_t wordToSend; /* variable to store word to write to TX FIFO */ - - if (handle->rxData != NULL) - { - if (handle->rxRemainingByteCount > 0) - { - while (LPSPI_GetRxFifoCount(base)) - { - /*Read out the data*/ - readData = LPSPI_ReadData(base); - - /*Decrease the read RX register times.*/ - --handle->readRegRemainingTimes; - - if (handle->rxRemainingByteCount < handle->bytesEachRead) - { - handle->bytesEachRead = handle->rxRemainingByteCount; - } - - LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); - handle->rxData += handle->bytesEachRead; - - /*Decrease the remaining RX byte count.*/ - handle->rxRemainingByteCount -= handle->bytesEachRead; - - if ((handle->txRemainingByteCount > 0) && (handle->txData != NULL)) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - } - - if (handle->rxRemainingByteCount == 0) - { - break; - } - } - } - - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) - { - base->FCR = - (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | - LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); - } - } - else if ((handle->txRemainingByteCount) && (handle->txData != NULL)) - { - LPSPI_SlaveTransferFillUpTxFifo(base, handle); - } - else - { - __NOP(); - } - - if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0)) - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ - if (handle->rxData == NULL) - { - if ((LPSPI_GetStatusFlags(base) & kLPSPI_FrameCompleteFlag) && (LPSPI_GetTxFifoCount(base) == 0)) - { - /* Complete the transfer and disable the interrupts */ - LPSPI_SlaveTransferComplete(base, handle); - } - else - { - LPSPI_ClearStatusFlags(base, kLPSPI_FrameCompleteFlag); - LPSPI_EnableInterrupts(base, kLPSPI_FrameCompleteInterruptEnable); - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - } - } - else - { - /* Complete the transfer and disable the interrupts */ - LPSPI_SlaveTransferComplete(base, handle); - } - } - - /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ - if ((LPSPI_GetStatusFlags(base) & kLPSPI_TransmitErrorFlag) && (base->IER & LPSPI_IER_TEIE_MASK)) - { - LPSPI_ClearStatusFlags(base, kLPSPI_TransmitErrorFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kLPSPI_Error; - } - handle->errorCount++; - } - /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ - if ((LPSPI_GetStatusFlags(base) & kLPSPI_ReceiveErrorFlag) && (base->IER & LPSPI_IER_REIE_MASK)) - { - LPSPI_ClearStatusFlags(base, kLPSPI_ReceiveErrorFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kLPSPI_Error; - } - handle->errorCount++; - } -} - -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap) -{ - assert(txData); - - uint32_t wordToSend = 0; - - switch (bytesEachWrite) - { - case 1: - wordToSend = *txData; - ++txData; - break; - - case 2: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - - break; - - case 3: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - break; - - case 4: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 24U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 24U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - break; - - default: - assert(false); - break; - } - return wordToSend; -} - -static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) -{ - assert(rxData); - - switch (bytesEachRead) - { - case 1: - *rxData = readData; - ++rxData; - break; - - case 2: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - } - else - { - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - case 3: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - } - else - { - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - case 4: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - } - else - { - *rxData = readData >> 24; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - default: - assert(false); - break; - } -} - -static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) -{ - if (LPSPI_IsMaster(base)) - { - s_lpspiMasterIsr(base, (lpspi_master_handle_t *)param); - } - else - { - s_lpspiSlaveIsr(base, (lpspi_slave_handle_t *)param); - } -} - -#if defined(LPSPI0) -void LPSPI0_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[0]); - LPSPI_CommonIRQHandler(LPSPI0, s_lpspiHandle[0]); -} -#endif - -#if defined(LPSPI1) -void LPSPI1_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[1]); - LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); -} -#endif - -#if defined(LPSPI2) -void LPSPI2_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[2]); - LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); -} -#endif - -#if defined(LPSPI3) -void LPSPI3_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[3]); - LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); -} -#endif - -#if defined(LPSPI4) -void LPSPI4_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[4]); - LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); -} -#endif - -#if defined(LPSPI5) -void LPSPI5_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[5]); - LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); -} -#endif - -#if defined(DMA_LPSPI0) -void DMA_SPI0_INT_IRQHandler(void) -{ - assert(s_lpspiHandle[0]); - LPSPI_CommonIRQHandler(DMA_LPSPI0, s_lpspiHandle[0]); -} -#endif - -#if defined(DMA_LPSPI1) -void DMA_SPI1_INT_IRQHandler(void) -{ - assert(s_lpspiHandle[1]); - LPSPI_CommonIRQHandler(DMA_LPSPI1, s_lpspiHandle[1]); -} -#endif -#if defined(DMA_LPSPI2) -void DMA_SPI2_INT_IRQHandler(void) -{ - assert(s_lpspiHandle[2]); - LPSPI_CommonIRQHandler(DMA_LPSPI2, s_lpspiHandle[2]); -} -#endif - -#if defined(DMA_LPSPI3) -void DMA_SPI3_INT_IRQHandler(void) -{ - assert(s_lpspiHandle[3]); - LPSPI_CommonIRQHandler(DMA_LPSPI3, s_lpspiHandle[3]); -} -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.h deleted file mode 100644 index cfac80f2c6980fdbfa528e6f750ba88d05086eba..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi.h +++ /dev/null @@ -1,1098 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPSPI_H_ -#define _FSL_LPSPI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpspi_driver - * @{ - */ - -/********************************************************************************************************************** - * Definitions - *********************************************************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPSPI driver version 2.0.1. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#ifndef LPSPI_DUMMY_DATA -/*! @brief LPSPI dummy data if no Tx data.*/ -#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ -#endif - -/*! @brief Status for the LPSPI driver.*/ -enum _lpspi_status -{ - kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ - kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ - kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ - kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ -}; - -/*! @brief LPSPI status flags in SPIx_SR register.*/ -enum _lpspi_flags -{ - kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ - kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ - kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ - kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ - kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ - kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ - kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ - kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ - kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ - kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | - LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | - LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ -}; - -/*! @brief LPSPI interrupt source.*/ -enum _lpspi_interrupt_enable -{ - kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ - kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ - kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ - kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ - kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ - kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ - kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ - kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ - kLPSPI_AllInterruptEnable = - (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | - LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ -}; - -/*! @brief LPSPI DMA source.*/ -enum _lpspi_dma_enable -{ - kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ - kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ -}; - -/*! @brief LPSPI master or slave mode configuration.*/ -typedef enum _lpspi_master_slave_mode -{ - kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ - kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ -} lpspi_master_slave_mode_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ -typedef enum _lpspi_which_pcs_config -{ - kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ - kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ - kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ - kLPSPI_Pcs3 = 3U /*!< PCS[3] */ -} lpspi_which_pcs_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ -typedef enum _lpspi_pcs_polarity_config -{ - kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ - kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ -} lpspi_pcs_polarity_config_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ -enum _lpspi_pcs_polarity -{ - kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ - kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ - kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ - kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ - kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ -}; - -/*! @brief LPSPI clock polarity configuration.*/ -typedef enum _lpspi_clock_polarity -{ - kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ - kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ -} lpspi_clock_polarity_t; - -/*! @brief LPSPI clock phase configuration.*/ -typedef enum _lpspi_clock_phase -{ - kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the - following edge.*/ - kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the - following edge.*/ -} lpspi_clock_phase_t; - -/*! @brief LPSPI data shifter direction options.*/ -typedef enum _lpspi_shift_direction -{ - kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ - kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ -} lpspi_shift_direction_t; - -/*! @brief LPSPI Host Request select configuration. */ -typedef enum _lpspi_host_request_select -{ - kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ - kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ -} lpspi_host_request_select_t; - -/*! @brief LPSPI Match configuration options. */ -typedef enum _lpspi_match_config -{ - kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ - kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ - kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ - kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ -} lpspi_match_config_t; - -/*! @brief LPSPI pin (SDO and SDI) configuration. */ -typedef enum _lpspi_pin_config -{ - kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ - kLPSPI_SdoInSdoOut = 1U, /*!< LPSPI SDO input, SDO output. */ - kLPSPI_SdiInSdiOut = 2U, /*!< LPSPI SDI input, SDI output. */ - kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ -} lpspi_pin_config_t; - -/*! @brief LPSPI data output configuration. */ -typedef enum _lpspi_data_out_config -{ - kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ - kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ -} lpspi_data_out_config_t; - -/*! @brief LPSPI transfer width configuration. */ -typedef enum _lpspi_transfer_width -{ - kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ - kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ - kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ -} lpspi_transfer_width_t; - -/*! @brief LPSPI delay type selection.*/ -typedef enum _lpspi_delay_type -{ - kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ - kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ - kLPSPI_BetweenTransfer /*!< Delay between transfers. */ -} lpspi_delay_type_t; - -#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ -#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ - -/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ -enum _lpspi_transfer_config_flag_for_master -{ - kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ - kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ - kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ - kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ - - kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ - - kLPSPI_MasterByteSwap = - 1U << 22 /*!< Is master swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - */ -}; - -#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ -#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ - -/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ -enum _lpspi_transfer_config_flag_for_slave -{ - kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ - kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ - kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ - kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ - - kLPSPI_SlaveByteSwap = - 1U << 22 /*!< Is slave swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - */ -}; - -/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ -enum _lpspi_transfer_state -{ - kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ - kLPSPI_Busy, /*!< Transfer queue is not finished. */ - kLPSPI_Error /*!< Transfer error. */ -}; - -/*! @brief LPSPI master configuration structure.*/ -typedef struct _lpspi_master_config -{ - uint32_t baudRate; /*!< Baud Rate for LPSPI. */ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ - lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ - lpspi_clock_phase_t cpha; /*!< Clock phase. */ - lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. - It sets the boundary value if out of range.*/ - uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum - delay. It sets the boundary value if out of range.*/ - uint32_t - betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum - delay. It sets the boundary value if out of range.*/ - - lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ - lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ - - lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data - *during single bit transfers.*/ - - lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated - * between accesses (LPSPI_PCS is negated). */ -} lpspi_master_config_t; - -/*! @brief LPSPI slave configuration structure.*/ -typedef struct _lpspi_slave_config -{ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ - lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ - lpspi_clock_phase_t cpha; /*!< Clock phase. */ - lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ - lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ - - lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data - *during single bit transfers.*/ - - lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated - * between accesses (LPSPI_PCS is negated). */ -} lpspi_slave_config_t; - -/*! -* @brief Forward declaration of the _lpspi_master_handle typedefs. -*/ -typedef struct _lpspi_master_handle lpspi_master_handle_t; - -/*! -* @brief Forward declaration of the _lpspi_slave_handle typedefs. -*/ -typedef struct _lpspi_slave_handle lpspi_slave_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * @param base LPSPI peripheral address. - * @param handle Pointer to the handle for the LPSPI master. - * @param status Success or error code describing whether the transfer is completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, - lpspi_master_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief Slave completion callback function pointer type. - * - * @param base LPSPI peripheral address. - * @param handle Pointer to the handle for the LPSPI slave. - * @param status Success or error code describing whether the transfer is completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief LPSPI master/slave transfer structure.*/ -typedef struct _lpspi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - volatile size_t dataSize; /*!< Transfer bytes. */ - - uint32_t - configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the - transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer - is used for slave.*/ -} lpspi_transfer_t; - -/*! @brief LPSPI master transfer handle structure used for transactional API. */ -struct _lpspi_master_handle -{ - volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ - volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ - - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/*! @brief LPSPI slave transfer handle structure used for transactional API. */ -struct _lpspi_slave_handle -{ - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ - - lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/********************************************************************************************************************** - * API - *********************************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the LPSPI master. - * - * @param base LPSPI peripheral address. - * @param masterConfig Pointer to structure lpspi_master_config_t. - * @param srcClock_Hz Module source input clock in Hertz - */ -void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Sets the lpspi_master_config_t structure to default values. - * - * This API initializes the configuration structure for LPSPI_MasterInit(). - * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified - * before calling the LPSPI_MasterInit(). - * Example: - * @code - * lpspi_master_config_t masterConfig; - * LPSPI_MasterGetDefaultConfig(&masterConfig); - * @endcode - * @param masterConfig pointer to lpspi_master_config_t structure - */ -void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); - -/*! - * @brief LPSPI slave configuration. - * - * @param base LPSPI peripheral address. - * @param slaveConfig Pointer to a structure lpspi_slave_config_t. - */ -void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); - -/*! - * @brief Sets the lpspi_slave_config_t structure to default values. - * - * This API initializes the configuration structure for LPSPI_SlaveInit(). - * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified - * before calling the LPSPI_SlaveInit(). - * Example: - * @code - * lpspi_slave_config_t slaveConfig; - * LPSPI_SlaveGetDefaultConfig(&slaveConfig); - * @endcode - * @param slaveConfig pointer to lpspi_slave_config_t structure. - */ -void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); - -/*! - * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. - * @param base LPSPI peripheral address. - */ -void LPSPI_Deinit(LPSPI_Type *base); - -/*! - * @brief Restores the LPSPI peripheral to reset state. Note that this function - * sets all registers to reset state. As a result, the LPSPI module can't work after calling - * this API. - * @param base LPSPI peripheral address. -*/ -void LPSPI_Reset(LPSPI_Type *base); - -/*! - * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. - * - * @param base LPSPI peripheral address. - * @param enable Pass true to enable module, false to disable module. - */ -static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) -{ - if (enable) - { - base->CR |= LPSPI_CR_MEN_MASK; - } - else - { - base->CR &= ~LPSPI_CR_MEN_MASK; - } -} - -/*! - *@} -*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the LPSPI status flag state. - * @param base LPSPI peripheral address. - * @return The LPSPI status(in SR register). - */ -static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) -{ - return (base->SR); -} - -/*! - * @brief Gets the LPSPI Tx FIFO size. - * @param base LPSPI peripheral address. - * @return The LPSPI Tx FIFO size. - */ -static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base) -{ - return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); -} - -/*! - * @brief Gets the LPSPI Rx FIFO size. - * @param base LPSPI peripheral address. - * @return The LPSPI Rx FIFO size. - */ -static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base) -{ - return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); -} - -/*! - * @brief Gets the LPSPI Tx FIFO count. - * @param base LPSPI peripheral address. - * @return The number of words in the transmit FIFO. - */ -static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) -{ - return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); -} - -/*! - * @brief Gets the LPSPI Rx FIFO count. - * @param base LPSPI peripheral address. - * @return The number of words in the receive FIFO. - */ -static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) -{ - return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); -} - -/*! - * @brief Clears the LPSPI status flag. - * - * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the - * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. - * Example usage: - * @code - * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); - * @endcode - * - * @param base LPSPI peripheral address. - * @param statusFlags The status flag used from type _lpspi_flags. - */ -static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) -{ - base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ -} - -/*! - *@} -*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the LPSPI interrupts. - * - * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. - * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. - * - * @code - * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. - */ -static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disables the LPSPI interrupts. - * - * @code - * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. - */ -static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! - *@} -*/ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the LPSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. - * @code - * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. - */ -static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) -{ - base->DER |= mask; -} - -/*! - * @brief Disables the LPSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. - * @code - * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. - */ -static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) -{ - base->DER &= ~mask; -} - -/*! - * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. - * - * This function gets the LPSPI Transmit Data Register address because this value is needed - * for the DMA operation. - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The LPSPI Transmit Data Register address. - */ -static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) -{ - return (uint32_t) & (base->TDR); -} - -/*! - * @brief Gets the LPSPI Receive Data Register address for a DMA operation. - * - * This function gets the LPSPI Receive Data Register address because this value is needed - * for the DMA operation. - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The LPSPI Receive Data Register address. - */ -static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) -{ - return (uint32_t) & (base->RDR); -} - -/*! - *@} -*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the LPSPI for either master or slave. - * - * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). - * - * @param base LPSPI peripheral address. - * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. - */ -static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) -{ - base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); -} - -/*! - * @brief Returns whether the LPSPI module is in master mode. - * - * @param base LPSPI peripheral address. - * @return Returns true if the module is in master mode or false if the module is in slave mode. - */ -static inline bool LPSPI_IsMaster(LPSPI_Type *base) -{ - return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); -} - -/*! - * @brief Flushes the LPSPI FIFOs. - * - * @param base LPSPI peripheral address. - * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. - * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. - */ -static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) -{ - base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); -} - -/*! - * @brief Sets the transmit and receive FIFO watermark values. - * - * This function allows the user to set the receive and transmit FIFO watermarks. The function - * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be - * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. - * - * @param base LPSPI peripheral address. - * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. - * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. - */ -static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) -{ - base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); -} - -/*! - * @brief Configures all LPSPI peripheral chip select polarities simultaneously. - * - * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). - * - * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of - * PCS is device-specific. - * @code - * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. - */ -static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) -{ - base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); -} - -/*! - * @brief Configures the frame size. - * - * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal - * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word - * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not - * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. - * - * Note 1 : The transmit command register should be initialized before enabling the LPSPI in slave mode, although - * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command - * register - * should only be changed if the LPSPI is idle. - * - * Note 2 : The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That - * means the TCR register should be written to when the Tx FIFO is not full. - * - * @param base LPSPI peripheral address. - * @param frameSize The frame size in number of bits. - */ -static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) -{ - base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); -} - -/*! - * @brief Sets the LPSPI baud rate in bits per second. - * - * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest - * possible baud rate without exceeding the desired baud rate and returns the - * calculated baud rate in bits-per-second. It requires the caller to provide - * the frequency of the module source clock (in Hertz). Note that the baud rate - * does not go into effect until the Transmit Control Register (TCR) is programmed - * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue - * parameter for later programming in the TCR. The higher level - * peripheral driver should alert the user of an out of range baud rate input. - * - * Note that the LPSPI module must first be disabled before configuring this. - * Note that the LPSPI module must be configured for master mode before configuring this. - * - * @param base LPSPI peripheral address. - * @param baudRate_Bps The desired baud rate in bits per second. - * @param srcClock_Hz Module source input clock in Hertz. - * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. - * @return The actual calculated baud rate. This function may also return a "0" if the - * LPSPI is not configured for master mode or if the LPSPI module is not disabled. - */ - -uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz, - uint32_t *tcrPrescaleValue); - -/*! - * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to - * change the delay values). - * - * This function configures the following: - * SCK to PCS delay, or - * PCS to SCK delay, or - * The configurations must occur between the transfer delay. - * - * The delay names are available in type lpspi_delay_type_t. - * - * The user passes the desired delay along with the delay value. - * This allows the user to directly set the delay values if they have - * pre-calculated them or if they simply wish to manually increment the value. - * - * Note that the LPSPI module must first be disabled before configuring this. - * Note that the LPSPI module must be configured for master mode before configuring this. - * - * @param base LPSPI peripheral address. - * @param scaler The 8-bit delay value 0x00 to 0xFF (255). - * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. - */ -void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); - -/*! - * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be - * disabled to change the delay values). - * - * This function calculates the values for the following: - * SCK to PCS delay, or - * PCS to SCK delay, or - * The configurations must occur between the transfer delay. - * - * The delay names are available in type lpspi_delay_type_t. - * - * The user passes the desired delay and the desired delay value in - * nano-seconds. The function calculates the value needed for the desired delay parameter - * and returns the actual calculated delay because an exact delay match may not be possible. In this - * case, the closest match is calculated without going below the desired delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in - * which case the maximum supported delay is returned. It is up to the higher level - * peripheral driver to alert the user of an out of range delay input. - * - * Note that the LPSPI module must be configured for master mode before configuring this. And note that - * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). - * - * @param base LPSPI peripheral address. - * @param delayTimeInNanoSec The desired delay value in nano-seconds. - * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. - * @param srcClock_Hz Module source input clock in Hertz. - * @return actual Calculated delay value in nano-seconds. - */ -uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, - uint32_t delayTimeInNanoSec, - lpspi_delay_type_t whichDelay, - uint32_t srcClock_Hz); - -/*! - * @brief Writes data into the transmit data buffer. - * - * This function writes data passed in by the user to the Transmit Data Register (TDR). - * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, - * the user has to manage sending the data one 32-bit word at a time. - * Any writes to the TDR result in an immediate push to the transmit FIFO. - * This function can be used for either master or slave modes. - * - * @param base LPSPI peripheral address. - * @param data The data word to be sent. - */ -static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) -{ - base->TDR = data; -} - -/*! - * @brief Reads data from the data buffer. - * - * This function reads the data from the Receive Data Register (RDR). - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The data read from the data buffer. - */ -static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) -{ - return (base->RDR); -} - -/*! - * @brief Set up the dummy data. - * - * @param base LPSPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - * Note: - * This API has no effect when LPSPI in slave interrupt mode, because driver - * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit - * FIFO and output pin is tristated. - */ -void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); - -/*! - *@} -*/ - -/*! - * @name Transactional - * @{ - */ -/*Transactional APIs*/ - -/*! - * @brief Initializes the LPSPI master handle. - * - * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a - * specified LPSPI instance, call this API once to get the initialized handle. - - * @param base LPSPI peripheral address. - * @param handle LPSPI handle pointer to lpspi_master_handle_t. - * @param callback DSPI callback. - * @param userData callback function parameter. - */ -void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, - lpspi_master_handle_t *handle, - lpspi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief LPSPI master transfer data using a polling method. - * - * This function transfers data using a polling method. This is a blocking function, which does not return until all - * transfers have been - * completed. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); - -/*! - * @brief LPSPI master transfer data using an interrupt method. - * - * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. - * When all data - * is transferred, the callback function is called. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); - -/*! - * @brief Gets the master transfer remaining bytes. - * - * This function gets the master transfer remaining bytes. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); - -/*! - * @brief LPSPI master abort transfer which uses an interrupt method. - * - * This function aborts a transfer which uses an interrupt method. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - */ -void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! - * @brief LPSPI Master IRQ handler function. - * - * This function processes the LPSPI transmit and receive IRQ. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - */ -void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! - * @brief Initializes the LPSPI slave handle. - * - * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a - * specified LPSPI instance, call this API once to get the initialized handle. - * - * @param base LPSPI peripheral address. - * @param handle LPSPI handle pointer to lpspi_slave_handle_t. - * @param callback DSPI callback. - * @param userData callback function parameter. - */ -void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - lpspi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief LPSPI slave transfer data using an interrupt method. - * - * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. - * When all data - * is transferred, the callback function is called. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); - -/*! - * @brief Gets the slave transfer remaining bytes. - * - * This function gets the slave transfer remaining bytes. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @return status of status_t. - */ -status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); - -/*! - * @brief LPSPI slave aborts a transfer which uses an interrupt method. - * - * This function aborts a transfer which uses an interrupt method. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - */ -void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! - * @brief LPSPI Slave IRQ handler function. - * - * This function processes the LPSPI transmit and receives an IRQ. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - */ -void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! - *@} -*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - /*! - *@} - */ - -#endif /*_FSL_LPSPI_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.c deleted file mode 100644 index 68f78ff0993c81e00c39c81d306b161050993886..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.c +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpspi_edma.h" - -/*********************************************************************************************************************** -* Definitons -***********************************************************************************************************************/ -/*! -* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. -*/ -typedef struct _lpspi_master_edma_private_handle -{ - LPSPI_Type *base; /*!< LPSPI peripheral base address. */ - lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ -} lpspi_master_edma_private_handle_t; - -/*! -* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. -*/ -typedef struct _lpspi_slave_edma_private_handle -{ - LPSPI_Type *base; /*!< LPSPI peripheral base address. */ - lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ -} lpspi_slave_edma_private_handle_t; - -/*********************************************************************************************************************** -* Prototypes -***********************************************************************************************************************/ -/*! -* @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -/*! -* @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); -/*! -* @brief Get instance number for LPSPI module. -* This is not a public API and it's extern from fsl_lpspi.c. -* @param base LPSPI peripheral base address -*/ -extern uint32_t LPSPI_GetInstance(LPSPI_Type *base); - -/*! -* @brief Check the argument for transfer . -* This is not a public API. It's extern from fsl_lpspi.c. -*/ -extern bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); - -static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); - -/*********************************************************************************************************************** -* Variables -***********************************************************************************************************************/ - -/*! @brief Pointers to lpspi edma handles for each instance. */ -static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; -static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t s_dummyData[]; -/*********************************************************************************************************************** -* Code -***********************************************************************************************************************/ -static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) -{ - assert(rxData); - - switch (bytesEachRead) - { - case 1: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - } - else - { - *rxData = readData >> 24; - ++rxData; - } - break; - - case 2: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - } - else - { - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - } - break; - - case 4: - - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - - break; - - default: - assert(false); - break; - } -} - -void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, - lpspi_master_edma_handle_t *handle, - lpspi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = LPSPI_GetInstance(base); - - s_lpspiMasterEdmaPrivateHandle[instance].base = base; - s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /*And since the dma transfer can not support 3 bytes .*/ - if ((bytesPerFrame % 4U) == 3) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - uint32_t instance = LPSPI_GetInstance(base); - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ - uint8_t txWatermark = 0; - uint8_t rxWatermark = 0; - - /*Used for byte swap*/ - uint32_t dif = 0; - - uint8_t bytesLastWrite = 0; - - bool isThereExtraTxBytes = false; - - uint8_t dummyData = s_dummyData[instance]; - - edma_transfer_config_t transferConfigRx; - edma_transfer_config_t transferConfigTx; - - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); - edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); - - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is - * hard to controlled by software. - */ - base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | - LPSPI_TCR_PCS(whichPcs); - - isThereExtraTxBytes = false; - handle->isThereExtraRxBytes = false; - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - - handle->bytesLastRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - - handle->bytesLastRead = 4; - - if ((transfer->dataSize % 4) != 0) - { - bytesLastWrite = transfer->dataSize % 4; - handle->bytesLastRead = bytesLastWrite; - - isThereExtraTxBytes = true; - - --handle->writeRegRemainingTimes; - - --handle->readRegRemainingTimes; - handle->isThereExtraRxBytes = true; - } - } - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, - &s_lpspiMasterEdmaPrivateHandle[instance]); - - /*Rx*/ - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - if (handle->rxData) - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigRx.destOffset = 1; - } - else - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigRx.destOffset = 0; - } - transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; - break; - - default: - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; - transferConfigRx.srcOffset = 0; - - transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; - - /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ - handle->nbytes = transferConfigRx.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigRx, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - - /*Tx*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - if (isThereExtraTxBytes) - { - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (bytesLastWrite) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_extraBytes); - - if (handle->isPcsContinuous) - { - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); - } - else - { - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); - } - } - - if (handle->isPcsContinuous) - { - handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); - - transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); - transferConfigTx.srcOffset = 0; - - transferConfigTx.destAddr = (uint32_t) & (base->TCR); - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_pcsContinuous); - EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); - } - - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - - transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; - - if (isThereExtraTxBytes) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_extraBytes); - } - else if (handle->isPcsContinuous) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_pcsContinuous); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, NULL); - } - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); - - return kStatus_Success; -} - -static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_lpspiEdmaPrivateHandle); - - uint32_t readData; - - lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; - - lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; - - LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - - if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) - { - while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) - { - } - readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); - - if (lpspiEdmaPrivateHandle->handle->rxData) - { - LPSPI_SeparateEdmaReadData( - &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - - lpspiEdmaPrivateHandle->handle->bytesLastRead]), - readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); - } - } - - lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; - - if (lpspiEdmaPrivateHandle->handle->callback) - { - lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, - kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); - } -} - -void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) -{ - assert(handle); - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = kLPSPI_Idle; -} - -status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - remainingByte = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, - lpspi_slave_edma_handle_t *handle, - lpspi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = LPSPI_GetInstance(base); - - s_lpspiSlaveEdmaPrivateHandle[instance].base = base; - s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - - uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /*And since the dma transfer can not support 3 bytes .*/ - if ((bytesPerFrame % 4U) == 3) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); - - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ - uint8_t txWatermark = 0; - uint8_t rxWatermark = 0; - - /*Used for byte swap*/ - uint32_t dif = 0; - - uint8_t bytesLastWrite = 0; - - uint32_t instance = LPSPI_GetInstance(base); - - edma_transfer_config_t transferConfigRx; - edma_transfer_config_t transferConfigTx; - - bool isThereExtraTxBytes = false; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); - - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is - * hard to controlled by software. - */ - base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | - LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); - - isThereExtraTxBytes = false; - handle->isThereExtraRxBytes = false; - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - - handle->bytesLastRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - - handle->bytesLastRead = 4; - - if ((transfer->dataSize % 4) != 0) - { - bytesLastWrite = transfer->dataSize % 4; - handle->bytesLastRead = bytesLastWrite; - - isThereExtraTxBytes = true; - --handle->writeRegRemainingTimes; - - handle->isThereExtraRxBytes = true; - --handle->readRegRemainingTimes; - } - } - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, - &s_lpspiSlaveEdmaPrivateHandle[instance]); - - /*Rx*/ - if (handle->readRegRemainingTimes > 0) - { - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - if (handle->rxData) - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigRx.destOffset = 1; - } - else - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigRx.destOffset = 0; - } - transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; - break; - - default: - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; - transferConfigRx.srcOffset = 0; - - transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = transferConfigRx.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigRx, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - } - - /*Tx*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - if (isThereExtraTxBytes) - { - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (bytesLastWrite) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_extraBytes); - - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); - } - - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - - transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; - - if (isThereExtraTxBytes) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_extraBytes); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, NULL); - } - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); - - return kStatus_Success; -} - -static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_lpspiEdmaPrivateHandle); - - uint32_t readData; - - lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; - - lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; - - LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - - if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) - { - while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) - { - } - readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); - - if (lpspiEdmaPrivateHandle->handle->rxData) - { - LPSPI_SeparateEdmaReadData( - &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - - lpspiEdmaPrivateHandle->handle->bytesLastRead]), - readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); - } - } - - lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; - - if (lpspiEdmaPrivateHandle->handle->callback) - { - lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, - kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); - } -} - -void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) -{ - assert(handle); - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = kLPSPI_Idle; -} - -status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - remainingByte = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.h deleted file mode 100644 index d35981e4332def318d039904ad67f5839d68f062..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpspi_edma.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPSPI_EDMA_H_ -#define _FSL_LPSPI_EDMA_H_ - -#include "fsl_lpspi.h" -#include "fsl_edma.h" - -/*! - * @addtogroup lpspi_edma_driver - * @{ - */ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! -* @brief Forward declaration of the _lpspi_master_edma_handle typedefs. -*/ -typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; - -/*! -* @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. -*/ -typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base LPSPI peripheral base address. - * @param handle Pointer to the handle for the LPSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, - lpspi_master_edma_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base LPSPI peripheral base address. - * @param handle Pointer to the handle for the LPSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, - lpspi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ -struct _lpspi_master_edma_handle -{ - volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ - - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */ - - volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR . */ - volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ - uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ - - uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ - - edma_handle_t *edmaRxRegToRxDataHandle; /*!CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | - LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); - - /* Configure the prescale value and clock source */ - base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | - LPTMR_PSR_PCS(config->prescalerClockSource)); -} - -void LPTMR_Deinit(LPTMR_Type *base) -{ - /* Disable the LPTMR and reset the internal logic */ - base->CSR &= ~LPTMR_CSR_TEN_MASK; - -#if defined(LPTMR_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPTMR_GetInstance(base); - - /* Gate the LPTMR clock*/ - CLOCK_DisableClock(s_lptmrClocks[instance]); -#if defined(LPTMR_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* LPTMR_CLOCKS */ -} - -void LPTMR_GetDefaultConfig(lptmr_config_t *config) -{ - assert(config); - - /* Use time counter mode */ - config->timerMode = kLPTMR_TimerModeTimeCounter; - /* Use input 0 as source in pulse counter mode */ - config->pinSelect = kLPTMR_PinSelectInput_0; - /* Pulse input pin polarity is active-high */ - config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - /* Counter resets whenever TCF flag is set */ - config->enableFreeRunning = false; - /* Bypass the prescaler */ - config->bypassPrescaler = true; - /* LPTMR clock source */ - config->prescalerClockSource = kLPTMR_PrescalerClock_1; - /* Divide the prescaler clock by 2 */ - config->value = kLPTMR_Prescale_Glitch_0; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lptmr.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lptmr.h deleted file mode 100644 index bad57e88a6a9ccccdb9ca9990dc2247a1871e24f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lptmr.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPTMR_H_ -#define _FSL_LPTMR_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lptmr - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ -/*@}*/ - -/*! @brief LPTMR pin selection used in pulse counter mode.*/ -typedef enum _lptmr_pin_select -{ - kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ - kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ - kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ - kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ -} lptmr_pin_select_t; - -/*! @brief LPTMR pin polarity used in pulse counter mode.*/ -typedef enum _lptmr_pin_polarity -{ - kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ - kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ -} lptmr_pin_polarity_t; - -/*! @brief LPTMR timer mode selection.*/ -typedef enum _lptmr_timer_mode -{ - kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ - kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ -} lptmr_timer_mode_t; - -/*! @brief LPTMR prescaler/glitch filter values*/ -typedef enum _lptmr_prescaler_glitch_value -{ - kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ - kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ - kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ - kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ - kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ - kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ - kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ - kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ - kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ - kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ - kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ - kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ - kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ - kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ - kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ - kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ -} lptmr_prescaler_glitch_value_t; - -/*! - * @brief LPTMR prescaler/glitch filter clock select. - * @note Clock connections are SoC-specific - */ -typedef enum _lptmr_prescaler_clock_select -{ - kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ - kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ - kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ - kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ -} lptmr_prescaler_clock_select_t; - -/*! @brief List of the LPTMR interrupts */ -typedef enum _lptmr_interrupt_enable -{ - kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ -} lptmr_interrupt_enable_t; - -/*! @brief List of the LPTMR status flags */ -typedef enum _lptmr_status_flags -{ - kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ -} lptmr_status_flags_t; - -/*! - * @brief LPTMR config structure - * - * This structure holds the configuration settings for the LPTMR peripheral. To initialize this - * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a - * pointer to your configuration structure instance. - * - * The configuration struct can be made constant so it resides in flash. - */ -typedef struct _lptmr_config -{ - lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ - lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ - lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ - bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow - False: counter is reset when the compare flag is set */ - bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */ - lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ - lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ -} lptmr_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation. - * - * @note This API should be called at the beginning of the application using the LPTMR driver. - * - * @param base LPTMR peripheral base address - * @param config A pointer to the LPTMR configuration structure. - */ -void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); - -/*! - * @brief Gates the LPTMR clock. - * - * @param base LPTMR peripheral base address - */ -void LPTMR_Deinit(LPTMR_Type *base); - -/*! - * @brief Fills in the LPTMR configuration structure with default settings. - * - * The default values are as follows. - * @code - * config->timerMode = kLPTMR_TimerModeTimeCounter; - * config->pinSelect = kLPTMR_PinSelectInput_0; - * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; - * config->enableFreeRunning = false; - * config->bypassPrescaler = true; - * config->prescalerClockSource = kLPTMR_PrescalerClock_1; - * config->value = kLPTMR_Prescale_Glitch_0; - * @endcode - * @param config A pointer to the LPTMR configuration structure. - */ -void LPTMR_GetDefaultConfig(lptmr_config_t *config); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= mask; - base->CSR = reg; -} - -/*! - * @brief Disables the selected LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t. - */ -static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~mask; - base->CSR = reg; -} - -/*! - * @brief Gets the enabled LPTMR interrupts. - * - * @param base LPTMR peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::lptmr_interrupt_enable_t - */ -static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TIE_MASK); -} - -/*! @}*/ - -#if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE) -/*! - * @brief Enable or disable timer DMA request - * - * @param base base LPTMR peripheral base address - * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable. - */ -static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable) -{ - if(enable) - { - base->CSR |= LPTMR_CSR_TDRE_MASK; - } - else - { - base->CSR &= ~(LPTMR_CSR_TDRE_MASK); - } -} -#endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the LPTMR status flags. - * - * @param base LPTMR peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::lptmr_status_flags_t - */ -static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) -{ - return (base->CSR & LPTMR_CSR_TCF_MASK); -} - -/*! - * @brief Clears the LPTMR status flags. - * - * @param base LPTMR peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::lptmr_status_flags_t. - */ -static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) -{ - base->CSR |= mask; -} - -/*! @}*/ - -/*! - * @name Read and write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers counts from 0 until it equals the count value set here. The count value is written to - * the CMR register. - * - * @note - * 1. The TCF flag is set with the CNR equals the count provided here and then increments. - * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. - * - * @param base LPTMR peripheral base address - * @param ticks A timer period in units of ticks, which should be equal or greater than 1. - */ -static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) -{ - assert(ticks > 0); - base->CMR = ticks - 1; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value in a range from 0 to a - * timer period. - * - * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. - * - * @param base LPTMR peripheral base address - * - * @return The current counter value in ticks - */ -static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) -{ - /* Must first write any value to the CNR. This synchronizes and registers the current value - * of the CNR into a temporary register which can then be read - */ - base->CNR = 0U; - return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT); -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer. - * - * After calling this function, the timer counts up to the CMR register value. - * Each time the timer reaches the CMR value and then increments, it generates a - * trigger pulse and sets the timeout interrupt flag. An interrupt is also - * triggered if the timer interrupt is enabled. - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StartTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg |= LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! - * @brief Stops the timer. - * - * This function stops the timer and resets the timer's counter register. - * - * @param base LPTMR peripheral base address - */ -static inline void LPTMR_StopTimer(LPTMR_Type *base) -{ - uint32_t reg = base->CSR; - - /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ - reg &= ~(LPTMR_CSR_TCF_MASK); - reg &= ~LPTMR_CSR_TEN_MASK; - base->CSR = reg; -} - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPTMR_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c deleted file mode 100644 index c65a934efd0d880b21b73623c1658cd192636ad7..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c +++ /dev/null @@ -1,1459 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpuart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* LPUART transfer state. */ -enum _lpuart_transfer_states -{ - kLPUART_TxIdle, /*!< TX idle. */ - kLPUART_TxBusy, /*!< TX busy. */ - kLPUART_RxIdle, /*!< RX idle. */ - kLPUART_RxBusy /*!< RX busy. */ -}; - -/* Typedef for interrupt handler. */ -typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the LPUART instance from peripheral base address. - * - * @param base LPUART peripheral base address. - * @return LPUART instance. - */ -uint32_t LPUART_GetInstance(LPUART_Type *base); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @userData handle LPUART handle pointer. - * @return Length of received data in RX ring buffer. - */ -static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Check whether the RX ring buffer is full. - * - * @userData handle LPUART handle pointer. - * @retval true RX ring buffer is full. - * @retval false RX ring buffer is not full. - */ -static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Write to TX register using non-blocking method. - * - * This function writes data to the TX register directly, upper layer must make - * sure the TX register is empty or TX FIFO has empty room before calling this function. - * - * @note This function does not check whether all the data has been sent out to bus, - * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is - * finished. - * - * @param base LPUART peripheral base address. - * @param data Start addresss of the data to write. - * @param length Size of the buffer to be sent. - */ -static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX register using non-blocking method. - * - * This function reads data from the TX register directly, upper layer must make - * sure the RX register is full or TX FIFO has data before calling this function. - * - * @param base LPUART peripheral base address. - * @param data Start addresss of the buffer to store the received data. - * @param length Size of the buffer. - */ -static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Array of LPUART handle. */ -static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT]; -/* Array of LPUART peripheral base address. */ -static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; -/* Array of LPUART IRQ number. */ -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; -static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; -#else -static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; -#endif -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of LPUART clock name. */ -static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; - -#if defined(LPUART_PERIPH_CLOCKS) -/* Array of LPUART functional clock name. */ -static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* LPUART ISR for transactional APIs. */ -static lpuart_isr_t s_lpuartIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -uint32_t LPUART_GetInstance(LPUART_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++) - { - if (s_lpuartBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpuartBases)); - - return instance; -} - -static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - size_t size; - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - bool full; - - if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - size_t i; - - /* The Non Blocking write data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { - base->DATA = data[i]; - } -} - -static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - size_t i; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* The Non Blocking read data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - data[i] = (base->DATA & 0x7F); - } - else - { - data[i] = base->DATA; - } -#else - data[i] = base->DATA; -#endif - } -} - -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) -{ - assert(config); - assert(config->baudRate_Bps); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); -#endif - - uint32_t temp; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = config->baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - config->baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff > ((config->baudRate_Bps / 100) * 3)) - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPUART_GetInstance(base); - - /* Enable lpuart clock */ - CLOCK_EnableClock(s_lpuartClock[instance]); -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - /*Reset all internal logic and registers, except the Global Register */ - LPUART_SoftwareReset(base); -#else - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); -#endif - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Set bit count and parity mode. */ - base->BAUD &= ~LPUART_BAUD_M10_MASK; - - temp = base->CTRL & - ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK); - - temp |= - (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType); - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (kLPUART_SevenDataBits == config->dataBitsCount) - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ - } - else - { - temp |= LPUART_CTRL_M7_MASK; - } - } - else -#endif - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ - } - } - - base->CTRL = temp; - -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - /* set stop bit per char */ - temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; - base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Set tx/rx WATER watermark - Note: - Take care of the RX FIFO, RX interrupt request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - RX interrupt because the water mark is 2. - */ - base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); - - /* Enable tx/rx FIFO */ - base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); - - /* Flush FIFO */ - base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); -#endif - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - /* Set the CTS configuration/TX CTS source. */ - base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); - if (config->enableRxRTS) - { - /* Enable the receiver RTS(request-to-send) function. */ - base->MODIR |= LPUART_MODIR_RXRTSE_MASK; - } - if (config->enableTxCTS) - { - /* Enable the CTS(clear-to-send) function. */ - base->MODIR |= LPUART_MODIR_TXCTSE_MASK; - } -#endif - - /* Set data bits order. */ - if (config->isMsb) - { - temp |= LPUART_STAT_MSBF_MASK; - } - else - { - temp &= ~LPUART_STAT_MSBF_MASK; - } - - base->STAT |= temp; - - /* Enable TX/RX base on configure structure. */ - temp = base->CTRL; - if (config->enableTx) - { - temp |= LPUART_CTRL_TE_MASK; - } - - if (config->enableRx) - { - temp |= LPUART_CTRL_RE_MASK; - } - - base->CTRL = temp; - - return kStatus_Success; -} -void LPUART_Deinit(LPUART_Type *base) -{ - uint32_t temp; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Wait tx FIFO send out*/ - while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) - { - } -#endif - /* Wait last char shoft out */ - while (0 == (base->STAT & LPUART_STAT_TC_MASK)) - { - } - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - - base->STAT |= temp; - - /* Disable the module. */ - base->CTRL = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = LPUART_GetInstance(base); - - /* Disable lpuart clock */ - CLOCK_DisableClock(s_lpuartClock[instance]); - -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPUART_GetDefaultConfig(lpuart_config_t *config) -{ - assert(config); - - config->baudRate_Bps = 115200U; - config->parityMode = kLPUART_ParityDisabled; - config->dataBitsCount = kLPUART_EightDataBits; - config->isMsb = false; -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - config->stopBitCount = kLPUART_OneStopBit; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - config->txFifoWatermark = 0; - config->rxFifoWatermark = 0; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - config->enableRxRTS = false; - config->enableTxCTS = false; - config->txCtsConfig = kLPUART_CtsSampleAtStart; - config->txCtsSource = kLPUART_CtsSourcePin; -#endif - config->rxIdleType = kLPUART_IdleTypeStartBit; - config->rxIdleConfig = kLPUART_IdleCharacter1; - config->enableTx = false; - config->enableRx = false; -} - -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - assert(baudRate_Bps); - - uint32_t temp, oldCtrl; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff < ((baudRate_Bps / 100) * 3)) - { - /* Store CTRL before disable Tx and Rx */ - oldCtrl = base->CTRL; - - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Restore CTRL. */ - base->CTRL = oldCtrl; - - return kStatus_Success; - } - else - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } -} - -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | - ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL |= mask; -} - -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & - ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL &= ~mask; -} - -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) -{ - uint32_t temp; - temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; -#endif - temp |= (base->CTRL & 0xFF0C000); - - return temp; -} - -uint32_t LPUART_GetStatusFlags(LPUART_Type *base) -{ - uint32_t temp; - temp = base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & - (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> - 16; -#endif - return temp; -} - -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) -{ - uint32_t temp; - status_t status; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp = (uint32_t)base->FIFO; - temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); - temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); - base->FIFO = temp; -#endif - temp = (uint32_t)base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); - temp |= mask & LPUART_STAT_LBKDIF_MASK; -#endif - temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); - temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); - temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); -#endif - base->STAT = temp; - /* If some flags still pending. */ - if (mask & LPUART_GetStatusFlags(base)) - { - /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, - kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, - kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ - status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ - } - else - { - status = kStatus_Success; - } - - return status; -} - -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - /* This API can only ensure that the data is written into the data buffer but can't - ensure all data in the data buffer are sent into the transmit shift buffer. */ - while (length--) - { - while (!(base->STAT & LPUART_STAT_TDRE_MASK)) - { - } - base->DATA = *(data++); - } -} - -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - uint32_t statusFlag; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - while (length--) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) -#else - while (!(base->STAT & LPUART_STAT_RDRF_MASK)) -#endif - { - statusFlag = LPUART_GetStatusFlags(base); - - if (statusFlag & kLPUART_RxOverrunFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - return kStatus_LPUART_RxHardwareOverrun; - } - - if (statusFlag & kLPUART_NoiseErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); - return kStatus_LPUART_NoiseError; - } - - if (statusFlag & kLPUART_FramingErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); - return kStatus_LPUART_FramingError; - } - - if (statusFlag & kLPUART_ParityErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); - return kStatus_LPUART_ParityError; - } - } -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - *(data++) = (base->DATA & 0x7F); - } - else - { - *(data++) = base->DATA; - } -#else - *(data++) = base->DATA; -#endif - } - - return kStatus_Success; -} - -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* Zero the handle. */ - memset(handle, 0, sizeof(lpuart_handle_t)); - - /* Set the TX/RX state. */ - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - /* Initial seven data bits flag */ - handle->isSevenDataBits = isSevenDataBits; -#endif - - /* Get instance from peripheral base address. */ - instance = LPUART_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_lpuartHandle[instance] = handle; - - s_lpuartIsr = LPUART_TransferHandleIRQ; - -/* Enable interrupt in NVIC. */ -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ - EnableIRQ(s_lpuartRxIRQ[instance]); - EnableIRQ(s_lpuartTxIRQ[instance]); -#else - EnableIRQ(s_lpuartIRQ[instance]); -#endif -} - -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize) -{ - assert(handle); - assert(ringBuffer); - - /* Setup the ring buffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); -} - -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kLPUART_RxIdle) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - status_t status; - - /* Return error if current TX busy. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kLPUART_TxBusy; - - /* Enable transmiter interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kLPUART_TxIdle; -} - -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to lpuart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to lpuart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable LPUART RX IRQ, protect ring buffer. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to LPUART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - } - /* Enable LPUART RX IRQ if previously enabled. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - - /* Enable RX interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - uint8_t count; - uint8_t tempCount; - - /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) - { - /* Clear overrun flag, otherwise the RX does not work. */ - base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); - } - } - - /* If IDLE flag is set and the IDLE interrupt is enabled. */ - if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); - - while ((count) && (handle->rxDataSize)) - { - tempCount = MIN(handle->rxDataSize, count); - - /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) - { - handle->rxState = kLPUART_RxIdle; - - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } -#endif - /* Clear IDLE flag.*/ - base->STAT |= LPUART_STAT_IDLE_MASK; - - /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) - { - LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable); - } - /* If callback is not NULL and rxDataSize is not 0. */ - if ((handle->callback) && (handle->rxDataSize)) - { - handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); - } - } - /* Receive data register full */ - if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) - { -/* Get the size that can be stored into buffer for this interrupt. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); -#else - count = 1; -#endif - - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - while ((count) && (handle->rxDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->rxDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kLPUART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - - /* If use RX ring buffer, receive data to ring buffer. */ - if (handle->rxRingBuffer) - { - while (count--) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - -/* Read data. */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (handle->isSevenDataBits) - { - handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F); - } - else - { - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; - } -#else - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; -#endif - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) - { -/* Get the bytes that available at this moment. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - - ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); -#else - count = 1; -#endif - - while ((count) && (handle->txDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->txDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to write the data to the registers. */ - LPUART_WriteNonBlocking(base, handle->txData, tempCount); - handle->txData += tempCount; - handle->txDataSize -= tempCount; - count -= tempCount; - - /* If all the data are written to data register, notify user with the callback, then TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kLPUART_TxIdle; - - /* Disable TX register empty interrupt. */ - base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); - } - } - } - } -} - -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - /* To be implemented by User. */ -} -#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART0_LPUART1_RX_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -} -void LPUART0_LPUART1_TX_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -} -#else -void LPUART0_LPUART1_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -} -#endif -#endif - -#if defined(LPUART0) -#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART0_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -void LPUART0_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -#else -void LPUART0_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -} -#endif -#endif -#endif - -#if defined(LPUART1) -#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART1_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -void LPUART1_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -#else -void LPUART1_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -} -#endif -#endif -#endif - -#if defined(LPUART2) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART2_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -void LPUART2_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -#else -void LPUART2_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -} -#endif -#endif - -#if defined(LPUART3) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART3_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -void LPUART3_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -#else -void LPUART3_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -} -#endif -#endif - -#if defined(LPUART4) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART4_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -void LPUART4_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -#else -void LPUART4_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -} -#endif -#endif - -#if defined(LPUART5) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART5_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -void LPUART5_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -#else -void LPUART5_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -} -#endif -#endif - -#if defined(CM4_0_LPUART) -void M4_0_LPUART_DriverIRQHandler(void) -{ - s_lpuartIsr(CM4_0_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0_LPUART)]); -} -#endif - -#if defined(CM4_1_LPUART) -void M4_1_LPUART_DriverIRQHandler(void) -{ - s_lpuartIsr(CM4_1_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1_LPUART)]); -} -#endif - -#if defined(DMA_LPUART0) -void DMA_UART0_INT_IRQHandler(void) -{ - s_lpuartIsr(DMA_LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART0)]); -} -#endif - -#if defined(DMA_LPUART1) -void DMA_UART1_INT_IRQHandler(void) -{ - s_lpuartIsr(DMA_LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART1)]); -} -#endif - -#if defined(DMA_LPUART2) -void DMA_UART2_INT_IRQHandler(void) -{ - s_lpuartIsr(DMA_LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART2)]); -} -#endif - -#if defined(DMA_LPUART3) -void DMA_UART3_INT_IRQHandler(void) -{ - s_lpuartIsr(DMA_LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART3)]); -} -#endif - -#if defined(DMA_LPUART4) -void DMA_UART4_INT_IRQHandler(void) -{ - s_lpuartIsr(DMA_LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART4)]); -} -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h deleted file mode 100644 index 6e448723dd56330cce479a27b087b377e4adc991..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h +++ /dev/null @@ -1,842 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPUART_H_ -#define _FSL_LPUART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpuart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPUART driver version 2.2.3. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) -/*@}*/ - -/*! @brief Error codes for the LPUART driver. */ -enum _lpuart_status -{ - kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ - kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ - kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ - kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ - kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ - kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ - kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ - kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ - kStatus_LPUART_RxRingBufferOverrun = - MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ - kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ - kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ - kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ - kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ - kStatus_LPUART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ - kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ -}; - -/*! @brief LPUART parity mode. */ -typedef enum _lpuart_parity_mode -{ - kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} lpuart_parity_mode_t; - -/*! @brief LPUART data bits count. */ -typedef enum _lpuart_data_bits -{ - kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ -#endif -} lpuart_data_bits_t; - -/*! @brief LPUART stop bit count. */ -typedef enum _lpuart_stop_bit_count -{ - kLPUART_OneStopBit = 0U, /*!< One stop bit */ - kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ -} lpuart_stop_bit_count_t; - -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT -/*! @brief LPUART transmit CTS source. */ -typedef enum _lpuart_transmit_cts_source -{ - kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ - kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ -} lpuart_transmit_cts_source_t; - -/*! @brief LPUART transmit CTS configure. */ -typedef enum _lpuart_transmit_cts_config -{ - kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ - kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ -} lpuart_transmit_cts_config_t; -#endif - -/*! @brief LPUART idle flag type defines when the receiver starts counting. */ -typedef enum _lpuart_idle_type_select -{ - kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ - kLPUART_IdleTypeStopBit = 1U, /*!< Start conuting after a stop bit. */ -} lpuart_idle_type_select_t; - -/*! @brief LPUART idle detected configuration. - * This structure defines the number of idle characters that must be received before - * the IDLE flag is set. - */ -typedef enum _lpuart_idle_config -{ - kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ -} lpuart_idle_config_t; - -/*! - * @brief LPUART interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all LPUART interrupt configurations. - */ -enum _lpuart_interrupt_enable -{ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ -#endif - kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ - kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ - kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ - kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ - kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ - kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ - kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ - kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ - kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ - kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ -#endif -}; - -/*! - * @brief LPUART status flags. - * - * This provides constants for the LPUART status flags for use in the LPUART functions. - */ -enum _lpuart_flags -{ - kLPUART_TxDataRegEmptyFlag = - (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ - kLPUART_TransmissionCompleteFlag = - (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ - kLPUART_RxDataRegFullFlag = - (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ - kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ - kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is - read from receive register */ - kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these - samples differ, noise flag sets */ - kLPUART_FramingErrorFlag = - (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ - kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char - detected and LIN circuit enabled */ -#endif - kLPUART_RxActiveEdgeFlag = - (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ - kLPUART_RxActiveFlag = - (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ - kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kLPUART_NoiseErrorInRxDataRegFlag = - (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ - kLPUART_ParityErrorInRxDataRegFlag = - (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ - kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ - kLPUART_TxFifoOverflowFlag = - (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ - kLPUART_RxFifoUnderflowFlag = - (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ -#endif -}; - -/*! @brief LPUART configuration structure. */ -typedef struct _lpuart_config -{ - uint32_t baudRate_Bps; /*!< LPUART baud rate */ - lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ - bool isMsb; /*!< Data bits order, LSB (default), MSB */ -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - uint8_t txFifoWatermark; /*!< TX FIFO watermark */ - uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - bool enableRxRTS; /*!< RX RTS enable */ - bool enableTxCTS; /*!< TX CTS enable */ - lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ - lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ -#endif - lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ - lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ - bool enableTx; /*!< Enable TX */ - bool enableRx; /*!< Enable RX */ -} lpuart_config_t; - -/*! @brief LPUART transfer structure. */ -typedef struct _lpuart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} lpuart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_handle lpuart_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); - -/*! @brief LPUART handle structure. */ -struct _lpuart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - lpuart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state. */ - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - bool isSevenDataBits; /*!< Seven data bits flag. */ -#endif -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - -/*! - * @name Software Reset - * @{ - */ - -/*! - * @brief Resets the LPUART using software. - * - * This function resets all internal logic and registers except the Global Register. - * Remains set until cleared by software. - * - * @param base LPUART peripheral base address. - */ -static inline void LPUART_SoftwareReset(LPUART_Type *base) -{ - base->GLOBAL |= LPUART_GLOBAL_RST_MASK; - base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; -} -/* @} */ -#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. - * - * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function - * to configure the configuration structure and get the default configuration. - * The example below shows how to use this API to configure the LPUART. - * @code - * lpuart_config_t lpuartConfig; - * lpuartConfig.baudRate_Bps = 115200U; - * lpuartConfig.parityMode = kLPUART_ParityDisabled; - * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig.isMsb = false; - * lpuartConfig.stopBitCount = kLPUART_OneStopBit; - * lpuartConfig.txFifoWatermark = 0; - * lpuartConfig.rxFifoWatermark = 1; - * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param config Pointer to a user-defined configuration structure. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success LPUART initialize succeed - */ -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a LPUART instance. - * - * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. - * - * @param base LPUART peripheral base address. - */ -void LPUART_Deinit(LPUART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the LPUART configuration structure to a default value. The default - * values are: - * lpuartConfig->baudRate_Bps = 115200U; - * lpuartConfig->parityMode = kLPUART_ParityDisabled; - * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig->isMsb = false; - * lpuartConfig->stopBitCount = kLPUART_OneStopBit; - * lpuartConfig->txFifoWatermark = 0; - * lpuartConfig->rxFifoWatermark = 1; - * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; - * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; - * lpuartConfig->enableTx = false; - * lpuartConfig->enableRx = false; - * - * @param config Pointer to a configuration structure. - */ -void LPUART_GetDefaultConfig(lpuart_config_t *config); - -/*! - * @brief Sets the LPUART instance baudrate. - * - * This function configures the LPUART module baudrate. This function is used to update - * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. - * @code - * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param baudRate_Bps LPUART baudrate to be set. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. - * @retval kStatus_Success Set baudrate succeeded. - */ -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets LPUART status flags. - * - * This function gets all LPUART status flags. The flags are returned as the logical - * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _lpuart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. - */ -uint32_t LPUART_GetStatusFlags(LPUART_Type *base); - -/*! - * @brief Clears status flags with a provided mask. - * - * This function clears LPUART status flags with a provided mask. Automatically cleared flags - * can't be cleared by this function. - * Flags that can only cleared or set by hardware are: - * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, - * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag - * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. - * - * @param base LPUART peripheral base address. - * @param mask the status flags to be cleared. The user can use the enumerators in the - * _lpuart_status_flag_t to do the OR operation and get the mask. - * @return 0 succeed, others failed. - * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but - * it is cleared automatically by hardware. - * @retval kStatus_Success Status in the mask are cleared. - */ -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables LPUART interrupts according to a provided mask. - * - * This function enables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. - * This examples shows how to enable TX empty interrupt and RX full interrupt: - * @code - * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. - */ -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Disables LPUART interrupts according to a provided mask. - * - * This function disables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. - */ -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Gets enabled LPUART interrupts. - * - * This function gets the enabled LPUART interrupts. The enabled interrupts are returned - * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check - * a specific interrupt enable status, compare the return value with enumerators - * in @ref _lpuart_interrupt_enable. - * For example, to check whether the TX empty interrupt is enabled: - * @code - * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); - * - * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. - */ -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); - -#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE -/*! - * @brief Gets the LPUART data register address. - * - * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. - * - * @param base LPUART peripheral base address. - * @return LPUART data register addresses which are used both by the transmitter and receiver. - */ -static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) -{ - return (uint32_t) & (base->DATA); -} - -/*! - * @brief Enables or disables the LPUART transmitter DMA request. - * - * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_TDMAE_MASK; - base->CTRL |= LPUART_CTRL_TIE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; - base->CTRL &= ~LPUART_CTRL_TIE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver DMA. - * - * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_RDMAE_MASK; - base->CTRL |= LPUART_CTRL_RIE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; - base->CTRL &= ~LPUART_CTRL_RIE_MASK; - } -} - -/* @} */ -#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables or disables the LPUART transmitter. - * - * This function enables or disables the LPUART transmitter. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_TE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_TE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver. - * - * This function enables or disables the LPUART receiver. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_RE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_RE_MASK; - } -} - -/*! - * @brief Writes to the transmitter register. - * - * This function writes data to the transmitter register directly. The upper layer must - * ensure that the TX register is empty or that the TX FIFO has room before calling this function. - * - * @param base LPUART peripheral base address. - * @param data Data write to the TX register. - */ -static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) -{ - base->DATA = data; -} - -/*! - * @brief Reads the receiver register. - * - * This function reads data from the receiver register directly. The upper layer must - * ensure that the receiver register is full or that the RX FIFO has data before calling this function. - * - * @param base LPUART peripheral base address. - * @return Data read from data register. - */ -static inline uint8_t LPUART_ReadByte(LPUART_Type *base) -{ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); - - if (isSevenDataBits) - { - return (base->DATA & 0x7F); - } - else - { - return base->DATA; - } -#else - return base->DATA; -#endif -} - -/*! - * @brief Writes to the transmitter register using a blocking method. - * - * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have - * room, and writes data to the transmitter buffer. - * - * @note This function does not check whether all data has been sent out to the bus. - * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is - * finished. - * - * @param base LPUART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); - -/*! -* @brief Reads the receiver data register using a blocking method. - * - * This function polls the receiver register, waits for the receiver register full or receiver FIFO - * has data, and reads data from the TX register. - * - * @param base LPUART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. - * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. - * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. - * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. - * @retval kStatus_Success Successfully received all data. - */ -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle. - * - * This function initializes the LPUART handle, which can be used for other LPUART - * transactional APIs. Usually, for a specified LPUART instance, - * call this API once to get the initialized handle. - * - * The LPUART driver supports the "background" receiving, which means that user can set up - * an RX ring buffer optionally. Data received is stored into the ring buffer even when the - * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * The ring buffer is disabled if passing NULL as @p ringBuffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData); -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function send data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data written to the transmitter register. When - * all data is written to the TX register in the ISR, the LPUART driver calls the callback - * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. - * - * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written - * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, - * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received is stored into the ring buffer even when - * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are not sent out. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been written to the LPUART transmitter register. - * - * This function gets the number of bytes that have been written to LPUART TX - * register by an interrupt method. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using the interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function - * which returns without waiting to ensure that all data are received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough for read, the receive - * request is saved by the LPUART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the LPUART driver notifies the upper layer - * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. - * The 5 bytes are copied to xfer->data, which returns with the - * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is - * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to xfer->data. When all data is received, the upper layer is notified. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into the transmit queue. - * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief LPUART IRQ handle function. - * - * This function handles the LPUART transmit and receive IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief LPUART Error IRQ handle function. - * - * This function handles the LPUART error IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.c deleted file mode 100644 index 3b42c3619bea0c9b466a3307aed0573b02913917..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_lpuart_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - assert(param); - - lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint32_t instance = LPUART_GetInstance(base); - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Note: - Take care of the RX FIFO, EDMA request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - EDMA transfer because the water mark is 2. - */ - if (rxEdmaHandle) - { - base->WATER &= (~LPUART_WATER_RXWATER_MASK); - } -#endif - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); - } -} - -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txState = kLPUART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - handle->rxState = kLPUART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->txEdmaHandle); - - /* Disable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->txEdmaHandle); - - handle->txState = kLPUART_TxIdle; -} - -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->rxEdmaHandle); - - /* Disable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->rxEdmaHandle); - - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.h deleted file mode 100644 index ac1969ab6e7302f3ad4be63144a1efef2cd061d8..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart_edma.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPUART_EDMA_H_ -#define _FSL_LPUART_EDMA_H_ - -#include "fsl_lpuart.h" -#include "fsl_edma.h" - -/*! - * @addtogroup lpuart_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_edma_handle lpuart_edma_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, - lpuart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief LPUART eDMA handle -*/ -struct _lpuart_edma_handle -{ - lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle which is used in transactional functions. - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txEdmaHandle User requested DMA handle for TX DMA transfer. - * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. - */ -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_LPUART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others fail. - * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using eDMA. - * - * This function aborts the sent data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Aborts the received data using eDMA. - * - * This function aborts the received data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes written to the LPUART TX register. - * - * This function gets the number of bytes written to the LPUART TX - * register by DMA. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*! - * @brief Gets the number of received bytes. - * - * This function gets the number of received bytes. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.c deleted file mode 100644 index dc008596ef835d3620ec4bbff8f65368bd492498..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mmdvsq.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned) -{ - uint32_t temp = 0; - - temp = base->CSR; - temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); - /* Prepare setting for calculation */ - temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(true); - /* Write setting to CSR register */ - base->CSR = temp; - /* Write dividend to DEND register */ - base->DEND = dividend; - /* Write divisor to DSOR register and start calculation if Fast-Start is enabled */ - base->DSOR = divisor; - /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */ - base->CSR |= MMDVSQ_CSR_SRT_MASK; - /* Return remainder, if divide-by-zero is enabled and occurred, reading from - * RES result is error terminated */ - return base->RES; -} - -int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned) -{ - uint32_t temp = 0; - - temp = base->CSR; - temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); - /* Prepare setting for calculation */ - temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(false); - /* Write setting mode to CSR register */ - base->CSR = temp; - /* Write dividend to DEND register */ - base->DEND = dividend; - /* Write divisor to DSOR register and start calculation when Fast-Start is enabled */ - base->DSOR = divisor; - /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */ - base->CSR |= MMDVSQ_CSR_SRT_MASK; - /* Return quotient, if divide-by-zero is enabled and occurred, reading from - * RES result is error terminated */ - return base->RES; -} - -uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand) -{ - /* Write radicand to RCND register , and start calculation */ - base->RCND = radicand; - /* Return result */ - return base->RES; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.h deleted file mode 100644 index 711203f40baf183090a3b2d49408a40f591911b2..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mmdvsq.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_MMDVSQ_H_ -#define _FSL_MMDVSQ_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mmdvsq - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_MMSVSQ_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ -/*@}*/ - -/*! @brief MMDVSQ execution status */ -typedef enum _mmdvsq_execution_status -{ - kMMDVSQ_IdleSquareRoot = 0x01U, /*!< MMDVSQ is idle; the last calculation was a square root */ - kMMDVSQ_IdleDivide = 0x02U, /*!< MMDVSQ is idle; the last calculation was division */ - kMMDVSQ_BusySquareRoot = 0x05U, /*!< MMDVSQ is busy processing a square root calculation */ - kMMDVSQ_BusyDivide = 0x06U /*!< MMDVSQ is busy processing a division calculation */ -} mmdvsq_execution_status_t; - -/*! @brief MMDVSQ divide fast start select */ -typedef enum _mmdvsq_fast_start_select -{ - kMMDVSQ_EnableFastStart = 0U, /*!< Division operation is initiated by a write to the DSOR register */ - kMMDVSQ_DisableFastStart = - 1U /*!< Division operation is initiated by a write to CSR[SRT] = 1; normal start instead fast start */ -} mmdvsq_fast_start_select_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name MMDVSQ functional Operation - * @{ - */ - -/*! - * @brief Performs the MMDVSQ division operation and returns the remainder. - * - * @param base MMDVSQ peripheral address - * @param dividend Dividend value - * @param divisor Divisor value - * @param isUnsigned Mode of unsigned divide - * - true unsigned divide - * - false signed divide - * - */ -int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned); - -/*! - * @brief Performs the MMDVSQ division operation and returns the quotient. - * - * @param base MMDVSQ peripheral address - * @param dividend Dividend value - * @param divisor Divisor value - * @param isUnsigned Mode of unsigned divide - * - true unsigned divide - * - false signed divide - * - */ -int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned); - -/*! - * @brief Performs the MMDVSQ square root operation. - * - * This function performs the MMDVSQ square root operation and returns the square root - * result of a given radicand value. - * - * @param base MMDVSQ peripheral address - * @param radicand Radicand value - * - */ -uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand); - -/* @} */ - -/*! - * @name MMDVSQ status Operation - * @{ - */ - -/*! - * @brief Gets the MMDVSQ execution status. - * - * This function checks the current MMDVSQ execution status of the combined - * CSR[BUSY, DIV, SQRT] indicators. - * - * @param base MMDVSQ peripheral address - * - * @return Current MMDVSQ execution status - */ -static inline mmdvsq_execution_status_t MMDVSQ_GetExecutionStatus(MMDVSQ_Type *base) -{ - return (mmdvsq_execution_status_t)(base->CSR >> MMDVSQ_CSR_SQRT_SHIFT); -} - -/*! - * @brief Configures MMDVSQ fast start mode. - * - * This function sets the MMDVSQ division fast start. The MMDVSQ supports two - * mechanisms for initiating a division operation. The default mechanism is - * a “fast start” where a write to the DSOR register begins the division. - * Alternatively, the start mechanism can begin after a write to the CSR - * register with CSR[SRT] set. - * - * @param base MMDVSQ peripheral address - * @param mode Mode of Divide-Fast-Start - * - kMmdvsqDivideFastStart = 0 - * - kMmdvsqDivideNormalStart = 1 - */ -static inline void MMDVSQ_SetFastStartConfig(MMDVSQ_Type *base, mmdvsq_fast_start_select_t mode) -{ - if (mode) - { - base->CSR |= MMDVSQ_CSR_DFS_MASK; - } - else - { - base->CSR &= ~MMDVSQ_CSR_DFS_MASK; - } -} - -/*! - * @brief Configures the MMDVSQ divide-by-zero mode. - * - * This function configures the MMDVSQ response to divide-by-zero - * calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read - * of the RES register is error-terminated to signal the processor of the - * attempted divide-by-zero. Otherwise, the register contents are returned. - * - * @param base MMDVSQ peripheral address - * @param isDivByZero Mode of Divide-By-Zero - * - kMmdvsqDivideByZeroDis = 0 - * - kMmdvsqDivideByZeroEn = 1 - */ -static inline void MMDVSQ_SetDivideByZeroConfig(MMDVSQ_Type *base, bool isDivByZero) -{ - if (isDivByZero) - { - base->CSR |= MMDVSQ_CSR_DZE_MASK; - } - else - { - base->CSR &= ~MMDVSQ_CSR_DZE_MASK; - } -} - -/* @} */ - -#if defined(__cplusplus) -} - -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_MMDVSQ_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c deleted file mode 100644 index ed982a6b348fb937711cbbb656d532ac7b0b310a..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_msmc.h" - -#if defined(__riscv) -#define CONFIG_NORMAL_SLEEP EVENT_UNIT->SLPCTRL = (EVENT_UNIT->SLPCTRL & ~0x03) | (1 << 0) -#define CONFIG_DEEP_SLEEP EVENT_UNIT->SLPCTRL |= 0x03; -#else -#define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk -#define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk -#endif - -status_t SMC_SetPowerModeRun(SMC_Type *base) -{ - uint32_t reg; - - reg = base->PMCTRL; - /* configure Normal RUN mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -status_t SMC_SetPowerModeHsrun(SMC_Type *base) -{ - uint32_t reg; - - reg = base->PMCTRL; - /* configure High Speed RUN mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -status_t SMC_SetPowerModeWait(SMC_Type *base) -{ - /* configure Normal Wait mode */ - CONFIG_NORMAL_SLEEP; - - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) -{ - uint32_t reg; - - /* configure the Partial Stop mode in Noraml Stop mode */ - reg = base->PMCTRL; - reg &= ~(SMC_PMCTRL_PSTOPO_MASK | SMC_PMCTRL_STOPM_MASK); - reg |= ((uint32_t)option << SMC_PMCTRL_PSTOPO_SHIFT) | (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ - CONFIG_DEEP_SLEEP; - - /* read back to make sure the configuration valid before entering stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - -#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) - /* check whether the power mode enter Stop mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -#else - return kStatus_Success; -#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ -} - -status_t SMC_SetPowerModeVlpr(SMC_Type *base) -{ - uint32_t reg; - - reg = base->PMCTRL; - /* configure VLPR mode */ - reg &= ~SMC_PMCTRL_RUNM_MASK; - reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); - base->PMCTRL = reg; - - return kStatus_Success; -} - -status_t SMC_SetPowerModeVlpw(SMC_Type *base) -{ - /* configure VLPW mode */ - /* Clear the SLEEPDEEP bit to disable deep sleep mode */ - CONFIG_NORMAL_SLEEP; - - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} - -status_t SMC_SetPowerModeVlps(SMC_Type *base) -{ - uint32_t reg; - - /* configure VLPS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - CONFIG_DEEP_SLEEP; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - -#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) - /* check whether the power mode enter Stop mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -#else - return kStatus_Success; -#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ -} - -status_t SMC_SetPowerModeLls(SMC_Type *base) -{ - uint32_t reg; - - /* configure to LLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - CONFIG_DEEP_SLEEP; - - /* read back to make sure the configuration valid before entering stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - -#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) - /* check whether the power mode enter Stop mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -#else - return kStatus_Success; -#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ -} - -#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) - -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) -status_t SMC_SetPowerModeVlls0(SMC_Type *base) -{ - uint32_t reg; - - /* configure to VLLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlls0 << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - CONFIG_DEEP_SLEEP; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ - -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) -status_t SMC_SetPowerModeVlls2(SMC_Type *base) -{ - uint32_t reg; - - /* configure to VLLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlls2 << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - CONFIG_DEEP_SLEEP; - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - - return kStatus_Success; -} -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ - -#else /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ -status_t SMC_SetPowerModeVlls(SMC_Type *base) -{ - uint32_t reg; - - /* configure to VLLS mode */ - reg = base->PMCTRL; - reg &= ~SMC_PMCTRL_STOPM_MASK; - reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); - base->PMCTRL = reg; - -#if defined(__riscv) - EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1); -#else - /* Set the SLEEPDEEP bit to enable deep sleep mode */ - CONFIG_DEEP_SLEEP; -#endif - - /* read back to make sure the configuration valid before enter stop mode */ - (void)base->PMCTRL; - __DSB(); - __WFI(); - __ISB(); - -#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) - /* check whether the power mode enter Stop mode succeed */ - if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) - { - return kStatus_SMC_StopAbort; - } - else - { - return kStatus_Success; - } -#else - return kStatus_Success; -#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ -} -#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ - -void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config) -{ - assert(config); - - uint32_t reg; - - reg = SMC_RPC_FILTCFG(config->slowClockFilterCount) | SMC_RPC_FILTEN(config->enableFilter); -#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN) - if (config->enableLpoFilter) - { - reg |= SMC_RPC_LPOFEN_MASK; - } -#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */ - - base->RPC = reg; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h deleted file mode 100644 index 8b0907be5392213f9796e1c961b348e14c99c80c..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h +++ /dev/null @@ -1,701 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MSMC_H_ -#define _FSL_MSMC_H_ - -#include "fsl_common.h" - -/*! @addtogroup msmc */ -/*! @{*/ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MSMC driver version 2.1.0. */ -#define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! - * @brief Power Modes Protection - */ -typedef enum _smc_power_mode_protection -{ - kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */ - kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */ - kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */ - kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */ - kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK | - SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode. */ -} smc_power_mode_protection_t; - -/*! - * @brief Power Modes in PMSTAT - */ -typedef enum _smc_power_state -{ - kSMC_PowerStateRun = 1U, /*!< 0000_0001 - Current power mode is RUN */ - kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode */ - kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ - kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ -} smc_power_state_t; - -/*! - * @brief Power Stop Entry Status in PMSTAT - */ -typedef enum _smc_power_stop_entry_status -{ - kSMC_PowerStopEntryAlt0 = 1U, /*!< Indicates a Stop mode entry since this field was last cleared. */ - kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */ - kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */ - kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */ - kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */ - kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */ -} smc_power_stop_entry_status_t; - -/*! - * @brief Run mode definition - */ -typedef enum _smc_run_mode -{ - kSMC_RunNormal = 0U, /*!< normal RUN mode. */ - kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */ - kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */ -} smc_run_mode_t; - -/*! - * @brief Stop mode definition - */ -typedef enum _smc_stop_mode -{ - kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ - kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */ - kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */ -#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) - kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */ -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */ -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) - kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */ -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ -#else - kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */ -#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ -} smc_stop_mode_t; - -/*! - * @brief Partial STOP option - */ -typedef enum _smc_partial_stop_mode -{ - kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ - kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ - kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ - kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/ -} smc_partial_stop_option_t; - -/*! - * @brief SMC configuration status - */ -enum _smc_status -{ - kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/ -}; - -/*! - * @brief System Reset Source Name definitions - */ -typedef enum _smc_reset_source -{ - kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */ - kSMC_SourcePor = SMC_SRS_POR_MASK, /*!< Power on reset */ - kSMC_SourceLvd = SMC_SRS_LVD_MASK, /*!< Low-voltage detect reset */ - kSMC_SourceHvd = SMC_SRS_HVD_MASK, /*!< High-voltage detect reset */ - kSMC_SourceWarm = SMC_SRS_WARM_MASK, /*!< Warm reset. Warm Reset flag will assert if any of the system reset - sources in this register assert (SRS[31:8]) */ - kSMC_SourceFatal = SMC_SRS_FATAL_MASK, /*!< Fatal reset */ - kSMC_SourceCore = - SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */ - kSMC_SourcePin = SMC_SRS_PIN_MASK, /*!< RESET_B pin reset. */ - kSMC_SourceMdm = SMC_SRS_MDM_MASK, /*!< MDM reset. */ - kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK, /*!< Reset Controller timeout reset. */ - kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */ - kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */ - kSMC_SourceWdog = SMC_SRS_WDOG_MASK, /*!< Watchdog reset */ - kSMC_SourceSoftware = SMC_SRS_SW_MASK, /*!< Software reset */ - kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK, /*!< Lockup reset. Core lockup or exception. */ - kSMC_SourceJtag = SMC_SRS_JTAG_MASK, /*!< JTAG system reset */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO) - kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */ -#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER) - kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */ -#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0) - kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */ -#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1) - kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */ -#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */ - /* Source All. */ - kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK | - SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK | - SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK | - SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK -#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO) - | - SMC_SRS_SECVIO_MASK -#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER) - | - SMC_SRS_TAMPER_MASK -#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0) - | - SMC_SRS_CORE0_MASK -#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */ -#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1) - | - SMC_SRS_CORE1_MASK -#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */ - , -} smc_reset_source_t; - -/*! - * @brief System reset interrupt enable bit definitions. - */ -typedef enum _smc_interrupt_enable -{ - kSMC_IntNone = 0U, /*!< No interrupt enabled. */ - kSMC_IntPin = SMC_SRIE_PIN_MASK, /*!< Pin reset interrupt. */ - kSMC_IntMdm = SMC_SRIE_MDM_MASK, /*!< MDM reset interrupt. */ - kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt. */ - kSMC_IntWdog = SMC_SRIE_WDOG_MASK, /*!< Watchdog interrupt. */ - kSMC_IntSoftware = SMC_SRIE_SW_MASK, /*!< Software reset interrupts. */ - kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK, /*!< Lock up interrupt. */ -#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0) - kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */ -#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */ -#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1) - kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */ -#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */ - kSMC_IntAll = SMC_SRIE_PIN_MASK | /*!< All system reset interrupts. */ - SMC_SRIE_MDM_MASK | - SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK -#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0) - | - SMC_SRIE_CORE0_MASK -#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */ -#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1) - | - SMC_SRIE_CORE1_MASK -#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */ -} smc_interrupt_enable_t; - -/*! - * @brief Reset pin filter configuration - */ -typedef struct _smc_reset_pin_filter_config -{ - uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles. */ - bool enableFilter; /*!< Reset pin filter enable/disable. */ -#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN) - bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */ -#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */ -} smc_reset_pin_filter_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name System mode controller APIs*/ -/*@{*/ - -/*! - * @brief Configures all power mode protection settings. - * - * This function configures the power mode protection settings for - * supported power modes in the specified chip family. The available power modes - * are defined in the smc_power_mode_protection_t. This should be done at an early - * system level initialization stage. See the reference manual for details. - * This register can only write once after the power reset. - * - * The allowed modes are passed as bit map, for example, to allow LLS and VLLS, - * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls). - * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). - * - * @param allowedModes Bitmap of the allowed power modes. - */ -static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) -{ - base->PMPROT = allowedModes; -} - -/*! - * @brief Gets the current power mode status. - * - * This function returns the current power mode stat. Once application - * switches the power mode, it should always check the stat to check whether it - * runs into the specified mode or not. An application should check - * this mode before switching to a different mode. The system requires that - * only certain modes can switch to other specific modes. See the - * reference manual for details and the smc_power_state_t for information about - * the power stat. - * - * @param base SMC peripheral base address. - * @return Current power mode status. - */ -static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) -{ - return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT); -} - -#if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) -/*! - * @brief Gets the result of the previous stop mode entry. - * - * This function returns the result of the previous stop mode entry. - * - * @param base SMC peripheral base address. - * @return Current power stop entry status. - */ -static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base) -{ - return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT); -} - -/*! - * @brief Clears all the result of the previous stop mode entry. - * - * This function clears all the result of the previous stop mode entry. - * - * @param base SMC peripheral base address. - * @return Current power stop entry status. - */ -static inline void SMC_ClearStopEntryStatus(SMC_Type *base) -{ - /* Only write 0x01 to clear this field, all other writes are ignored. */ - base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01); -} - -#endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */ - -/*! - * @brief Prepare to enter stop modes - * - * This function should be called before entering STOP/VLPS/LLS/VLLS modes. - */ -static inline void SMC_PreEnterStopModes(void) -{ - __disable_irq(); - __ISB(); -} - -/*! - * @brief Recovering after wake up from stop modes - * - * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. - * It is used together with @ref SMC_PreEnterStopModes. - */ -static inline void SMC_PostExitStopModes(void) -{ - __enable_irq(); - __ISB(); -} - -/*! - * @brief Prepare to enter wait modes - * - * This function should be called before entering WAIT/VLPW modes.. - */ -static inline void SMC_PreEnterWaitModes(void) -{ - __disable_irq(); - __ISB(); -} - -/*! - * @brief Recovering after wake up from stop modes - * - * This function should be called after wake up from WAIT/VLPW modes. - * It is used together with @ref SMC_PreEnterWaitModes. - */ -static inline void SMC_PostExitWaitModes(void) -{ - __enable_irq(); - __ISB(); -} - -/*! - * @brief Configure the system to RUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeRun(SMC_Type *base); - -/*! - * @brief Configure the system to HSRUN power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeHsrun(SMC_Type *base); - -/*! - * @brief Configure the system to WAIT power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeWait(SMC_Type *base); - -/*! - * @brief Configure the system to Stop power mode. - * - * @param base SMC peripheral base address. - * @param option Partial Stop mode option. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); - -/*! - * @brief Configure the system to VLPR power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpr(SMC_Type *base); - -/*! - * @brief Configure the system to VLPW power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlpw(SMC_Type *base); - -/*! - * @brief Configure the system to VLPS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlps(SMC_Type *base); -/*! - * @brief Configure the system to LLS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeLls(SMC_Type *base); - -#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) -/*! - * @brief Configure the system to VLLS0 power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls0(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ -#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) -/*! - * @brief Configure the system to VLLS2 power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls2(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */ -#else - /*! - * @brief Configure the system to VLLS power mode. - * - * @param base SMC peripheral base address. - * @return SMC configuration error code. - */ -status_t SMC_SetPowerModeVlls(SMC_Type *base); -#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ - -/*! - * @brief Gets the reset source status which caused a previous reset. - * - * This function gets the current reset source status. Use source masks - * defined in the smc_reset_source_t to get the desired source status. - * - * Example: - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog; - - // To test multiple reset sources. - resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin); - @endcode - * - * @param base SMC peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base) -{ - return base->SRS; -} - -/*! - * @brief Gets the sticky reset source status. - * - * This function gets the current reset source status that has not been cleared - * by software for some specific source. - * - * Example: - @code - uint32_t resetStatus; - - // To get all reset source statuses. - resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll; - - // To test whether the MCU is reset using Watchdog. - resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog; - - // To test multiple reset sources. - resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin); - @endcode - * - * @param base SMC peripheral base address. - * @return All reset source status bit map. - */ -static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base) -{ - return base->SSRS; -} - -/*! - * @brief Clears the sticky reset source status. - * - * This function clears the sticky system reset flags indicated by source masks. - * - * Example: - @code - // Clears multiple reset sources. - SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin)); - @endcode - * - * @param base SMC peripheral base address. - * @param sourceMasks reset source status bit map - */ -static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks) -{ - base->SSRS = sourceMasks; -} - -/*! - * @brief Configures the reset pin filter. - * - * This function sets the reset pin filter including the enablement/disablement and filter width. - * - * @param base SMC peripheral base address. - * @param config Pointer to the configuration structure. - */ -void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config); - -/*! - * @brief Sets the system reset interrupt configuration. - * - * For a graceful shut down, the MSMC supports delaying the assertion of the system - * reset for a period of time when the reset interrupt is generated. This function - * can be used to enable the interrupt. - * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details. - * For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows: - * SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin)); - * - * @param base SMC peripheral base address. - * @param intMask Bit mask of the system reset interrupts to enable. See - * smc_interrupt_enable_t for details. - */ -static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask) -{ - base->SRIE = intMask; -} - -/*! - * @brief Gets the source status of the system reset interrupt. - * - * This function gets the source status of the reset interrupt. Use source masks - * defined in the smc_interrupt_enable_t to get the desired source status. - * - * Example: - @code - uint32_t interruptStatus; - - // To get all reset interrupt source statuses. - interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll; - - // To test whether the reset interrupt of Watchdog is pending. - interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog; - - // To test multiple reset interrupt sources. - interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin); - @endcode - * - * @param base SMC peripheral base address. - * @return All reset interrupt source status bit map. - */ -static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base) -{ - return base->SRIF; -} - -/*! - * @brief Clears the source status of the system reset interrupt. - * - * This function clears the source status of the reset interrupt. Use source masks - * defined in the smc_interrupt_enable_t to get the desired source status. - * - * Example: - @code - uint32_t interruptStatus; - - // To clear all reset interrupt source statuses. - MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll); - - // To clear the reset interrupt of Watchdog. - SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog); - - // To clear multiple reset interrupt sources status. - SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin)); - @endcode - * - * @param base SMC peripheral base address. - * @param All reset interrupt source status bit map to clear. - */ -static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask) -{ - base->SRIF = intMask; -} - -#if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE) -/*! - * @brief Sets the core software reset feature configuration. - * - * The MSMC supports delaying the assertion of the system reset for a period of time while a core - * software reset is generated. This allows software to recover without reseting the entire system. - * This function can be used to enable/disable the core software reset feature. - * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details. - * For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows: - * SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin)); - * - * @param base SMC peripheral base address. - * @param intMask Bit mask of the core software reset to enable. See - * smc_interrupt_enable_t for details. - */ -static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask) -{ - base->CSRE = intMask; -} -#endif /* FSL_FEATURE_SMC_HAS_CSRE */ - -/*! - * @brief Gets the boot option configuration. - * - * This function gets the boot option configuration of MSMC. - * - * @param base SMC peripheral base address. - * @return The boot option configuration. 1 means boot option enabled. 0 means not. - */ -static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base) -{ - return base->MR; -} - -#if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM) -/*! - * @brief Sets the force boot option configuration. - * - * This function sets the focus boot option configuration of MSMC. It can force the corresponding - * boot option config to assert on next system reset. - * - * @param base SMC peripheral base address. - * @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not. - */ -static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val) -{ - base->FM = val; -} - -#if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR) -/*! - * @brief Enables the conresponding SRAM array in low power retention mode. - * - * This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is - * disabled, and only in RUN mode. - * - * @param base SMC peripheral base address. - * @param arrayIdx Index of responding SRAM array. - * @param enable Enable the SRAM array in low power retention mode. - */ -static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable) -{ - if (enable) - { - base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */ - } - else - { - base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */ - } -} -#endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */ - -#if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR) -/*! - * @brief Enables the conresponding SRAM array in STOP mode. - * - * This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes. - * When disabled, the corresponding SRAM array is powered off in STOP modes. - * - * @param base SMC peripheral base address. - * @param arrayIdx Index of responding SRAM array. - * @param enable Enable the SRAM array in STOP modes. - */ -static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable) -{ - if (enable) - { - base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */ - } - else - { - base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */ - } -} -#endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */ - -#endif /* FSL_FEATURE_SMC_HAS_FM */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_MSMC_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.c deleted file mode 100644 index 01d7a680f7b5793854ac36ec5e4edb2d08e0f3bb..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_mu.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to mu clocks for each instance. */ -static const clock_ip_name_t s_muClocks[] = MU_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointers to mu bases for each instance. */ -static MU_Type *const s_muBases[] = MU_BASE_PTRS; - -/****************************************************************************** - * Code - *****************************************************************************/ -static uint32_t MU_GetInstance(MU_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < (sizeof(s_muBases)/sizeof(s_muBases[0])); instance++) - { - if (s_muBases[instance] == base) - { - break; - } - } - - assert(instance < (sizeof(s_muBases)/sizeof(s_muBases[0]))); - - return instance; -} - -void MU_Init(MU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_muClocks[MU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void MU_Deinit(MU_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_muClocks[MU_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg) -{ - assert(regIndex < MU_TR_COUNT); - - /* Wait TX register to be empty. */ - while (!(base->SR & (kMU_Tx0EmptyFlag >> regIndex))) - { - } - - base->TR[regIndex] = msg; -} - -uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex) -{ - assert(regIndex < MU_TR_COUNT); - - /* Wait RX register to be full. */ - while (!(base->SR & (kMU_Rx0FullFlag >> regIndex))) - { - } - - return base->RR[regIndex]; -} - -void MU_SetFlags(MU_Type *base, uint32_t flags) -{ - /* Wait for update finished. */ - while (base->SR & MU_SR_FUP_MASK) - { - } - - MU_SetFlagsNonBlocking(base, flags); -} - -status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask) -{ - uint32_t reg = base->CR; - - /* Previous interrupt has been accepted. */ - if (!(reg & mask)) - { - /* All interrupts have been accepted, trigger now. */ - reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; - base->CR = reg; - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode) -{ -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - /* Clean the reset de-assert pending flag. */ - base->SR = MU_SR_RDIP_MASK; -#endif - -#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) - uint32_t reg = base->CCR; - - reg = (reg & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK)) | MU_CCR_BOOT(mode); - - base->CCR = reg; -#else - uint32_t reg = base->CR; - - reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BBOOT_MASK)) | MU_CR_BBOOT(mode); - - base->CR = reg; -#endif - -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - /* Wait for coming out of reset. */ - while (!(base->SR & MU_SR_RDIP_MASK)) - { - } -#endif -} - -void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode) -{ - /* - * MU_BootOtherCore and MU_BootCoreB are the same, MU_BootCoreB is kept - * for compatible with older platforms. - */ - MU_BootCoreB(base, mode); -} - -#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) -{ - volatile uint32_t sr = 0; - uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); - - ccr |= MU_CCR_BOOT(bootMode); - - if (holdReset) - { - ccr |= MU_CCR_RSTH_MASK; - } - - /* Clean the reset assert pending flag. */ - sr = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); - base->SR = sr; - - /* Set CCR[HR] to trigger hardware reset. */ - base->CCR = ccr | MU_CCR_HR_MASK; - - /* If don't wait the other core enters reset, return directly. */ - if (!waitReset) - { - return; - } - - /* Wait for the other core go to reset. */ - while (!(base->SR & MU_SR_RAIP_MASK)) - { - } - - if (!holdReset) - { - /* Clear CCR[HR]. */ - base->CCR = ccr; - - /* Wait for the other core out of reset. */ - while (!(base->SR & MU_SR_RDIP_MASK)) - { - } - } -} -#else -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode) -{ - volatile uint32_t sr = 0; - uint32_t cr = base->CR & ~(MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BOOT_MASK | MU_CR_GIRn_MASK | MU_CR_NMI_MASK); - - cr |= MU_CR_BOOT(bootMode); - - if (holdReset) - { - cr |= MU_CR_RSTH_MASK; - } - - /* Clean the reset assert pending flag. */ - sr = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); - base->SR = sr; - - /* Set CR[HR] to trigger hardware reset. */ - base->CR = cr | MU_CR_HR_MASK; - - /* If don't wait the other core enters reset, return directly. */ - if (!waitReset) - { - return; - } - - /* Wait for the other core go to reset. */ - while (!(base->SR & MU_SR_RAIP_MASK)) - { - } - - if (!holdReset) - { - /* Clear CR[HR]. */ - base->CR = cr; - - /* Wait for the other core out of reset. */ - while (!(base->SR & MU_SR_RDIP_MASK)) - { - } - } -} -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.h deleted file mode 100644 index 93968125c76e643571d106b90e0ea1d17a299efc..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_mu.h +++ /dev/null @@ -1,673 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_MU_H_ -#define _FSL_MU_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup mu - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief MU driver version 2.0.1. */ -#define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief MU status flags. - */ -enum _mu_status_flags -{ - kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), /*!< TX0 empty. */ - kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), /*!< TX1 empty. */ - kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), /*!< TX2 empty. */ - kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), /*!< TX3 empty. */ - - kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), /*!< RX0 full. */ - kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), /*!< RX1 full. */ - kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), /*!< RX2 full. */ - kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), /*!< RX3 full. */ - - kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), /*!< General purpose interrupt 0 pending. */ - kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), /*!< General purpose interrupt 0 pending. */ - kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), /*!< General purpose interrupt 0 pending. */ - kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), /*!< General purpose interrupt 0 pending. */ - - kMU_EventPendingFlag = MU_SR_EP_MASK, /*!< MU event pending. */ - kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, /*!< MU flags update is on-going. */ - -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pending. */ - kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, /*!< The other core reset de-assert interrupt pending. */ -#endif - -#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) - kMU_OtherSideInResetFlag = MU_SR_RS_MASK /*!< The other side is in reset. */ -#endif - -#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) - kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, /*!< The other side initializes MU reset. */ -#endif -#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) - kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK, /*!< Current side has been hardware reset by the other side. */ -#endif -}; - -/*! - * @brief MU interrupt source to enable. - */ -enum _mu_interrupt_enable -{ - kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), /*!< TX0 empty. */ - kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), /*!< TX1 empty. */ - kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), /*!< TX2 empty. */ - kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), /*!< TX3 empty. */ - - kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), /*!< RX0 full. */ - kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), /*!< RX1 full. */ - kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), /*!< RX2 full. */ - kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), /*!< RX3 full. */ - - kMU_GenInt0InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ - kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ - kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ - kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)), /*!< General purpose interrupt 3. */ - -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, /*!< The other core reset assert interrupt. */ - kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, /*!< The other core reset de-assert interrupt. */ -#endif -#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) - kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, /*!< The other side initializes MU reset. The interrupt - is ORed with the general purpose interrupt 3. The - general purpose interrupt 3 is issued when the other side - set the MU reset and this interrupt is enabled. */ -#endif -#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) - kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK, /*!< Current side has been hardware reset by the other side. */ -#endif -}; - -/*! - * @brief MU interrupt that could be triggered to the other core. - */ -enum _mu_interrupt_trigger -{ - kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, /*!< NMI interrupt. */ - kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ - kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ - kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ - kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) /*!< General purpose interrupt 3. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name MU initialization. - * @{ - */ -/*! - * @brief Initializes the MU module. - * - * This function enables the MU clock only. - * - * @param base MU peripheral base address. - */ -void MU_Init(MU_Type *base); - -/*! - * @brief De-initializes the MU module. - * - * This function disables the MU clock only. - * - * @param base MU peripheral base address. - */ -void MU_Deinit(MU_Type *base); - -/* @} */ - -/*! - * @name MU Message - * @{ - */ - -/*! - * @brief Writes a message to the TX register. - * - * This function writes a message to the specific TX register. It does not check - * whether the TX register is empty or not. The upper layer should make sure the TX - * register is empty before calling this function. This function can be used - * in ISR for better performance. - * - * @code - * while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } // Wait for TX0 register empty. - * MU_SendMsgNonBlocking(base, 0U, MSG_VAL); // Write message to the TX0 register. - * @endcode - * - * @param base MU peripheral base address. - * @param regIndex TX register index. - * @param msg Message to send. - */ -static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg) -{ - assert(regIndex < MU_TR_COUNT); - - base->TR[regIndex] = msg; -} - -/*! - * @brief Blocks to send a message. - * - * This function waits until the TX register is empty and sends the message. - * - * @param base MU peripheral base address. - * @param regIndex TX register index. - * @param msg Message to send. - */ -void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); - -/*! - * @brief Reads a message from the RX register. - * - * This function reads a message from the specific RX register. It does not check - * whether the RX register is full or not. The upper layer should make sure the RX - * register is full before calling this function. This function can be used - * in ISR for better performance. - * - * @code - * uint32_t msg; - * while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base))) - * { - * } // Wait for the RX0 register full. - * - * msg = MU_ReceiveMsgNonBlocking(base, 0U); // Read message from RX0 register. - * @endcode - * - * @param base MU peripheral base address. - * @param regIndex TX register index. - * @return The received message. - */ -static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex) -{ - assert(regIndex < MU_TR_COUNT); - - return base->RR[regIndex]; -} - -/*! - * @brief Blocks to receive a message. - * - * This function waits until the RX register is full and receives the message. - * - * @param base MU peripheral base address. - * @param regIndex RX register index. - * @return The received message. - */ -uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); - -/* @} */ - -/*! - * @name MU Flags - * @{ - */ - -/*! - * @brief Sets the 3-bit MU flags reflect on the other MU side. - * - * This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, - * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are - * updating to the other side. After the 3-bit MU flags are updated, the status flag - * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, - * the flags cannot be changed. The upper layer should make sure the status flag - * \c kMU_FlagsUpdatingFlag is cleared before calling this function. - * - * @code - * while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base)) - * { - * } // Wait for previous MU flags updating. - * - * MU_SetFlagsNonBlocking(base, 0U); // Set the mU flags. - * @endcode - * - * @param base MU peripheral base address. - * @param flags The 3-bit MU flags to set. - */ -static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) -{ - uint32_t reg = base->CR; - reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); - base->CR = reg; -} - -/*! - * @brief Blocks setting the 3-bit MU flags reflect on the other MU side. - * - * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, - * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are - * updating to the other side. After the 3-bit MU flags are updated, the status flag - * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, - * the flags cannot be changed. This function waits for the MU status flag - * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. - * - * @param base MU peripheral base address. - * @param flags The 3-bit MU flags to set. - */ -void MU_SetFlags(MU_Type *base, uint32_t flags); - -/*! - * @brief Gets the current value of the 3-bit MU flags set by the other side. - * - * This functions gets the current 3-bit MU flags on the current side. - * - * @param base MU peripheral base address. - * @return flags Current value of the 3-bit flags. - */ -static inline uint32_t MU_GetFlags(MU_Type *base) -{ - return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; -} - -/* @} */ - -/*! - * @name Status and Interrupt. - * @{ - */ - -/*! - * @brief Gets the MU status flags. - * - * This function returns the bit mask of the MU status flags. See _mu_status_flags. - * - * @code - * uint32_t flags; - * flags = MU_GetStatusFlags(base); // Get all status flags. - * if (kMU_Tx0EmptyFlag & flags) - * { - * // The TX0 register is empty. Message can be sent. - * MU_SendMsgNonBlocking(base, 0U, MSG0_VAL); - * } - * if (kMU_Tx1EmptyFlag & flags) - * { - * // The TX1 register is empty. Message can be sent. - * MU_SendMsgNonBlocking(base, 1U, MSG1_VAL); - * } - * @endcode - * - * @param base MU peripheral base address. - * @return Bit mask of the MU status flags, see _mu_status_flags. - */ -static inline uint32_t MU_GetStatusFlags(MU_Type *base) -{ - return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_MASK -#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) - | MU_SR_RS_MASK -#endif -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - | MU_SR_RDIP_MASK | MU_SR_RAIP_MASK -#endif -#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) - | MU_SR_MURIP_MASK -#endif -#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) - | MU_SR_HRIP_MASK -#endif - )); -} - -/*! - * @brief Clears the specific MU status flags. - * - * This function clears the specific MU status flags. The flags to clear should - * be passed in as bit mask. See _mu_status_flags. - * - * @code - * //Clear general interrupt 0 and general interrupt 1 pending flags. - * MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag); - * @endcode - * - * @param base MU peripheral base address. - * @param mask Bit mask of the MU status flags. See _mu_status_flags. The following - * flags are cleared by hardware, this function could not clear them. - * - kMU_Tx0EmptyFlag - * - kMU_Tx1EmptyFlag - * - kMU_Tx2EmptyFlag - * - kMU_Tx3EmptyFlag - * - kMU_Rx0FullFlag - * - kMU_Rx1FullFlag - * - kMU_Rx2FullFlag - * - kMU_Rx3FullFlag - * - kMU_EventPendingFlag - * - kMU_FlagsUpdatingFlag - * - kMU_OtherSideInResetFlag - */ -static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask) -{ - /* regMask is the mask of w1c status bits. */ - uint32_t regMask = MU_SR_GIPn_MASK; - -#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) - regMask |= (MU_SR_RDIP_MASK | MU_SR_RAIP_MASK); -#endif - -#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) - regMask |= MU_SR_MURIP_MASK; -#endif - -#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) - regMask |= MU_SR_HRIP_MASK; -#endif - - base->SR = (mask & regMask); -} - -/*! - * @brief Enables the specific MU interrupts. - * - * This function enables the specific MU interrupts. The interrupts to enable - * should be passed in as bit mask. See _mu_interrupt_enable. - * - * @code - * // Enable general interrupt 0 and TX0 empty interrupt. - * MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); - * @endcode - * - * @param base MU peripheral base address. - * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. - */ -static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask) -{ - uint32_t reg = base->CR; - reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; - base->CR = reg; -} - -/*! - * @brief Disables the specific MU interrupts. - * - * This function disables the specific MU interrupts. The interrupts to disable - * should be passed in as bit mask. See _mu_interrupt_enable. - * - * @code - * // Disable general interrupt 0 and TX0 empty interrupt. - * MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); - * @endcode - * - * @param base MU peripheral base address. - * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. - */ -static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask) -{ - uint32_t reg = base->CR; - reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); - base->CR = reg; -} - -/*! - * @brief Triggers interrupts to the other core. - * - * This function triggers the specific interrupts to the other core. The interrupts - * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger. - * The MU should not trigger an interrupt to the other core when the previous interrupt - * has not been processed by the other core. This function checks whether the - * previous interrupts have been processed. If not, it returns an error. - * - * @code - * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) - * { - * // Previous general purpose interrupt 0 or general purpose interrupt 2 - * // has not been processed by the other core. - * } - * @endcode - * - * @param base MU peripheral base address. - * @param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. - * @retval kStatus_Success Interrupts have been triggered successfully. - * @retval kStatus_Fail Previous interrupts have not been accepted. - */ -status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask); - -/*! - * @brief Clear non-maskable interrupt (NMI) sent by the other core. - * - * This functions clears non-maskable interrupt (NMI) sent by the other core. - * - * @param base MU peripheral base address. - */ -static inline void MU_ClearNmi(MU_Type *base) -{ - base->SR = MU_SR_NMIC_MASK; -} - -/* @} */ - -/*! - * @name MU misc functions - * @{ - */ - -/*! - * @brief Boots the core at B side. - * - * This function sets the B side core's boot configuration and releases the - * core from reset. - * - * @param base MU peripheral base address. - * @param mode Core B boot mode. - * @note Only MU side A can use this function. - */ -void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode); - -/*! - * @brief Holds the core reset of B side. - * - * This function causes the core of B side to be held in reset following any reset event. - * - * @param base MU peripheral base address. - * @note Only A side could call this function. - */ -static inline void MU_HoldCoreBReset(MU_Type *base) -{ -#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) - base->CCR |= MU_CCR_RSTH_MASK; -#else /* FSL_FEATURE_MU_HAS_CCR */ - uint32_t reg = base->CR; - reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK; - base->CR = reg; -#endif /* FSL_FEATURE_MU_HAS_CCR */ -} - -/*! - * @brief Boots the other core. - * - * This function boots the other core with a boot configuration. - * - * @param base MU peripheral base address. - * @param mode The other core boot mode. - */ -void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode); - -/*! - * @brief Holds the other core reset. - * - * This function causes the other core to be held in reset following any reset event. - * - * @param base MU peripheral base address. - */ -static inline void MU_HoldOtherCoreReset(MU_Type *base) -{ - /* - * MU_HoldOtherCoreReset and MU_HoldCoreBReset are the same, MU_HoldCoreBReset - * is kept for compatible with older platforms. - */ - MU_HoldCoreBReset(base); -} - -/*! - * @brief Resets the MU for both A side and B side. - * - * This function resets the MU for both A side and B side. Before reset, it is - * recommended to interrupt processor B, because this function may affect the - * ongoing processor B programs. - * - * @param base MU peripheral base address. - * @note For some platforms, only MU side A could use this function, check - * reference manual for details. - */ -static inline void MU_ResetBothSides(MU_Type *base) -{ - uint32_t reg = base->CR; - reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; - base->CR = reg; - -#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) - /* Wait for the other side out of reset. */ - while (base->SR & MU_SR_RS_MASK) - { - } -#endif /* FSL_FEATURE_MU_HAS_SR_RS */ -} - -#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) -/*! - * @brief Mask hardware reset by the other core. - * - * The other core could call MU_HardwareResetOtherCore() to reset current core. - * To mask the reset, call this function and pass in true. - * - * @param base MU peripheral base address. - * @param mask Pass true to mask the hardware reset, pass false to unmask it. - */ -static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) -{ - if (mask) - { - base->CCR |= MU_CCR_HRM_MASK; - } - else - { - base->CCR &= ~MU_CCR_HRM_MASK; - } -} -#endif - -/*! - * @brief Hardware reset the other core. - * - * This function resets the other core, the other core could mask the - * hardware reset by calling @ref MU_MaskHardwareReset. The hardware reset - * mask feature is only available for some platforms. - * This function could be used together with MU_BootOtherCore to control the - * other core reset workflow. - * - * Example 1: Reset the other core, and no hold reset - * @code - * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); - * @endcode - * In this example, the core at MU side B will reset with the specified boot mode. - * - * Example 2: Reset the other core and hold it, then boot the other core later. - * @code - * // Here the other core enters reset, and the reset is hold - * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); - * // Current core boot the other core when necessary. - * MU_BootOtherCore(MU_A, bootMode); - * @endcode - * - * @param base MU peripheral base address. - * @param waitReset Wait the other core enters reset. - * - true: Wait until the other core enters reset, if the other - * core has masked the hardware reset, then this function will - * be blocked. - * - false: Don't wait the reset. - * @param holdReset Hold the other core reset or not. - * - true: Hold the other core in reset, this function returns - * directly when the other core enters reset. - * - false: Don't hold the other core in reset, this function - * waits until the other core out of reset. - * @param bootMode Boot mode of the other core, if @p holdReset is true, this - * parameter is useless. - */ -void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); - -/*! - * @brief Enables or disables the clock on the other core. - * - * This function enables or disables the platform clock on the other core when - * that core enters a stop mode. If disabled, the platform clock for the other - * core is disabled when it enters stop mode. If enabled, the platform clock - * keeps running on the other core in stop mode, until this core also enters - * stop mode. - * - * @param base MU peripheral base address. - * @param enable Enable or disable the clock on the other core. - */ -static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) -{ -#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) - if (enable) - { - base->CCR |= MU_CCR_CLKE_MASK; - } - else - { - base->CCR &= ~MU_CCR_CLKE_MASK; - } -#else /* FSL_FEATURE_MU_HAS_CCR */ - uint32_t reg = base->CR; - - reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK); - - if (enable) - { - reg |= MU_CR_CLKE_MASK; - } - else - { - reg &= ~MU_CR_CLKE_MASK; - } - - base->CR = reg; -#endif /* FSL_FEATURE_MU_HAS_CCR */ -} - -/*! - * @brief Gets the power mode of the other core. - * - * This function gets the power mode of the other core. - * - * @param base MU peripheral base address. - * @return Power mode of the other core. - */ -static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type *base) -{ - return (mu_power_mode_t)((base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT); -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /* _FSL_MU_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_port.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_port.h deleted file mode 100644 index e0e808ca5f3a4360129dcf1f0f94f7597fb34487..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_port.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PORT_H_ -#define _FSL_PORT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup port - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! Version 2.0.2. */ -#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE -/*! @brief Internal resistor pull feature selection */ -enum _port_pull -{ - kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ - kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ - kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ - -#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE -/*! @brief Slew rate selection */ -enum _port_slew_rate -{ - kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ - kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ - -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN -/*! @brief Open Drain feature enable/disable */ -enum _port_open_drain_enable -{ - kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ - kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - -#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER -/*! @brief Passive filter feature enable/disable */ -enum _port_passive_filter_enable -{ - kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ - kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ -}; -#endif - -#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH -/*! @brief Configures the drive strength. */ -enum _port_drive_strength -{ - kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ - kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ - -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK -/*! @brief Unlock/lock the pin control register field[15:0] */ -enum _port_lock_register -{ - kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ - kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ -}; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @brief Pin mux selection */ -typedef enum _port_mux -{ - kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ - kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ - kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ - kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ - kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ - kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ - kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ - kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ - kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ - kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ - kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ - kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ - kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ - kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ - kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ - kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ -} port_mux_t; -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -/*! @brief Configures the interrupt generation condition. */ -typedef enum _port_interrupt -{ - kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ -#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST - kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ - kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ - kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ -#endif -#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG - kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ - kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ - kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ -#endif - kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ - kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ - kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ - kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ - kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ -#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER - kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ - kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ -#endif -} port_interrupt_t; - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER -/*! @brief Digital filter clock source selection */ -typedef enum _port_digital_filter_clock_source -{ - kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ - kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ -} port_digital_filter_clock_source_t; - -/*! @brief PORT digital filter feature configuration definition */ -typedef struct _port_digital_filter_config -{ - uint32_t digitalFilterWidth; /*!< Set digital filter width */ - port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ -} port_digital_filter_config_t; -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @brief PORT pin configuration structure */ -typedef struct _port_pin_config -{ -#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE - uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ -#else - uint16_t : 2; -#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ - -#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE - uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ - - uint16_t : 1; - -#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER - uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ - -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN - uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ - -#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH - uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ -#else - uint16_t : 1; -#endif - - uint16_t : 1; - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3) - uint16_t mux : 3; /*!< Pin mux Configure */ - uint16_t : 4; -#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4) - uint16_t mux : 4; /*!< Pin mux Configure */ - uint16_t : 3; -#else - uint16_t : 7, -#endif - -#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK - uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ -#else - uint16_t : 1; -#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ -} port_pin_config_t; -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -/******************************************************************************* -* API -******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH -/*! @name Configuration */ -/*@{*/ - -/*! - * @brief Sets the port PCR register. - * - * This is an example to define an input pin or output pin PCR configuration. - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnLockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) -{ - assert(config); - uint32_t addr = (uint32_t)&base->PCR[pin]; - *(volatile uint16_t *)(addr) = *((const uint16_t *)config); -} - -/*! - * @brief Sets the port PCR register for multiple pins. - * - * This is an example to define input pins or output pins PCR configuration. - * @code - * // Define a digital input pin PCR configuration - * port_pin_config_t config = { - * kPORT_PullUp , - * kPORT_PullEnable, - * kPORT_FastSlewRate, - * kPORT_PassiveFilterDisable, - * kPORT_OpenDrainDisable, - * kPORT_LowDriveStrength, - * kPORT_MuxAsGpio, - * kPORT_UnlockRegister, - * }; - * @endcode - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - * @param config PORT PCR register configuration structure. - */ -static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) -{ - assert(config); - - uint16_t pcrl = *((const uint16_t *)config); - - if (mask & 0xffffU) - { - base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; - } - if (mask >> 16) - { - base->GPCHR = (mask & 0xffff0000U) | pcrl; - } -} - -#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG -/*! - * @brief Sets the port interrupt configuration in PCR register for multiple pins. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - * @param config PORT pin interrupt configuration. - * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. - * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). - * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). - * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). - * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). - * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). - * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). - * - #kPORT_InterruptLogicZero : Interrupt when logic zero. - * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. - * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. - * - #kPORT_InterruptEitherEdge : Interrupt on either edge. - * - #kPORT_InterruptLogicOne : Interrupt when logic one. - * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). - * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. - */ -static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config) -{ - assert(config); - - if (mask & 0xffffU) - { - base->GICLR = (config << 16) | (mask & 0xffffU); - } - if (mask >> 16) - { - base->GICHR = (config << 16) | (mask & 0xffff0000U); - } -} -#endif - -/*! - * @brief Configures the pin muxing. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param mux pin muxing slot selection. - * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. - * - #kPORT_MuxAsGpio : Set as GPIO. - * - #kPORT_MuxAlt2 : chip-specific. - * - #kPORT_MuxAlt3 : chip-specific. - * - #kPORT_MuxAlt4 : chip-specific. - * - #kPORT_MuxAlt5 : chip-specific. - * - #kPORT_MuxAlt6 : chip-specific. - * - #kPORT_MuxAlt7 : chip-specific. - * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because - * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is - * reset to zero : kPORT_PinDisabledOrAnalog). - * This function is recommended to use to reset the pin mux - * - */ -static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); -} -#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ - -#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER - -/*! - * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) -{ - if (enable == true) - { - base->DFER |= mask; - } - else - { - base->DFER &= ~mask; - } -} - -/*! - * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. - * - * @param base PORT peripheral base pointer. - * @param config PORT digital filter configuration structure. - */ -static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) -{ - assert(config); - - base->DFCR = PORT_DFCR_CS(config->clockSource); - base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); -} - -#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ - -/*@}*/ - -/*! @name Interrupt */ -/*@{*/ - -/*! - * @brief Configures the port pin interrupt/DMA request. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT pin interrupt configuration. - * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. - * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). - * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). - * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). - * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). - * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). - * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). - * - #kPORT_InterruptLogicZero : Interrupt when logic zero. - * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. - * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. - * - #kPORT_InterruptEitherEdge : Interrupt on either edge. - * - #kPORT_InterruptLogicOne : Interrupt when logic one. - * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). - * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). - */ -static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); -} - -#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH -/*! - * @brief Configures the port pin drive strength. - * - * @param base PORT peripheral base pointer. - * @param pin PORT pin number. - * @param config PORT pin drive strength - * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured. - * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured. - */ -static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength) -{ - base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); -} -#endif - -/*! - * @brief Reads the whole port status flag. - * - * If a pin is configured to generate the DMA request, the corresponding flag - * is cleared automatically at the completion of the requested DMA transfer. - * Otherwise, the flag remains set until a logic one is written to that flag. - * If configured for a level sensitive interrupt that remains asserted, the flag - * is set again immediately. - * - * @param base PORT peripheral base pointer. - * @return Current port interrupt status flags, for example, 0x00010001 means the - * pin 0 and 16 have the interrupt. - */ -static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) -{ - return base->ISFR; -} - -/*! - * @brief Clears the multiple pin interrupt status flag. - * - * @param base PORT peripheral base pointer. - * @param mask PORT pin number macro. - */ -static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) -{ - base->ISFR = mask; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PORT_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.c deleted file mode 100644 index c58f582020751004a6685529b2a6a53ce6a4fd8b..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.c +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_rtc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -void RTC_Init(RTC_Type *base, const rtc_config_t *config) -{ - assert(config); - - uint32_t reg; - -#if defined(RTC_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* RTC_CLOCKS */ - - /* Issue a software reset if timer is invalid */ - if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) - { - RTC_Reset(RTC); - } - - reg = base->CR; - /* Setup the update mode and supervisor access mode */ - reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); - reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); -#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION - /* Setup the wakeup pin select */ - reg &= ~(RTC_CR_WPS_MASK); - reg |= RTC_CR_WPS(config->wakeupSelect); -#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ - base->CR = reg; - - /* Configure the RTC time compensation register */ - base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); - -#if defined(FSL_FEATURE_RTC_HAS_TSIC) && FSL_FEATURE_RTC_HAS_TSIC - /* Configure RTC timer seconds interrupt to be generated once per second */ - base->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK); -#endif -} - -void RTC_GetDefaultConfig(rtc_config_t *config) -{ - assert(config); - - /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ - config->wakeupSelect = false; - /* Registers cannot be written when locked */ - config->updateMode = false; - /* Non-supervisor mode write accesses are not supported and will generate a bus error */ - config->supervisorAccess = false; - /* Compensation interval used by the crystal compensation logic */ - config->compensationInterval = 0; - /* Compensation time used by the crystal compensation logic */ - config->compensationTime = 0; -} - -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Return error if the time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - base->TSR = RTC_ConvertDatetimeToSeconds(datetime); - - return kStatus_Success; -} - -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0; - - seconds = base->TSR; - RTC_ConvertSecondsToDatetime(seconds, datetime); -} - -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0; - uint32_t currSeconds = 0; - - /* Return error if the alarm time provided is not valid */ - if (!(RTC_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); - - /* Get the current time */ - currSeconds = base->TSR; - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* Set alarm in seconds*/ - base->TAR = alarmSeconds; - - return kStatus_Success; -} - -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0; - - /* Get alarm in seconds */ - alarmSeconds = base->TAR; - - RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); -} - -void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t tmp32 = 0U; - - /* RTC_IER */ - if (kRTC_TimeInvalidInterruptEnable == (kRTC_TimeInvalidInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TIIE_MASK; - } - if (kRTC_TimeOverflowInterruptEnable == (kRTC_TimeOverflowInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TOIE_MASK; - } - if (kRTC_AlarmInterruptEnable == (kRTC_AlarmInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TAIE_MASK; - } - if (kRTC_SecondsInterruptEnable == (kRTC_SecondsInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TSIE_MASK; - } -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - if (kRTC_MonotonicOverflowInterruptEnable == (kRTC_MonotonicOverflowInterruptEnable & mask)) - { - tmp32 |= RTC_IER_MOIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - base->IER |= tmp32; - -#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) - tmp32 = 0U; - - /* RTC_TIR */ - if (kRTC_TestModeInterruptEnable == (kRTC_TestModeInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_TMIE_MASK; - } - if (kRTC_FlashSecurityInterruptEnable == (kRTC_FlashSecurityInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_FSIE_MASK; - } -#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) - if (kRTC_TamperPinInterruptEnable == (kRTC_TamperPinInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_TPIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) - if (kRTC_SecurityModuleInterruptEnable == (kRTC_SecurityModuleInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_SIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) - if (kRTC_LossOfClockInterruptEnable == (kRTC_LossOfClockInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_LCIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ - base->TIR |= tmp32; -#endif /* FSL_FEATURE_RTC_HAS_TIR */ -} - -void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) -{ - uint32_t tmp32 = 0U; - - /* RTC_IER */ - if (kRTC_TimeInvalidInterruptEnable == (kRTC_TimeInvalidInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TIIE_MASK; - } - if (kRTC_TimeOverflowInterruptEnable == (kRTC_TimeOverflowInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TOIE_MASK; - } - if (kRTC_AlarmInterruptEnable == (kRTC_AlarmInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TAIE_MASK; - } - if (kRTC_SecondsInterruptEnable == (kRTC_SecondsInterruptEnable & mask)) - { - tmp32 |= RTC_IER_TSIE_MASK; - } -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - if (kRTC_MonotonicOverflowInterruptEnable == (kRTC_MonotonicOverflowInterruptEnable & mask)) - { - tmp32 |= RTC_IER_MOIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - base->IER &= (uint32_t)(~tmp32); - -#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) - tmp32 = 0U; - - /* RTC_TIR */ - if (kRTC_TestModeInterruptEnable == (kRTC_TestModeInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_TMIE_MASK; - } - if (kRTC_FlashSecurityInterruptEnable == (kRTC_FlashSecurityInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_FSIE_MASK; - } -#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) - if (kRTC_TamperPinInterruptEnable == (kRTC_TamperPinInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_TPIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) - if (kRTC_SecurityModuleInterruptEnable == (kRTC_SecurityModuleInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_SIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) - if (kRTC_LossOfClockInterruptEnable == (kRTC_LossOfClockInterruptEnable & mask)) - { - tmp32 |= RTC_TIR_LCIE_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ - base->TIR &= (uint32_t)(~tmp32); -#endif /* FSL_FEATURE_RTC_HAS_TIR */ -} - -uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) -{ - uint32_t tmp32 = 0U; - - /* RTC_IER */ - if (RTC_IER_TIIE_MASK == (RTC_IER_TIIE_MASK & base->IER)) - { - tmp32 |= kRTC_TimeInvalidInterruptEnable; - } - if (RTC_IER_TOIE_MASK == (RTC_IER_TOIE_MASK & base->IER)) - { - tmp32 |= kRTC_TimeOverflowInterruptEnable; - } - if (RTC_IER_TAIE_MASK == (RTC_IER_TAIE_MASK & base->IER)) - { - tmp32 |= kRTC_AlarmInterruptEnable; - } - if (RTC_IER_TSIE_MASK == (RTC_IER_TSIE_MASK & base->IER)) - { - tmp32 |= kRTC_SecondsInterruptEnable; - } -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - if (RTC_IER_MOIE_MASK == (RTC_IER_MOIE_MASK & base->IER)) - { - tmp32 |= kRTC_MonotonicOverflowInterruptEnable; - } -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - -#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) - /* RTC_TIR */ - if (RTC_TIR_TMIE_MASK == (RTC_TIR_TMIE_MASK & base->TIR)) - { - tmp32 |= kRTC_TestModeInterruptEnable; - } - if (RTC_TIR_FSIE_MASK == (RTC_TIR_FSIE_MASK & base->TIR)) - { - tmp32 |= kRTC_FlashSecurityInterruptEnable; - } -#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) - if (RTC_TIR_TPIE_MASK == (RTC_TIR_TPIE_MASK & base->TIR)) - { - tmp32 |= kRTC_TamperPinInterruptEnable; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) - if (RTC_TIR_SIE_MASK == (RTC_TIR_SIE_MASK & base->TIR)) - { - tmp32 |= kRTC_SecurityModuleInterruptEnable; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) - if (RTC_TIR_LCIE_MASK == (RTC_TIR_LCIE_MASK & base->TIR)) - { - tmp32 |= kRTC_LossOfClockInterruptEnable; - } -#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ -#endif /* FSL_FEATURE_RTC_HAS_TIR */ - - return tmp32; -} - -uint32_t RTC_GetStatusFlags(RTC_Type *base) -{ - uint32_t tmp32 = 0U; - - /* RTC_SR */ - if (RTC_SR_TIF_MASK == (RTC_SR_TIF_MASK & base->SR)) - { - tmp32 |= kRTC_TimeInvalidFlag; - } - if (RTC_SR_TOF_MASK == (RTC_SR_TOF_MASK & base->SR)) - { - tmp32 |= kRTC_TimeOverflowFlag; - } - if (RTC_SR_TAF_MASK == (RTC_SR_TAF_MASK & base->SR)) - { - tmp32 |= kRTC_AlarmFlag; - } -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - if (RTC_SR_MOF_MASK == (RTC_SR_MOF_MASK & base->SR)) - { - tmp32 |= kRTC_MonotonicOverflowFlag; - } -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ -#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF) - if (RTC_SR_TIDF_MASK == (RTC_SR_TIDF_MASK & base->SR)) - { - tmp32 |= kRTC_TamperInterruptDetectFlag; - } -#endif /* FSL_FEATURE_RTC_HAS_SR_TIDF */ - -#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) - /* RTC_TDR */ - if (RTC_TDR_TMF_MASK == (RTC_TDR_TMF_MASK & base->TDR)) - { - tmp32 |= kRTC_TestModeFlag; - } - if (RTC_TDR_FSF_MASK == (RTC_TDR_FSF_MASK & base->TDR)) - { - tmp32 |= kRTC_FlashSecurityFlag; - } -#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) - if (RTC_TDR_TPF_MASK == (RTC_TDR_TPF_MASK & base->TDR)) - { - tmp32 |= kRTC_TamperPinFlag; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) - if (RTC_TDR_STF_MASK == (RTC_TDR_STF_MASK & base->TDR)) - { - tmp32 |= kRTC_SecurityTamperFlag; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) - if (RTC_TDR_LCTF_MASK == (RTC_TDR_LCTF_MASK & base->TDR)) - { - tmp32 |= kRTC_LossOfClockTamperFlag; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ -#endif /* FSL_FEATURE_RTC_HAS_TDR */ - - return tmp32; -} - -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) -{ - /* The alarm flag is cleared by writing to the TAR register */ - if (mask & kRTC_AlarmFlag) - { - base->TAR = 0U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeOverflowFlag) - { - base->TSR = 1U; - } - - /* The timer overflow flag is cleared by initializing the TSR register. - * The time counter should be disabled for this write to be successful - */ - if (mask & kRTC_TimeInvalidFlag) - { - base->TSR = 1U; - } - -#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) - /* To clear, write logic one to this flag after exiting from all test modes */ - if (kRTC_TestModeFlag == (kRTC_TestModeFlag & mask)) - { - base->TDR = RTC_TDR_TMF_MASK; - } - /* To clear, write logic one to this flag after flash security is enabled */ - if (kRTC_FlashSecurityFlag == (kRTC_FlashSecurityFlag & mask)) - { - base->TDR = RTC_TDR_FSF_MASK; - } -#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) - /* To clear, write logic one to the corresponding flag after that tamper pin negates */ - if (kRTC_TamperPinFlag == (kRTC_TamperPinFlag & mask)) - { - base->TDR = RTC_TDR_TPF_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) - /* To clear, write logic one to this flag after security module has negated its tamper detect */ - if (kRTC_SecurityTamperFlag == (kRTC_SecurityTamperFlag & mask)) - { - base->TDR = RTC_TDR_STF_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) - /* To clear, write logic one to this flag after loss of clock negates */ - if (kRTC_LossOfClockTamperFlag == (kRTC_LossOfClockTamperFlag & mask)) - { - base->TDR = RTC_TDR_LCTF_MASK; - } -#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ -#endif /* FSL_FEATURE_RTC_HAS_TDR */ -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) -{ - assert(counter); - - *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); -} - -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) -{ - /* Prepare to initialize the register with the new value written */ - base->MER &= ~RTC_MER_MCE_MASK; - - base->MCHR = (uint32_t)((counter) >> 32); - base->MCLR = (uint32_t)(counter); -} - -status_t RTC_IncrementMonotonicCounter(RTC_Type *base) -{ - if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) - { - return kStatus_Fail; - } - - /* Prepare to switch to increment mode */ - base->MER |= RTC_MER_MCE_MASK; - /* Write anything so the counter increments*/ - base->MCLR = 1U; - - return kStatus_Success; -} - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.h deleted file mode 100644 index bb38d6bc0d607be03df7dcb1f06fd2eac0272ec4..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_rtc.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_RTC_H_ -#define _FSL_RTC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of RTC interrupts */ -typedef enum _rtc_interrupt_enable -{ - kRTC_TimeInvalidInterruptEnable = (1U << 0U), /*!< Time invalid interrupt.*/ - kRTC_TimeOverflowInterruptEnable = (1U << 1U), /*!< Time overflow interrupt.*/ - kRTC_AlarmInterruptEnable = (1U << 2U), /*!< Alarm interrupt.*/ - kRTC_SecondsInterruptEnable = (1U << 3U), /*!< Seconds interrupt.*/ -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - kRTC_MonotonicOverflowInterruptEnable = (1U << 4U), /*!< Monotonic Overflow Interrupt Enable */ -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR) && FSL_FEATURE_RTC_HAS_TIR) - kRTC_TestModeInterruptEnable = (1U << 5U), /* test mode interrupt */ - kRTC_FlashSecurityInterruptEnable = (1U << 6U), /* flash security interrupt */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_TPIE) && FSL_FEATURE_RTC_HAS_TIR_TPIE) - kRTC_TamperPinInterruptEnable = (1U << 7U), /* Tamper pin interrupt */ -#endif /* FSL_FEATURE_RTC_HAS_TIR_TPIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_SIE) && FSL_FEATURE_RTC_HAS_TIR_SIE) - kRTC_SecurityModuleInterruptEnable = (1U << 8U), /* security module interrupt */ -#endif /* FSL_FEATURE_RTC_HAS_TIR_SIE */ -#if (defined(FSL_FEATURE_RTC_HAS_TIR_LCIE) && FSL_FEATURE_RTC_HAS_TIR_LCIE) - kRTC_LossOfClockInterruptEnable = (1U << 9U), /* loss of clock interrupt */ -#endif /* FSL_FEATURE_RTC_HAS_TIR_LCIE */ -#endif /* FSL_FEATURE_RTC_HAS_TIR */ -} rtc_interrupt_enable_t; - -/*! @brief List of RTC flags */ -typedef enum _rtc_status_flags -{ - kRTC_TimeInvalidFlag = (1U << 0U), /*!< Time invalid flag */ - kRTC_TimeOverflowFlag = (1U << 1U), /*!< Time overflow flag */ - kRTC_AlarmFlag = (1U << 2U), /*!< Alarm flag*/ -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - kRTC_MonotonicOverflowFlag = (1U << 3U), /*!< Monotonic Overflow Flag */ -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ -#if (defined(FSL_FEATURE_RTC_HAS_SR_TIDF) && FSL_FEATURE_RTC_HAS_SR_TIDF) - kRTC_TamperInterruptDetectFlag = (1U << 4U), /*!< Tamper interrupt detect flag */ -#endif /* FSL_FEATURE_RTC_HAS_SR_TIDF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR) && FSL_FEATURE_RTC_HAS_TDR) - kRTC_TestModeFlag = (1U << 5U), /* Test mode flag */ - kRTC_FlashSecurityFlag = (1U << 6U), /* Flash security flag */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_TPF) && FSL_FEATURE_RTC_HAS_TDR_TPF) - kRTC_TamperPinFlag = (1U << 7U), /* Tamper pin flag */ -#endif /* FSL_FEATURE_RTC_HAS_TDR_TPF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_STF) && FSL_FEATURE_RTC_HAS_TDR_STF) - kRTC_SecurityTamperFlag = (1U << 8U), /* Security tamper flag */ -#endif /* FSL_FEATURE_RTC_HAS_TDR_STF */ -#if (defined(FSL_FEATURE_RTC_HAS_TDR_LCTF) && FSL_FEATURE_RTC_HAS_TDR_LCTF) - kRTC_LossOfClockTamperFlag = (1U << 9U), /* Loss of clock flag */ -#endif /* FSL_FEATURE_RTC_HAS_TDR_LCTF */ -#endif /* FSL_FEATURE_RTC_HAS_TDR */ -} rtc_status_flags_t; - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! @brief List of RTC Oscillator capacitor load settings */ -typedef enum _rtc_osc_cap_load -{ - kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ - kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ - kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ - kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */ -} rtc_osc_cap_load_t; - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! @brief Structure is used to hold the date and time */ -typedef struct _rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} rtc_datetime_t; - -#if (defined(FSL_FEATURE_RTC_HAS_PCR) && FSL_FEATURE_RTC_HAS_PCR) - -/*! - * @brief RTC pin config structure - */ -typedef struct _rtc_pin_config -{ - bool inputLogic; /*!< true: Tamper pin input data is logic one. - false: Tamper pin input data is logic zero. */ - bool pinActiveLow; /*!< true: Tamper pin is active low. - false: Tamper pin is active high. */ - bool filterEnable; /*!< true: Input filter is enabled on the tamper pin. - false: Input filter is disabled on the tamper pin. */ - bool pullSelectNegate; /*!< true: Tamper pin pull resistor direction will negate the tamper pin. - false: Tamper pin pull resistor direction will assert the tamper pin. */ - bool pullEnable; /*!< true: Pull resistor is enabled on tamper pin. - false: Pull resistor is disabled on tamper pin. */ -} rtc_pin_config_t; - -#endif /* FSL_FEATURE_RTC_HAS_PCR */ - -/*! - * @brief RTC config structure - * - * This structure holds the configuration settings for the RTC peripheral. To initialize this - * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _rtc_config -{ - bool wakeupSelect; /*!< true: Wakeup pin outputs the 32 KHz clock; - false:Wakeup pin used to wakeup the chip */ - bool updateMode; /*!< true: Registers can be written even when locked under certain - conditions, false: No writes allowed when registers are locked */ - bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; - false: Non-supervisor accesses are not supported */ - uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ - uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ -} rtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the RTC clock and configures the peripheral for basic operation. - * - * This function issues a software reset if the timer invalid flag is set. - * - * @note This API should be called at the beginning of the application using the RTC driver. - * - * @param base RTC peripheral base address - * @param config Pointer to the user's RTC configuration structure. - */ -void RTC_Init(RTC_Type *base, const rtc_config_t *config); - -/*! - * @brief Stops the timer and gate the RTC clock. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Deinit(RTC_Type *base) -{ - /* Stop the RTC timer */ - base->SR &= ~RTC_SR_TCE_MASK; - -#if defined(RTC_CLOCKS) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the module clock */ - CLOCK_DisableClock(kCLOCK_Rtc0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* RTC_CLOCKS */ -} - -/*! - * @brief Fills in the RTC config struct with the default settings. - * - * The default values are as follows. - * @code - * config->wakeupSelect = false; - * config->updateMode = false; - * config->supervisorAccess = false; - * config->compensationInterval = 0; - * config->compensationTime = 0; - * @endcode - * @param config Pointer to the user's RTC configuration structure. - */ -void RTC_GetDefaultConfig(rtc_config_t *config); - -/*! @}*/ - -/*! - * @name Current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the RTC date and time according to the given time structure. - * - * The RTC counter must be stopped prior to calling this function because writes to the RTC - * seconds register fail if the RTC counter is running. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - * - * @return kStatus_Success: Success in setting the time and starting the RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); - -/*! - * @brief Gets the RTC time and stores it in the given time structure. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - */ -void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); - -/*! - * @brief Sets the RTC alarm time. - * - * The function checks whether the specified alarm time is greater than the present - * time. If not, the function does not set the alarm and returns an error. - * - * @param base RTC peripheral base address - * @param alarmTime Pointer to the structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the RTC alarm time. - * - * @param base RTC peripheral base address - * @param datetime Pointer to the structure where the alarm date and time details are stored. - */ -void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask); - -/*! - * @brief Disables the selected RTC interrupts. - * - * @param base RTC peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask); - -/*! - * @brief Gets the enabled RTC interrupts. - * - * @param base RTC peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::rtc_interrupt_enable_t - */ -uint32_t RTC_GetEnabledInterrupts(RTC_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the RTC status flags. - * - * @param base RTC peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -uint32_t RTC_GetStatusFlags(RTC_Type *base); - -/*! - * @brief Clears the RTC status flags. - * - * @param base RTC peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::rtc_status_flags_t - */ -void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); - -/*! @}*/ - -/*! - * @brief Set RTC clock source. - * - * @param base RTC peripheral base address - * - * @note After setting this bit, wait the oscillator startup time before enabling - * the time counter to allow the 32.768 kHz clock time to stabilize. - */ -static inline void RTC_SetClockSource(RTC_Type *base) -{ - /* Enable the RTC 32KHz oscillator */ - base->CR |= RTC_CR_OSCE_MASK; -} - -#if (defined(FSL_FEATURE_RTC_HAS_TTSR) && FSL_FEATURE_RTC_HAS_TTSR) - -/*! - * @brief Get the RTC tamper time seconds. - * - * @param base RTC peripheral base address - */ -static inline uint32_t RTC_GetTamperTimeSeconds(RTC_Type *base) -{ - return base->TTSR; -} - -#endif /* FSL_FEATURE_RTC_HAS_TTSR */ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the RTC time counter. - * - * After calling this function, the timer counter increments once a second provided SR[TOF] or - * SR[TIF] are not set. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StartTimer(RTC_Type *base) -{ - base->SR |= RTC_SR_TCE_MASK; -} - -/*! - * @brief Stops the RTC time counter. - * - * RTC's seconds register can be written to only when the timer is stopped. - * - * @param base RTC peripheral base address - */ -static inline void RTC_StopTimer(RTC_Type *base) -{ - base->SR &= ~RTC_SR_TCE_MASK; -} - -/*! @}*/ - -#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) - -/*! - * @brief This function sets the specified capacitor configuration for the RTC oscillator. - * - * @param base RTC peripheral base address - * @param capLoad Oscillator loads to enable. This is a logical OR of members of the - * enumeration ::rtc_osc_cap_load_t - */ -static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) -{ - uint32_t reg = base->CR; - - reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); - reg |= capLoad; - - base->CR = reg; -} - -#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ - -/*! - * @brief Performs a software reset on the RTC module. - * - * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR - * registers. The SWR bit is cleared by software explicitly clearing it. - * - * @param base RTC peripheral base address - */ -static inline void RTC_Reset(RTC_Type *base) -{ - base->CR |= RTC_CR_SWR_MASK; - base->CR &= ~RTC_CR_SWR_MASK; - - /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ - base->TSR = 1U; -} - -#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) - -/*! - * @name Monotonic counter functions - * @{ - */ - -/*! - * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns - * them as a single value. - * - * @param base RTC peripheral base address - * @param counter Pointer to variable where the value is stored. - */ -void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); - -/*! - * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing - * the given single value. The Monotonic Overflow Flag in RTC_SR is cleared due to the API. - * - * @param base RTC peripheral base address - * @param counter Counter value - */ -void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); - -/*! - * @brief Increments the Monotonic Counter by one. - * - * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting - * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the - * monotonic counter low that causes it to overflow also increments the monotonic counter high. - * - * @param base RTC peripheral base address - * - * @return kStatus_Success: success - * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found - */ -status_t RTC_IncrementMonotonicCounter(RTC_Type *base); - -/*! @}*/ - -#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_RTC_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.c deleted file mode 100644 index 39ee19c7a0edfc88d05de8e4cf61badc22c1e51e..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sema42.h" - -/****************************************************************************** - * Definitions - *****************************************************************************/ -/* The first number write to RSTGDP when reset SEMA42 gate. */ -#define SEMA42_GATE_RESET_PATTERN_1 (0xE2U) -/* The second number write to RSTGDP when reset SEMA42 gate. */ -#define SEMA42_GATE_RESET_PATTERN_2 (0x1DU) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for SEMA42 module. - * - * @param base SEMA42 peripheral base address. - */ -uint32_t SEMA42_GetInstance(SEMA42_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to sema42 bases for each instance. */ -static SEMA42_Type *const s_sema42Bases[] = SEMA42_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to sema42 clocks for each instance. */ -static const clock_ip_name_t s_sema42Clocks[] = SEMA42_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/****************************************************************************** - * CODE - *****************************************************************************/ - -uint32_t SEMA42_GetInstance(SEMA42_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++) - { - if (s_sema42Bases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_sema42Bases)); - - return instance; -} - -void SEMA42_Init(SEMA42_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_sema42Clocks[SEMA42_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SEMA42_Deinit(SEMA42_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_sema42Clocks[SEMA42_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum) -{ - assert(gateNum < FSL_FEATURE_SEMA42_GATE_COUNT); - - ++procNum; - - /* Try to lock. */ - SEMA42_GATEn(base, gateNum) = procNum; - - /* Check locked or not. */ - if (procNum != SEMA42_GATEn(base, gateNum)) - { - return kStatus_SEMA42_Busy; - } - - return kStatus_Success; -} - -void SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum) -{ - assert(gateNum < FSL_FEATURE_SEMA42_GATE_COUNT); - - ++procNum; - - while (procNum != SEMA42_GATEn(base, gateNum)) - { - /* Wait for unlocked status. */ - while (SEMA42_GATEn(base, gateNum)) - { - } - - /* Lock the gate. */ - SEMA42_GATEn(base, gateNum) = procNum; - } -} - -status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum) -{ - /* - * Reset all gates if gateNum >= SEMA42_GATE_NUM_RESET_ALL - * Reset specific gate if gateNum < FSL_FEATURE_SEMA42_GATE_COUNT - */ - assert(!((gateNum < SEMA42_GATE_NUM_RESET_ALL) && (gateNum >= FSL_FEATURE_SEMA42_GATE_COUNT))); - - /* Check whether some reset is ongoing. */ - if (base->RSTGT_R & SEMA42_RSTGT_R_RSTGSM_MASK) - { - return kStatus_SEMA42_Reseting; - } - - /* First step. */ - base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_1); - /* Second step. */ - base->RSTGT_W = SEMA42_RSTGT_W_RSTGDP(SEMA42_GATE_RESET_PATTERN_2) | SEMA42_RSTGT_W_RSTGTN(gateNum); - - return kStatus_Success; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.h deleted file mode 100644 index 9ae3800ef36ce488c39b676f3b792092c6265fe4..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sema42.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SEMA42_H_ -#define _FSL_SEMA42_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sema42 - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SEMA42 driver version */ -#define FSL_SEMA42_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief SEMA42 status return codes. - */ -enum _sema42_status -{ - kStatus_SEMA42_Busy = MAKE_STATUS(kStatusGroup_SEMA42, 0), /*!< SEMA42 gate has been locked by other processor. */ - kStatus_SEMA42_Reseting = MAKE_STATUS(kStatusGroup_SEMA42, 1) /*!< SEMA42 gate reseting is ongoing. */ -}; - -/*! - * @brief SEMA42 gate lock status. - */ -typedef enum _sema42_gate_status -{ - kSEMA42_Unlocked = 0U, /*!< The gate is unlocked. */ - kSEMA42_LockedByProc0 = 1U, /*!< The gate is locked by processor 0. */ - kSEMA42_LockedByProc1 = 2U, /*!< The gate is locked by processor 1. */ - kSEMA42_LockedByProc2 = 3U, /*!< The gate is locked by processor 2. */ - kSEMA42_LockedByProc3 = 4U, /*!< The gate is locked by processor 3. */ - kSEMA42_LockedByProc4 = 5U, /*!< The gate is locked by processor 4. */ - kSEMA42_LockedByProc5 = 6U, /*!< The gate is locked by processor 5. */ - kSEMA42_LockedByProc6 = 7U, /*!< The gate is locked by processor 6. */ - kSEMA42_LockedByProc7 = 8U, /*!< The gate is locked by processor 7. */ - kSEMA42_LockedByProc8 = 9U, /*!< The gate is locked by processor 8. */ - kSEMA42_LockedByProc9 = 10U, /*!< The gate is locked by processor 9. */ - kSEMA42_LockedByProc10 = 11U, /*!< The gate is locked by processor 10. */ - kSEMA42_LockedByProc11 = 12U, /*!< The gate is locked by processor 11. */ - kSEMA42_LockedByProc12 = 13U, /*!< The gate is locked by processor 12. */ - kSEMA42_LockedByProc13 = 14U, /*!< The gate is locked by processor 13. */ - kSEMA42_LockedByProc14 = 15U /*!< The gate is locked by processor 14. */ -} sema42_gate_status_t; - -/*! @brief The number to reset all SEMA42 gates. */ -#define SEMA42_GATE_NUM_RESET_ALL (64U) - -/*! @brief SEMA42 gate n register address. - * - * The SEMA42 gates are sorted in the order 3, 2, 1, 0, 7, 6, 5, 4, ... not in the order - * 0, 1, 2, 3, 4, 5, 6, 7, ... The macro SEMA42_GATEn gets the SEMA42 gate based on the gate - * index. - * - * The input gate index is XOR'ed with 3U: - * 0 ^ 3 = 3 - * 1 ^ 3 = 2 - * 2 ^ 3 = 1 - * 3 ^ 3 = 0 - * 4 ^ 3 = 7 - * 5 ^ 3 = 6 - * 6 ^ 3 = 5 - * 7 ^ 3 = 4 - * ... - */ -#define SEMA42_GATEn(base, n) (*(&((base)->GATE3) + ((n) ^ 3U))) - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the SEMA42 module. - * - * This function initializes the SEMA42 module. It only enables the clock but does - * not reset the gates because the module might be used by other processors - * at the same time. To reset the gates, call either SEMA42_ResetGate or - * SEMA42_ResetAllGates function. - * - * @param base SEMA42 peripheral base address. - */ -void SEMA42_Init(SEMA42_Type *base); - -/*! - * @brief De-initializes the SEMA42 module. - * - * This function de-initializes the SEMA42 module. It only disables the clock. - * - * @param base SEMA42 peripheral base address. - */ -void SEMA42_Deinit(SEMA42_Type *base); - -/*! - * @brief Tries to lock the SEMA42 gate. - * - * This function tries to lock the specific SEMA42 gate. If the gate has been - * locked by another processor, this function returns an error code. - * - * @param base SEMA42 peripheral base address. - * @param gateNum Gate number to lock. - * @param procNum Current processor number. - * - * @retval kStatus_Success Lock the sema42 gate successfully. - * @retval kStatus_SEMA42_Busy Sema42 gate has been locked by another processor. - */ -status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum); - -/*! - * @brief Locks the SEMA42 gate. - * - * This function locks the specific SEMA42 gate. If the gate has been - * locked by other processors, this function waits until it is unlocked and then - * lock it. - * - * @param base SEMA42 peripheral base address. - * @param gateNum Gate number to lock. - * @param procNum Current processor number. - */ -void SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum); - -/*! - * @brief Unlocks the SEMA42 gate. - * - * This function unlocks the specific SEMA42 gate. It only writes unlock value - * to the SEMA42 gate register. However, it does not check whether the SEMA42 gate is locked - * by the current processor or not. As a result, if the SEMA42 gate is not locked by the current - * processor, this function has no effect. - * - * @param base SEMA42 peripheral base address. - * @param gateNum Gate number to unlock. - */ -static inline void SEMA42_Unlock(SEMA42_Type *base, uint8_t gateNum) -{ - assert(gateNum < FSL_FEATURE_SEMA42_GATE_COUNT); - - /* ^= 0x03U because SEMA42 gates are in the order 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 7, ...*/ - SEMA42_GATEn(base, gateNum) = kSEMA42_Unlocked; -} - -/*! - * @brief Gets the status of the SEMA42 gate. - * - * This function checks the lock status of a specific SEMA42 gate. - * - * @param base SEMA42 peripheral base address. - * @param gateNum Gate number. - * - * @return status Current status. - */ -static inline sema42_gate_status_t SEMA42_GetGateStatus(SEMA42_Type *base, uint8_t gateNum) -{ - assert(gateNum < FSL_FEATURE_SEMA42_GATE_COUNT); - - return (sema42_gate_status_t)(SEMA42_GATEn(base, gateNum)); -} - -/*! - * @brief Resets the SEMA42 gate to an unlocked status. - * - * This function resets a SEMA42 gate to an unlocked status. - * - * @param base SEMA42 peripheral base address. - * @param gateNum Gate number. - * - * @retval kStatus_Success SEMA42 gate is reset successfully. - * @retval kStatus_SEMA42_Reseting Some other reset process is ongoing. - */ -status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum); - -/*! - * @brief Resets all SEMA42 gates to an unlocked status. - * - * This function resets all SEMA42 gate to an unlocked status. - * - * @param base SEMA42 peripheral base address. - * - * @retval kStatus_Success SEMA42 is reset successfully. - * @retval kStatus_SEMA42_Reseting Some other reset process is ongoing. - */ -static inline status_t SEMA42_ResetAllGates(SEMA42_Type *base) -{ - return SEMA42_ResetGate(base, SEMA42_GATE_NUM_RESET_ALL); -} - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_SEMA42_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.c deleted file mode 100644 index 1d1dd9c70506564056bf334b961ade9916c2c983..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sim.h" - -/******************************************************************************* - * Codes - ******************************************************************************/ -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) -{ - SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); - - SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; -} -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -void SIM_GetUniqueId(sim_uid_t *uid) -{ -#if defined(SIM_UIDH) - uid->H = SIM->UIDH; -#endif -#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM) - uid->M = SIM->UIDM; -#else - uid->MH = SIM->UIDMH; - uid->ML = SIM->UIDML; -#endif /* FSL_FEATURE_SIM_HAS_UIDM */ - uid->L = SIM->UIDL; -} - -#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) -void SIM_GetRfAddr(sim_rf_addr_t *info) -{ - info->rfAddrL = SIM->RFADDRL; - info->rfAddrH = SIM->RFADDRH; -} -#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.h deleted file mode 100644 index f98425cfaf51beba293b60431fdd5724af7628d5..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_sim.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SIM_H_ -#define _FSL_SIM_H_ - -#include "fsl_common.h" - -/*! @addtogroup sim */ -/*! @{*/ - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ -/*@}*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*!@brief USB voltage regulator enable setting. */ -enum _sim_usb_volt_reg_enable_mode -{ - kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ - kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ - kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ - kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | - SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ -}; -#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ - -/*!@brief Unique ID. */ -typedef struct _sim_uid -{ -#if defined(SIM_UIDH) - uint32_t H; /*!< UIDH. */ -#endif - -#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM) - uint32_t M; /*!< SIM_UIDM. */ -#else - uint32_t MH; /*!< UIDMH. */ - uint32_t ML; /*!< UIDML. */ -#endif /* FSL_FEATURE_SIM_HAS_UIDM */ - uint32_t L; /*!< UIDL. */ -} sim_uid_t; - -#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) -/*! @brief RF Mac Address.*/ -typedef struct _sim_rf_addr -{ - uint32_t rfAddrL; /*!< RFADDRL. */ - uint32_t rfAddrH; /*!< RFADDRH. */ -} sim_rf_addr_t; -#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ - -/*!@brief Flash enable mode. */ -enum _sim_flash_mode -{ - kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ - kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) -/*! - * @brief Sets the USB voltage regulator setting. - * - * This function configures whether the USB voltage regulator is enabled in - * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations - * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable - * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, - * use: - * - * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); - * - * @param mask USB voltage regulator enable setting. - */ -void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); -#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ - -/*! - * @brief Gets the unique identification register value. - * - * @param uid Pointer to the structure to save the UID value. - */ -void SIM_GetUniqueId(sim_uid_t *uid); - -/*! - * @brief Sets the flash enable mode. - * - * @param mode The mode to set; see \ref _sim_flash_mode for mode details. - */ -static inline void SIM_SetFlashMode(uint8_t mode) -{ - SIM->FCFG1 = mode; -} - -#if (defined(FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) && FSL_FEATURE_SIM_HAS_RF_MAC_ADDR) -/*! - * @brief Gets the RF address register value. - * - * @param info Pointer to the structure to save the RF address value. - */ -void SIM_GetRfAddr(sim_rf_addr_t *info); -#endif /* FSL_FEATURE_SIM_HAS_RF_MAC_ADDR */ - -#if (defined(FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN) && FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN) - -/*! - * @brief Enable the Systick clock or not. - * - * The Systick clock is enabled by default. - * - * @param enable The switcher for Systick clock. - */ -static inline void SIM_EnableSystickClock(bool enable) -{ - if (enable) - { - SIM->MISC2 &= ~SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Clear to enable. */ - } - else - { - SIM->MISC2 |= SIM_MISC2_SYSTICK_CLK_EN_MASK; /* Set to disable. */ - } -} - -#endif /* FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_SIM_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.c deleted file mode 100644 index 57d17ef779658e711d5a35d7d0254fc019356fd8..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_spm.h" -#include "math.h" /* Using floor() function to convert float variable to int. */ - -void SPM_GetRegulatorStatus(SPM_Type *base, spm_regulator_status_t *info) -{ - assert(info); - - volatile uint32_t tmp32 = base->RSR; /* volatile here is to make sure this value is actually from the hardware. */ - - info->isRadioRunForcePowerModeOn = (SPM_RSR_RFRUNFORCE_MASK == (tmp32 & SPM_RSR_RFRUNFORCE_MASK)); - info->radioLowPowerModeStatus = - (spm_radio_low_power_mode_status_t)((tmp32 & SPM_RSR_RFPMSTAT_MASK) >> SPM_RSR_RFPMSTAT_SHIFT); - info->mcuLowPowerModeStatus = - (spm_mcu_low_power_mode_status_t)((tmp32 & SPM_RSR_MCUPMSTAT_MASK) >> SPM_RSR_MCUPMSTAT_SHIFT); - info->isDcdcLdoOn = - (0x4 == (0x4 & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<2 responses DCDC LDO. */ - info->isRfLdoOn = - (0x2 == (0x2 & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<1 responses RF LDO. */ - info->isCoreLdoOn = - (0x1 == (0x1 & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<0 responses CORE LDO. */ -} - -void SPM_SetLowVoltDetectConfig(SPM_Type *base, const spm_low_volt_detect_config_t *config) -{ - uint32_t tmp32 = base->LVDSC1 & - ~(SPM_LVDSC1_VDD_LVDIE_MASK | SPM_LVDSC1_VDD_LVDRE_MASK | SPM_LVDSC1_VDD_LVDV_MASK | - SPM_LVDSC1_COREVDD_LVDIE_MASK | SPM_LVDSC1_COREVDD_LVDRE_MASK); - - /* VDD voltage detection. */ - tmp32 |= SPM_LVDSC1_VDD_LVDV(config->vddLowVoltDetectSelect); - if (config->enableIntOnVddLowVolt) - { - tmp32 |= SPM_LVDSC1_VDD_LVDIE_MASK; - } - if (config->enableResetOnVddLowVolt) - { - tmp32 |= SPM_LVDSC1_VDD_LVDRE_MASK; - } - /* Clear the Low Voltage Detect Flag with previouse power detect setting. */ - tmp32 |= SPM_LVDSC1_VDD_LVDACK_MASK; - - /* COREVDD voltage detection. */ - if (config->enableIntOnCoreLowVolt) - { - tmp32 |= SPM_LVDSC1_COREVDD_LVDIE_MASK; - } - if (config->enableResetOnCoreLowVolt) - { - tmp32 |= SPM_LVDSC1_COREVDD_LVDRE_MASK; - } - tmp32 |= SPM_LVDSC1_COREVDD_LVDACK_MASK; /* Clear previous error flag. */ - - base->LVDSC1 = tmp32; -} - -void SPM_SetLowVoltWarningConfig(SPM_Type *base, const spm_low_volt_warning_config_t *config) -{ - uint32_t tmp32 = base->LVDSC2 & ~(SPM_LVDSC2_VDD_LVWV_MASK | SPM_LVDSC2_VDD_LVWIE_MASK); - - tmp32 |= SPM_LVDSC2_VDD_LVWV(config->vddLowVoltDetectSelect); - if (config->enableIntOnVddLowVolt) - { - tmp32 |= SPM_LVDSC2_VDD_LVWIE_MASK; - } - tmp32 |= SPM_LVDSC2_VDD_LVWACK_MASK; /* Clear previous error flag. */ - - base->LVDSC2 = tmp32; -} - -void SPM_SetHighVoltDetectConfig(SPM_Type *base, const spm_high_volt_detect_config_t *config) -{ - uint32_t tmp32; - - tmp32 = base->HVDSC1 & ~(SPM_HVDSC1_VDD_HVDIE_MASK | SPM_HVDSC1_VDD_HVDRE_MASK |\ - SPM_HVDSC1_VDD_HVDV_MASK); - tmp32 |= SPM_HVDSC1_VDD_HVDV(config->vddHighVoltDetectSelect); - if(config->enableIntOnVddHighVolt) - { - tmp32 |= SPM_HVDSC1_VDD_HVDIE_MASK; - } - if(config->enableResetOnVddHighVolt) - { - tmp32 |= SPM_HVDSC1_VDD_HVDRE_MASK; - } - tmp32 |= SPM_HVDSC1_VDD_HVDACK_MASK; /* Clear previous error flag. */ - - base->HVDSC1 = tmp32; -} - -void SPM_SetRfLdoConfig(SPM_Type *base, const spm_rf_ldo_config_t *config) -{ - uint32_t tmp32 = 0U; - - switch (config->lowPowerMode) - { - case kSPM_RfLdoRemainInHighPowerInLowPowerModes: - tmp32 |= SPM_RFLDOLPCNFG_LPSEL_MASK; - break; - default: /* kSPM_RfLdoEnterLowPowerInLowPowerModes. */ - break; - } - base->RFLDOLPCNFG = tmp32; - - tmp32 = SPM_RFLDOSC_IOSSSEL(config->softStartDuration) | SPM_RFLDOSC_IOREGVSEL(config->rfIoRegulatorVolt); - if (config->enableCurSink) - { - tmp32 |= SPM_RFLDOSC_ISINKEN_MASK; - } - base->RFLDOSC = tmp32; -} - -void SPM_SetDcdcBattMonitor(SPM_Type *base, uint32_t batAdcVal) -{ - /* Clear the value and disable it at first. */ - base->DCDCC2 &= ~(SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK | SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK); - if (0U != batAdcVal) - { - /* When setting the value to BATT_VAL field, it should be zero before. */ - base->DCDCC2 |= SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(batAdcVal); - base->DCDCC2 |= SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK; - } -} - -void SPM_EnableVddxStepLock(SPM_Type *base, bool enable) -{ - if (enable) - { - base->DCDCC3 |= (SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK | SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK); - } - else - { - base->DCDCC3 &= ~(SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK | SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK); - } -} - -void SPM_BypassDcdcBattMonitor(SPM_Type *base, bool enable, uint32_t value) -{ - if (enable) - { - /* Set the user-defined value before enable the bypass. */ - base->DCDCC3 = (base->DCDCC3 & ~SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) | SPM_DCDCC3_DCDC_VBAT_VALUE(value); - /* Enable the bypass and load the user-defined value. */ - base->DCDCC3 |= SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; - } - else - { - base->DCDCC3 &= ~SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; - } -} - -void SPM_SetDcdcIntegratorConfig(SPM_Type *base, const spm_dcdc_integrator_config_t *config) -{ - int32_t tmp32u; - double dutyCycle; - - if (NULL == config) - { - base->DCDCC4 = 0U; - } - else - { - dutyCycle = ((config->vdd1p2Value / config->vBatValue)*32 - 16)*8192; - tmp32u = (int32_t)(dutyCycle); - base->DCDCC4 = SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK | SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK | - SPM_DCDCC4_INTEGRATOR_VALUE(tmp32u); - } -} - - - -void SPM_SetLowPowerReqOutPinConfig(SPM_Type *base, const spm_low_power_req_out_pin_config_t *config) -{ - if ((NULL == config) || (config->pinOutEnable)) - { - base->LPREQPINCNTRL = 0U; - } - else - { - base->LPREQPINCNTRL = - SPM_LPREQPINCNTRL_POLARITY(config->pinOutPol) | SPM_LPREQPINCNTRL_LPREQOE_MASK; /* Enable the output. */ - } -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.h deleted file mode 100644 index c6d7c51c9f28406d605248ccde4053f88249d6ab..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_spm.h +++ /dev/null @@ -1,861 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SPM_H_ -#define _FSL_SPM_H_ - -#include "fsl_common.h" - -/*! @addtogroup spm */ -/*! @{ */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SPM driver version */ -#define FSL_SPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/*! - * @brief IP version ID definition. - */ -typedef struct _spm_version_id -{ - uint16_t feature; /*!< Feature Specification Number. */ - uint8_t minor; /*!< Minor version number. */ - uint8_t major; /*!< Major version number. */ -} spm_version_id_t; - -/*! - * @brief Status of last RADIO Power Mode Configuration. - */ -typedef enum _spm_radio_low_power_mode_status -{ - kSPM_RadioLowPowerModeReserved = 0x0, /*!< Reserved. */ - kSPM_RadioLowPowerModeVLPS = 0x1, /*!< Current Power mode is VLPS. */ - kSPM_RadioLowPowerModeLLS = 0x2, /*!< Current Power mode is LLS. */ - kSPM_RadioLowPowerModeVLLS = 0x4, /*!< Current Power mode is VLLS. */ -} spm_radio_low_power_mode_status_t; - -/*! - * @brief Status of last MCU STOP Mode Power Configuration. - */ -typedef enum _spm_mcu_low_power_mode_status -{ - kSPM_McuLowPowerModeReserved = 0U, /*!< Reserved. */ - kSPM_McuLowPowerModeSTOP = 1U, /*!< Last Low Power mode is STOP. */ - kSPM_McuLowPowerModeVLPS = (1U << 1), /*!< Last Low Power mode is VLPS. */ - kSPM_McuLowPowerModeLLS = (1U << 2), /*!< Last Low Power mode is LLS. */ - kSPM_McuLowPowerModeVLLS23 = (1U << 3), /*!< Last Low Power mode is VLLS23. */ - kSPM_McuLowPowerModeVLLS01 = (1U << 4), /*!< Last Low Power mode is VLLS01. */ -} spm_mcu_low_power_mode_status_t; - -/*! - * @brief define the mask code for LDO regulators. - * - * These mask can be combined with 'or' as a parameter to any function. - */ -enum _spm_ldo_regulator -{ - kSPM_CoreLdo = 1U, /*!< Mask code for CORE LDO. */ - kSPM_RfLdo = (1U << 1), /*!< Mask code for RF LDO. */ - kSPM_DcdcLdo = (1U << 2), /*!< Mask code for DCDC LDO. */ -}; - -/*! - * @brief Keep the regulator status information. - */ -typedef struct _spm_regulator_status -{ - bool isRadioRunForcePowerModeOn; /*!< RADIO Run Force Power Mode Status. */ - spm_radio_low_power_mode_status_t radioLowPowerModeStatus; /*!< Status of last RADIO Power Mode Configuration. */ - spm_mcu_low_power_mode_status_t mcuLowPowerModeStatus; /*!< Status of last MCU STOP Mode Power Configuration. */ - bool isDcdcLdoOn; /*!< DCDC LDO regulator enabled. */ - bool isRfLdoOn; /*!< RF LDO regulator enabled. */ - bool isCoreLdoOn; /*!< Core LDO regulator enabled. */ -} spm_regulator_status_t; - -/*! - * @brief Configure the CORE LDO in run modes. - */ -enum _spm_core_ldo_run_mode_config -{ - kSPM_CoreLdoRunModeEnableRtcPowerMonitor = - SPM_CORERCNFG_RTCVDDMEN_MASK, /*!< RTC power monitor enabled in run modes. */ - kSPM_CoreLdoRunModeEnableUsbPowerMonitor = - SPM_CORERCNFG_USBVDDMEN_MASK, /*!< USB power monitor enabled in run modes. */ - kSPM_CoreLdoRunModeEnableVddioPowerMonitor = - SPM_CORERCNFG_VDDIOVDDMEN_MASK, /*!< VDDIO power monitor enabled in run modes. */ -}; - -/*! - * @brief Configure the CORE LDO in low power modes. - */ -enum _spm_core_ldo_low_power_mode_config -{ - kSPM_CoreLdoLowPowerModeEnableRtcPowerMonitor = - SPM_CORELPCNFG_RTCVDDMEN_MASK, /*!< RTC power monitor enabled in LP modes. */ - kSPM_CoreLdoLowPowerModeEnableUsbPowerMonitor = - SPM_CORELPCNFG_USBVDDMEN_MASK, /*!< USB power monitor enabled in LP modes. */ - kSPM_CoreLdoLowPowerModeEnableVddioPowerMonitor = - SPM_CORELPCNFG_VDDIOVDDMEN_MASK, /*!< VDDIO power monitor enabled in LP modes. */ - kSPM_CoreLdoLowPowerModeEnableAllReference = - SPM_CORELPCNFG_ALLREFEN_MASK, /*!< Enable all reference (bandgap, WELL - BIAS, 1k clk and LP 25na) in VLLS. */ - kSPM_CoreLdoLowPowerModeEnableHighDrive = SPM_CORELPCNFG_LPHIDRIVE_MASK, /*!< Enable high driver in low power. */ - kSPM_CoreLdoLowPowerModeEnableLVD = - SPM_CORELPCNFG_LVDEN_MASK, /*!< Enable level voltage detect in VLP/STOP modes. */ - kSPM_CoreLdoLowPowerModeEnablePOR = SPM_CORELPCNFG_POREN_MASK, /*!< POR brownout remains enabled in VLLS mode. */ - kSPM_CoreLdoLowPowerModeEnableLPO = SPM_CORELPCNFG_LPOEN_MASK, /*!< LPO remains enabled in VLLS modes. */ - kSPM_CoreLdoLowPowerModeEnableBandgapBufferHightDrive = - SPM_CORELPCNFG_BGBDS_MASK, /*!< Enable the high drive for Bandgap Buffer. */ - kSPM_CoreLdoLowPowerModeEnableBandgapBuffer = SPM_CORELPCNFG_BGBEN_MASK, /*!< Enable Bandgap Buffer. */ - kSPM_CoreLdoLowPowerModeEnableBandgapInVLPx = SPM_CORELPCNFG_BGEN_MASK, /*!< Enable Bandgap in VLPx mode. */ - kSPM_CoreLdoLowPowerModeRemainInHighPower = - SPM_CORELPCNFG_LPSEL_MASK, /*!< Core LDO remains in high power state in VLP/Stop modes. */ -}; - -/*! - * @brief Sets the Core LDO voltage level. - */ -typedef enum _spm_core_ldo_voltage_select -{ - kSPM_CoreLdoVoltLevel1P2 = 0U, /*!< Regulate to 1.2V set by the CORETRIM[VTRIM1P2] register. */ - kSPM_CoreLdoVoltLevel1P1 = 1U, /*!< Regulate to 1.1V set by the CORETRIM[VTRIM1P1] register. */ - kSPM_CoreLdoVoltLevelOffset = 3U, /*!< Regulate to Offset Voltage set by CORETRIM[OFFVTRIM] register. */ -} spm_core_ldo_volt_select_t; - -/*! - * @brief Low-voltage Detect Voltage Select - */ -typedef enum _spm_low_volt_detect_volt_select -{ - kSPM_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/ - kSPM_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/ -} spm_low_volt_detect_volt_select_t; - -/*! - * @brief Low-voltage Detect Configuration Structure. - * - * This structure reuses the configuration structure from legacy PMC module. - */ -typedef struct _spm_low_volt_detect_config -{ - /* VDD voltage detection. */ - bool enableIntOnVddLowVolt; /*!< Enable interrupt when VDD Low-voltage detect. */ - bool enableResetOnVddLowVolt; /*!< Enable forcing a system reset when VDD Low-voltage detect. */ - spm_low_volt_detect_volt_select_t vddLowVoltDetectSelect; /*!< Low-voltage detect trip point voltage selection. */ - - /* CORE voltage detection. */ - bool enableIntOnCoreLowVolt; /*!< Enable interrupt when Core Low-voltage detect. */ - bool enableResetOnCoreLowVolt; /*!< Enable forcing a system reset when Core Low-voltage detect. */ -} spm_low_volt_detect_config_t; - -/*! - * @brief Low-voltage Warning Voltage Select. - */ -typedef enum _spm_low_volt_warning_volt_select -{ - kSPM_LowVoltWarningLowTrip = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/ - kSPM_LowVoltWarningMID1Trip = 1U, /*!< Mid1-trip point selected (VLVW = VLVW2)*/ - kSPM_LowVoltWarningMID2Trip = 2U, /*!< Mid2-trip point selected (VLVW = VLVW3)*/ - kSPM_LowVoltWarningHighTrip = 3U /*!< High-trip point selected (VLVW = VLVW4)*/ -} spm_low_volt_warning_volt_select_t; - -/*! - * @brief Low-voltage Warning Configuration Structure - */ -typedef struct _spm_low_volt_warning_config -{ - bool enableIntOnVddLowVolt; /*!< Enable interrupt when low-voltage warning*/ - spm_low_volt_warning_volt_select_t vddLowVoltDetectSelect; /*!< Low-voltage warning trip point voltage selection*/ -} spm_low_volt_warning_config_t; - -/*! - * @brief High-voltage Detect Voltage Select. - */ -typedef enum _spm_high_volt_detect_volt_select -{ - kSPM_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/ - kSPM_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/ -} spm_high_volt_detect_volt_select_t; - -/*! - * @brief High-voltage Detect Configuration Structure. - * - * This structure reuses the configuration structure from legacy PMC module. - */ -typedef struct _spm_high_volt_detect_config -{ - bool enableIntOnVddHighVolt; /*!< Enable interrupt when high-voltage detect*/ - bool enableResetOnVddHighVolt; /*!< Enable system reset when high-voltage detect*/ - spm_high_volt_detect_volt_select_t vddHighVoltDetectSelect; /*!< High-voltage detect trip point voltage selection*/ -} spm_high_volt_detect_config_t; - -/*! - * @brief Defines the RF LDO low power behiavior when in low power modes. - */ -typedef enum _spm_rf_ldo_low_power_mode -{ - kSPM_RfLdoEnterLowPowerInLowPowerModes = 0U, /*!< RF LDO regulator enters low power state in VLP/Stop modes. */ - kSPM_RfLdoRemainInHighPowerInLowPowerModes = - 1U, /*!< RF LDO regulator remains in high power state in VLP/Stop modes. */ -} spm_rf_ldo_low_power_mode_t; - -/*! - * @brief Selects the soft start duration delay for the IO 1.8 full power regulator. - */ -typedef enum _spm_rf_ldo_soft_start_duration -{ - kSPM_RfLdoSoftStartDuration110us = 0U, /*!< 110 us. */ - kSPM_RfLdoSoftStartDuration95us = 1U, /*!< 95 us. */ - kSPM_RfLdoSoftStartDuration60us = 2U, /*!< 60 us. */ - kSPM_RfLdoSoftStartDuration48us = 3U, /*!< 48 us. */ - kSPM_RfLdoSoftStartDuration38us = 4U, /*!< 38 us. */ - kSPM_RfLdoSoftStartDuration30us = 5U, /*!< 30 us. */ - kSPM_RfLdoSoftStartDuration24us = 6U, /*!< 24 us. */ - kSPM_RfLdoSoftStartDuration17us = 7U, /*!< 17 us. */ -} spm_rf_ldo_soft_start_duration_t; - -/*! - * @brief IO Regulator Voltage Select. - */ -typedef enum _spm_rf_io_regulator_volt_select -{ - kSPM_RfIoRegulatorVoltLevel1p8 = 0U, /*!< Regulate to 1.8V. */ - kSPM_RfIoRegulatorVoltLevel1p5 = 1U, /*!< Regulate to 1.5V. */ -} spm_rf_io_regulator_volt_select_t; - -/*! - * @brief RF LDO configuration structure. - */ -typedef struct _spm_rf_ldo_config -{ - spm_rf_ldo_low_power_mode_t lowPowerMode; /*!< RF LDO low power behaviour when in low power modes. */ - spm_rf_ldo_soft_start_duration_t - softStartDuration; /*!< Selects the soft start duration delay for the IO 1.8 full power regulator. */ - bool enableCurSink; /*!< Enables current sink feature of low power regulator.*/ - spm_rf_io_regulator_volt_select_t rfIoRegulatorVolt; /*!< IO Regulator Voltage Select. */ -} spm_rf_ldo_config_t; - -/*! - * @brief Selects which sns 1p8 vdd pin is used. - */ -typedef enum _spm_rf_vdd_1p8_sns_pin_select -{ - kSPM_RfVdd1p8Sns0 = 0U, /*!< VDD1p8_SNS0 selected. */ - kSPM_RfVdd1p8Sns1 = 1U, /*!< VDD1p8_SNS1 selected. */ -} spm_rf_vdd_1p8_sns_pin_select_t; - -/*! - * @brief Selects the trim point for RF LDO. - */ -typedef enum _spm_rf_ldo_volt_trim_select -{ - kSPM_RfLdoLowPowerVolt1p8Trim, /*!< RF LDO Low Power 1.8V trim point value. */ - kSPM_RfLdoLowPowerVlot1p5Trim, /*!< RF LDO Low Power 1.5V trim point value. */ - kSPM_RfLdoHighPowerVolt1p8Trim, /*!< RF LDO High Power 1.8V trim point value. */ - kSPM_RfLdoHighPowerVolt1p5Trim, /*!< RF LDO High Power 1.5V trim point value/ */ - kSPM_RfLdoRegulatorOffsetTrim, -} spm_rf_ldo_volt_trim_select_t; - -/*! - * @brief Configuration for setting DCDC integrator value. - */ -typedef struct _spm_dcdc_integrator_value_config -{ - double vdd1p2Value; /*!< VDD1P2 output voltage value. */ - double vBatValue; /*!< Battery input voltage value, or the Vdd_dcdcin voltage value. */ -} spm_dcdc_integrator_config_t; - -/*! - * @brief Defines the selection of DCDC vbat voltage divider for ADC measure. - */ -typedef enum _spm_dcdc_vbat_adc_divider -{ - kSPM_DcdcVbatAdcOff = 0U, /*!< OFF. */ - kSPM_DcdcVbatAdcDivider1 = 1U, /*!< VBAT. */ - kSPM_DcdcVbatAdcDivider2 = 2U, /*!< VBAT /2. */ - kSPM_DcdcVbatAdcDivider4 = 3U, /*!< VBAT /4. */ -} spm_dcdc_vbat_adc_divider_t; - -/*! - * @brief Configuration of power switch delay. - */ -typedef struct _spm_power_switch_delay_config -{ - uint32_t coreRegFromDeepPowerDownToIso; /*!< Deep Power Down Wakeup Switch to ISO Delay. <= 0xFF */ - uint32_t coreRegFromLowPowerToIso; /*!< Low Power Wakeup Switch to ISO Delay. */ - uint32_t lowPowerToBandgapOn; /*!< Low Power Wake Up Delay. */ - uint32_t dcdcStartupDelay; /*!< Configures the number of cycles for DCDC startup before the Core - LDO or RF LDO can be disabled. */ - uint32_t ldoCoreSwitchHsrunDelay; /*!< Configures the number of cycles delay for LDO CORE - Regulator in and out of HSRUN mode. */ -} spm_power_switch_delay_config_t; - -/*! - * @brief Defines the selection of low power request pin out pin polarity. - */ -typedef enum _spm_low_power_req_out_pin_pol -{ - kSPM_LowPowerReqOutPinHighTruePol = 0U, /*!< High true polarity. */ - kSPM_LowPowerReqOutPinLowTruePol = 1U, /*!< Low true polarity. */ -} spm_low_power_req_out_pin_pol_t; - -/*! - * @brief Configuration structure of low power request out pin. - */ -typedef struct _spm_low_power_req_out_pin_config -{ - spm_low_power_req_out_pin_pol_t pinOutPol; /*!< ow power request pin out pin polarity. */ - bool pinOutEnable; /*!< Low Power request output pin is enabled or not. */ -} spm_low_power_req_out_pin_config_t; - -/*! - * @brief Defines the selection of DCDC driver strength. - * - * The more FETs are enabled, the more drive strength DCDC would provide. - */ -typedef enum _spm_dcdc_drive_strength -{ - kSPM_DcdcDriveStrengthWithNormal = 0U, /*!< No additional FET setting. */ - kSPM_DcdcDriveStrengthWithHalfFETs = 0x4, /*!< Half FETs. */ - kSPM_DcdcDriveStrengthWithDoubleFETs = 0x2, /*!< Double FETs. */ - kSPM_DcdcDriveStrengthWithExtraHalfFETs = 0x1, /*!< Half FETs. */ - kSPM_DcdcDriveStrengthWithHalfAndDoubleFETs = 0x6, /*!< Half + Double FETs. */ - kSPM_DcdcDriveStrengthWithHalfAndExtraDoubleFETs = 0x5, /*!< Half + Extra Double FETs. */ - kSPM_DcdcDriveStrengthWithDoubleAndExtraDoubleFETs = 0x3, /*!< Double + Extra Double FETs. */ - kSPM_DcdcDriveStrengthWithAllFETs = 7U, /*!< Half + Double + Extra Double FETs. */ -} spm_dcdc_drive_strength_t; - -/*! - * @brief DCDC flags. - */ -enum _spm_dcdc_flags -{ - kSPM_DcdcStableOKFlag = SPM_DCDCSC_DCDC_STS_DC_OK_MASK, /*!< Status flag to indicate DCDC lock. */ - kSPM_DcdcClockFaultFlag = - SPM_DCDCSC_CLKFLT_FAULT_MASK, /*!< Asserts if DCDC detect a clk fault. Will cause a system lvd reset to assert. - */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! @name System Power Manager. */ -/*@{*/ - -/*! - * @brief Gets the SPM version ID. - * - * This function gets the SPM version ID, including major version number, - * minor version number, and a feature specification number. - * - * @param base SPM peripheral base address. - * @param versionId Pointer to version ID structure. - */ -static inline void SPM_GetVersionId(SPM_Type *base, spm_version_id_t *versionId) -{ - *((uint32_t *)versionId) = base->VERID; -} - -/*! - * @brief Gets the regulators Status. - * - * @param base SPM peripheral base address. - * @param info Pointer to status structure, see to #spm_regulator_status_t. - */ -void SPM_GetRegulatorStatus(SPM_Type *base, spm_regulator_status_t *info); - -/*! - * @brief Controls which regulators are enabled in RUN and HSRUN modes. - * - * This function controls which regulator (CORE LDO, RF LDO, and DCDC) are enabled in RUN and HSRUN - * modes. It sets the SPM_RCTRL register. - * Note that the RCTRL bits are reset solely on a POR/LVD only event. - * - * @param base SPM peripheral base address. - * @param enable Enable or disable the LDOs list in ldoMask. - * @param ldoMask Mask value of LDO list. See to #_spm_ldo_regulator. - */ -static inline void SPM_EnableRegulatorInRunMdoe(SPM_Type *base, bool enable, uint32_t ldoMask) -{ - if (enable) - { - base->RCTRL |= SPM_RCTRL_REGSEL(ldoMask); - } - else - { - base->RCTRL &= ~SPM_RCTRL_REGSEL(ldoMask); - } -} - -/*! - * @brief Controls which regulators are enabled in low power modes. - * - * This function controls which regulator (CORE LDO, RF LDO, and DCDC) are enabled in low power - * modes. It sets the SPM_LPCTRL register. - * Note that the SPM_LPCTRL bits are reset solely on a POR/LVD only event. - * - * @param base SPM peripheral base address. - * @param enable Enable or disable the LDOs list in ldoMask. - * @param ldoMask Mask value of LDO list. - */ -static inline void SPM_EnableRegulatorInLowPowerMode(SPM_Type *base, bool enable, uint32_t ldoMask) -{ - if (enable) - { - base->LPCTRL |= SPM_LPCTRL_REGSEL(ldoMask); - } - else - { - base->LPCTRL &= ~SPM_LPCTRL_REGSEL(ldoMask); - } -} - -/*! - * @brief Configures the CORE LDO working in run modes. - * - * @param base SPM peripheral base address. - * @param conifgMask Mask value of configuration items. See to #_spm_core_ldo_run_mode_config. - */ -static inline void SPM_SetCoreLdoRunModeConfig(SPM_Type *base, uint32_t configMask) -{ - base->CORERCNFG = configMask; -} - -/*! - * @brief Configures the CORE LDO working in low power modes. - * - * @param base SPM peripheral base address. - * @param conifgMask Mask value of configuration items. See to #_spm_core_ldo_low_power_mode_config. - */ -static inline void SPM_SetCoreLdoLowPowerModeConfig(SPM_Type *base, uint32_t configMask) -{ - base->CORELPCNFG = configMask; -} - -/*! - * @brief Check if the CORE LDO is in run regulation. - * - * @param base SPM peripheral base address. - * @retval true Regulator is in run regulation. - * @retval false Regulator is in stop regulation or in transition to/from it. - */ -static inline bool SPM_GetCoreLdoInRunRegulationFlag(SPM_Type *base) -{ - return (SPM_CORESC_REGONS_MASK == (SPM_CORESC_REGONS_MASK & base->CORESC)); -} - -/*! - * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. - * - * This function reads the Acknowledge Isolation setting that indicates - * whether certain peripherals and the I/O pads are in a latched state as - * a result of having been in the VLLS mode. - * - * @param base SPM peripheral base address. - * @return ACK isolation - * 0 - Peripherals and I/O pads are in a normal run state. - * 1 - Certain peripherals and I/O pads are in an isolated and - * latched state. - */ -static inline bool SPM_GetPeriphIOIsolationFlag(SPM_Type *base) -{ - return (SPM_CORESC_ACKISO_MASK == (base->CORESC & SPM_CORESC_ACKISO_MASK)); -} - -/*! - * @brief Acknowledges the isolation flag to Peripherals and I/O pads. - * - * This function clears the ACK Isolation flag. Writing one to this setting - * when it is set releases the I/O pads and certain peripherals to their normal - * run mode state. - * - * @param base SPM peripheral base address. - */ -static inline void SPM_ClearPeriphIOIsolationFlag(SPM_Type *base) -{ - base->CORESC |= SPM_CORESC_ACKISO_MASK; -} - -/*@}*/ - -/*! @name VDD Low voltage detection APIs*/ -/*@{*/ - -/*! - * @brief Configures the low-voltage detect setting. - * - * This function configures the low-voltage detect setting, including the trip - * point voltage setting, enables or disables the interrupt, enables or disables the system reset. - * - * @param base SPM peripheral base address. - * @param config Pointer to low-voltage detect configuration structure, see to #spm_low_volt_detect_config_t. - */ -void SPM_SetLowVoltDetectConfig(SPM_Type *base, const spm_low_volt_detect_config_t *config); - -/*! - * @brief Gets VDD Low-voltage Detect Flag status. - * - * @param base SPM peripheral base address. - * @return Current low-voltage detect flag - * - true: Low-voltage detected - * - false: Low-voltage not detected - */ -static inline bool SPM_GetVddLowVoltDetectFlag(SPM_Type *base) -{ - return (SPM_LVDSC1_VDD_LVDF_MASK == (base->LVDSC1 & SPM_LVDSC1_VDD_LVDF_MASK)); -} - -/*! - * @brief Acknowledges clearing the Low-voltage Detect flag. - * - * This function acknowledges the low-voltage detection errors. - * - * @param base SPM peripheral base address. - */ -static inline void SPM_ClearVddLowVoltDetectFlag(SPM_Type *base) -{ - base->LVDSC1 |= SPM_LVDSC1_VDD_LVDACK_MASK; /* W1C. */ -} - -/*@}*/ - -/*! @name CORE LDO Low voltage detection APIs */ -/*@{*/ - -/*! - * @brief Gets the COREVdds Low-voltage Detect Flag status. - * - * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected. - * - * @param base SPM peripheral base address. - * @return Current low-voltage detect flag - * - true: Low-voltage detected - * - false: Low-voltage not detected - */ -static inline bool SPM_GetCoreLowVoltDetectFlag(SPM_Type *base) -{ - return (SPM_LVDSC1_COREVDD_LVDF_MASK == (base->LVDSC1 & SPM_LVDSC1_COREVDD_LVDF_MASK)); -} - -/*! - * @brief Acknowledges clearing the CORE VDD Low-voltage Detect flag. - * - * This function acknowledges the CORE VDD low-voltage detection errors. - * - * @param base SPM peripheral base address. - */ -static inline void SPM_ClearCoreLowVoltDetectFlag(SPM_Type *base) -{ - base->LVDSC1 |= SPM_LVDSC1_COREVDD_LVDACK_MASK; /* W1C. */ -} - -/*! - * @brief Configures the low-voltage warning setting. - * - * This function configures the low-voltage warning setting, including the trip - * point voltage setting and enabling or disabling the interrupt. - * - * @param base SPM peripheral base address. - * @param config Pointer to Low-voltage warning configuration structure, see to #spm_low_volt_warning_config_t. - */ -void SPM_SetLowVoltWarningConfig(SPM_Type *base, const spm_low_volt_warning_config_t *config); - -/*! - * @brief Gets Vdd Low-voltage Warning Flag status. - * - * This function polls the current LVWF status. When 1 is returned, it - * indicates a low-voltage warning event. LVWF is set when V Supply transitions - * below the trip point or after reset and V Supply is already below the V LVW. - * - * @param base SPM peripheral base address. - * @return Current LVWF status - * - true: Low-voltage Warning Flag is set. - * - false: the Low-voltage Warning does not happen. - */ -static inline bool SPM_GetVddLowVoltWarningFlag(SPM_Type *base) -{ - return (SPM_LVDSC2_VDD_LVWF_MASK == (base->LVDSC2 & SPM_LVDSC2_VDD_LVWF_MASK)); -} - -/*! - * @brief Acknowledges the Low-voltage Warning flag. - * - * This function acknowledges the low voltage warning errors (write 1 to - * clear LVWF). - * - * @param base SPM peripheral base address. - */ -static inline void SPM_ClearLowVoltWarningFlag(SPM_Type *base) -{ - base->LVDSC2 |= SPM_LVDSC2_VDD_LVWACK_MASK; /* W1C. */ -} - -/*@}*/ - -/*! @name VDD high voltage detection APIs. */ -/*@{*/ - -/*! - * @brief Configures the high-voltage detect setting. - * - * This function configures the high-voltage detect setting, including the trip - * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. - * - * @param base SPM peripheral base address. - * @param config High-voltage detect configuration structure, see to #spm_high_volt_detect_config_t. - */ -void SPM_SetHighVoltDetectConfig(SPM_Type *base, const spm_high_volt_detect_config_t *config); - -/*! - * @brief Gets the High-voltage Detect Flag status. - * - * This function reads the current HVDF status. If it returns 1, a low - * voltage event is detected. - * - * @param base SPM peripheral base address. - * @return Current high-voltage detect flag - * - true: High-voltage detected - * - false: High-voltage not detected - */ -static inline bool SPM_GetHighVoltDetectFlag(SPM_Type *base) -{ - return (SPM_HVDSC1_VDD_HVDF_MASK == (base->HVDSC1 & SPM_HVDSC1_VDD_HVDF_MASK)); -} - -/*! - * @brief Acknowledges clearing the High-voltage Detect flag. - * - * This function acknowledges the high-voltage detection errors (write 1 to - * clear HVDF). - * - * @param base SPM peripheral base address. - */ -static inline void SPM_ClearHighVoltDetectFlag(SPM_Type *base) -{ - base->HVDSC1 |= SPM_HVDSC1_VDD_HVDACK_MASK; /* W1C. */ -} - -/*@}*/ - -/*! @name RF LDO Low voltage detection APIs */ -/*@{*/ - -/*! - * @brief Configures the RF LDO. - * - * @param base SPM peripheral base address. - * @param config Pointer to configuration structure, see to #spm_rf_ldo_config_t. - */ -void SPM_SetRfLdoConfig(SPM_Type *base, const spm_rf_ldo_config_t *config); - -/*! - * @brief Selects which SNS 1p8 vdd pin is used. - * - * @param base SPM peripheral base address. - * @param pin Selection of SNS 1p8 Vdd pin to be used, see to #spm_rf_vdd_1p8_sns_pin_select_t. - */ -static inline void SPM_SelectVdd1p8SnsPin(SPM_Type *base, spm_rf_vdd_1p8_sns_pin_select_t pin) -{ - base->RFLDOSC = (base->RFLDOSC & ~SPM_RFLDOSC_VDD1P8SEL_MASK) | SPM_RFLDOSC_VDD1P8SEL(pin); -} - -/*! @name DCDC Control APIs*/ -/*@{*/ - -/*! - * @brief Sets DCDC battery monitor with its ADC value. - * - * For better accuracy, software would call this function to set the battery voltage value into DCDC - * measured by ADC. - * - * @param base SPM peripheral base address. - * @param batAdcVal ADC measured battery value with an 8mV LSB resolution. - * Value 0 would disable the battery monitor. - */ -void SPM_SetDcdcBattMonitor(SPM_Type *base, uint32_t batAdcVal); - -/*! - * @brief Sets DCDC VBAT voltage divider. - * - * The divided VBAT output is input to an ADC channel which allows the battery voltage to be measured. - * - * @param base SPM peripheral base address. - * @param divider Setting divider, see to #spm_dcdc_vbat_adc_divider_t. - */ -static inline void SPM_SetDcdcVbatAdcMeasure(SPM_Type *base, spm_dcdc_vbat_adc_divider_t divider) -{ - base->DCDCSC = (base->DCDCSC & ~SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) | SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(divider); -} - -/*! - * @brief Power down output range comparator. - * - * @param base SPM peripheral base address. - * @param enable Power down the CMP or not. - */ -static inline void SPM_EnablePowerDownCmpOffset(SPM_Type *base, bool enable) -{ - if (enable) - { - base->DCDCSC |= SPM_DCDCSC_PWD_CMP_OFFSET_MASK; - } - else - { - base->DCDCSC &= ~SPM_DCDCSC_PWD_CMP_OFFSET_MASK; - } -} - -/*! - * @brief Get the status flags of DCDC module. - * - * @param base SPM peripheral base address. - * @return Mask value of flags. See to #_spm_dcdc_flags. - */ -static inline uint32_t SPM_GetDcdcStatusFlags(SPM_Type *base) -{ - return (base->DCDCSC & (SPM_DCDCSC_DCDC_STS_DC_OK_MASK | SPM_DCDCSC_CLKFLT_FAULT_MASK)); -} - -/*! - * @brief Disable stepping for VDD1P8 and VDD1P2. - * - * Must lock the step for VDD1P8 and VDD1p2 before enteing low power modes. - * - * @param base SPM peripheral base address. - * @param enable Enable the lock or not to VDDx stepping. - */ -void SPM_EnableVddxStepLock(SPM_Type *base, bool enable); - -/*! - * @brief Set the DCDC drive strength. - * - * Do set the DCDC drive strength according to actuall loading. - * The related register bits are: - * - DCDCC3[DCDC_MINPWR_HALF_FETS] - * - DCDCC3[DCDC_MINPWR_DOUBLE_FETS] - * - DCDCC3[DCDC_MINPWR_EXTRA_DOUBLE_FETS] - * The more FETs are enabled, the more drive strength DCDC would provide. - * - * @param base SPM peripheral base address. - * @param strength Selection of setting, see to #spm_dcdc_drive_strength_t - */ -static inline void SPM_SetDcdcDriveStrength(SPM_Type *base, spm_dcdc_drive_strength_t strength) -{ - base->DCDCC3 = (base->DCDCC3 & ~0xE000000U) | ((uint32_t)(strength) << 25); -} - -/*! - * @brief Bypasses the ADC measure value - * - * Forces DCDC to bypass the adc measuring state and loads the user-defined value in this function. - * - * @param base SPM peripheral base address. - * @param enable Enable the bypass or not. - * @param value User-setting value to be available instead of ADC measured value. - */ -void SPM_BypassDcdcBattMonitor(SPM_Type *base, bool enable, uint32_t value); - -/*! - * @brief Configure the DCDC integrator value. - * - * Integrator value can be loaded in pulsed mode. Software can program this value according to - * battery voltage and VDD1P2 output target value before goes to the pulsed mode. - * - @code - spm_dcdc_integrator_config_t SpmDcdcIntegratorConfigStruct = - { - .vdd1p2Value = 1.2f, - .vBatValue = 3.34f - }; - @endcode - * - * @param base SPM peripheral base address. - * @param config Pointer to configuration structure, see to #spm_dcdc_integrator_config_t. - * Passing NULL would clear all user-defined setting and use hardware default setting. - */ -void SPM_SetDcdcIntegratorConfig(SPM_Type *base, const spm_dcdc_integrator_config_t *config); - -/*! - * @brief Sets the target value of VDD1P2 in buck HSRUN mode. - * - * Sets target value of VDD1P2 in buck HSRUN mode. 25 mV each step from 0x00 to 0x0F. This value is - * automatically selected on entry into HSRUN. On exit from HSRUN, DCDC VDD1P2 trim values will - * default back to values set by DCDC_VDD1P2CTRL_TRG_BUCK register, which is operated with the API of - * SPM_SetDcdcVdd1p2ValueBuck(). - * - * @param base SPM peripheral base address. - * @param value Setting value of VDD1P2 in buck HSRUN mode. - */ -static inline void SPM_SetDcdcVdd1p2ValueHsrun(SPM_Type *base, uint32_t value) -{ - base->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) | SPM_DCDCC6_DCDC_HSVDD_TRIM(value); -} - -/*! - * @brief Sets the target value of VDD1P2 in buck mode. - * - * Sets the target value of VDD1P2 in buck mode, 25 mV each step from 0x00 to 0x0F. - * - * @param base SPM peripheral base address. - * @param value Setting value of VDD1P2 in buck mode. - */ -static inline void SPM_SetDcdcVdd1p2ValueBuck(SPM_Type *base, uint32_t value) -{ - base->DCDCC6 = - (base->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK) | SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(value); -} - -/*! - * @brief Sets the target value of VDD1P8. - * - * Sets the target value of VDD1P8 in buck mode, 25 mV each step from 0x00 to 0x3F. - * - * @param base SPM peripheral base address. - * @param value Setting value of VDD1P8 output. - */ -static inline void SPM_SetDcdcVdd1p8Value(SPM_Type *base, uint32_t value) -{ - base->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK) | SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(value); -} - -/*@}*/ - -/*! @name Misc */ -/*@{*/ - -/*! - * @brief Configures the low power requeset output pin. - * - * @param base SPM peripheral base address. - * @param config Pointer to the configuration structure, see to #spm_low_power_req_out_pin_config_t. - */ -void SPM_SetLowPowerReqOutPinConfig(SPM_Type *base, const spm_low_power_req_out_pin_config_t *config); - -/*@}*/ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_SPM_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.c deleted file mode 100644 index eecb5ee139a6b4bafd6a3f0639e5e9a2e8c9d203..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.c +++ /dev/null @@ -1,744 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_tpm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define TPM_COMBINE_SHIFT (8U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base TPM peripheral base address - * - * @return The TPM instance - */ -static uint32_t TPM_GetInstance(TPM_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to TPM bases for each instance. */ -static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to TPM clocks for each instance. */ -static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t TPM_GetInstance(TPM_Type *base) -{ - uint32_t instance; - uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < tpmArrayCount; instance++) - { - if (s_tpmBases[instance] == base) - { - break; - } - } - - assert(instance < tpmArrayCount); - - return instance; -} - -void TPM_Init(TPM_Type *base, const tpm_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the module clock */ - CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL - /* TPM reset is available on certain SoC's */ - TPM_Reset(base); -#endif - - /* Set the clock prescale factor */ - base->SC = TPM_SC_PS(config->prescale); - - /* Setup the counter operation */ - base->CONF = TPM_CONF_DOZEEN(config->enableDoze) | TPM_CONF_GTBEEN(config->useGlobalTimeBase) | - TPM_CONF_CROT(config->enableReloadOnTrigger) | TPM_CONF_CSOT(config->enableStartOnTrigger) | - TPM_CONF_CSOO(config->enableStopOnOverflow) | -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - TPM_CONF_CPOT(config->enablePauseOnTrigger) | -#endif -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - TPM_CONF_TRGSRC(config->triggerSource) | -#endif - TPM_CONF_TRGSEL(config->triggerSelect); - if (config->enableDebugMode) - { - base->CONF |= TPM_CONF_DBGMODE_MASK; - } - else - { - base->CONF &= ~TPM_CONF_DBGMODE_MASK; - } -} - -void TPM_Deinit(TPM_Type *base) -{ - /* Stop the counter */ - base->SC &= ~TPM_SC_CMOD_MASK; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the TPM clock */ - CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void TPM_GetDefaultConfig(tpm_config_t *config) -{ - assert(config); - - /* TPM clock divide by 1 */ - config->prescale = kTPM_Prescale_Divide_1; - /* Use internal TPM counter as timebase */ - config->useGlobalTimeBase = false; - /* TPM counter continues in doze mode */ - config->enableDoze = false; - /* TPM counter pauses when in debug mode */ - config->enableDebugMode = false; - /* TPM counter will not be reloaded on input trigger */ - config->enableReloadOnTrigger = false; - /* TPM counter continues running after overflow */ - config->enableStopOnOverflow = false; - /* TPM counter starts immediately once it is enabled */ - config->enableStartOnTrigger = false; -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - config->enablePauseOnTrigger = false; -#endif - /* Choose trigger select 0 as input trigger for controlling counter operation */ - config->triggerSelect = kTPM_Trigger_Select_0; -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - /* Choose external trigger source to control counter operation */ - config->triggerSource = kTPM_TriggerSource_External; -#endif -} - -status_t TPM_SetupPwm(TPM_Type *base, - const tpm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - tpm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz) -{ - assert(chnlParams); - assert(pwmFreq_Hz); - assert(numOfChnls); - assert(srcClock_Hz); -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if(mode == kTPM_CombinedPwm) - { - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - } -#endif - - uint32_t mod; - uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK))); - uint16_t cnv; - uint8_t i; - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/ - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } -#endif - - switch (mode) - { - case kTPM_EdgeAlignedPwm: -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - case kTPM_CombinedPwm: -#endif - base->SC &= ~TPM_SC_CPWMS_MASK; - mod = (tpmClock / pwmFreq_Hz) - 1; - break; - case kTPM_CenterAlignedPwm: - base->SC |= TPM_SC_CPWMS_MASK; - mod = tpmClock / (pwmFreq_Hz * 2); - break; - default: - return kStatus_Fail; - } - - /* Return an error in case we overflow the registers, probably would require changing - * clock source to get the desired frequency */ - if (mod > 65535U) - { - return kStatus_Fail; - } - /* Set the PWM period */ - base->MOD = mod; - - /* Setup each TPM channel */ - for (i = 0; i < numOfChnls; i++) - { - /* Return error if requested dutycycle is greater than the max allowed */ - if (chnlParams->dutyCyclePercent > 100) - { - return kStatus_Fail; - } -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if (mode == kTPM_CombinedPwm) - { - uint16_t cnvFirstEdge; - - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlParams->chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) - { - return kStatus_Fail; - } - - /* Return error if requested value is greater than the max allowed */ - if (chnlParams->firstEdgeDelayPercent > 100) - { - return kStatus_Fail; - } - /* Configure delay of the first edge */ - if (chnlParams->firstEdgeDelayPercent == 0) - { - /* No delay for the first edge */ - cnvFirstEdge = 0; - } - else - { - cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; - } - /* Configure dutycycle */ - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - cnvFirstEdge = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - /* Set the combine bit for the channel pair */ - base->COMBINE |= (1U << (TPM_COMBINE_COMBINE0_SHIFT + (TPM_COMBINE_SHIFT * chnlParams->chnlNumber))); - - /* When switching mode, disable channel n first */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode for channel n, PWM output requires mode select to be set to 2 */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set the channel pair values */ - base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; - - /* When switching mode, disable channel n + 1 first */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode for channel n + 1, PWM output requires mode select to be set to 2 */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set the channel pair values */ - base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - } - else - { -#endif - if (chnlParams->dutyCyclePercent == 0) - { - /* Signal stays low */ - cnv = 0; - } - else - { - cnv = (mod * chnlParams->dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - } - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlParams->chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlParams->chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested PWM mode, PWM output requires mode select to be set to 2 */ - base->CONTROLS[chnlParams->chnlNumber].CnSC |= - ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlParams->chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - } -#endif - - chnlParams++; - } - - return kStatus_Success; -} - -void TPM_UpdatePwmDutycycle(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if(currentPwmMode == kTPM_CombinedPwm) - { - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - } -#endif - - uint16_t cnv, mod; - - mod = base->MOD; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - if (currentPwmMode == kTPM_CombinedPwm) - { - uint16_t cnvFirstEdge; - - /* This check is added for combined mode as the channel number should be the pair number */ - if (chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) - { - return; - } - cnv = (mod * dutyCyclePercent) / 100; - cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; - } - else - { -#endif - cnv = (mod * dutyCyclePercent) / 100; - /* For 100% duty cycle */ - if (cnv >= mod) - { - cnv = mod + 1; - } - base->CONTROLS[chnlNumber].CnV = cnv; -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - } -#endif -} - -void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - - uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK); - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Clear the field and write the new level value */ - reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - base->CONTROLS[chnlNumber].CnSC = reg; - - /* Wait till mode change is acknowledged */ - reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - while (reg != (base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1*/ - if ((chnlNumber == 0) || (chnlNumber == 1)) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - /* The TPM's COMBINE register required to be effective */ - if( FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base) ) - { - /* Clear the combine bit for chnlNumber */ - base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2)); - } -#endif - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Set the requested input capture mode */ - base->CONTROLS[chnlNumber].CnSC |= captureMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -void TPM_SetupOutputCompare(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_output_compare_mode_t compareMode, - uint32_t compareValue) -{ - assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1 */ - if ((chnlNumber == 0) || (chnlNumber == 1)) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - - /* When switching mode, disable channel first */ - base->CONTROLS[chnlNumber].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Setup the channel output behaviour when a match occurs with the compare value */ - base->CONTROLS[chnlNumber].CnSC |= compareMode; - - /* Setup the compare value */ - base->CONTROLS[chnlNumber].CnV = compareValue; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlNumber].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -void TPM_SetupDualEdgeCapture(TPM_Type *base, - tpm_chnl_t chnlPairNumber, - const tpm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue) -{ - assert(edgeParam); - assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2); - assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); - - uint32_t reg; - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL - /* The TPM's QDCTRL register required to be effective */ - if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) - { - /* Clear quadrature Decoder mode for channel 0 or 1*/ - if (chnlPairNumber == 0) - { - base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; - } - } -#endif - - /* Unlock: When switching mode, disable channel first */ - base->CONTROLS[chnlPairNumber * 2].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlPairNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &= - ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Now, the registers for input mode can be operated. */ - if (edgeParam->enableSwap) - { - /* Set the combine and swap bits for the channel pair */ - base->COMBINE |= (TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK) - << (TPM_COMBINE_SHIFT * chnlPairNumber); - - /* Input filter setup for channel n+1 input */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); - reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); - base->FILTER = reg; - } - else - { - reg = base->COMBINE; - /* Clear the swap bit for the channel pair */ - reg &= ~(TPM_COMBINE_COMSWAP0_MASK << (TPM_COMBINE_COMSWAP0_SHIFT * chnlPairNumber)); - - /* Set the combine bit for the channel pair */ - reg |= TPM_COMBINE_COMBINE0_MASK << (TPM_COMBINE_SHIFT * chnlPairNumber); - base->COMBINE = reg; - - /* Input filter setup for channel n input */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); - base->FILTER = reg; - } - - /* Setup the edge detection from channel n */ - base->CONTROLS[chnlPairNumber * 2].CnSC |= edgeParam->currChanEdgeMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[chnlPairNumber * 2].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - - /* Setup the edge detection from channel n+1 */ - base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC |= edgeParam->nextChanEdgeMode; - - /* Wait till mode change is acknowledged */ - while (!(base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC & - (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } -} -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -void TPM_SetupQuadDecode(TPM_Type *base, - const tpm_phase_params_t *phaseAParams, - const tpm_phase_params_t *phaseBParams, - tpm_quad_decode_mode_t quadMode) -{ - assert(phaseAParams); - assert(phaseBParams); - assert(FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)); - - base->CONTROLS[0].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[0].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - uint32_t reg; - - /* Set Phase A filter value */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH0FVAL_MASK); - reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); - base->FILTER = reg; - -#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL - /* Set Phase A polarity */ - if (phaseAParams->phasePolarity) - { - base->POL |= TPM_POL_POL0_MASK; - } - else - { - base->POL &= ~TPM_POL_POL0_MASK; - } -#endif - - base->CONTROLS[1].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); - - /* Wait till mode change to disable channel is acknowledged */ - while ((base->CONTROLS[1].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) - { - } - /* Set Phase B filter value */ - reg = base->FILTER; - reg &= ~(TPM_FILTER_CH1FVAL_MASK); - reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); - base->FILTER = reg; -#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL - /* Set Phase B polarity */ - if (phaseBParams->phasePolarity) - { - base->POL |= TPM_POL_POL1_MASK; - } - else - { - base->POL &= ~TPM_POL_POL1_MASK; - } -#endif - - /* Set Quadrature mode */ - reg = base->QDCTRL; - reg &= ~(TPM_QDCTRL_QUADMODE_MASK); - reg |= TPM_QDCTRL_QUADMODE(quadMode); - base->QDCTRL = reg; - - /* Enable Quad decode */ - base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; -} - -#endif - -void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask) -{ - uint32_t chnlInterrupts = (mask & 0xFF); - uint8_t chnlNumber = 0; - - /* Enable the timer overflow interrupt */ - if (mask & kTPM_TimeOverflowInterruptEnable) - { - base->SC |= TPM_SC_TOIE_MASK; - } - - /* Enable the channel interrupts */ - while (chnlInterrupts) - { - if (chnlInterrupts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInterrupts = chnlInterrupts >> 1U; - } -} - -void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask) -{ - uint32_t chnlInterrupts = (mask & 0xFF); - uint8_t chnlNumber = 0; - - /* Disable the timer overflow interrupt */ - if (mask & kTPM_TimeOverflowInterruptEnable) - { - base->SC &= ~TPM_SC_TOIE_MASK; - } - - /* Disable the channel interrupts */ - while (chnlInterrupts) - { - if (chnlInterrupts & 0x1) - { - base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK; - } - chnlNumber++; - chnlInterrupts = chnlInterrupts >> 1U; - } -} - -uint32_t TPM_GetEnabledInterrupts(TPM_Type *base) -{ - uint32_t enabledInterrupts = 0; - int8_t chnlCount = FSL_FEATURE_TPM_CHANNEL_COUNTn(base); - - /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */ - assert(chnlCount != -1); - - /* Check if timer overflow interrupt is enabled */ - if (base->SC & TPM_SC_TOIE_MASK) - { - enabledInterrupts |= kTPM_TimeOverflowInterruptEnable; - } - - /* Check if the channel interrupts are enabled */ - while (chnlCount > 0) - { - chnlCount--; - if (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK) - { - enabledInterrupts |= (1U << chnlCount); - } - } - - return enabledInterrupts; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.h deleted file mode 100644 index c18d5757fda53955694996dec98466cfe18e1db4..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tpm.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_TPM_H_ -#define _FSL_TPM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup tpm - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ -/*@}*/ - -/*! - * @brief List of TPM channels. - * @note Actual number of available channels is SoC dependent - */ -typedef enum _tpm_chnl -{ - kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/ - kTPM_Chnl_1, /*!< TPM channel number 1 */ - kTPM_Chnl_2, /*!< TPM channel number 2 */ - kTPM_Chnl_3, /*!< TPM channel number 3 */ - kTPM_Chnl_4, /*!< TPM channel number 4 */ - kTPM_Chnl_5, /*!< TPM channel number 5 */ - kTPM_Chnl_6, /*!< TPM channel number 6 */ - kTPM_Chnl_7 /*!< TPM channel number 7 */ -} tpm_chnl_t; - -/*! @brief TPM PWM operation modes */ -typedef enum _tpm_pwm_mode -{ - kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */ - kTPM_CenterAlignedPwm, /*!< Center aligned PWM */ -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - kTPM_CombinedPwm /*!< Combined PWM */ -#endif -} tpm_pwm_mode_t; - -/*! @brief TPM PWM output pulse mode: high-true, low-true or no output */ -typedef enum _tpm_pwm_level_select -{ - kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */ - kTPM_LowTrue, /*!< Low true pulses */ - kTPM_HighTrue /*!< High true pulses */ -} tpm_pwm_level_select_t; - -/*! @brief Options to configure a TPM channel's PWM signal */ -typedef struct _tpm_chnl_pwm_signal_param -{ - tpm_chnl_t chnlNumber; /*!< TPM channel to configure. - In combined mode (available in some SoC's, this represents the - channel pair number */ - tpm_pwm_level_select_t level; /*!< PWM output active level select */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0=inactive signal(0% duty cycle)... - 100=always active signal (100% duty cycle)*/ -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE - uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. - Specifies the delay to the first edge in a PWM period. - If unsure, leave as 0; Should be specified as - percentage of the PWM period */ -#endif -} tpm_chnl_pwm_signal_param_t; - -/*! - * @brief Trigger options available. - * - * This is used for both internal & external trigger sources (external option available in certain SoC's) - * - * @note The actual trigger options available is SoC-specific. - */ -typedef enum _tpm_trigger_select -{ - kTPM_Trigger_Select_0 = 0U, - kTPM_Trigger_Select_1, - kTPM_Trigger_Select_2, - kTPM_Trigger_Select_3, - kTPM_Trigger_Select_4, - kTPM_Trigger_Select_5, - kTPM_Trigger_Select_6, - kTPM_Trigger_Select_7, - kTPM_Trigger_Select_8, - kTPM_Trigger_Select_9, - kTPM_Trigger_Select_10, - kTPM_Trigger_Select_11, - kTPM_Trigger_Select_12, - kTPM_Trigger_Select_13, - kTPM_Trigger_Select_14, - kTPM_Trigger_Select_15 -} tpm_trigger_select_t; - -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION -/*! - * @brief Trigger source options available - * - * @note This selection is available only on some SoC's. For SoC's without this selection, the only - * trigger source available is internal triger. - */ -typedef enum _tpm_trigger_source -{ - kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */ - kTPM_TriggerSource_Internal /*!< Use internal trigger */ -} tpm_trigger_source_t; -#endif - -/*! @brief TPM output compare modes */ -typedef enum _tpm_output_compare_mode -{ - kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ - kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ - kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */ - kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */ - kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */ - kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */ -} tpm_output_compare_mode_t; - -/*! @brief TPM input capture edge */ -typedef enum _tpm_input_capture_edge -{ - kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */ - kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */ - kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ -} tpm_input_capture_edge_t; - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -/*! - * @brief TPM dual edge capture parameters - * - * @note This mode is available only on some SoC's. - */ -typedef struct _tpm_dual_edge_capture_param -{ - bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored; - false: Use channel n input, channel n+1 input is ignored */ - tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ - tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ -} tpm_dual_edge_capture_param_t; -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -/*! - * @brief TPM quadrature decode modes - * - * @note This mode is available only on some SoC's. - */ -typedef enum _tpm_quad_decode_mode -{ - kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ - kTPM_QuadCountAndDir /*!< Count and direction encoding mode */ -} tpm_quad_decode_mode_t; - -/*! @brief TPM quadrature phase polarities */ -typedef enum _tpm_phase_polarity -{ - kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ - kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */ -} tpm_phase_polarity_t; - -/*! @brief TPM quadrature decode phase parameters */ -typedef struct _tpm_phase_param -{ - uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */ - tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */ -} tpm_phase_params_t; -#endif - -/*! @brief TPM clock source selection*/ -typedef enum _tpm_clock_source -{ - kTPM_SystemClock = 1U, /*!< System clock */ - kTPM_ExternalClock /*!< External clock */ -} tpm_clock_source_t; - -/*! @brief TPM prescale value selection for the clock source*/ -typedef enum _tpm_clock_prescale -{ - kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ - kTPM_Prescale_Divide_2, /*!< Divide by 2 */ - kTPM_Prescale_Divide_4, /*!< Divide by 4 */ - kTPM_Prescale_Divide_8, /*!< Divide by 8 */ - kTPM_Prescale_Divide_16, /*!< Divide by 16 */ - kTPM_Prescale_Divide_32, /*!< Divide by 32 */ - kTPM_Prescale_Divide_64, /*!< Divide by 64 */ - kTPM_Prescale_Divide_128 /*!< Divide by 128 */ -} tpm_clock_prescale_t; - -/*! - * @brief TPM config structure - * - * This structure holds the configuration settings for the TPM peripheral. To initialize this - * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _tpm_config -{ - tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */ - bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled; - false: disabled */ - tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */ -#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ -#endif - bool enableDoze; /*!< true: TPM counter is paused in doze mode; - false: TPM counter continues in doze mode */ - bool enableDebugMode; /*!< true: TPM counter continues in debug mode; - false: TPM counter is paused in debug mode */ - bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger; - false: TPM counter not reloaded */ - bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow; - false: TPM counter continues running after overflow */ - bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected; - false: TPM counter starts immediately */ -#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted; - false: TPM counter continues running */ -#endif -} tpm_config_t; - -/*! @brief List of TPM interrupts */ -typedef enum _tpm_interrupt_enable -{ - kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/ - kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/ - kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/ - kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/ - kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/ - kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/ - kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/ - kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/ - kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/ -} tpm_interrupt_enable_t; - -/*! @brief List of TPM flags */ -typedef enum _tpm_status_flags -{ - kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */ - kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */ - kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */ - kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */ - kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */ - kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */ - kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */ - kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */ - kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */ -} tpm_status_flags_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the TPM clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the TPM driver. - * - * @param base TPM peripheral base address - * @param config Pointer to user's TPM config structure. - */ -void TPM_Init(TPM_Type *base, const tpm_config_t *config); - -/*! - * @brief Stops the counter and gates the TPM clock - * - * @param base TPM peripheral base address - */ -void TPM_Deinit(TPM_Type *base); - -/*! - * @brief Fill in the TPM config struct with the default settings - * - * The default values are: - * @code - * config->prescale = kTPM_Prescale_Divide_1; - * config->useGlobalTimeBase = false; - * config->dozeEnable = false; - * config->dbgMode = false; - * config->enableReloadOnTrigger = false; - * config->enableStopOnOverflow = false; - * config->enableStartOnTrigger = false; - *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER - * config->enablePauseOnTrigger = false; - *#endif - * config->triggerSelect = kTPM_Trigger_Select_0; - *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION - * config->triggerSource = kTPM_TriggerSource_External; - *#endif - * @endcode - * @param config Pointer to user's TPM config structure. - */ -void TPM_GetDefaultConfig(tpm_config_t *config); - -/*! @}*/ - -/*! - * @name Channel mode operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters - * - * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this - * function to configure all the TPM channels that will be used to output a PWM signal - * - * @param base TPM peripheral base address - * @param chnlParams Array of PWM channel parameters to configure the channel(s) - * @param numOfChnls Number of channels to configure, this should be the size of the array passed in - * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz TPM counter clock in Hz - * - * @return kStatus_Success if the PWM setup was successful, - * kStatus_Error on failure - */ -status_t TPM_SetupPwm(TPM_Type *base, - const tpm_chnl_pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - tpm_pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz); - -/*! - * @brief Update the duty cycle of an active PWM signal - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number. In combined mode, this represents - * the channel pair number - * @param currentPwmMode The current PWM mode set during PWM setup - * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void TPM_UpdatePwmDutycycle(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_pwm_mode_t currentPwmMode, - uint8_t dutyCyclePercent); - -/*! - * @brief Update the edge level selection for a channel - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. - * See the appropriate SoC reference manual for details about this field. - */ -void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level); - -/*! - * @brief Enables capturing an input signal on the channel using the function parameters. - * - * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into - * the CnV register. The user has to read the CnV register separately to get this value. - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param captureMode Specifies which edge to capture - */ -void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode); - -/*! - * @brief Configures the TPM to generate timed pulses. - * - * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel - * output is changed based on what is specified in the compareMode argument. - * - * @param base TPM peripheral base address - * @param chnlNumber The channel number - * @param compareMode Action to take on the channel output when the compare condition is met - * @param compareValue Value to be programmed in the CnV register. - */ -void TPM_SetupOutputCompare(TPM_Type *base, - tpm_chnl_t chnlNumber, - tpm_output_compare_mode_t compareMode, - uint32_t compareValue); - -#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE -/*! - * @brief Configures the dual edge capture mode of the TPM. - * - * This function allows to measure a pulse width of the signal on the input of channel of a - * channel pair. The filter function is disabled if the filterVal argument passed is zero. - * - * @param base TPM peripheral base address - * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3 - * @param edgeParam Sets up the dual edge capture function - * @param filterValue Filter value, specify 0 to disable filter. - */ -void TPM_SetupDualEdgeCapture(TPM_Type *base, - tpm_chnl_t chnlPairNumber, - const tpm_dual_edge_capture_param_t *edgeParam, - uint32_t filterValue); -#endif - -#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL -/*! - * @brief Configures the parameters and activates the quadrature decode mode. - * - * @param base TPM peripheral base address - * @param phaseAParams Phase A configuration parameters - * @param phaseBParams Phase B configuration parameters - * @param quadMode Selects encoding mode used in quadrature decoder mode - */ -void TPM_SetupQuadDecode(TPM_Type *base, - const tpm_phase_params_t *phaseAParams, - const tpm_phase_params_t *phaseBParams, - tpm_quad_decode_mode_t quadMode); -#endif - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected TPM interrupts. - * - * @param base TPM peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask); - -/*! - * @brief Disables the selected TPM interrupts. - * - * @param base TPM peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask); - -/*! - * @brief Gets the enabled TPM interrupts. - * - * @param base TPM peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::tpm_interrupt_enable_t - */ -uint32_t TPM_GetEnabledInterrupts(TPM_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the TPM status flags - * - * @param base TPM peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::tpm_status_flags_t - */ -static inline uint32_t TPM_GetStatusFlags(TPM_Type *base) -{ - return base->STATUS; -} - -/*! - * @brief Clears the TPM status flags - * - * @param base TPM peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::tpm_status_flags_t - */ -static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask) -{ - /* Clear the status flags */ - base->STATUS = mask; -} - -/*! @}*/ - -/*! - * @name Read and write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of ticks. - * - * Timers counts from 0 until it equals the count value set here. The count value is written to - * the MOD register. - * - * @note - * 1. This API allows the user to use the TPM module as a timer. Do not mix usage - * of this API with TPM's PWM setup API's. - * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks. - * - * @param base TPM peripheral base address - * @param ticks A timer period in units of ticks, which should be equal or greater than 1. - */ -static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) -{ - base->MOD = ticks; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value in a range from 0 to a - * timer period. - * - * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. - * - * @param base TPM peripheral base address - * - * @return The current counter value in ticks - */ -static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base) -{ - return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT); -} - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the TPM counter. - * - * - * @param base TPM peripheral base address - * @param clockSource TPM clock source; once clock source is set the counter will start running - */ -static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource) -{ - uint32_t reg = base->SC; - - reg &= ~(TPM_SC_CMOD_MASK); - reg |= TPM_SC_CMOD(clockSource); - base->SC = reg; -} - -/*! - * @brief Stops the TPM counter. - * - * @param base TPM peripheral base address - */ -static inline void TPM_StopTimer(TPM_Type *base) -{ - /* Set clock source to none to disable counter */ - base->SC &= ~(TPM_SC_CMOD_MASK); - - /* Wait till this reads as zero acknowledging the counter is disabled */ - while (base->SC & TPM_SC_CMOD_MASK) - { - } -} - -/*! @}*/ - -#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL -/*! - * @brief Performs a software reset on the TPM module. - * - * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.. - * - * @note TPM software reset is available on certain SoC's only - * - * @param base TPM peripheral base address - */ -static inline void TPM_Reset(TPM_Type *base) -{ - base->GLOBAL |= TPM_GLOBAL_RST_MASK; - base->GLOBAL &= ~TPM_GLOBAL_RST_MASK; -} -#endif - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_TPM_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.c deleted file mode 100644 index cecc699d5cc2403276bfbbebf64693c32a6dc068..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.c +++ /dev/null @@ -1,1628 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_trng.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/******************************************************************************* - * Definitions - *******************************************************************************/ -/* Default values for user configuration structure.*/ -#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ - defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 -#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ - defined(KL82Z7_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 -#elif defined(K81F25615_SERIES) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 -#else -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 -#endif - -#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 -#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 -#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500 -#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 -#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 -#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 - -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384 -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 -#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 0x3fffff -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 - -/*! @brief TRNG work mode */ -typedef enum _trng_work_mode -{ - kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ - kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ -} trng_work_mode_t; - -/*! @brief TRNG statistical check type*/ -typedef enum _trng_statistical_check -{ - kTRNG_StatisticalCheckMonobit = - 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ - kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during - entropy generation. */ - kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ - kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ -} trng_statistical_check_t; - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ -/*! - * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) - * - * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, - * the RTY_CT value indicates the number of times a retry should occur before - * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This - * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing - * the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ -#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) - -/*! @brief Set the RTY_CT field to a new value. */ -#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCML - RNG Statistical Check Monobit Limit Register - ******************************************************************************/ -/*! - * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) - * - * Reset value: 0x010C0568U - * - * The RNG Statistical Check Monobit Limit Register defines the allowable - * maximum and minimum number of ones/zero detected during entropy generation. To pass - * the test, the number of ones/zeroes generated must be less than the programmed - * maximum value, and the number of ones/zeroes generated must be greater than - * (maximum - range). If this test fails, the Retry Counter in SCMISC will be - * decremented, and a retry will occur if the Retry Count has not reached zero. If - * the Retry Count has reached zero, an error will be generated. Note that this - * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, - * this offset is used as SCMC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCML register - */ -/*@{*/ -#define TRNG_SCML_REG(base) ((base)->SCML) -#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) -#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) -#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) - * - * Monobit Maximum Limit. Defines the maximum allowable count taken during - * entropy generation. The number of ones/zeroes detected during entropy generation - * must be less than MONO_MAX, else a retry or error will occur. This register is - * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ -#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) - -/*! @brief Set the MONO_MAX field to a new value. */ -#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) - * - * Monobit Range. The number of ones/zeroes detected during entropy generation - * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. - * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ -#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) - -/*! @brief Set the MONO_RNG field to a new value. */ -#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) - * - * Reset value: 0x00B20195U - * - * The RNG Statistical Check Run Length 1 Limit Register defines the allowable - * maximum and minimum number of runs of length 1 detected during entropy - * generation. To pass the test, the number of runs of length 1 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 1 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR1L register - */ -/*@{*/ -#define TRNG_SCR1L_REG(base) ((base)->SCR1L) -#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) -#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) -#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) - * - * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 1 detected during entropy generation must be less than RUN1_MAX, else a - * retry or error will occur. This register is cleared to 01E5h (decimal 485) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ -#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) - -/*! @brief Set the RUN1_MAX field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) - * - * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) - * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a - * retry or error will occur. This register is cleared to 0102h (decimal 258) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ -#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) - -/*! @brief Set the RUN1_RNG field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) - * - * Reset value: 0x007A00DCU - * - * The RNG Statistical Check Run Length 2 Limit Register defines the allowable - * maximum and minimum number of runs of length 2 detected during entropy - * generation. To pass the test, the number of runs of length 2 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 2 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR2L register - */ -/*@{*/ -#define TRNG_SCR2L_REG(base) ((base)->SCR2L) -#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) -#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) -#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR2L bitfields - */ - -/*! - * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) - * - * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 2 detected during entropy generation must be less than RUN2_MAX, else a - * retry or error will occur. This register is cleared to 00DCh (decimal 220) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ -#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) - -/*! @brief Set the RUN2_MAX field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) - * - * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) - * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a - * retry or error will occur. This register is cleared to 007Ah (decimal 122) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ -#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) - -/*! @brief Set the RUN2_RNG field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) - * - * Reset value: 0x0058007DU - * - * The RNG Statistical Check Run Length 3 Limit Register defines the allowable - * maximum and minimum number of runs of length 3 detected during entropy - * generation. To pass the test, the number of runs of length 3 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 3 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR3L register - */ -/*@{*/ -#define TRNG_SCR3L_REG(base) ((base)->SCR3L) -#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) -#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) -#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR3L bitfields - */ - -/*! - * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) - * - * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 3 detected during entropy generation must be less than RUN3_MAX, else a - * retry or error will occur. This register is cleared to 007Dh (decimal 125) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ -#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) - -/*! @brief Set the RUN3_MAX field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) - * - * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) - * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a - * retry or error will occur. This register is cleared to 0058h (decimal 88) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ -#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) - -/*! @brief Set the RUN3_RNG field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) - * - * Reset value: 0x0040004BU - * - * The RNG Statistical Check Run Length 4 Limit Register defines the allowable - * maximum and minimum number of runs of length 4 detected during entropy - * generation. To pass the test, the number of runs of length 4 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 4 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR4L register - */ -/*@{*/ -#define TRNG_SCR4L_REG(base) ((base)->SCR4L) -#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) -#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) -#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR4L bitfields - */ - -/*! - * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) - * - * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 4 detected during entropy generation must be less than RUN4_MAX, else a - * retry or error will occur. This register is cleared to 004Bh (decimal 75) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ -#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) - -/*! @brief Set the RUN4_MAX field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) - * - * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) - * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a - * retry or error will occur. This register is cleared to 0040h (decimal 64) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ -#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) - -/*! @brief Set the RUN4_RNG field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 5 Limit Register defines the allowable - * maximum and minimum number of runs of length 5 detected during entropy - * generation. To pass the test, the number of runs of length 5 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 5 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR5L register - */ -/*@{*/ -#define TRNG_SCR5L_REG(base) ((base)->SCR5L) -#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) -#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) -#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR5L bitfields - */ - -/*! - * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) - * - * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 5 detected during entropy generation must be less than RUN5_MAX, else a - * retry or error will occur. This register is cleared to 002Fh (decimal 47) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ -#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) - -/*! @brief Set the RUN5_MAX field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) - * - * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) - * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a - * retry or error will occur. This register is cleared to 002Eh (decimal 46) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ -#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) - -/*! @brief Set the RUN5_RNG field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable - * maximum and minimum number of runs of length 6 or more detected during entropy - * generation. To pass the test, the number of runs of length 6 or more (for - * samples of both 0 and 1) must be less than the programmed maximum value, and the - * number of runs of length 6 or more must be greater than (maximum - range). If - * this test fails, the Retry Counter in SCMISC will be decremented, and a retry - * will occur if the Retry Count has not reached zero. If the Retry Count has - * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is - * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is - * used as SCR6PC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR6PL register - */ -/*@{*/ -#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) -#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) -#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) -#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR6PL bitfields - */ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) - * - * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 - * or more (for both 0 and 1) detected during entropy generation. The number of - * runs of length 6 or more detected during entropy generation must be less than - * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh - * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ -#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) - -/*! @brief Set the RUN6P_MAX field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) - * - * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and - * 1) detected during entropy generation must be greater than RUN6P_MAX - - * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh - * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ -#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) - -/*! @brief Set the RUN6P_RNG field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRMAX - RNG Poker Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) - * - * Reset value: 0x00006920U - * - * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during - * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is - * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used - * as the PKRSQ readback register. - */ -/*! - * @name Constants and macros for entire TRNG_PKRMAX register - */ -/*@{*/ -#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) -#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) -#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) -#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRMAX bitfields - */ - -/*! - * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) - * - * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is - * run which requires a maximum and minimum limit. The maximum allowable result is - * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if - * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by - * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers - * combined are used to define the minimum allowable Poker result, which is PKR_MAX - - * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used - * to read the Poker Test Square Calculation result in register PKRSQ, as defined - * in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ -#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) - -/*! @brief Set the PKR_MAX field to a new value. */ -#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ - (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRRNG - RNG Poker Range Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) - * - * Reset value: 0x000009A3U - * - * The RNG Poker Range Register defines the difference between the TRNG Poker - * Maximum Limit and the minimum limit. These limits are used during the TRNG - * Statistical Check Poker Test. - */ -/*! - * @name Constants and macros for entire TRNG_PKRRNG register - */ -/*@{*/ -#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) -#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) -#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) -#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRRNG bitfields - */ - -/*! - * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) - * - * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which - * requires a maximum and minimum limit. The maximum is programmed in the - * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG - * value from the programmed maximum value. This field is writable only if - * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is - * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that - * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ -#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) - -/*! @brief Set the PKR_RNG field to a new value. */ -#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ - (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) - * - * Reset value: 0x00006400U - * - * The RNG Frequency Count Maximum Limit Register defines the maximum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is greater than this programmed maximum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note - * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMAX register - */ -/*@{*/ -#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) -#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) -#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) -#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMAX bitfields - */ - -/*! - * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) - * - * Frequency Counter Maximum Limit. Defines the maximum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. - * Note that if MCTL[PRGM] bit is 0, this register address is used to read the - * Frequency Count result in register FRQCNT, as defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ -#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) - -/*! @brief Set the FRQ_MAX field to a new value. */ -#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ - (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) - * - * Reset value: 0x00000640U - * - * The RNG Frequency Count Minimum Limit Register defines the minimum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is less than this programmed minimum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMIN register - */ -/*@{*/ -#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) -#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) -#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) -#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMIN bitfields - */ - -/*! - * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) - * - * Frequency Count Minimum Limit. Defines the minimum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 - * by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ -#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) - -/*! @brief Set the FRQ_MIN field to a new value. */ -#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ - (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_MCTL - RNG Miscellaneous Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) - * - * Reset value: 0x00012001U - * - * This register is intended to be used for programming, configuring and testing - * the RNG. It is the main register to read/write, in order to enable Entropy - * generation, to stop entropy generation and to block access to entropy registers. - * This is done via the special TRNG_ACC and PRGM bits below. The RNG - * Miscellaneous Control Register is a read/write register used to control the RNG's True - * Random Number Generator (TRNG) access, operation and test. Note that in many - * cases two RNG registers share the same address, and a particular register at the - * shared address is selected based upon the value in the PRGM field of the MCTL - * register. - */ -/*! - * @name Constants and macros for entire TRNG_MCTL register - */ -/*@{*/ -#define TRNG_MCTL_REG(base) ((base)->MCTL) -#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) -#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) -#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) - * - * Force System Clock. If set, the system clock is used to operate the TRNG, - * instead of the ring oscillator. This is for test use only, and indeterminate - * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is - * being written to 1 simultaneously to writing this bit. This bit is cleared by - * writing the RST_DEF bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ -#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) - -/*! @brief Set the FOR_SCLK field to a new value. */ -#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) - * - * Oscillator Divide. Determines the amount of dividing done to the ring - * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is - * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This - * field is cleared to 00 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use ring oscillator with no divide - * - 0b01 - use ring oscillator divided-by-2 - * - 0b10 - use ring oscillator divided-by-4 - * - 0b11 - use ring oscillator divided-by-8 - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ -#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) - -/*! @brief Set the OSC_DIV field to a new value. */ -#define TRNG_WR_MCTL_OSC_DIV(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) - * - * Sample Mode. Determines the method of sampling the ring oscillator while - * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM - * bit is being written to 1 simultaneously with writing this field. This field - * is cleared to 01 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical - * Checker - * - 0b01 - use raw data into both Entropy shifter and Statistical Checker - * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into - * Statistical Checker - * - 0b11 - reserved. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ -#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) - -/*! @brief Set the SAMP_MODE field to a new value. */ -#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field PRGM[16] (RW) - * - * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, - * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is - * in Program Mode. Note that different RNG registers are accessible at the same - * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG - * register descriptions. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ -#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) - -/*! @brief Set the PRGM field to a new value. */ -#define TRNG_WR_MCTL_PRGM(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field RST_DEF[6] (WO) - * - * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and - * bits within registers, to their default state. This bit is writable only if PRGM - * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this - * bit. Reading this bit always produces a 0. - */ -/*@{*/ -/*! @brief Set the RST_DEF field to a new value. */ -#define TRNG_WR_MCTL_RST_DEF(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) - * - * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy - * value that can be read via the ENT0-ENT15 registers. The Entropy value may be - * read once the ENT VAL bit is asserted. Also see ENTa register descriptions - * (For a = 0 to 15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ -#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) - -/*! @brief Set the TRNG_ACC field to a new value. */ -#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) - * - * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before - * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG - * free-running ring oscillator whenever new entropy is being generated and turns off the - * ring oscillator when entropy generation is complete. If the RNG clock is - * stopped while the TRNG ring oscillator is running, the oscillator will continue - * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG - * ring oscillator is not running. and therefore it is ok to stop the RNG clock. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ -#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) - * - * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then - * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 - * through ENT14 should be read before reading ENT15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ -#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ERR[12] (W1C) - * - * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear - * errors. Writing 0 has no effect. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ERR field. */ -#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) - -/*! @brief Set the ERR field to a new value. */ -#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SDCTL - RNG Seed Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_SDCTL - RNG Seed Control Register (RW) - * - * Reset value: 0x0C8009C4U - * - * The RNG Seed Control Register contains two fields. One field defines the - * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field - * indicates the number of samples that will taken during each TRNG Entropy - * generation (SAMP_SIZE). - */ -/*! - * @name Constants and macros for entire TRNG_SDCTL register - */ -/*@{*/ -#define TRNG_SDCTL_REG(base) ((base)->SDCTL) -#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) -#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) -#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SDCTL bitfields - */ - -/*! - * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) - * - * Sample Size. Defines the total number of Entropy samples that will be taken - * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h - * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ -#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) - -/*! @brief Set the SAMP_SIZE field to a new value. */ -#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ - (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) -/*@}*/ - -/*! - * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) - * - * Entropy Delay. Defines the length (in system clocks) of each Entropy sample - * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read - * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ -#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) - -/*! @brief Set the ENT_DLY field to a new value. */ -#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SBLIM - RNG Sparse Bit Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) - * - * Reset value: 0x0000003FU - * - * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is - * selected during Entropy Generation. It defines the maximum number of consecutive Von - * Neumann samples which may be discarded before an error is generated. Note - * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SBLIM register - */ -/*@{*/ -#define TRNG_SBLIM_REG(base) ((base)->SBLIM) -#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) -#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) -#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SBLIM bitfields - */ - -/*! - * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) - * - * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], - * samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. The Sparse Bit Limit defines the maximum number of - * consecutive samples that may be discarded before an error is generated. This field - * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by - * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this - * register address is used to read the Total Samples count in register TOTSAM, as - * defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ -#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) - -/*! @brief Set the SB_LIM field to a new value. */ -#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) - * - * Reset value: 0x0001001FU - * - * The RNG Statistical Check Miscellaneous Register contains the Long Run - * Maximum Limit value and the Retry Count value. This register is accessible only when - * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot - * be written. - */ -/*! - * @name Constants and macros for entire TRNG_SCMISC register - */ -/*@{*/ -#define TRNG_SCMISC_REG(base) ((base)->SCMISC) -#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) -#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) -#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCMISC bitfields - */ - -/*! - * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) - * - * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive - * samples of all 1, or all 0, that is allowed during the Entropy generation. - * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes - * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ -#define TRNG_RD_SCMISC_LRUN_MAX(base) \ - ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) - -/*! @brief Set the LRUN_MAX field to a new value. */ -#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ - (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_ENT - RNG TRNG Entropy Read Register - ******************************************************************************/ - -/*! - * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) - * - * Reset value: 0x00000000U - * - * The RNG TRNG can be programmed to generate an entropy value that is readable - * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the - * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this - * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. - * Note that once ENT15 is read, the entropy value will be cleared and a new - * value will begin generation, so it is important that ENT15 be read last. These - * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 - * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. - */ -/*! - * @name Constants and macros for entire TRNG_ENT register - */ -/*@{*/ -#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) -#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) -/*@}*/ - -/******************************************************************************* - * TRNG_SEC_CFG - RNG Security Configuration Register - ******************************************************************************/ - -/*! - * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The RNG Security Configuration Register is a read/write register used to - * control the test mode, programmability and state modes of the RNG. Many bits are - * place holders for this version. More configurability will be added here. Clears - * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 - * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use - * these registers, if hard coded. - */ -/*! - * @name Constants and macros for entire TRNG_SEC_CFG register - */ -/*@{*/ -#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) -#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) -#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) -#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) - * - * If set the TRNG registers cannot be programmed. That is, regardless of the - * TRNG access mode in the SA-TRNG Miscellaneous Control Register. - * - * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous - * Control Register's access mode bit. - * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents - * TRNG register programming. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ -#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ - ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) - -/*! @brief Set the NO_PRGM field to a new value. */ -#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ - (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) -/*@}*/ - -/*! @brief Array to map TRNG instance number to base pointer. */ -static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clock array name */ -static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit); -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); -static uint32_t trng_GetInstance(TRNG_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t trng_GetInstance(TRNG_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) - { - if (s_trngBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_trngBases)); - - return instance; -} - -/*FUNCTION********************************************************************* - * - * Function Name : TRNG_InitUserConfigDefault - * Description : Initializes user configuration structure to default settings. - * - *END*************************************************************************/ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) -{ - status_t result; - - if (userConfig != 0) - { - userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; - userConfig->clockMode = kTRNG_ClockModeRingOscillator; - userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; - userConfig->sampleMode = kTRNG_SampleModeRaw; - userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; - userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; - userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - - /* Statistical Check Parameters.*/ - userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; - userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; - - userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; - userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; - userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; - userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; - userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; - userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; - userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; - userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; - userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; - userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; - userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; - userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; - userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; - userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; - userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; - userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; - userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; - userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; - - result = kStatus_Success; - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -/*! - * @brief Sets the TRNG retry count. - * - * This function sets the retry counter which defines the number of times a - * statistical check may fails during the TRNG Entropy Generation before - * generating an error. -*/ -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) -{ - status_t status; - - if ((retry_count >= 1u) && (retry_count <= 15u)) - { - /* Set retry count.*/ - TRNG_WR_SCMISC_RTY_CT(base, retry_count); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical check limits. - * - * This function is used to set minimum and maximum limits of statistical checks. - * - */ -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit) -{ - uint32_t range; - status_t status = kStatus_Success; - - if (limit && (limit->maximum > limit->minimum)) - { - range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ - - switch (statistical_check) - { - case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during - entropy generation. */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) - { - TRNG_WR_SCML_MONO_MAX(base, limit->maximum); - TRNG_WR_SCML_MONO_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected - during entropy generation. */ - if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) - { - TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); - TRNG_WR_SCR1L_RUN1_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected - during entropy generation. */ - if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) - { - TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); - TRNG_WR_SCR2L_RUN2_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected - during entropy generation. */ - if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) - { - TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); - TRNG_WR_SCR3L_RUN3_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected - during entropy generation. */ - if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) - { - TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); - TRNG_WR_SCR4L_RUN4_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected - during entropy generation. */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); - TRNG_WR_SCR5L_RUN5_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected - during entropy generation */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); - TRNG_WR_SCR6PL_RUN6P_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during - entropy generation . */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) - { - TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); - TRNG_WR_PKRRNG_PKR_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency - count during entropy generation . */ - if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) - { - TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); - TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); - } - else - { - status = kStatus_InvalidArgument; - } - break; - default: - status = kStatus_InvalidArgument; - break; - } - } - - return status; -} - -/*FUNCTION********************************************************************* - * - * Function Name : trng_ApplyUserConfig - * Description : Apply user configuration settings to TRNG module. - * - *END*************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t status; - - if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, - &userConfig->runBit6PlusLimit)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, - &userConfig->frequencyCountLimit)) == kStatus_Success)) - { - TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); - TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); - TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); - TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); - TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); - TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); - TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); - } - - return status; -} - -/*! - * @brief Gets a entry data from the TRNG. - * - * This function gets an entropy data from TRNG. - * Entropy data is spread over TRNG_ENT_COUNT registers. - * Read register number is defined by index parameter. -*/ -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) -{ - uint32_t data; - - index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ - - data = TRNG_RD_ENT(base, index); - - if (index == (TRNG_ENT_COUNT - 1)) - { - /* Dummy read. Defect workaround. - * TRNG could not clear ENT_VAL flag automatically, application - * had to do a dummy reading operation for anyone TRNG register - * to clear it firstly, then to read the RTENT0 to RTENT15 again */ - index = TRNG_RD_ENT(base, 0); - } - - return data; -} - -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t result; - - /* Check input parameters.*/ - if ((base != 0) && (userConfig != 0)) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate. */ - CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the registers of TRNG module to reset state. */ - /* Must be in program mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - /* Reset Defaults.*/ - TRNG_WR_MCTL_RST_DEF(base, 1); - - /* Set configuration.*/ - if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) - { - /* Start entropy generation.*/ - /* Set to Run mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); - /* Enable TRNG Access Mode. To generate an Entropy - * value that can be read via the true0-true15 registers.*/ - TRNG_WR_MCTL_TRNG_ACC(base, 1); - - if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ - { - TRNG_WR_SEC_CFG_NO_PRGM(base, 1); - } - - result = kStatus_Success; - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -void TRNG_Deinit(TRNG_Type *base) -{ - /* Check input parameters.*/ - if (base) - { - /* Move to program mode. Stop entropy generation.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - - /* Check before clock stop. - TRNG turns on the TRNG free-running ring oscillator whenever new entropy - is being generated and turns off the ring oscillator when entropy generation - is complete. If the TRNG clock is stopped while the TRNG ring oscillator - is running, the oscillator continues running though the RNG clock. - is stopped. */ - while (TRNG_RD_MCTL_TSTOP_OK(base) == 0) - { - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable Clock*/ - CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -} - -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Success; - uint32_t random_32; - uint8_t *random_p; - uint32_t random_size; - uint8_t *data_p = (uint8_t *)data; - uint32_t i; - int index = 0; - - /* Check input parameters.*/ - if (base && data && dataSize) - { - do - { - /* Wait for Valid or Error flag*/ - while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0)) - { - } - - /* Check HW error.*/ - if (TRNG_RD_MCTL_ERR(base)) - { - result = kStatus_Fail; /* TRNG module error occurred */ - /* Clear error.*/ - TRNG_WR_MCTL_ERR(base, 1); - break; /* No sense stay here.*/ - } - - /* Read Entropy.*/ - random_32 = trng_ReadEntropy(base, index++); - - random_p = (uint8_t *)&random_32; - - if (dataSize < sizeof(random_32)) - { - random_size = dataSize; - } - else - { - random_size = sizeof(random_32); - } - - for (i = 0U; i < random_size; i++) - { - *data_p++ = *random_p++; - } - - dataSize -= random_size; - } while (dataSize > 0); - - /* Start a new entropy generation. - It is done by reading of the last entropy register.*/ - if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1)) - { - trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.h deleted file mode 100644 index 1edc7038f82a30ff07a5ef6a6da1b2febcd54331..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_trng.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_TRNG_DRIVER_H_ -#define _FSL_TRNG_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/*! - * @addtogroup trng - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief TRNG driver version 2.0.1. - * - * Current version: 2.0.1 - * - * Change log: - * - Version 2.0.1 - * - add support for KL8x and KL28Z - * - update default OSCDIV for K81 to divide by 2 - */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief TRNG sample mode. Used by trng_config_t. */ -typedef enum _trng_sample_mode -{ - kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeVonNeumannRaw = - 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ -} trng_sample_mode_t; - -/*! @brief TRNG clock mode. Used by trng_config_t. */ -typedef enum _trng_clock_mode -{ - kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ - kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and - indeterminate results may occur. */ -} trng_clock_mode_t; - -/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ -typedef enum _trng_ring_osc_div -{ - kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ - kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ - kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ - kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ -} trng_ring_osc_div_t; - -/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ -typedef struct _trng_statistical_check_limit -{ - uint32_t maximum; /*!< Maximum limit.*/ - uint32_t minimum; /*!< Minimum limit.*/ -} trng_statistical_check_limit_t; - -/*! - * @brief Data structure for the TRNG initialization - * - * This structure initializes the TRNG by calling the TRNG_Init() function. - * It contains all TRNG configurations. - */ -typedef struct _trng_user_config -{ - bool lock; /*!< @brief Disable programmability of TRNG registers. */ - trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ - trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ - trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ - /* Seed Control*/ - uint16_t - entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ - uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during - Entropy generation. */ - uint16_t - sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of - * consecutive samples that may be discarded before an error is generated. - * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). - * Samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. */ - /* Statistical Check Parameters.*/ - uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails - * during the TRNG Entropy Generation before generating an error. */ - uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, - * that is allowed during the Entropy generation. */ - trng_statistical_check_limit_t - monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected - during entropy generation. */ - trng_statistical_check_limit_t - runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5 - detected during entropy generation. */ - trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of - number of runs of length 6 or more detected during entropy - generation. */ - trng_statistical_check_limit_t - pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ - trng_statistical_check_limit_t - frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency - count. */ -} trng_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the user configuration structure to default values. - * - * This function initializes the configuration structure to default values. The default - * values are as follows. - * @code - * user_config->lock = 0; - * user_config->clockMode = kTRNG_ClockModeRingOscillator; - * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. - * user_config->sampleMode = kTRNG_SampleModeRaw; - * user_config->entropyDelay = 3200; - * user_config->sampleSize = 2500; - * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - * user_config->retryCount = 63; - * user_config->longRunMaxLimit = 34; - * user_config->monobitLimit.maximum = 1384; - * user_config->monobitLimit.minimum = 1116; - * user_config->runBit1Limit.maximum = 405; - * user_config->runBit1Limit.minimum = 227; - * user_config->runBit2Limit.maximum = 220; - * user_config->runBit2Limit.minimum = 98; - * user_config->runBit3Limit.maximum = 125; - * user_config->runBit3Limit.minimum = 37; - * user_config->runBit4Limit.maximum = 75; - * user_config->runBit4Limit.minimum = 11; - * user_config->runBit5Limit.maximum = 47; - * user_config->runBit5Limit.minimum = 1; - * user_config->runBit6PlusLimit.maximum = 47; - * user_config->runBit6PlusLimit.minimum = 1; - * user_config->pokerLimit.maximum = 26912; - * user_config->pokerLimit.minimum = 24445; - * user_config->frequencyCountLimit.maximum = 0x3fffff; - * user_config->frequencyCountLimit.minimum = 1600; - * @endcode - * - * @param user_config User configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); - -/*! - * @brief Initializes the TRNG. - * - * This function initializes the TRNG. - * When called, the TRNG entropy generation starts immediately. - * - * @param base TRNG base address - * @param userConfig Pointer to the initialization configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); - -/*! - * @brief Shuts down the TRNG. - * - * This function shuts down the TRNG. - * - * @param base TRNG base address. - */ -void TRNG_Deinit(TRNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the TRNG. - * - * @param base TRNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ -#endif /*_FSL_TRNG_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tstmr.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tstmr.h deleted file mode 100644 index d93b8a3ef2fef1e62b87ee69dd1ad6b6089c1c47..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_tstmr.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_TSTMR_H_ -#define _FSL_TSTMR_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup tstmr_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_TSTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ - /*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Reads the time stamp. - * - * This function reads the low and high registers and returns the 56-bit free running - * counter value. This can be read by software at any time to determine the software ticks. - * - * @param base TSTMR peripheral base address. - * - * @return The 56-bit time stamp value. - */ -static inline uint64_t TSTMR_ReadTimeStamp(TSTMR_Type* base) -{ - return *(volatile uint64_t*)(base); -} - -/*! - * @brief Delays for a specified number of microseconds. - * - * This function repeatedly reads the timestamp register and waits for the user-specified - * delay value. - * - * @param base TSTMR peripheral base address. - * @param delayInUs Delay value in microseconds. - */ -static inline void TSTMR_DelayUs(TSTMR_Type* base, uint32_t delayInUs) -{ - uint64_t startTime = TSTMR_ReadTimeStamp(base); -#if defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ - while (TSTMR_ReadTimeStamp(base) - startTime < delayInUs) -#elif defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ - while (TSTMR_ReadTimeStamp(base) - startTime < 8 * delayInUs) -#else - assert(0); -#endif - { - } -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_TSTMR_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.c deleted file mode 100644 index 905e7ce6a81895ba8660206fce9f1a1b6742cd7e..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.c +++ /dev/null @@ -1,1632 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usdhc.h" -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL -#include "fsl_cache.h" -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Clock setting */ -/* Max SD clock divisor from base clock */ -#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) -#define USDHC_PREV_DVS(x) ((x) -= 1U) -#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) - -/* Typedef for interrupt handler. */ -typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base USDHC peripheral base address. - * @return Instance number. - */ -static uint32_t USDHC_GetInstance(USDHC_Type *base); - -/*! - * @brief Set transfer interrupt. - * - * @param base USDHC peripheral base address. - * @param usingInterruptSignal True to use IRQ signal. - */ -static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); - -/*! - * @brief Start transfer according to current transfer state - * - * @param base USDHC peripheral base address. - * @param command Command to be sent. - * @param data Data to be transferred. - */ -static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data); - -/*! - * @brief Receive command response - * - * @param base USDHC peripheral base address. - * @param command Command to be sent. - */ -static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); - -/*! - * @brief Read DATAPORT when buffer enable bit is set. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @param transferredWords The number of data words have been transferred last time transaction. - * @return The number of total data words have been transferred after this time transaction. - */ -static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); - -/*! - * @brief Read data by using DATAPORT polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @retval kStatus_Fail Read DATAPORT failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); - -/*! - * @brief Write DATAPORT when buffer enable bit is set. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @param transferredWords The number of data words have been transferred last time. - * @return The number of total data words have been transferred after this time transaction. - */ -static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); - -/*! - * @brief Write data by using DATAPORT polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be transferred. - * @retval kStatus_Fail Write DATAPORT failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); - -/*! - * @brief Transfer data by polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be transferred. - * @param use DMA flag. - * @retval kStatus_Fail Transfer data failed. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); - -/*! - * @brief Handle card detect interrupt. - * - * @param handle USDHC handle. - * @param interruptFlags Card detect related interrupt flags. - */ -static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle command interrupt. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param interruptFlags Command related interrupt flags. - */ -static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle data interrupt. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param interruptFlags Data related interrupt flags. - */ -static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle SDIO card interrupt signal. - * - * @param handle USDHC handle. - */ -static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle); - -/*! - * @brief Handle SDIO block gap event. - * - * @param handle USDHC handle. - */ -static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle); - -/*! -* @brief Handle retuning -* -* @param interrupt flags -*/ -static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! -* @brief wait command done -* -* @param base USDHC peripheral base address. -* @param command configuration -* @param execute tuning flag -*/ -static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief USDHC base pointer array */ -static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; - -/*! @brief USDHC internal handle pointer array */ -static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; - -/*! @brief USDHC IRQ name array */ -static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief USDHC clock array name */ -static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* USDHC ISR for transactional APIs. */ -static usdhc_isr_t s_usdhcIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t USDHC_GetInstance(USDHC_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_usdhcBase)); - - return instance; -} - -static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) -{ - uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ - - /* Disable all interrupts */ - USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); - USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); - DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); - - interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | - kUSDHC_SDR104TuningFlag); - - USDHC_EnableInterruptStatus(base, interruptEnabled); - - if (usingInterruptSignal) - { - USDHC_EnableInterruptSignal(base, interruptEnabled); - } -} - -static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data) -{ - assert(NULL != command); - - if ((data != NULL) && (data->blockCount > USDHC_MAX_BLOCK_COUNT)) - { - return kStatus_InvalidArgument; - } - - /* Define the flag corresponding to each response type. */ - switch (command->responseType) - { - case kCARD_ResponseTypeNone: - break; - case kCARD_ResponseTypeR1: /* Response 1 */ - case kCARD_ResponseTypeR5: /* Response 5 */ - case kCARD_ResponseTypeR6: /* Response 6 */ - case kCARD_ResponseTypeR7: /* Response 7 */ - - command->flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); - break; - - case kCARD_ResponseTypeR1b: /* Response 1 with busy */ - case kCARD_ResponseTypeR5b: /* Response 5 with busy */ - command->flags |= - (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); - break; - - case kCARD_ResponseTypeR2: /* Response 2 */ - command->flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); - break; - - case kCARD_ResponseTypeR3: /* Response 3 */ - case kCARD_ResponseTypeR4: /* Response 4 */ - command->flags |= (kUSDHC_ResponseLength48Flag); - break; - - default: - break; - } - - if (command->type == kCARD_CommandTypeAbort) - { - command->flags |= kUSDHC_CommandTypeAbortFlag; - } - - if (data) - { - command->flags |= kUSDHC_DataPresentFlag; - - if (data->rxData) - { - command->flags |= kUSDHC_DataReadFlag; - } - if (data->blockCount > 1U) - { - command->flags |= (kUSDHC_MultipleBlockFlag | kUSDHC_EnableBlockCountFlag); - /* auto command 12 */ - if (data->enableAutoCommand12) - { - /* Enable Auto command 12. */ - command->flags |= kUSDHC_EnableAutoCommand12Flag; - } - /* auto command 23 */ - if (data->enableAutoCommand23) - { - command->flags |= kUSDHC_EnableAutoCommand23Flag; - } - } - /* config data block size/block count */ - base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | - (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); - - /* auto command 23, auto send set block count cmd before multiple read/write */ - if (((command->flags & kUSDHC_EnableAutoCommand23Flag) != 0U)) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_AC23EN_MASK; - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; - /* config the block count to DS_ADDR */ - base->DS_ADDR = data->blockCount; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_AC23EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; - } - } - - return kStatus_Success; -} - -static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) -{ - uint32_t i; - - if (command->responseType != kCARD_ResponseTypeNone) - { - command->response[0U] = base->CMD_RSP0; - if (command->responseType == kCARD_ResponseTypeR2) - { - command->response[1U] = base->CMD_RSP1; - command->response[2U] = base->CMD_RSP2; - command->response[3U] = base->CMD_RSP3; - - i = 4U; - /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document - after removed internal CRC7 and end bit. */ - do - { - command->response[i - 1U] <<= 8U; - if (i > 1U) - { - command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); - } - } while (i--); - } - } - /* check response error flag */ - if ((command->responseErrorFlags != 0U) && - ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || - (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0U) - { - return kStatus_USDHC_SendCommandFailed; - } - } - - return kStatus_Success; -} - -static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = USDHC_ReadData(base); - i++; - } - - return transferredWords; -} - -static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U, interruptStatus = 0U; - status_t error = kStatus_Success; - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((error == kStatus_Success) && (transferredWords < totalWords)) - { - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) - { - } - - interruptStatus = USDHC_GetInterruptStatusFlags(base); - /* during std tuning process, software do not need to read data, but wait BRR is enough */ - if ((data->executeTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); - return kStatus_Success; - } - else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); - /* if tuning error occur ,return directly */ - error = kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - /* clear data error flag */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); - } - else - { - } - - if (error == kStatus_Success) - { - transferredWords = USDHC_ReadDataPort(base, data, transferredWords); - /* clear buffer read ready */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); - } - } - - /* Clear data complete flag after the last read operation. */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); - - return error; -} - -static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ - uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ - if (writeWatermark >= totalWords) - { - wordsCanBeWrote = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrote = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left - words. */ - else - { - wordsCanBeWrote = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrote) - { - USDHC_WriteData(base, data->txData[transferredWords++]); - i++; - } - - return transferredWords; -} - -static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) -{ - uint32_t totalWords; - - uint32_t transferredWords = 0U, interruptStatus = 0U; - status_t error = kStatus_Success; - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); - - while ((error == kStatus_Success) && (transferredWords < totalWords)) - { - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) - { - } - - interruptStatus = USDHC_GetInterruptStatusFlags(base); - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); - /* if tuning error occur ,return directly */ - return kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - /* clear data error flag */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); - } - else - { - } - - if (error == kStatus_Success) - { - transferredWords = USDHC_WriteDataPort(base, data, transferredWords); - /* clear buffer write ready */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); - } - } - - /* Wait write data complete or data transfer error after the last writing operation. */ - while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) - { - } - - if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); - - return error; -} - -void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) -{ - assert(NULL != command); - - uint32_t mixCtrl, xferType; - - mixCtrl = base->MIX_CTRL; - xferType = base->CMD_XFR_TYP; - - /* config mix parameter */ - mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | - USDHC_MIX_CTRL_AC12EN_MASK); - mixCtrl |= ((command->flags) & (USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | - USDHC_MIX_CTRL_AC12EN_MASK)); - - /* config cmd index */ - xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | - USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK); - - xferType |= (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | - ((command->flags) & - (USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | - USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK))); - /* config the mix parameter */ - base->MIX_CTRL = mixCtrl; - /* config the command xfertype and argument */ - base->CMD_ARG = command->argument; - base->CMD_XFR_TYP = xferType; -} - -static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning) -{ - assert(NULL != command); - - status_t error = kStatus_Success; - uint32_t interruptStatus = 0U; - /* tuning cmd do not need to wait command done */ - if (!executeTuning) - { - /* Wait command complete or USDHC encounters error. */ - while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) - { - } - - interruptStatus = USDHC_GetInterruptStatusFlags(base); - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - error = kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) - { - error = kStatus_Fail; - } - else - { - } - /* Receive response when command completes successfully. */ - if (error == kStatus_Success) - { - error = USDHC_ReceiveCommandResponse(base, command); - } - - USDHC_ClearInterruptStatusFlags( - base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); - } - - return error; -} - -static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) -{ - status_t error = kStatus_Success; - uint32_t interruptStatus = 0U; - - if (enDMA) - { - /* Wait data complete or USDHC encounters error. */ - while (!(USDHC_GetInterruptStatusFlags(base) & - (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag))) - { - } - - interruptStatus = USDHC_GetInterruptStatusFlags(base); - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - error = kStatus_USDHC_TuningError; - } - else if ((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U) - { - if ((!(data->enableIgnoreError)) || (interruptStatus & kUSDHC_DataTimeoutFlag)) - { - error = kStatus_Fail; - } - } - else - { - } - - USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | - kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); - } - else - { - if (data->rxData) - { - error = USDHC_ReadByDataPortBlocking(base, data); - } - else - { - error = USDHC_WriteByDataPortBlocking(base, data); - } - } - -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* invalidate cache for read */ - if ((data != NULL) && (data->rxData != NULL)) - { - /* invalidate the DCACHE */ - DCACHE_InvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } -#endif - - return error; -} - -void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) -{ - assert(config); - assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); - assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); - assert(config->writeBurstLen <= 16U); - - uint32_t proctl, sysctl, wml; - - /* Enable USDHC clock. */ - CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); - - /* Reset USDHC. */ - USDHC_Reset(base, kUSDHC_ResetAll, 100U); - - proctl = base->PROT_CTRL; - wml = base->WTMK_LVL; - sysctl = base->SYS_CTRL; - - proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); - /* Endian mode*/ - proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); - - /* Watermark level */ - wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | - USDHC_WTMK_LVL_WR_BRST_LEN_MASK); - wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | - USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); - - /* config the data timeout value */ - sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; - sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); - - base->SYS_CTRL = sysctl; - base->WTMK_LVL = wml; - base->PROT_CTRL = proctl; - -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - /* disable external DMA */ - base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; -#endif - /* disable internal DMA */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - - /* Enable interrupt status but doesn't enable interrupt signal. */ - USDHC_SetTransferInterrupt(base, false); -} - -void USDHC_Deinit(USDHC_Type *base) -{ - /* Disable clock. */ - CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); -} - -bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) -{ - base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); - /* Delay some time to wait reset success. */ - while ((base->SYS_CTRL & mask) != 0U) - { - if (timeout == 0U) - { - break; - } - timeout--; - } - - return ((!timeout) ? false : true); -} - -void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) -{ - assert(capability); - - uint32_t htCapability; - uint32_t maxBlockLength; - - htCapability = base->HOST_CTRL_CAP; - - /* Get the capability of USDHC. */ - maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); - capability->maxBlockLength = (512U << maxBlockLength); - /* Other attributes not in HTCAPBLT register. */ - capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; - capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | - kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); - capability->flags |= (htCapability & kUSDHC_SupportV300Flag); - capability->flags |= (htCapability & kUSDHC_SupportV180Flag); - capability->flags |= - (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); - /* USDHC support 4/8 bit data bus width. */ - capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); -} - -uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) -{ - assert(srcClock_Hz != 0U); - assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); - - uint32_t totalDiv = 0U; - uint32_t divisor = 0U; - uint32_t prescaler = 0U; - uint32_t sysctl = 0U; - uint32_t nearestFrequency = 0U; - uint32_t maxClKFS = ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U); - bool enDDR = false; - /* DDR mode max clkfs can reach 512 */ - if ((base->MIX_CTRL & USDHC_MIX_CTRL_DDR_EN_MASK) != 0U) - { - enDDR = true; - maxClKFS *= 2U; - } - /* calucate total divisor first */ - totalDiv = srcClock_Hz / busClock_Hz; - - if (totalDiv != 0U) - { - /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ - if ((srcClock_Hz / totalDiv) > busClock_Hz) - { - totalDiv++; - } - - /* divide the total divisor to div and prescaler */ - if (totalDiv > USDHC_MAX_DVS) - { - prescaler = totalDiv / USDHC_MAX_DVS; - /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ - while (((maxClKFS % prescaler) != 0U) || (prescaler == 1U)) - { - prescaler++; - } - /* calucate the divisor */ - divisor = totalDiv / prescaler; - /* fine tuning the divisor until divisor * prescaler >= totalDiv */ - while ((divisor * prescaler) < totalDiv) - { - divisor++; - } - nearestFrequency = srcClock_Hz / divisor / prescaler; - } - else - { - /* in this situation , divsior and SDCLKFS can generate same clock - use SDCLKFS*/ - if ((USDHC_MAX_DVS % totalDiv) == 0U) - { - divisor = 0U; - prescaler = totalDiv; - } - else - { - divisor = totalDiv; - prescaler = 0U; - } - nearestFrequency = srcClock_Hz / totalDiv; - } - } - /* in this condition , srcClock_Hz = busClock_Hz, */ - else - { - /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the - totoal divider = 2U */ - divisor = 0U; - prescaler = 0U; - nearestFrequency = srcClock_Hz; - } - - /* calucate the value write to register */ - if (divisor != 0U) - { - USDHC_PREV_DVS(divisor); - } - /* calucate the value write to register */ - if (prescaler != 0U) - { - USDHC_PREV_CLKFS(prescaler, (enDDR ? 2U : 1U)); - } - - /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ - sysctl = base->SYS_CTRL; - sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); - sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); - base->SYS_CTRL = sysctl; - - /* Wait until the SD clock is stable. */ - while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) - { - } - - return nearestFrequency; -} - -bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) -{ - base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; - /* Delay some time to wait card become active state. */ - while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) - { - if (!timeout) - { - break; - } - timeout--; - } - - return ((!timeout) ? false : true); -} - -void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) -{ - assert(config); - assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); - assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); - - uint32_t mmcboot = 0U; - - mmcboot = (USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode) | - USDHC_MMC_BOOT_BOOT_BLK_CNT(config->blockCount)); - - if (config->enableBootAck) - { - mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; - } - if (config->enableBoot) - { - mmcboot |= USDHC_MMC_BOOT_BOOT_EN_MASK; - } - if (config->enableAutoStopAtBlockGap) - { - mmcboot |= USDHC_MMC_BOOT_AUTO_SABG_EN_MASK; - } - - base->MMC_BOOT = mmcboot; -} - -status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - usdhc_data_t *dataConfig, - uint32_t flags) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->admaTable); - assert(NULL != dataConfig); - - const uint32_t *startAddress; - uint32_t entries; - uint32_t i, dmaBufferLen = 0U; - usdhc_adma1_descriptor_t *adma1EntryAddress; - usdhc_adma2_descriptor_t *adma2EntryAddress; - uint32_t dataBytes = dataConfig->blockSize * dataConfig->blockCount; - const uint32_t *data = (dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData; - - /* check DMA data buffer address align or not */ - if (((dmaConfig->dmaMode == kUSDHC_DmaModeAdma1) && (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U)) || - ((dmaConfig->dmaMode == kUSDHC_DmaModeAdma2) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U)) || - ((dmaConfig->dmaMode == kUSDHC_DmaModeSimple) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U))) - { - return kStatus_USDHC_DMADataAddrNotAlign; - } - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (dataBytes % sizeof(uint32_t) != 0U) - { - /* make the data length as word-aligned */ - dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); - } - - startAddress = data; - - switch (dmaConfig->dmaMode) - { -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - case kUSDHC_ExternalDMA: - /* enable the external DMA */ - base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; - break; -#endif - case kUSDHC_DmaModeSimple: - /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, - and block count should load to DS_ADDR*/ - if ((flags & kUSDHC_EnableAutoCommand23Flag) != 0U) - { - base->ADMA_SYS_ADDR = (uint32_t)data; - } - else - { - base->DS_ADDR = (uint32_t)data; - } - - break; - - case kUSDHC_DmaModeAdma1: - - /* Check if ADMA descriptor's number is enough. */ - if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) - { - entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); - } - - /* ADMA1 needs two descriptors to finish a transfer */ - entries <<= 1U; - - if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t))) - { - return kStatus_OutOfRange; - } - - adma1EntryAddress = (usdhc_adma1_descriptor_t *)(dmaConfig->admaTable); - for (i = 0U; i < entries; i += 2U) - { - if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) - { - dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - dataBytes -= dmaBufferLen; - } - else - { - dmaBufferLen = dataBytes; - } - - adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); - adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; - adma1EntryAddress[i + 1U] = ((uint32_t)(startAddress) << USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); - adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; - startAddress += dmaBufferLen / sizeof(uint32_t); - } - /* the end of the descriptor */ - adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; - /* When use ADMA, disable simple DMA */ - base->DS_ADDR = 0U; - base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); - break; - - case kUSDHC_DmaModeAdma2: - /* Check if ADMA descriptor's number is enough. */ - if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) - { - entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); - } - - if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t))) - { - return kStatus_OutOfRange; - } - - adma2EntryAddress = (usdhc_adma2_descriptor_t *)(dmaConfig->admaTable); - for (i = 0U; i < entries; i++) - { - if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) - { - dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - dataBytes -= dmaBufferLen; - } - else - { - dmaBufferLen = dataBytes; - } - - /* Each descriptor for ADMA2 is 64-bit in length */ - adma2EntryAddress[i].address = startAddress; - adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); - adma2EntryAddress[i].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; - startAddress += (dmaBufferLen / sizeof(uint32_t)); - } - /* set the end bit */ - adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; - /* When use ADMA, disable simple DMA */ - base->DS_ADDR = 0U; - base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); - - break; - default: - return kStatus_USDHC_PrepareAdmaDescriptorFailed; - } - - /* for external dma */ - if (dmaConfig->dmaMode != kUSDHC_ExternalDMA) - { -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - /* disable the external DMA if support */ - base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; -#endif - /* select DMA mode and config the burst length */ - base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); - base->PROT_CTRL |= - USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); - /* enable DMA */ - base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; - } - - /* disable the interrupt signal for interrupt mode */ - USDHC_DisableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); - - return kStatus_Success; -} - -status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) -{ - assert(transfer); - - status_t error = kStatus_Success; - usdhc_command_t *command = transfer->command; - usdhc_data_t *data = transfer->data; - bool enDMA = false; - - /* Wait until command/data bus out of busy status. */ - while (USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) - { - } - while (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag)) - { - } - /*check re-tuning request*/ - if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); - return kStatus_USDHC_ReTuningRequest; - } - -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - if ((data != NULL) && (!(data->executeTuning))) - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - - /* config the transfer parameter */ - if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) - { - return kStatus_InvalidArgument; - } - - /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ - if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) - { - error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); - /* if the target data buffer address is not align , we change the transfer mode - * to polling automatically, other DMA config error will not cover by driver, user - * should handle it - */ - if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) - { - return kStatus_USDHC_PrepareAdmaDescriptorFailed; - } - else if (error == kStatus_USDHC_DMADataAddrNotAlign) - { - enDMA = false; - /* disable DMA, using polling mode in this situation */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - } - else - { - enDMA = true; - } - } - else - { - /* disable DMA */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - } - /* send command */ - USDHC_SendCommand(base, command); - /* wait command done */ - error = USDHC_WaitCommandDone(base, command, ((data == NULL) ? false : data->executeTuning)); - /* transfer data */ - if ((data != NULL) && (error == kStatus_Success)) - { - return USDHC_TransferDataBlocking(base, data, enDMA); - } - - return error; -} - -status_t USDHC_TransferNonBlocking(USDHC_Type *base, - usdhc_handle_t *handle, - usdhc_adma_config_t *dmaConfig, - usdhc_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - status_t error = kStatus_Success; - usdhc_command_t *command = transfer->command; - usdhc_data_t *data = transfer->data; - - /* Wait until command/data bus out of busy status. */ - if ((USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) || - (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag))) - { - return kStatus_USDHC_BusyTransferring; - } - - /*check re-tuning request*/ - if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); - return kStatus_USDHC_ReTuningRequest; - } - -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - if ((data != NULL) && (!(data->executeTuning))) - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - - /* Save command and data into handle before transferring. */ - handle->command = command; - handle->data = data; - handle->interruptFlags = 0U; - /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ - handle->transferredWords = 0U; - - if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) - { - return kStatus_InvalidArgument; - } - - /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ - if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) - { - error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); - /* if the target data buffer address is not align , we change the transfer mode - * to polling automatically, other DMA config error will not cover by driver, user - * should handle it - */ - if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) - { - return kStatus_USDHC_PrepareAdmaDescriptorFailed; - } - else if (error == kStatus_USDHC_DMADataAddrNotAlign) - { - /* disable DMA, using polling mode in this situation */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - /* enable the interrupt signal for interrupt mode */ - USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); - } - else - { - } - } - else - { - /* disable DMA */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - } - - /* enable the buffer read ready for std tuning */ - if ((data != NULL) && (data->executeTuning)) - { - USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag); - } - - /* send command */ - USDHC_SendCommand(base, command); - - return kStatus_Success; -} - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) -#else -void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) -{ - if (enable) - { - /* make sure std_tun_en bit is clear */ - base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; - /* disable auto tuning here */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - /* execute tuning for SDR104 mode */ - base->MIX_CTRL |= - USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; - } - else - { /* abort the tuning */ - base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); - } -} - -status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) -{ - uint32_t clkTuneCtrl = 0U; - - clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; - - clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; - - clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); - - /* load the delay setting */ - base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; - /* check delat setting error */ - if (base->CLK_TUNE_CTRL_STATUS & - (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) -{ - uint32_t tuningCtrl = 0U; - - if (enable) - { - /* feedback clock */ - base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; - /* config tuning start and step */ - tuningCtrl = base->TUNING_CTRL; - tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); - tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | - USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); - base->TUNING_CTRL = tuningCtrl; - - /* excute tuning */ - base->AUTOCMD12_ERR_STATUS |= - (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); - } - else - { - /* disable the standard tuning */ - base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; - /* clear excute tuning */ - base->AUTOCMD12_ERR_STATUS &= - ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); - } -} - -void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) -{ - uint32_t busWidth = 0U; - - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; - busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; - if (busWidth == kUSDHC_DataBusWidth1Bit) - { - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else if (busWidth == kUSDHC_DataBusWidth4Bit) - { - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else if (busWidth == kUSDHC_DataBusWidth8Bit) - { - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else - { - } -} -#endif - -static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags) -{ - if (interruptFlags & kUSDHC_CardInsertionFlag) - { - if (handle->callback.CardInserted) - { - handle->callback.CardInserted(); - } - } - else - { - if (handle->callback.CardRemoved) - { - handle->callback.CardRemoved(); - } - } -} - -static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command); - - if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data))) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); - } - } - else - { - /* Receive response */ - if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); - } - } - else if ((!(handle->data)) && (handle->callback.TransferComplete)) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - else - { - } - } -} - -static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data); - - if (((!(handle->data->enableIgnoreError)) || (interruptFlags & kUSDHC_DataTimeoutFlag)) && - (interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag))) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); - } - } - else - { - if (interruptFlags & kUSDHC_BufferReadReadyFlag) - { - /* std tuning process only need to wait BRR */ - if (handle->data->executeTuning) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - else - { - handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); - } - } - else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) - { - handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); - } - else if (interruptFlags & kUSDHC_DataCompleteFlag) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - else - { - /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* invalidate cache for read */ - if ((handle->data != NULL) && (handle->data->rxData != NULL)) - { - /* invalidate the DCACHE */ - DCACHE_InvalidateByRange((uint32_t)handle->data->rxData, - (handle->data->blockSize) * (handle->data->blockCount)); - } -#endif - } -} - -static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle) -{ - if (handle->callback.SdioInterrupt) - { - handle->callback.SdioInterrupt(); - } -} - -static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->callback.ReTuning); - /* retuning request */ - if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) - { - handle->callback.ReTuning(); /* retuning fail */ - } -} - -static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle) -{ - if (handle->callback.SdioBlockGap) - { - handle->callback.SdioBlockGap(); - } -} - -void USDHC_TransferCreateHandle(USDHC_Type *base, - usdhc_handle_t *handle, - const usdhc_transfer_callback_t *callback, - void *userData) -{ - assert(handle); - assert(callback); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.CardInserted = callback->CardInserted; - handle->callback.CardRemoved = callback->CardRemoved; - handle->callback.SdioInterrupt = callback->SdioInterrupt; - handle->callback.SdioBlockGap = callback->SdioBlockGap; - handle->callback.TransferComplete = callback->TransferComplete; - handle->callback.ReTuning = callback->ReTuning; - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_usdhcHandle[USDHC_GetInstance(base)] = handle; - - /* Enable interrupt in NVIC. */ - USDHC_SetTransferInterrupt(base, true); - /* disable the tuning pass interrupt */ - USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); - /* save IRQ handler */ - s_usdhcIsr = USDHC_TransferHandleIRQ; - - EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); -} - -void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) -{ - assert(handle); - - uint32_t interruptFlags; - - interruptFlags = USDHC_GetInterruptStatusFlags(base); - handle->interruptFlags = interruptFlags; - - if (interruptFlags & kUSDHC_CardDetectFlag) - { - USDHC_TransferHandleCardDetect(handle, (interruptFlags & kUSDHC_CardDetectFlag)); - } - if (interruptFlags & kUSDHC_CommandFlag) - { - USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); - } - if (interruptFlags & kUSDHC_DataFlag) - { - USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); - } - if (interruptFlags & kUSDHC_CardInterruptFlag) - { - USDHC_TransferHandleSdioInterrupt(handle); - } - if (interruptFlags & kUSDHC_BlockGapEventFlag) - { - USDHC_TransferHandleSdioBlockGap(handle); - } - if (interruptFlags & kUSDHC_SDR104TuningFlag) - { - USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); - } - - USDHC_ClearInterruptStatusFlags(base, interruptFlags); -} - -#ifdef USDHC0 -void USDHC0_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); -} -#endif - -#ifdef USDHC1 -void USDHC1_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); -} -#endif - -#ifdef USDHC2 -void USDHC2_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); -} - -#endif diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.h deleted file mode 100644 index 77fd8e911bd50e995626d8f21daf31b96f1ab377..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_usdhc.h +++ /dev/null @@ -1,1358 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USDHC_H_ -#define _FSL_USDHC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usdhc - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.1.2. */ -#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U)) -/*@}*/ - -/*! @brief Maximum block count can be set one time */ -#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) - -/*! @brief USDHC status */ -enum _usdhc_status -{ - kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ - kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ - kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ - kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ - kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ - kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ - kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ - -}; - -/*! @brief Host controller capabilities flag mask */ -enum _usdhc_capability_flag -{ - kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ - kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ - kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ - kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ - kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ - kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ - kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ - /* Put additional two flags in HTCAPBLT_MBL's position. */ - kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ - kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ - /* sd version 3.0 new feature */ - kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) - kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ -#else - kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ -#endif -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ -#else - kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ -#endif -}; - -/*! @brief Wakeup event mask */ -enum _usdhc_wakeup_event -{ - kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ - kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ - kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ - - kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | - kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ -}; - -/*! @brief Reset type mask */ -enum _usdhc_reset -{ - kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ - kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ - kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ -#else - kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ -#endif - - kUSDHC_ResetsAll = - (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ -}; - -/*! @brief Transfer flag mask */ -enum _usdhc_transfer_flag -{ - kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ - - kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ - kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ - kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ - - kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ - kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ - kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ - kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ - kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ - - kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ - kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ - kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ - - kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ - kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ - kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ -}; - -/*! @brief Present status flag mask */ -enum _usdhc_present_status_flag -{ - kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ - kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ - kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ - kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ - kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ - kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ - kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ - kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ - kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ -#else - kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ - kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ -#endif - - kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ - kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ - - kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ - kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ - kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ - kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ - kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ - kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ - kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ - kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ -}; - -/*! @brief Interrupt status flag mask */ -enum _usdhc_interrupt_status_flag -{ - kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ - kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ - kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ - kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ - kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ - kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ - kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ - kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ - kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ - kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ - kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ -#else - kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ - kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ - kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ -#endif - - kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ - kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ - kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ - kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ - kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ - kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ - kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ - kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ - kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ - - kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | - kUSDHC_CommandIndexErrorFlag), /*!< Command error */ - kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | - kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ - kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ - kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | - kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ - kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ - kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ - kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), - - kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | - kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ -}; - -/*! @brief Auto CMD12 error status flag mask */ -enum _usdhc_auto_command12_error_status_flag -{ - kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ - kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ - kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ - kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ - kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ - kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ -}; - -/*! @brief standard tuning flag */ -enum _usdhc_standard_tuning -{ -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ExecuteTuning = 0U, /*!< not support */ - kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ -#else - kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ - kUSDHC_TuningSampleClockSel = - USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used - select sampleing clock */ -#endif -}; - -/*! @brief ADMA error status flag mask */ -enum _usdhc_adma_error_status_flag -{ - kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ - kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ -}; - -/*! - * @brief ADMA error state - * - * This state is the detail state when ADMA error has occurred. - */ -typedef enum _usdhc_adma_error_state -{ - kUSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ - kUSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ - kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ - kUSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ -} usdhc_adma_error_state_t; - -/*! @brief Force event mask */ -enum _usdhc_force_event -{ - kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ - kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ - kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ - kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ - kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ - kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ - kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ - kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ - kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ - kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ - kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ - kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ - kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ - kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ - kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ - kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ForceEventTuningError = 0U, /*!< not support */ -#else - kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ -#endif - kUSDHC_ForceEventsAll = - (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | - kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | - kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | - kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | - kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | - kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | - kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ -}; - -/*! @brief Data transfer width */ -typedef enum _usdhc_data_bus_width -{ - kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ - kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ - kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ -} usdhc_data_bus_width_t; - -/*! @brief Endian mode */ -typedef enum _usdhc_endian_mode -{ - kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ - kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ - kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ -} usdhc_endian_mode_t; - -/*! @brief DMA mode */ -typedef enum _usdhc_dma_mode -{ - kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ - kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ - kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ - kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ -} usdhc_dma_mode_t; - -/*! @brief SDIO control flag mask */ -enum _usdhc_sdio_control_flag -{ - kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ - kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ - kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ - kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ - kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ -}; - -/*! @brief MMC card boot mode */ -typedef enum _usdhc_boot_mode -{ - kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ - kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ -} usdhc_boot_mode_t; - -/*! @brief The command type */ -typedef enum _usdhc_card_command_type -{ - kCARD_CommandTypeNormal = 0U, /*!< Normal command */ - kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ - kCARD_CommandTypeResume = 2U, /*!< Resume command */ - kCARD_CommandTypeAbort = 3U, /*!< Abort command */ -} usdhc_card_command_type_t; - -/*! - * @brief The command response type. - * - * Define the command response type from card to host controller. - */ -typedef enum _usdhc_card_response_type -{ - kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ - kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ - kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ - kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ - kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ - kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ - kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ - kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ - kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ - kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ -} usdhc_card_response_type_t; - -/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ -#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) -/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ -#define USDHC_ADMA1_LENGTH_ALIGN (4096U) -/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ -#define USDHC_ADMA2_ADDRESS_ALIGN (4U) -/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ -#define USDHC_ADMA2_LENGTH_ALIGN (4U) - -/* ADMA1 descriptor table - * |------------------------|---------|--------------------------| - * | Address/page field |Reserved | Attribute | - * |------------------------|---------|--------------------------| - * |31 12|11 6|05 |04 |03|02 |01 |00 | - * |------------------------|---------|----|----|--|---|---|-----| - * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| - * |------------------------|---------|----|----|--|---|---|-----| - * - * - * |------|------|-----------------|-------|-------------| - * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | - * |------|------|-----------------|---------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------|-------------| - * | 0 | 1 | Set data length | 0000 | Data Length | - * |------|------|-----------------|-------|-------------| - * | 1 | 0 | Transfer data | Data address | - * |------|------|-----------------|---------------------| - * | 1 | 1 | Link descriptor | Descriptor address | - * |------|------|-----------------|---------------------| - */ -/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) -/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) -/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) -/*! @brief The mask for LENGTH field in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) -/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U) - -/*! @brief The mask for the control/status field in ADMA1 descriptor */ -enum _usdhc_adma1_descriptor_flag -{ - kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ - kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ - kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ - kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ - kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ - kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ - kUSDHC_Adma1DescriptorTypeTransfer = - (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ - kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | - kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ - kUSDHC_Adma1DescriptorTypeSetLength = - (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ -}; - -/* ADMA2 descriptor table - * |----------------|---------------|-------------|--------------------------| - * | Address field | Length | Reserved | Attribute | - * |----------------|---------------|-------------|--------------------------| - * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * - * - * | Act2 | Act1 | Comment | Operation | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 1 | Reserved | Read this line and go to next one | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 1 | Link descriptor | Link to another descriptor | - * |------|------|-----------------|-------------------------------------------------------------------| - */ -/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) -/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) -/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) - -/*! @brief ADMA1 descriptor control and status mask */ -enum _usdhc_adma2_descriptor_flag -{ - kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ - kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ - kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ - kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ - kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ - - kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ - kUSDHC_Adma2DescriptorTypeReserved = - (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ - kUSDHC_Adma2DescriptorTypeTransfer = - (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ - kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | - kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ -}; - -/*! @brief dma transfer burst len config. */ -typedef enum _usdhc_burst_len -{ - kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ - kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ - kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ -} usdhc_burst_len_t; - -/*! @brief Defines the adma1 descriptor structure. */ -typedef uint32_t usdhc_adma1_descriptor_t; - -/*! @brief Defines the ADMA2 descriptor structure. */ -typedef struct _usdhc_adma2_descriptor -{ - uint32_t attribute; /*!< The control and status field */ - const uint32_t *address; /*!< The address field */ -} usdhc_adma2_descriptor_t; - -/*! - * @brief USDHC capability information. - * - * Defines a structure to save the capability information of USDHC. - */ -typedef struct _usdhc_capability -{ - uint32_t sdVersion; /*!< support SD card/sdio version */ - uint32_t mmcVersion; /*!< support emmc card version */ - uint32_t maxBlockLength; /*!< Maximum block length united as byte */ - uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ - uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ -} usdhc_capability_t; - -/*! @brief Data structure to configure the MMC boot feature */ -typedef struct _usdhc_boot_config -{ - uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ - usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ - uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ - bool enableBootAck; /*!< Enable or disable boot ACK */ - bool enableBoot; /*!< Enable or disable fast boot */ - bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ -} usdhc_boot_config_t; - -/*! @brief Data structure to initialize the USDHC */ -typedef struct _usdhc_config -{ - uint32_t dataTimeout; /*!< Data timeout value */ - usdhc_endian_mode_t endianMode; /*!< Endian mode */ - uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ - uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ - uint8_t readBurstLen; /*!< Read burst len */ - uint8_t writeBurstLen; /*!< Write burst len */ -} usdhc_config_t; - -/*! - * @brief Card data descriptor - * - * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card - * driver - * want to ignore the error event to read/write all the data not to stop read/write immediately when error event - * happen for example bus testing procedure for MMC card. - */ -typedef struct _usdhc_data -{ - bool enableAutoCommand12; /*!< Enable auto CMD12 */ - bool enableAutoCommand23; /*!< Enable auto CMD23 */ - bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ - bool executeTuning; /*!< execute tuning flag */ - - size_t blockSize; /*!< Block size */ - uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< Buffer to save data read */ - const uint32_t *txData; /*!< Data buffer to write */ -} usdhc_data_t; - -/*! - * @brief Card command descriptor - * - * Define card command-related attribute. - */ -typedef struct _usdhc_command -{ - uint32_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - usdhc_card_command_type_t type; /*!< Command type */ - usdhc_card_response_type_t responseType; /*!< Command response type */ - uint32_t response[4U]; /*!< Response for this command */ - uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check - the command reponse*/ - uint32_t flags; /*!< Cmd flags */ -} usdhc_command_t; - -/*! @brief ADMA configuration */ -typedef struct _usdhc_adma_config -{ - usdhc_dma_mode_t dmaMode; /*!< DMA mode */ - - usdhc_burst_len_t burstLen; /*!< burst len config */ - - uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ - uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ -} usdhc_adma_config_t; - -/*! @brief Transfer state */ -typedef struct _usdhc_transfer -{ - usdhc_data_t *data; /*!< Data to transfer */ - usdhc_command_t *command; /*!< Command to send */ -} usdhc_transfer_t; - -/*! @brief USDHC handle typedef */ -typedef struct _usdhc_handle usdhc_handle_t; - -/*! @brief USDHC callback functions. */ -typedef struct _usdhc_transfer_callback -{ - void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ - void (*CardRemoved)(void); /*!< Card removed occurs */ - void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ - void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ - void (*TransferComplete)(USDHC_Type *base, - usdhc_handle_t *handle, - status_t status, - void *userData); /*!< Transfer complete callback */ - void (*ReTuning)(void); /*!< handle the re-tuning */ -} usdhc_transfer_callback_t; - -/*! - * @brief USDHC handle - * - * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when - * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in - * usdhc_interrupt_flag_t. - * - * @note All the fields except interruptFlags and transferredWords must be allocated by the user. - */ -struct _usdhc_handle -{ - /* Transfer parameter */ - usdhc_data_t *volatile data; /*!< Data to transfer */ - usdhc_command_t *volatile command; /*!< Command to send */ - - /* Transfer status */ - volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ - volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ - - /* Callback functions */ - usdhc_transfer_callback_t callback; /*!< Callback function */ - void *userData; /*!< Parameter for transfer complete callback */ -}; - -/*! @brief USDHC transfer function. */ -typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); - -/*! @brief USDHC host descriptor */ -typedef struct _usdhc_host -{ - USDHC_Type *base; /*!< USDHC peripheral base address */ - uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ - usdhc_config_t config; /*!< USDHC configuration */ - usdhc_capability_t capability; /*!< USDHC capability information */ - usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ -} usdhc_host_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief USDHC module initialization function. - * - * Configures the USDHC according to the user configuration. - * - * Example: - @code - usdhc_config_t config; - config.cardDetectDat3 = false; - config.endianMode = kUSDHC_EndianModeLittle; - config.dmaMode = kUSDHC_DmaModeAdma2; - config.readWatermarkLevel = 128U; - config.writeWatermarkLevel = 128U; - USDHC_Init(USDHC, &config); - @endcode - * - * @param base USDHC peripheral base address. - * @param config USDHC configuration information. - * @retval kStatus_Success Operate successfully. - */ -void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); - -/*! - * @brief Deinitializes the USDHC. - * - * @param base USDHC peripheral base address. - */ -void USDHC_Deinit(USDHC_Type *base); - -/*! - * @brief Resets the USDHC. - * - * @param base USDHC peripheral base address. - * @param mask The reset type mask(_usdhc_reset). - * @param timeout Timeout for reset. - * @retval true Reset successfully. - * @retval false Reset failed. - */ -bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); - -/* @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Sets the ADMA descriptor table configuration. - * - * @param base USDHC peripheral base address. - * @param adma configuration - * @param data Data descriptor - * @param command flags - * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - usdhc_data_t *dataConfig, - uint32_t flags); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt status. - * - * @param base USDHC peripheral base address. - * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS_EN |= mask; -} - -/*! - * @brief Disables the interrupt status. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS_EN &= ~mask; -} - -/*! - * @brief Enables the interrupt signal corresponding to the interrupt status flag. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) -{ - base->INT_SIGNAL_EN |= mask; -} - -/*! - * @brief Disables the interrupt signal corresponding to the interrupt status flag. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) -{ - base->INT_SIGNAL_EN &= ~mask; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the current interrupt status. - * - * @param base USDHC peripheral base address. - * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) -{ - return base->INT_STATUS; -} - -/*! - * @brief Clears a specified interrupt status. - * write 1 clears - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS = mask; -} - -/*! - * @brief Gets the status of auto command 12 error. - * - * @param base USDHC peripheral base address. - * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). - */ -static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) -{ - return base->AUTOCMD12_ERR_STATUS; -} - -/*! - * @brief Gets the status of the ADMA error. - * - * @param base USDHC peripheral base address. - * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). - */ -static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) -{ - return base->ADMA_ERR_STATUS; -} - -/*! - * @brief Gets a present status. - * - * This function gets the present USDHC's status except for an interrupt status and an error status. - * - * @param base USDHC peripheral base address. - * @return Present USDHC's status flags mask(_usdhc_present_status_flag). - */ -static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) -{ - return base->PRES_STATE; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Gets the capability information. - * - * @param base USDHC peripheral base address. - * @param capability Structure to save capability information. - */ -void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); - -/*! - * @brief force the card clock on. - * - * @param base USDHC peripheral base address. - * @param enable/disable flag. - */ -static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; - } - else - { - base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; - } -} - -/*! - * @brief Sets the SD bus clock frequency. - * - * @param base USDHC peripheral base address. - * @param srcClock_Hz USDHC source clock frequency united in Hz. - * @param busClock_Hz SD bus clock frequency united in Hz. - * - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); - -/*! - * @brief Sends 80 clocks to the card to set it to the active state. - * - * This function must be called each time the card is inserted to ensure that the card can receive the command - * correctly. - * - * @param base USDHC peripheral base address. - * @param timeout Timeout to initialize card. - * @retval true Set card active successfully. - * @retval false Set card active failed. - */ -bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); - -/*! - * @brief trigger a hardware reset. - * - * @param base USDHC peripheral base address. - * @param 1 or 0 level - */ -static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) -{ - if (high) - { - base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; - } - else - { - base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; - } -} - -/*! - * @brief Sets the data transfer width. - * - * @param base USDHC peripheral base address. - * @param width Data transfer width. - */ -static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) -{ - base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); -} - -/*! - * @brief Fills the the data port. - * - * This function is used to implement the data transfer by Data Port instead of DMA. - * - * @param base USDHC peripheral base address. - * @param data The data about to be sent. - */ -static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) -{ - base->DATA_BUFF_ACC_PORT = data; -} - -/*! - * @brief Retrieves the data from the data port. - * - * This function is used to implement the data transfer by Data Port instead of DMA. - * - * @param base USDHC peripheral base address. - * @return The data has been read. - */ -static inline uint32_t USDHC_ReadData(USDHC_Type *base) -{ - return base->DATA_BUFF_ACC_PORT; -} - -/*! -* @brief send command function -* -* @param base USDHC peripheral base address. -* @param command configuration -*/ -void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); - -/*! - * @brief Enables or disables a wakeup event in low-power mode. - * - * @param base USDHC peripheral base address. - * @param mask Wakeup events mask(_usdhc_wakeup_event). - * @param enable True to enable, false to disable. - */ -static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= mask; - } - else - { - base->PROT_CTRL &= ~mask; - } -} - -/*! - * @brief detect card insert status. - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; - } - else - { - base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; - } -} - -/*! - * @brief detect card insert status. - * - * @param base USDHC peripheral base address. - */ -static inline bool USDHC_DetectCardInsert(USDHC_Type *base) -{ - return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; -} - -/*! - * @brief Enables or disables the SDIO card control. - * - * @param base USDHC peripheral base address. - * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). - * @param enable True to enable, false to disable. - */ -static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= mask; - } - else - { - base->PROT_CTRL &= ~mask; - } -} -/*! - * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. - * - * @param base USDHC peripheral base address. - */ -static inline void USDHC_SetContinueRequest(USDHC_Type *base) -{ - base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; -} - -/*! - * @brief Configures the MMC boot feature. - * - * Example: - @code - usdhc_boot_config_t config; - config.ackTimeoutCount = 4; - config.bootMode = kUSDHC_BootModeNormal; - config.blockCount = 5; - config.enableBootAck = true; - config.enableBoot = true; - config.enableAutoStopAtBlockGap = true; - USDHC_SetMmcBootConfig(USDHC, &config); - @endcode - * - * @param base USDHC peripheral base address. - * @param config The MMC boot configuration information. - */ -void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); - -/*! - * @brief Forces generating events according to the given mask. - * - * @param base USDHC peripheral base address. - * @param mask The force events mask(_usdhc_force_event). - */ -static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) -{ - base->FORCE_EVENT = mask; -} - -/*! - * @brief select the usdhc output voltage - * - * @param base USDHC peripheral base address. - * @param true 1.8V, false 3.0V - */ -static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) -{ - if (en18v) - { - base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; - } - else - { - base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; - } -} - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) -#else - /*! - * @brief check the SDR50 mode request tuning bit - * When this bit set, user should call USDHC_StandardTuning function - * @param base USDHC peripheral base address. - */ -static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) -{ - return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; -} - -/*! - * @brief check the request re-tuning bit - * When this bit is set, user should do manual tuning or standard tuning function - * @param base USDHC peripheral base address. - */ -static inline bool USDHC_RequestReTuning(USDHC_Type *base) -{ - return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; -} - -/*! - * @brief the SDR104 mode auto tuning enable and disable - * This function should call after tuning function execute pass, auto tuning will handle - * by hardware - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - } -} - -/*! - * @brief the config the re-tuning timer for mode 1 and mode 3 - * This timer is used for standard tuning auto re-tuning, - * @param base USDHC peripheral base address. - * @param timer counter value - */ -static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) -{ - base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; - base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); -} - -/*! - * @brief the auto tuning enbale for CMD/DATA line - * - * @param base USDHC peripheral base address. - */ -void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); - -/*! - * @brief manual tuning trigger or abort - * User should handle the tuning cmd and find the boundary of the delay - * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS - * This function should called before USDHC_AdjustDelayforSDR104 function - * @param base USDHC peripheral base address. - * @param tuning enable flag - */ -void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); - -/*! - * @brief the SDR104 mode delay setting adjust - * This function should called after USDHC_ManualTuningForSDR104 - * @param base USDHC peripheral base address. - * @param delay setting configuration - * @retval kStatus_Fail config the delay setting fail - * @retval kStatus_Success config the delay setting success - */ -status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); - -/*! - * @brief the enable standard tuning function - * The standard tuning window and tuning counter use the default config - * tuning cmd is send by the software, user need to check the tuning result - * can be used for SDR50,SDR104,HS200 mode tuning - * @param base USDHC peripheral base address. - * @param tuning start tap - * @param tuning step - * @param enable/disable flag - */ -void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); - -/*! - * @brief Get execute std tuning status - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) -{ - return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); -} - -/*! - * @brief check std tuning result - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) -{ - return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); -} - -/*! - * @brief check tuning error - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) -{ - return (base->CLK_TUNE_CTRL_STATUS & - (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); -} - -#endif -/*! - * @brief the enable/disable DDR mode - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - * @param nibble position - */ -static inline void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) -{ - if (enable) - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; - base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; - } -} - -/*! - * @brief the enable/disable HS400 mode - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -#if FSL_FEATURE_USDHC_HAS_HS400_MODE -static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; - } -} - -/*! - * @brief reset the strobe DLL - * - * @param base USDHC peripheral base address. - */ -static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) -{ - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; -} - -/*! - * @brief enable/disable the strobe DLL - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; - } - else - { - base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; - } -} - -/*! - * @brief config the strobe DLL delay target and update interval - * - * @param base USDHC peripheral base address. - * @param delay target - * @param update interval - */ -static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) -{ - base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | - USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); - - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | - USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); -} - -/*! - * @brief get the strobe DLL status - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) -{ - return base->STROBE_DLL_STATUS; -} - -#endif - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Transfers the command/data using a blocking method. - * - * This function waits until the command response/data is received or the USDHC encounters an error by polling the - * status - * flag. - * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support - * the re-entry mechanism. - * - * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. - * - * @param base USDHC peripheral base address. - * @param adma configuration - * @param transfer Transfer content. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. - * @retval kStatus_USDHC_SendCommandFailed Send command failed. - * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); - -/*! - * @brief Creates the USDHC handle. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void USDHC_TransferCreateHandle(USDHC_Type *base, - usdhc_handle_t *handle, - const usdhc_transfer_callback_t *callback, - void *userData); - -/*! - * @brief Transfers the command/data using an interrupt and an asynchronous method. - * - * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an - * error. - * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support - * the re-entry mechanism. - * - * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param adma configuration. - * @param transfer Transfer content. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_USDHC_BusyTransferring Busy transferring. - * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_TransferNonBlocking(USDHC_Type *base, - usdhc_handle_t *handle, - usdhc_adma_config_t *dmaConfig, - usdhc_transfer_t *transfer); - -/*! - * @brief IRQ handler for the USDHC. - * - * This function deals with the IRQs on the given host controller. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - */ -void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_USDHC_H_*/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.c deleted file mode 100644 index f8755577633b2c5d9b703a89d32132d0dbd92708..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wdog32.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask) -{ - if (mask & kWDOG32_InterruptFlag) - { - base->CS |= WDOG_CS_FLG_MASK; - } -} - -void WDOG32_GetDefaultConfig(wdog32_config_t *config) -{ - assert(config); - - config->enableWdog32 = true; - config->clockSource = kWDOG32_ClockSource1; - config->prescaler = kWDOG32_ClockPrescalerDivide1; - config->workMode.enableWait = true; - config->workMode.enableStop = false; - config->workMode.enableDebug = false; - config->testMode = kWDOG32_TestModeDisabled; - config->enableUpdate = true; - config->enableInterrupt = false; - config->enableWindowMode = false; - config->windowValue = 0U; - config->timeoutValue = 0xFFFFU; -} - -void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - uint32_t primaskValue = 0U; - - value = WDOG_CS_EN(config->enableWdog32) | WDOG_CS_CLK(config->clockSource) | WDOG_CS_INT(config->enableInterrupt) | - WDOG_CS_WIN(config->enableWindowMode) | WDOG_CS_UPDATE(config->enableUpdate) | - WDOG_CS_DBG(config->workMode.enableDebug) | WDOG_CS_STOP(config->workMode.enableStop) | - WDOG_CS_WAIT(config->workMode.enableWait) | WDOG_CS_PRES(config->prescaler) | WDOG_CS_CMD32EN(true) | - WDOG_CS_TST(config->testMode); - - /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence - * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ - primaskValue = DisableGlobalIRQ(); - WDOG32_Unlock(base); - base->WIN = config->windowValue; - base->TOVAL = config->timeoutValue; - base->CS = value; - EnableGlobalIRQ(primaskValue); -} - -void WDOG32_Deinit(WDOG_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupts */ - primaskValue = DisableGlobalIRQ(); - WDOG32_Unlock(base); - WDOG32_Disable(base); - EnableGlobalIRQ(primaskValue); -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.h deleted file mode 100644 index 90dde81ae1b097c311bf1226181ead895152e6e3..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_wdog32.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_WDOG32_H_ -#define _FSL_WDOG32_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wdog32 - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ -/*! @name Unlock sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_UNLOCK (WDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ -#define WDOG_SECOND_WORD_OF_UNLOCK ((WDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */ -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_REFRESH (WDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ -#define WDOG_SECOND_WORD_OF_REFRESH ((WDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */ -/*@}*/ -/*! @name Driver version */ -/*@{*/ -/*! @brief WDOG32 driver version 2.0.0. */ -#define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Describes WDOG32 clock source. */ -typedef enum _wdog32_clock_source -{ - kWDOG32_ClockSource0 = 0U, /*!< Clock source 0 */ - kWDOG32_ClockSource1 = 1U, /*!< Clock source 1 */ - kWDOG32_ClockSource2 = 2U, /*!< Clock source 2 */ - kWDOG32_ClockSource3 = 3U, /*!< Clock source 3 */ -} wdog32_clock_source_t; - -/*! @brief Describes the selection of the clock prescaler. */ -typedef enum _wdog32_clock_prescaler -{ - kWDOG32_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ - kWDOG32_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ -} wdog32_clock_prescaler_t; - -/*! @brief Defines WDOG32 work mode. */ -typedef struct _wdog32_work_mode -{ - bool enableWait; /*!< Enables or disables WDOG32 in wait mode */ - bool enableStop; /*!< Enables or disables WDOG32 in stop mode */ - bool enableDebug; /*!< Enables or disables WDOG32 in debug mode */ -} wdog32_work_mode_t; - -/*! @brief Describes WDOG32 test mode. */ -typedef enum _wdog32_test_mode -{ - kWDOG32_TestModeDisabled = 0U, /*!< Test Mode disabled */ - kWDOG32_UserModeEnabled = 1U, /*!< User Mode enabled */ - kWDOG32_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ - kWDOG32_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ -} wdog32_test_mode_t; - -/*! @brief Describes WDOG32 configuration structure. */ -typedef struct _wdog32_config -{ - bool enableWdog32; /*!< Enables or disables WDOG32 */ - wdog32_clock_source_t clockSource; /*!< Clock source select */ - wdog32_clock_prescaler_t prescaler; /*!< Clock prescaler value */ - wdog32_work_mode_t workMode; /*!< Configures WDOG32 work mode in debug stop and wait mode */ - wdog32_test_mode_t testMode; /*!< Configures WDOG32 test mode */ - bool enableUpdate; /*!< Update write-once register enable */ - bool enableInterrupt; /*!< Enables or disables WDOG32 interrupt */ - bool enableWindowMode; /*!< Enables or disables WDOG32 window mode */ - uint16_t windowValue; /*!< Window value */ - uint16_t timeoutValue; /*!< Timeout value */ -} wdog32_config_t; - -/*! - * @brief WDOG32 interrupt configuration structure. - * - * This structure contains the settings for all of the WDOG32 interrupt configurations. - */ -enum _wdog32_interrupt_enable_t -{ - kWDOG32_InterruptEnable = WDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */ -}; - -/*! - * @brief WDOG32 status flags. - * - * This structure contains the WDOG32 status flags for use in the WDOG32 functions. - */ -enum _wdog32_status_flags_t -{ - kWDOG32_RunningFlag = WDOG_CS_EN_MASK, /*!< Running flag, set when WDOG32 is enabled */ - kWDOG32_InterruptFlag = WDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WDOG32 Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes the WDOG32 configuration structure. - * - * This function initializes the WDOG32 configuration structure to default values. The default - * values are: - * @code - * wdog32Config->enableWdog32 = true; - * wdog32Config->clockSource = kWDOG32_ClockSource1; - * wdog32Config->prescaler = kWDOG32_ClockPrescalerDivide1; - * wdog32Config->workMode.enableWait = true; - * wdog32Config->workMode.enableStop = false; - * wdog32Config->workMode.enableDebug = false; - * wdog32Config->testMode = kWDOG32_TestModeDisabled; - * wdog32Config->enableUpdate = true; - * wdog32Config->enableInterrupt = false; - * wdog32Config->enableWindowMode = false; - * wdog32Config->windowValue = 0U; - * wdog32Config->timeoutValue = 0xFFFFU; - * @endcode - * - * @param config Pointer to the WDOG32 configuration structure. - * @see wdog32_config_t - */ -void WDOG32_GetDefaultConfig(wdog32_config_t *config); - -/*! - * @brief Initializes the WDOG32 module. - * - * This function initializes the WDOG32. - * To reconfigure the WDOG32 without forcing a reset first, enableUpdate must be set to true - * in the configuration. - * - * Example: - * @code - * wdog32_config_t config; - * WDOG32_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * config.enableUpdate = true; - * WDOG32_Init(wdog_base,&config); - * @endcode - * - * @param base WDOG32 peripheral base address. - * @param config The configuration of the WDOG32. - */ -void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config); - -/*! - * @brief De-initializes the WDOG32 module. - * - * This function shuts down the WDOG32. - * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. - * - * @param base WDOG32 peripheral base address. - */ -void WDOG32_Deinit(WDOG_Type *base); - -/* @} */ - -/*! - * @name WDOG32 functional Operation - * @{ - */ - -/*! - * @brief Enables the WDOG32 module. - * - * This function writes a value into the WDOG_CS register to enable the WDOG32. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address. - */ -static inline void WDOG32_Enable(WDOG_Type *base) -{ - base->CS |= WDOG_CS_EN_MASK; -} - -/*! - * @brief Disables the WDOG32 module. - * - * This function writes a value into the WDOG_CS register to disable the WDOG32. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address - */ -static inline void WDOG32_Disable(WDOG_Type *base) -{ - base->CS &= ~WDOG_CS_EN_MASK; -} - -/*! - * @brief Enables the WDOG32 interrupt. - * - * This function writes a value into the WDOG_CS register to enable the WDOG32 interrupt. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address. - * @param mask The interrupts to enable. - * The parameter can be a combination of the following source if defined: - * @arg kWDOG32_InterruptEnable - */ -static inline void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask) -{ - base->CS |= mask; -} - -/*! - * @brief Disables the WDOG32 interrupt. - * - * This function writes a value into the WDOG_CS register to disable the WDOG32 interrupt. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address. - * @param mask The interrupts to disabled. - * The parameter can be a combination of the following source if defined: - * @arg kWDOG32_InterruptEnable - */ -static inline void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask) -{ - base->CS &= ~mask; -} - -/*! - * @brief Gets the WDOG32 all status flags. - * - * This function gets all status flags. - * - * Example to get the running flag: - * @code - * uint32_t status; - * status = WDOG32_GetStatusFlags(wdog_base) & kWDOG32_RunningFlag; - * @endcode - * @param base WDOG32 peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false). @see _wdog32_status_flags_t - * - true: related status flag has been set. - * - false: related status flag is not set. - */ -static inline uint32_t WDOG32_GetStatusFlags(WDOG_Type *base) -{ - return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK)); -} - -/*! - * @brief Clears the WDOG32 flag. - * - * This function clears the WDOG32 status flag. - * - * Example to clear an interrupt flag: - * @code - * WDOG32_ClearStatusFlags(wdog_base,kWDOG32_InterruptFlag); - * @endcode - * @param base WDOG32 peripheral base address. - * @param mask The status flags to clear. - * The parameter can be any combination of the following values: - * @arg kWDOG32_InterruptFlag - */ -void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask); - -/*! - * @brief Sets the WDOG32 timeout value. - * - * This function writes a timeout value into the WDOG_TOVAL register. - * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address - * @param timeoutCount WDOG32 timeout value, count of WDOG32 clock ticks. - */ -static inline void WDOG32_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) -{ - base->TOVAL = timeoutCount; -} - -/*! - * @brief Sets the WDOG32 window value. - * - * This function writes a window value into the WDOG_WIN register. - * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base WDOG32 peripheral base address. - * @param windowValue WDOG32 window value. - */ -static inline void WDOG32_SetWindowValue(WDOG_Type *base, uint16_t windowValue) -{ - base->WIN = windowValue; -} - -/*! - * @brief Unlocks the WDOG32 register written. - * - * This function unlocks the WDOG32 register written. - * - * Before starting the unlock sequence and following the configuration, disable the global interrupts. - * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. - * After the configuration finishes, re-enable the global interrupts. - * - * @param base WDOG32 peripheral base address - */ -static inline void WDOG32_Unlock(WDOG_Type *base) -{ - if ((base->CS) & WDOG_CS_CMD32EN_MASK) - { - base->CNT = WDOG_UPDATE_KEY; - } - else - { - base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; - base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; - } -} - -/*! - * @brief Refreshes the WDOG32 timer. - * - * This function feeds the WDOG32. - * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WDOG32 peripheral base address - */ -static inline void WDOG32_Refresh(WDOG_Type *base) -{ - if ((base->CS) & WDOG_CS_CMD32EN_MASK) - { - base->CNT = WDOG_REFRESH_KEY; - } - else - { - base->CNT = WDOG_FIRST_WORD_OF_REFRESH; - base->CNT = WDOG_SECOND_WORD_OF_REFRESH; - } -} - -/*! - * @brief Gets the WDOG32 counter value. - * - * This function gets the WDOG32 counter value. - * - * @param base WDOG32 peripheral base address. - * @return Current WDOG32 counter value. - */ -static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base) -{ - return base->CNT; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WDOG32_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.c deleted file mode 100644 index cf03afc1f814b2a693616a1f0df10c3cb96e0ba3..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_xrdc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define XRDC_DERR_W1_EST_VAL(w1) ((w1 & XRDC_DERR_W_EST_MASK) >> XRDC_DERR_W_EST_SHIFT) -#define XRDC_DERR_W1_EPORT_VAL(w1) ((w1 & XRDC_DERR_W_EPORT_MASK) >> XRDC_DERR_W_EPORT_SHIFT) -#define XRDC_DERR_W1_ERW_VAL(w1) ((w1 & XRDC_DERR_W_ERW_MASK) >> XRDC_DERR_W_ERW_SHIFT) -#define XRDC_DERR_W1_EATR_VAL(w1) ((w1 & XRDC_DERR_W_EATR_MASK) >> XRDC_DERR_W_EATR_SHIFT) -#define XRDC_DERR_W1_EDID_VAL(w1) ((w1 & XRDC_DERR_W_EDID_MASK) >> XRDC_DERR_W_EDID_SHIFT) - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP) -#define XRDC_MRGD_DXACP_WIDTH (3U) /* The width of XRDC_MRDG_DxACP. */ -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) -#define XRDC_MRGD_DXSEL_WIDTH (3U) /* The width of XRDC_MRDG_DxSEL. */ -#endif -#define XRDC_PDAC_DXACP_WIDTH (3U) /* The width of XRDC_PDAC_DxACP. */ - -/* For the force exclusive accesss lock release procedure. */ -#define XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1 (0x02000046U) /* The width of XRDC_MRDG_DxACP. */ -#define XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2 (0x02000052U) /* The width of XRDC_PDAC_DxACP. */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Clock name of XRDC. */ -#if (FSL_CLOCK_XRDC_GATE_COUNT > 1) -static const clock_ip_name_t s_xrdcClock[] = XRDC_CLOCKS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || defined(__riscv)) -/*! - * @brief Count the leading zeros. - * - * Count the leading zeros of an 32-bit data. This function is only defined - * for CM0 and CM0+ for IAR, because other cortex series have the clz instruction, - * KEIL and ARMGCC have toolchain build in function for this purpose. - * - * @param data The data to process. - * @return Count of the leading zeros. - */ -static uint32_t XRDC_CountLeadingZeros(uint32_t data) -{ - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count++; - mask >>= 1U; - } - - return count; -} -#endif - -void XRDC_Init(XRDC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - -#if FSL_CLOCK_XRDC_GATE_COUNT -#if (FSL_CLOCK_XRDC_GATE_COUNT == 1) - CLOCK_EnableClock(kCLOCK_Xrdc0); -#else - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(s_xrdcClock); i++) - { - CLOCK_EnableClock(s_xrdcClock[i]); - } -#endif -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XRDC_Deinit(XRDC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - -#if FSL_CLOCK_XRDC_GATE_COUNT -#if (FSL_CLOCK_XRDC_GATE_COUNT == 1) - CLOCK_EnableClock(kCLOCK_Xrdc0); -#else - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(s_xrdcClock); i++) - { - CLOCK_DisableClock(s_xrdcClock[i]); - } -#endif -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XRDC_GetHardwareConfig(XRDC_Type *base, xrdc_hardware_config_t *config) -{ - assert(config); - - config->masterNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMSTR_MASK) >> XRDC_HWCFG0_NMSTR_SHIFT) + 1U; - config->domainNumber = ((base->HWCFG0 & XRDC_HWCFG0_NDID_MASK) >> XRDC_HWCFG0_NDID_SHIFT) + 1U; - config->pacNumber = ((base->HWCFG0 & XRDC_HWCFG0_NPAC_MASK) >> XRDC_HWCFG0_NPAC_SHIFT) + 1U; - config->mrcNumber = ((base->HWCFG0 & XRDC_HWCFG0_NMRC_MASK) >> XRDC_HWCFG0_NMRC_SHIFT) + 1U; -} - -status_t XRDC_GetAndClearFirstDomainError(XRDC_Type *base, xrdc_error_t *error) -{ - return XRDC_GetAndClearFirstSpecificDomainError(base, error, XRDC_GetCurrentMasterDomainId(base)); -} - -status_t XRDC_GetAndClearFirstSpecificDomainError(XRDC_Type *base, xrdc_error_t *error, uint8_t domainId) -{ - assert(error); - - uint32_t errorBitMap; /* Domain error location bit map. */ - uint32_t errorIndex; /* The index of first domain error. */ - uint32_t regW1; /* To save XRDC_DERR_W1. */ - - /* Get the error bitmap. */ - errorBitMap = base->DERRLOC[domainId]; - - if (!errorBitMap) /* No error captured. */ - { - return kStatus_XRDC_NoError; - } - -/* Get the first error controller index. */ -#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || defined(__riscv)) - errorIndex = 31U - XRDC_CountLeadingZeros(errorBitMap); -#else - errorIndex = 31U - __CLZ(errorBitMap); -#endif - -#if (defined(FSL_FEATURE_XRDC_HAS_FDID) && FSL_FEATURE_XRDC_HAS_FDID) - /* Must write FDID[FDID] with the domain ID before reading the Domain Error registers. */ - base->FDID = XRDC_FDID_FDID(domainId); -#endif /* FSL_FEATURE_XRDC_HAS_FDID */ - /* Get the error information. */ - regW1 = base->DERR_W[errorIndex][1]; - error->controller = (xrdc_controller_t)errorIndex; - error->address = base->DERR_W[errorIndex][0]; - error->errorState = (xrdc_error_state_t)XRDC_DERR_W1_EST_VAL(regW1); - error->errorAttr = (xrdc_error_attr_t)XRDC_DERR_W1_EATR_VAL(regW1); - error->errorType = (xrdc_error_type_t)XRDC_DERR_W1_ERW_VAL(regW1); - error->errorPort = XRDC_DERR_W1_EPORT_VAL(regW1); - error->domainId = XRDC_DERR_W1_EDID_VAL(regW1); - - /* Clear error pending. */ - base->DERR_W[errorIndex][3] = XRDC_DERR_W_RECR(0x01U); - - return kStatus_Success; -} - -void XRDC_GetMemAccessDefaultConfig(xrdc_mem_access_config_t *config) -{ - assert(config); - - uint8_t i; - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE) - config->enableSema = false; - config->semaNum = 0U; -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */ - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ) - config->size = kXRDC_MemSizeNone; -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */ -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SRD) && FSL_FEATURE_XRDC_NO_MRGD_SRD) - config->subRegionDisableMask = 0U; -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SRD */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR) - config->codeRegion = kXRDC_MemCodeRegion0; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_CR */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) - config->enableAccset1Lock = false; - config->enableAccset2Lock = false; - config->accset1 = 0x000U; - config->accset2 = 0x000U; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */ - - config->lockMode = kXRDC_AccessConfigLockWritable; - - config->baseAddress = 0U; -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) - config->endAddress = 0U; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR */ - - for (i = 0U; i < FSL_FEATURE_XRDC_DOMAIN_COUNT; i++) - { -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP) - config->policy[i] = kXRDC_AccessPolicyNone; -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) - config->policy[i] = kXRDC_AccessFlagsNone; -#endif - } - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) - config->exclAccessLockMode = kXRDC_ExclAccessLockDisabled; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */ -} - -void XRDC_SetMemAccessConfig(XRDC_Type *base, const xrdc_mem_access_config_t *config) -{ - assert(config); -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ) - /* Not allowed to set sub-region disable mask for memory region smaller than 256-bytes. */ - assert(!((config->size < kXRDC_MemSize256B) && (config->subRegionDisableMask))); - /* Memory region minimum size = 32 bytes and base address must be aligned to 0-module-2**(SZ+1). */ - assert(config->size >= kXRDC_MemSize32B); - assert(!(config->baseAddress & ((1U << (config->size + 1U)) - 1U))); -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */ - - uint32_t i; - uint32_t regValue; - uint8_t index = (uint8_t)config->mem; - - /* Set MRGD_W0. */ - base->MRGD[index].MRGD_W[0] = config->baseAddress; - -/* Set MRGD_W1. */ -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ) - base->MRGD[index].MRGD_W[1] = XRDC_MRGD_W_SZ(config->size) | XRDC_MRGD_W_SRD(config->subRegionDisableMask); -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) - base->MRGD[index].MRGD_W[1] = config->endAddress; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR */ - - /* Set MRGD_W2. */ - regValue = 0U; -/* Set MRGD_W2[D0ACP ~ D7ACP] or MRGD_W2[D0SEL ~ D2SEL]. */ -#if (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 8U) - i = FSL_FEATURE_XRDC_DOMAIN_COUNT; -#elif(FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16U) - i = 8U; -#else -#error Does not support more than 16 domain. -#endif - - while (i--) - { -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP) - regValue <<= XRDC_MRGD_DXACP_WIDTH; -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) - regValue <<= XRDC_MRGD_DXSEL_WIDTH; -#endif - regValue |= config->policy[i]; - } - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE) - regValue |= XRDC_MRGD_W_SE(config->enableSema) | XRDC_MRGD_W_SNUM(config->semaNum); -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */ - - base->MRGD[index].MRGD_W[2] = regValue; - - /* Set MRGD_W3. */ - regValue = 0U; - -#if ((FSL_FEATURE_XRDC_DOMAIN_COUNT > 8U) && (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16)) - /* Set MRGD_W3[D8ACP ~ D15ACP]. */ - for (i = FSL_FEATURE_XRDC_DOMAIN_COUNT - 1U; i > 7U; i--) - { - regValue <<= XRDC_MRGD_DXACP_WIDTH; - regValue |= config->policy[i]; - } -#endif - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR) - regValue |= XRDC_MRGD_W_CR(config->codeRegion); -#endif - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) && FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) - regValue |= XRDC_MRGD_W_VLD_MASK | XRDC_MRGD_W_LK2(config->lockMode); -#endif - - base->MRGD[index].MRGD_W[3] = regValue; - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) - /* - * Set MRGD_W3[EAL]. - * If write with a value of MRGD_W3[EAL]=0, then the other fields of MRGD_W3 are updated. - * If write with a value of MRGD_W3[EAL]!=0, then only the EAL is updated. - */ - if (kXRDC_ExclAccessLockDisabled != config->exclAccessLockMode) - { - base->MRGD[index].MRGD_W[3] = XRDC_MRGD_W_EAL(config->exclAccessLockMode); - } -#endif - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) - /* Set MRGD_W4. */ - base->MRGD[index].MRGD_W[4] = XRDC_MRGD_W_LKAS1(config->enableAccset1Lock) | XRDC_MRGD_W_ACCSET1(config->accset1) | - XRDC_MRGD_W_LKAS2(config->enableAccset2Lock) | XRDC_MRGD_W_ACCSET2(config->accset2) | - XRDC_MRGD_W_VLD_MASK | XRDC_MRGD_W_LK2(config->lockMode); -#endif -} - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) -void XRDC_SetMemExclAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_excl_access_lock_config_t lockMode) -{ - /* Write kXRDC_ExclAccessLockDisabled is not allowed. */ - assert(kXRDC_ExclAccessLockDisabled != lockMode); - - uint32_t reg = base->MRGD[mem].MRGD_W[4]; - - /* Step 1. Set the memory region exclusive access lock mode configuration. */ - base->MRGD[mem].MRGD_W[3] = XRDC_MRGD_W_EAL(lockMode); - - /* Step 2. Set MRGD_W3 will clear the MRGD_W4[VLD]. So should re-assert it. */ - base->MRGD[mem].MRGD_W[4] = reg; -} - -void XRDC_ForceMemExclAccessLockRelease(XRDC_Type *base, xrdc_mem_t mem) -{ - uint32_t primask; - - primask = DisableGlobalIRQ(); - base->MRGD[mem].MRGD_W[3] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1; - base->MRGD[mem].MRGD_W[3] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2; - EnableGlobalIRQ(primask); -} -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) -void XRDC_SetMemAccsetLock(XRDC_Type *base, xrdc_mem_t mem, xrdc_mem_accset_t accset, bool lock) -{ - uint32_t lkasMask = 0U; - - switch (accset) - { - case kXRDC_MemAccset1: - lkasMask = XRDC_MRGD_W_LKAS1_MASK; - break; - case kXRDC_MemAccset2: - lkasMask = XRDC_MRGD_W_LKAS2_MASK; - break; - default: - break; - } - - if (lock) - { - base->MRGD[mem].MRGD_W[4] |= lkasMask; - } - else - { - base->MRGD[mem].MRGD_W[4] &= ~lkasMask; - } -} -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */ - -void XRDC_GetPeriphAccessDefaultConfig(xrdc_periph_access_config_t *config) -{ - assert(config); - - uint8_t i; - -#if !(defined(FSL_FEATURE_XRDC_NO_PDAC_SE) && FSL_FEATURE_XRDC_NO_PDAC_SE) - config->enableSema = false; - config->semaNum = 0U; -#endif /* FSL_FEATURE_XRDC_NO_PDAC_SE */ - config->lockMode = kXRDC_AccessConfigLockWritable; -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) - config->exclAccessLockMode = kXRDC_ExclAccessLockDisabled; -#endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */ - for (i = 0U; i < FSL_FEATURE_XRDC_DOMAIN_COUNT; i++) - { - config->policy[i] = kXRDC_AccessPolicyNone; - } -} - -void XRDC_SetPeriphAccessConfig(XRDC_Type *base, const xrdc_periph_access_config_t *config) -{ - assert(config); - - uint32_t i; - uint32_t regValue; - uint8_t index = (uint8_t)config->periph; - - /* Set PDAC_W0[D0ACP ~ D7ACP]. */ - regValue = 0U; -#if (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 8U) - i = FSL_FEATURE_XRDC_DOMAIN_COUNT; -#elif(FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16U) - i = 8U; -#else -#error Does not support more than 16 domain. -#endif - - while (i--) - { - regValue <<= XRDC_PDAC_DXACP_WIDTH; - regValue |= config->policy[i]; - } - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE) - regValue |= (XRDC_PDAC_W_SE(config->enableSema) | XRDC_PDAC_W_SNUM(config->semaNum)); -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SE */ - - /* Set PDAC_W0. */ - base->PDAC_W[index][0U] = regValue; - -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) - /* - * If write with a value of PDAC_W1[EAL]=0, then the other fields of PDAC_W1 are updated. - * If write with a value of PDAC_W1[EAL]!=0, then only the EAL is updated. - */ - base->PDAC_W[index][1U] = XRDC_PDAC_W_EAL(config->exclAccessLockMode); -#endif - - regValue = 0U; -#if ((FSL_FEATURE_XRDC_DOMAIN_COUNT > 8U) && (FSL_FEATURE_XRDC_DOMAIN_COUNT <= 16)) - /* Set PDAC_W1[D8ACP ~ D15ACP]. */ - - for (i = FSL_FEATURE_XRDC_DOMAIN_COUNT - 1U; i > 7U; i--) - { - regValue <<= XRDC_PDAC_DXACP_WIDTH; - regValue |= config->policy[i]; - } -#endif - /* Set PDAC_W1. */ - base->PDAC_W[index][1] = regValue | XRDC_PDAC_W_VLD_MASK | XRDC_PDAC_W_LK2(config->lockMode); -} - -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) -void XRDC_ForcePeriphExclAccessLockRelease(XRDC_Type *base, xrdc_periph_t periph) -{ - uint32_t primask; - - primask = DisableGlobalIRQ(); - base->PDAC_W[periph][1] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL1; - base->PDAC_W[periph][1] = XRDC_FORCE_EXCL_ACS_LOCK_REL_VAL2; - EnableGlobalIRQ(primask); -} -#endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.h deleted file mode 100644 index 2993847e18969e9fe5287d1ce9689a8a6a886cb9..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/fsl_xrdc.h +++ /dev/null @@ -1,1249 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_XRDC_H_ -#define _FSL_XRDC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup xrdc - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ -#define FSL_XRDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ - -#ifndef FSL_CLOCK_XRDC_GATE_COUNT -#define FSL_CLOCK_XRDC_GATE_COUNT 1U -#endif - -/*! @brief XRDC status. */ -enum _xrdc_status -{ - kStatus_XRDC_NoError = MAKE_STATUS(kStatusGroup_XRDC, 0) /*!< No error captured. */ -}; - -/*! - * @brief XRDC hardware configuration. - */ -typedef struct _xrdc_hardware_config -{ - uint8_t masterNumber; /*!< Number of bus masters. */ - uint8_t domainNumber; /*!< Number of domains. */ - uint8_t pacNumber; /*!< Number of PACs. */ - uint8_t mrcNumber; /*!< Number of MRCs. */ -} xrdc_hardware_config_t; - -/*! - * @brief XRDC PID enable mode, the register bit XRDC_MDA_Wx[PE], used for domain hit evaluation. - */ -typedef enum _xrdc_pid_enable -{ - kXRDC_PidDisable, /*!< PID is not used in domain hit evalution. */ - kXRDC_PidDisable1, /*!< PID is not used in domain hit evalution. */ - kXRDC_PidExp0, /*!< ((XRDC_MDA_W[PID] & ~XRDC_MDA_W[PIDM]) == (XRDC_PID[PID] & ~XRDC_MDA_W[PIDM])). */ - kXRDC_PidExp1 /*!< ~((XRDC_MDA_W[PID] & ~XRDC_MDA_W[PIDM]) == (XRDC_PID[PID] & ~XRDC_MDA_W[PIDM])). */ -} xrdc_pid_enable_t; - -/*! - * @brief XRDC domain ID select method, the register bit XRDC_MDA_Wx[DIDS], used for - * domain hit evaluation. - */ -typedef enum _xrdc_did_sel -{ - kXRDC_DidMda, /*!< Use MDAn[3:0] as DID. */ - kXRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */ - kXRDC_DidMdaAndInput, /*!< Use MDAn[3:2] concatenated with DID_in[1:0] as DID. */ - kXRDC_DidReserved /*!< Reserved. */ -} xrdc_did_sel_t; - -/*! - * @brief XRDC secure attribute, the register bit XRDC_MDA_Wx[SA], used for non-processor - * bus master domain assignment. - */ -typedef enum _xrdc_secure_attr -{ - kXRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */ - kXRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */ - kXRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */ - kXRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */ -} xrdc_secure_attr_t; - -/*! - * @brief XRDC privileged attribute, the register bit XRDC_MDA_Wx[PA], used for non-processor - * bus master domain assignment. - */ -typedef enum _xrdc_privilege_attr -{ - kXRDC_ForceUser, /*!< Force the bus attribute for this master to user. */ - kXRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */ - kXRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */ - kXRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */ -} xrdc_privilege_attr_t; - -/*! - * @brief Domain assignment for the processor bus master. - */ -typedef struct _xrdc_processor_domain_assignment -{ - uint32_t domainId : 4U; /*!< Domain ID. */ - uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref xrdc_did_sel_t. */ - uint32_t pidEnable : 2U; /*!< PId enable method, see @ref xrdc_pid_enable_t. */ - uint32_t pidMask : 6U; /*!< PId mask. */ - uint32_t : 2U; /*!< Reserved. */ - uint32_t pid : 6U; /*!< PId value. */ - uint32_t : 2U; /*!< Reserved. */ -#if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPID) && FSL_FEATURE_XRDC_NO_MDA_LPID) - uint32_t logicPartId : 4U; /*!< Logical partition ID. */ -#else - uint32_t : 4U; /*!< Reserved. */ -#endif -#if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPE) && FSL_FEATURE_XRDC_NO_MDA_LPE) - uint32_t enableLogicPartId : 1U; /*!< Logical partition ID. */ -#else - uint32_t : 1U; /*!< Reserved. */ -#endif /* FSL_FEATURE_XRDC_NO_MDA_LPE */ - uint32_t : 1U; /*!< Reserved. */ - uint32_t lock : 1U; /*!< Lock the register. */ - uint32_t : 1U; /*!< Reserved. */ -} xrdc_processor_domain_assignment_t; - -/*! - * @brief Domain assignment for the non-processor bus master. - */ -typedef struct _xrdc_non_processor_domain_assignment -{ - uint32_t domainId : 4U; /*!< Domain ID. */ - uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref xrdc_privilege_attr_t. */ - uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref xrdc_secure_attr_t. */ - uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */ - uint32_t : 15U; /*!< Reserved. */ -#if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPID) && FSL_FEATURE_XRDC_NO_MDA_LPID) - uint32_t logicPartId : 4U; /*!< Logical partition ID. */ -#else - uint32_t : 4U; /*!< Reserved. */ -#endif -#if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPE) && FSL_FEATURE_XRDC_NO_MDA_LPE) - uint32_t enableLogicPartId : 1U; /*!< Enable logical partition ID. */ -#else - uint32_t : 1U; /*!< Reserved. */ -#endif - uint32_t : 1U; /*!< Reserved. */ - uint32_t lock : 1U; /*!< Lock the register. */ - uint32_t : 1U; /*!< Reserved. */ -} xrdc_non_processor_domain_assignment_t; - -/*! - * @brief XRDC PID LK2 definition XRDC_PIDn[LK2] - */ -typedef enum _xrdc_pid_lock -{ - kXRDC_PidLockSecurePrivilegeWritable = 0U, /*!< Writable by any secure privileged write. */ - kXRDC_PidLockSecurePrivilegeWritable1 = 1U, /*!< Writable by any secure privileged write. */ - kXRDC_PidLockMasterXOnly = 2U, /*!< PIDx is only writable by master x. */ - kXRDC_PidLockLocked = 3U /*!< Read-only until the next reset. */ -} xrdc_pid_lock_t; - -/*! - * @brief XRDC process identifier (PID) configuration. - */ -typedef struct _xrdc_pid_config -{ - uint32_t pid : 6U; /*!< PID value, PIDn[PID]. */ -#if (defined(FSL_FEATURE_XRDC_HAS_PID_SP4SM) && FSL_FEATURE_XRDC_HAS_PID_SP4SM) - uint32_t : 21U; /*!< Reserved. */ - uint32_t sp4smEnable : 1U; /*!< Enable special 4-state model. */ -#else - uint32_t : 22U; /*!< Reserved. */ -#endif - uint32_t tsmEnable : 1U; /*!< Enable three-state model. */ - uint32_t lockMode : 2U; /*!< PIDn configuration lock mode, see @ref xrdc_pid_lock_t. */ - uint32_t : 1U; /*!< Reserved. */ -} xrdc_pid_config_t; - -/*! - * @brief XRDC domain access control policy. - */ -typedef enum _xrdc_access_policy -{ - /* policy SecurePriv SecureUser NonSecurePriv NonSecureUsr*/ - kXRDC_AccessPolicyNone = 0U, /* 000 none none none none */ - kXRDC_AccessPolicySpuR = 1U, /* 001 r r none none */ - kXRDC_AccessPolicySpRw = 2U, /* 010 r,w none none none */ - kXRDC_AccessPolicySpuRw = 3U, /* 011 r,w r,w none none */ - kXRDC_AccessPolicySpuRwNpR = 4U, /* 100 r,w r,w r none */ - kXRDC_AccessPolicySpuRwNpuR = 5U, /* 101 r,w r,w r r */ - kXRDC_AccessPolicySpuRwNpRw = 6U, /* 110 r,w r,w r,w none */ - kXRDC_AccessPolicyAll = 7U /* 111 r,w r,w r,w r,w */ -} xrdc_access_policy_t; - -/*! - * @brief Access configuration lock mode, the register field PDAC and MRGD LK2. - */ -typedef enum _xrdc_access_config_lock -{ - kXRDC_AccessConfigLockWritable = 0U, /*!< Entire PDACn/MRGDn can be written. */ - kXRDC_AccessConfigLockWritable1 = 1U, /*!< Entire PDACn/MRGDn can be written. */ - kXRDC_AccessConfigLockDomainXOnly = 2U, /*!< Domain x only write the DxACP field. */ - kXRDC_AccessConfigLockLocked = 3U /*!< PDACn is read-only until the next reset. */ -} xrdc_access_config_lock_t; - -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) || \ - (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) -/*! - * @brief Exclusive access lock mode configuration, the register field PDAC and MRGD EAL. - */ -typedef enum _xrdc_excl_access_lock_config -{ - kXRDC_ExclAccessLockDisabled = 0U, /*!< Lock disabled. */ - kXRDC_ExclAccessLockDisabledUntilNextRst = 1U, /*!< Lock disabled until next reset. */ - kXRDC_ExclAccessLockEnabledStateAvail = 2U, /*!< Lock enabled, lock state = available. */ - kXRDC_ExclAccessLockEnabledStateNotAvail = 3U /*!< Lock enabled, lock state = not available. */ -} xrdc_excl_access_lock_config_t; -#endif - -/*! - * @brief XRDC peripheral domain access control configuration. - */ -typedef struct _xrdc_periph_access_config -{ - xrdc_periph_t periph; /*!< Peripheral name. */ - xrdc_access_config_lock_t lockMode; /*!< PDACn lock configuration. */ -#if !(defined(FSL_FEATURE_XRDC_NO_PDAC_SE) && FSL_FEATURE_XRDC_NO_PDAC_SE) - bool enableSema; /*!< Enable semaphore or not. */ - uint32_t semaNum; /*!< Semaphore number. */ -#endif -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) - xrdc_excl_access_lock_config_t exclAccessLockMode; /*!< Exclusive access lock configuration. */ -#endif - xrdc_access_policy_t policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy for each domain. */ -} xrdc_periph_access_config_t; - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ) -/*! - * @brief XRDC memory size definition. - */ -typedef enum _xrdc_mem_size -{ - kXRDC_MemSizeNone = 0U, /*!< None size. */ - kXRDC_MemSize32B = 4U, /*!< 2^(4+1) = 32 */ - kXRDC_MemSize64B = 5U, /*!< 2^(5+1) = 64 */ - kXRDC_MemSize128B = 6U, /*!< 2^(6+1) = 128 */ - kXRDC_MemSize256B = 7U, /*!< 2^(7+1) = 256 */ - kXRDC_MemSize512B = 8U, /*!< 2^(8+1) = 512 */ - kXRDC_MemSize1K = 9U, /*!< 2^(9+1) = 1kB */ - kXRDC_MemSize2K = 10U, /*!< 2^(10+1) = 2kB */ - kXRDC_MemSize4K = 11U, /*!< 2^(11+1) = 4kB */ - kXRDC_MemSize8K = 12U, /*!< 2^(12+1) = 8kB */ - kXRDC_MemSize16K = 13U, /*!< 2^(13+1) = 16kB */ - kXRDC_MemSize32K = 14U, /*!< 2^(14+1) = 32kB */ - kXRDC_MemSize64K = 15U, /*!< 2^(15+1) = 64kB */ - kXRDC_MemSize128K = 16U, /*!< 2^(16+1) = 128kB */ - kXRDC_MemSize256K = 17U, /*!< 2^(17+1) = 256kB */ - kXRDC_MemSize512K = 18U, /*!< 2^(18+1) = 512kB */ - kXRDC_MemSize1M = 19U, /*!< 2^(19+1) = 1MB */ - kXRDC_MemSize2M = 20U, /*!< 2^(20+1) = 2MB */ - kXRDC_MemSize4M = 21U, /*!< 2^(21+1) = 4MB */ - kXRDC_MemSize8M = 22U, /*!< 2^(22+1) = 8MB */ - kXRDC_MemSize16M = 23U, /*!< 2^(23+1) = 16MB */ - kXRDC_MemSize32M = 24U, /*!< 2^(24+1) = 32MB */ - kXRDC_MemSize64M = 25U, /*!< 2^(25+1) = 64MB */ - kXRDC_MemSize128M = 26U, /*!< 2^(26+1) = 128MB */ - kXRDC_MemSize256M = 27U, /*!< 2^(27+1) = 256MB */ - kXRDC_MemSize512M = 28U, /*!< 2^(28+1) = 512MB */ - kXRDC_MemSize1G = 29U, /*!< 2^(29+1) = 1GB */ - kXRDC_MemSize2G = 30U, /*!< 2^(30+1) = 2GB */ - kXRDC_MemSize4G = 31U /*!< 2^(31+1) = 4GB */ -} xrdc_mem_size_t; -#endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) -/*! - * @brief XRDC memory ACCSET (SET of programmable access flags). - */ -typedef enum _xrdc_mem_accset -{ - kXRDC_MemAccset1 = 0U, /*!< Memory region SET 1 of programmable access flags. */ - kXRDC_MemAccset2 = 1U, /*!< Memory region SET 2 of programmable access flags. */ -} xrdc_mem_accset_t; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR) -/*! - * @brief XRDC memory code region indicator. - */ -typedef enum _xrdc_mem_code_region -{ - kXRDC_MemCodeRegion0 = 0U, /*!< Code region indicator 0=data. */ - kXRDC_MemCodeRegion1 = 1U, /*!< Code region indicator 1=code. */ -} xrdc_mem_code_region_t; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_CR */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) -/*! - * @brief XRDC domain access flags/policy select. - * - * Policy: - * {R,W,X} Read, write, execute flags. - * flag = 0 : inhibits access, flag = 1 : allows access. - * policy => SecurePriv_NonSecurePriv_SecureUser_NonSecureUsr - * xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X} - * - * PS > PN > US > UN PS > PN > US > UN - * DxSEL CodeRegion = 0 CodeRegion = 1 - * 000 000_000_000_000 = 0x000 000_000_000_000 = 0x000 - * 001 ACCSET1 - * 010 ACCSET2 - * 011 110_000_000_000 = 0xC00 001_001_001_001 = 0x249 - * 100 110_110_000_000 = 0xD80 111_000_000_000 = 0xE00 - * 101 110_110_100_100 = 0xDA4 110_111_000_000 = 0xDC0 - * 110 110_110_110_000 = 0xDB0 110_110_111_000 = 0xDB8 - * 111 110_110_110_110 = 0xDB6 110_110_111_111 = 0xDBF - */ -typedef enum _xrdc_access_flags_select -{ - kXRDC_AccessFlagsNone = 0U, /* Select predefined constant {r,w,x} flags. See the table above. */ - kXRDC_AccessFlagsAlt1 = 1U, /* Select ACCSET1 4*{r,w,x} fully‐programmable access flags. */ - kXRDC_AccessFlagsAlt2 = 2U, /* Select ACCSET2 4*{r,w,x} fully‐programmable access flags. */ - kXRDC_AccessFlagsAlt3 = 3U, /* Select predefined constant {r,w,x} flags. See the table above. */ - kXRDC_AccessFlagsAlt4 = 4U, /* Select predefined constant {r,w,x} flags. See the table above. */ - kXRDC_AccessFlagsAlt5 = 5U, /* Select predefined constant {r,w,x} flags. See the table above. */ - kXRDC_AccessFlagsAlt6 = 6U, /* Select predefined constant {r,w,x} flags. See the table above. */ - kXRDC_AccessFlagsAlt7 = 7U /* Select predefined constant {r,w,x} flags. See the table above. */ -} xrdc_access_flags_select_t; -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_DXSEL */ - -/*! - * @brief XRDC memory region domain access control configuration. - */ -typedef struct _xrdc_mem_access_config -{ - xrdc_mem_t mem; /*!< Memory region descriptor name. */ -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE) - bool enableSema; /*!< Enable semaphore or not. */ - uint8_t semaNum; /*!< Semaphore number. */ -#endif -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ) - xrdc_mem_size_t size; /*!< Memory region size. */ -#endif -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SRD) && FSL_FEATURE_XRDC_NO_MRGD_SRD) - uint8_t subRegionDisableMask; /*!< Sub-region disable mask. */ -#endif - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) - bool enableAccset1Lock; /*!< Enable ACCSET1 access lock or not. */ - bool enableAccset2Lock; /*!< Enable ACCSET2 access lock or not. */ - uint16_t accset1; /*!< SET 1 of Programmable access flags. - xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X}. - flag = 0 : inhibits access, flag = 1 : allows access. */ - uint16_t accset2; /*!< SET 2 of Programmable access flags. - xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X}. - flag = 0 : inhibits access, flag = 1 : allows access. */ -#endif - xrdc_access_config_lock_t lockMode; /*!< MRGDn lock configuration. */ - -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP) - xrdc_access_policy_t policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy for each domain. */ -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) - xrdc_access_flags_select_t - policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy/flags select for each domain. */ -#endif - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR) - xrdc_mem_code_region_t codeRegion; /*!< Code region select. @ref xrdc_mem_code_region_t. */ -#endif - - uint32_t baseAddress; /*!< Memory region base/start address. */ -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) - uint32_t endAddress; /*!< Memory region end address. The 5 LSB of end address - is ignored and forced to 0x1F by hardware. */ -#endif -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) - xrdc_excl_access_lock_config_t exclAccessLockMode; /*!< Exclusive access lock configuration. */ -#endif -} xrdc_mem_access_config_t; - -/*! - * @brief XRDC controller definition for domain error check. - */ -typedef enum _xrdc_controller -{ - kXRDC_MemController0 = 0U, /*!< Memory region controller 0. */ - kXRDC_MemController1 = 1U, /*!< Memory region controller 1. */ - kXRDC_MemController2 = 2U, /*!< Memory region controller 2. */ - kXRDC_MemController3 = 3U, /*!< Memory region controller 3. */ - kXRDC_MemController4 = 4U, /*!< Memory region controller 4. */ - kXRDC_MemController5 = 5U, /*!< Memory region controller 5. */ - kXRDC_MemController6 = 6U, /*!< Memory region controller 6. */ - kXRDC_MemController7 = 7U, /*!< Memory region controller 7. */ - kXRDC_MemController8 = 8U, /*!< Memory region controller 8. */ - kXRDC_MemController9 = 9U, /*!< Memory region controller 9. */ - kXRDC_MemController10 = 10U, /*!< Memory region controller 10. */ - kXRDC_MemController11 = 11U, /*!< Memory region controller 11. */ - kXRDC_MemController12 = 12U, /*!< Memory region controller 12. */ - kXRDC_MemController13 = 13U, /*!< Memory region controller 13. */ - kXRDC_MemController14 = 14U, /*!< Memory region controller 14. */ - kXRDC_MemController15 = 15U, /*!< Memory region controller 15. */ - kXRDC_PeriphController0 = 16U, /*!< Peripheral access controller 0. */ - kXRDC_PeriphController1 = 17U, /*!< Peripheral access controller 1. */ - kXRDC_PeriphController2 = 18U, /*!< Peripheral access controller 2. */ - kXRDC_PeriphController3 = 19U, /*!< Peripheral access controller 3. */ -} xrdc_controller_t; - -/*! - * @brief XRDC domain error state definition XRDC_DERR_W1_n[EST]. - */ -typedef enum _xrdc_error_state -{ - kXRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */ - kXRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */ - kXRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */ - kXRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */ -} xrdc_error_state_t; - -/*! - * @brief XRDC domain error attribute definition XRDC_DERR_W1_n[EATR]. - */ -typedef enum _xrdc_error_attr -{ - kXRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */ - kXRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */ - kXRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */ - kXRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */ - kXRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */ - kXRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */ - kXRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */ - kXRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */ -} xrdc_error_attr_t; - -/*! - * @brief XRDC domain error access type definition XRDC_DERR_W1_n[ERW]. - */ -typedef enum _xrdc_error_type -{ - kXRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */ - kXRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */ -} xrdc_error_type_t; - -/*! - * @brief XRDC domain error definition. - */ -typedef struct _xrdc_error -{ - xrdc_controller_t controller; /*!< Which controller captured access violation. */ - uint32_t address; /*!< Access address that generated access violation. */ - xrdc_error_state_t errorState; /*!< Error state. */ - xrdc_error_attr_t errorAttr; /*!< Error attribute. */ - xrdc_error_type_t errorType; /*!< Error type. */ - uint8_t errorPort; /*!< Error port. */ - uint8_t domainId; /*!< Domain ID. */ -} xrdc_error_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the XRDC module. - * - * This function enables the XRDC clock. - * - * @param base XRDC peripheral base address. - */ -void XRDC_Init(XRDC_Type *base); - -/*! - * @brief De-initializes the XRDC module. - * - * This function disables the XRDC clock. - * - * @param base XRDC peripheral base address. - */ -void XRDC_Deinit(XRDC_Type *base); - -/*! - * @name XRDC manager (XRDC_MGR) - * @{ - */ - -/*! - * @brief Gets the XRDC hardware configuration. - * - * This function gets the XRDC hardware configurations, including number of bus - * masters, number of domains, number of MRCs and number of PACs. - * - * @param base XRDC peripheral base address. - * @param config Pointer to the structure to get the configuration. - */ -void XRDC_GetHardwareConfig(XRDC_Type *base, xrdc_hardware_config_t *config); - -/*! - * @brief Locks the XRDC global control register XRDC_CR. - * - * This function locks the XRDC_CR register. After it is locked, the register is - * read-only until the next reset. - * - * @param base XRDC peripheral base address. - */ -static inline void XRDC_LockGlobalControl(XRDC_Type *base) -{ - base->CR |= XRDC_CR_LK1_MASK; -} - -/*! - * @brief Sets the XRDC global valid. - * - * This function sets the XRDC global valid or invalid. When the XRDC is global - * invalid, all accesses from all bus masters to all slaves are allowed. - * - * @param base XRDC peripheral base address. - * @param valid True to valid XRDC. - */ -static inline void XRDC_SetGlobalValid(XRDC_Type *base, bool valid) -{ - if (valid) - { -#if (defined(FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) && FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) - base->CR |= (XRDC_CR_GVLDM_MASK | XRDC_CR_GVLDC_MASK | XRDC_CR_GVLDP_MASK); -#else - base->CR |= XRDC_CR_GVLD_MASK; -#endif - } - else - { -#if (defined(FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) && FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) - base->CR &= ~(XRDC_CR_GVLDM_MASK | XRDC_CR_GVLDC_MASK | XRDC_CR_GVLDP_MASK); -#else - base->CR &= ~XRDC_CR_GVLD_MASK; -#endif - } -} - -/*! - * @brief Gets the domain ID of the current bus master. - * - * This function returns the domain ID of the current bus master. - * - * @param base XRDC peripheral base address. - * @return Domain ID of current bus master. - */ -static inline uint8_t XRDC_GetCurrentMasterDomainId(XRDC_Type *base) -{ - return (uint8_t)((base->HWCFG1 & XRDC_HWCFG1_DID_MASK) >> XRDC_HWCFG1_DID_SHIFT); -} - -/*! - * @brief Gets and clears the first domain error of the current domain. - * - * This function gets the first access violation information for the current domain - * and clears the pending flag. There might be multiple access violations pending - * for the current domain. This function only processes the first error. - * - * @param base XRDC peripheral base address. - * @param error Pointer to the error information. - * @return If the access violation is captured, this function returns the kStatus_Success. - * The error information can be obtained from the parameter error. If no - * access violation is captured, this function returns the kStatus_XRDC_NoError. - */ -status_t XRDC_GetAndClearFirstDomainError(XRDC_Type *base, xrdc_error_t *error); - -/*! - * @brief Gets and clears the first domain error of the specific domain. - * - * This function gets the first access violation information for the specific domain - * and clears the pending flag. There might be multiple access violations pending - * for the current domain. This function only processes the first error. - * - * @param base XRDC peripheral base address. - * @param error Pointer to the error information. - * @param domainId The error of which domain to get and clear. - * @return If the access violation is captured, this function returns the kStatus_Success. - * The error information can be obtained from the parameter error. If no - * access violation is captured, this function returns the kStatus_XRDC_NoError. - */ -status_t XRDC_GetAndClearFirstSpecificDomainError(XRDC_Type *base, xrdc_error_t *error, uint8_t domainId); - -/*@}*/ - -/*! - * @name XRDC Master Domain Assignment Controller (XRDC_MDAC). - * @{ - */ - -/*! - * @brief Gets the default PID configuration structure. - * - * This function initializes the configuration structure to default values. The default - * values are: - * - * @code - * config->pid = 0U; - * config->tsmEnable = 0U; - * config->sp4smEnable = 0U; - * config->lockMode = kXRDC_PidLockSecurePrivilegeWritable; - * @endcode - * - * @param config Pointer to the configuration structure. - */ -static inline void XRDC_GetPidDefaultConfig(xrdc_pid_config_t *config) -{ - assert(config); - - (*((uint32_t *)config)) = 0U; -} - -/*! - * @brief Configures the PID for a specific bus master. - * - * This function configures the PID for a specific bus master. Do not use this - * function for non-processor bus masters. - * - * @param base XRDC peripheral base address. - * @param master Which bus master to configure. - * @param config Pointer to the configuration structure. - */ -static inline void XRDC_SetPidConfig(XRDC_Type *base, xrdc_master_t master, const xrdc_pid_config_t *config) -{ - assert(config); - - base->PID[master] = *((const uint32_t *)config); -} - -/*! - * @brief Sets the PID configuration register lock mode. - * - * This function sets the PID configuration register lock XRDC_PIDn[LK2]. - * - * @param base XRDC peripheral base address. - * @param master Which master's PID to lock. - * @param lockMode Lock mode to set. - */ -static inline void XRDC_SetPidLockMode(XRDC_Type *base, xrdc_master_t master, xrdc_pid_lock_t lockMode) -{ - uint32_t reg = base->PID[master]; - - reg = ((reg & ~XRDC_PID_LK2_MASK) | XRDC_PID_LK2(lockMode)); - - base->PID[master] = reg; -} - -/*! - * @brief Gets the default master domain assignment for non-processor bus master. - * - * This function gets the default master domain assignment for non-processor bus master. - * It should only be used for the no-processor bus masters, such as DMA. This function - * sets the assignment as follows: - * - * @code - * assignment->domainId = 0U; - * assignment->privilegeAttr = kXRDC_ForceUser; - * assignment->privilegeAttr = kXRDC_ForceSecure; - * assignment->bypassDomainId = 0U; - * assignment->blogicPartId = 0U; - * assignment->benableLogicPartId = 0U; - * assignment->lock = 0U; - * @endcode - * - * @param assignment Pointer to the assignment structure. - */ -static inline void XRDC_GetDefaultNonProcessorDomainAssignment(xrdc_non_processor_domain_assignment_t *assignment) -{ - assert(assignment); - - *(uint32_t *)assignment = 0U; -} - -/*! - * @brief Gets the default master domain assignment for the processor bus master. - * - * This function gets the default master domain assignment for the processor bus master. - * It should only be used for the processor bus masters, such as CORE0. This function - * sets the assignment as follows: - * - * @code - * assignment->domainId = 0U; - * assignment->domainIdSelect = kXRDC_DidMda; - * assignment->dpidEnable = kXRDC_PidDisable; - * assignment->pidMask = 0U; - * assignment->pid = 0U; - * assignment->logicPartId = 0U; - * assignment->enableLogicPartId = 0U; - * assignment->lock = 0U; - * @endcode - * - * @param assignment Pointer to the assignment structure. - */ -static inline void XRDC_GetDefaultProcessorDomainAssignment(xrdc_processor_domain_assignment_t *assignment) -{ - assert(assignment); - - *(uint32_t *)assignment = 0U; -} - -/*! - * @brief Sets the non-processor bus master domain assignment. - * - * This function sets the non-processor master domain assignment as valid. - * One bus master might have multiple domain assignment registers. The parameter - * \p assignIndex specifies which assignment register to set. - * - * Example: Set domain assignment for DMA0. - * @code - * xrdc_non_processor_domain_assignment_t nonProcessorAssignment; - * - * XRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); // Get default assignment - * // Modify necessary members. - * nonProcessorAssignment.domainId = 1; - * nonProcessorAssignment.xxx = xxx; // Other modifications. - * - * // Set the domain assignment. Only 1 assignment register for DMA0. Pass in 0U as assignIndex; - * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterDma0, 0U, &nonProcessorAssignment); - * @endcode - * - * @param base XRDC peripheral base address. - * @param master Which master to configure. - * @param assignIndex Which assignment register to set. - * @param assignment Pointer to the assignment structure. - */ -static inline void XRDC_SetNonProcessorDomainAssignment(XRDC_Type *base, - xrdc_master_t master, - uint8_t assignIndex, - const xrdc_non_processor_domain_assignment_t *assignment) -{ - /* Make sure the master is a non-CPU/non-processor master */ - assert(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK); - /* Make sure the master has the assignment register. */ - assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); - assert(assignment); - - base->MDA[master].MDA_W[assignIndex] = ((*(const uint32_t *)assignment) | XRDC_MDA_W_VLD_MASK); -} - -/*! - * @brief Sets the processor bus master domain assignment. - * - * This function sets the processor master domain assignment as valid. - * One bus master might have multiple domain assignment registers. The parameter - * \p assignIndex specifies which assignment register to set. - * - * Example: Set domain assignment for core 0. - * @code - * xrdc_processor_domain_assignment_t processorAssignment; - * - * XRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); // Get default assignment - * - * // Set the domain assignment. There are 3 assignment registers for core 0. - * // Set assignment register 0. - * processorAssignment.domainId = 1; - * processorAssignment.xxx = xxx; // Other modifications. - * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 0U, &processorAssignment); - * - * // Set assignment register 1. - * processorAssignment.domainId = 2; - * processorAssignment.xxx = xxx; // Other modifications. - * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 1U, &processorAssignment); - * - * // Set assignment register 2. - * processorAssignment.domainId = 0; - * processorAssignment.xxx = xxx; // Other modifications. - * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 2U, &processorAssignment); - * @endcode - * - * @param base XRDC peripheral base address. - * @param master Which master to configure. - * @param assignIndex Which assignment register to set. - * @param assignment Pointer to the assignment structure. - */ -static inline void XRDC_SetProcessorDomainAssignment(XRDC_Type *base, - xrdc_master_t master, - uint8_t assignIndex, - const xrdc_processor_domain_assignment_t *assignment) -{ - /* Make sure the master is a CPU/processor master */ - assert(!(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK)); - /* Make sure the master has the assignment register. */ - assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); - assert(assignment); - - base->MDA[master].MDA_W[assignIndex] = ((*(const uint32_t *)assignment) | XRDC_MDA_W_VLD_MASK); -} - -/*! - * @brief Locks the bus master domain assignment register. - * - * This function locks the master domain assignment. One bus master might have - * multiple domain assignment registers. The parameter \p assignIndex specifies - * which assignment register to lock. After it is locked, the register can't be changed - * until next reset. - * - * @param base XRDC peripheral base address. - * @param master Which master to configure. - * @param assignIndex Which assignment register to lock. - */ -static inline void XRDC_LockMasterDomainAssignment(XRDC_Type *base, xrdc_master_t master, uint8_t assignIndex) -{ - /* Make sure the master has the assignment register. */ - assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); - - base->MDA[master].MDA_W[assignIndex] |= XRDC_MDA_W_LK1_MASK; -} - -/*! - * @brief Sets the master domain assignment as valid or invalid. - * - * This function sets the master domain assignment as valid or invalid. One bus master might have - * multiple domain assignment registers. The parameter \p assignIndex specifies - * which assignment register to configure. - * - * @param base XRDC peripheral base address. - * @param master Which master to configure. - * @param assignIndex Index for the domain assignment register. - * @param valid True to set valid, false to set invalid. - */ -static inline void XRDC_SetMasterDomainAssignmentValid(XRDC_Type *base, - xrdc_master_t master, - uint8_t assignIndex, - bool valid) -{ - /* Make sure the master has the assignment register. */ - assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); - - if (valid) - { - base->MDA[master].MDA_W[assignIndex] |= XRDC_MDA_W_VLD_MASK; - } - else - { - base->MDA[master].MDA_W[assignIndex] &= ~XRDC_MDA_W_VLD_MASK; - } -} - -/*@}*/ - -/*! - * @name XRDC Memory Region Controller (XRDC_MRC) - * @{ - */ - -/*! - * @brief Gets the default memory region access policy. - * - * This function gets the default memory region access policy. - * It sets the policy as follows: - * @code - * config->enableSema = false; - * config->semaNum = 0U; - * config->subRegionDisableMask = 0U; - * config->size = kXrdcMemSizeNone; - * config->lockMode = kXRDC_AccessConfigLockWritable; - * config->baseAddress = 0U; - * config->policy[0] = kXRDC_AccessPolicyNone; - * config->policy[1] = kXRDC_AccessPolicyNone; - * ... - * config->policy[15] = kXRDC_AccessPolicyNone; - * @endcode - * - * @param config Pointer to the configuration structure. - */ -void XRDC_GetMemAccessDefaultConfig(xrdc_mem_access_config_t *config); - -/*! - * @brief Sets the memory region access policy. - * - * This function sets the memory region access configuration as valid. - * There are two methods to use it: - * - * Example 1: Set one configuration run time. - * @code - * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1. - * xrdc_mem_access_config_t config = - * { - * .mem = kXRDC_MemMrc0_1, - * .baseAddress = 0x20000000U, - * .size = kXRDC_MemSize1K, - * .policy[0] = kXRDC_AccessPolicyAll - * }; - * XRDC_SetMemAccessConfig(XRDC, &config); - * @endcode - * - * Example 2: Set multiple configurations during startup. - * @code - * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1. - * // Set memory region 0x1FFF0000 ~ 0x1FFF0800 accessible by domain 0, use MRC0_2. - * xrdc_mem_access_config_t configs[] = - * { - * { - * .mem = kXRDC_MemMrc0_1, - * .baseAddress = 0x20000000U, - * .size = kXRDC_MemSize1K, - * .policy[0] = kXRDC_AccessPolicyAll - * }, - * { - * .mem = kXRDC_MemMrc0_2, - * .baseAddress = 0x1FFF0000U, - * .size = kXRDC_MemSize2K, - * .policy[0] = kXRDC_AccessPolicyAll - * } - * }; - * - * // Set the configurations. - * for (i=0U; i<((sizeof(configs)/sizeof(configs[0]))); i++) - * { - * XRDC_SetMemAccessConfig(XRDC, &configs[i]); - * } - * @endcode - * - * @param base XRDC peripheral base address. - * @param config Pointer to the access policy configuration structure. - */ -void XRDC_SetMemAccessConfig(XRDC_Type *base, const xrdc_mem_access_config_t *config); - -/*! - * @brief Sets the memory region descriptor register lock mode. - * - * @param base XRDC peripheral base address. - * @param mem Which memory region descriptor to lock. - * @param lockMode The lock mode to set. - */ -static inline void XRDC_SetMemAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_access_config_lock_t lockMode) -{ -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_LK2) && FSL_FEATURE_XRDC_NO_MRGD_W3_LK2) - uint32_t reg = base->MRGD[mem].MRGD_W[3]; - - reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode)); - - base->MRGD[mem].MRGD_W[3] = reg; -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2) && FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2) - uint32_t reg = base->MRGD[mem].MRGD_W[4]; - - reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode)); - - base->MRGD[mem].MRGD_W[4] = reg; -#endif -} - -/*! - * @brief Sets the memory region descriptor as valid or invalid. - * - * This function sets the memory region access configuration dynamically. For example: - * - * @code - * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1. - * xrdc_mem_access_config_t config = - * { - * .mem = kXRDC_MemMrc0_1, - * .baseAddress = 0x20000000U, - * .size = kXRDC_MemSize1K, - * .policy[0] = kXRDC_AccessPolicyAll - * }; - * XRDC_SetMemAccessConfig(XRDC, &config); - * - * // Set the memory access configuration invalid. - * XRDC_SetMemAccessValid(kXRDC_MemMrc0_1, false); - * - * // Set the memory access configuration valid, the region 0x20000000 ~ 0x20000400 accessible by domain 0 - * XRDC_SetMemAccessValid(kXRDC_MemMrc0_1, true); - * @endcode - * - * @param base XRDC peripheral base address. - * @param mem Which memory region descriptor to set. - * @param valid True to set valid, false to set invalid. - */ -static inline void XRDC_SetMemAccessValid(XRDC_Type *base, xrdc_mem_t mem, bool valid) -{ -#if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) && FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) - if (valid) - { - base->MRGD[mem].MRGD_W[3] |= XRDC_MRGD_W_VLD_MASK; - } - else - { - base->MRGD[mem].MRGD_W[3] &= ~XRDC_MRGD_W_VLD_MASK; - } -#elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD) && FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD) - if (valid) - { - base->MRGD[mem].MRGD_W[4] |= XRDC_MRGD_W_VLD_MASK; - } - else - { - base->MRGD[mem].MRGD_W[4] &= ~XRDC_MRGD_W_VLD_MASK; - } -#endif -} - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL) -/*! - * @brief Sets the memory region exclusive access lock mode configuration. - * - * Note: Any write to MRGD_W[0-3]_n clears the MRGD_W4_n[VLD] indicator so a coherent register state can be supported. - * It is indispensable to re-assert the valid bit when dynamically changing the EAL in the MRGD, which is done in - * this API. - * - * @param base XRDC peripheral base address. - * @param mem Which memory region's exclusive access lock mode to configure. - * @param lockMode The exclusive access lock mode to set. - */ -void XRDC_SetMemExclAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_excl_access_lock_config_t lockMode); - -/*! - * @brief Forces the release of the memory region exclusive access lock. - * - * A lock can be forced to the available state (EAL=10) by a domain that does not own the - * lock through the forced lock release procedure: - * The procedure to force a exclusive access lock release is as follows: - * 1. Write 0x02000046 to W1 register (PAC/MSC) or W3 register (MRC) - * 2. Write 0x02000052 to W1 register (PAC/MSC) or W3 register (MRC) - * - * Note: The two writes must be consecutive, any intervening write to the register resets the sequence. - * - * @param base XRDC peripheral base address. - * @param mem Which memory region's exclusive access lock to force release. - */ -void XRDC_ForceMemExclAccessLockRelease(XRDC_Type *base, xrdc_mem_t mem); - -/*! - * @brief Gets the exclusive access lock domain owner of the memory region. - * - * This function returns the domain ID of the exclusive access lock owner of the memory region. - * - * @param base XRDC peripheral base address. - * @param mem Which memory region's exclusive access lock domain owner to get. - * @return Domain ID of the memory region exclusive access lock owner. - */ -static inline uint8_t XRDC_GetMemExclAccessLockDomainOwner(XRDC_Type *base, xrdc_mem_t mem) -{ - return (uint8_t)((base->MRGD[mem].MRGD_W[2U] & XRDC_MRGD_W_EALO_MASK) >> XRDC_MRGD_W_EALO_SHIFT); -} -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */ - -#if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) -/*! - * @brief Sets the memory region ACCSET (programmable access flags) lock. - * - * @param base XRDC peripheral base address. - * @param mem Which memory region descriptor to lock. - * @param mem Which set/index of ACCSET to lock. - * @param lock True to set lock, false to set unlock. - */ -void XRDC_SetMemAccsetLock(XRDC_Type *base, xrdc_mem_t mem, xrdc_mem_accset_t accset, bool lock); -#endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */ - -/*@}*/ - -/*! - * @name XRDC Peripheral Access Controller (XRDC_PAC) - * @{ - */ - -/*! - * @brief Gets the default peripheral access configuration. - * - * The default configuration is set as follows: - * @code - * config->enableSema = false; - * config->semaNum = 0U; - * config->lockMode = kXRDC_AccessConfigLockWritable; - * config->policy[0] = kXRDC_AccessPolicyNone; - * config->policy[1] = kXRDC_AccessPolicyNone; - * ... - * config->policy[15] = kXRDC_AccessPolicyNone; - * @endcode - * - * @param config Pointer to the configuration structure. - */ -void XRDC_GetPeriphAccessDefaultConfig(xrdc_periph_access_config_t *config); - -/*! - * @brief Sets the peripheral access configuration. - * - * This function sets the peripheral access configuration as valid. Two - * methods to use it: - * Method 1: Set for one peripheral, which is used for runtime settings. - * @code - * xrdc_periph_access_config_t config; - * - * // Set LPTMR0 accessible by domain 0 - * config.periph = kXRDC_PeriphLptmr0; - * config.policy[0] = kXRDC_AccessPolicyAll; - * XRDC_SetPeriphAccessConfig(XRDC, &config); - * @endcode - * - * Method 2: Set for multiple peripherals, which is used for initialization settings. - * @code - * // Prepare the configurations - * xrdc_periph_access_config_t configs[] = - * { - * { - * .periph = kXRDC_PeriphLptmr0, - * .policy[0] = kXRDC_AccessPolicyAll, - * .policy[1] = kXRDC_AccessPolicyAll - * }, - * { - * .periph = kXRDC_PeriphLpuart0, - * .policy[0] = kXRDC_AccessPolicyAll, - * .policy[1] = kXRDC_AccessPolicyAll - * } - * }; - * - * // Set the configurations. - * for (i=0U; i<(sizeof(configs)/sizeof(configs[0])), i++) - * { - * XRDC_SetPeriphAccessConfig(XRDC, &config[i]); - * } - * @endcode - * - * @param base XRDC peripheral base address. - * @param config Pointer to the configuration structure. - */ -void XRDC_SetPeriphAccessConfig(XRDC_Type *base, const xrdc_periph_access_config_t *config); - -/*! - * @brief Sets the peripheral access configuration register lock mode. - * - * @param base XRDC peripheral base address. - * @param periph Which peripheral access configuration register to lock. - * @param lockMode The lock mode to set. - */ -static inline void XRDC_SetPeriphAccessLockMode(XRDC_Type *base, - xrdc_periph_t periph, - xrdc_access_config_lock_t lockMode) -{ - uint32_t reg = base->PDAC_W[periph][1]; - -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) - /* If there is PDAC_W1[EAL], should not write non-zero value to EAL. */ - reg = ((reg & ~(XRDC_PDAC_W_LK2_MASK | XRDC_PDAC_W_EAL_MASK)) | XRDC_PDAC_W_LK2(lockMode)); -#else - reg = ((reg & ~XRDC_PDAC_W_LK2_MASK) | XRDC_PDAC_W_LK2(lockMode)); -#endif - - base->PDAC_W[periph][1] = reg; -} - -/*! - * @brief Sets the peripheral access as valid or invalid. - * - * This function sets the peripheral access configuration dynamically. For example: - * - * @code - * // Set LPTMR0 accessible by domain 0. - * xrdc_periph_access_config_t config = - * { - * .periph = kXRDC_PeriphLptmr0; - * .policy[0] = kXRDC_AccessPolicyAll; - * }; - * XRDC_SetPeriphAccessConfig(XRDC, &config); - * - * // Set the LPTMR0 access configuration invalid. - * XRDC_SetPeriphAccessValid(kXrdcPeriLptmr0, false); - * - * // Set the LPTMR0 access configuration valid, the LPTMR0 accessible by domain 0. - * XRDC_SetPeriphAccessValid(kXrdcPeriLptmr0, true); - * @endcode - * - * @param base XRDC peripheral base address. - * @param periph Which peripheral access configuration to set. - * @param valid True to set valid, false to set invalid. - */ -static inline void XRDC_SetPeriphAccessValid(XRDC_Type *base, xrdc_periph_t periph, bool valid) -{ -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) - /* If there is PDAC_W1[EAL], should not write non-zero value to EAL. */ - uint32_t reg = base->PDAC_W[periph][1] & ~XRDC_PDAC_W_EAL_MASK; - - if (valid) - { - base->PDAC_W[periph][1] = reg | XRDC_PDAC_W_VLD_MASK; - } - else - { - base->PDAC_W[periph][1] = reg & ~XRDC_PDAC_W_VLD_MASK; - } -#else - if (valid) - { - base->PDAC_W[periph][1] |= XRDC_PDAC_W_VLD_MASK; - } - else - { - base->PDAC_W[periph][1] &= ~XRDC_PDAC_W_VLD_MASK; - } -#endif -} - -#if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) -/*! - * @brief Sets the peripheral exclusive access lock mode configuration. - * - * @param base XRDC peripheral base address. - * @param periph Which peripheral's exclusive access lock mode to configure. - * @param lockMode The exclusive access lock mode to set. - */ -static inline void XRDC_SetPeriphExclAccessLockMode(XRDC_Type *base, - xrdc_periph_t periph, - xrdc_excl_access_lock_config_t lockMode) -{ - /* Write kXRDC_ExclAccessLockDisabled is not allowed. */ - assert(kXRDC_ExclAccessLockDisabled != lockMode); - - uint32_t reg = base->PDAC_W[periph][1]; - - reg = ((reg & ~XRDC_PDAC_W_EAL_MASK) | XRDC_PDAC_W_EAL(lockMode)); - - base->PDAC_W[periph][1] = reg; -} - -/*! - * @brief Forces the release of the peripheral exclusive access lock. - * - * A lock can be forced to the available state (EAL=10) by a domain that does not own the - * lock through the forced lock release procedure: - * The procedure to force a exclusive access lock release is as follows: - * 1. Write 0x02000046 to W1 register (PAC/MSC) or W3 register (MRC) - * 2. Write 0x02000052 to W1 register (PAC/MSC) or W3 register (MRC) - * - * Note: The two writes must be consecutive, any intervening write to the register resets the sequence. - * - * @param base XRDC peripheral base address. - * @param periph Which peripheral's exclusive access lock to force release. - */ -void XRDC_ForcePeriphExclAccessLockRelease(XRDC_Type *base, xrdc_periph_t periph); - -/*! - * @brief Gets the exclusive access lock domain owner of the peripheral. - * - * This function returns the domain ID of the exclusive access lock owner of the peripheral. - * - * @param base XRDC peripheral base address. - * @param periph Which peripheral's exclusive access lock domain owner to get. - * @return Domain ID of the peripheral exclusive access lock owner. - */ -static inline uint8_t XRDC_GetPeriphExclAccessLockDomainOwner(XRDC_Type *base, xrdc_periph_t periph) -{ - return (uint8_t)((base->PDAC_W[periph][0U] & XRDC_PDAC_W_EALO_MASK) >> XRDC_PDAC_W_EALO_SHIFT); -} -#endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */ -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_XRDC_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/fsl_device_registers.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/fsl_device_registers.h deleted file mode 100644 index 391d54fb56f3b8bc41170354a08f4d0f297b8ebe..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/fsl_device_registers.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if defined(CPU_RV32M1_cm0plus) - -#define RV32M1_cm0plus_SERIES - -/* CMSIS-style register definitions */ -#include "RV32M1_cm0plus.h" -/* CPU specific feature definitions */ -#include "RV32M1_cm0plus_features.h" - -#elif defined(CPU_RV32M1_cm4) - -#define RV32M1_cm4_SERIES - -/* CMSIS-style register definitions */ -#include "RV32M1_cm4.h" -/* CPU specific feature definitions */ -#include "RV32M1_cm4_features.h" - -#elif defined(CPU_RV32M1_zero_riscy) - -#define RV32M1_zero_riscy_SERIES - -/* CMSIS-style register definitions */ -#include "RV32M1_zero_riscy.h" -/* CPU specific feature definitions */ -#include "RV32M1_zero_riscy_features.h" - -#elif defined(CPU_RV32M1_ri5cy) - -#define RV32M1_ri5cy_SERIES - -/* CMSIS-style register definitions */ -#include "RV32M1_ri5cy.h" -/* CPU specific feature definitions */ -#include "RV32M1_ri5cy_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S deleted file mode 100644 index b8b04cae5bca7498d945a5915989866c16f3856f..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S +++ /dev/null @@ -1,226 +0,0 @@ -/* ------------------------------------------------------------------------- */ -/* @file: startup_RV32M1_ri5cy.s */ -/* @purpose: RI5CY Core Device Startup File */ -/* RV32M1_ri5cy */ -/* @version: 1.0 */ -/* @date: 2018-10-2 */ -/* @build: b180926 */ -/* ------------------------------------------------------------------------- */ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2018 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ - - -// Copyright 2017 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -#define EXCEPTION_STACK_SIZE 0x58 - - .text - .section .vectors, "ax" - .option norvc; - - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - - // reset vector - jal x0, Reset_Handler - - // Illegal instrution exception - jal x0, IllegalInstruction_Handler - - // ecall handler - jal x0, Ecall_Handler - - // LSU error - jal x0, LSU_Handler - - .section .startup - -/* Reset Handler */ -Reset_Handler: - - # Disable global interrupt. */ - csrci mstatus, 8 - - # initialize stack pointer - la sp, __StackTop - - # initialize global pointer - la gp, __global_pointer - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - call __libc_init_array - - # Enable global interrupt. */ - csrsi mstatus, 8 - - jal main - ebreak - - .size Reset_Handler, . - Reset_Handler - - .global _init - .global _fini -_init: -_fini: - ret - - // saves all caller-saved registers (except return address) -store_regs: - sw x3, 0x00(x2) // gp - sw x4, 0x04(x2) // tp - sw x5, 0x08(x2) // t0 - sw x6, 0x0c(x2) // t1 - sw x7, 0x10(x2) // t2 - sw x10, 0x14(x2) // a0 - sw x11, 0x18(x2) // a1 - sw x12, 0x1c(x2) // a2 - sw x13, 0x20(x2) // a3 - sw x14, 0x24(x2) // a4 - sw x15, 0x28(x2) // a5 - sw x16, 0x2c(x2) // a6 - sw x17, 0x30(x2) // a7 - - csrr a0, 0x7B0 - csrr a1, 0x7B1 - csrr a2, 0x7B2 - sw a0, 0x34(x2) // lpstart[0] - sw a1, 0x38(x2) // lpend[0] - sw a2, 0x3c(x2) // lpcount[0] - csrr a0, 0x7B4 - csrr a1, 0x7B5 - csrr a2, 0x7B6 - sw a0, 0x40(x2) // lpstart[1] - sw a1, 0x44(x2) // lpend[1] - sw a2, 0x48(x2) // lpcount[1] - - csrr a0, 0x341 - sw a0, 0x4c(x2) // mepc - csrr a1, 0x300 - sw a1, 0x50(x2) // mstatus - jalr x0, x1 - - // load back registers from stack -end_except: - lw a1, 0x50(x2) // mstatus - csrrw x0, 0x300, a1 - lw a0, 0x4c(x2) // mepc - csrrw x0, 0x341, a0 - - lw a0, 0x40(x2) // lpstart[1] - lw a1, 0x44(x2) // lpend[1] - lw a2, 0x48(x2) // lpcount[1] - csrrw x0, 0x7B4, a0 - csrrw x0, 0x7B5, a1 - csrrw x0, 0x7B6, a2 - lw a0, 0x34(x2) // lpstart[0] - lw a1, 0x38(x2) // lpend[0] - lw a2, 0x3c(x2) // lpcount[0] - csrrw x0, 0x7B0, a0 - csrrw x0, 0x7B1, a1 - csrrw x0, 0x7B2, a2 - - lw x3, 0x00(x2) // gp - lw x4, 0x04(x2) // tp - lw x5, 0x08(x2) // t0 - lw x6, 0x0c(x2) // t1 - lw x7, 0x10(x2) // t2 - lw x10, 0x14(x2) // a0 - lw x11, 0x18(x2) // a1 - lw x12, 0x1c(x2) // a2 - lw x13, 0x20(x2) // a3 - lw x14, 0x24(x2) // a4 - lw x15, 0x28(x2) // a5 - lw x16, 0x2c(x2) // a6 - lw x17, 0x30(x2) // a7 - - lw x1, 0x54(x2) - addi x2, x2, EXCEPTION_STACK_SIZE - mret - - .weak IRQ_Handler - .type IRQ_Handler, %function -IRQ_Handler: - addi x2, x2, -EXCEPTION_STACK_SIZE - sw x1, 0x54(x2) - jal x1, store_regs - la x1, end_except - csrr a0, mcause - jal x0, SystemIrqHandler - .size IRQ_Handler, . - IRQ_Handler - - .macro define_exception_entry entry_name handler_name - .weak \entry_name -\entry_name: - addi x2, x2, -EXCEPTION_STACK_SIZE - sw x1, 0x54(x2) - jal x1, store_regs - la x1, end_except - jal x0, \handler_name - .endm - -define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc -define_exception_entry Ecall_Handler Ecall_HandlerFunc -define_exception_entry LSU_Handler LSU_HandlerFunc - - .weak IllegalInstruction_HandlerFunc - .type IllegalInstruction_HandlerFunc, %function -IllegalInstruction_HandlerFunc: - j . - .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc - - .weak Ecall_HandlerFunc - .type Ecall_HandlerFunc, %function -Ecall_HandlerFunc: - j . - .size Ecall_HandlerFunc, . - Ecall_HandlerFunc - - .weak LSU_HandlerFunc - .type LSU_HandlerFunc, %function -LSU_HandlerFunc: - j . - .size LSU_HandlerFunc, . - LSU_HandlerFunc diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S deleted file mode 100644 index 45bad812a8124f8a7f27054d6d07ea8d7de54406..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S +++ /dev/null @@ -1,225 +0,0 @@ -/* ------------------------------------------------------------------------- */ -/* @file: startup_RV32M1_zero_riscy.s */ -/* @purpose: ZERO_RISCY Core Device Startup File */ -/* RV32M1_zero_riscy */ -/* @version: 1.0 */ -/* @date: 2018-10-2 */ -/* @build: b180926 */ -/* ------------------------------------------------------------------------- */ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2018 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ - -// Copyright 2017 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -#define EXCEPTION_STACK_SIZE 0x58 - - .text - .section .vectors, "ax" - .option norvc; - - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - jal x0, IRQ_Handler - - // reset vector - jal x0, Reset_Handler - - // Illegal instrution exception - jal x0, IllegalInstruction_Handler - - // ecall handler - jal x0, Ecall_Handler - - // LSU error - jal x0, LSU_Handler - - .section .startup - -/* Reset Handler */ -Reset_Handler: - - # Disable global interrupt. */ - csrci mstatus, 8 - - # initialize stack pointer - la sp, __StackTop - - # initialize global pointer - la gp, __global_pointer - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - call __libc_init_array - - # Enable global interrupt. */ - csrsi mstatus, 8 - - jal main - ebreak - - .size Reset_Handler, . - Reset_Handler - - .global _init - .global _fini -_init: -_fini: - ret - - // saves all caller-saved registers (except return address) -store_regs: - sw x3, 0x00(x2) // gp - sw x4, 0x04(x2) // tp - sw x5, 0x08(x2) // t0 - sw x6, 0x0c(x2) // t1 - sw x7, 0x10(x2) // t2 - sw x10, 0x14(x2) // a0 - sw x11, 0x18(x2) // a1 - sw x12, 0x1c(x2) // a2 - sw x13, 0x20(x2) // a3 - sw x14, 0x24(x2) // a4 - sw x15, 0x28(x2) // a5 - sw x16, 0x2c(x2) // a6 - sw x17, 0x30(x2) // a7 - - csrr a0, 0x7B0 - csrr a1, 0x7B1 - csrr a2, 0x7B2 - sw a0, 0x34(x2) // lpstart[0] - sw a1, 0x38(x2) // lpend[0] - sw a2, 0x3c(x2) // lpcount[0] - csrr a0, 0x7B4 - csrr a1, 0x7B5 - csrr a2, 0x7B6 - sw a0, 0x40(x2) // lpstart[1] - sw a1, 0x44(x2) // lpend[1] - sw a2, 0x48(x2) // lpcount[1] - - csrr a0, 0x341 - sw a0, 0x4c(x2) // mepc - csrr a1, 0x300 - sw a1, 0x50(x2) // mstatus - jalr x0, x1 - - // load back registers from stack -end_except: - lw a1, 0x50(x2) // mstatus - csrrw x0, 0x300, a1 - lw a0, 0x4c(x2) // mepc - csrrw x0, 0x341, a0 - - lw a0, 0x40(x2) // lpstart[1] - lw a1, 0x44(x2) // lpend[1] - lw a2, 0x48(x2) // lpcount[1] - csrrw x0, 0x7B4, a0 - csrrw x0, 0x7B5, a1 - csrrw x0, 0x7B6, a2 - lw a0, 0x34(x2) // lpstart[0] - lw a1, 0x38(x2) // lpend[0] - lw a2, 0x3c(x2) // lpcount[0] - csrrw x0, 0x7B0, a0 - csrrw x0, 0x7B1, a1 - csrrw x0, 0x7B2, a2 - - lw x3, 0x00(x2) // gp - lw x4, 0x04(x2) // tp - lw x5, 0x08(x2) // t0 - lw x6, 0x0c(x2) // t1 - lw x7, 0x10(x2) // t2 - lw x10, 0x14(x2) // a0 - lw x11, 0x18(x2) // a1 - lw x12, 0x1c(x2) // a2 - lw x13, 0x20(x2) // a3 - lw x14, 0x24(x2) // a4 - lw x15, 0x28(x2) // a5 - lw x16, 0x2c(x2) // a6 - lw x17, 0x30(x2) // a7 - - lw x1, 0x54(x2) - addi x2, x2, EXCEPTION_STACK_SIZE - mret - - .weak IRQ_Handler - .type IRQ_Handler, %function -IRQ_Handler: - addi x2, x2, -EXCEPTION_STACK_SIZE - sw x1, 0x54(x2) - jal x1, store_regs - la x1, end_except - csrr a0, mcause - jal x0, SystemIrqHandler - .size IRQ_Handler, . - IRQ_Handler - - .macro define_exception_entry entry_name handler_name - .weak \entry_name -\entry_name: - addi x2, x2, -EXCEPTION_STACK_SIZE - sw x1, 0x54(x2) - jal x1, store_regs - la x1, end_except - jal x0, \handler_name - .endm - -define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc -define_exception_entry Ecall_Handler Ecall_HandlerFunc -define_exception_entry LSU_Handler LSU_HandlerFunc - - .weak IllegalInstruction_HandlerFunc - .type IllegalInstruction_HandlerFunc, %function -IllegalInstruction_HandlerFunc: - j . - .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc - - .weak Ecall_HandlerFunc - .type Ecall_HandlerFunc, %function -Ecall_HandlerFunc: - j . - .size Ecall_HandlerFunc, . - Ecall_HandlerFunc - - .weak LSU_HandlerFunc - .type LSU_HandlerFunc, %function -LSU_HandlerFunc: - j . - .size LSU_HandlerFunc, . - LSU_HandlerFunc diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c deleted file mode 100644 index 87838a8adb0c0c6f24e9f4a9784a638f02e70f2a..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c +++ /dev/null @@ -1,556 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_ri5cy -** RV32M1_ri5cy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_ri5cy - * @version 1.0 - * @date 2018-10-02 - * @brief Device specific configuration file for RV32M1_ri5cy - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -typedef void (*irq_handler_t)(void); - -extern void DMA0_0_4_8_12_DriverIRQHandler(void); -extern void DMA0_1_5_9_13_DriverIRQHandler(void); -extern void DMA0_2_6_10_14_DriverIRQHandler(void); -extern void DMA0_3_7_11_15_DriverIRQHandler(void); -extern void DMA0_Error_IRQHandler(void); -extern void CMC0_IRQHandler(void); -extern void EWM_IRQHandler(void); -extern void FTFE_Command_Complete_IRQHandler(void); -extern void FTFE_Read_Collision_IRQHandler(void); -extern void LLWU0_IRQHandler(void); -extern void MUA_IRQHandler(void); -extern void SPM_IRQHandler(void); -extern void WDOG0_IRQHandler(void); -extern void SCG_IRQHandler(void); -extern void LPIT0_IRQHandler(void); -extern void RTC_IRQHandler(void); -extern void LPTMR0_IRQHandler(void); -extern void LPTMR1_IRQHandler(void); -extern void TPM0_IRQHandler(void); -extern void TPM1_IRQHandler(void); -extern void TPM2_IRQHandler(void); -extern void EMVSIM0_IRQHandler(void); -extern void FLEXIO0_DriverIRQHandler(void); -extern void LPI2C0_DriverIRQHandler(void); -extern void LPI2C1_DriverIRQHandler(void); -extern void LPI2C2_DriverIRQHandler(void); -extern void I2S0_DriverIRQHandler(void); -extern void USDHC0_DriverIRQHandler(void); -extern void LPSPI0_DriverIRQHandler(void); -extern void LPSPI1_DriverIRQHandler(void); -extern void LPSPI2_DriverIRQHandler(void); -extern void LPUART0_DriverIRQHandler(void); -extern void LPUART1_DriverIRQHandler(void); -extern void LPUART2_DriverIRQHandler(void); -extern void USB0_IRQHandler(void); -extern void PORTA_IRQHandler(void); -extern void PORTB_IRQHandler(void); -extern void PORTC_IRQHandler(void); -extern void PORTD_IRQHandler(void); -extern void ADC0_IRQHandler(void); -extern void LPCMP0_IRQHandler(void); -extern void LPDAC0_IRQHandler(void); -extern void CAU3_Task_Complete_IRQHandler(void); -extern void CAU3_Security_Violation_IRQHandler(void); -extern void TRNG_IRQHandler(void); -extern void LPIT1_IRQHandler(void); -extern void LPTMR2_IRQHandler(void); -extern void TPM3_IRQHandler(void); -extern void LPI2C3_DriverIRQHandler(void); -extern void LPSPI3_DriverIRQHandler(void); -extern void LPUART3_DriverIRQHandler(void); -extern void PORTE_IRQHandler(void); -extern void LPCMP1_IRQHandler(void); -extern void RF0_0_IRQHandler(void); -extern void RF0_1_IRQHandler(void); -extern void INTMUX0_0_DriverIRQHandler(void); -extern void INTMUX0_1_DriverIRQHandler(void); -extern void INTMUX0_2_DriverIRQHandler(void); -extern void INTMUX0_3_DriverIRQHandler(void); -extern void INTMUX0_4_DriverIRQHandler(void); -extern void INTMUX0_5_DriverIRQHandler(void); -extern void INTMUX0_6_DriverIRQHandler(void); -extern void INTMUX0_7_DriverIRQHandler(void); -extern void INTMUX0_8_DriverIRQHandler(void); -extern void DMA0_0_4_8_12_IRQHandler(void); -extern void DMA0_1_5_9_13_IRQHandler(void); -extern void DMA0_2_6_10_14_IRQHandler(void); -extern void DMA0_3_7_11_15_IRQHandler(void); -extern void FLEXIO0_IRQHandler(void); -extern void LPI2C0_IRQHandler(void); -extern void LPI2C1_IRQHandler(void); -extern void LPI2C2_IRQHandler(void); -extern void I2S0_IRQHandler(void); -extern void USDHC0_IRQHandler(void); -extern void LPSPI0_IRQHandler(void); -extern void LPSPI1_IRQHandler(void); -extern void LPSPI2_IRQHandler(void); -extern void LPUART0_IRQHandler(void); -extern void LPUART1_IRQHandler(void); -extern void LPUART2_IRQHandler(void); -extern void LPI2C3_IRQHandler(void); -extern void LPSPI3_IRQHandler(void); -extern void LPUART3_IRQHandler(void); -extern void INTMUX0_0_IRQHandler(void); -extern void INTMUX0_1_IRQHandler(void); -extern void INTMUX0_2_IRQHandler(void); -extern void INTMUX0_3_IRQHandler(void); -extern void INTMUX0_4_IRQHandler(void); -extern void INTMUX0_5_IRQHandler(void); -extern void INTMUX0_6_IRQHandler(void); -extern void INTMUX0_7_IRQHandler(void); - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -extern uint32_t __etext; -extern uint32_t __data_start__; -extern uint32_t __data_end__; - -extern uint32_t __bss_start__; -extern uint32_t __bss_end__; - -static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) -{ - while(p_vma <= p_vma_end) - { - *p_vma = *p_load; - ++p_load; - ++p_vma; - } -} - -static void zero_section(uint32_t * start, uint32_t * end) -{ - uint32_t * p_zero = start; - - while(p_zero <= end) - { - *p_zero = 0; - ++p_zero; - } -} - -#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \ - void __attribute__((weak)) irq_handler(void) { driver_irq_handler();} - -#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler"))) - -DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler); - -DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler); -DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler); - -__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] = -{ - DMA0_0_4_8_12_IRQHandler, - DMA0_1_5_9_13_IRQHandler, - DMA0_2_6_10_14_IRQHandler, - DMA0_3_7_11_15_IRQHandler, - DMA0_Error_IRQHandler, - CMC0_IRQHandler, - MUA_IRQHandler, - USB0_IRQHandler, - USDHC0_IRQHandler, - I2S0_IRQHandler, - FLEXIO0_IRQHandler, - EMVSIM0_IRQHandler, - LPIT0_IRQHandler, - LPSPI0_IRQHandler, - LPSPI1_IRQHandler, - LPI2C0_IRQHandler, - LPI2C1_IRQHandler, - LPUART0_IRQHandler, - PORTA_IRQHandler, - TPM0_IRQHandler, - LPDAC0_IRQHandler, - ADC0_IRQHandler, - LPCMP0_IRQHandler, - RTC_IRQHandler, - INTMUX0_0_IRQHandler, - INTMUX0_1_IRQHandler, - INTMUX0_2_IRQHandler, - INTMUX0_3_IRQHandler, - INTMUX0_4_IRQHandler, - INTMUX0_5_IRQHandler, - INTMUX0_6_IRQHandler, - INTMUX0_7_IRQHandler, - EWM_IRQHandler, - FTFE_Command_Complete_IRQHandler, - FTFE_Read_Collision_IRQHandler, - LLWU0_IRQHandler, - SPM_IRQHandler, - WDOG0_IRQHandler, - SCG_IRQHandler, - LPTMR0_IRQHandler, - LPTMR1_IRQHandler, - TPM1_IRQHandler, - TPM2_IRQHandler, - LPI2C2_IRQHandler, - LPSPI2_IRQHandler, - LPUART1_IRQHandler, - LPUART2_IRQHandler, - PORTB_IRQHandler, - PORTC_IRQHandler, - PORTD_IRQHandler, - CAU3_Task_Complete_IRQHandler, - CAU3_Security_Violation_IRQHandler, - TRNG_IRQHandler, - LPIT1_IRQHandler, - LPTMR2_IRQHandler, - TPM3_IRQHandler, - LPI2C3_IRQHandler, - LPSPI3_IRQHandler, - LPUART3_IRQHandler, - PORTE_IRQHandler, - LPCMP1_IRQHandler, - RF0_0_IRQHandler, - RF0_1_IRQHandler, -}; - -extern uint32_t __VECTOR_TABLE[]; - -static uint32_t irqNesting = 0; - -static void DefaultIRQHandler(void) -{ - for (;;) - { - } -} - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if (DISABLE_WDOG) - WDOG0->CNT = 0xD928C520U; - WDOG0->TOVAL = 0xFFFF; - WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; -#endif /* (DISABLE_WDOG) */ - - SystemInitHook(); - - copy_section(&__etext, &__data_start__, &__data_end__); - zero_section(&__bss_start__, &__bss_end__); - - /* Setup the vector table address. */ - irqNesting = 0; - - __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */ - __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */ - - /* Clear all pending flags. */ - EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF; - EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF; - /* Set all interrupt as secure interrupt. */ - EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF; -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */ - uint16_t Divider; - Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; - - switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { - case 0x1: - /* System OSC */ - SCGOUTClock = CPU_XTAL_CLK_HZ; - break; - case 0x2: - /* Slow IRC */ - SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000); - break; - case 0x3: - /* Fast IRC */ - SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000; - break; - case 0x5: - /* Low Power FLL */ - SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000; - break; - default: - return; - } - SystemCoreClock = (SCGOUTClock / Divider); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} - -#if defined(__IAR_SYSTEMS_ICC__) -#pragma weak SystemIrqHandler -void SystemIrqHandler(uint32_t mcause) { -#elif defined(__GNUC__) -__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) { -#else - #error Not supported compiler type -#endif - uint32_t intNum; - - if (mcause & 0x80000000) /* For external interrupt. */ - { - intNum = mcause & 0x1FUL; - - irqNesting++; - - /* Clear pending flag in EVENT unit .*/ - EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum); - - /* Read back to make sure write finished. */ - (void)(EVENT_UNIT->INTPTPENDCLEAR); - - __enable_irq(); /* Support nesting interrupt */ - - /* Now call the real irq handler for intNum */ - isrTable[intNum](); - - __disable_irq(); - - irqNesting--; - } -} - -/* Use LIPT0 channel 0 for systick. */ -#define SYSTICK_LPIT LPIT0 -#define SYSTICK_LPIT_CH 0 -#define SYSTICK_LPIT_IRQn LPIT0_IRQn - -/* Leverage LPIT0 to provide Systick */ -void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority) -{ - /* Init pit module */ - CLOCK_EnableClock(kCLOCK_Lpit0); - - /* Reset the timer channels and registers except the MCR register */ - SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK; - SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK; - - /* Setup timer operation in debug and doze modes and enable the module */ - SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK; - - /* Set timer period for channel 0 */ - SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1; - - /* Enable timer interrupts for channel 0 */ - SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH); - - /* Set interrupt priority. */ - EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority); - - /* Enable interrupt at the EVENT unit */ - EnableIRQ(SYSTICK_LPIT_IRQn); - - /* Start channel 0 */ - SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH); -} - -uint32_t SystemGetIRQNestingLevel(void) -{ - return irqNesting; -} - -void SystemClearSystickFlag(void) -{ - /* Channel 0. */ - SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH); -} - -void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority) -{ - uint8_t regIdx; - uint8_t regOffset; - - if ((IRQn < 32) && (intPriority < 8)) - { - /* - * 4 priority control registers, each register controls 8 interrupts. - * Bit 0-2: interrupt 0 - * Bit 4-7: interrupt 1 - * ... - * Bit 28-30: interrupt 7 - */ - regIdx = IRQn >> 3U; - regOffset = (IRQn & 0x07U) * 4U; - - EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset); - } -} - -uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn) -{ - uint8_t regIdx; - uint8_t regOffset; - int32_t intPriority; - - if ((IRQn < 32)) - { - /* - * 4 priority control registers, each register controls 8 interrupts. - * Bit 0-2: interrupt 0 - * Bit 4-7: interrupt 1 - * ... - * Bit 28-30: interrupt 7 - */ - regIdx = IRQn >> 3U; - regOffset = (IRQn & 0x07U) << 2U; - - intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF; - return (uint8_t)intPriority; - } - return 0; -} - -bool SystemInISR(void) -{ - return ((EVENT_UNIT->INTPTENACTIVE) != 0);; -} - -void EVENT_SystemReset(void) -{ - EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h deleted file mode 100644 index c46b2e7470340531247c8abaa873d767f2cafe1d..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h +++ /dev/null @@ -1,182 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_ri5cy -** RV32M1_ri5cy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_ri5cy - * @version 1.0 - * @date 2018-10-02 - * @brief Device specific configuration file for RV32M1_ri5cy (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_RV32M1_ri5cy_H_ -#define _SYSTEM_RV32M1_ri5cy_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ -#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - -/* Low power mode enable */ -/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */ -#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */ -#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */ - -#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ - - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -/** - * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler. - * - * It is called from IRQ exception context and dispatches to registered handler according to - * MCAUSE interrupt number. - * - * @param mcause IRQ acknowledge value read from MCAUSE - */ -void SystemIrqHandler(uint32_t mcause); - -/** - * @brief Get IRQ nesting level of current context. - * - * If the return value is 0, then the context is not ISR, otherwise the context is ISR. - * - * @return IRQ nesting level - */ -uint32_t SystemGetIRQNestingLevel (void); - -/** - * @brief Setup systick for RTOS system. - * - * @param tickRateHz Tick number per second - * @param intPriority IRQ interrupt priority (the smaller, the higher priority) - */ -void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority); - -/** - * @brief Clear systick flag status so that next tick interrupt may occur. - */ -void SystemClearSystickFlag (void); - -/** - * @brief Sysem is in ISR or not. - */ -bool SystemInISR(void); - -#define SysTick_Handler LPIT0_IRQHandler - -/** - * @brief Set interrupt priority in Event unit. - */ -void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority); - -/** - * @brief Get interrupt priority in Event unit. - */ -uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn); - -/** - * @brief Reset the system. - */ -void EVENT_SystemReset(void); - -#define NVIC_SystemReset EVENT_SystemReset - -/* Priority setting macro remap. */ -#define NVIC_SetPriority EVENT_SetIRQPriority - -/* Priority getting macro remap. */ -#define NVIC_GetPriority EVENT_GetIRQPriority - - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_RV32M1_ri5cy_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c deleted file mode 100644 index 03700975f1e453ff5d9410275776c07027bc6bef..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c +++ /dev/null @@ -1,535 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_zero_riscy -** RV32M1_zero_riscy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_zero_riscy - * @version 1.0 - * @date 2018-10-02 - * @brief Device specific configuration file for RV32M1_zero_riscy - * (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -typedef void (*irq_handler_t)(void); - -extern void CTI1_IRQHandler(void); -extern void DMA1_04_DriverIRQHandler(void); -extern void DMA1_15_DriverIRQHandler(void); -extern void DMA1_26_DriverIRQHandler(void); -extern void DMA1_37_DriverIRQHandler(void); -extern void DMA1_Error_DriverIRQHandler(void); -extern void CMC1_IRQHandler(void); -extern void LLWU1_IRQHandler(void); -extern void MUB_IRQHandler(void); -extern void WDOG1_IRQHandler(void); -extern void CAU3_Task_Complete_IRQHandler(void); -extern void CAU3_Security_Violation_IRQHandler(void); -extern void TRNG_IRQHandler(void); -extern void LPIT1_IRQHandler(void); -extern void LPTMR2_IRQHandler(void); -extern void TPM3_IRQHandler(void); -extern void LPI2C3_DriverIRQHandler(void); -extern void RF0_0_IRQHandler(void); -extern void RF0_1_IRQHandler(void); -extern void LPSPI3_DriverIRQHandler(void); -extern void LPUART3_DriverIRQHandler(void); -extern void PORTE_IRQHandler(void); -extern void LPCMP1_IRQHandler(void); -extern void RTC_IRQHandler(void); -extern void INTMUX1_0_DriverIRQHandler(void); -extern void INTMUX1_1_DriverIRQHandler(void); -extern void INTMUX1_2_DriverIRQHandler(void); -extern void INTMUX1_3_DriverIRQHandler(void); -extern void INTMUX1_4_DriverIRQHandler(void); -extern void INTMUX1_5_DriverIRQHandler(void); -extern void INTMUX1_6_DriverIRQHandler(void); -extern void INTMUX1_7_DriverIRQHandler(void); -extern void EWM_IRQHandler(void); -extern void FTFE_Command_Complete_IRQHandler(void); -extern void FTFE_Read_Collision_IRQHandler(void); -extern void SPM_IRQHandler(void); -extern void SCG_IRQHandler(void); -extern void LPIT0_IRQHandler(void); -extern void LPTMR0_IRQHandler(void); -extern void LPTMR1_IRQHandler(void); -extern void TPM0_IRQHandler(void); -extern void TPM1_IRQHandler(void); -extern void TPM2_IRQHandler(void); -extern void EMVSIM0_IRQHandler(void); -extern void FLEXIO0_DriverIRQHandler(void); -extern void LPI2C0_DriverIRQHandler(void); -extern void LPI2C1_DriverIRQHandler(void); -extern void LPI2C2_DriverIRQHandler(void); -extern void I2S0_DriverIRQHandler(void); -extern void USDHC0_DriverIRQHandler(void); -extern void LPSPI0_DriverIRQHandler(void); -extern void LPSPI1_DriverIRQHandler(void); -extern void LPSPI2_DriverIRQHandler(void); -extern void LPUART0_DriverIRQHandler(void); -extern void LPUART1_DriverIRQHandler(void); -extern void LPUART2_DriverIRQHandler(void); -extern void USB0_IRQHandler(void); -extern void PORTA_IRQHandler(void); -extern void PORTB_IRQHandler(void); -extern void PORTC_IRQHandler(void); -extern void PORTD_IRQHandler(void); -extern void ADC0_IRQHandler(void); -extern void LPCMP0_IRQHandler(void); -extern void LPDAC0_IRQHandler(void); -extern void DMA1_15_IRQHandler(void); -extern void DMA1_26_IRQHandler(void); -extern void DMA1_37_IRQHandler(void); -extern void DMA1_Error_IRQHandler(void); -extern void LPI2C3_IRQHandler(void); -extern void LPSPI3_IRQHandler(void); -extern void LPUART3_IRQHandler(void); -extern void INTMUX1_0_IRQHandler(void); -extern void INTMUX1_1_IRQHandler(void); -extern void INTMUX1_2_IRQHandler(void); -extern void INTMUX1_3_IRQHandler(void); -extern void INTMUX1_4_IRQHandler(void); -extern void INTMUX1_5_IRQHandler(void); -extern void INTMUX1_6_IRQHandler(void); -extern void INTMUX1_7_IRQHandler(void); -extern void FLEXIO0_IRQHandler(void); -extern void LPI2C0_IRQHandler(void); -extern void LPI2C1_IRQHandler(void); -extern void LPI2C2_IRQHandler(void); -extern void I2S0_IRQHandler(void); -extern void USDHC0_IRQHandler(void); -extern void LPSPI0_IRQHandler(void); -extern void LPSPI1_IRQHandler(void); -extern void LPSPI2_IRQHandler(void); -extern void LPUART0_IRQHandler(void); -extern void LPUART1_IRQHandler(void); -extern void LPUART2_IRQHandler(void); - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -extern uint32_t __etext; -extern uint32_t __data_start__; -extern uint32_t __data_end__; - -extern uint32_t __bss_start__; -extern uint32_t __bss_end__; - -static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end) -{ - while(p_vma <= p_vma_end) - { - *p_vma = *p_load; - ++p_load; - ++p_vma; - } -} - -static void zero_section(uint32_t * start, uint32_t * end) -{ - uint32_t * p_zero = start; - - while(p_zero <= end) - { - *p_zero = 0; - ++p_zero; - } -} - -#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \ - void __attribute__((weak)) irq_handler(void) { driver_irq_handler();} - -#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler"))) - -DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler); -DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler); - -DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler); -DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler); -DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler); -DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler); -DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler); - -__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] = -{ - CTI1_IRQHandler, - DMA1_04_IRQHandler, - DMA1_15_IRQHandler, - DMA1_26_IRQHandler, - DMA1_37_IRQHandler, - DMA1_Error_IRQHandler, - CMC1_IRQHandler, - LLWU1_IRQHandler, - MUB_IRQHandler, - WDOG1_IRQHandler, - CAU3_Task_Complete_IRQHandler, - CAU3_Security_Violation_IRQHandler, - TRNG_IRQHandler, - LPIT1_IRQHandler, - LPTMR2_IRQHandler, - TPM3_IRQHandler, - LPI2C3_IRQHandler, - RF0_0_IRQHandler, - RF0_1_IRQHandler, - LPSPI3_IRQHandler, - LPUART3_IRQHandler, - PORTE_IRQHandler, - LPCMP1_IRQHandler, - RTC_IRQHandler, - INTMUX1_0_IRQHandler, - INTMUX1_1_IRQHandler, - INTMUX1_2_IRQHandler, - INTMUX1_3_IRQHandler, - INTMUX1_4_IRQHandler, - INTMUX1_5_IRQHandler, - INTMUX1_6_IRQHandler, - INTMUX1_7_IRQHandler, - EWM_IRQHandler, - FTFE_Command_Complete_IRQHandler, - FTFE_Read_Collision_IRQHandler, - SPM_IRQHandler, - SCG_IRQHandler, - LPIT0_IRQHandler, - LPTMR0_IRQHandler, - LPTMR1_IRQHandler, - TPM0_IRQHandler, - TPM1_IRQHandler, - TPM2_IRQHandler, - EMVSIM0_IRQHandler, - FLEXIO0_IRQHandler, - LPI2C0_IRQHandler, - LPI2C1_IRQHandler, - LPI2C2_IRQHandler, - I2S0_IRQHandler, - USDHC0_IRQHandler, - LPSPI0_IRQHandler, - LPSPI1_IRQHandler, - LPSPI2_IRQHandler, - LPUART0_IRQHandler, - LPUART1_IRQHandler, - LPUART2_IRQHandler, - USB0_IRQHandler, - PORTA_IRQHandler, - PORTB_IRQHandler, - PORTC_IRQHandler, - PORTD_IRQHandler, - ADC0_IRQHandler, - LPCMP0_IRQHandler, - LPDAC0_IRQHandler, -}; - -extern uint32_t __VECTOR_TABLE[]; - -static uint32_t irqNesting = 0; - -static void DefaultIRQHandler(void) -{ - for (;;) - { - } -} - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if (DISABLE_WDOG) - WDOG1->CNT = 0xD928C520U; - WDOG1->TOVAL = 0xFFFF; - WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; -#endif /* (DISABLE_WDOG) */ - - SystemInitHook(); - - copy_section(&__etext, &__data_start__, &__data_end__); - zero_section(&__bss_start__, &__bss_end__); - - /* Setup the vector table address. */ - irqNesting = 0; - - __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */ - __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */ - - /* Clear all pending flags. */ - EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF; - EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF; - /* Set all interrupt as secure interrupt. */ - EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF; -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */ - uint16_t Divider; - Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; - - switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { - case 0x1: - /* System OSC */ - SCGOUTClock = CPU_XTAL_CLK_HZ; - break; - case 0x2: - /* Slow IRC */ - SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000); - break; - case 0x3: - /* Fast IRC */ - SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000; - break; - case 0x5: - /* Low Power FLL */ - SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000; - break; - default: - return; - } - SystemCoreClock = (SCGOUTClock / Divider); -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} - -#if defined(__IAR_SYSTEMS_ICC__) -#pragma weak SystemIrqHandler -void SystemIrqHandler(uint32_t mcause) { -#elif defined(__GNUC__) -__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) { -#else - #error Not supported compiler type -#endif - uint32_t intNum; - - if (mcause & 0x80000000) /* For external interrupt. */ - { - intNum = mcause & 0x1FUL; - - irqNesting++; - - /* Clear pending flag in EVENT unit .*/ - EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum); - - /* Read back to make sure write finished. */ - (void)(EVENT_UNIT->INTPTPENDCLEAR); - - __enable_irq(); /* Support nesting interrupt */ - - /* Now call the real irq handler for intNum */ - isrTable[intNum](); - - __disable_irq(); - - irqNesting--; - } -} - -/* Use LIPT1 channel 0 for systick. */ -#define SYSTICK_LPIT LPIT1 -#define SYSTICK_LPIT_CH 0 -#define SYSTICK_LPIT_IRQn LPIT1_IRQn - -/* Leverage LPIT0 to provide Systick */ -void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority) -{ - /* Init pit module */ - CLOCK_EnableClock(kCLOCK_Lpit1); - - /* Reset the timer channels and registers except the MCR register */ - SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK; - SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK; - - /* Setup timer operation in debug and doze modes and enable the module */ - SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK; - - /* Set timer period for channel 0 */ - SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1; - - /* Enable timer interrupts for channel 0 */ - SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH); - - /* Set interrupt priority. */ - EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority); - - /* Enable interrupt at the EVENT unit */ - EnableIRQ(SYSTICK_LPIT_IRQn); - - /* Start channel 0 */ - SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH); -} - -uint32_t SystemGetIRQNestingLevel(void) -{ - return irqNesting; -} - -void SystemClearSystickFlag(void) -{ - /* Channel 0. */ - SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH); -} - -void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority) -{ - uint8_t regIdx; - uint8_t regOffset; - - if ((IRQn < 32) && (intPriority < 8)) - { - /* - * 4 priority control registers, each register controls 8 interrupts. - * Bit 0-2: interrupt 0 - * Bit 4-7: interrupt 1 - * ... - * Bit 28-30: interrupt 7 - */ - regIdx = IRQn >> 3U; - regOffset = (IRQn & 0x07U) * 4U; - - EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset); - } -} - -bool SystemInISR(void) -{ - return ((EVENT_UNIT->INTPTENACTIVE) != 0);; -} - -void EVENT_SystemReset(void) -{ - EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK; -} diff --git a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h b/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h deleted file mode 100644 index 733ac5365615ca90ab1203702c58c72da8081b96..0000000000000000000000000000000000000000 --- a/ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h +++ /dev/null @@ -1,174 +0,0 @@ -/* -** ################################################################### -** Processors: RV32M1_zero_riscy -** RV32M1_zero_riscy -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018 -** Version: rev. 1.0, 2018-10-02 -** Build: b180926 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2018-10-02) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file RV32M1_zero_riscy - * @version 1.0 - * @date 2018-10-02 - * @brief Device specific configuration file for RV32M1_zero_riscy (header - * file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_RV32M1_zero_riscy_H_ -#define _SYSTEM_RV32M1_zero_riscy_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ -#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - -/* Low power mode enable */ -/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */ -#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */ -#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */ - -#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ - - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -/** - * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler. - * - * It is called from IRQ exception context and dispatches to registered handler according to - * MCAUSE interrupt number. - * - * @param mcause IRQ acknowledge value read from MCAUSE - */ -void SystemIrqHandler(uint32_t mcause); - -/** - * @brief Get IRQ nesting level of current context. - * - * If the return value is 0, then the context is not ISR, otherwise the context is ISR. - * - * @return IRQ nesting level - */ -uint32_t SystemGetIRQNestingLevel (void); - -/** - * @brief Setup systick for RTOS system. - * - * @param tickRateHz Tick number per second - * @param intPriority IRQ interrupt priority (the smaller, the higher priority) - */ -void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority); - -/** - * @brief Clear systick flag status so that next tick interrupt may occur. - */ -void SystemClearSystickFlag (void); - -#define SysTick_Handler LPIT1_IRQHandler - -/** - * @brief Sysem is in ISR or not. - */ -bool SystemInISR(void); - -/** - * @brief Set interrupt priority in Event unit. - */ -void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority); - -/* Priority setting macro remap. */ -#define NVIC_SetPriority EVENT_SetIRQPriority - -/** - * @brief Reset the system. - */ -void EVENT_SystemReset(void); - -#define NVIC_SystemReset EVENT_SystemReset - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_RV32M1_zero_riscy_H_ */ diff --git a/ext/hal/openisa/vega_sdk_riscv/Kconfig b/modules/Kconfig.vega similarity index 100% rename from ext/hal/openisa/vega_sdk_riscv/Kconfig rename to modules/Kconfig.vega diff --git a/west.yml b/west.yml index fe98cafd8cf915bf73f82e25abfb5a4c2b83fcbd..fdf2e74eec41c0fb5a50c568252780688bad879d 100644 --- a/west.yml +++ b/west.yml @@ -52,6 +52,9 @@ manifest: - name: hal_nordic revision: 7bf2d404d0bf7f36d77d5090b5207f8b4676776c path: modules/hal/nordic + - name: hal_openisa + revision: be5c01f86c96500def5079bcc58d2baefdffb6c8 + path: modules/hal/openisa - name: hal_silabs revision: 9151e614c23997074acd1096a3e8a9e5c255d5b9 path: modules/hal/silabs