Commit 25f4eb9a authored by Jiafei Pan's avatar Jiafei Pan Committed by Henrik Brix Andersen
Browse files

boards: imx943_evk: a55: add NETC support



Enabled NETC support on i.MX 943 A55 platform.

Signed-off-by: default avatarJiafei Pan <Jiafei.Pan@nxp.com>
parent f62cadee
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+43 −0
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@@ -2,6 +2,14 @@
# SPDX-License-Identifier: Apache-2.0

if SOC_MIMX94398_A55

if ETH_NXP_IMX_NETC

config GIC_V3_ITS
	default y

endif # ETH_NXP_IMX_NETC

# GIC ITS depends on kernel heap which init priority is 30, so set
# GIC to be 31, mailbox and SCMI will be initialized by the order
# according to dts dependency although they use the same init priority.
@@ -20,6 +28,41 @@ config ARM_SCMI_TRANSPORT_INIT_PRIORITY
config CLOCK_CONTROL_INIT_PRIORITY
	default 31 if SOC_MIMX94398_A55

# Enlarge default networking stack
if NETWORKING

config NET_L2_ETHERNET
	default y

config NET_TX_STACK_SIZE
	default 8192

config NET_RX_STACK_SIZE
	default 8192

if NET_TCP

config NET_TCP_WORKQ_STACK_SIZE
	default 8192

endif # NET_TCP

if NET_MGMT_EVENT

config NET_MGMT_EVENT_STACK_SIZE
	default 8192

endif # NET_MGMT_EVENT

if NET_SOCKETS_SERVICE

config NET_SOCKETS_SERVICE_STACK_SIZE
	default 8192

endif # NET_SOCKETS_SERVICE

endif # NETWORKING

endif # SOC_MIMX94398_A55

if SOC_MIMX94398_M33
+4 −0
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@@ -71,6 +71,10 @@ The ENET0, ENETC1, ENETC2 ports could be enabled for M33 by west build option

The two switch ports could be verified via :zephyr:code-sample:`dsa`.

For A55 Core, ENET0, ENETC1, ENETC2 ports are enabled by default, so no overlay is
needed, but NETC depends on GIC ITS, so need to make sure to allocate heap memory to
be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE.

Programming and Debugging (A55)
*******************************

+64 −0
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@@ -45,3 +45,67 @@
	pinctrl-0 = <&lpuart1_default>;
	pinctrl-names = "default";
};

&emdio {
	pinctrl-0 = <&emdio_default>;
	pinctrl-names = "default";
	status = "okay";

	phy0: phy@f {
		compatible = "ethernet-phy";
		reg = <0xf>;
		status = "disabled";
	};

	phy1: phy@10 {
		compatible = "ethernet-phy";
		reg = <0x10>;
		status = "disabled";
	};

	phy2: phy@5 {
		compatible = "realtek,rtl8211f";
		reg = <0x5>;
		status = "okay";
	};

	phy3: phy@6 {
		compatible = "realtek,rtl8211f";
		reg = <0x6>;
		status = "okay";
	};

	phy4: phy@7 {
		compatible = "realtek,rtl8211f";
		reg = <0x7>;
		status = "okay";
	};
};

&enetc_psi0 {
	pinctrl-0 = <&eth2_default>;
	pinctrl-names = "default";
	phy-handle = <&phy2>;
	phy-connection-type = "rgmii";
	status = "okay";
};

&enetc_psi1 {
	pinctrl-0 = <&eth3_default>;
	pinctrl-names = "default";
	phy-handle = <&phy3>;
	phy-connection-type = "rgmii";
	status = "okay";
};

&enetc_psi2 {
	pinctrl-0 = <&eth4_default>;
	pinctrl-names = "default";
	phy-handle = <&phy4>;
	phy-connection-type = "rgmii";
	status = "okay";
};

&netc_ptp_clock0 {
	status = "okay";
};
+2 −1
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@@ -11,8 +11,9 @@ arch: arm64
toolchain:
  - zephyr
  - cross-compile
ram: 1024
ram: 10240
supported:
  - gpio
  - net
  - uart
vendor: nxp