dts: arm: gigadevice: introduce dac for gd32 series soc (222f42f2) · Commits · Wenxi XU / zephyr

dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi

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		/*
		* Copyright (c) 2021 BrainCo Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <mem.h>
		#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>

		/ {
		soc {
		dac: dac@40007400 {
		compatible = "gd,gd32-dac";
		reg = <0x40007400 0x400>;
		rcu-periph-clock = <0x71d>;
		num-channels = <1>;
		label = "DAC";
		status = "disabled";
		#io-channel-cells = <1>;
		};
		};
		};

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		*/

		#include <mem.h>
		#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
		#include <gigadevice/gd32f3x0/gd32f350.dtsi>

		/ {
		soc {

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		*/

		#include <mem.h>
		#include <gigadevice/gd32f3x0/gd32f3x0.dtsi>
		#include <gigadevice/gd32f3x0/gd32f350.dtsi>

		/ {
		soc {

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		# Copyright (c) 2021 BrainCo Inc.
		# SPDX-License-Identifier: Apache-2.0

		description: GigaDevice GD32 series DAC module

		compatible: "gd,gd32-dac"

		include: [dac-controller.yaml, pinctrl-device.yaml]

		properties:
		reg:
		required: true

		rcu-periph-clock:
		type: int
		description: Reset Control Unit Peripheral Clock ID
		required: true

		num-channels:
		type: int
		description: Number of DAC output channels
		required: true

		reset-val:
		type: int
		default: 0
		description: Reset value of DAC output. Defaults to 0, the SoC default.
		required: false

		"#io-channel-cells":
		const: 1

		io-channel-cells:
		- output