board: imx8mp_evk: add ENET support on Cortex-A Core (20dae220) · Commits · Wenxi XU / zephyr

boards/nxp/imx8mp_evk/doc/index.rst

+8 −0

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		@@ -55,8 +55,16 @@ features:
		+-----------+------------+-------------------------------------+
		\| ARM TIMER \| on-chip \| system clock \|
		+-----------+------------+-------------------------------------+
		\| CLOCK \| on-chip \| clock_control \|
		+-----------+------------+-------------------------------------+
		\| PINMUX \| on-chip \| pinmux \|
		+-----------+------------+-------------------------------------+
		\| RDC \| on-chip \| Resource Domain Controller \|
		+-----------+------------+-------------------------------------+
		\| UART \| on-chip \| serial port \|
		+-----------+------------+-------------------------------------+
		\| ENET \| on-chip \| ethernet port \|
		+-----------+------------+-------------------------------------+

		The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware
		features:

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		/*
		* Copyright (c) 2022, NXP
		* Copyright 2022-2024 NXP
		* SPDX-License-Identifier: Apache-2.0
		*
		*/
		@@ -26,4 +26,44 @@
		drive-strength = "x1";
		};
		};

		pinmux_mdio: pinmux_mdio {
		group0 {
		pinmux = <&iomuxc_sai1_rxd2_enet_mdc_enet1_mdc>,
		<&iomuxc_sai1_rxd3_enet_mdio_enet1_mdio>;
		slew-rate = "slow";
		drive-strength = "x4";
		};
		};

		pinmux_enet: pinmux_enet {
		group0 {
		pinmux = <&iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0>,
		<&iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1>,
		<&iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2>,
		<&iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3>,
		<&iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc>,
		<&iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
		input-schmitt-enable;
		slew-rate = "fast";
		drive-strength = "x1";
		};

		group1 {
		pinmux = <&iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0>,
		<&iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1>,
		<&iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2>,
		<&iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3>,
		<&iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>,
		<&iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc>;
		slew-rate = "fast";
		drive-strength = "x6";
		};

		group2 {
		pinmux = <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>;
		slew-rate = "fast";
		drive-strength = "x1";
		};
		};
		};

+26 −1

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		/*
		* Copyright 2021-2022 NXP
		* Copyright 2021-2024 NXP
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		@@ -34,6 +34,31 @@
		sram0: memory@c0000000 {
		reg = <0xc0000000 DT_SIZE_M(1)>;
		};

		};

		&enet {
		status = "okay";
		};

		&enet_mac {
		pinctrl-0 = <&pinmux_enet>;
		pinctrl-names = "default";
		phy-handle = <&phy>;
		zephyr,random-mac-address;
		phy-connection-type = "rgmii";
		status = "okay";
		};

		&enet_mdio {
		pinctrl-0 = <&pinmux_mdio>;
		pinctrl-names = "default";
		status = "okay";
		phy: phy@0 {
		compatible = "realtek,rtl8211f";
		reg = <1>;
		status = "okay";
		};
		};

		&uart4 {

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		@@ -124,6 +124,36 @@
		status = "disabled";
		};

		enet: enet@30be0000 {
		compatible = "nxp,enet1g";
		reg = <0x30be0000 DT_SIZE_K(64)>;
		clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
		status = "disabled";

		enet_mac: ethernet {
		compatible = "nxp,enet-mac";
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-names = "COMMON";
		interrupt-parent = <&gic>;
		nxp,mdio = <&enet_mdio>;
		nxp,ptp-clock = <&enet_ptp_clock>;
		status = "disabled";
		};
		enet_mdio: mdio {
		compatible = "nxp,enet-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};
		enet_ptp_clock: ptp_clock {
		compatible = "nxp,enet-ptp-clock";
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
		status = "disabled";
		};
		};

		iomuxc: iomuxc@30330000 {
		compatible = "nxp,imx-iomuxc";
		reg = <0x30330000 DT_SIZE_K(64)>;