Commit 1f4b5ddd authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Andrew Boie
Browse files

riscv32: rename to riscv 



With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: default avatarNicolas Pitre <npitre@baylibre.com>
parent 48b4ad4b

CODEOWNERS

+10 −8
Original line number Diff line number Diff line
@@ -39,10 +39,10 @@ 
/arch/x86/                                @andrewboie @gnuless

/arch/nios2/                              @andrewboie @wentongwu

/arch/posix/                              @aescolar

/arch/riscv32/                            @kgugala @pgielda @nategraff-sifive

/arch/riscv/                              @kgugala @pgielda @nategraff-sifive

/soc/posix/                               @aescolar

/soc/riscv32/                             @kgugala @pgielda @nategraff-sifive

/soc/riscv32/openisa*/                    @MaureenHelm

/soc/riscv/                               @kgugala @pgielda @nategraff-sifive

/soc/riscv/openisa*/                      @MaureenHelm

/arch/x86/core/                           @andrewboie @gnuless

/arch/x86/core/ia32/crt0.S                @andrewboie @gnuless

/arch/x86/core/pcie.c                     @gnuless
@@ -88,8 +88,8 @@ 
/boards/nios2/altera_max10/               @wentongwu

/boards/arm/stm32_min_dev/                @cbsiddharth

/boards/posix/                            @aescolar

/boards/riscv32/                          @kgugala @pgielda @nategraff-sifive

/boards/riscv32/rv32m1_vega/              @MaureenHelm

/boards/riscv/                            @kgugala @pgielda @nategraff-sifive

/boards/riscv/rv32m1_vega/                @MaureenHelm

/boards/shields/                          @erwango

/boards/x86/                              @andrewboie @nashif

/boards/x86/up_squared/                   @gnuless
@@ -178,8 +178,10 @@ 
/dts/arm/nordic/                          @ioannisg @carlescufi

/dts/arm/nxp/                             @MaureenHelm

/dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg

/dts/riscv32/rv32m1*                      @MaureenHelm

/dts/riscv32/riscv32-litex-vexriscv.dtsi  @mateusz-holenko @kgugala @pgielda

/dts/riscv/microsemi-miv.dtsi             @galak

/dts/riscv/rv32m1*                        @MaureenHelm

/dts/riscv/riscv32-fe310.dtsi             @nategraff-sifive

/dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda

/dts/xtensa/xtensa.dtsi                   @ydamigos

/dts/bindings/                            @galak

/dts/bindings/can/                        @alexanderwachter
@@ -227,7 +229,7 @@ 
/include/arch/nios2/                      @andrewboie

/include/arch/nios2/arch.h                @andrewboie

/include/arch/posix/                      @aescolar

/include/arch/riscv32/                    @nategraff-sifive @kgugala @pgielda

/include/arch/riscv/                      @nategraff-sifive @kgugala @pgielda

/include/arch/x86/                        @andrewboie @wentongwu

/include/arch/common/                     @andrewboie @andyross @nashif

/include/arch/x86/ia32/arch.h             @andrewboie

arch/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -41,8 +41,8 @@ config NIOS2 
	select ATOMIC_OPERATIONS_C

	select HAS_DTS



config RISCV32

	bool "RISCV32 architecture"

config RISCV

	bool "RISCV architecture"

	select HAS_DTS



config XTENSA

arch/riscv32/Kconfig→arch/riscv/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -4,14 +4,15 @@ 
# SPDX-License-Identifier: Apache-2.0

#



menu "RISCV32 Options"

	depends on RISCV32

menu "RISCV Options"

	depends on RISCV



config ARCH

	string

	default "riscv64" if 64BIT

	default "riscv32"



menu "RISCV32 Processor Options"

menu "RISCV Processor Options"



config INCLUDE_RESET_VECTOR

	bool "Include Reset vector"

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