clock_control: esp32c3: added clock control (1e328fe1) · Commits · Wenxi XU / zephyr

drivers/clock_control/CMakeLists.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -5,6 +5,7 @@ zephyr_library()
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2 clock_control_esp32s2.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32C3 clock_control_esp32c3.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
		zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)

drivers/clock_control/Kconfig

+2 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,8 @@ source "drivers/clock_control/Kconfig.esp32"

		source "drivers/clock_control/Kconfig.esp32s2"

		source "drivers/clock_control/Kconfig.esp32c3"

		source "drivers/clock_control/Kconfig.litex"

		source "drivers/clock_control/Kconfig.rcar"

drivers/clock_control/Kconfig.esp32c3

0 → 100644

+10 −0

Original line number	Diff line number	Diff line
		# ESP32C3 Clock Driver configuration options

		# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
		# SPDX-License-Identifier: Apache-2.0

		config CLOCK_CONTROL_ESP32C3
		bool "ESP32C3 Clock driver"
		depends on SOC_ESP32C3
		help
		Enable support for ESP32C3 clock driver.

drivers/clock_control/clock_control_esp32c3.c

0 → 100644

+109 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#define DT_DRV_COMPAT espressif_esp32_rtc

		#include <dt-bindings/clock/esp32c3_clock.h>
		#include <hal/clk_gate_ll.h>
		#include <soc/soc_caps.h>
		#include <soc/soc.h>
		#include <soc/rtc.h>
		#include <rtc_clk_common.h>

		#include <soc.h>
		#include <drivers/clock_control.h>
		#include <driver/periph_ctrl.h>

		static int clock_control_esp32_on(const struct device *dev,
		clock_control_subsys_t sys)
		{
		ARG_UNUSED(dev);
		periph_module_enable((periph_module_t)sys);
		return 0;
		}

		static int clock_control_esp32_off(const struct device *dev,
		clock_control_subsys_t sys)
		{
		ARG_UNUSED(dev);
		periph_module_disable((periph_module_t)sys);
		return 0;
		}

		static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
		clock_control_subsys_t sys)
		{
		ARG_UNUSED(dev);
		uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
		uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);

		if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
		return CLOCK_CONTROL_STATUS_ON;
		}
		return CLOCK_CONTROL_STATUS_OFF;
		}

		static int clock_control_esp32_get_rate(const struct device *dev,
		clock_control_subsys_t sub_system,
		uint32_t *rate)
		{
		ARG_UNUSED(dev);
		ARG_UNUSED(sub_system);

		uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
		uint32_t cpuperiod_sel;
		uint32_t source_freq_mhz;
		uint32_t clk_div;

		switch (soc_clk_sel) {
		case DPORT_SOC_CLK_SEL_XTAL:
		clk_div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
		source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
		*rate = MHZ(source_freq_mhz / clk_div);
		return 0;
		case DPORT_SOC_CLK_SEL_PLL:
		cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
		if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
		*rate = MHZ(80);
		} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
		*rate = MHZ(160);
		} else {
		*rate = 0;
		return -ENOTSUP;
		}
		return 0;
		case DPORT_SOC_CLK_SEL_8M:
		*rate = MHZ(8);
		return 0;
		default:
		*rate = 0;
		return -ENOTSUP;
		}
		}

		static int clock_control_esp32_init(const struct device *dev)
		{
		ARG_UNUSED(dev);

		return 0;
		}

		static const struct clock_control_driver_api clock_control_esp32_api = {
		.on = clock_control_esp32_on,
		.off = clock_control_esp32_off,
		.async_on = NULL,
		.get_rate = clock_control_esp32_get_rate,
		.get_status = clock_control_esp32_get_status,
		};

		DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
		&clock_control_esp32_init,
		NULL,
		NULL,
		NULL,
		PRE_KERNEL_1,
		CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
		&clock_control_esp32_api);

dts/riscv/espressif/esp32c3.dtsi

+11 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,7 @@
		#include <mem.h>
		#include <dt-bindings/gpio/gpio.h>
		#include <dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
		#include <dt-bindings/clock/esp32c3_clock.h>

		/ {
		#address-cells = <1>;
		@@ -59,6 +60,16 @@
		status = "okay";
		};

		rtc: rtc@60008000 {
		compatible = "espressif,esp32-rtc";
		reg = <0x60008000 0x1000>;
		label = "RTC";
		xtal-freq = <ESP32_CLK_XTAL_40M>;
		xtal-div = <0>;
		#clock-cells = <1>;
		status = "ok";
		};

		gpio0: gpio@60004000 {
		compatible = "espressif,esp32-gpio";
		gpio-controller;

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