soc: st: Add support for STOP3 on STM32U5 (19b39406) · Commits · Wenxi XU / zephyr

drivers/counter/counter_ll_stm32_rtc.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -185,7 +185,7 @@ static void rtc_stm32_irq_config(const struct device *dev);

		static int rtc_stm32_start(const struct device *dev)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WBAX)
		#if defined(CONFIG_SOC_SERIES_STM32WBAX) \|\| defined(CONFIG_SOC_SERIES_STM32U5X)
		const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
		const struct rtc_stm32_config *cfg = dev->config;

		@@ -208,7 +208,7 @@ static int rtc_stm32_start(const struct device *dev)

		static int rtc_stm32_stop(const struct device *dev)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WBAX)
		#if defined(CONFIG_SOC_SERIES_STM32WBAX) \|\| defined(CONFIG_SOC_SERIES_STM32U5X)
		const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
		const struct rtc_stm32_config *cfg = dev->config;

+3 −1

Original line number	Diff line number	Diff line
		@@ -59,16 +59,18 @@ config STM32_LPTIM_TICK_FREQ_RATIO_OVERRIDE
		This options allows to override this check

		config STM32_LPTIM_STDBY_TIMER
		bool "Use an additional timer while entering Standby mode"
		bool
		default $(dt_chosen_enabled,$(DT_CHOSEN_STDBY_TIMER))
		depends on COUNTER
		depends on TICKLESS_KERNEL
		select EXPERIMENTAL
		help
		Use an additional timer while entering Standby mode.
		There are chips e.g. STM32WBAX family that use LPTIM as a system timer,
		but LPTIM is not clocked in standby mode. These chips usually have
		another timer that is not stopped, but it has lower frequency e.g.
		RTC, thus it can't be used as a main system timer.
		Same approach is used on STM32U5 and STOP3 mode.

		Use the Standby timer for timeout (wakeup) when the system is entering
		Standby state.

+16 −3

Original line number	Diff line number	Diff line
		@@ -204,7 +204,22 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)

		next = pm_policy_next_state(CURRENT_CPU, ticks);

		if ((next != NULL) && idle && (next->state == PM_STATE_SUSPEND_TO_RAM)) {
		/* Check if STANBY or STOP3 is requested */
		timeout_stdby = false;
		if ((next != NULL) && idle) {
		#ifdef CONFIG_PM_S2RAM
		if (next->state == PM_STATE_SUSPEND_TO_RAM) {
		timeout_stdby = true;
		}
		#endif
		#ifdef CONFIG_STM32_STOP3_LP_MODE
		if ((next->state == PM_STATE_SUSPEND_TO_IDLE) && (next->substate_id == 4)) {
		timeout_stdby = true;
		}
		#endif
		}

		if (timeout_stdby) {
		uint64_t timeout_us =
		((uint64_t)ticks * USEC_PER_SEC) / CONFIG_SYS_CLOCK_TICKS_PER_SEC;

		@@ -215,8 +230,6 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
		.flags = 0,
		};

		timeout_stdby = true;

		/* Set the alarm using timer that runs the standby.
		* Needed rump-up/setting time, lower accurency etc. should be
		* included in the exit-latency in the power state definition.

+7 −0

Original line number	Diff line number	Diff line
		@@ -65,6 +65,13 @@
		substate-id = <3>;
		min-residency-us = <900>;
		};
		/omit-if-no-ref/ stop3: state3 {
		compatible = "zephyr,power-state";
		power-state-name = "suspend-to-idle";
		substate-id = <4>;
		min-residency-us = <200000>;
		exit-latency-us = <130>;
		};
		};
		};

+15 −0

Original line number	Diff line number	Diff line
		@@ -3,6 +3,8 @@
		# Copyright (c) 2021 Linaro Limited
		# SPDX-License-Identifier: Apache-2.0

		DT_CHOSEN_STDBY_TIMER := st,lptim-stdby-timer

		config SOC_SERIES_STM32U5X
		select ARM
		select CPU_CORTEX_M33
		@@ -15,3 +17,16 @@ config SOC_SERIES_STM32U5X
		select HAS_STM32CUBE
		select HAS_PM
		select HAS_POWEROFF

		config STM32_STOP3_LP_MODE
		bool
		default $(dt_path_enabled,/cpus/power-states/state3) && $(dt_chosen_enabled,$(DT_CHOSEN_STDBY_TIMER))
		help
		Enable support for STM32 STOP3 low-power mode.
		Based on the Cortex-M33 Deepsleep mode combined with peripheral clock gating.
		All clocks in the core domain are stopped.
		The PLL, MSIS, MSIK, HSI16, and HSE oscillators are disabled.
		All SRAMs and register contents are preserved.
		SRAMs can be totally or partially switched off to further reduce consumption.
		GPIOs are left floating and additional pull-up or pull-down can be applied
		via PWR registers.