clock_control: introduce mcux pcc driver (168e1291) · Commits · Wenxi XU / zephyr

drivers/clock_control/CMakeLists.txt

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		@@ -2,6 +2,7 @@

		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM clock_control_mcux_ccm.c)
		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC clock_control_mcux_pcc.c)
		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c)
		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF nrf_power_clock.c)
		zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE quark_se_clock_control.c)

drivers/clock_control/Kconfig

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		@@ -33,6 +33,8 @@ source "drivers/clock_control/Kconfig.beetle"

		source "drivers/clock_control/Kconfig.mcux_ccm"

		source "drivers/clock_control/Kconfig.mcux_pcc"

		source "drivers/clock_control/Kconfig.mcux_sim"

		source "drivers/clock_control/Kconfig.rv32m1"

drivers/clock_control/Kconfig.mcux_pcc

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		# Kconfig - MCUXpresso SDK PCC
		#
		# Copyright (c) 2019 Vestas Wind Systems A/S
		#
		# SPDX-License-Identifier: Apache-2.0
		#

		menuconfig CLOCK_CONTROL_MCUX_PCC
		bool "MCUX PCC driver"
		depends on HAS_MCUX_PCC
		help
		Enable support for MCUX PCC driver.

drivers/clock_control/clock_control_mcux_pcc.c

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		/*
		* Copyright (c) 2019 Vestas Wind Systems A/S
		*
		* Based on clock_control_rv32m1_pcc.c, which is:
		* Copyright (c) 2018 Foundries.io
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <errno.h>
		#include <soc.h>
		#include <clock_control.h>
		#include <fsl_clock.h>

		#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
		#include <logging/log.h>
		LOG_MODULE_REGISTER(clock_control_mcux_pcc);

		struct mcux_pcc_config {
		u32_t base_address;
		};

		#define DEV_CFG(dev) ((struct mcux_pcc_config *)(dev->config->config_info))
		#define DEV_BASE(dev) (DEV_CFG(dev)->base_address)
		#ifndef MAKE_PCC_REGADDR
		#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
		#endif

		static inline clock_ip_name_t clock_ip(struct device *dev,
		clock_control_subsys_t sub_system)
		{
		u32_t offset = POINTER_TO_UINT(sub_system);

		return MAKE_PCC_REGADDR(DEV_BASE(dev), offset);
		}

		static int mcux_pcc_on(struct device *dev, clock_control_subsys_t sub_system)
		{
		CLOCK_EnableClock(clock_ip(dev, sub_system));
		return 0;
		}

		static int mcux_pcc_off(struct device *dev, clock_control_subsys_t sub_system)
		{
		CLOCK_DisableClock(clock_ip(dev, sub_system));
		return 0;
		}

		static int mcux_pcc_get_rate(struct device *dev,
		clock_control_subsys_t sub_system,
		u32_t *rate)
		{
		*rate = CLOCK_GetIpFreq(clock_ip(dev, sub_system));
		return 0;
		}

		static int mcux_pcc_init(struct device *dev)
		{
		return 0;
		}

		static const struct clock_control_driver_api mcux_pcc_api = {
		.on = mcux_pcc_on,
		.off = mcux_pcc_off,
		.get_rate = mcux_pcc_get_rate,
		};

		#if defined(DT_MCUX_PCC_0_NAME)
		static const struct mcux_pcc_config mcux_pcc0_config = {
		.base_address = DT_MCUX_PCC_0_BASE_ADDRESS
		};

		DEVICE_AND_API_INIT(mcux_pcc0, DT_MCUX_PCC_0_NAME,
		&mcux_pcc_init,
		NULL, &mcux_pcc0_config,
		PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
		&mcux_pcc_api);
		#endif

dts/bindings/arm/nxp,kinetis-pcc.yaml

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		#
		# Copyright (c) 2019 Vestas Wind Systems A/S
		#
		# SPDX-License-Identifier: Apache-2.0
		#
		---
		title: NXP Kinetis PCC (Peripheral Clock Controller)
		version: 0.1

		description: >
		This is a representation of the NXP Kinetis PCC IP node

		properties:
		compatible:
		type: string
		category: required
		description: compatible strings
		constraint: "nxp,kinetis-pcc"
		generation: define

		reg:
		type: int
		description: mmio register space
		generation: define
		category: required

		label:
		type: string
		category: required
		description: Human readable string describing the device (used by Zephyr for API name)
		generation: define

		"#cells":
		- name
		- offset
		...

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