Commit 15d4545a authored by Alberto Escolar Piedras's avatar Alberto Escolar Piedras Committed by Carles Cufi
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nrf52_bsim: docs: Minor update 



The EGU has been modelled now. Add it to the list of
supported peripherals.

Signed-off-by: default avatarAlberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
parent 361f443e

boards/posix/nrf52_bsim/doc/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ This board models some of the NRF52 SOC peripherals: 
* Accelerated address resolver

* Clock control

* PPI (Programmable Peripheral Interconnect)

* EGU (Event Generator Unit)



The nrf52_bsim board definition uses the POSIX architecture to

run applications natively on the development system, this has the benefit of

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