Commit 13ca0dc8 authored by Guillaume Gautier's avatar Guillaume Gautier Committed by Carles Cufi
Browse files

drivers: adc: stm32: refactor calibration 



Refactor calibration code in anticipation of PM addition.

Signed-off-by: default avatarGuillaume Gautier <guillaume.gautier-ext@st.com>
parent 84bfb4a6

drivers/adc/adc_stm32.c

+147 −134
Original line number Diff line number Diff line
@@ -341,6 +341,52 @@ static int check_buffer(const struct adc_sequence *sequence, 
	return 0;

}



/*

 * Enable ADC peripheral, and wait until ready if required by SOC.

 */

static int adc_stm32_enable(ADC_TypeDef *adc)

{

	if (LL_ADC_IsEnabled(adc) == 1UL) {

		return 0;

	}



#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)

	LL_ADC_ClearFlag_ADRDY(adc);

	LL_ADC_Enable(adc);



	/*

	 * Enabling ADC modules in many series may fail if they are

	 * still not stabilized, this will wait for a short time (about 1ms)

	 * to ensure ADC modules are properly enabled.

	 */

	uint32_t count_timeout = 0;



	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {

#ifdef CONFIG_SOC_SERIES_STM32F0X

		/* For F0, continue to write ADEN=1 until ADRDY=1 */

		if (LL_ADC_IsEnabled(adc) == 0UL) {

			LL_ADC_Enable(adc);

		}

#endif /* CONFIG_SOC_SERIES_STM32F0X */

		count_timeout++;

		k_busy_wait(100);

		if (count_timeout >= 10) {

			return -ETIMEDOUT;

		}

	}

#else

	/*

	 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC.

	 * On F1 and F37x if ADON holds 1 (LL_ADC_IsEnabled is true) and 1 is

	 * written, then conversion starts. That's not what is expected.

	 */

	LL_ADC_Enable(adc);

#endif



	return 0;

}



static void adc_stm32_start_conversion(const struct device *dev)

{

	const struct adc_stm32_cfg *config = dev->config;
@@ -356,6 +402,53 @@ static void adc_stm32_start_conversion(const struct device *dev) 
#endif

}



/*

 * Disable ADC peripheral, and wait until it is disabled

 */

static void adc_stm32_disable(ADC_TypeDef *adc)

{

	if (LL_ADC_IsEnabled(adc) != 1UL) {

		return;

	}



	/* Stop ongoing conversion if any

	 * Software must poll ADSTART (or JADSTART) until the bit is reset before assuming

	 * the ADC is completely stopped.

	 */



#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)

	if (LL_ADC_REG_IsConversionOngoing(adc)) {

		LL_ADC_REG_StopConversion(adc);

		while (LL_ADC_REG_IsConversionOngoing(adc)) {

		}

	}

#endif



#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \

	!defined(CONFIG_SOC_SERIES_STM32F0X) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \

	!defined(CONFIG_SOC_SERIES_STM32G0X) && \

	!defined(CONFIG_SOC_SERIES_STM32L0X) && \

	!defined(CONFIG_SOC_SERIES_STM32WBAX) && \

	!defined(CONFIG_SOC_SERIES_STM32WLX)

	if (LL_ADC_INJ_IsConversionOngoing(adc)) {

		LL_ADC_INJ_StopConversion(adc);

		while (LL_ADC_INJ_IsConversionOngoing(adc)) {

		}

	}

#endif



	LL_ADC_Disable(adc);



	/* Wait ADC is fully disabled so that we don't leave the driver into intermediate state

	 * which could prevent enabling the peripheral

	 */

	while (LL_ADC_IsEnabled(adc) == 1UL) {

	}

}



#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)



#define HAS_CALIBRATION
@@ -369,7 +462,7 @@ static void adc_stm32_start_conversion(const struct device *dev) 
#define ADC_DELAY_CALIB_ADC_CYCLES	LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES

#endif



static void adc_stm32_calib_delay(const struct device *dev)

static void adc_stm32_calibration_delay(const struct device *dev)

{

	/*

	 * Calibration of F1 and F3 (ADC1_V2_5) must start two cycles after ADON
@@ -397,7 +490,7 @@ static void adc_stm32_calib_delay(const struct device *dev) 
	}

}



static void adc_stm32_calib(const struct device *dev)

static void adc_stm32_calibration_start(const struct device *dev)

{

	const struct adc_stm32_cfg *config =

		(const struct adc_stm32_cfg *)dev->config;
@@ -429,54 +522,60 @@ static void adc_stm32_calib(const struct device *dev) 
	while (LL_ADC_IsCalibrationOnGoing(adc)) {

	}

}

#endif



/*

 * Disable ADC peripheral, and wait until it is disabled

 */

static void adc_stm32_disable(ADC_TypeDef *adc)

static int adc_stm32_calibrate(const struct device *dev)

{

	if (LL_ADC_IsEnabled(adc) != 1UL) {

		return;

	}



	/* Stop ongoing conversion if any

	 * Software must poll ADSTART (or JADSTART) until the bit is reset before assuming

	 * the ADC is completely stopped.

	 */

	const struct adc_stm32_cfg *config =

		(const struct adc_stm32_cfg *)dev->config;

	ADC_TypeDef *adc = config->base;

	int err;



#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)

	if (LL_ADC_REG_IsConversionOngoing(adc)) {

		LL_ADC_REG_StopConversion(adc);

		while (LL_ADC_REG_IsConversionOngoing(adc)) {

		}

	}

#endif

#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)

	adc_stm32_disable(adc);

	adc_stm32_calibration_start(dev);

	adc_stm32_calibration_delay(dev);

#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */



#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \

	!defined(CONFIG_SOC_SERIES_STM32F0X) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \

	!defined(CONFIG_SOC_SERIES_STM32G0X) && \

	!defined(CONFIG_SOC_SERIES_STM32L0X) && \

	!defined(CONFIG_SOC_SERIES_STM32WBAX) && \

	!defined(CONFIG_SOC_SERIES_STM32WLX)

	if (LL_ADC_INJ_IsConversionOngoing(adc)) {

		LL_ADC_INJ_StopConversion(adc);

		while (LL_ADC_INJ_IsConversionOngoing(adc)) {

		}

	err = adc_stm32_enable(adc);

	if (err < 0) {

		return err;

	}

#endif



	LL_ADC_Disable(adc);

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)

	adc_stm32_calibration_delay(dev);

	adc_stm32_calibration_start(dev);

#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */



	/* Wait ADC is fully disabled so that we don't leave the driver into intermediate state

	 * which could prevent enabling the peripheral

#ifdef CONFIG_SOC_SERIES_STM32H7X

	/*

	 * To ensure linearity the factory calibration values

	 * should be loaded on initialization.

	 */

	while (LL_ADC_IsEnabled(adc) == 1UL) {

	uint32_t channel_offset = 0U;

	uint32_t linear_calib_buffer = 0U;



	if (adc == ADC1) {

		channel_offset = 0UL;

	} else if (adc == ADC2) {

		channel_offset = 8UL;

	} else   /*Case ADC3*/ {

		channel_offset = 16UL;

	}

	/* Read factory calibration factors */

	for (uint32_t count = 0UL; count < ADC_LINEAR_CALIB_REG_COUNT; count++) {

		linear_calib_buffer = *(uint32_t *)(

			ADC_LINEAR_CALIB_REG_1_ADDR + channel_offset + count

		);

		LL_ADC_SetCalibrationLinearFactor(

			adc, LL_ADC_CALIB_LINEARITY_WORD1 << count,

			linear_calib_buffer

		);

	}

#endif /* CONFIG_SOC_SERIES_STM32H7X */



	return 0;

}

#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) */



#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \

	!defined(CONFIG_SOC_SERIES_STM32F1X) && \
@@ -609,52 +708,6 @@ static int adc_stm32_oversampling(ADC_TypeDef *adc, uint8_t ratio) 
}

#endif /* CONFIG_SOC_SERIES_STM32xxx */



/*

 * Enable ADC peripheral, and wait until ready if required by SOC.

 */

static int adc_stm32_enable(ADC_TypeDef *adc)

{

	if (LL_ADC_IsEnabled(adc) == 1UL) {

		return 0;

	}



#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)

	LL_ADC_ClearFlag_ADRDY(adc);

	LL_ADC_Enable(adc);



	/*

	 * Enabling ADC modules in many series may fail if they are

	 * still not stabilized, this will wait for a short time (about 1ms)

	 * to ensure ADC modules are properly enabled.

	 */

	uint32_t count_timeout = 0;



	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {

#ifdef CONFIG_SOC_SERIES_STM32F0X

		/* For F0, continue to write ADEN=1 until ADRDY=1 */

		if (LL_ADC_IsEnabled(adc) == 0UL) {

			LL_ADC_Enable(adc);

		}

#endif /* CONFIG_SOC_SERIES_STM32F0X */

		count_timeout++;

		k_busy_wait(100);

		if (count_timeout >= 10) {

			return -ETIMEDOUT;

		}

	}

#else

	/*

	 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC.

	 * On F1 and F37x if ADON holds 1 (LL_ADC_IsEnabled is true) and 1 is

	 * written, then conversion starts. That's not what is expected.

	 */

	LL_ADC_Enable(adc);

#endif



	return 0;

}



#ifdef CONFIG_ADC_STM32_DMA

static void dma_callback(const struct device *dev, void *user_data,

			 uint32_t channel, int status)
@@ -899,12 +952,8 @@ static int start_read(const struct device *dev, 
#endif /* HAS_OVERSAMPLING */



	if (sequence->calibrate) {

#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \

	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)



		/* we cannot calibrate the ADC while the ADC is enabled */

		adc_stm32_disable(adc);

		adc_stm32_calib(dev);

#if defined(HAS_CALIBRATION)

		adc_stm32_calibrate(dev);

#else

		LOG_ERR("Calibration not supported");

		return -ENOTSUP;
@@ -1236,6 +1285,8 @@ static int adc_stm32_init(const struct device *dev) 
	ADC_TypeDef *adc = (ADC_TypeDef *)config->base;

	int err;



	ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */



	LOG_DBG("Initializing %s", dev->name);



	if (!device_is_ready(clk)) {
@@ -1264,6 +1315,7 @@ static int adc_stm32_init(const struct device *dev) 
		LOG_ERR("ADC pinctrl setup failed (%d)", err);

		return err;

	}



#if defined(CONFIG_SOC_SERIES_STM32U5X)

	/* Enable the independent analog supply */

	LL_PWR_EnableVDDA();
@@ -1306,51 +1358,12 @@ static int adc_stm32_init(const struct device *dev) 
	k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);

#endif



#if defined(HAS_CALIBRATION) && !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)

	adc_stm32_disable(adc);

	adc_stm32_calib(dev);

	adc_stm32_calib_delay(dev);

#endif /* HAS_CALIBRATION && !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */



	err = adc_stm32_enable(adc);

	if (err < 0) {

		return err;

	}



	config->irq_cfg_func();



#if defined(HAS_CALIBRATION) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)

	adc_stm32_calib_delay(dev);

	adc_stm32_calib(dev);

	LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);

#endif /* HAS_CALIBRATION && DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */



#ifdef CONFIG_SOC_SERIES_STM32H7X

	/*

	 * To ensure linearity the factory calibration values

	 * should be loaded on initialization.

	 */

	uint32_t channel_offset = 0U;

	uint32_t linear_calib_buffer = 0U;

#if defined(HAS_CALIBRATION)

	adc_stm32_calibrate(dev);

#endif /* HAS_CALIBRATION */



	if (adc == ADC1) {

		channel_offset = 0UL;

	} else if (adc == ADC2) {

		channel_offset = 8UL;

	} else   /*Case ADC3*/ {

		channel_offset = 16UL;

	}

	/* Read factory calibration factors */

	for (uint32_t count = 0UL; count < ADC_LINEAR_CALIB_REG_COUNT; count++) {

		linear_calib_buffer = *(uint32_t *)(

			ADC_LINEAR_CALIB_REG_1_ADDR + channel_offset + count

		);

		LL_ADC_SetCalibrationLinearFactor(

			adc, LL_ADC_CALIB_LINEARITY_WORD1 << count,

			linear_calib_buffer

		);

	}

#endif

	adc_context_unlock_unconditionally(&data->ctx);



	return 0;

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