pcie: shell: Print more MSI-X information (12f67c11) · Commits · Wenxi XU / zephyr

drivers/pcie/host/shell.c

+31 −2

Original line number	Diff line number	Diff line
		@@ -24,13 +24,42 @@ static void show_msi(const struct shell *shell, pcie_bdf_t bdf)
		data = pcie_conf_read(bdf, msi + PCIE_MSI_MCR);
		shell_fprintf(shell, SHELL_NORMAL, " MSI support%s%s\n",
		(data & PCIE_MSI_MCR_64) ? ", 64-bit" : "",
		(data & PCIE_MSI_MCR_EN) ? ", enabled" : "");
		(data & PCIE_MSI_MCR_EN) ?
		", enabled" : ", disabled");
		}

		msi = pcie_get_cap(bdf, PCI_CAP_ID_MSIX);

		if (msi) {
		shell_fprintf(shell, SHELL_NORMAL, " MSI-X support\n");
		uint32_t offset, table_size;
		uint8_t bir;

		data = pcie_conf_read(bdf, msi + PCIE_MSIX_MCR);

		table_size = ((data & PCIE_MSIX_MCR_TSIZE) >>
		PCIE_MSIX_MCR_TSIZE_SHIFT) + 1;

		shell_fprintf(shell, SHELL_NORMAL,
		" MSI-X support%s table size %d\n",
		(data & PCIE_MSIX_MCR_EN) ?
		", enabled" : ", disabled",
		table_size);

		offset = pcie_conf_read(bdf, msi + PCIE_MSIX_TR);
		bir = offset & PCIE_MSIX_TR_BIR;
		offset &= PCIE_MSIX_TR_OFFSET;

		shell_fprintf(shell, SHELL_NORMAL,
		"\tTable offset 0x%x BAR %d\n",
		offset, bir);

		offset = pcie_conf_read(bdf, msi + PCIE_MSIX_PBA);
		bir = offset & PCIE_MSIX_PBA_BIR;
		offset &= PCIE_MSIX_PBA_OFFSET;

		shell_fprintf(shell, SHELL_NORMAL,
		"\tPBA offset 0x%x BAR %d\n",
		offset, bir);
		}
		#endif
		}

+5 −1

Original line number	Diff line number	Diff line
		@@ -147,9 +147,13 @@ extern bool pcie_msi_enable(pcie_bdf_t bdf,
		#define PCIE_MSIR_TABLE_ENTRY_SIZE 16

		#define PCIE_MSIX_TR 1U
		#define PCIE_MSIX_TR_BIR 0x00000007U /* BIR mask */
		#define PCIE_MSIX_TR_BIR 0x00000007U /* Table BIR mask */
		#define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */

		#define PCIE_MSIX_PBA 2U
		#define PCIE_MSIX_PBA_BIR 0x00000007U /* PBA BIR mask */
		#define PCIE_MSIX_PBA_OFFSET 0xFFFFFFF8U /* Offset mask */

		#define PCIE_VTBL_MA 0U /* Msg Address offset */
		#define PCIE_VTBL_MUA 4U /* Msg Upper Address offset */
		#define PCIE_VTBL_MD 8U /* Msg Data offset */