clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32 (12b53d12) · Commits · Wenxi XU / zephyr

boards/arm/qemu_cortex_m0/nrf_timer_timer.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -247,7 +247,7 @@ uint32_t sys_clock_elapsed(void)
		return ret;
		}

		uint32_t z_timer_cycle_get_32(void)
		uint32_t sys_clock_cycle_get_32(void)
		{
		k_spinlock_key_t key = k_spin_lock(&lock);
		uint32_t ret = counter_sub(counter(), last_count) + last_count;

drivers/timer/Kconfig

+2 −2

Original line number	Diff line number	Diff line
		@@ -30,12 +30,12 @@ config APIC_TIMER_IRQ_PRIORITY
		This option specifies the IRQ priority used by the local APIC timer.

		config APIC_TIMER_TSC
		bool "Use invariant TSC for z_timer_cycle_get_32()"
		bool "Use invariant TSC for sys_clock_cycle_get_32()"
		help
		If your CPU supports invariant TSC, and you know the ratio of the
		TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
		timer frequency), then enable this for a much faster and more
		accurate z_timer_cycle_get_32().
		accurate sys_clock_cycle_get_32().

		if APIC_TIMER_TSC

drivers/timer/altera_avalon_timer_hal.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -49,7 +49,7 @@ int sys_clock_driver_init(const struct device *device)
		return 0;
		}

		uint32_t z_timer_cycle_get_32(void)
		uint32_t sys_clock_cycle_get_32(void)
		{
		/* Per the Altera Embedded IP Peripherals guide, you cannot
		* use a timer instance for both the system clock and timestamps

drivers/timer/apic_timer.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
		* This driver enables the local APIC as the Zephyr system timer. It supports
		* both legacy ("tickful") mode as well as TICKLESS_KERNEL. The driver will
		* work with any APIC that has the ARAT "always running APIC timer" feature
		* (CPUID 0x06, EAX bit 2); for the more accurate z_timer_cycle_get_32(),
		* (CPUID 0x06, EAX bit 2); for the more accurate sys_clock_cycle_get_32(),
		* the invariant TSC feature (CPUID 0x80000007: EDX bit 8) is also required.
		* (Ultimately systems with invariant TSCs should use a TSC-based driver,
		* and the TSC-related parts should be stripped from this implementation.)
		@@ -31,7 +31,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
		* by the local APIC timer block (before it gets to the timer divider).
		*
		* CONFIG_APIC_TIMER_TSC=y enables the more accurate TSC-based cycle counter
		* for z_timer_cycle_get_32(). This also requires the next options be set.
		* for sys_clock_cycle_get_32(). This also requires the next options be set.
		*
		* CONFIG_APIC_TIMER_TSC_N=<n>
		* CONFIG_APIC_TIMER_TSC_M=<m>
		@@ -187,7 +187,7 @@ uint32_t sys_clock_elapsed(void)

		#ifdef CONFIG_APIC_TIMER_TSC

		uint32_t z_timer_cycle_get_32(void)
		uint32_t sys_clock_cycle_get_32(void)
		{
		uint64_t tsc = z_tsc_read();
		uint32_t cycles;
		@@ -198,7 +198,7 @@ uint32_t z_timer_cycle_get_32(void)

		#else

		uint32_t z_timer_cycle_get_32(void)
		uint32_t sys_clock_cycle_get_32(void)
		{
		uint32_t ret;
		uint32_t ccr;

drivers/timer/arcv2_timer0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -437,7 +437,7 @@ uint32_t sys_clock_elapsed(void)
		return cyc / CYC_PER_TICK;
		}

		uint32_t z_timer_cycle_get_32(void)
		uint32_t sys_clock_cycle_get_32(void)
		{
		#if SMP_TIMER_DRIVER
		return z_arc_connect_gfrc_read() - start_time;

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