Commit 0da8ec70 authored by Watson Zeng's avatar Watson Zeng Committed by Anas Nashif
Browse files

arch: arc: enable divide zero exception



STATUS32.DZ(bit 13) is the EV_DivZero exception enable bit, and it's
not enabled by default. we need to set it explicitly to enable divide
zero exception on early boot and each thread's setup.

The DZ bit is ignored on write and read as zero when there is no
hardware division configured. So we can simply set DZ bit even if
there is no hardware division configured.

Signed-off-by: default avatarWatson Zeng <zhiwei@synopsys.com>
parent 856ff7db
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+4 −0
Original line number Diff line number Diff line
@@ -83,6 +83,10 @@ SECTION_FUNC(TEXT,__start)
	sr r0, [_ARC_V2_IRQ_VECT_BASE]
#endif

	lr r0, [_ARC_V2_STATUS32]
	bset r0, r0, _ARC_V2_STATUS32_DZ_BIT
	kflag r0

#if defined(CONFIG_USERSPACE)
	lr r0, [_ARC_V2_STATUS32]
	bset r0, r0, _ARC_V2_STATUS32_US_BIT
+2 −2
Original line number Diff line number Diff line
@@ -150,14 +150,14 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
	 * level/mask can't be set from user space that's not worse than
	 * executing a loop without yielding.
	 */
	iframe->status32 = _ARC_V2_STATUS32_US;
	iframe->status32 = _ARC_V2_STATUS32_US | _ARC_V2_STATUS32_DZ;
	if (is_user(thread)) {
		iframe->pc = (uint32_t)z_user_thread_entry_wrapper;
	} else {
		iframe->pc = (uint32_t)z_thread_entry_wrapper;
	}
#else
	iframe->status32 = 0;
	iframe->status32 = _ARC_V2_STATUS32_DZ;
	iframe->pc = ((uint32_t)z_thread_entry_wrapper);
#endif /* CONFIG_USERSPACE */
#ifdef CONFIG_ARC_SECURE_FIRMWARE
+2 −1
Original line number Diff line number Diff line
@@ -132,7 +132,8 @@
#define _ARC_V2_STATUS32_N (1 << 10)
#define _ARC_V2_STATUS32_Z (1 << 11)
#define _ARC_V2_STATUS32_L (1 << 12)
#define _ARC_V2_STATUS32_DZ (1 << 13)
#define _ARC_V2_STATUS32_DZ_BIT 13
#define _ARC_V2_STATUS32_DZ (1 << _ARC_V2_STATUS32_DZ_BIT)
#define _ARC_V2_STATUS32_SC_BIT 14
#define _ARC_V2_STATUS32_SC (1 << _ARC_V2_STATUS32_SC_BIT)
#define _ARC_V2_STATUS32_ES (1 << 15)