soc: intel_adsp: tools: merge cavstool.py and acetool.py code (0ca7ef78) · Commits · Wenxi XU / zephyr

soc/intel/intel_adsp/tools/acetool.py

+2 −719

File changed.

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soc/intel/intel_adsp/tools/cavstool.py

+209 −16

Changes for soc/intel/intel_adsp/tools/cavstool.py: 209 added lines, 16 removed lines.
Original line number	Diff line number	Diff line
		@@ -21,15 +21,18 @@ PAGESZ = 4096
		HUGEPAGESZ = 2 * 1024 * 1024
		HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp."

		# SRAM windows. Each appears in a 128k region starting at 512k.
		# SRAM windows. Base and stride varies depending on ADSP version
		#
		# Window 0 is the FW_STATUS area, and 4k after that the IPC "outbox"
		# Window 1 is the IPC "inbox" (host-writable memory, just 384 bytes currently)
		# Window 2 is unused by this script
		# Window 2 is debug, divided into multiple slots, unused by this script
		# Window 3 is winstream-formatted log output
		OUTBOX_OFFSET = (512 + (0 * 128)) * 1024 + 4096
		INBOX_OFFSET = (512 + (1 * 128)) * 1024
		WINSTREAM_OFFSET = (512 + (3 * 128)) * 1024

		WINDOW_BASE = 0x80000
		WINDOW_STRIDE = 0x20000

		WINDOW_BASE_ACE = 0x180000
		WINDOW_STRIDE_ACE = 0x8000

		# pylint: disable=duplicate-code

		@@ -188,17 +191,34 @@ class HDAStream:
		self.debug()
		log.info(f"Reset stream {self.stream_id}")

		def adsp_is_cavs():
		return cavs15 or cavs18 or cavs15

		def adsp_is_ace():
		return ace15 or ace20

		def adsp_mem_window_config():
		if adsp_is_ace():
		base = WINDOW_BASE_ACE
		stride = WINDOW_STRIDE_ACE
		else:
		base = WINDOW_BASE
		stride = WINDOW_STRIDE

		return (base, stride)

		def map_regs():
		p = runx(f"grep -iEl 'PCI_CLASS=40(10\|38)0' /sys/bus/pci/devices/*/uevent")
		pcidir = os.path.dirname(p)

		# Platform/quirk detection. ID lists cribbed from the SOF kernel driver
		global cavs15, cavs18, cavs25
		global cavs15, cavs18, cavs25, ace15, ace20
		did = int(open(f"{pcidir}/device").read().rstrip(), 16)
		cavs15 = did in [ 0x5a98, 0x1a98, 0x3198 ]
		cavs18 = did in [ 0x9dc8, 0xa348, 0x02c8, 0x06c8, 0xa3f0 ]
		cavs25 = did in [ 0xa0c8, 0x43c8, 0x4b55, 0x4b58, 0x7ad0, 0x51c8 ]
		ace15 = did in [ 0x7e28 ]
		ace20 = did in [ 0xa828 ]

		# Check sysfs for a loaded driver and remove it
		if os.path.exists(f"{pcidir}/driver"):
		@@ -249,6 +269,20 @@ def map_regs():
		global bar4_mmap
		(bar4_mem, bar4_mmap) = bar_map(pcidir, 4)
		dsp = Regs(bar4_mem)
		if adsp_is_ace():
		dsp.HFDSSCS = 0x1000
		dsp.HFPWRCTL = 0x1d18
		dsp.HFPWRSTS = 0x1d1c
		dsp.DSP2CXCTL_PRIMARY = 0x178d04
		dsp.HFIPCXTDR = 0x73200
		dsp.HFIPCXTDA = 0x73204
		dsp.HFIPCXIDR = 0x73210
		dsp.HFIPCXIDA = 0x73214
		dsp.HFIPCXCTL = 0x73228
		dsp.HFIPCXTDDY = 0x73300
		dsp.HFIPCXIDDY = 0x73380
		dsp.SRAM_FW_STATUS = WINDOW_BASE_ACE
		else:
		dsp.ADSPCS = 0x00004
		dsp.HIPCTDR = 0x00040 if cavs15 else 0x000c0
		dsp.HIPCTDA = 0x000c4 # 1.8+ only
		@@ -256,7 +290,7 @@ def map_regs():
		dsp.HIPCIDR = 0x00048 if cavs15 else 0x000d0
		dsp.HIPCIDA = 0x000d4 # 1.8+ only
		dsp.HIPCIDD = 0x0004c if cavs15 else 0x000d8
		dsp.SRAM_FW_STATUS = 0x80000 # Start of first SRAM window
		dsp.SRAM_FW_STATUS = WINDOW_BASE # Start of first SRAM window
		dsp.freeze()

		return (hda, sd, dsp, hda_ostream_id)
		@@ -461,6 +495,128 @@ def load_firmware(fw_file):
		sd.CTL \|= 1
		log.info(f"cAVS firmware load complete")

		def load_firmware_ace(fw_file):
		try:
		fw_bytes = open(fw_file, "rb").read()
		# Resize fw_bytes for MTL
		if len(fw_bytes) < 512 * 1024:
		fw_bytes += b'\x00' * (512 * 1024 - len(fw_bytes))
		except Exception as e:
		log.error(f"Could not read firmware file: `{fw_file}'")
		log.error(e)
		sys.exit(1)

		(magic, sz) = struct.unpack("4sI", fw_bytes[0:8])
		if magic == b'$AE1':
		log.info(f"Trimming {sz} bytes of extended manifest")
		fw_bytes = fw_bytes[sz:len(fw_bytes)]

		# This actually means "enable access to BAR4 registers"!
		hda.PPCTL \|= (1 << 30) # GPROCEN, "global processing enable"

		log.info("Resetting HDA device")
		hda.GCTL = 0
		while hda.GCTL & 1: pass
		hda.GCTL = 1
		while not hda.GCTL & 1: pass

		log.info("Turning of DSP subsystem")
		dsp.HFDSSCS &= ~(1 << 16) # clear SPA bit
		time.sleep(0.002)
		# wait for CPA bit clear
		while dsp.HFDSSCS & (1 << 24):
		log.info("Waiting for DSP subsystem power off")
		time.sleep(0.1)

		log.info("Turning on DSP subsystem")
		dsp.HFDSSCS \|= (1 << 16) # set SPA bit
		time.sleep(0.002) # needed as the CPA bit may be unstable
		# wait for CPA bit
		while not dsp.HFDSSCS & (1 << 24):
		log.info("Waiting for DSP subsystem power on")
		time.sleep(0.1)

		log.info("Turning on Domain0")
		dsp.HFPWRCTL \|= 0x1 # set SPA bit
		time.sleep(0.002) # needed as the CPA bit may be unstable
		# wait for CPA bit
		while not dsp.HFPWRSTS & 0x1:
		log.info("Waiting for DSP domain0 power on")
		time.sleep(0.1)

		log.info("Turning off Primary Core")
		dsp.DSP2CXCTL_PRIMARY &= ~(0x1) # clear SPA
		time.sleep(0.002) # wait for CPA settlement
		while dsp.DSP2CXCTL_PRIMARY & (1 << 8):
		log.info("Waiting for DSP primary core power off")
		time.sleep(0.1)

		log.info(f"Configuring HDA stream {hda_ostream_id} to transfer firmware image")
		(buf_list_addr, num_bufs) = setup_dma_mem(fw_bytes)
		sd.CTL = 1
		while (sd.CTL & 1) == 0: pass
		sd.CTL = 0
		while (sd.CTL & 1) == 1: pass
		sd.CTL \|= (1 << 20) # Set stream ID to anything non-zero
		sd.BDPU = (buf_list_addr >> 32) & 0xffffffff
		sd.BDPL = buf_list_addr & 0xffffffff
		sd.CBL = len(fw_bytes)
		sd.LVI = num_bufs - 1
		hda.PPCTL \|= (1 << hda_ostream_id)

		# SPIB ("Software Position In Buffer") is an Intel HDA extension
		# that puts a transfer boundary into the stream beyond which the
		# other side will not read. The ROM wants to poll on a "buffer
		# full" bit on the other side that only works with this enabled.
		hda.SPBFCTL \|= (1 << hda_ostream_id)
		hda.SD_SPIB = len(fw_bytes)


		# Send the DSP an IPC message to tell the device how to boot.
		# Note: with cAVS 1.8+ the ROM receives the stream argument as an
		# index within the array of output streams (and we always use the
		# first one by construction). But with 1.5 it's the HDA index,
		# and depends on the number of input streams on the device.
		stream_idx = 0
		ipcval = ( (1 << 31) # BUSY bit
		\| (0x01 << 24) # type = PURGE_FW
		\| (1 << 14) # purge_fw = 1
		\| (stream_idx << 9)) # dma_id
		log.info(f"Sending IPC command, HFIPCXIDR = 0x{ipcval:x}")
		dsp.HFIPCXIDR = ipcval

		log.info("Turning on Primary Core")
		dsp.DSP2CXCTL_PRIMARY \|= 0x1 # clear SPA
		time.sleep(0.002) # wait for CPA settlement
		while not dsp.DSP2CXCTL_PRIMARY & (1 << 8):
		log.info("Waiting for DSP primary core power on")
		time.sleep(0.1)

		log.info("Waiting for IPC acceptance")
		while dsp.HFIPCXIDR & (1 << 31):
		log.info("Waiting for IPC busy bit clear")
		time.sleep(0.1)

		log.info("ACK IPC")
		dsp.HFIPCXIDA \|= (1 << 31)

		log.info(f"Starting DMA, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
		sd.CTL \|= 2 # START flag

		wait_fw_entered()

		# Turn DMA off and reset the stream. Clearing START first is a
		# noop per the spec, but absolutely required for stability.
		# Apparently the reset doesn't stop the stream, and the next load
		# starts before it's ready and kills the load (and often the DSP).
		# The sleep too is required, on at least one board (a fast
		# chromebook) putting the two writes next each other also hangs
		# the DSP!
		sd.CTL &= ~2 # clear START
		time.sleep(0.1)
		sd.CTL \|= 1
		log.info(f"ACE firmware load complete")

		def fw_is_alive():
		return dsp.SRAM_FW_STATUS & ((1 << 28) - 1) == 5 # "FW_ENTERED"

		@@ -485,17 +641,20 @@ def wait_fw_entered(timeout_s=2):
		else:
		log.info("FW alive, FW_STATUS = 0x%x", dsp.SRAM_FW_STATUS)

		def winstream_offset():
		( base, stride ) = adsp_mem_window_config()
		return base + stride * 3

		# This SHOULD be just "mem[start:start+length]", but slicing an mmap
		# array seems to be unreliable on one of my machines (python 3.6.9 on
		# Ubuntu 18.04). Read out bytes individually.
		def win_read(start, length):
		try:
		return b''.join(bar4_mmap[WINSTREAM_OFFSET + x].to_bytes(1, 'little')
		return b''.join(bar4_mmap[winstream_offset() + x].to_bytes(1, 'little')
		for x in range(start, start + length))
		except IndexError as ie:
		# A FW in a bad state may cause winstream garbage
		log.error("IndexError in bar4_mmap[%d + %d]", WINSTREAM_OFFSET, start)
		log.error("IndexError in bar4_mmap[%d + %d]", winstream_offset(), start)
		log.error("bar4_mmap.size()=%d", bar4_mmap.size())
		raise ie

		@@ -528,8 +687,19 @@ def winstream_read(last_seq):

		async def ipc_delay_done():
		await asyncio.sleep(0.1)
		if adsp_is_ace():
		dsp.HFIPCXTDA = ~(1<<31) & dsp.HFIPCXTDA # Signal done
		else:
		dsp.HIPCTDA = 1<<31

		def inbox_offset():
		( base, stride ) = adsp_mem_window_config()
		return base + stride

		def outbox_offset():
		( base, _ ) = adsp_mem_window_config()
		return base + 4096

		ipc_timestamp = 0

		# Super-simple command language, driven by the test code on the DSP
		@@ -554,8 +724,8 @@ def ipc_command(data, ext_data):
		ipc_timestamp = t
		send_msg = True
		elif data == 5: # copy word at outbox[ext_data >> 16] to inbox[ext_data & 0xffff]
		src = OUTBOX_OFFSET + 4 * (ext_data >> 16)
		dst = INBOX_OFFSET + 4 * (ext_data & 0xffff)
		src = outbox_offset() + 4 * (ext_data >> 16)
		dst = inbox_offset() + 4 * (ext_data & 0xffff)
		for i in range(4):
		bar4_mmap[dst + i] = bar4_mmap[src + i]
		elif data == 6: # HDA RESET (init if not exists)
		@@ -634,16 +804,38 @@ def ipc_command(data, ext_data):

		return

		if adsp_is_ace():
		dsp.HFIPCXTDR = 1<<31 # Ack local interrupt, also signals DONE on v1.5
		if done:
		dsp.HFIPCXTDA = ~(1<<31) & dsp.HFIPCXTDA # Signal done
		if send_msg:
		log.debug("ipc: sending msg 0x%08x" % ext_data)
		dsp.HFIPCXIDDY = ext_data
		dsp.HFIPCXIDR = (1<<31) \| ext_data
		else:
		dsp.HIPCTDR = 1<<31 # Ack local interrupt, also signals DONE on v1.5
		if cavs18:
		time.sleep(0.01) # Needed on 1.8, or the command below won't send!

		if done and not cavs15:
		dsp.HIPCTDA = 1<<31 # Signal done
		if send_msg:
		dsp.HIPCIDD = ext_data
		dsp.HIPCIDR = (1<<31) \| ext_data

		def handle_ipc():
		if adsp_is_ace():
		if dsp.HFIPCXIDA & 0x80000000:
		log.debug("ipc: Ack DSP reply with IDA_DONE")
		dsp.HFIPCXIDA = 1<<31 # must ACK any DONE interrupts that arrive!
		if dsp.HFIPCXTDR & 0x80000000:
		ipc_command(dsp.HFIPCXTDR & ~0x80000000, dsp.HFIPCXTDDY)
		return

		if dsp.HIPCIDA & 0x80000000:
		dsp.HIPCIDA = 1<<31 # must ACK any DONE interrupts that arrive!
		if dsp.HIPCTDR & 0x80000000:
		ipc_command(dsp.HIPCTDR & ~0x80000000, dsp.HIPCTDD)

		async def main():
		#TODO this bit me, remove the globals, write a little FirmwareLoader class or something to contain.
		global hda, sd, dsp, hda_ostream_id, hda_streams
		@@ -664,8 +856,12 @@ async def main():
		log.error("Firmware file argument missing")
		sys.exit(1)

		if adsp_is_ace():
		load_firmware_ace(args.fw_file)
		else:
		load_firmware(args.fw_file)
		time.sleep(0.1)

		if not args.quiet:
		sys.stdout.write("--\n")

		@@ -679,10 +875,7 @@ async def main():
		sys.stdout.write(output)
		sys.stdout.flush()
		if not args.log_only:
		if dsp.HIPCIDA & 0x80000000:
		dsp.HIPCIDA = 1<<31 # must ACK any DONE interrupts that arrive!
		if dsp.HIPCTDR & 0x80000000:
		ipc_command(dsp.HIPCTDR & ~0x80000000, dsp.HIPCTDD)
		handle_ipc()


		ap = argparse.ArgumentParser(description="DSP loader/logger tool", allow_abbrev=False)

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