Commit 0c397c7b authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Kumar Gala
Browse files

boards: stm32: fix default HSI clock configuration 



To avoid configuration surprises, replace
CONFIG_CLOCK_STM32_PLL_SRC_HSI
with
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
No impact today, but could depend on tools.

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent bce1b974

boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ CONFIG_CLOCK_CONTROL=y 
# SYSCLK selection

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# PLL configuration

CONFIG_CLOCK_STM32_PLL_SRC_HSI

CONFIG_CLOCK_STM32_PLL_SRC_HSI=y

# produce 80MHz clock at PLL output

CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20

boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig

+1 −2
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ CONFIG_CLOCK_CONTROL=y 
# SYSCLK selection

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# PLL configuration

CONFIG_CLOCK_STM32_PLL_SRC_HSI

CONFIG_CLOCK_STM32_PLL_SRC_HSI=y

# produce 80MHz clock at PLL output

CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20
@@ -54,4 +54,3 @@ CONFIG_PWM_STM32=y 
CONFIG_PWM_STM32_2=y

#enable MPU

CONFIG_STM32_ARM_MPU_ENABLE=y

boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ CONFIG_CLOCK_CONTROL=y 
# SYSCLK selection

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# PLL configuration

CONFIG_CLOCK_STM32_PLL_SRC_HSI

CONFIG_CLOCK_STM32_PLL_SRC_HSI=y

# produce 80MHz clock at PLL output

CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20

boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ CONFIG_CLOCK_CONTROL=y 
# SYSCLK selection

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# PLL configuration

CONFIG_CLOCK_STM32_PLL_SRC_HSI

CONFIG_CLOCK_STM32_PLL_SRC_HSI=y

# produce 80MHz clock at PLL output

CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20

CRA Git | Maintained and supported by SUSTech CRA and CCSE