Commit 08c165f2 authored by Daniel Leung's avatar Daniel Leung Committed by Anas Nashif
Browse files

arm: cypress/psoc6: add SoC specific linker input sections 



The Cypress PSoC6 specifies some input sections in the startup
scripts. These sections (.heap, .stack, etc.) need to be placed
at correct location.

Signed-off-by: default avatarDaniel Leung <daniel.leung@intel.com>
parent 2fed930f

include/arch/arm/cortex_m/scripts/linker.ld

+2 −0
Original line number Diff line number Diff line
@@ -114,6 +114,8 @@ SECTIONS 


	KEEP(*(IRQ_VECTOR_TABLE))



	KEEP(*(.vectors))



	KEEP(*(.openocd_dbg))

	KEEP(*(".openocd_dbg.*"))

soc/arm/cypress/psoc6/Kconfig.series

+2 −0
Original line number Diff line number Diff line
@@ -11,5 +11,7 @@ config SOC_SERIES_PSOC62 
	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

	select CPU_HAS_SYSTICK

	select HAS_CYPRESS_DRIVERS

	select SOC_NOINIT_LD

	select SOC_RWDATA_LD

	help

	  Enable support for Cypress PSoC6 MCU series

soc/arm/cypress/psoc6/soc-noinit.ld

0 → 100644
+16 −0
Original line number Diff line number Diff line 
	/*

	 * Extracted from:

	 * ext/hal/cypress/.../devices/psoc6/linker/gcc/cy8c6xx6_cm0plus.ld

	 *

	 * Size of sections are calculated in the startup scripts,

	 * so they don't have to be specified here.

	 */



	. = ALIGN(8);

	KEEP(*(.ram_vectors))



	. = ALIGN(4);

	KEEP(*(.heap))



	. = ALIGN(4);

	KEEP(*(.stack))

soc/arm/cypress/psoc6/soc-rwdata.ld

0 → 100644
+6 −0
Original line number Diff line number Diff line 
	/*

	 * Extracted from:

	 * ext/hal/cypress/.../devices/psoc6/linker/gcc/cy8c6xx6_cm0plus.ld

	 */



	KEEP(*(.cy_ramfunc))

CRA Git | Maintained and supported by SUSTech CRA and CCSE