Commit 0836af8f authored by Francois Ramu's avatar Francois Ramu Committed by Christopher Friedt
Browse files

dts: arm: stm32 devices have lptim irq priority set to 1 



The priority of the LPTim interrupt on each stm32 soc
is put at the same level as the SysTick. This priority
level is given by the system Handler priority reg
(SHPR3) when the PM is not configured.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 14b63148

dts/arm/st/g0/stm32g0.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007c00 0x400>;

			interrupts = <17 0>;

			interrupts = <17 1>;

			interrupt-names = "wakeup";

			status = "disabled";

			label = "LPTIM_1";

dts/arm/st/l0/stm32l0.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007c00 0x400>;

			interrupts = <13 0>;

			interrupts = <13 1>;

			interrupt-names = "wakeup";

			status = "disabled";

			label = "LPTIM_1";

dts/arm/st/l4/stm32l4.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007c00 0x400>;

			interrupts = <65 0>;

			interrupts = <65 1>;

			interrupt-names = "wakeup";

			status = "disabled";

			label = "LPTIM_1";

dts/arm/st/l5/stm32l5.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -277,7 +277,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007c00 0x400>;

			interrupts = <67 0>;

			interrupts = <67 1>;

			interrupt-names = "wakeup";

			status = "disabled";

			label = "LPTIM_1";

dts/arm/st/wb/stm32wb.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -369,7 +369,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40007c00 0x400>;

			interrupts = <47 0>;

			interrupts = <47 1>;

			interrupt-names = "wakeup";

			status = "disabled";

			label = "LPTIM_1";

CRA Git | Maintained and supported by SUSTech CRA and CCSE