everywhere: replace double words

	hex "SRAM Base Address"

	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))

	help

	  The SRAM base address. The default value comes from from

	  The SRAM base address. The default value comes from

	  /chosen/zephyr,sram in devicetree. The user should generally avoid

	  changing it via menuconfig or in configuration files.

	 *

	 * Note that interrupts are disabled up to this point on the ARM

	 * architecture variants other than the Cortex-M. It is also important

	 * to note that that most interrupt controllers require that the nested

	 * to note that most interrupt controllers require that the nested

	 * interrupts are handled after the active interrupt is acknowledged;

	 * this is be done through the `get_active` interrupt controller

	 * interface function.

	/* Don't clear BSS if the section is not present

	 * in memory at boot. Or else it would cause page

	 * faults. Zeroing BSS will be done later once the

	 * the paging mechanism has been initialized.

	 * paging mechanism has been initialized.

	 */

	call	z_bss_zero

#endif

add_bin_file_to_the_next_link(gen_idt_output irq_vectors_alloc)

if(CONFIG_GDT_DYNAMIC)

  # Use gen_gdt.py and objcopy to generate gdt.o from from the elf

  # Use gen_gdt.py and objcopy to generate gdt.o from the elf

  # file ${ZEPHYR_PREBUILT_EXECUTABLE}, creating the temp file gdt.bin along the

  # way.

  #

	status = "okay";

};

/* On enabled, 'core-clock', as above, is required to to be 192MHz. */

/* On enabled, 'core-clock', as above, is required to be 192MHz. */

zephyr_udc0: &usbd {

	pinctrl-0 = <&usbd_default>;

	pinctrl-names = "default";