dts: arm: st: add DTSI for STM32WBA65x device (0771d55d) · Commits · Wenxi XU / zephyr

dts/arm/st/wba/stm32wba.dtsi

+1 −1

Changes for dts/arm/st/wba/stm32wba.dtsi: 1 added line, 1 removed line.
Original line number	Diff line number	Diff line
		@@ -502,7 +502,7 @@
		compatible = "swj-connector";
		pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14
		&debug_jtdi_pa15 &debug_jtdo_swo_pb3
		&debug_jtrst_pb4>;
		&debug_njtrst_pb4>;
		pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15
		&analog_pb3 &analog_pb4>;
		pinctrl-names = "default", "sleep";

dts/arm/st/wba/stm32wba65.dtsi

0 → 100644

+80 −0

Changes for dts/arm/st/wba/stm32wba65.dtsi: 80 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2025 STMicroelectronics
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		#include <st/wba/stm32wba55.dtsi>

		/ {
		soc {
		compatible = "st,stm32wba65", "st,stm32wba", "simple-bus";

		pinctrl: pin-controller@42020000 {
		gpiod: gpio@42020c00 {
		compatible = "st,stm32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x42020c00 0x400>;
		clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
		};

		gpioe: gpio@42021000 {
		compatible = "st,stm32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x42021000 0x400>;
		clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
		};

		gpiog: gpio@42021800 {
		compatible = "st,stm32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		/* GPIOG has an independent IO supply VDDIO2 */
		reg = <0x42021800 0x400>;
		clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
		};
		};

		usart3: serial@40004800 {
		compatible = "st,stm32-usart", "st,stm32-uart";
		reg = <0x40004800 0x400>;
		clocks = <&rcc STM32_CLOCK(APB1, 18)>;
		resets = <&rctl STM32_RESET(APB1L, 18U)>;
		interrupts = <79 0>;
		status = "disabled";
		};

		spi2: spi@40003800 {
		compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x40003800 0x400>;
		interrupts = <75 5>;
		clocks = <&rcc STM32_CLOCK(APB1, 14)>;
		status = "disabled";
		};

		timers4: timers@40000800 {
		compatible = "st,stm32-timers";
		reg = <0x40000800 0x400>;
		clocks = <&rcc STM32_CLOCK(APB1, 2)>;
		resets = <&rctl STM32_RESET(APB1L, 2U)>;
		interrupts = <72 0>;
		interrupt-names = "global";
		st,prescaler = <0>;
		status = "disabled";

		counter {
		compatible = "st,stm32-counter";
		status = "disabled";
		};

		pwm {
		compatible = "st,stm32-pwm";
		status = "disabled";
		#pwm-cells = <3>;
		};
		};
		};
		};

dts/arm/st/wba/stm32wba65Xi.dtsi

0 → 100644

+26 −0

Changes for dts/arm/st/wba/stm32wba65Xi.dtsi: 26 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2025 STMicroelectronics
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		#include <mem.h>
		#include <st/wba/stm32wba65.dtsi>

		/ {
		sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(448)>;
		};

		sram1: memory@20070000 {
		compatible = "mmio-sram";
		reg = <0x20070000 DT_SIZE_K(64)>;
		};

		soc {
		flash-controller@40022000 {
		flash0: flash@8000000 {
		reg = <0x08000000 DT_SIZE_M(2)>;
		};
		};
		};
		};

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