tests: power: multicore: Fix the idle synchronization issue (05434d1b) · Commits · Wenxi XU / zephyr

On Quark SE, to enter the Low Power Sensing Standby(LPSS) State, ARC can enter the Deep Sleep state (LPSS bit enable + SS2) and wait for the Lakemont core to enter C2 or C2LP state. To achieve LPSS, ARC core enters the Deep Sleep state much before the Lakemont core enters the C2 or C2LP state and waits for the LPSS entry. Also fixed the Deep Sleep state entry according to the Quark SE C100 documentation. Signed-off-by:

Ramakrishna Pallala <ramakrishna.pallala@intel.com>

tests/power/multicore/arc/src/main.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@
		#include <ipm.h>
		#include <ipm/ipm_quark_se.h>

		#define TASK_TIME_IN_SEC 10
		#define TASK_TIME_IN_SEC 5
		#define MAX_SUSPEND_DEVICE_COUNT 15

		static struct device *suspended_devices[MAX_SUSPEND_DEVICE_COUNT];
		@@ -48,12 +48,12 @@ int _sys_soc_suspend(s32_t ticks)

		suspend_devices();

		_sys_soc_set_power_state(SYS_POWER_STATE_DEEP_SLEEP_2);
		_sys_soc_set_power_state(SYS_POWER_STATE_DEEP_SLEEP);

		if (!post_ops_done) {
		post_ops_done = 1;
		resume_devices();
		_sys_soc_power_state_post_ops(SYS_POWER_STATE_DEEP_SLEEP_2);
		_sys_soc_power_state_post_ops(SYS_POWER_STATE_DEEP_SLEEP);
		}

		return SYS_PM_DEEP_SLEEP;
		@@ -63,7 +63,7 @@ void _sys_soc_resume(void)
		{
		if (!post_ops_done) {
		post_ops_done = 1;
		_sys_soc_power_state_post_ops(SYS_POWER_STATE_DEEP_SLEEP_2);
		_sys_soc_power_state_post_ops(SYS_POWER_STATE_DEEP_SLEEP);
		resume_devices();
		}
		}

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