dts: ambiq: add mspi nodes to apollo510 soc (0341e388) · Commits · Wenxi XU / zephyr

dts/arm/ambiq/ambiq_apollo510.dtsi

+68 −0

Changes for dts/arm/ambiq/ambiq_apollo510.dtsi: 68 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -115,6 +115,30 @@
		reg = <SSRAM_BASE_ADDR SSRAM_MAX_SIZE>;
		};

		xip0: memory@MSPI0_APERTURE_BASE_NAME {
		compatible = "zephyr,memory-region";
		reg = <MSPI0_APERTURE_BASE_ADDR MSPI0_APERTURE_MAX_SIZE>;
		zephyr,memory-region = "XIP0";
		};

		xip1: memory@MSPI1_APERTURE_BASE_NAME {
		compatible = "zephyr,memory-region";
		reg = <MSPI1_APERTURE_BASE_ADDR MSPI1_APERTURE_MAX_SIZE>;
		zephyr,memory-region = "XIP1";
		};

		xip2: memory@MSPI2_APERTURE_BASE_NAME {
		compatible = "zephyr,memory-region";
		reg = <MSPI2_APERTURE_BASE_ADDR MSPI2_APERTURE_MAX_SIZE>;
		zephyr,memory-region = "XIP2";
		};

		xip3: memory@MSPI3_APERTURE_BASE_NAME {
		compatible = "zephyr,memory-region";
		reg = <MSPI3_APERTURE_BASE_ADDR MSPI3_APERTURE_MAX_SIZE>;
		zephyr,memory-region = "XIP3";
		};

		soc {
		compatible = "ambiq,apollo510", "ambiq,apollo5x", "simple-bus";

		@@ -169,6 +193,50 @@
		clocks = <&uartclk>;
		};

		mspi0: mspi@MSPI0_BASE_NAME {
		compatible = "ambiq,mspi-controller";
		reg = <MSPI0_REG_BASE MSPI0_REG_SIZE>,
		<MSPI0_APERTURE_BASE_ADDR MSPI0_APERTURE_MAX_SIZE>;
		clock-frequency = <125000000>;
		interrupts = <20 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		mspi1: mspi@MSPI1_BASE_NAME {
		compatible = "ambiq,mspi-controller";
		reg = <MSPI1_REG_BASE MSPI1_REG_SIZE>,
		<MSPI1_APERTURE_BASE_ADDR MSPI1_APERTURE_MAX_SIZE>;
		clock-frequency = <96000000>;
		interrupts = <21 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		mspi2: mspi@MSPI2_BASE_NAME {
		compatible = "ambiq,mspi-controller";
		reg = <MSPI2_REG_BASE MSPI2_REG_SIZE>,
		<MSPI2_APERTURE_BASE_ADDR MSPI2_APERTURE_MAX_SIZE>;
		clock-frequency = <96000000>;
		interrupts = <22 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		mspi3: mspi@MSPI3_BASE_NAME {
		compatible = "ambiq,mspi-controller";
		reg = <MSPI3_REG_BASE MSPI3_REG_SIZE>,
		<MSPI3_APERTURE_BASE_ADDR MSPI3_APERTURE_MAX_SIZE>;
		clock-frequency = <125000000>;
		interrupts = <54 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		pinctrl: pin-controller@GPIO_BASE_NAME {
		compatible = "ambiq,apollo5-pinctrl";
		reg = <GPIO_REG_BASE GPIO_REG_SIZE>;

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