Commit 020a0d31 authored by Quang Le's avatar Quang Le Committed by Benjamin Cabé
Browse files

drivers: interrupt controller: Add support for RZ/N2L 



Add interrupt controller driver support for RZ/N2L

Signed-off-by: default avatarQuang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: default avatarNhut Nguyen <nhut.nguyen.kc@renesas.com>
parent 6a00473f

drivers/interrupt_controller/intc_renesas_rz_ext_irq.c

+85 −6
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 * Copyright (c) 2024-2025 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -9,12 +9,17 @@ 
#include <zephyr/device.h>

#include <zephyr/devicetree.h>

#include <zephyr/kernel.h>

#include <zephyr/irq.h>

#include <zephyr/drivers/pinctrl.h>

#include <zephyr/irq.h>

#include <zephyr/logging/log.h>

#if defined(CONFIG_SOC_SERIES_RZG3S)

#include <instances/rzg/r_intc_irq.h>

#include <instances/rzg/r_intc_nmi.h>

#elif defined(CONFIG_SOC_SERIES_RZN2L)

#include <instances/rzn/r_icu.h>

#endif /* CONFIG_SOC_SERIES_* */

#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>

#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>



LOG_MODULE_REGISTER(rz_ext_irq, CONFIG_INTC_LOG_LEVEL);
@@ -31,8 +36,12 @@ struct intc_rz_ext_irq_data { 
};



/* FSP interruption handlers. */

#if defined(CONFIG_SOC_SERIES_RZG3S)

void r_intc_irq_isr(void);

void r_intc_nmi_isr(void);

#elif defined(CONFIG_SOC_SERIES_RZN2L)

void r_icu_isr(void);

#endif /* CONFIG_SOC_SERIES_* */



int intc_rz_ext_irq_enable(const struct device *dev)

{
@@ -74,6 +83,29 @@ int intc_rz_ext_irq_set_callback(const struct device *dev, intc_rz_ext_irq_callb 
	return 0;

}



int intc_rz_ext_irq_set_type(const struct device *dev, uint8_t trig)

{

	const struct intc_rz_ext_irq_config *config = dev->config;

	struct intc_rz_ext_irq_data *data = dev->data;

	fsp_err_t err = FSP_SUCCESS;

	external_irq_cfg_t *p_cfg = (external_irq_cfg_t *)config->fsp_cfg;



	p_cfg->trigger = (external_irq_trigger_t)trig;

	err = config->fsp_api->close(data->fsp_ctrl);



	if (err != FSP_SUCCESS) {

		return -EIO;

	}



	err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);



	if (err != FSP_SUCCESS) {

		return -EIO;

	}



	return 0;

}



static int intc_rz_ext_irq_init(const struct device *dev)

{

	const struct intc_rz_ext_irq_config *config = dev->config;
@@ -109,16 +141,22 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args) 
	}

}



#define EXT_IRQ_RZG_IRQ_CONNECT(index, isr, isr_nmi)                                               \

#ifdef CONFIG_CPU_CORTEX_M

#define GET_IRQ_FLAGS(index) 0

#else /* Cortex-A/R */

#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags)

#endif



#define EXT_IRQ_RZ_IRQ_CONNECT(index, isr, isr_nmi)                                                \

	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(index, 0, irq), DT_INST_IRQ_BY_IDX(index, 0, priority),     \

		    COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq),                                 \

		    (isr_nmi), (isr)), NULL, 0);

		    (isr_nmi), (isr)), NULL, GET_IRQ_FLAGS(index));



#define INTC_RZG_EXT_IRQ_INIT(index)                                                               \

	static const external_irq_cfg_t g_external_irq##index##_cfg = {                            \

		.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0),                            \

		.filter_enable = true,                                                             \

		.pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_1,                                            \

		.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1,                               \

		.p_callback = intc_rz_ext_irq_callback,                                            \

		.p_context = DEVICE_DT_INST_GET(index),                                            \

		.p_extend = NULL,                                                                  \
@@ -149,7 +187,44 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args) 
                                                                                                   \

	static int intc_rz_ext_irq_init_##index(const struct device *dev)                          \

	{                                                                                          \

		EXT_IRQ_RZG_IRQ_CONNECT(index, r_intc_irq_isr, r_intc_nmi_isr)                     \

		EXT_IRQ_RZ_IRQ_CONNECT(index, r_intc_irq_isr, r_intc_nmi_isr)                      \

		return intc_rz_ext_irq_init(dev);                                                  \

	};                                                                                         \

                                                                                                   \

	DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL,                           \

			      &intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index,        \

			      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);



#define INTC_RZTN_EXT_IRQ_INIT(index)                                                              \

	static const external_irq_cfg_t g_external_irq##index##_cfg = {                            \

		.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0),                            \

		.filter_enable = true,                                                             \

		.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1,                               \

		.p_callback = intc_rz_ext_irq_callback,                                            \

		.p_context = DEVICE_DT_INST_GET(index),                                            \

		.p_extend = NULL,                                                                  \

		.ipl = DT_INST_IRQ_BY_IDX(index, 0, priority),                                     \

		.irq = DT_INST_IRQ_BY_IDX(index, 0, irq),                                          \

		.channel = DT_INST_REG_ADDR(index),                                                \

	};                                                                                         \

                                                                                                   \

	PINCTRL_DT_INST_DEFINE(index);                                                             \

                                                                                                   \

	struct intc_rz_ext_irq_config intc_rz_ext_irq_config##index = {                            \

		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                               \

		.fsp_cfg = (external_irq_cfg_t *)&g_external_irq##index##_cfg,                     \

		.fsp_api = &g_external_irq_on_icu,                                                 \

	};                                                                                         \

                                                                                                   \

	icu_instance_ctrl_t g_external_irq##index##_ctrl;                                          \

                                                                                                   \

	static struct intc_rz_ext_irq_data intc_rz_ext_irq_data##index = {                         \

		.fsp_ctrl = (icu_instance_ctrl_t *)&g_external_irq##index##_ctrl,                  \

	};                                                                                         \

                                                                                                   \

	static int intc_rz_ext_irq_init_##index(const struct device *dev)                          \

	{                                                                                          \

		EXT_IRQ_RZ_IRQ_CONNECT(index, r_icu_isr, NULL);                                    \

		return intc_rz_ext_irq_init(dev);                                                  \

	};                                                                                         \

                                                                                                   \
@@ -157,4 +232,8 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args) 
			      &intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index,        \

			      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);



#if defined(CONFIG_SOC_SERIES_RZG3S)

DT_INST_FOREACH_STATUS_OKAY(INTC_RZG_EXT_IRQ_INIT)

#elif defined(CONFIG_SOC_SERIES_RZN2L)

DT_INST_FOREACH_STATUS_OKAY(INTC_RZTN_EXT_IRQ_INIT)

#endif

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

+151 −0
Original line number Diff line number Diff line
@@ -88,6 +88,157 @@ 
			};

		};



		icu: icu@81048000 {

			reg = <0x81048000 0x1000>;

			interrupt-parent = <&gic>;

			#address-cells = <1>;

			#size-cells = <0>;



			irq0: irq0@0 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x0>;

				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq1: irq@1 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x1>;

				interrupts = <GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq2: irq@2 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x2>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq3: irq@3 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x3>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq4: irq@4 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x4>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq5: irq@5 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x5>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq6: irq@6 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x6>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq7: irq@7 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x7>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq8: irq@8 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x8>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq9: irq@9 {

				compatible = "renesas,rz-ext-irq";

				reg = <0x9>;

				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq10: irq@a {

				compatible = "renesas,rz-ext-irq";

				reg = <0xa>;

				interrupts = <GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq11: irq@b {

				compatible = "renesas,rz-ext-irq";

				reg = <0xb>;

				interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq12: irq@c {

				compatible = "renesas,rz-ext-irq";

				reg = <0xc>;

				interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq13: irq@d {

				compatible = "renesas,rz-ext-irq";

				reg = <0xd>;

				interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq14: irq@e {

				compatible = "renesas,rz-ext-irq";

				reg = <0xe>;

				interrupts = <GIC_SPI 394 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};



			irq15: irq@f {

				compatible = "renesas,rz-ext-irq";

				reg = <0xf>;

				interrupts = <GIC_SPI 395 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;

				interrupt-controller;

				#interrupt-cells = <2>;

				status = "disabled";

			};

		};



		pinctrl: pinctrl@800a0000 {

			compatible = "renesas,rzn-pinctrl";

			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;

dts/bindings/interrupt-controller/renesas,rz-ext-irq.yaml

+1 −4
Original line number Diff line number Diff line 
# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



description: Renesas RZG external interrupt controller

description: Renesas RZ external interrupt controller



compatible: "renesas,rz-ext-irq"



include: [interrupt-controller.yaml, base.yaml, pinctrl-device.yaml]



properties:

  "#address-cells":

    const: 0



  "#interrupt-cells":

    const: 2

include/zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h

+17 −3
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 * Copyright (c) 2024-2025 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -7,11 +7,16 @@ 
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_

#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_



#define RZ_EXT_IRQ_TRIG_FALLING   0

#define RZ_EXT_IRQ_TRIG_RISING    1

#define RZ_EXT_IRQ_TRIG_BOTH_EDGE 2

#define RZ_EXT_IRQ_TRIG_LEVEL_LOW 3



/** RZ external interrupt callback */

typedef void (*intc_rz_ext_irq_callback_t)(void *arg);



/**

 * @brief Enable external interrupt for specified channel at NVIC.

 * @brief Enable external interrupt for specified channel.

 *

 * @param dev: pointer to interrupt controller instance

 * @return 0 on success, or negative value on error
@@ -19,7 +24,7 @@ typedef void (*intc_rz_ext_irq_callback_t)(void *arg); 
int intc_rz_ext_irq_enable(const struct device *dev);



/**

 * @brief Disable external interrupt for specified channel at NVIC.

 * @brief Disable external interrupt for specified channel.

 *

 * @param dev: pointer to interrupt controller instance

 * @return 0 on success, or negative value on error
@@ -37,4 +42,13 @@ int intc_rz_ext_irq_disable(const struct device *dev); 
int intc_rz_ext_irq_set_callback(const struct device *dev, intc_rz_ext_irq_callback_t cb,

				 void *arg);



/**

 * @brief Change trigger external interrupt type for specified channel.

 *

 * @param dev: pointer to interrupt controller instance

 * @param trig: trigger type to be changed

 * @return 0 on success, or negative value on error

 */

int intc_rz_ext_irq_set_type(const struct device *dev, uint8_t trig);



#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_ */

modules/Kconfig.renesas_fsp

+5 −0
Original line number Diff line number Diff line
@@ -218,4 +218,9 @@ config USE_RZ_FSP_SCI_UART 
	help

	  Enable RZ FSP SCI UART driver



config USE_RZ_FSP_EXT_IRQ

	bool

	help

	  Enable RZ FSP External IRQ driver



endif

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