arch: riscv: update coredump for 64BIT RISCV (0144ed6b) · Commits · Wenxi XU / zephyr

arch/riscv/core/coredump.c

+27 −0

Original line number	Diff line number	Diff line
		@@ -7,9 +7,35 @@
		#include <string.h>
		#include <zephyr/debug/coredump.h>

		#ifndef CONFIG_64BIT
		#define ARCH_HDR_VER 1
		#else
		#define ARCH_HDR_VER 2
		#endif

		struct riscv_arch_block {
		#ifdef CONFIG_64BIT
		struct {
		uint64_t ra;
		uint64_t tp;
		uint64_t t0;
		uint64_t t1;
		uint64_t t2;
		uint64_t a0;
		uint64_t a1;
		uint64_t a2;
		uint64_t a3;
		uint64_t a4;
		uint64_t a5;
		uint64_t a6;
		uint64_t a7;
		uint64_t t3;
		uint64_t t4;
		uint64_t t5;
		uint64_t t6;
		uint64_t pc;
		} r;
		#else /* !CONFIG_64BIT */
		struct {
		uint32_t ra;
		uint32_t tp;
		@@ -32,6 +58,7 @@ struct riscv_arch_block {
		#endif /* !CONFIG_RISCV_ISA_RV32E */
		uint32_t pc;
		} r;
		#endif /* CONFIG_64BIT */
		} __packed;

		/*

scripts/coredump/gdbstubs/arch/risc_v.py

+12 −5

Original line number	Diff line number	Diff line
		@@ -13,7 +13,6 @@ from gdbstubs.gdbstub import GdbStub

		logger = logging.getLogger("gdbstub")


		class RegNum():
		ZERO = 0
		RA = 1
		@@ -52,6 +51,7 @@ class RegNum():

		class GdbStub_RISC_V(GdbStub):
		ARCH_DATA_BLK_STRUCT = "<IIIIIIIIIIIIIIIIII"
		ARCH_DATA_BLK_STRUCT_2 = "<QQQQQQQQQQQQQQQQQQ"

		GDB_SIGNAL_DEFAULT = 7

		@@ -66,7 +66,12 @@ class GdbStub_RISC_V(GdbStub):

		def parse_arch_data_block(self):
		arch_data_blk = self.logfile.get_arch_data()['data']
		self.arch_data_ver = self.logfile.get_arch_data()['hdr_ver']

		if self.arch_data_ver == 1:
		tu = struct.unpack(self.ARCH_DATA_BLK_STRUCT, arch_data_blk)
		elif self.arch_data_ver == 2:
		tu = struct.unpack(self.ARCH_DATA_BLK_STRUCT_2, arch_data_blk)

		self.registers = dict()

		@@ -90,7 +95,7 @@ class GdbStub_RISC_V(GdbStub):
		self.registers[RegNum.PC] = tu[17]

		def handle_register_group_read_packet(self):
		reg_fmt = "<I"
		reg_fmt = "<I" if self.arch_data_ver == 1 else "<Q"

		idx = 0
		pkt = b''
		@@ -102,7 +107,8 @@ class GdbStub_RISC_V(GdbStub):
		else:
		# Register not in coredump -> unknown value
		# Send in "xxxxxxxx"
		pkt += b'x' * 8
		length = 8 if self.arch_data_ver == 1 else 16
		pkt += b'x' * length

		idx += 1

		@@ -111,4 +117,5 @@ class GdbStub_RISC_V(GdbStub):
		def handle_register_single_read_packet(self, pkt):
		# Mark registers as "<unavailable>". 'p' packets are not sent for the registers
		# currently handled in this file so we can safely reply "xxxxxxxx" here.
		self.put_gdb_packet(b'x' * 8)
		length = 8 if self.arch_data_ver == 1 else 16
		self.put_gdb_packet(b'x' * length)

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