Unverified Commit ef863820 authored by Andrzej Puzdrowski's avatar Andrzej Puzdrowski Committed by GitHub
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synchronized up to the mcu-tool/mcuboot ad1fb3dd

Synchronized to:
https://github.com/mcu-tools/mcuboot/commit/ad1fb3dde2aaf88b433f6d534c84f843c279fac8



doc: actualize zephyr-rtos port README
Kconfig: prefer swap move if scratch_partition not enabled
Kconfig: Explicitly select CONFIG_CRC for CONFIG_MCUBOOT_SERIAL

- imgtool: add option to export public PEM

merged using GitHub web gui.

Signed-off-by: default avatarAndrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
parents cfec947e cbc16809
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+12 −9
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@
#elif __ESPRESSIF__
#include <bootloader_utility.h>
#include <esp_rom_sys.h>
#include <rom/crc.h>
#include <esp_crc.h>
#include <endian.h>
#include <mbedtls/base64.h>
#else
@@ -78,7 +78,10 @@

BOOT_LOG_MODULE_DECLARE(mcuboot);

#define BOOT_SERIAL_INPUT_MAX   512
#ifndef MCUBOOT_SERIAL_MAX_RECEIVE_SIZE
#define MCUBOOT_SERIAL_MAX_RECEIVE_SIZE 512
#endif

#define BOOT_SERIAL_OUT_MAX     (128 * BOOT_IMAGE_NUMBER)

#ifdef __ZEPHYR__
@@ -107,8 +110,8 @@ BOOT_LOG_MODULE_DECLARE(mcuboot);
#define IMAGES_ITER(x)
#endif

static char in_buf[BOOT_SERIAL_INPUT_MAX + 1];
static char dec_buf[BOOT_SERIAL_INPUT_MAX + 1];
static char in_buf[MCUBOOT_SERIAL_MAX_RECEIVE_SIZE + 1];
static char dec_buf[MCUBOOT_SERIAL_MAX_RECEIVE_SIZE + 1];
const struct boot_uart_funcs *boot_uf;
static struct nmgr_hdr *bs_hdr;
static bool bs_entry;
@@ -552,7 +555,7 @@ out:
    BOOT_LOG_INF("RX: 0x%x", rc);
    zcbor_map_start_encode(cbor_state, 10);
    zcbor_tstr_put_lit_cast(cbor_state, "rc");
    zcbor_uint32_put(cbor_state, rc);
    zcbor_int32_put(cbor_state, rc);
    if (rc == 0) {
        zcbor_tstr_put_lit_cast(cbor_state, "off");
        zcbor_uint32_put(cbor_state, curr_off);
@@ -578,7 +581,7 @@ bs_rc_rsp(int rc_code)
{
    zcbor_map_start_encode(cbor_state, 10);
    zcbor_tstr_put_lit_cast(cbor_state, "rc");
    zcbor_uint32_put(cbor_state, rc_code);
    zcbor_int32_put(cbor_state, rc_code);
    zcbor_map_end_encode(cbor_state, 10);
    boot_serial_output();
}
@@ -732,8 +735,8 @@ boot_serial_output(void)
    crc =  crc16_itu_t(crc, data, len);
#elif __ESPRESSIF__
    /* For ESP32 it was used the CRC API in rom/crc.h */
    crc =  ~crc16_be(~CRC16_INITIAL_CRC, (uint8_t *)bs_hdr, sizeof(*bs_hdr));
    crc =  ~crc16_be(~crc, (uint8_t *)data, len);
    crc =  ~esp_crc16_be(~CRC16_INITIAL_CRC, (uint8_t *)bs_hdr, sizeof(*bs_hdr));
    crc =  ~esp_crc16_be(~crc, (uint8_t *)data, len);
#else
    crc = crc16_ccitt(CRC16_INITIAL_CRC, bs_hdr, sizeof(*bs_hdr));
    crc = crc16_ccitt(crc, data, len);
@@ -819,7 +822,7 @@ boot_serial_in_dec(char *in, int inlen, char *out, int *out_off, int maxout)
#ifdef __ZEPHYR__
    crc = crc16_itu_t(CRC16_INITIAL_CRC, out, len);
#elif __ESPRESSIF__
    crc = ~crc16_be(~CRC16_INITIAL_CRC, (uint8_t *)out, len);
    crc = ~esp_crc16_be(~CRC16_INITIAL_CRC, (uint8_t *)out, len);
#else
    crc = crc16_ccitt(CRC16_INITIAL_CRC, out, len);
#endif
+1 −1
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ bootutil_find_key(uint8_t image_index, uint8_t *key, uint16_t key_len)

    rc = boot_retrieve_public_key_hash(image_index, key_hash, &key_hash_size);
    if (rc) {
        return rc;
        return -1;
    }

    /* Adding hardening to avoid this potential attack:
+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@
list(APPEND hal_srcs
    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/regi2c_ctrl.c
    ${esp_idf_dir}/components/efuse/src/esp_efuse_api_key_esp32xx.c
    ${esp_idf_dir}/components/esp_rom/patches/esp_rom_crc.c
    )

list(APPEND LINKER_SCRIPTS
+3 −13
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@
#include "esp_rom_gpio.h"

#include "bootloader_init.h"
#include "bootloader_common.h"
#include "bootloader_console.h"
#include "bootloader_mem.h"
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
@@ -120,18 +122,6 @@ static esp_err_t bootloader_init_spi_flash(void)
    return ESP_OK;
}

static void bootloader_init_uart_console(void)
{
    const int uart_num = 0;

    uartAttach(NULL);
    ets_install_uart_printf();
    uart_tx_wait_idle(0);

    const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
    uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
}

static void bootloader_super_wdt_auto_feed(void)
{
    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
@@ -158,7 +148,7 @@ esp_err_t bootloader_init(void)
    /* config clock */
    bootloader_clock_configure();
    /* initialize uart console, from now on, we can use ets_printf */
    bootloader_init_uart_console();
    bootloader_console_init();
    /* read bootloader header */
    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
        goto err;
+3 −11
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@
#include "esp_efuse.h"

#include "bootloader_init.h"
#include "bootloader_common.h"
#include "bootloader_console.h"
#include "bootloader_mem.h"
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
@@ -142,16 +144,6 @@ static esp_err_t bootloader_init_spi_flash(void)
    return ESP_OK;
}

static void bootloader_init_uart_console(void)
{
    const int uart_num = 0;

    esp_rom_install_uart_printf();
    esp_rom_uart_tx_wait_idle(0);
    uint32_t clock_hz = UART_CLK_FREQ_ROM;
    esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}

static void wdt_reset_cpu0_info_enable(void)
{
    REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
@@ -261,7 +253,7 @@ esp_err_t bootloader_init(void)
    // config clock
    bootloader_clock_configure();
    /* initialize uart console, from now on, we can use ets_printf */
    bootloader_init_uart_console();
    bootloader_console_init();
    // Check and run XMC startup flow
    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
       goto err;
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