Commit d532029c authored by Almir Okato's avatar Almir Okato Committed by Fabio Utzig
Browse files

espressif: Add ESP32-S2 initial basic support 



ESP32S2 target added to the Espressif port, modified CMakeLists,
and added the bootloader related files to esp32s2 target directory.

Signed-off-by: default avatarAlmir Okato <almir.okato@espressif.com>
parent 056d9bc8

boot/espressif/hal/CMakeLists.txt

+26 −6
Original line number Diff line number Diff line
@@ -7,11 +7,13 @@ set(esp_idf_dir ${IDF_PATH}) 
set(SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src)

set(INCLUDE_DIRS

    ${CMAKE_CURRENT_LIST_DIR}/include

    ${CMAKE_CURRENT_LIST_DIR}/include/${MCUBOOT_TARGET})

    ${CMAKE_CURRENT_LIST_DIR}/include/${MCUBOOT_TARGET}

    )



list(APPEND INCLUDE_DIRS

    ${esp_idf_dir}/components/esp_common/include

    ${esp_idf_dir}/components/esp_rom/include

    ${esp_idf_dir}/components/esp_rom/include/${MCUBOOT_TARGET}

    ${esp_idf_dir}/components/xtensa/${MCUBOOT_TARGET}/include

    ${esp_idf_dir}/components/spi_flash/include

    ${esp_idf_dir}/components/spi_flash/private_include
@@ -21,6 +23,7 @@ list(APPEND INCLUDE_DIRS 
    ${esp_idf_dir}/components/soc/include

    ${esp_idf_dir}/components/esp_hw_support/include

    ${esp_idf_dir}/components/hal/${MCUBOOT_TARGET}/include

    ${esp_idf_dir}/components/hal/${MCUBOOT_TARGET}/include/hal

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/private_include

    ${esp_idf_dir}/components/bootloader_support/include
@@ -30,8 +33,8 @@ list(APPEND INCLUDE_DIRS 
    ${esp_idf_dir}/components/efuse/${MCUBOOT_TARGET}/include

    )

set(hal_srcs

    ${SRC_DIR}/bootloader_init.c

    ${SRC_DIR}/bootloader_wdt.c

    ${SRC_DIR}/${MCUBOOT_TARGET}/bootloader_init.c

    ${esp_idf_dir}/components/hal/mpu_hal.c

    ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash.c

    ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash_config_${MCUBOOT_TARGET}.c
@@ -50,6 +53,12 @@ set(hal_srcs 
    ${esp_idf_dir}/components/${MCUBOOT_TARGET}/clk.c

    )



if ("${MCUBOOT_TARGET}" STREQUAL "esp32s2")

    list(APPEND hal_srcs

        ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/regi2c_ctrl.c

    )

endif()



set(CFLAGS

    "-nostdlib"

    "-mlongcalls"
@@ -97,6 +106,7 @@ add_library(hal STATIC ${hal_srcs} ${INCLUDE_DIRS}) 
set_source_files_properties(

    ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash.c

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_clk_init.c

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_init.c

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_clk.c

    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_time.c

    PROPERTIES COMPILE_FLAGS
@@ -114,13 +124,23 @@ target_compile_options( 
    ${CFLAGS}

    )



target_link_libraries(

    hal

    PUBLIC

    ${LDFLAGS}

set(LINKER_SCRIPTS

    -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.ld

    -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.libgcc.ld

    -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.api.ld

    -T${esp_idf_dir}/components/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.peripherals.ld

    -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.newlib-funcs.ld

    )



if ("${MCUBOOT_TARGET}" STREQUAL "esp32s2")

    list(APPEND LINKER_SCRIPTS

        -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.spiflash.ld

    )

endif()



target_link_libraries(

    hal

    PUBLIC

    ${LDFLAGS}

    ${LINKER_SCRIPTS}

    )

boot/espressif/hal/include/esp32s2/sdkconfig.h

0 → 100644
+15 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#define BOOTLOADER_BUILD 1

#define CONFIG_IDF_TARGET_ESP32S2 1

#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1

#define CONFIG_ESP32S2_XTAL_FREQ 40

#define CONFIG_MCUBOOT 1

#define NDEBUG 1

#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000

#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200

#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000

boot/espressif/hal/include/mcuboot_config/mcuboot_logging.h

+5 −1
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 


#pragma once



#include "sdkconfig.h"



extern int ets_printf(const char *fmt, ...);



#define MCUBOOT_LOG_LEVEL_OFF      0
@@ -14,8 +16,10 @@ extern int ets_printf(const char *fmt, ...); 
#define MCUBOOT_LOG_LEVEL_INFO     3

#define MCUBOOT_LOG_LEVEL_DEBUG    4



#if (MCUBOOT_TARGET == esp32)

#if CONFIG_IDF_TARGET_ESP32

#define TARGET "[esp32]"

#elif CONFIG_IDF_TARGET_ESP32S2

#define TARGET "[esp32s2]"

#else

#error "Selected target not supported."

#endif

boot/espressif/hal/src/bootloader_init.c→boot/espressif/hal/src/esp32/bootloader_init.c

+4 −4
Original line number Diff line number Diff line
@@ -23,10 +23,10 @@ 


#include "hal/wdt_hal.h"



#include "esp32/rom/cache.h"

#include "esp32/rom/ets_sys.h"

#include "esp32/rom/spi_flash.h"

#include "esp32/rom/uart.h"

#include "rom/cache.h"

#include "rom/ets_sys.h"

#include "rom/spi_flash.h"

#include "rom/uart.h"



esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;

boot/espressif/hal/src/esp32s2/bootloader_init.c

0 → 100644
+208 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <stdint.h>

#include <string.h>

#include "sdkconfig.h"

#include "esp_attr.h"

#include "esp_image_format.h"



#include "esp_rom_efuse.h"

#include "esp_rom_gpio.h"



#include "bootloader_init.h"

#include "bootloader_mem.h"

#include "bootloader_clock.h"

#include "bootloader_flash_config.h"

#include "bootloader_flash.h"

#include "bootloader_flash_priv.h"



#include "soc/dport_reg.h"

#include "soc/efuse_reg.h"

#include "soc/rtc.h"

#include "soc/extmem_reg.h"

#include "soc/io_mux_reg.h"



#include "hal/wdt_hal.h"



#include "rom/cache.h"

#include "rom/ets_sys.h"

#include "rom/spi_flash.h"

#include "rom/uart.h"



esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;



void bootloader_clear_bss_section(void)

{

    memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));

}



static void bootloader_reset_mmu(void)

{

    Cache_Suspend_ICache();

    Cache_Invalidate_ICache_All();

    Cache_MMU_Init();



    /* normal ROM boot exits with DROM0 cache unmasked,

    but serial bootloader exits with it masked. */

    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);

}



esp_err_t bootloader_read_bootloader_header(void)

{

    if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {

        return ESP_FAIL;

    }

    return ESP_OK;

}



static void update_flash_config(const esp_image_header_t *bootloader_hdr)

{

    uint32_t size;

    switch (bootloader_hdr->spi_size) {

    case ESP_IMAGE_FLASH_SIZE_1MB:

        size = 1;

        break;

    case ESP_IMAGE_FLASH_SIZE_2MB:

        size = 2;

        break;

    case ESP_IMAGE_FLASH_SIZE_4MB:

        size = 4;

        break;

    case ESP_IMAGE_FLASH_SIZE_8MB:

        size = 8;

        break;

    case ESP_IMAGE_FLASH_SIZE_16MB:

        size = 16;

        break;

    default:

        size = 2;

    }

    uint32_t autoload = Cache_Suspend_ICache();

    // Set flash chip size

    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);

    Cache_Resume_ICache(autoload);

}



void IRAM_ATTR bootloader_configure_spi_pins(int drv)

{

    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();

    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();

    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;

    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;

    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;

    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;

    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;

    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;

    if (spiconfig != 0) {

        clk_gpio_num = spiconfig         & 0x3f;

        q_gpio_num = (spiconfig >> 6)    & 0x3f;

        d_gpio_num = (spiconfig >> 12)   & 0x3f;

        cs0_gpio_num = (spiconfig >> 18) & 0x3f;

        hd_gpio_num = (spiconfig >> 24)  & 0x3f;

        wp_gpio_num = wp_pin;

    }

    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);

    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);

    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);

    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);

    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {

        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);

    }

    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {

        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);

    }

}



static void IRAM_ATTR bootloader_init_flash_configure(void)

{

    bootloader_flash_dummy_config(&bootloader_image_hdr);

    bootloader_flash_cs_timing_config();

}



static esp_err_t bootloader_init_spi_flash(void)

{

    bootloader_init_flash_configure();

    esp_rom_spiflash_unlock();



    update_flash_config(&bootloader_image_hdr);

    return ESP_OK;

}



void bootloader_config_wdt(void)

{

    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};

    wdt_hal_write_protect_disable(&rtc_wdt_ctx);

    wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false);

    wdt_hal_write_protect_enable(&rtc_wdt_ctx);



#ifdef CONFIG_ESP_MCUBOOT_WDT_ENABLE

    wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);

    uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);

    wdt_hal_write_protect_disable(&rtc_wdt_ctx);

    wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);

    wdt_hal_enable(&rtc_wdt_ctx);

    wdt_hal_write_protect_enable(&rtc_wdt_ctx);

#endif



    wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};

    wdt_hal_write_protect_disable(&wdt_ctx);

    wdt_hal_set_flashboot_en(&wdt_ctx, false);

    wdt_hal_write_protect_enable(&wdt_ctx);

}



static void bootloader_init_uart_console(void)

{

    const int uart_num = 0;



    uartAttach(NULL);

    ets_install_uart_printf();

    uart_tx_wait_idle(0);



    const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;

    uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);

}



static void bootloader_super_wdt_auto_feed(void)

{

    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);

}



esp_err_t bootloader_init(void)

{

    esp_err_t ret = ESP_OK;

    bootloader_super_wdt_auto_feed();



    bootloader_init_mem();



    /* check that static RAM is after the stack */

#ifndef NDEBUG

    {

        assert(&_bss_start <= &_bss_end);

        assert(&_data_start <= &_data_end);

    }

#endif

    /* clear bss section */

    bootloader_clear_bss_section();

    /* reset MMU */

    bootloader_reset_mmu();

    /* config clock */

    bootloader_clock_configure();

    /* initialize uart console, from now on, we can use ets_printf */

    bootloader_init_uart_console();

    /* read bootloader header */

    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {

        goto err;

    }

    /* initialize spi flash */

    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {

        goto err;

    }

    /* config WDT */

    bootloader_config_wdt();

err:

    return ret;

}

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