Commit cd22b693 authored by Sylvio Alves's avatar Sylvio Alves Committed by almir-okato
Browse files

espressif: extend loader data 



Add additional regions in loader to include
RTC, LP, IROM and DROM information.

Signed-off-by: default avatarSylvio Alves <sylvio.alves@espressif.com>
parent 0cd1d0a4

boot/espressif/hal/include/esp_mcuboot_image.h

+21 −8
Original line number Diff line number Diff line
@@ -23,4 +23,17 @@ typedef struct esp_image_load_header { 
    uint32_t dram_dest_addr;           /* Destination address(VMA) for DRAM region */

    uint32_t dram_flash_offset;        /* Flash offset(LMA) for start of DRAM region */

    uint32_t dram_size;                /* Size of DRAM region */

    uint32_t lp_rtc_iram_dest_addr;    /* Destination address (VMA) for LP_IRAM region */

    uint32_t lp_rtc_iram_flash_offset; /* Flash offset (LMA) for LP_IRAM region */

    uint32_t lp_rtc_iram_size;         /* Size of LP_IRAM region */

    uint32_t lp_rtc_dram_dest_addr;    /* Destination address (VMA) for LP_DRAM region */

    uint32_t lp_rtc_dram_flash_offset; /* Flash offset (LMA) for LP_DRAM region */

    uint32_t lp_rtc_dram_size;         /* Size of LP_DRAM region */

    uint32_t irom_map_addr;            /* Mapped address (VMA) for IROM region */

    uint32_t irom_flash_offset;        /* Flash offset (LMA) for IROM region */

    uint32_t irom_size;                /* Size of IROM region */

    uint32_t drom_map_addr;            /* Mapped address (VMA) for DROM region */

    uint32_t drom_flash_offset;        /* Flash offset (LMA) for DROM region */

    uint32_t drom_size;                /* Size of DROM region */

    uint32_t _reserved[4];             /* Up to 24 words reserved for the header */

} esp_image_load_header_t;

boot/espressif/port/esp32s2/ld/bootloader.ld

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ MEMORY 
{

  iram_seg (RWX) :                  org = 0x40047000, len = 0x9000

  iram_loader_seg (RWX) :           org = 0x40050000, len = 0x6000

  dram_seg (RW) :                   org = 0x3FFE6000, len = 0x9000

  dram_seg (RW) :                   org = 0x3FFE6000, len = 0x9A00

}



/*  Default entry point:  */

boot/espressif/port/esp_loader.c

+65 −0
Original line number Diff line number Diff line
@@ -23,6 +23,24 @@ 
#include "app_cpu_start.h"

#endif



#include "esp_rom_sys.h"

#include "esp_cpu.h"



#if CONFIG_IDF_TARGET_ESP32

#define LP_RTC_PREFIX "RTC"

#elif CONFIG_IDF_TARGET_ESP32S2

#define LP_RTC_PREFIX "RTC"

#elif CONFIG_IDF_TARGET_ESP32S3

#define LP_RTC_PREFIX "RTC"

#elif CONFIG_IDF_TARGET_ESP32C2

#elif CONFIG_IDF_TARGET_ESP32C3

#define LP_RTC_PREFIX "RTC"

#elif CONFIG_IDF_TARGET_ESP32C6

#define LP_RTC_PREFIX "LP"

#elif CONFIG_IDF_TARGET_ESP32H2

#define LP_RTC_PREFIX "LP"

#endif



static int load_segment(const struct flash_area *fap, uint32_t data_addr, uint32_t data_len, uint32_t load_addr)

{

    const uint32_t *data = (const uint32_t *)bootloader_mmap((fap->fa_off + data_addr), data_len);
@@ -69,6 +87,26 @@ void esp_app_image_load(int image_index, int slot, unsigned int hdr_offset, unsi 
        FIH_PANIC;

    }



#if SOC_RTC_FAST_MEM_SUPPORTED

    if (load_header.lp_rtc_iram_size > 0) {

        if (!esp_ptr_in_rtc_iram_fast((void *)load_header.lp_rtc_iram_dest_addr) ||

            !esp_ptr_in_rtc_iram_fast((void *)(load_header.lp_rtc_iram_dest_addr + load_header.lp_rtc_iram_size))) {

            BOOT_LOG_ERR("%s_IRAM region in load header is not valid. Aborting", LP_RTC_PREFIX);

            FIH_PANIC;

        }

    }

#endif



#if SOC_RTC_SLOW_MEM_SUPPORTED

    if (load_header.lp_rtc_dram_size > 0) {

        if (!esp_ptr_in_rtc_slow((void *)load_header.lp_rtc_dram_dest_addr) ||

            !esp_ptr_in_rtc_slow((void *)(load_header.lp_rtc_dram_dest_addr + load_header.lp_rtc_dram_size))) {

            BOOT_LOG_ERR("%s_RAM region in load header is not valid. Aborting %p", LP_RTC_PREFIX, load_header.lp_rtc_dram_dest_addr);

            FIH_PANIC;

        }

    }

#endif



    if (!esp_ptr_in_iram((void *)load_header.entry_addr)) {

        BOOT_LOG_ERR("Application entry point (0x%x) is not in IRAM. Aborting", load_header.entry_addr);

        FIH_PANIC;
@@ -80,6 +118,33 @@ void esp_app_image_load(int image_index, int slot, unsigned int hdr_offset, unsi 
    BOOT_LOG_INF("IRAM segment: start=0x%x, size=0x%x, vaddr=0x%x", fap->fa_off + load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);

    load_segment(fap, load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);



#if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED

    if (load_header.lp_rtc_dram_size > 0) {

        soc_reset_reason_t reset_reason = esp_rom_get_reset_reason(0);



        /* Unless waking from deep sleep (implying RTC memory is intact), load its segments */

        if (reset_reason != RESET_REASON_CORE_DEEP_SLEEP) {

            BOOT_LOG_INF("%s_RAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", LP_RTC_PREFIX,

                         (fap->fa_off + load_header.lp_rtc_dram_flash_offset), load_header.lp_rtc_dram_dest_addr,

                         load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_size);

            load_segment(fap, load_header.lp_rtc_dram_flash_offset,

                         load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_dest_addr);

        } else {

            BOOT_LOG_INF("%s_RAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) noload", LP_RTC_PREFIX,

                         load_header.lp_rtc_dram_flash_offset, load_header.lp_rtc_dram_dest_addr,

                         load_header.lp_rtc_dram_size, load_header.lp_rtc_dram_size);

        }

    }



    if (load_header.lp_rtc_iram_size > 0) {

        BOOT_LOG_INF("%s_IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", LP_RTC_PREFIX,

                     (fap->fa_off + load_header.lp_rtc_iram_flash_offset), load_header.lp_rtc_iram_dest_addr,

                     load_header.lp_rtc_iram_size, load_header.lp_rtc_iram_size);

        load_segment(fap, load_header.lp_rtc_iram_flash_offset,

                     load_header.lp_rtc_iram_size, load_header.lp_rtc_iram_dest_addr);

    }

#endif



    BOOT_LOG_INF("start=0x%x", load_header.entry_addr);

    uart_tx_wait_idle(0);

docs/release-notes.d/espressif-idf-version-checking.md

+1 −0
Original line number Diff line number Diff line 
- Added verification for supported IDF-based HAL version.

- Fixed missing macro for XMC flash devices on ESP32-S3

- Extended image loader header to include RTC/LP RAM, DROM and IROM segments.

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