Merge pull request #60 from d3zd3z/zephyr-to-1.8 (c6153874) · Commits · Wenxi XU / Mcuboot

.github/workflows/fih_tests.yaml

0 → 100644

+49 −0

Original line number	Diff line number	Diff line
		on:
		push:
		branches:
		- main
		pull_request:

		name: FIH hardening

		jobs:
		config:
		strategy:
		matrix:
		fih_env:
		# FIH environment must use the following space separated format:
		# BUILD_TYPE SKIP_SIZE DAMAGE_TYPE FIH_LEVEL(optional)
		- "RELEASE 2,4,6,8,10 SIGNATURE"
		- "RELEASE 2,4,6,8,10 SIGNATURE LOW"
		- "RELEASE 2,4,6,8,10 SIGNATURE MEDIUM"
		- "MINSIZEREL 2,4,6 SIGNATURE"
		- "MINSIZEREL 2,4,6 SIGNATURE LOW"
		- "MINSIZEREL 2,4,6 SIGNATURE MEDIUM"
		- "MINSIZEREL 8,10 SIGNATURE"
		- "MINSIZEREL 8,10 SIGNATURE LOW"
		- "MINSIZEREL 8,10 SIGNATURE MEDIUM"
		runs-on: ubuntu-latest
		steps:
		- uses: actions/checkout@v2
		with:
		fetch-depth: 0
		# Uses Mbed TLS from TFM, and nothing else from here.
		submodules: false
		- name: Print the environment
		run: \|
		uname -a
		lscpu
		free
		pwd
		- name: Signed commit check
		if: ${{ github.event_name == 'pull_request' }}
		run: \|
		./ci/check-signed-off-by.sh
		- name: FIH hardening test install
		run: \|
		./ci/fih-tests_install.sh
		- name: FIH hardening test run
		env:
		FIH_ENV: ${{ matrix.fih_env }}
		run: \|
		./ci/fih-tests_run.sh

+4 −0

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		@@ -33,6 +33,10 @@ jobs:
		- "sig-ecdsa-mbedtls enc-ec256-mbedtls validate-primary-slot"
		- "sig-ecdsa-mbedtls enc-aes256-ec256 validate-primary-slot"
		- "sig-rsa validate-primary-slot overwrite-only downgrade-prevention"
		- "sig-rsa validate-primary-slot ram-load"
		- "sig-rsa validate-primary-slot direct-xip"
		- "sig-rsa validate-primary-slot ram-load multiimage"
		- "sig-rsa validate-primary-slot direct-xip multiimage"
		runs-on: ubuntu-latest
		env:
		MULTI_FEATURES: ${{ matrix.features }}

+3 −0

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		@@ -25,3 +25,6 @@ rusty-tags.*
		# Python egg metadata, regenerated from source files by setuptools.
		/scripts/*.egg-info
		/scripts/*.egg

		# The target directory from Rust development
		/target/

+4 −0

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		@@ -22,3 +22,7 @@
		[submodule "ext/cddl-gen"]
		path = ext/cddl-gen
		url = https://github.com/NordicSemiconductor/cddl-gen.git
		[submodule "boot/espressif/hal/esp-idf"]
		path = boot/espressif/hal/esp-idf
		url = https://github.com/espressif/esp-idf.git
		branch = release/v4.3

+3 −1