Commit 75958ecf authored May 20, 2022 by Ryan McClelland Committed by Andrzej Puzdrowski May 24, 2022

boot: zephyr: add Kconfig for arm cortex-m that implements a cache

The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.

Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>

parent ccd490ca

boot/zephyr/main.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -196,7 +196,7 @@ static void do_boot(struct boot_rsp *rsp)
		#if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
		cleanup_arm_nvic(); /* cleanup NVIC registers */

		#ifdef CONFIG_CPU_CORTEX_M7
		#ifdef CONFIG_CPU_CORTEX_M_HAS_CACHE
		/* Disable instruction cache and data cache before chain-load the application */
		SCB_DisableDCache();
		SCB_DisableICache();