diff --git a/stm32cube/stm32f7xx/README b/stm32cube/stm32f7xx/README
index c7a2773ea515598a84449d53a8c3601c80bf888d..2314beb2ed27937c957d0c665819f98d5b011b4a 100644
--- a/stm32cube/stm32f7xx/README
+++ b/stm32cube/stm32f7xx/README
@@ -6,7 +6,7 @@ Origin:
http://www.st.com/en/embedded-software/stm32cubef7.html
Status:
- version 1.12.0
+ version 1.15.0
Purpose:
ST Microelectronics official MCU package for STM32F7 series.
@@ -23,7 +23,7 @@ URL:
http://www.st.com/en/embedded-software/stm32cubef7.html
commit:
- version 1.12.0
+ version 1.15.0
Maintained-by:
External
@@ -36,19 +36,6 @@ License Link:
Patch List:
- *Current implementation of LL_SPI_TransmitData16 on F3/F7/L4 family
- generates following warning:
- "warning: dereferencing type-punned pointer will break strict-aliasing
- rules [-Wstrict-aliasing]"
- Besides being forbidden by rule, this cast is not needed, as register is
- 16 bits wide. Modification has been tested on L4 SoC.
- stm32yyxx_ll_spi.h being included in soc.h file, warning is generated
- at each compiled object, this commit allows a clean build.
- Impacted files:
- drivers/include/stm32f7xx_ll_spi.h
- ST Bug tracker ID: 13359
-
-
*Disable new CAN API and enable Legacy API
A new CAN API has been delivered on recent F7 stm32cube.
This new API breaks current CAN driver. Disable the new API and enable the
diff --git a/stm32cube/stm32f7xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32f7xx/drivers/include/Legacy/stm32_hal_legacy.h
index 5aa10ce3468c9fa38dd974f45ed8286a3fc47d2b..889db8f18f339bdb159c058cd58a96ff96134c02 100644
--- a/stm32cube/stm32f7xx/drivers/include/Legacy/stm32_hal_legacy.h
+++ b/stm32cube/stm32f7xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -7,36 +7,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
#ifdef __cplusplus
extern "C" {
@@ -110,6 +94,10 @@
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
/**
* @}
*/
@@ -274,7 +262,100 @@
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#endif /* STM32L4 */
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#endif /* STM32H7 */
/**
* @}
@@ -355,6 +436,38 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
/**
* @}
@@ -386,7 +499,7 @@
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#else
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
@@ -427,16 +540,25 @@
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+#endif
+
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -456,78 +578,6 @@
* @}
*/
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
- #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
- #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
- #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
- #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
- #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
- #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-
- #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
- #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
- #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
- #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
- #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
- #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
- #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
- #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
- #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-
-#endif /* STM32H7 */
-
-
-/**
- * @}
- */
-
-
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@@ -564,7 +614,7 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -696,6 +746,16 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+ #define I2S_IT_TXE I2S_IT_TXP
+ #define I2S_IT_RXNE I2S_IT_RXP
+
+ #define I2S_FLAG_TXE I2S_FLAG_TXP
+ #define I2S_FLAG_RXNE I2S_FLAG_RXP
+ #define I2S_FLAG_FRE I2S_FLAG_TIFRE
+#endif
+
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
@@ -820,6 +880,21 @@
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+ #define SPI_IT_TXE SPI_IT_TXP
+ #define SPI_IT_RXNE SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -887,6 +962,15 @@
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
/**
* @}
*/
@@ -1047,8 +1131,9 @@
* @}
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1072,7 +1157,7 @@
/**
* @}
*/
-#endif /* STM32L4 || STM32F7*/
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@@ -1164,6 +1249,28 @@
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
/**
* @}
*/
@@ -1243,6 +1350,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
/**
* @}
*/
@@ -1456,10 +1571,17 @@
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#if defined(STM32H7)
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
@@ -1725,6 +1847,10 @@
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+#if defined(STM32H7)
+ #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
/**
* @}
*/
@@ -2120,6 +2246,20 @@
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2790,6 +2930,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -2917,8 +3058,10 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
+#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
@@ -3047,6 +3190,7 @@
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
#endif
/**
* @}
@@ -3236,10 +3380,7 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
-#if defined(STM32F7)
-#else
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-#endif
/**
* @}
*/
@@ -3277,6 +3418,21 @@
* @}
*/
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
@@ -3289,7 +3445,7 @@
}
#endif
-#endif /* ___STM32_HAL_LEGACY */
+#endif /* STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/Legacy/stm32f7xx_hal_can_legacy.h b/stm32cube/stm32f7xx/drivers/include/Legacy/stm32f7xx_hal_can_legacy.h
index 1a1697a14d2e13acdbf7fef56962e53b40182107..76b6385d4851dfbbe43f982cea8c19a3a7c01336 100644
--- a/stm32cube/stm32f7xx/drivers/include/Legacy/stm32f7xx_hal_can_legacy.h
+++ b/stm32cube/stm32f7xx/drivers/include/Legacy/stm32f7xx_hal_can_legacy.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32_assert_template.h b/stm32cube/stm32f7xx/drivers/include/stm32_assert_template.h
index d14016f7f015b4caf8757236fe5e7dde5353b192..4711b65d8f92aad7451e91ba385a3a1625ca737a 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32_assert_template.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32_assert_template.h
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal.h
index 19d99ed9fb30e94f17534ed23ca4839442bd4625..b32105260fbda162273c64e5f71ecc30f91fa578 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal.h
@@ -7,29 +7,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -204,6 +188,17 @@ HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+/**
+ * @}
+ */
+
+ /* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc.h
index cd94151d71163acb6d49b4c24c7cd15f37f55203..52a95434cdc96eca759387dfcc5226e9b6aa7433 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -72,54 +56,54 @@
*/
typedef struct
{
- uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
- all the ADCs.
- This parameter can be a value of @ref ADC_ClockPrescaler */
- uint32_t Resolution; /*!< Configures the ADC resolution.
- This parameter can be a value of @ref ADC_Resolution */
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
- This parameter can be a value of @ref ADC_Data_Align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be a value of @ref ADC_Scan_mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
- This parameter can be a value of @ref ADC_EOCSelection.
- Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
- Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
- or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
- Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
- If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge by default.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
- uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
- If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
- This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
- or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
- This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
+ all the ADCs.
+ This parameter can be a value of @ref ADC_ClockPrescaler */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADC_Data_Align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADC_Scan_mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADC_EOCSelection.
+ Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+ Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+ or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+ Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+ If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge by default.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ This parameter can be set to ENABLE or DISABLE. */
}ADC_InitTypeDef;
@@ -162,7 +146,7 @@ typedef struct
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
This parameter can be a value of @ref ADC_channels */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
+ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
@@ -205,7 +189,11 @@ typedef struct
/**
* @brief ADC handle Structure definition
*/
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
typedef struct
+#endif
{
ADC_TypeDef *Instance; /*!< Register base address */
@@ -220,7 +208,40 @@ typedef struct
__IO uint32_t State; /*!< ADC communication state */
__IO uint32_t ErrorCode; /*!< ADC Error code */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef;
+
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -238,6 +259,9 @@ typedef struct
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -493,7 +517,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @retval None
*/
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
/**
* @brief Enable the ADC peripheral.
@@ -568,6 +602,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc_ex.h
index a060d89cd57e1591a9c056ced820804ee72093b8..c53e7639f4d373116bb3ea773730a8eef2785482 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_adc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -71,58 +55,58 @@
*/
typedef struct
{
- uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t InjectedRank; /*!< Rank in the injected group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
- Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
- This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
- If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
/**
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_can.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_can.h
index 5b2ef71a5f72889eb4f801e7745b26b9c05833f2..c076e077fda9db1b1b310fd67bbdc7313907cec9 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_can.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_can.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -151,7 +135,7 @@ typedef struct
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set to ENABLE or DISABLE. */
+ This parameter can be a value of @ref CAN_filter_activation */
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
For single CAN instances, this parameter is meaningless.
@@ -233,8 +217,58 @@ typedef struct __CAN_HandleTypeDef
__IO uint32_t ErrorCode; /*!< CAN Error code.
This parameter can be a value of @ref CAN_Error_Code */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
+ void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
+ void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
+ void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
+ void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
+ void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
+ void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
+ void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
+ void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
+ void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
+ void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
+ void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
+ void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
+
+ void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
+ void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
} CAN_HandleTypeDef;
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL CAN common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
+ HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
+ HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
+ HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
+ HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
+ HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
+ HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
+ HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
+ HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
+ HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
+ HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
+
+ HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
+ HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
+
+} HAL_CAN_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CAN Callback pointer definition
+ */
+typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
+
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -272,6 +306,11 @@ typedef struct __CAN_HandleTypeDef
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
+
/**
* @}
*/
@@ -364,6 +403,15 @@ typedef struct __CAN_HandleTypeDef
* @}
*/
+/** @defgroup CAN_filter_activation CAN Filter Activation
+ * @{
+ */
+#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
+#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
+/**
+ * @}
+ */
+
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
@@ -496,7 +544,15 @@ typedef struct __CAN_HandleTypeDef
* @param __HANDLE__ CAN handle.
* @retval None
*/
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_CAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @brief Enable the specified CAN interrupts.
@@ -587,6 +643,12 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/**
* @}
*/
@@ -732,12 +794,16 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#if defined(CAN2)
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#endif
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+ ((ACTIVATION) == CAN_FILTER_ENABLE))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cec.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cec.h
index cc683db49cc410c8ff3ee5a7e2f0803fd7a0adda..ed7ee8c55796a0470361530bbea5114cbfa81837 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cec.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cec.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CEC_H
-#define __STM32F7xx_HAL_CEC_H
+#ifndef STM32F7xx_HAL_CEC_H
+#define STM32F7xx_HAL_CEC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -124,11 +108,11 @@ typedef struct
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
-}CEC_InitTypeDef;
+} CEC_InitTypeDef;
/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * @brief HAL CEC State definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -165,27 +149,16 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
+typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+typedef struct __CEC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
@@ -208,7 +181,40 @@ typedef struct
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
-}CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __CEC_HandleTypeDef
+ *hcec); /*!< CEC Tx Transfer completed callback */
+ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
+
+ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
+
+#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
+} CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL CEC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
+ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
+ HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
+ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
+ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
+} HAL_CEC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CEC Callback pointer definition
+ */
+typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
+typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -217,7 +223,25 @@ typedef struct
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+/** @defgroup CEC_State_Definition CEC State Code Definition
+ * @{
+ */
+#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
+/**
+ * @}
+ */
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
@@ -231,6 +255,9 @@ typedef struct
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -396,7 +423,7 @@ typedef struct
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -430,11 +457,19 @@ typedef struct
* @param __HANDLE__ CEC handle.
* @retval None
*/
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
-
+#else
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0)
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
@@ -608,6 +643,15 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -616,9 +660,10 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
@@ -703,21 +748,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
* @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
/**
* @}
*/
@@ -744,6 +789,6 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
}
#endif
-#endif /* __STM32F7xx_HAL_CEC_H */
+#endif /* STM32F7xxHAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_conf.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_conf.h
index cdb55f97775e4b248c8667bf04b2d21c2173ef43..8a835ae2e560c84952571b7c9b25d583131a369d 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_conf.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_conf.h
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -52,8 +36,8 @@
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
-/* #define HAL_CAN_MODULE_ENABLED */
-#define HAL_CAN_LEGACY_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_CEC_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
@@ -62,6 +46,7 @@
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
@@ -164,6 +149,45 @@
#define PREFETCH_ENABLE 1U /* To enable prefetch */
#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
@@ -307,6 +331,10 @@
#include "stm32f7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cortex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cortex.h
index d55a22de14c1ca3755eae5b7cda15480ddf0c3bc..6242ed4f57b1f76f20e7209ce43ffbf1cbd6ad6f 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cortex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cortex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc.h
index ec8601774a1207da54c72911375672d585c08285..ece8790235a753a2d746cc2e623e61f94718bccc 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CRC_H
-#define __STM32F7xx_HAL_CRC_H
+#ifndef STM32F7xx_HAL_CRC_H
+#define STM32F7xx_HAL_CRC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,8 +32,7 @@
* @{
*/
-/** @defgroup CRC CRC
- * @brief CRC HAL module driver
+/** @addtogroup CRC
* @{
*/
@@ -58,8 +41,8 @@
* @{
*/
-/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
- * @{
+/**
+ * @brief CRC HAL State Structure definition
*/
typedef enum
{
@@ -68,13 +51,10 @@ typedef enum
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
-}HAL_CRC_StateTypeDef;
-/**
- * @}
- */
+} HAL_CRC_StateTypeDef;
-/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
- * @{
+/**
+ * @brief CRC Init Structure definition
*/
typedef struct
{
@@ -82,46 +62,43 @@ typedef struct
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
- uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
- CRC_POLYLENGTH_32B (32-bit CRC)
- CRC_POLYLENGTH_16B (16-bit CRC)
- CRC_POLYLENGTH_8B (8-bit CRC)
- CRC_POLYLENGTH_7B (7-bit CRC) */
+ @arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
- is set to DEFAULT_INIT_VALUE_ENABLE */
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
- CRC_INPUTDATA_INVERSION_NONE no input data inversion
- CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+ @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
- CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
- CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
-}CRC_InitTypeDef;
-/**
- * @}
- */
+ @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
+} CRC_InitTypeDef;
-/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
- * @{
+/**
+ * @brief CRC Handle Structure definition
*/
typedef struct
{
@@ -135,30 +112,26 @@ typedef struct
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
- CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
- CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
- CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
+
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
must occur if InputBufferFormat is not one of the three values listed above */
-}CRC_HandleTypeDef;
-/**
- * @}
- */
-
+} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC exported constants
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
-#define DEFAULT_CRC32_POLY 0x04C11DB7U
-
+#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
@@ -166,8 +139,7 @@ typedef struct
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
-#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
-
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
@@ -175,10 +147,8 @@ typedef struct
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
-
-
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
@@ -186,20 +156,19 @@ typedef struct
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
-#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
-
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
-/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
-#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
-#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
-#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
-#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
+#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
@@ -207,26 +176,34 @@ typedef struct
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
-#define HAL_CRC_LENGTH_32B 32U
-#define HAL_CRC_LENGTH_16B 16U
-#define HAL_CRC_LENGTH_8B 8U
-#define HAL_CRC_LENGTH_7B 7U
-
+#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
-/** @defgroup CRC_Input_Buffer_Format CRC input buffer format
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
-#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
-#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
-#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
+#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
@@ -234,13 +211,13 @@ typedef struct
/**
* @}
*/
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC exported macros
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
-/** @brief Reset CRC handle state
+/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
@@ -249,155 +226,103 @@ typedef struct
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
- * @retval None.
+ * @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
- * @param __HANDLE__ CRC handle
- * @param __INIT__ 32-bit initial value
- * @retval None.
+ * @param __HANDLE__ CRC handle
+ * @param __INIT__ 32-bit initial value
+ * @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @param __VALUE__ 8-bit value to be stored in the ID register
+ * @param __VALUE__ Value to be stored in the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @retval 8-bit value of the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
-/* Include CRC HAL Extension module */
-#include "stm32f7xx_hal_crc_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-/* Aliases for inter STM32 series compatibility */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
-/**
- * @}
- */
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRC_Private_Types CRC Private Types
- * @{
- */
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRC_Private_Defines CRC Private Defines
- * @{
- */
-
-/**
- * @}
- */
+/* Include CRC HAL Extended module */
+#include "stm32f7xx_hal_crc_ex.h"
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Variables CRC Private Variables
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Constants CRC Private Constants
+/* Initialization and de-initialization functions ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRC_Private_Macros CRC Private Macros
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
-#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
- ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
-#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
- ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
-#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_8B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_7B))
-#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
-
-
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
-
/**
* @}
*/
@@ -414,7 +339,6 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
}
#endif
-#endif /* __STM32F7xx_HAL_CRC_H */
+#endif /* STM32F7xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc_ex.h
index 3b2923c86af52b5b561742b9c5e4162fc7aaf419..f2ebba1f3a7637ab83e38a4dacdd9a0fbc0a77d7 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_crc_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
- * @brief Header file of CRC HAL extension module.
+ * @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CRC_EX_H
-#define __STM32F7xx_HAL_CRC_EX_H
+#ifndef STM32F7xx_HAL_CRC_EX_H
+#define STM32F7xx_HAL_CRC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,74 +32,64 @@
* @{
*/
-/** @defgroup CRCEx CRCEx
+/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
- * @{
- */
-
-/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
-#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
-#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
-#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
-#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
-#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
-/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
-#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
-#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
- ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
-
/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
+ * @}
+ */
-/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
- * @param __HANDLE__ CRC handle
- * @retval None.
+ * @param __HANDLE__ CRC handle
+ * @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
- * @param __HANDLE__ CRC handle
- * @retval None.
+ * @param __HANDLE__ CRC handle
+ * @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
- * @param __HANDLE__ CRC handle
+ * @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
- * @retval None.
+ * @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
@@ -123,23 +97,37 @@
* @}
*/
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+/** @addtogroup CRCEx_Exported_Functions
* @{
*/
-/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
+/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
-/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-
/**
* @}
*/
@@ -148,7 +136,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
* @}
*/
-
/**
* @}
*/
@@ -161,6 +148,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
}
#endif
-#endif /* __STM32F7xx_HAL_CRC_EX_H */
+#endif /* STM32F7xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp.h
index 5a82b3f3d8ea771dc8c4085ce7aa8e13fd691d16..4d00f584a775290aec4f66499e5171acecdce79b 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -41,14 +25,14 @@
extern "C" {
#endif
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
-#if defined (CRYP)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-
+#if defined (AES) || defined (CRYP)
/** @addtogroup CRYP
* @{
*/
@@ -59,761 +43,276 @@
* @{
*/
-/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
- * @{
+/**
+ * @brief CRYP Init Structure definition
*/
typedef struct
{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
-
- uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
-
- uint8_t* pKey; /*!< The key used for encryption/decryption */
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
+ uint32_t* pKey; /*!< The key used for encryption/decryption */
+ uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ AES Algorithm ECB/CBC/CTR/GCM or CCM
+ This parameter can be a value of @ref CRYP_Algorithm_Mode */
+ uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ GCM : also known as Additional Authentication Data
+ CCM : named B1 composed of the associated data length and Associated Data. */
+ uint32_t HeaderSize; /*!< The size of header buffer in word */
+ uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
- uint8_t* pInitVect; /*!< The initialization vector used also as initialization
- counter in CTR mode */
+}CRYP_ConfigTypeDef;
- uint8_t IVSize; /*!< The size of initialization vector.
- This parameter (called nonce size in CCM) is used only
- in AES-128/192/256 encryption/decryption CCM mode */
-
- uint8_t TagSize; /*!< The size of returned authentication TAG.
- This parameter is used only in AES-128/192/256
- encryption/decryption CCM mode */
-
- uint8_t* Header; /*!< The header used in GCM and CCM modes */
-
- uint32_t HeaderSize; /*!< The size of header buffer in bytes */
-
- uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
- This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
-}CRYP_InitTypeDef;
/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
- * @{
+ * @brief CRYP State Structure definition
*/
-
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
- HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
+ HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
}HAL_CRYP_STATETypeDef;
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
- * @{
- */
-
-
-typedef enum
-{
- HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
- HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
- HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase
- This is relevant only with CCM and GCM modes */
-}HAL_PhaseTypeDef;
/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
- * @{
+ * @brief CRYP handle Structure definition
*/
-typedef struct
+typedef struct __CRYP_HandleTypeDef
{
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
-
- CRYP_InitTypeDef Init; /*!< CRYP required parameters */
-
- uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
-
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
-
- HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
-
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-}CRYP_HandleTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Key_Size CRYP Key Size
- * @{
- */
-#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000U)
-#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
-#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-/**
- * @}
- */
+#if defined (CRYP)
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+#else /* AES*/
+ AES_TypeDef *Instance; /*!< AES Register base address */
+#endif /* End AES or CRYP */
-/** @defgroup CRYP_Data_Type CRYP Data Type
- * @{
- */
-#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U)
-#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-/**
- * @}
- */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
- * @{
- */
-#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003CU)
-#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000U)
-#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004U)
-#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008U)
-#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000CU)
-#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010U)
-#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014U)
-#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018U)
-#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001CU)
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020U)
-#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024U)
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028U)
-#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002CU)
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030U)
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034U)
-/**
- * @}
- */
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
-/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
- * @{
- */
-#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
-/**
- * @}
- */
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
- * @{
- */
-#define CRYP_FLAG_BUSY ((uint32_t)0x00000010U) /*!< The CRYP core is currently
- processing a block of data
- or a key preparation (for
- AES decryption). */
-#define CRYP_FLAG_IFEM ((uint32_t)0x00000001U) /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF ((uint32_t)0x00000002U) /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE ((uint32_t)0x00000004U) /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU ((uint32_t)0x00000008U) /*!< Output FIFO is Full */
-#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U) /*!< Output FIFO service raw
- interrupt status */
-#define CRYP_FLAG_INRIS ((uint32_t)0x01000001U) /*!< Input FIFO service raw
- interrupt status */
-/**
- * @}
- */
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-/**
- * @}
- */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
- * @{
- */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
-/** @brief Reset CRYP handle state
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
- * @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
-/**
- * @brief Flush the data FIFO.
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+ uint16_t Size; /*!< length of input data in word */
-/**
- * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param MODE The algorithm mode.
- * @retval None
- */
-#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
+ uint32_t Phase; /*!< CRYP peripheral phase */
-/** @brief Check whether the specified CRYP flag is set or not.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
- * @arg CRYP_FLAG_IFEM: Input FIFO is empty
- * @arg CRYP_FLAG_IFNF: Input FIFO is not full
- * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
- * @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ specifies the interrupt to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
-/**
- * @brief Enable the CRYP interrupt.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ CRYP Interrupt.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-/**
- * @brief Disable the CRYP interrupt.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ CRYP interrupt.
- * @retval None
- */
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-/**
- * @}
- */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-/* Include CRYP HAL Extension module */
-#include "stm32f7xx_hal_cryp_ex.h"
+ void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+}CRYP_HandleTypeDef;
-/** @addtogroup CRYP_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
-/** @addtogroup CRYP_Exported_Functions_Group2
- * @{
- */
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group3
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
+ * @brief HAL CRYP Callback ID enumeration definition
* @{
*/
-/* DES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* DES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* DES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
- * @}
- */
+typedef enum
+{
+ HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */
+ HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */
+ HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */
-/** @addtogroup CRYP_Exported_Functions_Group4
- * @{
- */
-/* TDES encryption/decryption using polling **********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* TDES encryption/decryption using interrupt ********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* TDES encryption/decryption using DMA **************************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
- * @}
- */
+ HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
+ HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-/** @addtogroup CRYP_Exported_Functions_Group5
- * @{
- */
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+}HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group6
+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
+ * @brief HAL CRYP Callback pointer definition
* @{
*/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
-/** @addtogroup CRYP_Exported_Functions_Group7
- * @{
- */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Types CRYP Private Types
- * @{
- */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
+/** @defgroup CRYP_Error_Definition CRYP Error Definition
* @{
*/
-#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
+#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
+#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
-#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
-
-
-#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_1B))
-
-
- /**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* CRYP */
+#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
/**
* @}
*/
-#if defined (AES)
-
-/** @addtogroup STM32F7xx_HAL_Driver
+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
+#if defined(CRYP)
-/** @addtogroup CRYP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
- * @{
- */
-
-/**
- * @brief CRYP Configuration Structure definition
- */
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
-
- uint32_t KeySize; /*!< 128 or 256-bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
-
- uint32_t OperatingMode; /*!< AES operating mode.
- This parameter can be a value of @ref CRYP_AES_OperatingMode */
-
- uint32_t ChainingMode; /*!< AES chaining mode.
- This parameter can be a value of @ref CRYP_AES_ChainingMode */
-
- uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption.
- This parameter can be a value of @ref CRYP_Key_Write */
-
- uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
- Galois Message Authentication Code (GMAC) or Cipher Message
- Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
- the latter is applicable.
- This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
+#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
+#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
+#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
+#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
+#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
- uint8_t* pKey; /*!< Encryption/Decryption Key */
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
- uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC,
- (and CCM when applicable) modes */
-
- uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
-
- uint64_t HeaderSize; /*!< Header size in bytes */
-
-}CRYP_InitTypeDef;
-
-/**
- * @brief HAL CRYP State structures definition
- */
-typedef enum
-{
- HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
- HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
- HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04, /*!< CRYP error state */
- HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */
-}HAL_CRYP_STATETypeDef;
-
-/**
- * @brief HAL CRYP phase structures definition
- */
-typedef enum
-{
- HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
- HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
- HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but
- GCM/GMAC/CMAC(/CCM) initialization phase has not started */
- HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */
- HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */
- HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */
- HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */
- HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */
- HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */
- HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */
-}HAL_PhaseTypeDef;
-
-/**
- * @brief HAL CRYP mode suspend definitions
- */
-typedef enum
-{
- HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */
- HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */
-}HAL_SuspendTypeDef;
-
-
-/**
- * @brief HAL CRYP Error Codes definition
- */
-#define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */
-#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */
-#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */
-#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */
-
-/**
- * @brief CRYP handle Structure definition
- */
-typedef struct
-{
- AES_TypeDef *Instance; /*!< Register base address */
-
- CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */
-
- uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
-
- uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
-
- uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining
- number of bytes to process */
-
- uint32_t CrypOutCount; /*!< Output data size in bytes */
-
- HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC
- (or CCM when applicable) modes.
- Indicates the last phase carried out to ease
- phase transitions */
-
- DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
- HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
-}CRYP_HandleTypeDef;
+#else /* AES*/
+#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
+#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
+#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
+#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
+#endif /* End AES or CRYP */
/**
* @}
*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Key_Size Key size selection
+/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
-#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#if defined(CRYP)
+#define CRYP_KEYSIZE_128B 0x00000000U
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
+#else /* AES*/
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#endif /* End AES or CRYP */
/**
* @}
*/
-/** @defgroup CRYP_Data_Type AES Data Type selection
+/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
-#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) /*!< 32-bit data type (no swapping) */
+#if defined(CRYP)
+#define CRYP_DATATYPE_32B 0x00000000U
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
+#else /* AES*/
+#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
-/**
- * @}
- */
-
- /** @defgroup CRYP_AES_State AES Enable state
- * @{
- */
-#define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */
-#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */
-/**
- * @}
- */
+#endif /* End AES or CRYP */
-/** @defgroup CRYP_AES_OperatingMode AES operating mode
- * @{
- */
-#define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */
-#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
-#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
-#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
-#define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC authentication tag generation */
/**
* @}
*/
-/** @defgroup CRYP_AES_ChainingMode AES chaining mode
+/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */
-#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
-#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
-#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
-#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
-#if defined(AES_CR_NPBLB)
-#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */
-#endif
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Write AES decryption key write-up flag
- * @{
- */
-#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */
-#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */
-/**
- * @}
- */
-
-/** @defgroup CRYP_DMAIN DMA Input phase management enable state
- * @{
- */
-#define CRYP_DMAIN_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Input phase management */
-#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */
-/**
- * @}
- */
-
-/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
- * @{
- */
-#define CRYP_DMAOUT_DISABLE ((uint32_t)0x00000000) /*!< Disable DMA Output phase management */
-#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */
-/**
- * @}
- */
-
+#if defined (CRYP)
+#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
+#else /* AES*/
+#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
+#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
+#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
+#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
+#endif /* End AES or CRYP */
-/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
- * @{
- */
-#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */
-#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */
-/* Definitions duplication for code readibility's sake:
- supported or not supported chain modes are not specified for each phase */
-#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */
-#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
-#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
-#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
/**
* @}
*/
-/** @defgroup CRYP_Flags AES status flags
+/** @defgroup CRYP_Flags CRYP Flags
* @{
*/
-
+#if defined (CRYP)
+/* Flags in the SR register */
+#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
+#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
+ or a key preparation (for AES decryption). */
+/* Flags in the RISR register */
+#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#else /* AES*/
+/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
-/**
- * @}
- */
-
-/** @defgroup CRYP_Clear_Flags AES clearing flags
- * @{
- */
-
+/* clearing flags */
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
-#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
-/**
- * @}
- */
+#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
+#endif /* End AES or CRYP */
-/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
- * @{
- */
-#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
-#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
-/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags
- * @{
- */
-#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
-#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
-#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
-/**
- * @}
- */
/**
* @}
@@ -824,339 +323,307 @@ typedef struct
* @{
*/
-/** @brief Reset CRYP handle state.
+/** @brief Reset CRYP handle state
* @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
- * @brief Enable the CRYP AES peripheral.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
-
-/**
- * @brief Disable the CRYP AES peripheral.
- * @retval None
- */
-#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
-
-/**
- * @brief Set the algorithm operating mode.
- * @param __OPERATING_MODE__ specifies the operating mode
- * This parameter can be one of the following values:
- * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
- * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
- * @arg @ref CRYP_ALGOMODE_DECRYPT decryption
- * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
- * @retval None
- */
-#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
-
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
- * @brief Set the algorithm chaining mode.
- * @param __CHAINING_MODE__ specifies the chaining mode
- * This parameter can be one of the following values:
- * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
- * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
- * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
- * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
- * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
-
-
+#if defined(CRYP)
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
+#else /* AES*/
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * This parameter can be one of the following values for CRYP:
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
-
+#define CRYP_FLAG_MASK 0x0000001FU
+#if defined(CRYP)
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+#else /* AES*/
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#endif /* End AES or CRYP */
/** @brief Clear the CRYP pending status flag.
- * @param __FLAG__ specifies the flag to clear.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
+#if defined(AES)
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
- * @param __INTERRUPT__ CRYP interrupt source to check
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP interrupt source to check
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __INTERRUPT__ specifies the interrupt to check.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
+ * This parameter can be one of the following values for CRYP:
+ * @arg CRYP_IT_INI: Input FIFO service masked interrupt status
+ * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-
-
-/** @brief Clear the CRYP pending interrupt.
- * @param __INTERRUPT__ specifies the IT to clear.
- * This parameter can be one of the following values:
- * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
- * @retval None
- */
-#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
-
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @brief Enable the CRYP interrupt.
- * @param __INTERRUPT__ CRYP Interrupt.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * This parameter can be one of the following values for CRYP:
+ * @ CRYP_IT_INI : Input FIFO service interrupt mask.
+ * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
-
+#if defined(CRYP)
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
- * @param __INTERRUPT__ CRYP Interrupt.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * This parameter can be one of the following values for CRYP:
+ * @ CRYP_IT_INI : Input FIFO service interrupt mask.
+ * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @}
*/
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Macros CRYP Private Macros
+/* Include CRYP HAL Extended module */
+#include "stm32f7xx_hal_cryp_ex.h"
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
- * @brief Verify the key size length.
- * @param __KEYSIZE__ Ciphering/deciphering algorithm key size.
- * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+ * @}
*/
-#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
-/**
- * @brief Verify the input data type.
- * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.
- * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
*/
-#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
/**
- * @brief Verify the CRYP AES IP running mode.
- * @param __MODE__ CRYP AES IP running mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ * @}
*/
-#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
- ((__MODE__) == CRYP_AES_ENABLE))
-/**
- * @brief Verify the selected CRYP algorithm.
- * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
- * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
*/
-#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
+/* Interrupt Handler functions **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
- * @brief Verify the selected CRYP chaining algorithm.
- * @param __CHAINMODE__ Selected CRYP chaining algorithm.
- * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+ * @}
*/
-#if defined(AES_CR_NPBLB)
-#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
-#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
-#endif
/**
- * @brief Verify the deciphering key write option.
- * @param __WRITE__ deciphering key write option.
- * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+ * @}
*/
-#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
- ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
-/**
- * @brief Verify the CRYP input data DMA mode.
- * @param __MODE__ CRYP input data DMA mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
*/
-#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
- ((__MODE__) == CRYP_DMAIN_ENABLE))
-/**
- * @brief Verify the CRYP output data DMA mode.
- * @param __MODE__ CRYP output data DMA mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
+ * @{
*/
-#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
- ((__MODE__) == CRYP_DMAOUT_ENABLE))
+#if defined(CRYP)
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+#else /* AES*/
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
+
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+#endif /* End AES or CRYP */
+
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
+ ((DATATYPE) == CRYP_DATATYPE_16B) || \
+ ((DATATYPE) == CRYP_DATATYPE_8B) || \
+ ((DATATYPE) == CRYP_DATATYPE_1B))
/**
- * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+ * @}
*/
-#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
- ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
- ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
- ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
/**
* @}
*/
-/* Include CRYP HAL Extended module */
-#include "stm32f7xx_hal_cryp_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
-
-/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
* @{
*/
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-
-/* MSP initialization/de-initialization functions ****************************/
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
-
-/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
*/
-/* AES encryption/decryption processing functions ****************************/
-
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
*/
-/* CallBack functions ********************************************************/
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
-/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
*/
-/* AES interrupt handling function *******************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
* @{
*/
-/* Peripheral State functions ************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
+
/**
* @}
*/
+
/**
* @}
*/
+#endif /* TinyAES or CRYP*/
/**
* @}
*/
-#endif /* AES */
-
-
#ifdef __cplusplus
}
#endif
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp_ex.h
index d80a77dfcfecc14ea60286212f59d1dd7360ce8c..3913bf20ae9ba7244e238ce77658417aa9e2ee61 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_cryp_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -44,8 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
-#if defined (CRYP)
-
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -53,110 +35,24 @@
/** @addtogroup CRYPEx
* @{
*/
-
/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants
- * @{
- */
-
-/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
- * @{
- */
-#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000U)
-#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004U)
-#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008U)
-#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000CU)
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
- * @brief The phases are relevant only to AES-GCM and AES-CCM
- * @{
- */
-#define CRYP_PHASE_INIT ((uint32_t)0x00000000U)
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
+/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
-/**
- * @brief Set the phase: Init, header, payload, final.
- * This is relevant only for GCM and CCM modes.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __PHASE__ The phase.
- * @retval None
- */
-#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0)
-
/**
* @}
*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
- * @{
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
- * @{
- */
-
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group2
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
*/
-void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
- /**
- * @}
- */
-
-
- /* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
*/
@@ -201,83 +97,40 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
* @}
*/
-/**
- * @}
- */
-
-#endif /* CRYP */
-
-#if defined (AES)
-
-/** @addtogroup CRYPEx_Exported_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
*/
-
+#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
*/
-
-/* CallBack functions ********************************************************/
-void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
-
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
* @}
*/
+#endif /* CRYP||AES */
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
*/
-
-/* AES encryption/decryption processing functions ****************************/
-HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
-HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
-
-/* AES encryption/decryption/authentication processing functions *************/
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group3
- * @{
- */
-
-/* AES suspension/resumption functions ***************************************/
-void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
-void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
-void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
-
+void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
+#endif /* AES */
/**
* @}
*/
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
- * @{
- */
-HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
-#endif /* AES */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac.h
index 7b9bfa13f31530728d36c42f23bd10f86a47e821..f5fac9ea488e97fc730b9e8e659d24f5335f89b7 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -72,7 +56,11 @@ typedef enum
/**
* @brief DAC handle Structure definition
*/
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
typedef struct
+#endif
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -85,6 +73,19 @@ typedef struct
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+
+ void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}DAC_HandleTypeDef;
@@ -99,6 +100,31 @@ typedef struct
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DAC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
+ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
+ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
+ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
+ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
+ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
+ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+ HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
+}HAL_DAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DAC Callback pointer definition
+ */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -115,6 +141,9 @@ typedef struct
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -194,22 +223,30 @@ typedef struct
*/
/** @brief Reset DAC handle state
- * @param __HANDLE__ specifies the DAC handle.
+ * @param __HANDLE__: specifies the DAC handle.
* @retval None
*/
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel
- * @param __HANDLE__ specifies the DAC handle.
- * @param __DAC_CHANNEL__ specifies the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_CHANNEL__: specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
/** @brief Disable the DAC channel
- * @param __HANDLE__ specifies the DAC handle
- * @param __DAC_CHANNEL__ specifies the DAC channel.
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_CHANNEL__: specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
@@ -217,22 +254,22 @@ typedef struct
/** @brief Enable the DAC interrupt
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
- * @param __HANDLE__ DAC handle
- * @param __INTERRUPT__ DAC interrupt source to check
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -241,8 +278,8 @@ typedef struct
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -251,8 +288,8 @@ typedef struct
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -318,6 +355,11 @@ void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -360,19 +402,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__ specifies the DAC alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac_ex.h
index a1f80cfd9e8a7ed53b9d9eb7c950b96f45d68758..3854fd0efda40b1b64cc1e04f0a657400b140797 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dac_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi.h
index ae7e464e9ff470857a5508760d981323eae01d63..cbfff3dfa4f1fd9a0a21f2a653da963f04c5447a 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -128,7 +112,7 @@ typedef struct
/**
* @brief DCMI handle Structure definition
*/
-typedef struct
+typedef struct __DCMI_HandleTypeDef
{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
@@ -149,8 +133,32 @@ typedef struct
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
__IO uint32_t ErrorCode; /*!< DCMI Error code */
-
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
+ void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
+ void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
+ void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
+ void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
+ void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}DCMI_HandleTypeDef;
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+typedef enum
+{
+ HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
+ HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
+ HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
+ HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
+ HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
+ HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
+
+}HAL_DCMI_CallbackIDTypeDef;
+
+typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
@@ -163,11 +171,14 @@ typedef struct
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
-#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
-#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
-#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
+#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
+#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -373,7 +384,11 @@ typedef struct
* @param __HANDLE__ specifies the DCMI handle.
* @retval None
*/
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
/**
* @brief Enable the DCMI.
@@ -487,6 +502,12 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi_ex.h
index c6653baddb201ca65921d6e91a48fcd1810cb35c..506ce462eab76327751a674e925a46dce51a7028 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dcmi_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_def.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_def.h
index 1f36f034b4feb09c589d1644fb5f241eab397a37..cc53c585b9982c26096f7d1322e11729bad8e8ff 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_def.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_def.h
@@ -7,29 +7,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -45,7 +29,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx.h"
#include "Legacy/stm32_hal_legacy.h"
-#include
+#include
/* Exported types ------------------------------------------------------------*/
@@ -75,8 +59,8 @@ typedef enum
#define HAL_MAX_DELAY 0xFFFFFFFFU
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dfsdm.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dfsdm.h
index c76947dd027e5eaee4d9cb77ac540308f4134f0e..c2783cdcd24e8bb7e91d1eddd276adb8183d3c81 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dfsdm.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dfsdm.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -133,13 +117,40 @@ typedef struct
/**
* @brief DFSDM channel handle structure definition
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Channel_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
+ void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
+ void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
+ void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
+#endif
}DFSDM_Channel_HandleTypeDef;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief DFSDM channel callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
+ HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
+ HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */
+ HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */
+}HAL_DFSDM_Channel_CallbackIDTypeDef;
+
+/**
+ * @brief DFSDM channel callback pointer definition
+ */
+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+#endif
/**
* @brief HAL DFSDM Filter states definition
*/
@@ -205,7 +216,11 @@ typedef struct
/**
* @brief DFSDM filter handle structure definition
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Filter_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
@@ -220,6 +235,17 @@ typedef struct
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
+ void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
+ void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
+ void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
+ void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */
+ void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */
+ void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */
+ void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */
+#endif
}DFSDM_Filter_HandleTypeDef;
/**
@@ -241,6 +267,27 @@ typedef struct
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief DFSDM filter callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
+ HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
+ HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
+ HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
+ HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */
+ HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */
+ HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */
+}HAL_DFSDM_Filter_CallbackIDTypeDef;
+
+/**
+ * @brief DFSDM filter callback pointer definition
+ */
+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+#endif
/**
* @}
*/
@@ -392,6 +439,9 @@ typedef struct
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid callback error occurs */
+#endif
/**
* @}
*/
@@ -460,16 +510,32 @@ typedef struct
*/
/** @brief Reset DFSDM channel handle state.
- * @param __HANDLE__ DFSDM channel handle.
+ * @param __HANDLE__: DFSDM channel handle.
* @retval None
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+#endif
/** @brief Reset DFSDM filter handle state.
- * @param __HANDLE__ DFSDM filter handle.
+ * @param __HANDLE__: DFSDM filter handle.
* @retval None
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+#endif
/**
* @}
@@ -489,6 +555,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Channel callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
+ pDFSDM_Channel_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
+#endif
/**
* @}
*/
@@ -536,6 +611,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Filter callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
+ pDFSDM_Filter_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ pDFSDM_Filter_AwdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma.h
index 6e38a818549e6e4ffa42b5c316c789f74ef2e8d1..b0cf57a096d21ba48eaae5b86bc1500f8af560ca 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma2d.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma2d.h
index 81b72f883be12c74b6594372ce8533ff720c601c..31d5b1a1656be3fddc0d0181f320d046a5850b77 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma2d.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma2d.h
@@ -6,46 +6,30 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DMA2D_H
-#define __STM32F7xx_HAL_DMA2D_H
+#ifndef STM32F7xx_HAL_DMA2D_H
+#define STM32F7xx_HAL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
+#if defined (DMA2D)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
-#if defined (DMA2D)
-
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -59,22 +43,7 @@
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{
*/
-#define MAX_DMA2D_LAYER 2
-
-/**
- * @brief DMA2D color Structure definition
- */
-typedef struct
-{
- uint32_t Blue; /*!< Configures the blue value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Green; /*!< Configures the green value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Red; /*!< Configures the red value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-} DMA2D_ColorTypeDef;
+#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @brief DMA2D CLUT Structure definition
@@ -103,16 +72,18 @@ typedef struct
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
-#if defined (DMA2D_OPFCCR_AI)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
-#endif /* DMA2D_OPFCCR_AI */
-#if defined (DMA2D_OPFCCR_RBS)
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */
-#endif /* DMA2D_OPFCCR_RBS */
+
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+
+
} DMA2D_InitTypeDef;
@@ -139,22 +110,14 @@ typedef struct
- InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
-
-#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
- This parameter can be one value of @ref DMA2D_Alpha_Inverted.
- This feature is only available on devices :
- STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
-
-#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
+ This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
-#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
- This parameter can be one value of @ref DMA2D_RB_Swap
- This feature is only available on devices :
- STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
+ This parameter can be one value of @ref DMA2D_RB_Swap. */
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
-#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
} DMA2D_LayerCfgTypeDef;
@@ -184,6 +147,17 @@ typedef struct __DMA2D_HandleTypeDef
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+
+ void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+
+ void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+
+ void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
@@ -192,6 +166,13 @@ typedef struct __DMA2D_HandleTypeDef
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D Callback pointer definition
+ */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -204,11 +185,15 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
-#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
-#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
-#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
-#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
+#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
+#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
+#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -216,9 +201,9 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
-#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
-#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
@@ -227,7 +212,7 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{
*/
-#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
@@ -239,17 +224,17 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
-#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
-#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
-#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
-#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
-#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
-#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
-#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
-#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
-#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
-#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
-#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
+#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
+#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
+#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
+#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
+#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
+#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
+#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
+#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
/**
* @}
*/
@@ -257,46 +242,47 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
-#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
-#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
/**
* @}
*/
-#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
-/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
* @{
*/
-#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
-#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
+#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */
/**
* @}
*/
-#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
-#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{
*/
-#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
-#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
+#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */
+#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */
/**
* @}
*/
-#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+
+
+
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
-#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
-#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
+#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
-
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
@@ -331,6 +317,21 @@ typedef struct __DMA2D_HandleTypeDef
* @}
*/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
+ HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
+ HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
+ HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
+ HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
+ HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
+}HAL_DMA2D_CallbackIDTypeDef;
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
/**
* @}
@@ -344,7 +345,16 @@ typedef struct __DMA2D_HandleTypeDef
* @param __HANDLE__ specifies the DMA2D handle.
* @retval None
*/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
/**
* @brief Enable the DMA2D.
@@ -448,6 +458,11 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
@@ -530,7 +545,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
-#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
+#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
/**
* @}
*/
@@ -538,7 +553,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{
*/
-#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */
+#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Layers DMA2D Layers
+ * @{
+ */
+#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
+#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
/**
* @}
*/
@@ -546,7 +570,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
-#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
/**
* @}
*/
@@ -554,8 +578,8 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
-#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
-#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
/**
* @}
*/
@@ -563,7 +587,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
-#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
/**
* @}
*/
@@ -577,31 +601,41 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
+
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+
+
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
@@ -624,13 +658,13 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
-#endif /* DMA2D */
+#endif /* defined (DMA2D) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_DMA2D_H */
+#endif /* STM32F7xx_HAL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma_ex.h
index fac7c40a06e2617cd228f2277515dad12217f314..7496b8c38ba967babf53a75e745c142b53a95808 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dma_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dsi.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dsi.h
index 8506413ca9e850ee21d591567a74e096f1061e56..38cb0e5718b422e097ef15ad582bba5a709d53c1 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dsi.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_dsi.h
@@ -6,42 +6,26 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_DSI_H
-#define __STM32F7xx_HAL_DSI_H
+#ifndef STM32F7xx_HAL_DSI_H
+#define STM32F7xx_HAL_DSI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (STM32F769xx) || defined (STM32F779xx)
+#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -60,32 +44,32 @@
*/
typedef struct
{
- uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
- This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
+ uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
+ This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
- uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
- The values 0 and 1 stop the TX_ESC clock generation */
+ uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
+ The values 0 and 1 stop the TX_ESC clock generation */
- uint32_t NumberOfLanes; /*!< Number of lanes
- This parameter can be any value of @ref DSI_Number_Of_Lanes */
+ uint32_t NumberOfLanes; /*!< Number of lanes
+ This parameter can be any value of @ref DSI_Number_Of_Lanes */
-}DSI_InitTypeDef;
+} DSI_InitTypeDef;
/**
* @brief DSI PLL Clock structure definition
*/
typedef struct
{
- uint32_t PLLNDIV; /*!< PLL Loop Division Factor
- This parameter must be a value between 10 and 125 */
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
- uint32_t PLLIDF; /*!< PLL Input Division Factor
- This parameter can be any value of @ref DSI_PLL_IDF */
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
- uint32_t PLLODF; /*!< PLL Output Division Factor
- This parameter can be any value of @ref DSI_PLL_ODF */
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
-}DSI_PLLInitTypeDef;
+} DSI_PLLInitTypeDef;
/**
* @brief DSI Video mode configuration
@@ -114,7 +98,7 @@ typedef struct
This parameter can be any value of @ref DSI_HSYNC_Polarity */
uint32_t VSPolarity; /*!< VSYNC pin polarity
- This parameter can be any value of @ref DSI_VSYNC_Polarity */
+ This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
uint32_t DEPolarity; /*!< Data Enable pin polarity
This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
@@ -163,116 +147,116 @@ typedef struct
uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
This parameter can be any value of @ref DSI_FBTA_acknowledge */
-}DSI_VidCfgTypeDef;
+} DSI_VidCfgTypeDef;
/**
* @brief DSI Adapted command mode configuration
*/
typedef struct
{
- uint32_t VirtualChannelID; /*!< Virtual channel ID */
+ uint32_t VirtualChannelID; /*!< Virtual channel ID */
- uint32_t ColorCoding; /*!< Color coding for LTDC interface
- This parameter can be any value of @ref DSI_Color_Coding */
+ uint32_t ColorCoding; /*!< Color coding for LTDC interface
+ This parameter can be any value of @ref DSI_Color_Coding */
- uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
- pixels. This parameter can be any value between 0x00 and 0xFFFF */
+ uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
+ pixels. This parameter can be any value between 0x00 and 0xFFFFU */
- uint32_t TearingEffectSource; /*!< Tearing effect source
- This parameter can be any value of @ref DSI_TearingEffectSource */
+ uint32_t TearingEffectSource; /*!< Tearing effect source
+ This parameter can be any value of @ref DSI_TearingEffectSource */
- uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
- This parameter can be any value of @ref DSI_TearingEffectPolarity */
+ uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
+ This parameter can be any value of @ref DSI_TearingEffectPolarity */
- uint32_t HSPolarity; /*!< HSYNC pin polarity
- This parameter can be any value of @ref DSI_HSYNC_Polarity */
+ uint32_t HSPolarity; /*!< HSYNC pin polarity
+ This parameter can be any value of @ref DSI_HSYNC_Polarity */
- uint32_t VSPolarity; /*!< VSYNC pin polarity
- This parameter can be any value of @ref DSI_VSYNC_Polarity */
+ uint32_t VSPolarity; /*!< VSYNC pin polarity
+ This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
- uint32_t DEPolarity; /*!< Data Enable pin polarity
- This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
+ uint32_t DEPolarity; /*!< Data Enable pin polarity
+ This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
- uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
- This parameter can be any value of @ref DSI_Vsync_Polarity */
+ uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
+ This parameter can be any value of @ref DSI_Vsync_Polarity */
- uint32_t AutomaticRefresh; /*!< Automatic refresh mode
- This parameter can be any value of @ref DSI_AutomaticRefresh */
+ uint32_t AutomaticRefresh; /*!< Automatic refresh mode
+ This parameter can be any value of @ref DSI_AutomaticRefresh */
- uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
- This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
+ uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
-}DSI_CmdCfgTypeDef;
+} DSI_CmdCfgTypeDef;
/**
* @brief DSI command transmission mode configuration
*/
typedef struct
{
- uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
+ uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
- uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
+ uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
- uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
+ uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
- uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
+ uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
- uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
+ uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
- uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
+ uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
- uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
- This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
+ uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
- uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
+ uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
- uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
+ uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
- uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
+ uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
- uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
- This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
+ uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
+ This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
- uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
- This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
+ uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
+ This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
- uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
- This parameter can be any value of @ref DSI_AcknowledgeRequest */
+ uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
+ This parameter can be any value of @ref DSI_AcknowledgeRequest */
-}DSI_LPCmdTypeDef;
+} DSI_LPCmdTypeDef;
/**
* @brief DSI PHY Timings definition
*/
typedef struct
{
- uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
- to low-power transmission */
+ uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
+ to low-power transmission */
- uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
- to high-speed transmission */
+ uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
+ to high-speed transmission */
- uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
- to low-power transmission */
+ uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
+ to low-power transmission */
- uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
- to high-speed transmission */
+ uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
+ to high-speed transmission */
- uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
+ uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
- uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
- Stop state */
+ uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
+ Stop state */
-}DSI_PHY_TimerTypeDef;
+} DSI_PHY_TimerTypeDef;
/**
* @brief DSI HOST Timeouts definition
@@ -298,7 +282,7 @@ typedef struct
uint32_t BTATimeout; /*!< BTA time-out */
-}DSI_HOST_TimeoutTypeDef;
+} DSI_HOST_TimeoutTypeDef;
/**
* @brief DSI States Structure definition
@@ -310,12 +294,16 @@ typedef enum
HAL_DSI_STATE_ERROR = 0x02U,
HAL_DSI_STATE_BUSY = 0x03U,
HAL_DSI_STATE_TIMEOUT = 0x04U
-}HAL_DSI_StateTypeDef;
+} HAL_DSI_StateTypeDef;
/**
* @brief DSI Handle Structure definition
*/
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+typedef struct __DSI_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
{
DSI_TypeDef *Instance; /*!< Register base address */
DSI_InitTypeDef Init; /*!< DSI required parameters */
@@ -323,7 +311,40 @@ typedef struct
__IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
__IO uint32_t ErrorCode; /*!< DSI Error code */
uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
-}DSI_HandleTypeDef;
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */
+ void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */
+ void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */
+
+ void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */
+ void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+} DSI_HandleTypeDef;
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DSI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */
+ HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */
+
+ HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */
+ HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */
+ HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */
+
+} HAL_DSI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DSI Callback pointer definition
+ */
+typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_DCS_Command DSI DCS Command
@@ -380,9 +401,9 @@ typedef struct
/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
* @{
*/
-#define DSI_VID_MODE_NB_PULSES 0U
-#define DSI_VID_MODE_NB_EVENTS 1U
-#define DSI_VID_MODE_BURST 2U
+#define DSI_VID_MODE_NB_PULSES 0U
+#define DSI_VID_MODE_NB_EVENTS 1U
+#define DSI_VID_MODE_BURST 2U
/**
* @}
*/
@@ -390,8 +411,8 @@ typedef struct
/** @defgroup DSI_Color_Mode DSI Color Mode
* @{
*/
-#define DSI_COLOR_MODE_FULL 0U
-#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
+#define DSI_COLOR_MODE_FULL 0x00000000U
+#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
/**
* @}
*/
@@ -399,8 +420,8 @@ typedef struct
/** @defgroup DSI_ShutDown DSI ShutDown
* @{
*/
-#define DSI_DISPLAY_ON 0U
-#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
+#define DSI_DISPLAY_ON 0x00000000U
+#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
/**
* @}
*/
@@ -408,8 +429,8 @@ typedef struct
/** @defgroup DSI_LP_Command DSI LP Command
* @{
*/
-#define DSI_LP_COMMAND_DISABLE 0U
-#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
+#define DSI_LP_COMMAND_DISABLE 0x00000000U
+#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
/**
* @}
*/
@@ -417,8 +438,8 @@ typedef struct
/** @defgroup DSI_LP_HFP DSI LP HFP
* @{
*/
-#define DSI_LP_HFP_DISABLE 0U
-#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
+#define DSI_LP_HFP_DISABLE 0x00000000U
+#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
/**
* @}
*/
@@ -426,8 +447,8 @@ typedef struct
/** @defgroup DSI_LP_HBP DSI LP HBP
* @{
*/
-#define DSI_LP_HBP_DISABLE 0U
-#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
+#define DSI_LP_HBP_DISABLE 0x00000000U
+#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
/**
* @}
*/
@@ -435,8 +456,8 @@ typedef struct
/** @defgroup DSI_LP_VACT DSI LP VACT
* @{
*/
-#define DSI_LP_VACT_DISABLE 0U
-#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
+#define DSI_LP_VACT_DISABLE 0x00000000U
+#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
/**
* @}
*/
@@ -444,8 +465,8 @@ typedef struct
/** @defgroup DSI_LP_VFP DSI LP VFP
* @{
*/
-#define DSI_LP_VFP_DISABLE 0
-#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
+#define DSI_LP_VFP_DISABLE 0x00000000U
+#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
/**
* @}
*/
@@ -453,8 +474,8 @@ typedef struct
/** @defgroup DSI_LP_VBP DSI LP VBP
* @{
*/
-#define DSI_LP_VBP_DISABLE 0U
-#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
+#define DSI_LP_VBP_DISABLE 0x00000000U
+#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
/**
* @}
*/
@@ -462,8 +483,8 @@ typedef struct
/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
* @{
*/
-#define DSI_LP_VSYNC_DISABLE 0U
-#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
+#define DSI_LP_VSYNC_DISABLE 0x00000000U
+#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
/**
* @}
*/
@@ -471,8 +492,8 @@ typedef struct
/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
* @{
*/
-#define DSI_FBTAA_DISABLE 0U
-#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
+#define DSI_FBTAA_DISABLE 0x00000000U
+#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
/**
* @}
*/
@@ -480,8 +501,8 @@ typedef struct
/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
* @{
*/
-#define DSI_TE_DSILINK 0U
-#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
+#define DSI_TE_DSILINK 0x00000000U
+#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
/**
* @}
*/
@@ -489,8 +510,8 @@ typedef struct
/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
* @{
*/
-#define DSI_TE_RISING_EDGE 0U
-#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
+#define DSI_TE_RISING_EDGE 0x00000000U
+#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
/**
* @}
*/
@@ -498,8 +519,8 @@ typedef struct
/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
* @{
*/
-#define DSI_VSYNC_FALLING 0U
-#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
+#define DSI_VSYNC_FALLING 0x00000000U
+#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
/**
* @}
*/
@@ -507,8 +528,8 @@ typedef struct
/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
* @{
*/
-#define DSI_AR_DISABLE 0U
-#define DSI_AR_ENABLE DSI_WCFGR_AR
+#define DSI_AR_DISABLE 0x00000000U
+#define DSI_AR_ENABLE DSI_WCFGR_AR
/**
* @}
*/
@@ -516,8 +537,8 @@ typedef struct
/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
* @{
*/
-#define DSI_TE_ACKNOWLEDGE_DISABLE 0U
-#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
+#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
+#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
/**
* @}
*/
@@ -525,8 +546,8 @@ typedef struct
/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
* @{
*/
-#define DSI_ACKNOWLEDGE_DISABLE 0U
-#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
+#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
+#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
/**
* @}
*/
@@ -534,8 +555,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
* @{
*/
-#define DSI_LP_GSW0P_DISABLE 0U
-#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
+#define DSI_LP_GSW0P_DISABLE 0x00000000U
+#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
/**
* @}
*/
@@ -543,8 +564,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
* @{
*/
-#define DSI_LP_GSW1P_DISABLE 0U
-#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
+#define DSI_LP_GSW1P_DISABLE 0x00000000U
+#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
/**
* @}
*/
@@ -552,8 +573,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
* @{
*/
-#define DSI_LP_GSW2P_DISABLE 0U
-#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
+#define DSI_LP_GSW2P_DISABLE 0x00000000U
+#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
/**
* @}
*/
@@ -561,8 +582,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
* @{
*/
-#define DSI_LP_GSR0P_DISABLE 0U
-#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
+#define DSI_LP_GSR0P_DISABLE 0x00000000U
+#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
/**
* @}
*/
@@ -570,8 +591,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
* @{
*/
-#define DSI_LP_GSR1P_DISABLE 0U
-#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
+#define DSI_LP_GSR1P_DISABLE 0x00000000U
+#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
/**
* @}
*/
@@ -579,8 +600,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
* @{
*/
-#define DSI_LP_GSR2P_DISABLE 0U
-#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
+#define DSI_LP_GSR2P_DISABLE 0x00000000U
+#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
/**
* @}
*/
@@ -588,8 +609,8 @@ typedef struct
/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
* @{
*/
-#define DSI_LP_GLW_DISABLE 0U
-#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
+#define DSI_LP_GLW_DISABLE 0x00000000U
+#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
/**
* @}
*/
@@ -597,8 +618,8 @@ typedef struct
/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
* @{
*/
-#define DSI_LP_DSW0P_DISABLE 0U
-#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
+#define DSI_LP_DSW0P_DISABLE 0x00000000U
+#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
/**
* @}
*/
@@ -606,8 +627,8 @@ typedef struct
/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
* @{
*/
-#define DSI_LP_DSW1P_DISABLE 0U
-#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
+#define DSI_LP_DSW1P_DISABLE 0x00000000U
+#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
/**
* @}
*/
@@ -615,8 +636,8 @@ typedef struct
/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
* @{
*/
-#define DSI_LP_DSR0P_DISABLE 0U
-#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
+#define DSI_LP_DSR0P_DISABLE 0x00000000U
+#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
/**
* @}
*/
@@ -624,8 +645,8 @@ typedef struct
/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
* @{
*/
-#define DSI_LP_DLW_DISABLE 0U
-#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
+#define DSI_LP_DLW_DISABLE 0x00000000U
+#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
/**
* @}
*/
@@ -633,8 +654,8 @@ typedef struct
/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
* @{
*/
-#define DSI_LP_MRDP_DISABLE 0U
-#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
+#define DSI_LP_MRDP_DISABLE 0x00000000U
+#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
/**
* @}
*/
@@ -642,8 +663,8 @@ typedef struct
/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
* @{
*/
-#define DSI_HS_PM_DISABLE 0U
-#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
+#define DSI_HS_PM_DISABLE 0x00000000U
+#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
/**
* @}
*/
@@ -652,7 +673,7 @@ typedef struct
/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
* @{
*/
-#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0U
+#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
/**
* @}
@@ -661,8 +682,8 @@ typedef struct
/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
* @{
*/
-#define DSI_ONE_DATA_LANE 0U
-#define DSI_TWO_DATA_LANES 1U
+#define DSI_ONE_DATA_LANE 0U
+#define DSI_TWO_DATA_LANES 1U
/**
* @}
*/
@@ -670,14 +691,14 @@ typedef struct
/** @defgroup DSI_FlowControl DSI Flow Control
* @{
*/
-#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
-#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
-#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
-#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
-#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
- DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
- DSI_FLOW_CONTROL_EOTP_TX)
+#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
+#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
+#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
+#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
+#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+ DSI_FLOW_CONTROL_EOTP_TX)
/**
* @}
*/
@@ -685,9 +706,9 @@ typedef struct
/** @defgroup DSI_Color_Coding DSI Color Coding
* @{
*/
-#define DSI_RGB565 ((uint32_t)0x00000000U) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
-#define DSI_RGB666 ((uint32_t)0x00000003U) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
-#define DSI_RGB888 ((uint32_t)0x00000005U)
+#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
+#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
+#define DSI_RGB888 0x00000005U
/**
* @}
*/
@@ -696,7 +717,7 @@ typedef struct
* @{
*/
#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
-#define DSI_LOOSELY_PACKED_DISABLE 0U
+#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
/**
* @}
*/
@@ -704,16 +725,16 @@ typedef struct
/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
* @{
*/
-#define DSI_HSYNC_ACTIVE_HIGH 0U
+#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
/**
* @}
*/
-/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity
+/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
* @{
*/
-#define DSI_VSYNC_ACTIVE_HIGH 0U
+#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
/**
* @}
@@ -722,7 +743,7 @@ typedef struct
/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
* @{
*/
-#define DSI_DATA_ENABLE_ACTIVE_HIGH 0U
+#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
/**
* @}
@@ -731,13 +752,13 @@ typedef struct
/** @defgroup DSI_PLL_IDF DSI PLL IDF
* @{
*/
-#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)
-#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)
-#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)
-#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)
-#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)
-#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)
-#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)
+#define DSI_PLL_IN_DIV1 0x00000001U
+#define DSI_PLL_IN_DIV2 0x00000002U
+#define DSI_PLL_IN_DIV3 0x00000003U
+#define DSI_PLL_IN_DIV4 0x00000004U
+#define DSI_PLL_IN_DIV5 0x00000005U
+#define DSI_PLL_IN_DIV6 0x00000006U
+#define DSI_PLL_IN_DIV7 0x00000007U
/**
* @}
*/
@@ -745,10 +766,10 @@ typedef struct
/** @defgroup DSI_PLL_ODF DSI PLL ODF
* @{
*/
-#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)
-#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)
-#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)
-#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)
+#define DSI_PLL_OUT_DIV1 0x00000000U
+#define DSI_PLL_OUT_DIV2 0x00000001U
+#define DSI_PLL_OUT_DIV4 0x00000002U
+#define DSI_PLL_OUT_DIV8 0x00000003U
/**
* @}
*/
@@ -756,14 +777,14 @@ typedef struct
/** @defgroup DSI_Flags DSI Flags
* @{
*/
-#define DSI_FLAG_TE DSI_WISR_TEIF
-#define DSI_FLAG_ER DSI_WISR_ERIF
-#define DSI_FLAG_BUSY DSI_WISR_BUSY
-#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
-#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
-#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
-#define DSI_FLAG_RRS DSI_WISR_RRS
-#define DSI_FLAG_RR DSI_WISR_RRIF
+#define DSI_FLAG_TE DSI_WISR_TEIF
+#define DSI_FLAG_ER DSI_WISR_ERIF
+#define DSI_FLAG_BUSY DSI_WISR_BUSY
+#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
+#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
+#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
+#define DSI_FLAG_RRS DSI_WISR_RRS
+#define DSI_FLAG_RR DSI_WISR_RRIF
/**
* @}
*/
@@ -771,11 +792,11 @@ typedef struct
/** @defgroup DSI_Interrupts DSI Interrupts
* @{
*/
-#define DSI_IT_TE DSI_WIER_TEIE
-#define DSI_IT_ER DSI_WIER_ERIE
-#define DSI_IT_PLLL DSI_WIER_PLLLIE
-#define DSI_IT_PLLU DSI_WIER_PLLUIE
-#define DSI_IT_RR DSI_WIER_RRIE
+#define DSI_IT_TE DSI_WIER_TEIE
+#define DSI_IT_ER DSI_WIER_ERIE
+#define DSI_IT_PLLL DSI_WIER_PLLLIE
+#define DSI_IT_PLLU DSI_WIER_PLLUIE
+#define DSI_IT_RR DSI_WIER_RRIE
/**
* @}
*/
@@ -783,11 +804,11 @@ typedef struct
/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
* @{
*/
-#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /*!< DCS short write, no parameters */
-#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /*!< DCS short write, one parameter */
-#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /*!< Generic short write, no parameters */
-#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /*!< Generic short write, one parameter */
-#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /*!< Generic short write, two parameters */
+#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
+#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
+#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
+#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
/**
* @}
*/
@@ -795,8 +816,8 @@ typedef struct
/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
* @{
*/
-#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /*!< DCS long write */
-#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /*!< Generic long write */
+#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
+#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
/**
* @}
*/
@@ -804,10 +825,10 @@ typedef struct
/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
* @{
*/
-#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U) /*!< DCS short read */
-#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /*!< Generic short read, no parameters */
-#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /*!< Generic short read, one parameter */
-#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /*!< Generic short read, two parameters */
+#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
+#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
+#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
+#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
/**
* @}
*/
@@ -815,17 +836,20 @@ typedef struct
/** @defgroup DSI_Error_Data_Type DSI Error Data Type
* @{
*/
-#define HAL_DSI_ERROR_NONE 0
-#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001U) /*!< acknowledge errors */
-#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002U) /*!< PHY related errors */
-#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004U) /*!< transmission error */
-#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008U) /*!< reception error */
-#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010U) /*!< ECC errors */
-#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020U) /*!< CRC error */
-#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040U) /*!< Packet Size error */
-#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080U) /*!< End Of Transmission error */
-#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100U) /*!< FIFO overflow error */
-#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200U) /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_NONE 0U
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -833,8 +857,8 @@ typedef struct
/** @defgroup DSI_Lane_Group DSI Lane Group
* @{
*/
-#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
-#define DSI_DATA_LANES ((uint32_t)0x00000001U)
+#define DSI_CLOCK_LANE 0x00000000U
+#define DSI_DATA_LANES 0x00000001U
/**
* @}
*/
@@ -842,9 +866,9 @@ typedef struct
/** @defgroup DSI_Communication_Delay DSI Communication Delay
* @{
*/
-#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)
-#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)
-#define DSI_HS_DELAY ((uint32_t)0x00000002U)
+#define DSI_SLEW_RATE_HSTX 0x00000000U
+#define DSI_SLEW_RATE_LPTX 0x00000001U
+#define DSI_HS_DELAY 0x00000002U
/**
* @}
*/
@@ -852,8 +876,8 @@ typedef struct
/** @defgroup DSI_CustomLane DSI CustomLane
* @{
*/
-#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U)
-#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)
+#define DSI_SWAP_LANE_PINS 0x00000000U
+#define DSI_INVERT_HS_SIGNAL 0x00000001U
/**
* @}
*/
@@ -861,9 +885,9 @@ typedef struct
/** @defgroup DSI_Lane_Select DSI Lane Select
* @{
*/
-#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
-#define DSI_DATA_LANE0 ((uint32_t)0x00000001U)
-#define DSI_DATA_LANE1 ((uint32_t)0x00000002U)
+#define DSI_CLK_LANE 0x00000000U
+#define DSI_DATA_LANE0 0x00000001U
+#define DSI_DATA_LANE1 0x00000002U
/**
* @}
*/
@@ -871,80 +895,143 @@ typedef struct
/** @defgroup DSI_PHY_Timing DSI PHY Timing
* @{
*/
-#define DSI_TCLK_POST ((uint32_t)0x00000000U)
-#define DSI_TLPX_CLK ((uint32_t)0x00000001U)
-#define DSI_THS_EXIT ((uint32_t)0x00000002U)
-#define DSI_TLPX_DATA ((uint32_t)0x00000003U)
-#define DSI_THS_ZERO ((uint32_t)0x00000004U)
-#define DSI_THS_TRAIL ((uint32_t)0x00000005U)
-#define DSI_THS_PREPARE ((uint32_t)0x00000006U)
-#define DSI_TCLK_ZERO ((uint32_t)0x00000007U)
-#define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)
+#define DSI_TCLK_POST 0x00000000U
+#define DSI_TLPX_CLK 0x00000001U
+#define DSI_THS_EXIT 0x00000002U
+#define DSI_TLPX_DATA 0x00000003U
+#define DSI_THS_ZERO 0x00000004U
+#define DSI_THS_TRAIL 0x00000005U
+#define DSI_THS_PREPARE 0x00000006U
+#define DSI_TCLK_ZERO 0x00000007U
+#define DSI_TCLK_PREPARE 0x00000008U
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
+/**
+ * @brief Reset DSI handle state.
+ * @param __HANDLE__: DSI handle
+ * @retval None
+ */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
+#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
+
/**
* @brief Enables the DSI host.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
+#define __HAL_DSI_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Disables the DSI host.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
+#define __HAL_DSI_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Enables the DSI wrapper.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Disable the DSI wrapper.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Enables the DSI PLL.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Disables the DSI PLL.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Enables the DSI regulator.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
+#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Disables the DSI regulator.
- * @param __HANDLE__ DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
+#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @brief Get the DSI pending flags.
- * @param __HANDLE__ DSI handle.
- * @param __FLAG__ Get the specified flag.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
@@ -960,8 +1047,8 @@ typedef struct
/**
* @brief Clears the DSI pending flags.
- * @param __HANDLE__ DSI handle.
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
@@ -974,8 +1061,8 @@ typedef struct
/**
* @brief Enables the specified DSI interrupts.
- * @param __HANDLE__ DSI handle.
- * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
+ * @param __HANDLE__ DSI handle.
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -988,8 +1075,8 @@ typedef struct
/**
* @brief Disables the specified DSI interrupts.
- * @param __HANDLE__ DSI handle
- * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -1001,9 +1088,9 @@ typedef struct
#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
/**
- * @brief Checks whether the specified DSI interrupt has occurred or not.
- * @param __HANDLE__ DSI handle
- * @param __INTERRUPT__ specifies the DSI interrupt source to check.
+ * @brief Checks whether the specified DSI interrupt source is enabled or not.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt source to check.
* This parameter can be one of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -1012,7 +1099,7 @@ typedef struct
* @arg DSI_IT_RR : Regulator Ready Interrupt
* @retval The state of INTERRUPT (SET or RESET).
*/
-#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
+#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
/* Exported functions --------------------------------------------------------*/
/** @defgroup DSI_Exported_Functions DSI Exported Functions
@@ -1028,6 +1115,13 @@ void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+ pDSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1050,14 +1144,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t* ParametersTable);
+ uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
- uint8_t* Array,
+ uint8_t *Array,
uint32_t Size,
uint32_t Mode,
uint32_t DCSCmd,
- uint8_t* ParametersTable);
+ uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
@@ -1066,11 +1160,14 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+ uint32_t Value);
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
-HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
-HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+ FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
+ uint32_t Value);
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
@@ -1115,7 +1212,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
/** @defgroup DSI_Private_Constants DSI Private Constants
* @{
*/
-#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */
+#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
/**
* @}
*/
@@ -1139,7 +1236,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
-#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5)
+#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
@@ -1229,12 +1326,12 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
/**
* @}
*/
-#endif /*STM32F769xx | STM32F779xx */
+#endif /* DSI */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_DSI_H */
+#endif /* STM32F7xx_HAL_DSI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_eth.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_eth.h
index 9141c6fb013090ca0f4af5b45a14d1ad27ade05d..1c70c5f985db006359828efdb632e1386c20381b 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_eth.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_eth.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -628,7 +612,11 @@ typedef struct
* @brief ETH Handle Structure definition
*/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
typedef struct
+#endif
{
ETH_TypeDef *Instance; /*!< Register base address */
@@ -646,8 +634,40 @@ typedef struct
HAL_LockTypeDef Lock; /*!< ETH Lock */
+ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
+ void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */
+ void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
} ETH_HandleTypeDef;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ETH Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
+ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
+ HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
+ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
+ HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
+
+}HAL_ETH_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ETH Callback pointer definition
+ */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1594,7 +1614,15 @@ typedef struct
* @param __HANDLE__ specifies the ETH handle.
* @retval None
*/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.
@@ -2111,6 +2139,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_exti.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_exti.h
new file mode 100644
index 0000000000000000000000000000000000000000..b62eade50e25c4d5d5bf1292d8fd7e5cc8b0a3a6
--- /dev/null
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_exti.h
@@ -0,0 +1,260 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_EXTI_H
+#define __STM32F7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+typedef enum
+{
+ HAL_EXTI_COMMON_CB_ID = 0x00U,
+ HAL_EXTI_RISING_CB_ID = 0x01U,
+ HAL_EXTI_FALLING_CB_ID = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< Exti line number */
+ void (* PendingCallback)(void); /*!< Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
+#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
+#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
+#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
+#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
+#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
+#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
+#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
+#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
+#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
+#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
+#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
+#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
+#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
+#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
+#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
+#if defined(EXTI_IMR_IM16)
+#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
+#endif /* EXTI_IMR_IM16 */
+#if defined(EXTI_IMR_IM17)
+#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#endif /* EXTI_IMR_IM17 */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#endif /* EXTI_IMR_IM20 */
+#if defined(EXTI_IMR_IM21)
+#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#endif /* EXTI_IMR_IM21 */
+#if defined(EXTI_IMR_IM22)
+#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#endif /* EXTI_IMR_IM22 */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
+#endif /* EXTI_IMR_IM23 */
+#if defined(EXTI_IMR_IM24)
+#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
+#endif /* EXTI_IMR_IM24 */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_NONE 0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT 0x00000002u
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 25u
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__))
+
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
+ ((__LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash.h
index 0fba4c21ee5882e3c9090e6e60753c2655ef915d..ed073e9396e0753e933943e611b6084f1a4296e6 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash_ex.h
index 2205595b085f570c516ed7840e4e2280268b6135..572d7e5006ba3c21400e5f35e8f3e91b310c607a 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_flash_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio.h
index bfb6164d7a57b79baef68715ab4275fb6a2c4fc1..c590c5021b5b9fb4b5148da395b76ea2593d5884 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio_ex.h
index 5d46ffcbd083c46284a43d494d081c15f948be20..bdd947e455d61cbb816de24dc976843a08bcae58 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_gpio_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash.h
index 5d76e02e4bcaa1cdf2c6513812c35b2803562089..3cf5c25900034cc6a23faca42c154a7511f6de18 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash.h
@@ -6,52 +6,34 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_HASH_H
-#define __STM32F7xx_HAL_HASH_H
+#ifndef STM32F7xx_HAL_HASH_H
+#define STM32F7xx_HAL_HASH_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-
+#if defined (HASH)
/** @addtogroup HASH
- * @brief HASH HAL module driver
- * @{
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
@@ -59,122 +41,172 @@
* @{
*/
-/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
- * @{
+/**
+ * @brief HASH Configuration Structure definition
*/
-
typedef struct
{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref HASH_Data_Type */
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+ This parameter can be a value of @ref HASH_Data_Type. */
- uint32_t KeySize; /*!< The key size is used only in HMAC operation */
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation */
-}HASH_InitTypeDef;
+ uint8_t* pKey; /*!< The key is used only in HMAC operation. */
-/**
- * @}
- */
+} HASH_InitTypeDef;
-/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
- * @{
+/**
+ * @brief HAL State structures definition
*/
-
typedef enum
{
- HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
- HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
- HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
- HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
+ HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
+ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
+ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
}HAL_HASH_StateTypeDef;
/**
- * @}
+ * @brief HAL phase structures definition
*/
+typedef enum
+{
+ HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
+ HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
+ HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
+ (step 1 consists in entering the inner hash function key) */
+ HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
+ (step 2 consists in entering the message text) */
+ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
+ (step 3 consists in entering the outer hash function key) */
+}HAL_HASH_PhaseTypeDef;
-/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
- * @{
+/**
+ * @brief HAL HASH mode suspend definitions
*/
-
typedef enum
{
- HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
- HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in processing phase */
-}HAL_HASHPhaseTypeDef;
+ HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
+ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
+}HAL_HASH_SuspendTypeDef;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
- * @}
+ * @brief HAL HASH common Callback ID enumeration definition
*/
+typedef enum
+{
+ HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
+ HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
+ HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
+ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
+ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
+}HAL_HASH_CallbackIDTypeDef;
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
- * @{
- */
+/**
+ * @brief HASH Handle Structure definition
+ */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+typedef struct __HASH_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
{
- HASH_InitTypeDef Init; /*!< HASH required parameters */
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+
+ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+ uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+
+ uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputted data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+
+ __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
+
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
- uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
- uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
- __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint32_t HashInCount; /*!< Counter of inputed data */
+ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
- __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+ HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
- HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+ FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
- HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
+ __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
- DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
+ __IO uint32_t ErrorCode; /*!< HASH Error code */
- HAL_LockTypeDef Lock; /*!< HASH locking object */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
- __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
+ void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+
+ void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+
+ void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+
+ void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
- * @}
+ * @brief HAL HASH Callback pointer definition
*/
-
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup HASH_Exported_Constants HASH Exported Constants
+
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
* @{
*/
-/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
+/** @defgroup HASH_Algo_Selection HASH algorithm selection
* @{
*/
-#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */
-#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
-#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
-#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
+/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
* @{
*/
-#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */
-#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
-/** @defgroup HASH_Data_Type HASH Data Type
+/** @defgroup HASH_Data_Type HASH input data type
* @{
*/
-#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
@@ -182,250 +214,390 @@ typedef struct
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
- * @brief HASH HMAC Long key used only for HMAC mode
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
* @{
*/
-#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
+#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
+/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
+/** @defgroup HASH_interrupts_definition HASH interrupts definitions
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
+
+/**
+ * @}
+ */
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
/**
* @}
*/
+/** @defgroup HASH_Error_Definition HASH Error Definition
+ * @{
+ */
+#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */
+#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup HASH_Exported_Macros HASH Exported Macros
* @{
*/
-/** @brief Reset HASH handle state
- * @param __HANDLE__ specifies the HASH handle.
+/** @brief Check whether or not the specified HASH flag is set.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+ * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+ * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+ * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief Clear the specified HASH flag.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief Enable the specified HASH interrupt.
+ * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Disable the specified HASH interrupt.
+ * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+ * @param __HANDLE__: HASH handle.
* @retval None
*/
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-/** @brief Check whether the specified HASH flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
- * @arg HASH_FLAG_DCIS: Digest calculation complete
- * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
- * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
- * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+
+/** @brief Reset HASH handle status.
+ * @param __HANDLE__: HASH handle.
+ * @retval None
*/
-#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)))
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
/**
- * @brief Enable the multiple DMA mode.
- * This feature is available only in STM32F429x and STM32F439x devices.
+ * @brief Enable the multi-buffer DMA transfer mode.
+ * @note This bit is set when hashing large files when multiple DMA transfers are needed.
* @retval None
*/
-#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
+#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
/**
- * @brief Disable the multiple DMA mode.
+ * @brief Disable the multi-buffer DMA transfer mode.
* @retval None
*/
-#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
/**
- * @brief Start the digest computation
+ * @brief Start the digest computation.
* @retval None
*/
-#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
+#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
/**
- * @brief Set the number of valid bits in last word written in Data register
- * @param SIZE size in byte of last data written in Data register.
+ * @brief Set the number of valid bits in the last word written in data register DIN.
+ * @param __SIZE__: size in bytes of last data written in Data register.
* @retval None
*/
-#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
- HASH->STR |= 8 * ((SIZE) % 4);\
- }while(0)
+#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
+
+/**
+ * @brief Reset the HASH core.
+ * @retval None
+ */
+#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
/**
* @}
*/
-/* Include HASH HAL Extension module */
-#include "stm32f7xx_hal_hash_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HASH_Exported_Functions HASH Exported Functions
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
* @{
*/
-
-/** @addtogroup HASH_Exported_Functions_Group1
- * @{
+/**
+ * @brief Return digest length in bytes.
+ * @retval Digest length
*/
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
/**
- * @}
+ * @brief Return number of words already pushed in the FIFO.
+ * @retval Number of words already pushed in the FIFO
*/
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
-/** @addtogroup HASH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
- * @}
+ * @brief Ensure that HASH input data type is valid.
+ * @param __DATATYPE__: HASH input data type.
+ * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
-/** @addtogroup HASH_Exported_Functions_Group3
- * @{
+
+
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+ * processing in polling mode.
+ * @note This check is valid only for multi-buffer HASH processing in polling mode.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
- * @}
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HASH processing in DMA mode.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
-/** @addtogroup HASH_Exported_Functions_Group4
- * @{
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HMAC processing in DMA mode.
+ * @param __HANDLE__: HASH handle.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
- * @}
+ * @brief Ensure that handle phase is set to HASH processing.
+ * @param __HANDLE__: HASH handle.
+ * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
+#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
-/** @addtogroup HASH_Exported_Functions_Group5
- * @{
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
- * @}
+ * @brief Ensure that handle phase is set to HMAC processing.
+ * @param __HANDLE__: HASH handle.
+ * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
+#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-/** @addtogroup HASH_Exported_Functions_Group6
- * @{
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/** @addtogroup HASH_Exported_Functions_Group7
+/* Include HASH HAL Extended module */
+#include "stm32f7xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
-/**
- * @}
- */
-/** @addtogroup HASH_Exported_Functions_Group8
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+
+/* Initialization/de-initialization methods **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
- /**
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @{
+ */
+
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
* @}
*/
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HASH_Private_Types HASH Private Types
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
* @{
*/
+/* HASH processing using IT **************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Variables HASH Private Variables
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
* @{
*/
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Constants HASH Private Constants
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
* @{
*/
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros HASH Private Macros
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
* @{
*/
-#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/**
+ * @}
+ */
-#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
- ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @{
+ */
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_8B) || \
- ((__DATATYPE__) == HASH_DATATYPE_1B))
+/**
+ * @}
+ */
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @{
+ */
-#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
- ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
-#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
+/* Peripheral State methods **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
+/**
+ * @}
+ */
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/* Private functions -----------------------------------------------------------*/
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
* @{
*/
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
/**
* @}
*/
@@ -433,16 +605,17 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#endif /* HASH*/
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_HASH_H */
+#endif /* STM32F7xx_HAL_HASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash_ex.h
index b7c812f86a27665d4c9b4aa68627cab1dbdbee0d..6c0fc99faff09398d17a149de157ff0bb583d88b 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hash_ex.h
@@ -2,92 +2,65 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.h
* @author MCD Application Team
- * @brief Header file of HASH HAL Extension module.
+ * @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_HASH_EX_H
-#define __STM32F7xx_HAL_HASH_EX_H
+#ifndef STM32F7xx_HAL_HASH_EX_H
+#define STM32F7xx_HAL_HASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-
+#if defined (HASH)
/** @addtogroup HASHEx
- * @brief HASHEx HAL Extension module driver
- * @{
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+
+
/* Exported functions --------------------------------------------------------*/
-/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
-/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @{
*/
@@ -98,10 +71,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @{
*/
-
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
@@ -111,71 +83,59 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @{
*/
-void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
-/**
- * @}
- */
-
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Types HASHEx Private Types
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @{
*/
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Variables HASHEx Private Variables
- * @{
- */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Constants HASHEx Private Constants
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @{
*/
-/**
- * @}
- */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Macros HASHEx Private Macros
- * @{
- */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Functions HASHEx Private Functions
- * @{
- */
-
/**
* @}
*/
@@ -183,15 +143,17 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
+#endif /* HASH*/
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_HASH_EX_H */
+
+#endif /* STM32F7xx_HAL_HASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hcd.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hcd.h
index 7d1859e0ad8f2d47ca2923ffec7b737afffbd5b5..7488da76dcf4e3ea2d32ac2f854820b17f1285a7 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hcd.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_hcd.h
@@ -6,44 +6,29 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_HCD_H
-#define __STM32F7xx_HAL_HCD_H
+#ifndef STM32F7xx_HAL_HCD_H
+#define STM32F7xx_HAL_HCD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_usb.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -81,14 +66,31 @@ typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{
*/
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
+ __IO uint32_t ErrorCode; /*!< HCD Error code */
void *pData; /*!< Pointer Stack Handler */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
+ void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
+ void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
+ void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
+ void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
+ void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
+
+ void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
} HCD_HandleTypeDef;
/**
* @}
@@ -118,6 +120,18 @@ typedef struct
*/
#define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+ * @brief HCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -156,18 +170,59 @@ typedef struct
* @{
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+ * @brief HAL USB OTG HCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+ * @brief HAL USB OTG HCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+ uint8_t epnum,
+ HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -177,15 +232,15 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
- uint8_t direction ,
+ uint8_t ch_num,
+ uint8_t direction,
uint8_t ep_type,
uint8_t token,
- uint8_t* pbuff,
+ uint8_t *pbuff,
uint16_t length,
uint8_t do_ping);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
@@ -193,8 +248,8 @@ void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -262,11 +317,12 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_HCD_H */
+#endif /* STM32F7xx_HAL_HCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c.h
index 80b7a23faab394b92b81cd9b30a7ca5b0fb7fac2..17228434082d213cf507c106c0ca9788ae6915b3 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2C_H
-#define __STM32F7xx_HAL_I2C_H
+#ifndef STM32F7xx_HAL_I2C_H
+#define STM32F7xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
@@ -102,17 +86,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
- * b5 IP initilisation status\n
- * 0 : Reset (IP not initialized)\n
- * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
+ * b5 Peripheral initialization status\n
+ * 0 : Reset (peripheral not initialized)\n
+ * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
- * 1 : Listen (IP in Address Listen Mode)\n
+ * 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
- * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
@@ -186,6 +170,11 @@ typedef enum
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
@@ -226,7 +215,54 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL I2C Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
+
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2C Callback pointer definition
+ */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -249,6 +285,12 @@ typedef struct __I2C_HandleTypeDef
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define I2C_OTHER_FRAME (0x000000AAU)
+#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
@@ -397,7 +439,15 @@ typedef struct __I2C_HandleTypeDef
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
@@ -470,6 +520,7 @@ typedef struct __I2C_HandleTypeDef
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
+#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
@@ -529,6 +580,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -554,10 +614,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
@@ -569,6 +629,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/**
* @}
*/
@@ -661,15 +726,19 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME_NO_STOP))
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
-#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
@@ -679,6 +748,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
@@ -705,6 +777,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif
-#endif /* __STM32F7xx_HAL_I2C_H */
+#endif /* STM32F7xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c_ex.h
index 46d6bcbd43856c18f40bcfc6092de0c9159eadb9..f377d8187d32fcfe0dfacb5d67d68ef60630cac0 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2c_ex.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2C_EX_H
-#define __STM32F7xx_HAL_I2C_EX_H
+#ifndef STM32F7xx_HAL_I2C_EX_H
+#define STM32F7xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
@@ -152,7 +136,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
+#if (defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP))
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
@@ -216,6 +200,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
}
#endif
-#endif /* __STM32F7xx_HAL_I2C_EX_H */
+#endif /* STM32F7xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2s.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2s.h
index 5bc14bba092d822e8e18b166e73da8f582e8d416..dca9ca03b1a01b8297a4459423d9e9e9464d55c6 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2s.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_i2s.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_I2S_H
-#define __STM32F7xx_HAL_I2S_H
+#ifndef STM32F7xx_HAL_I2S_H
+#define STM32F7xx_HAL_I2S_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -80,9 +64,9 @@ typedef struct
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
- uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
- This parameter can be a value of @ref I2S_Clock_Source */
-}I2S_InitTypeDef;
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
@@ -94,77 +78,104 @@ typedef enum
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-
-}HAL_I2S_StateTypeDef;
+} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
+typedef struct __I2S_HandleTypeDef
+#else
typedef struct
+#endif
{
- SPI_TypeDef *Instance; /* I2S registers base address */
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
- I2S_InitTypeDef Init; /* I2S communication parameters */
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
- uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
- __IO uint16_t TxXferSize; /* I2S Tx transfer size */
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
- __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
- uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
- __IO uint16_t RxXferSize; /* I2S Rx transfer size */
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
- __IO uint16_t RxXferCount; /* I2S Rx transfer counter
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
- decremented when a sample is received.
+ decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
- DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
- DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
- __IO HAL_LockTypeDef Lock; /* I2S locking object */
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
- __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
- __IO uint32_t ErrorCode; /* I2S Error code */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
+ void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
+ void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
+ void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
+ void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
-}I2S_HandleTypeDef;
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/**
- * @}
+ * @brief HAL I2S Callback ID enumeration definition
*/
+typedef enum
+{
+ HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
+ HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
+ HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
+ HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
+ HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
+ HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
+ HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
- * @{
- */
+} HAL_I2S_CallbackIDTypeDef;
-/** @defgroup I2S_Error_Defintion I2S_Error_Defintion
- *@brief I2S Error Code
- * @{
+/**
+ * @brief HAL I2S Callback pointer definition
*/
-#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
-#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) /*!< UDR error */
-#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) /*!< Unknow Error error */
+typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup I2S_Clock_Source I2S Clock Source
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
-#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
-#define I2S_CLOCK_PLL ((uint32_t)0x00000002U)
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -172,10 +183,10 @@ typedef struct
/** @defgroup I2S_Mode I2S Mode
* @{
*/
-#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
-#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
-#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
-#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
+#define I2S_MODE_SLAVE_TX (0x00000000U)
+#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
@@ -183,11 +194,11 @@ typedef struct
/** @defgroup I2S_Standard I2S Standard
* @{
*/
-#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
-#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
-#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
-#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
-#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
+#define I2S_STANDARD_PHILIPS (0x00000000U)
+#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
@@ -195,19 +206,19 @@ typedef struct
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
-#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
-#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
-#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
+#define I2S_DATAFORMAT_16B (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
-#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
+#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
@@ -215,26 +226,25 @@ typedef struct
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
-#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
-#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
-#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
-#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
-#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
-#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
-#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
-#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
-#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
-#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
+#define I2S_AUDIOFREQ_192K (192000U)
+#define I2S_AUDIOFREQ_96K (96000U)
+#define I2S_AUDIOFREQ_48K (48000U)
+#define I2S_AUDIOFREQ_44K (44100U)
+#define I2S_AUDIOFREQ_32K (32000U)
+#define I2S_AUDIOFREQ_22K (22050U)
+#define I2S_AUDIOFREQ_16K (16000U)
+#define I2S_AUDIOFREQ_11K (11025U)
+#define I2S_AUDIOFREQ_8K (8000U)
+#define I2S_AUDIOFREQ_DEFAULT (2U)
/**
* @}
*/
-
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
-#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
@@ -242,9 +252,9 @@ typedef struct
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
@@ -252,52 +262,85 @@ typedef struct
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+
+#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
+/** @defgroup I2S_Clock_Source I2S Clock Source Definition
+ * @{
+ */
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
+#define I2S_CLOCK_PLL ((uint32_t)0x00000002U)
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
+/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
- * @param __HANDLE__ specifies the I2S handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif
+
+/** @brief Enable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-/** @brief Enable or disable the specified I2S interrupts.
+/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
@@ -314,7 +357,7 @@ typedef struct
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
@@ -330,55 +373,57 @@ typedef struct
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
-
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ }while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+/** @addtogroup I2S_Exported_Functions
* @{
*/
-/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
-
-/* Initialization and de-initialization functions *****************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
+/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
@@ -401,7 +446,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
@@ -415,7 +460,6 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @}
*/
-
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -431,34 +475,70 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of I2S SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun error flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_CHSIDE: Channel side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if I2S Mode parameter is in allowed range.
+ * @param __MODE__ specifies the I2S Mode.
+ * This parameter can be a value of @ref I2S_Mode
+ * @retval None
+ */
+#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
+ ((__MODE__) == I2S_MODE_SLAVE_RX) || \
+ ((__MODE__) == I2S_MODE_MASTER_TX) || \
+ ((__MODE__) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
+ ((__STANDARD__) == I2S_STANDARD_MSB) || \
+ ((__STANDARD__) == I2S_STANDARD_LSB) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
+ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+
+/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the I2S serial clock steady state.
+ * This parameter can be a value of @ref I2S_Clock_Polarity
+ * @retval None
+ */
+#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
+ ((__CPOL__) == I2S_CPOL_HIGH))
+
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_PLL))
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX)|| \
- ((MODE) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
/**
* @}
*/
@@ -470,12 +550,11 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F7xx_HAL_I2S_H */
+#endif /* STM32F7xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda.h
index d7ae51d94d958a017ec6f17870ce5f3e8f83039a..f382d73c0b21533e60cafa5ffaaa387fdad82ff4 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_IRDA_H
-#define __STM32F7xx_HAL_IRDA_H
+#ifndef STM32F7xx_HAL_IRDA_H
+#define STM32F7xx_HAL_IRDA_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,6 +40,7 @@
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
+
/**
* @brief IRDA Init Structure definition
*/
@@ -63,7 +48,8 @@ typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+ Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate)))
+ where usart_ker_clk is the IRDA input clock */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDAEx_Word_Length */
@@ -75,7 +61,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
@@ -84,11 +70,12 @@ typedef struct
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
+
+} IRDA_InitTypeDef;
/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+ * @brief HAL IRDA State definition
+ * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -97,14 +84,14 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -114,9 +101,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -125,103 +112,161 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
+typedef uint32_t HAL_IRDA_StateTypeDef;
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
- IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
-}IRDA_ClockSourceTypeDef;
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
+} IRDA_ClockSourceTypeDef;
/**
* @brief IRDA handle Structure definition
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
- USART_TypeDef *Instance; /* IRDA registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
- IRDA_InitTypeDef Init; /* IRDA communication parameters */
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
- uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
- uint16_t TxXferSize; /* IRDA Tx Transfer size */
+ uint16_t Mask; /*!< USART RX RDR register mask */
- __IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
- uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
- uint16_t RxXferSize; /* IRDA Rx Transfer size */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
- uint16_t Mask; /* IRDA RX RDR register mask */
+ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
- DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
- DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
- HAL_LockTypeDef Lock; /* Locking object */
+ void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
- __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+ void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
- __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+ void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
- __IO uint32_t ErrorCode; /* IRDA Error code */
+ void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
-}IRDA_HandleTypeDef;
+ void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
+
+
+ void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
- * @}
+ * @brief HAL IRDA Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
+ HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
+ HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
+ HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
+ HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
+ HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
+ HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
+ HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
+
+ HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
+ HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+ * @brief HAL IRDA Callback pointer definition
*/
+typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
- * @brief IRDA Configuration enumeration values definition
+ * @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
* @{
*/
-/** @defgroup IRDA_Error_Code IRDA Error Code
- * @brief IRDA Error Code
+
+/** @defgroup IRDA_State_Definition IRDA State Code Definition
* @{
*/
+#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -229,20 +274,19 @@ typedef struct
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
-#define IRDA_PARITY_NONE ((uint32_t)0x0000U)
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
+#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
-
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
+#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
+#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
@@ -250,35 +294,35 @@ typedef struct
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
-#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U)
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
/**
* @}
*/
- /** @defgroup IRDA_State IRDA State
+/** @defgroup IRDA_State IRDA State
* @{
*/
-#define IRDA_STATE_DISABLE ((uint32_t)0x0000U)
-#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
/**
* @}
*/
- /** @defgroup IRDA_Mode IRDA Mode
+/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
-#define IRDA_MODE_DISABLE ((uint32_t)0x0000U)
-#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
+#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
-/** @defgroup IRDA_One_Bit IRDA One Bit
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
-#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
-#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
+#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
/**
* @}
*/
@@ -286,8 +330,8 @@ typedef struct
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
-#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U)
-#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
+#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
/**
* @}
*/
@@ -295,8 +339,18 @@ typedef struct
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
-#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U)
-#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
+#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
@@ -306,23 +360,22 @@ typedef struct
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define IRDA_FLAG_REACK ((uint32_t)0x00400000U)
-#define IRDA_FLAG_TEACK ((uint32_t)0x00200000U)
-#define IRDA_FLAG_BUSY ((uint32_t)0x00010000U)
-#define IRDA_FLAG_ABRF ((uint32_t)0x00008000U)
-#define IRDA_FLAG_ABRE ((uint32_t)0x00004000U)
-#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
-#define IRDA_FLAG_TC ((uint32_t)0x00000040U)
-#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
-#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
-#define IRDA_FLAG_NE ((uint32_t)0x00000004U)
-#define IRDA_FLAG_FE ((uint32_t)0x00000002U)
-#define IRDA_FLAG_PE ((uint32_t)0x00000001U)
+#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
+#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
+#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
+#define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */
+#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
+#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */
+#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
+#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
+#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
+#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
/**
* @}
*/
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
@@ -332,53 +385,50 @@ typedef struct
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-#define IRDA_IT_PE ((uint16_t)0x0028U)
-#define IRDA_IT_TXE ((uint16_t)0x0727U)
-#define IRDA_IT_TC ((uint16_t)0x0626U)
-#define IRDA_IT_RXNE ((uint16_t)0x0525U)
-#define IRDA_IT_IDLE ((uint16_t)0x0424U)
-
-
-
-/** Elements values convention: 000000000XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- */
-#define IRDA_IT_ERR ((uint16_t)0x0060U)
-
-/** Elements values convention: 0000ZZZZ00000000b
- * - ZZZZ : Flag position in the ISR register(4bits)
- */
-#define IRDA_IT_ORE ((uint16_t)0x0300U)
-#define IRDA_IT_NE ((uint16_t)0x0200U)
-#define IRDA_IT_FE ((uint16_t)0x0100U)
+#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
+
+/* Elements values convention: 000000000XXYYYYYb
+ - YYYYY : Interrupt source position in the XX register (5bits)
+ - XX : Interrupt source register (2bits)
+ - 01: CR1 register
+ - 10: CR2 register
+ - 11: CR3 register */
+#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
+
+/* Elements values convention: 0000ZZZZ00000000b
+ - ZZZZ : Flag position in the ISR register(4bits) */
+#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
/**
* @}
*/
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
-#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
*/
-
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
-#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
+#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
+#define IRDA_CR_POS 5U /*!< IRDA control register position */
+#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
+#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
/**
* @}
*/
@@ -387,18 +437,28 @@ typedef struct
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
-/** @brief Reset IRDA handle state
- * @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
+/** @brief Reset IRDA handle state.
+ * @param __HANDLE__ IRDA handle.
* @retval None
*/
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -408,7 +468,7 @@ typedef struct
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -419,6 +479,7 @@ typedef struct
* @arg @ref IRDA_CLEAR_NEF
* @arg @ref IRDA_CLEAR_OREF
* @arg @ref IRDA_CLEAR_TCF
+ * @arg @ref IRDA_CLEAR_IDLEF
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -456,135 +517,135 @@ typedef struct
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
- * UART peripheral
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
- * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg IRDA_FLAG_BUSY: Busy flag
- * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
- * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg IRDA_FLAG_TXE: Transmit data register empty flag
- * @arg IRDA_FLAG_TC: Transmission Complete flag
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
- * @arg IRDA_FLAG_IDLE: Idle Line detection flag
- * @arg IRDA_FLAG_ORE: OverRun Error flag
- * @arg IRDA_FLAG_NE: Noise Error flag
- * @arg IRDA_FLAG_FE: Framing Error flag
- * @arg IRDA_FLAG_PE: Parity Error flag
+ * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref IRDA_FLAG_BUSY Busy flag
+ * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
+ * @arg @ref IRDA_FLAG_TC Transmission Complete flag
+ * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref IRDA_FLAG_ORE OverRun Error flag
+ * @arg @ref IRDA_FLAG_NE Noise Error flag
+ * @arg @ref IRDA_FLAG_FE Framing Error flag
+ * @arg @ref IRDA_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
- * UART peripheral
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __IT__ specifies the IRDA interrupt source to check.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ORE: OverRun Error interrupt
- * @arg IRDA_IT_NE: Noise Error interrupt
- * @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Check whether the specified IRDA interrupt source is enabled.
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ORE OverRun Error interrupt
+ * @arg @ref IRDA_IT_NE Noise Error interrupt
+ * @arg @ref IRDA_IT_FE Framing Error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __IT__ specifies the IRDA interrupt source to check.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ORE: OverRun Error interrupt
- * @arg IRDA_IT_NE: Noise Error interrupt
- * @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
- * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
- * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
- * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
- * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
/** @brief Set a specific IRDA request flag.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
- * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
- *
+ * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-/** @brief Enable UART/USART associated to IRDA Handle
+/** @brief Enable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the IRDA one bit sample method.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable UART/USART associated to IRDA Handle
+/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
- * The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -593,7 +654,91 @@ typedef struct
* @}
*/
-/* Include IRDA HAL Extension module */
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Macros
+ * @{
+ */
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
+ * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
+
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
+ * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
+
+/** @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__ IRDA frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \
+ ((__PARITY__) == IRDA_PARITY_ODD))
+
+/** @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__ IRDA communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__ IRDA power mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/** @brief Ensure that IRDA state is valid.
+ * @param __STATE__ IRDA state mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+ ((__STATE__) == IRDA_STATE_ENABLE))
+
+/** @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__ IRDA associated UART/USART mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
+ ((__MODE__) == IRDA_MODE_ENABLE))
+
+/** @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__ IRDA sampling rate.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__ IRDA DMA TX mode.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/** @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__ IRDA DMA RX mode.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/** @brief Ensure that IRDA request is valid.
+ * @param __PARAM__ IRDA request.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
#include "stm32f7xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
@@ -601,7 +746,7 @@ typedef struct
* @{
*/
-/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -610,6 +755,13 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -642,99 +794,26 @@ void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
-
-/**
- * @}
- */
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral State methods **************************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
- * @{
- */
-
-/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask
- * @{
- */
-#define IRDA_IT_MASK ((uint16_t)0x001FU)
-/**
- * @}
- */
-/**
- * @}
- */
+/* Peripheral Control functions ************************************************/
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
-/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
- * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
- * @retval True or False
- */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-
-/** @brief Ensure that IRDA prescaler value is strictly larger than 0
- * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
- * @retval True or False
- */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
-
-#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
- ((__PARITY__) == IRDA_PARITY_EVEN) || \
- ((__PARITY__) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))
-
-#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
- ((__MODE__) == IRDA_POWERMODE_NORMAL))
-
-#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
- ((__STATE__) == IRDA_STATE_ENABLE))
-
-#define IS_IRDA_MODE(__STATE__) (((__STATE__) == IRDA_MODE_DISABLE) || \
- ((__STATE__) == IRDA_MODE_ENABLE))
-
-#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-
-#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
- ((__DMATX__) == IRDA_DMA_TX_ENABLE))
-
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
- ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
- ((PARAM) == IRDA_SENDBREAK_REQUEST) || \
- ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
- ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @{
+ * @}
*/
/**
@@ -753,6 +832,6 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
}
#endif
-#endif /* __STM32F7xx_HAL_IRDA_H */
+#endif /* STM32F7xx_HAL_IRDA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda_ex.h
index bb0ac13c5d54177a303399f4ac40538bddd4c674..247cb740aef1a432777b5c2fe277711343a212cb 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_irda_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
- * @brief Header file of IRDA HAL Extension module.
+ * @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_IRDA_EX_H
-#define __STM32F7xx_HAL_IRDA_EX_H
+#ifndef STM32F7xx_HAL_IRDA_EX_H
+#define STM32F7xx_HAL_IRDA_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -61,28 +45,28 @@
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
* @{
*/
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
/**
* @}
*/
-
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
-/** @brief Reports the IRDA clock source.
- * @param __HANDLE__ specifies the IRDA Handle
- * @param __CLOCKSOURCE__ output variable
+
+/** @brief Report the IRDA clock source.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -104,6 +88,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -124,6 +109,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -144,6 +130,49 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -164,56 +193,111 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART7) \
+ { \
+ switch(__HAL_RCC_GET_UART7_SOURCE()) \
+ { \
+ case RCC_UART7CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART7CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART7CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART7CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART8) \
+ { \
+ switch(__HAL_RCC_GET_UART8_SOURCE()) \
+ { \
+ case RCC_UART8CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART8CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART8CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART8CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
- } while(0)
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
-/** @brief Reports the mask to apply to retrieve the received data
+/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * @param __HANDLE__ specifies the IRDA Handle
- * @retval mask to apply to USART RDR register value.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU ; \
} \
} \
-} while(0)
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+} while(0U)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
- ((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
+/** @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__ IRDA frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
/**
* @}
*/
@@ -232,6 +316,6 @@
}
#endif
-#endif /* __STM32F7xx_HAL_IRDA_EX_H */
+#endif /* STM32F7xx_HAL_IRDA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_iwdg.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_iwdg.h
index 4a65b9f0395fb6f550856336a6d186fe33221c3c..7ceb39568c4a45fb05a7e1c18a928c08b37293d8 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_iwdg.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_iwdg.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_IWDG_H
-#define __STM32F7xx_HAL_IWDG_H
+#ifndef STM32F7xx_HAL_IWDG_H
+#define STM32F7xx_HAL_IWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -81,8 +65,8 @@ typedef struct
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
-}IWDG_HandleTypeDef;
/**
* @}
@@ -96,13 +80,14 @@ typedef struct
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
-#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+
/**
* @}
*/
@@ -115,6 +100,7 @@ typedef struct
* @}
*/
+
/**
* @}
*/
@@ -126,14 +112,14 @@ typedef struct
/**
* @brief Enable the IWDG peripheral.
- * @param __HANDLE__ IWDG handle
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+ * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@@ -194,21 +180,21 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__ IWDG handle
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__ IWDG handle
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
- * @param __PRESCALER__ IWDG prescaler value
+ * @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
@@ -221,18 +207,19 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @brief Check IWDG reload value.
- * @param __RELOAD__ IWDG reload value
+ * @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
- * @param __WINDOW__ IWDG window value
+ * @param __WINDOW__ IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
+
/**
* @}
*/
@@ -250,6 +237,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
}
#endif
-#endif /* __STM32F7xx_HAL_IWDG_H */
+#endif /* STM32F7xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_jpeg.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_jpeg.h
index 4cfc2606e1cb4fc5f58105cc99645a19e116f542..52022146dbd8abd2f2d66ed53c5bc28d9db66af9 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_jpeg.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_jpeg.h
@@ -6,41 +6,25 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_JPEG_H
-#define __STM32F7xx_HAL_JPEG_H
+#ifndef STM32F7xx_HAL_JPEG_H
+#define STM32F7xx_HAL_JPEG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#if defined (JPEG)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -63,19 +47,19 @@
*/
typedef struct
{
- uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
- This parameter can be a value of @ref JPEG_ColorSpace_Type */
+ uint32_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
+ This parameter can be a value of @ref JPEG_ColorSpace */
- uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
- This parameter can be a value of @ref JPEG_ChromaSubsampling_Type */
+ uint32_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
+ This parameter can be a value of @ref JPEG_ChromaSubsampling */
- uint32_t ImageHeight; /*!< Image height : number of lines */
+ uint32_t ImageHeight; /*!< Image height : number of lines */
- uint32_t ImageWidth; /*!< Image width : number of pixels per line */
+ uint32_t ImageWidth; /*!< Image width : number of pixels per line */
- uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
+ uint32_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
-}JPEG_ConfTypeDef;
+} JPEG_ConfTypeDef;
/**
* @}
*/
@@ -93,7 +77,7 @@ typedef enum
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
-}HAL_JPEG_STATETypeDef;
+} HAL_JPEG_STATETypeDef;
/**
* @}
@@ -104,7 +88,11 @@ typedef enum
* @brief JPEG handle Structure definition
* @{
*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+typedef struct __JPEG_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
{
JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
@@ -144,12 +132,70 @@ typedef struct
__IO uint32_t Context; /*!< JPEG Internal context */
-}JPEG_HandleTypeDef;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg,
+ JPEG_ConfTypeDef *pInfo); /*!< JPEG Info ready callback */
+ void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef
+ *hjpeg); /*!< JPEG Encode complete callback */
+ void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef
+ *hjpeg); /*!< JPEG Decode complete callback */
+ void (*ErrorCallback)(struct __JPEG_HandleTypeDef
+ *hjpeg); /*!< JPEG Error callback */
+ void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg,
+ uint32_t NbDecodedData); /*!< JPEG Get Data callback */
+ void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
+ uint32_t OutDataLength); /*!< JPEG Data ready callback */
+
+ void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg); /*!< JPEG Msp Init callback */
+ void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef
+ *hjpeg); /*!< JPEG Msp DeInit callback */
+
+
+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
+
+} JPEG_HandleTypeDef;
/**
* @}
*/
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition
+ * @brief HAL JPEG Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, /*!< JPEG Encode Complete callback ID */
+ HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, /*!< JPEG Decode Complete callback ID */
+ HAL_JPEG_ERROR_CB_ID = 0x03U, /*!< JPEG Error callback ID */
+
+ HAL_JPEG_MSPINIT_CB_ID = 0x04U, /*!< JPEG MspInit callback ID */
+ HAL_JPEG_MSPDEINIT_CB_ID = 0x05U /*!< JPEG MspDeInit callback ID */
+
+} HAL_JPEG_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition
+ * @brief HAL JPEG Callback pointer definition
+ * @{
+ */
+typedef void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg); /*!< pointer to a common JPEG callback function */
+typedef void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
+ JPEG_ConfTypeDef *pInfo); /*!< pointer to an Info ready JPEG callback function */
+typedef void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
+ uint32_t NbDecodedData); /*!< pointer to a Get data JPEG callback function */
+typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
+ uint32_t OutDataLength); /*!< pointer to a Data ready JPEG callback function */
+/**
+ * @}
+ */
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -170,7 +216,9 @@ typedef struct
#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
-
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -179,13 +227,13 @@ typedef struct
* @brief JPEG Quantization Table Size
* @{
*/
-#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)
+#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */
/**
* @}
*/
-/** @defgroup JPEG_ColorSpace_Type JPEG ColorSpace
+/** @defgroup JPEG_ColorSpace JPEG ColorSpace
* @brief JPEG Color Space
* @{
*/
@@ -199,7 +247,7 @@ typedef struct
*/
-/** @defgroup JPEG_ChromaSubsampling_Type JPEG Chrominance Sampling
+/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
* @brief JPEG Chrominance Sampling
* @{
*/
@@ -277,7 +325,15 @@ typedef struct
* @param __HANDLE__ specifies the JPEG handle.
* @retval None
*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/**
@@ -310,7 +366,7 @@ typedef struct
* and the internal registers have been updated
* @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
*
- * @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
+ * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
@@ -323,7 +379,7 @@ typedef struct
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
- * @retval : None
+ * @retval None
*/
#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
@@ -341,14 +397,14 @@ typedef struct
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
- * @retval : No retrun
+ * @retval No retrun
*/
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
/**
* @brief Disable Interrupt.
* @param __HANDLE__ specifies the JPEG handle.
- * @param __INTERRUPT__ specifies the interrupt to disable
+ * @param __INTERRUPT__ specifies the interrupt to disable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
@@ -357,11 +413,11 @@ typedef struct
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
- * @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
+ * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
* located in the same IT enable register (CR register).
- * @retval : No retrun
+ * @retval No retrun
*/
-#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
+#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
/**
@@ -376,7 +432,7 @@ typedef struct
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
- * @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
+ * @retval returns The new state of __INTERRUPT__ (Enabled or disabled)
*/
#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
@@ -398,6 +454,24 @@ HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
+ pJPEG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
+ pJPEG_InfoReadyCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
+ pJPEG_DataReadyCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg);
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -410,7 +484,8 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
-HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
+HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
+ uint8_t *QTable2, uint8_t *QTable3);
/**
* @}
@@ -420,12 +495,18 @@ HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t
* @{
*/
/* JPEG processing functions **************************************/
-HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
-HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
-HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
-HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
+HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
+HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout);
+HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength);
+HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength);
+HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength);
+HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
@@ -440,12 +521,12 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
* @{
*/
/* JPEG Decode/Encode callback functions ********************************************************/
-void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
+void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
-void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
+void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
/**
* @}
@@ -517,10 +598,6 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
* @{
*/
-/** @defgroup JPEG_IS_Definitions JPEG Private macros to check input parameters
- * @{
- */
-
#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
@@ -539,10 +616,6 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
* @}
*/
-/**
- * @}
- */
-
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
* @{
@@ -569,11 +642,11 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
* @}
*/
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* JPEG */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_JPEG_H */
+#endif /* STM32F7xx_HAL_JPEG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_lptim.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_lptim.h
index 7672896ed7d609201058d75c7abcfb560451f046..5c495c0a5cfe25cf93d3ec5dde8327f6790df71c 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_lptim.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_lptim.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc.h
index cf57c9e30af562b06dca1a317f2a90f8aa65d401..0d68f21e154190e0d1c8c17f3fd0385e641dc9ed 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc.h
@@ -6,42 +6,26 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_LTDC_H
-#define __STM32F7xx_HAL_LTDC_H
+#ifndef STM32F7xx_HAL_LTDC_H
+#define STM32F7xx_HAL_LTDC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+#if defined (LTDC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -60,7 +44,7 @@
/** @defgroup LTDC_Exported_Types LTDC Exported Types
* @{
*/
-#define MAX_LAYER 2
+#define MAX_LAYER 2U
/**
* @brief LTDC color structure definition
@@ -176,12 +160,16 @@ typedef enum
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
-}HAL_LTDC_StateTypeDef;
+} HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+typedef struct __LTDC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
@@ -195,7 +183,41 @@ typedef struct
__IO uint32_t ErrorCode; /*!< LTDC Error code */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
+ void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
+ void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
+
+ void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
+ void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+
} LTDC_HandleTypeDef;
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL LTDC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
+ HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
+
+ HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
+ HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
+ HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
+
+} HAL_LTDC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL LTDC Callback pointer definition
+ */
+typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -208,10 +230,22 @@ typedef struct
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
-#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */
-#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */
-#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */
-#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */
+#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
+#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
+#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
+#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Layer LTDC Layer
+ * @{
+ */
+#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
+#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
/**
* @}
*/
@@ -219,8 +253,8 @@ typedef struct
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
-#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
+#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
@@ -228,8 +262,8 @@ typedef struct
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
-#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
+#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
*/
@@ -237,8 +271,8 @@ typedef struct
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
-#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */
-#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
+#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
@@ -246,8 +280,8 @@ typedef struct
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
-#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */
-#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
+#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
@@ -255,8 +289,8 @@ typedef struct
/** @defgroup LTDC_SYNC LTDC SYNC
* @{
*/
-#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
-#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
/**
* @}
*/
@@ -264,7 +298,7 @@ typedef struct
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
-#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */
+#define LTDC_COLOR 0x000000FFU /*!< Color mask */
/**
* @}
*/
@@ -272,8 +306,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
-#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
@@ -281,8 +315,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
-#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */
-#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
@@ -290,14 +324,14 @@ typedef struct
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
-#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
@@ -305,7 +339,7 @@ typedef struct
/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
-#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
+#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
/**
* @}
*/
@@ -313,11 +347,11 @@ typedef struct
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
-#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
-#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
+#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
+#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
-#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
-#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
+#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
+#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
/**
* @}
*/
@@ -325,21 +359,21 @@ typedef struct
/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
-#define LTDC_IT_LI LTDC_IER_LIE
-#define LTDC_IT_FU LTDC_IER_FUIE
-#define LTDC_IT_TE LTDC_IER_TERRIE
-#define LTDC_IT_RR LTDC_IER_RRIE
+#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
+#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
+#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
+#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
/**
* @}
*/
-/** @defgroup LTDC_Flag LTDC Flag
+/** @defgroup LTDC_Flags LTDC Flags
* @{
*/
-#define LTDC_FLAG_LI LTDC_ISR_LIF
-#define LTDC_FLAG_FU LTDC_ISR_FUIF
-#define LTDC_FLAG_TE LTDC_ISR_TERRIF
-#define LTDC_FLAG_RR LTDC_ISR_RRIF
+#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
+#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
+#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
+#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
/**
* @}
*/
@@ -347,8 +381,8 @@ typedef struct
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
-#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
-#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
+#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
+#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
@@ -362,56 +396,71 @@ typedef struct
* @{
*/
-/** @brief Reset LTDC handle state
- * @param __HANDLE__ specifies the LTDC handle.
+/** @brief Reset LTDC handle state.
+ * @param __HANDLE__ LTDC handle
* @retval None
*/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @brief Enable the LTDC.
- * @param __HANDLE__ LTDC handle
+ * @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
/**
* @brief Disable the LTDC.
- * @param __HANDLE__ LTDC handle
+ * @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
/**
* @brief Enable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be enabled
- * This parameter can be 0 or 1
+ * @param __HANDLE__ LTDC handle
+ * @param __LAYER__ Specify the layer to be enabled.
+ * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
- * @param __HANDLE__ LTDC handle
- * @param __LAYER__ Specify the layer to be disabled
- * This parameter can be 0 or 1
+ * @param __HANDLE__ LTDC handle
+ * @param __LAYER__ Specify the layer to be disabled.
+ * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
/**
- * @brief Reload Layer Configuration.
- * @param __HANDLE__ LTDC handle
+ * @brief Reload immediately all LTDC Layers.
+ * @param __HANDLE__ LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/**
+ * @brief Reload during vertical blanking period all LTDC Layers.
+ * @param __HANDLE__ LTDC handle
* @retval None.
*/
-#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
/* Interrupt & Flag management */
/**
* @brief Get the LTDC pending flags.
- * @param __HANDLE__ LTDC handle
- * @param __FLAG__ Get the specified flag.
+ * @param __HANDLE__ LTDC handle
+ * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
@@ -423,8 +472,8 @@ typedef struct
/**
* @brief Clears the LTDC pending flags.
- * @param __HANDLE__ LTDC handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__ LTDC handle
+ * @param __FLAG__ Specify the flag to clear.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
@@ -436,8 +485,8 @@ typedef struct
/**
* @brief Enables the specified LTDC interrupts.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ specifies the LTDC interrupt sources to be enabled.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
@@ -449,8 +498,8 @@ typedef struct
/**
* @brief Disables the specified LTDC interrupts.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ specifies the LTDC interrupt sources to be disabled.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
@@ -461,9 +510,9 @@ typedef struct
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
- * @brief Checks whether the specified LTDC interrupt has occurred or not.
- * @param __HANDLE__ LTDC handle
- * @param __INTERRUPT__ specifies the LTDC interrupt source to check.
+ * @brief Check whether the specified LTDC interrupt has occurred or not.
+ * @param __HANDLE__ LTDC handle
+ * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
* This parameter can be one of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
@@ -471,15 +520,13 @@ typedef struct
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval The state of INTERRUPT (SET or RESET).
*/
-#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/**
* @}
*/
-#if defined (STM32F769xx) || defined (STM32F779xx)
/* Include LTDC HAL Extension module */
#include "stm32f7xx_hal_ltdc_ex.h"
-#endif /* STM32F769xx) | STM32F779xx */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
@@ -491,11 +538,18 @@ typedef struct
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
-void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -557,79 +611,52 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
* @}
*/
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LTDC_Private_Types LTDC Private Types
- * @{
- */
-
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Variables LTDC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
/* Private constants ---------------------------------------------------------*/
-/** @defgroup LTDC_Private_Constants LTDC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
-#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
-#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
- ((HSPOL) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
- ((VSPOL) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
- ((DEPOL) == LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
- ((PCPOL) == LTDC_PCPOLARITY_IIPC))
-#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
-#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
-#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
-#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
-#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
-#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
- ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
-#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
- ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
-#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
- ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
-#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
-#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
-#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
-#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
-#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
-#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
-#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
-#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
-#define IS_LTDC_RELAOD(RELOADTYPE) (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
+#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
+#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
+#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
+ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
+#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
+ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
+#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
+#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
+#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
@@ -646,15 +673,17 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
/**
* @}
*/
+#endif /* LTDC */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_LTDC_H */
+#endif /* STM32F7xx_HAL_LTDC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc_ex.h
index 14993b454eaba4f7842fd2046df8ddffcbb97b7d..f13712ed875889f9649a92a0a30c0095b2eb58a4 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_ltdc_ex.h
@@ -6,42 +6,27 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_LTDC_EX_H
-#define __STM32F7xx_HAL_LTDC_EX_H
+#ifndef STM32F7xx_HAL_LTDC_EX_H
+#define STM32F7xx_HAL_LTDC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined (STM32F769xx) || defined (STM32F779xx)
+#if defined (LTDC) && defined (DSI)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dsi.h"
@@ -56,79 +41,30 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
-/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+/** @addtogroup LTDCEx_Exported_Functions
* @{
*/
-HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
-HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
-/**
- * @}
- */
-
- /* Private types -------------------------------------------------------------*/
-/** @defgroup LTDCEx_Private_Types LTDCEx Private Types
+/** @addtogroup LTDCEx_Exported_Functions_Group1
* @{
*/
-
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables
- * @{
- */
-
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
-/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros
- * @{
- */
-
- /**
- * @}
- */
-
/* Private functions ---------------------------------------------------------*/
-/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions
- * @{
- */
-
-/**
- * @}
- */
/**
* @}
@@ -138,12 +74,12 @@ HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef
* @}
*/
-#endif /*STM32F769xx | STM32F779xx */
+#endif /* LTDC && DSI */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_LTDC_EX_H */
+#endif /* STM32F7xx_HAL_LTDC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mdios.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mdios.h
index dc96432034b623d6411ef0c401323ee18bbee9f2..6a908d2c6d7427501028d37a5e8c11ea0b9b7445 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mdios.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mdios.h
@@ -5,30 +5,14 @@
* @brief Header file of MDIOS HAL module.
******************************************************************************
* @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -95,7 +79,11 @@ typedef struct
* @{
*/
+#if ( USE_HAL_MDIOS_REGISTER_CALLBACKS == 1 )
+typedef struct __MDIOS_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
{
MDIOS_TypeDef *Instance; /*!< Register base address */
@@ -104,8 +92,41 @@ typedef struct
__IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
HAL_LockTypeDef Lock; /*!< MDIOS Lock */
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+ void (* WriteCpltCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Write Complete Callback */
+ void (* ReadCpltCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Read Complete Callback */
+ void (* ErrorCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Error Callback */
+ void (* WakeUpCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Wake UP Callback */
+ void (* MspInitCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Msp Init callback */
+ void (* MspDeInitCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Msp DeInit callback */
+
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
}MDIOS_HandleTypeDef;
+#if ( USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL MDIOS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_MDIOS_MSPINIT_CB_ID = 0x00U, /*!< MDIOS MspInit callback ID */
+ HAL_MDIOS_MSPDEINIT_CB_ID = 0x01U, /*!< MDIOS MspDeInit callback ID */
+ HAL_MDIOS_WRITE_COMPLETE_CB_ID = 0x02U, /*!< MDIOS Write Complete Callback ID */
+ HAL_MDIOS_READ_COMPLETE_CB_ID = 0x03U, /*!< MDIOS Read Complete Callback ID */
+ HAL_MDIOS_ERROR_CB_ID = 0x04U, /*!< MDIOS Error Callback ID */
+ HAL_MDIOS_WAKEUP_CB_ID = 0x05U /*!< MDIOS Wake UP Callback ID */
+}HAL_MDIOS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL MDIOS Callback pointer definition
+ */
+typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< pointer to an MDIOS callback function */
+
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -247,7 +268,15 @@ typedef struct
* @param __HANDLE__ MDIOS handle.
* @retval None
*/
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_MDIOS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/**
* @brief Enable/Disable the MDIOS peripheral.
@@ -425,6 +454,11 @@ HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mmc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mmc.h
index 1b48d2a10e468af51728f2c90084c87bf4566bbc..00f439923092436196b36b8a54b4fa54f1c5a5e7 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mmc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_mmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -124,7 +108,11 @@ typedef struct
/**
* @brief MMC handle Structure definition
*/
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+typedef struct __MMC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
@@ -156,6 +144,15 @@ typedef struct
uint32_t CID[4]; /*!< MMC card identification number table */
+ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+
+ void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
+#endif
}MMC_HandleTypeDef;
/**
@@ -227,10 +224,35 @@ typedef struct
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_MMC_CardCIDTypeDef;
+/**
+ * @}
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
+ HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
+ HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
+ HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
+
+ HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
+ HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
+}HAL_MMC_CallbackIDTypeDef;
/**
* @}
*/
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+ * @{
+ */
+typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+#endif
/**
* @}
*/
@@ -282,7 +304,9 @@ typedef struct
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -335,6 +359,19 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+/** @brief Reset MMC handle state.
+ * @param __HANDLE__ : MMC handle.
+ * @retval None
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
+#endif
/**
* @brief Enable the MMC device.
@@ -565,6 +602,12 @@ void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/* MMC callback registering/unregistering */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nand.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nand.h
index 236bdf794078824c3614244a1e1881b834dc2512..7c3bc16aa02697d974fa5a52fb6d018b47dc8a8f 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nand.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nand.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -128,7 +112,11 @@ typedef struct
/**
* @brief NAND handle Structure definition
*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+typedef struct __NAND_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
@@ -140,7 +128,30 @@ typedef struct
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
-}NAND_HandleTypeDef;
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
+#endif
+} NAND_HandleTypeDef;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL NAND Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
+ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
+ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
+}HAL_NAND_CallbackIDTypeDef;
+
+/**
+ * @brief HAL NAND Callback pointer definition
+ */
+typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
+#endif
+
/**
* @}
*/
@@ -155,7 +166,15 @@ typedef struct
* @param __HANDLE__ specifies the NAND handle.
* @retval None
*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+#endif
/**
* @}
@@ -209,6 +228,12 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressT
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/* NAND callback registering/unregistering */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nor.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nor.h
index 246edbfdd88a810857a650bb2665d94572695ec4..411e3e0ed96431a1c69af4c0ba523a90a2f75a36 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nor.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_nor.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -119,7 +103,12 @@ typedef struct
/**
* @brief NOR handle Structure definition
*/
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+typedef struct __NOR_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -131,7 +120,27 @@ typedef struct
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-}NOR_HandleTypeDef;
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
+#endif
+} NOR_HandleTypeDef;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL NOR Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
+ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
+}HAL_NOR_CallbackIDTypeDef;
+
+/**
+ * @brief HAL NOR Callback pointer definition
+ */
+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
+#endif
/**
* @}
*/
@@ -145,7 +154,15 @@ typedef struct
* @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_NOR_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+#endif
/**
* @}
*/
@@ -185,6 +202,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/* NOR callback registering/unregistering */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd.h
index 984eeedd162fd21b6ec33376b17e7b7ff33fb8b2..4afcf4112faaf4824955c906136e94c067325158 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd.h
@@ -6,44 +6,30 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PCD_H
-#define __STM32F7xx_HAL_PCD_H
+#ifndef STM32F7xx_HAL_PCD_H
+#define STM32F7xx_HAL_PCD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_usb.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -76,20 +62,39 @@ typedef enum
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
-}PCD_LPM_StateTypeDef;
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+ PCD_BCD_ERROR = 0xFF,
+ PCD_BCD_CONTACT_DETECTION = 0xFE,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00,
+} PCD_BCD_MsgTypeDef;
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
-#endif /* USB_OTG_FS || USB_OTG_HS */
-
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief PCD Handle Structure definition
*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
@@ -98,13 +103,34 @@ typedef struct
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
+
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
+ This parameter can be set to ENABLE or DISABLE */
void *pData; /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
+ void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
+ void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
+ void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
+ void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
+ void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
+ void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
+
+ void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
+ void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
+ void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
+ void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
+ void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
+
+ void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
@@ -122,10 +148,8 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#if defined (USB_OTG_HS)
#define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U
-#endif
#define PCD_SPEED_FULL 2U
/**
* @}
@@ -141,15 +165,14 @@ typedef struct
* @}
*/
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+ * @brief PCD Error Code definition
* @{
*/
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE 9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE 5U
-#endif /* USBD_HS_TRDT_VALUE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -199,7 +222,7 @@ typedef struct
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
@@ -219,6 +242,64 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+ * @brief HAL USB OTG PCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
+ HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
+ HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
+ HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
+ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
+ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+
+ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
+ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+ * @brief HAL USB OTG PCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
+
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -232,17 +313,18 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
@@ -258,7 +340,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
@@ -297,27 +379,44 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-#ifndef LL_EXTI_LINE_18
-#define LL_EXTI_LINE_18 0x00040000U
-#endif
-
-#ifndef LL_EXTI_LINE_20
-#define LL_EXTI_LINE_20 0x00100000U
-#endif
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17 Connected to the USB EXTI Line */
-#define USB_OTG_HS_WAKEUP_EXTI_LINE LL_EXTI_LINE_20 /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
-
/**
* @}
*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
+#endif
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
@@ -334,11 +433,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_PCD_H */
+#endif /* STM32F7xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd_ex.h
index ede43f0600e6fc8a099ef9df90b474606227c0af..8f9da2812236ba93e129d27a756b4c7018eaae10 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pcd_ex.h
@@ -6,44 +6,29 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_PCD_EX_H
-#define __STM32F7xx_HAL_PCD_EX_H
+#ifndef STM32F7xx_HAL_PCD_EX_H
+#define STM32F7xx_HAL_PCD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -52,23 +37,6 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
-typedef enum
-{
- PCD_LPM_L0_ACTIVE = 0x00, /* on */
- PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-
-typedef enum
-{
- PCD_BCD_ERROR = 0xFF,
- PCD_BCD_CONTACT_DETECTION = 0xFE,
- PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
- PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
- PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
- PCD_BCD_DISCOVERY_COMPLETED = 0x00,
-
-}PCD_BCD_MsgTypeDef;
-
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -82,10 +50,12 @@ typedef enum
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
@@ -104,12 +74,13 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_PCD_EX_H */
+#endif /* STM32F7xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr.h
index 23899e08b248f3da0f96d03bd506f1d1beafdf00..99d6c23c0402ce64f6c6a43694c1d0d5e3942311 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr_ex.h
index 2bf158b9bdb06f77e23a5fd1b7b4af625858fdc7..91dc4e45ef3050dcac87a21c26b592844b5eab5f 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_pwr_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_qspi.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_qspi.h
index b573720137db633990f990d1a0176e16df80d1b2..70a3220d7f7a8b0a33435f063bdc040ddeaa3340 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_qspi.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_qspi.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -112,7 +96,11 @@ typedef enum
/**
* @brief QSPI Handle Structure definition
*/
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+typedef struct __QSPI_HandleTypeDef
+#else
typedef struct
+#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
@@ -127,6 +115,21 @@ typedef struct
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
+ void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
+
+ void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
+#endif
}QSPI_HandleTypeDef;
/**
@@ -195,6 +198,33 @@ typedef struct
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL QSPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
+ HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
+ HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
+ HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
+ HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
+ HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
+ HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
+ HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
+ HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
+ HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
+
+ HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
+ HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
+}HAL_QSPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL QSPI Callback pointer definition
+ */
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
+#endif
/**
* @}
*/
@@ -211,6 +241,9 @@ typedef struct
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -432,7 +465,15 @@ typedef struct
* @param __HANDLE__ QSPI handle.
* @retval None
*/
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+#endif
/** @brief Enable QSPI
* @param __HANDLE__ specifies the QSPI Handle.
@@ -580,6 +621,12 @@ void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/* QSPI callback registering/unregistering */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc.h
index 8432564df55e1ae1f920b58c16d36a39a9736560..821bdb98bff81c6f5d1f020d07f550b8828da8a2 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc_ex.h
index d43c6bfc767409d7ed0dd4d6e6e3042a3777ad97..0a7580d564deb5a069b8040dde87c24fec802236 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rcc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rng.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rng.h
index a22f2fe6b94884f4afea0130b703a89b5e64b723..3245aa70c6e9f31e4d802fd7713774abffd4e0b2 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rng.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rng.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_RNG_H
-#define __STM32F7xx_HAL_RNG_H
+#ifndef STM32F7xx_HAL_RNG_H
+#define STM32F7xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
@@ -48,6 +32,8 @@
* @{
*/
+#if defined (RNG)
+
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
@@ -59,7 +45,15 @@
* @{
*/
-/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
* @{
*/
typedef enum
@@ -70,26 +64,61 @@ typedef enum
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
-}HAL_RNG_StateTypeDef;
+} HAL_RNG_StateTypeDef;
/**
* @}
*/
-/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+typedef struct __RNG_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
{
RNG_TypeDef *Instance; /*!< Register base address */
- uint32_t RandomNumber; /*!< Last Generated random number */
-
HAL_LockTypeDef Lock; /*!< RNG locking object */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
-}RNG_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< RNG Error code */
+
+ uint32_t RandomNumber; /*!< Last Generated RNG Data */
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
+ void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
+
+ void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
+ void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+} RNG_HandleTypeDef;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RNG Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
+
+ HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
+ HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
+
+} HAL_RNG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RNG Callback pointer definition
+ */
+typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
+typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
@@ -100,7 +129,6 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
@@ -121,7 +149,21 @@ typedef struct
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
+/**
+ * @}
+ */
+/** @defgroup RNG_Error_Definition RNG Error Definition
+ * @{
+ */
+#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
+#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
+#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
@@ -131,7 +173,6 @@ typedef struct
*/
/* Exported macros -----------------------------------------------------------*/
-
/** @defgroup RNG_Exported_Macros RNG Exported Macros
* @{
*/
@@ -140,7 +181,15 @@ typedef struct
* @param __HANDLE__ RNG Handle
* @retval None
*/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_RNG_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @brief Enables the RNG peripheral.
@@ -161,9 +210,9 @@ typedef struct
* @param __HANDLE__ RNG Handle
* @param __FLAG__ RNG flag
* This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready
- * @arg RNG_FLAG_CECS: Clock error current status
- * @arg RNG_FLAG_SECS: Seed error current status
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
@@ -178,8 +227,6 @@ typedef struct
*/
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
-
-
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__ RNG Handle
@@ -227,14 +274,23 @@ typedef struct
* @{
*/
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -244,14 +300,13 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
/**
* @}
@@ -261,47 +316,11 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
- * @{
- */
-
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
/**
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
- * @{
- */
-
/**
* @}
*/
@@ -314,34 +333,18 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
- * @{
- */
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
- * @{
- */
-
/**
* @}
*/
-/**
- * @}
- */
+#endif /* RNG */
/**
* @}
@@ -351,6 +354,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
}
#endif
-#endif /* __STM32F7xx_HAL_RNG_H */
+
+#endif /* STM32F7xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc.h
index 0229e146de1b2c0f6d951c71169639d9d209842d..87feafad8429013fbbcda2e1b0f6e5685d90bdf9 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -125,7 +109,7 @@ typedef struct
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
}RTC_TimeTypeDef;
@@ -176,7 +160,11 @@ typedef struct
/**
* @brief RTC Handle Structure definition
*/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -186,8 +174,52 @@ typedef struct
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
+
+ void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
+
+ void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
+
+ void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
+
+ void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
+
+ void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
+
+ void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
+
+ void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
+
+ void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
}RTC_HandleTypeDef;
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RTC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
+ HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
+ HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
+}HAL_RTC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RTC Callback pointer definition
+ */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -419,7 +451,15 @@ typedef struct
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0u)
+#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
@@ -635,6 +675,12 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc_ex.h
index 071db3fbac098b1827df529d391502004d8e7e51..1738e64620152f1b942a8af2c44c9fc575b828f5 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_rtc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai.h
index 4d35f96097c3c7b53a748a99d5c73dddf175fe24..5e384b937075198e9692dca9db55a1b8af3e6773 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -232,11 +216,42 @@ typedef struct __SAI_HandleTypeDef
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
__IO uint32_t ErrorCode; /*!< SAI Error code */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
+ void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
+ void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
+ void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
+ void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
+ void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
+ void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
+#endif
}SAI_HandleTypeDef;
/**
* @}
*/
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief SAI callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
+ HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
+ HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
+ HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
+ HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
+ HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
+ HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
+} HAL_SAI_CallbackIDTypeDef;
+
+/**
+ * @brief SAI callback pointer definition
+ */
+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
+#endif
+
/**
* @}
*/
@@ -259,6 +274,9 @@ typedef struct __SAI_HandleTypeDef
#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */
#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -395,7 +413,6 @@ typedef struct __SAI_HandleTypeDef
* @}
*/
-
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{
*/
@@ -423,8 +440,7 @@ typedef struct __SAI_HandleTypeDef
* @}
*/
-
- /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{
*/
#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
@@ -556,17 +572,24 @@ typedef struct __SAI_HandleTypeDef
*/
/* Exported macro ------------------------------------------------------------*/
-
/** @defgroup SAI_Exported_Macros SAI Exported Macros
- * @brief macros to handle interrupts and specific configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific configurations
+ * @{
+ */
/** @brief Reset SAI handle state.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/** @brief Enable or disable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
@@ -638,13 +661,11 @@ typedef struct __SAI_HandleTypeDef
*/
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup SAI_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
-
/** @addtogroup SAI_Exported_Functions_Group1
* @{
*/
@@ -654,6 +675,14 @@ HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/* SAI callbacks register/unregister functions ********************************/
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai_ex.h
index e888f8f8e3db3b1bfba75deaf32f226f2105cc8d..1a521cb593b2557c51a7d91e18f98be30fce6fac 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sai_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sd.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sd.h
index 1d06b1c1972e35b3bee6d5c7e6cb783466033ec2..3762b8da254ec06eb251f2489f8bc190eedeb668 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sd.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sd.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -127,7 +111,7 @@ typedef struct
/**
* @brief SD handle Structure definition
*/
-typedef struct
+typedef struct __SD_HandleTypeDef
{
SD_TypeDef *Instance; /*!< SD registers base address */
@@ -159,6 +143,15 @@ typedef struct
uint32_t CID[4]; /*!< SD card identification number table */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
+
+ void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
+#endif
}SD_HandleTypeDef;
/**
@@ -255,6 +248,32 @@ typedef struct
* @}
*/
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
+ HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
+ HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
+ HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
+
+ HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
+ HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
+}HAL_SD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+ * @{
+ */
+typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+#endif
/**
* @}
*/
@@ -306,6 +325,10 @@ typedef struct
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif
+
/**
* @}
*/
@@ -354,6 +377,19 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+/** @brief Reset SD handle state.
+ * @param __HANDLE__ : SD handle.
+ * @retval None
+ */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif
/**
* @brief Enable the SD device.
@@ -584,6 +620,12 @@ void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sdram.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sdram.h
index 04645047888808affb032c010a3783d9f59d0c79..1eacf0fee330f3b29b29fff8ee60081aec6ad982 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sdram.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sdram.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -75,7 +59,11 @@ typedef enum
/**
* @brief SDRAM handle Structure definition
*/
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SDRAM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
{
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
@@ -87,7 +75,34 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-}SDRAM_HandleTypeDef;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */
+ void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */
+ void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */
+ void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */
+#endif
+} SDRAM_HandleTypeDef;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SDRAM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */
+ HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */
+ HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */
+ HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */
+ HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */
+}HAL_SDRAM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SDRAM Callback pointer definition
+ */
+typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
+typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
@@ -103,8 +118,15 @@ typedef struct
* @param __HANDLE__ specifies the SDRAM handle.
* @retval None
*/
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
-
+#endif
/**
* @}
*/
@@ -148,6 +170,13 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/* SDRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard.h
index 569de3c4a7dbaafa317ddfee1ff78ba0ae644243..6d0ae017143cda0c23c2f392bfa20f97e4f25db5 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SMARTCARD_H
-#define __STM32F7xx_HAL_SMARTCARD_H
+#ifndef STM32F7xx_HAL_SMARTCARD_H
+#define STM32F7xx_HAL_SMARTCARD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -64,7 +48,8 @@ typedef struct
{
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+ Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
+ where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
@@ -72,53 +57,55 @@ typedef struct
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
- uint32_t Parity; /*!< Specifies the parity mode.
+ uint16_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@note The parity is enabled by default (PCE is forced to 1).
Since the WordLength is forced to 8 bits + parity, M is
forced to 1 and the parity bit is the 9th bit. */
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */
+ deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler */
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
+ by 2 to give the division factor of the source clock frequency */
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time */
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_State */
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
- uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
- uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
- it is used to implement the Character Wait Time (CWT) and
- Block Wait Time (BWT). It is coded over 24 bits. */
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
- uint32_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
- This parameter can be any value from 0x0 to 0xFF */
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFF */
- uint32_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
- receive and transmit mode). When set to 0, retransmission is
- disabled. Otherwise, its maximum value is 7 (before signalling
- an error) */
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
-}SMARTCARD_InitTypeDef;
+} SMARTCARD_InitTypeDef;
/**
* @brief SMARTCARD advanced features initalization structure definition
@@ -154,11 +141,11 @@ typedef struct
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
relevant flag is available) or once guard time period has elapsed.
This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
-}SMARTCARD_AdvFeatureInitTypeDef;
+} SMARTCARD_AdvFeatureInitTypeDef;
/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+ * @brief HAL SMARTCARD State definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -167,14 +154,14 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -184,9 +171,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -195,384 +182,329 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
-
-/**
- * @brief SMARTCARD clock sources definition
- */
-typedef enum
-{
- SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
-}SMARTCARD_ClockSourceTypeDef;
+typedef uint32_t HAL_SMARTCARD_StateTypeDef;
/**
* @brief SMARTCARD handle Structure definition
*/
-typedef struct
+typedef struct __SMARTCARD_HandleTypeDef
{
- USART_TypeDef *Instance; /*!< USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
- __IO uint32_t ErrorCode; /* SmartCard Error code */
+ HAL_LockTypeDef Lock; /*!< Locking object */
-}SMARTCARD_HandleTypeDef;
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
- * @{
- */
-/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
- * @brief SMARTCARD Error Code
- * @{
- */
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20U) /*!< Receiver TimeOut error */
-/**
- * @}
- */
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
-/**
- * @}
- */
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
- * @{
- */
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
+
+ void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
+
+ void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
+
+ void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
- * @}
+ * @brief HAL SMARTCARD Callback ID enumeration definition
*/
+typedef enum
+{
+ HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
+ HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
+ HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
+ HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
+ HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
+ HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
+
+ HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
+ HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
- * @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
- * @}
+ * @brief HAL SMARTCARD Callback pointer definition
*/
+typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
- * @}
+ * @brief SMARTCARD clock sources
*/
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
+} SMARTCARD_ClockSourceTypeDef;
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
- * @{
- */
-#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000U)
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
* @{
*/
-#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000U)
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-/**
- * @}
- */
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000U)
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
/**
* @}
*/
-/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling
+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000U)
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
-
-/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000U)
+#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */
/**
* @}
*/
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
-#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
+#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */
+#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
/**
* @}
*/
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
-
+#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */
/**
* @}
*/
-/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
* @{
*/
-#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
-#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
+#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */
/**
* @}
*/
-/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */
/**
* @}
*/
-/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */
/**
* @}
*/
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
* @{
*/
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */
/**
* @}
*/
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */
/**
* @}
*/
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
* @{
*/
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */
/**
* @}
*/
-/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
-/** @defgroup SmartCard_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
* @{
*/
-#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000U)
-#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000U)
-#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000U)
-#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000U)
-#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800U)
-#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
-#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
-#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
-#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
-#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
-#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
-#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
* @{
*/
-
-#define SMARTCARD_IT_PE ((uint16_t)0x0028U)
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727U)
-#define SMARTCARD_IT_TC ((uint16_t)0x0626U)
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U)
-#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U)
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060U)
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300U)
-#define SMARTCARD_IT_NE ((uint16_t)0x0200U)
-#define SMARTCARD_IT_FE ((uint16_t)0x0100U)
-
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU)
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU)
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
-
-/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
* @{
*/
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear Flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
* @{
*/
-#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
-
-/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
* @{
*/
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17U)
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
-/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
* @{
*/
-#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8U)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
/**
* @}
*/
-/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
* @{
*/
-#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24U)
+#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */
/**
* @}
*/
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
* @{
*/
-#define SMARTCARD_IT_MASK ((uint16_t)0x001FU)
+#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */
+#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */
+#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */
+#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */
/**
* @}
*/
@@ -581,45 +513,38 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
-/** @brief Reset SMARTCARD handle state
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2
+/** @brief Reset SMARTCARD handle states.
+ * @param __HANDLE__ SMARTCARD handle.
* @retval None
*/
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
-
-/** @brief Flush the Smartcard DR register
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/** @brief Flush the Smartcard Data registers.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @retval None
*/
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
-
-/** @brief Checks whether the specified Smartcard flag is set or not.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
- * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg SMARTCARD_FLAG_BUSY: Busy flag
- * @arg SMARTCARD_FLAG_EOBF: End of block flag
- * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
- * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
- * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
- * @arg SMARTCARD_FLAG_NE: Noise Error flag
- * @arg SMARTCARD_FLAG_FE: Framing Error flag
- * @arg SMARTCARD_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -631,9 +556,7 @@ typedef struct
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
* @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
- @if STM32L443xx
- * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
- @endif
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
@@ -646,7 +569,6 @@ typedef struct
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
@@ -671,160 +593,460 @@ typedef struct
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
-/** @brief Enables the specified SmartCard interrupt.
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
+ * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
+ * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
+ * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
+ * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
+ * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
+ * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
+ * @arg @ref SMARTCARD_FLAG_NE Noise error flag
+ * @arg @ref SMARTCARD_FLAG_FE Framing error flag
+ * @arg @ref SMARTCARD_FLAG_PE Parity error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-/** @brief Disables the specified SmartCard interrupt.
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __IT__ specifies the SMARTCARD interrupt to check.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
- * @arg SMARTCARD_IT_NE: Noise Error interrupt
- * @arg SMARTCARD_IT_FE: Framing Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
-
-/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __IT__ specifies the SMARTCARD interrupt source to check.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
- * @arg SMARTCARD_IT_NE: Noise Error interrupt
- * @arg SMARTCARD_IT_FE: Framing Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
- (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
-
-
-/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
+ * to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg USART_CLEAR_EOBF: End Of Block Clear Flag
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
- * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
- *
+ * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+ * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-/** @brief Enable the USART associated to the SMARTCARD Handle
+/** @brief Enable the SMARTCARD one bit sample method.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/** @brief Macros to enable or disable the SmartCard DMA request.
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * The Handle Instance which can be USART1 or USART2.
- * @param __REQUEST__ specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
- * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART6CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+
+/** @brief Check the Baud rate range.
+ * @note The maximum Baud Rate is derived from the maximum clock on F7 (216 MHz)
+ * divided by the oversampling used on the SMARTCARD (i.e. 16).
+ * @param __BAUDRATE__ Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 13500001U)
+
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__ block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__ number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
+
+/** @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__ SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/** @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__ SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/** @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__ SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__ SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/** @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__ SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__ SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__ SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/** @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__ SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__ SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__ SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__ SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__ SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/** @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__ SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
/**
* @}
*/
-/* Include SMARTCARD HAL Extension module */
+/* Include SMARTCARD HAL Extended module */
#include "stm32f7xx_hal_smartcard_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
+/* Initialization and de-initialization functions ****************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group1
* @{
*/
-/* Initialization/de-initialization functions **********************************/
+
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @}
*/
+/* IO operation functions *****************************************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
-/* IO operation functions *******************************************************/
+
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
@@ -843,89 +1065,26 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
- * @}
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
* @{
*/
-#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
-#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
- ((__PARITY__) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
- ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
- ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
- ((__NACK__) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
- SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
- SMARTCARD_ADVFEATURE_SWAP_INIT | \
- SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
- SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
- ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
- ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
- ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
- ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
- ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
-
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @{
- */
-
/**
* @}
*/
@@ -942,6 +1101,6 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
}
#endif
-#endif /* __STM32F7xx_HAL_SMARTCARD_H */
+#endif /* STM32F7xx_HAL_SMARTCARD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard_ex.h
index 3a26cae9c6e7e9c8ff270a374818fc98e440503d..061b0f4e82458946fdda8ff42d7d5e713d1ffe3d 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smartcard_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @brief Header file of SMARTCARD HAL module.
+ * @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SMARTCARD_EX_H
-#define __STM32F7xx_HAL_SMARTCARD_EX_H
+#ifndef STM32F7xx_HAL_SMARTCARD_EX_H
+#define STM32F7xx_HAL_SMARTCARD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -73,24 +57,41 @@
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
+#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
-
-
-
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
+#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
/**
* @}
*/
@@ -105,10 +106,23 @@
* - ZZZZZ : Flag position in the ISR register(5 bits)
* @{
*/
+#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
+#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */
+#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
#endif /* USART_TCBGT_SUPPORT */
+
/**
* @}
*/
@@ -118,7 +132,7 @@
*/
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise error detected clear flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
@@ -131,96 +145,14 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reports the SMARTCARD clock source.
- * @param __HANDLE__ specifies the USART Handle
- * @param __CLOCKSOURCE__ output variable
- * @retval the USART clocking source, written in __CLOCKSOURCE__.
+/**
+ * @}
+ */
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+ * @{
*/
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
- switch(__HAL_RCC_GET_USART6_SOURCE()) \
- { \
- case RCC_USART6CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
- break; \
- case RCC_USART6CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART6CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART6CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- break; \
- } \
- } \
- } while(0)
/** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -240,13 +172,13 @@
{ \
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
} \
- } while(0)
+ } while(0U)
#else
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
do { \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
- } while(0)
-#endif
+ } while(0U)
+#endif /* USART_TCBGT_SUPPORT */
/** @brief Return the transmission completion flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -256,38 +188,76 @@
* @retval Transmission completion flag
*/
#if defined(USART_TCBGT_SUPPORT)
-#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
#else
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
-#endif
+#endif /* USART_TCBGT_SUPPORT */
-/**
- * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+
+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
* @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
*/
#if defined(USART_TCBGT_SUPPORT)
-#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
((__TXCOMPLETE__) == SMARTCARD_TC))
#else
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
-#endif
+#endif /* USART_TCBGT_SUPPORT */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
/* Initialization and de-initialization functions ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
+ * @{
+ */
+
/* IO operation functions *****************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
+ * @{
+ */
+
/* Peripheral Control functions ***********************************************/
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
-/* Peripheral State and Error functions ***************************************/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
/**
* @}
@@ -301,6 +271,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef
}
#endif
-#endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */
+#endif /* STM32F7xx_HAL_SMARTCARD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smbus.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smbus.h
index ff2ea4e4e432df66fc5e44074464ff7fbc0813d3..e0b67da98e5fbb8fc141bafcf1d5936cf374fdff 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smbus.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_smbus.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SMBUS_H
-#define __STM32F7xx_HAL_SMBUS_H
+#ifndef STM32F7xx_HAL_SMBUS_H
+#define STM32F7xx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
@@ -136,6 +120,10 @@ typedef struct
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
@@ -144,7 +132,7 @@ typedef struct
* @brief SMBUS handle Structure definition
* @{
*/
-typedef struct
+typedef struct __SMBUS_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@@ -166,7 +154,47 @@ typedef struct
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
+ HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
+ HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
+ HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
+
+ HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
+ HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
+
+} HAL_SMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMBUS Callback pointer definition
+ */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -234,7 +262,7 @@ typedef struct
* @}
*/
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
@@ -373,7 +401,15 @@ typedef struct
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#endif
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -419,7 +455,7 @@ typedef struct
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@@ -444,10 +480,10 @@ typedef struct
* @arg @ref SMBUS_FLAG_BUSY Bus busy
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
*
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -546,13 +582,13 @@ typedef struct
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
- IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
@@ -571,8 +607,8 @@ typedef struct
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
@@ -590,7 +626,7 @@ typedef struct
* @{
*/
-/* Initialization and de-initialization functions **********************************/
+/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
@@ -598,6 +634,14 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -694,6 +738,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
#endif
-#endif /* __STM32F7xx_HAL_SMBUS_H */
+#endif /* STM32F7xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spdifrx.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spdifrx.h
index 80f32b6f9231b06b07662f2ba85a90922ff17225..99420bfbaa0acc942c3e566a7db8d6de172b4d09 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spdifrx.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spdifrx.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SPDIFRX_H
-#define __STM32F7xx_HAL_SPDIFRX_H
+#ifndef STM32F7xx_HAL_SPDIFRX_H
+#define STM32F7xx_HAL_SPDIFRX_H
#ifdef __cplusplus
extern "C" {
@@ -44,11 +28,11 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
-#if defined (SPDIFRX)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+#if defined (SPDIFRX)
/** @addtogroup SPDIFRX
* @{
@@ -82,19 +66,18 @@ typedef struct
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
-
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
- uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_V_Mask */
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PE_Mask */
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
-}SPDIFRX_InitTypeDef;
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+} SPDIFRX_InitTypeDef;
/**
* @brief SPDIFRX SetDataFormat structure definition
@@ -119,7 +102,7 @@ typedef struct
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
-}SPDIFRX_SetDataFormatTypeDef;
+} SPDIFRX_SetDataFormatTypeDef;
/**
* @brief HAL State structures definition
@@ -132,12 +115,16 @@ typedef enum
HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
-}HAL_SPDIFRX_StateTypeDef;
+} HAL_SPDIFRX_StateTypeDef;
/**
* @brief SPDIFRX handle Structure definition
*/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+typedef struct __SPDIFRX_HandleTypeDef
+#else
typedef struct
+#endif
{
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
@@ -145,7 +132,7 @@ typedef struct
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
- uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
@@ -173,13 +160,44 @@ typedef struct
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
- __IO uint32_t ErrorCode; /* SPDIFRX Error code */
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */
-}SPDIFRX_HandleTypeDef;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
+ void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
+ void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
+ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
+ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
+ void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */
+ void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+} SPDIFRX_HandleTypeDef;
/**
* @}
*/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SPDIFRX Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, /*!< SPDIFRX Data flow half completed callback ID */
+ HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, /*!< SPDIFRX Data flow completed callback */
+ HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, /*!< SPDIFRX Control flow half completed callback */
+ HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U, /*!< SPDIFRX Control flow completed callback */
+ HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */
+ HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */
+ HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */
+}HAL_SPDIFRX_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPDIFRX Callback pointer definition
+ */
+typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
@@ -193,6 +211,9 @@ typedef struct
#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */
#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -200,10 +221,10 @@ typedef struct
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
* @{
*/
-#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
-#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
-#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
-#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
+#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
+#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
+#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
+#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
/**
* @}
*/
@@ -211,10 +232,10 @@ typedef struct
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
* @{
*/
-#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
-#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
-#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
-#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
+#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
+#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
+#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
+#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
/**
* @}
*/
@@ -222,26 +243,26 @@ typedef struct
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
* @{
*/
-#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
+#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
/**
* @}
*/
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
-* @{
-*/
-#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
+ * @{
+ */
+#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
-* @{
-*/
-#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
-#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+ * @{
+ */
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/
@@ -249,17 +270,17 @@ typedef struct
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
* @{
*/
-#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
+#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
-* @{
-*/
-#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
-#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
+ * @{
+ */
+#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
/**
* @}
*/
@@ -267,8 +288,8 @@ typedef struct
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
* @{
*/
-#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
-#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
+#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
/**
* @}
*/
@@ -276,9 +297,9 @@ typedef struct
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
* @{
*/
-#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
-#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
-#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
+#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
+#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
+#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
/**
* @}
*/
@@ -286,8 +307,8 @@ typedef struct
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
* @{
*/
-#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
-#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
+#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
/**
* @}
*/
@@ -306,13 +327,13 @@ typedef struct
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
* @{
*/
-#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
-#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
-#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
-#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
-#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
-#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
-#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
/**
* @}
*/
@@ -320,15 +341,15 @@ typedef struct
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
* @{
*/
-#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
-#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
-#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
-#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
-#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
-#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
-#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
-#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
-#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
/**
* @}
*/
@@ -346,7 +367,15 @@ typedef struct
* @param __HANDLE__ SPDIFRX handle.
* @retval None
*/
-#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
* @param __HANDLE__ specifies the SPDIFRX Handle.
@@ -369,7 +398,7 @@ typedef struct
/** @brief Enable or disable the specified SPDIFRX interrupts.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
@@ -385,7 +414,7 @@ typedef struct
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
* @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
@@ -400,8 +429,8 @@ typedef struct
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPDIFRX flag is set or not.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_RXNE
* @arg SPDIFRX_FLAG_CSRNE
@@ -414,11 +443,11 @@ typedef struct
* @arg SPDIFRX_FLAG_TERR
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_PERR
@@ -447,6 +476,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -459,7 +494,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
@@ -467,7 +502,6 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
@@ -484,8 +518,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
* @{
*/
/* Peripheral Control and State functions ************************************/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
/**
* @}
*/
@@ -500,32 +534,41 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
* @{
*/
-#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
- ((INPUT) == SPDIFRX_INPUT_IN2) || \
- ((INPUT) == SPDIFRX_INPUT_IN3) || \
- ((INPUT) == SPDIFRX_INPUT_IN0))
-#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
- ((RET) == SPDIFRX_MAXRETRIES_3) || \
- ((RET) == SPDIFRX_MAXRETRIES_15) || \
- ((RET) == SPDIFRX_MAXRETRIES_63))
-#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
- ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
-#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
- ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
+
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
+
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
- ((VAL) == SPDIFRX_VALIDITYMASK_ON))
-#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
- ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
-#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
- ((CHANNEL) == SPDIFRX_CHANNEL_B))
-#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
-#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
- ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
-
-#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
- ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
+
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+
/**
* @}
*/
@@ -541,12 +584,11 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
-
+#endif /* SPDIFRX */
/**
* @}
*/
-#endif /* SPDIFRX */
#ifdef __cplusplus
}
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi.h
index 86387d4d2b040d4f2479cf558d22a117326e943e..4d5be75d8835aff367fe4cec6aaf8c10829f772b 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_SPI_H
-#define __STM32F7xx_HAL_SPI_H
+#ifndef STM32F7xx_HAL_SPI_H
+#define STM32F7xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
@@ -62,48 +46,48 @@ extern "C" {
*/
typedef struct
{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
- uint32_t DataSize; /*!< Specifies the SPI data size.
+ uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
This parameter can be a value of @ref SPI_CRC_length */
- uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
@@ -116,14 +100,14 @@ typedef struct
*/
typedef enum
{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
} HAL_SPI_StateTypeDef;
/**
@@ -131,46 +115,83 @@ typedef enum
*/
typedef struct __SPI_HandleTypeDef
{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
- uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
- __IO uint32_t ErrorCode; /*!< SPI Error code */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
@@ -178,14 +199,17 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
-#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) /*!< Error during SPI Abort procedure */
+#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -193,7 +217,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Mode SPI Mode
* @{
*/
-#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
+#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
@@ -202,7 +226,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
-#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
+#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
@@ -212,19 +236,19 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U)
-#define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U)
-#define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U)
-#define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U)
-#define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U)
-#define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U)
-#define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U)
-#define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U)
-#define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U)
-#define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U)
-#define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U)
-#define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U)
-#define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U)
+#define SPI_DATASIZE_4BIT (0x00000300U)
+#define SPI_DATASIZE_5BIT (0x00000400U)
+#define SPI_DATASIZE_6BIT (0x00000500U)
+#define SPI_DATASIZE_7BIT (0x00000600U)
+#define SPI_DATASIZE_8BIT (0x00000700U)
+#define SPI_DATASIZE_9BIT (0x00000800U)
+#define SPI_DATASIZE_10BIT (0x00000900U)
+#define SPI_DATASIZE_11BIT (0x00000A00U)
+#define SPI_DATASIZE_12BIT (0x00000B00U)
+#define SPI_DATASIZE_13BIT (0x00000C00U)
+#define SPI_DATASIZE_14BIT (0x00000D00U)
+#define SPI_DATASIZE_15BIT (0x00000E00U)
+#define SPI_DATASIZE_16BIT (0x00000F00U)
/**
* @}
*/
@@ -232,7 +256,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
-#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
+#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
@@ -241,7 +265,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
-#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
+#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
@@ -251,8 +275,8 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
-#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
+#define SPI_NSS_HARD_INPUT (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
@@ -261,7 +285,7 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U)
+#define SPI_NSS_PULSE_DISABLE (0x00000000U)
/**
* @}
*/
@@ -269,14 +293,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
-#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
-#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
-#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
-#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
-#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
-#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
-#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
@@ -284,7 +308,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
-#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
+#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
@@ -293,7 +317,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
+#define SPI_TIMODE_DISABLE (0x00000000U)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
@@ -302,7 +326,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
+#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
@@ -315,9 +339,9 @@ typedef struct __SPI_HandleTypeDef
* SPI_CRC_LENGTH_8BIT : CRC 8bit
* SPI_CRC_LENGTH_16BIT : CRC 16bit
*/
-#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U)
-#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U)
-#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U)
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT (0x00000002U)
/**
* @}
*/
@@ -327,13 +351,12 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be one of the following values:
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
* RXNE event is generated if the FIFO
- * level is greater or equal to 1/2(16-bits).
+ * level is greater or equal to 1/4(8-bits).
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4(8 bits). */
+ * level is greater or equal to 1/2(16 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U)
-
+#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
/**
* @}
*/
@@ -360,6 +383,7 @@ typedef struct __SPI_HandleTypeDef
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
/**
* @}
*/
@@ -367,10 +391,10 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
*/
-#define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U)
-#define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U)
-#define SPI_FTLVL_FULL ((uint32_t)0x00001800U)
+#define SPI_FTLVL_EMPTY (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
+#define SPI_FTLVL_HALF_FULL (0x00001000U)
+#define SPI_FTLVL_FULL (0x00001800U)
/**
* @}
@@ -379,10 +403,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
-#define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U)
-#define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U)
-#define SPI_FRLVL_FULL ((uint32_t)0x00000600U)
+#define SPI_FRLVL_EMPTY (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
+#define SPI_FRLVL_HALF_FULL (0x00000400U)
+#define SPI_FRLVL_FULL (0x00000600U)
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -397,20 +425,39 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif
-/** @brief Enable or disable the specified SPI interrupts.
+/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI handle.
+ * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SPI Handle.
@@ -454,13 +501,13 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
@@ -473,7 +520,7 @@ typedef struct __SPI_HandleTypeDef
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
- } while(0)
+ } while(0U)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__ specifies the SPI Handle.
@@ -485,21 +532,21 @@ typedef struct __SPI_HandleTypeDef
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
- }while(0)
+ }while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/**
* @}
@@ -515,96 +562,206 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of SPI SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of SPI CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
+/** @brief Checks if SPI Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Mode.
+ * This parameter can be a value of @ref SPI_Mode
+ * @retval None
+ */
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+ ((__MODE__) == SPI_MODE_MASTER))
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+/** @brief Checks if SPI Direction Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * This parameter can be a value of @ref SPI_Direction
+ * @retval None
+ */
+#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
+/** @brief Checks if SPI Direction Mode parameter is 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_15BIT) || \
- ((DATASIZE) == SPI_DATASIZE_14BIT) || \
- ((DATASIZE) == SPI_DATASIZE_13BIT) || \
- ((DATASIZE) == SPI_DATASIZE_12BIT) || \
- ((DATASIZE) == SPI_DATASIZE_11BIT) || \
- ((DATASIZE) == SPI_DATASIZE_10BIT) || \
- ((DATASIZE) == SPI_DATASIZE_9BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT) || \
- ((DATASIZE) == SPI_DATASIZE_7BIT) || \
- ((DATASIZE) == SPI_DATASIZE_6BIT) || \
- ((DATASIZE) == SPI_DATASIZE_5BIT) || \
- ((DATASIZE) == SPI_DATASIZE_4BIT))
+/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
+/** @brief Checks if SPI Data Size parameter is in allowed range.
+ * @param __DATASIZE__ specifies the SPI Data Size.
+ * This parameter can be a value of @ref SPI_Data_Size
+ * @retval None
+ */
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_4BIT))
+
+/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the SPI serial clock steady state.
+ * This parameter can be a value of @ref SPI_Clock_Polarity
+ * @retval None
+ */
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
+/** @brief Checks if SPI Clock Phase parameter is in allowed range.
+ * @param __CPHA__ specifies the SPI Clock Phase.
+ * This parameter can be a value of @ref SPI_Clock_Phase
+ * @retval None
+ */
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
+/** @brief Checks if SPI Slave Select parameter is in allowed range.
+ * @param __NSS__ specifies the SPI Slave Select management parameter.
+ * This parameter can be a value of @ref SPI_Slave_Select_management
+ * @retval None
+ */
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
- ((NSSP) == SPI_NSS_PULSE_DISABLE))
+/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
+ * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
+ * This parameter can be a value of @ref SPI_NSSP_Mode
+ * @retval None
+ */
+#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
+ ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
+ * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
+ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ * @retval None
+ */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
+
+/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
+ * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
+ * This parameter can be a value of @ref SPI_MSB_LSB_transmission
+ * @retval None
+ */
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
+/** @brief Checks if SPI TI mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI TI mode.
+ * This parameter can be a value of @ref SPI_TI_mode
+ * @retval None
+ */
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+ ((__MODE__) == SPI_TIMODE_ENABLE))
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
- ((MODE) == SPI_TIMODE_ENABLE))
+/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
+ * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
+ * This parameter can be a value of @ref SPI_CRC_Calculation
+ * @retval None
+ */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+/** @brief Checks if SPI CRC length is in allowed range.
+ * @param __LENGTH__ specifies the SPI CRC length.
+ * This parameter can be a value of @ref SPI_CRC_length
+ * @retval None
+ */
+#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
+ ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
+ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
- ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
- ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
+ * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
+ * @retval None
+ */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))
+/** @brief Checks if DMA handle is valid.
+ * @param __HANDLE__ specifies a DMA Handle.
+ * @retval None
+ */
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
/**
* @}
*/
+/* Include SPI HAL Extended module */
+#include "stm32f7xx_hal_spi_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
-/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
@@ -612,26 +769,32 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
+/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
@@ -652,10 +815,9 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
* @}
*/
-/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
-
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
@@ -679,9 +841,6 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
}
#endif
-#endif /* __STM32F7xx_HAL_SPI_H */
+#endif /* STM32F7xx_HAL_SPI_H */
-/**
- * @}
- */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi_ex.h
new file mode 100644
index 0000000000000000000000000000000000000000..63a0153a714de1821e3130bed699ee0ff1d391fb
--- /dev/null
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_spi_ex.h
@@ -0,0 +1,75 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F7xx_HAL_SPI_EX_H
+#define STM32F7xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F7xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sram.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sram.h
index 5f19616ebcb3346bd2f714d1e83496773c2e21cf..6f7dda7f293fec35e52d2cb08e4b7be375d90c0f 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sram.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_sram.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -67,12 +51,16 @@ typedef enum
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
-}HAL_SRAM_StateTypeDef;
+} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -86,8 +74,32 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-}SRAM_HandleTypeDef;
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
+#endif
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SRAM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
+ HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
+ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
+ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
+}HAL_SRAM_CallbackIDTypeDef;
+/**
+ * @brief HAL SRAM Callback pointer definition
+ */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
@@ -103,7 +115,15 @@ typedef struct
* @param __HANDLE__ SRAM handle
* @retval None
*/
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif
/**
* @}
@@ -145,6 +165,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim.h
index 7c078aeffd9647bb2711dd46c7a33bbf67a31a3f..d5cde2b1c4e55b1c07ff493031d5840ea983d3aa 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_TIM_H
-#define __STM32F7xx_HAL_TIM_H
+#ifndef STM32F7xx_HAL_TIM_H
+#define STM32F7xx_HAL_TIM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -75,28 +59,26 @@ typedef struct
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
-
} TIM_Base_InitTypeDef;
/**
* @brief TIM Output Compare Configuration Structure definition
*/
-
typedef struct
{
uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
@@ -106,20 +88,20 @@ typedef struct
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;
/**
@@ -128,7 +110,7 @@ typedef struct
typedef struct
{
uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
@@ -138,15 +120,15 @@ typedef struct
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -158,15 +140,13 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;
-
/**
* @brief TIM Input Capture Configuration Structure definition
*/
-
typedef struct
{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -181,7 +161,6 @@ typedef struct
/**
* @brief TIM Encoder Configuration Structure definition
*/
-
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
@@ -217,49 +196,96 @@ typedef struct
*/
typedef struct
{
- uint32_t ClockSource; /*!< TIM clock sources.
+ uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity.
+ uint32_t ClockPolarity; /*!< TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler.
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
/**
- * @brief Clear Input Configuration Handle Structure definition
+ * @brief TIM Clear Input Configuration Handle Structure definition
*/
typedef struct
{
- uint32_t ClearInputState; /*!< TIM clear Input state.
+ uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources.
- This parameter can be a value of @ref TIMEx_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct
+{
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+} TIM_MasterConfigTypeDef;
/**
* @brief TIM Slave configuration Structure definition
*/
-typedef struct {
+typedef struct
+{
uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIMEx_Slave_Mode */
+ This parameter can be a value of @ref TIM_Slave_Mode */
uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
+ This parameter can be a value of @ref TIM_Trigger_Selection */
uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+} TIM_SlaveConfigTypeDef;
-}TIM_SlaveConfigTypeDef;
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the break input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Break2State; /*!< TIM Break2 State
+ This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity
+ This parameter can be a value of @ref TIM_Break2_Polarity */
+ uint32_t Break2Filter; /*!< TIM break2 input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
/**
* @brief HAL State structures definition
@@ -271,7 +297,7 @@ typedef enum
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
+} HAL_TIM_StateTypeDef;
/**
* @brief HAL Active channel structures definition
@@ -282,50 +308,59 @@ typedef enum
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
+} HAL_TIM_ActiveChannel;
/**
* @brief TIM Time Base Handle Structure definition
*/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
+ This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- void (* Base_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
- void (* Base_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
- void (* IC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
- void (* IC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
- void (* OC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
- void (* OC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
- void (* PWM_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
- void (* PWM_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
- void (* OnePulse_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
- void (* OnePulse_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
- void (* Encoder_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
- void (* Encoder_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
- void (* HallSensor_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
- void (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
-
- void (* PeriodElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
- void (* TriggerCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
- void (* IC_CaptureCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
- void (* OC_DelayElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
- void (* PWM_PulseFinishedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
- void (* ErrorCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
- void (* CommutationCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
- void (* BreakCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
-
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-}TIM_HandleTypeDef;
+} TIM_HandleTypeDef;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
@@ -333,85 +368,152 @@ typedef struct __TIM_HandleTypeDef
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */
- HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */
- HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */
- HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */
- HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */
- HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */
- HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */
- HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */
- HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */
- HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */
- HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */
- HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */
- HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Encoder MspDeInit Callback ID */
- HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Encoder MspDeInit Callback ID */
-
- HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */
- HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */
- HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */
- HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */
- HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */
- HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */
- HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */
- HAL_TIM_BREAK_CB_ID = 0x15U /*!< TIM Break Callback ID */
-
-}HAL_TIM_CallbackIDTypeDef;
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
/**
* @brief HAL TIM Callback pointer definition
*/
-typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
+#define TIM_DMABASE_DMAR 0x00000013U
+#define TIM_DMABASE_OR 0x00000014U
+#define TIM_DMABASE_CCMR3 0x00000015U
+#define TIM_DMABASE_CCR5 0x00000016U
+#define TIM_DMABASE_CCR6 0x00000017U
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1 0x00000018U
+#define TIM_DMABASE_AF2 0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
* @}
*/
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
/**
* @}
*/
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
/**
* @}
*/
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
/**
* @}
*/
@@ -419,9 +521,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
/**
* @}
*/
@@ -429,9 +531,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
/**
* @}
*/
@@ -439,18 +540,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
-#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
/**
* @}
*/
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
/**
* @}
*/
@@ -458,8 +559,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
/**
* @}
*/
@@ -467,8 +568,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
/**
* @}
*/
@@ -476,60 +577,59 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
/**
* @}
*/
@@ -537,8 +637,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -546,25 +646,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
/**
* @}
*/
-/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
* @{
*/
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
/**
* @}
*/
@@ -572,107 +671,108 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
/**
* @}
*/
-/** @defgroup TIM_DMA_sources TIM DMA sources
+/** @defgroup TIM_DMA_sources TIM DMA Sources
* @{
*/
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
/**
* @}
*/
-/** @defgroup TIM_Event_Source TIM Event Source
+/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
-#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
/**
* @}
*/
-/** @defgroup TIM_Flag_definition TIM Flag definition
+/** @defgroup TIM_Channel TIM Channel
* @{
*/
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
+#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
/**
* @}
*/
-/** @defgroup TIM_Clock_Source TIM Clock Source
+/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
* @}
*/
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
@@ -680,10 +780,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/
@@ -691,8 +791,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
@@ -700,45 +800,75 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
-
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+ * @{
+ */
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
/**
* @}
*/
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
-/** @defgroup TIM_Break_Polarity TIM Break Polarity
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
* @{
*/
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
/**
* @}
*/
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
* @{
*/
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
+#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
+#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+ (if none of the break inputs BRK and BRK2 is active) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
@@ -746,39 +876,96 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET ((uint32_t)0x0000U)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
/**
* @}
*/
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
* @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
+#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
/**
* @}
*/
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
* @{
*/
-#define TIM_TS_ITR0 ((uint32_t)0x0000U)
-#define TIM_TS_ITR1 ((uint32_t)0x0010U)
-#define TIM_TS_ITR2 ((uint32_t)0x0020U)
-#define TIM_TS_ITR3 ((uint32_t)0x0030U)
-#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
-#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
-#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
-#define TIM_TS_ETRF ((uint32_t)0x0070U)
-#define TIM_TS_NONE ((uint32_t)0xFFFFU)
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
+#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
+#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
+#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
/**
* @}
*/
@@ -786,8 +973,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
@@ -798,97 +985,80 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
* @}
*/
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Selection
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
* @}
*/
-/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABASE_CR1 (0x00000000U)
-#define TIM_DMABASE_CR2 (0x00000001U)
-#define TIM_DMABASE_SMCR (0x00000002U)
-#define TIM_DMABASE_DIER (0x00000003U)
-#define TIM_DMABASE_SR (0x00000004U)
-#define TIM_DMABASE_EGR (0x00000005U)
-#define TIM_DMABASE_CCMR1 (0x00000006U)
-#define TIM_DMABASE_CCMR2 (0x00000007U)
-#define TIM_DMABASE_CCER (0x00000008U)
-#define TIM_DMABASE_CNT (0x00000009U)
-#define TIM_DMABASE_PSC (0x0000000AU)
-#define TIM_DMABASE_ARR (0x0000000BU)
-#define TIM_DMABASE_RCR (0x0000000CU)
-#define TIM_DMABASE_CCR1 (0x0000000DU)
-#define TIM_DMABASE_CCR2 (0x0000000EU)
-#define TIM_DMABASE_CCR3 (0x0000000FU)
-#define TIM_DMABASE_CCR4 (0x00000010U)
-#define TIM_DMABASE_BDTR (0x00000011U)
-#define TIM_DMABASE_DCR (0x00000012U)
-#define TIM_DMABASE_OR (0x00000013U)
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
-/** @defgroup DMA_Handle_index DMA Handle index
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
/**
* @}
*/
-/** @defgroup Channel_CC_State Channel CC State
+/** @defgroup TIM_Break_System TIM Break System
* @{
*/
-#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
-#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
-#define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
-#define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
+#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
/**
* @}
*/
@@ -896,31 +1066,46 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/**
* @}
*/
+/* End of exported constants -------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
*/
-/** @brief Reset TIM handle state
- * @param __HANDLE__ TIM handle
+
+/** @brief Reset TIM handle state.
+ * @param __HANDLE__ TIM handle.
* @retval None
*/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
- */
+ */
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-/**
- * @brief Enable the TIM update source request.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
-
/**
* @brief Enable the TIM main Output.
* @param __HANDLE__ TIM handle
@@ -935,22 +1120,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
-/**
- * @brief Disable the TIM update source request.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
@@ -959,18 +1137,26 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
- } \
+ } \
} while(0)
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -985,8 +1171,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -1001,8 +1187,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
/** @brief Enable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to enable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
@@ -1016,8 +1202,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
/** @brief Disable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to disable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
@@ -1031,18 +1217,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1052,18 +1241,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1074,8 +1266,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
/**
* @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -1090,8 +1282,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -1103,21 +1295,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
*/
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
/**
* @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __PRESC__: specifies the Prescaler new value.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
@@ -1128,66 +1320,68 @@ mode.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
* @brief Get the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
/**
- * @brief Set the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval 16-bit or 32-bit value of the timer auto-reload
+ * @retval None
*/
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
+
/**
- * @brief Get the TIM Autoreload Register value on runtime
+ * @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
- * @retval None
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
/**
- * @brief Set the TIM Clock Division value on runtime without calling
- * another time any Init function.
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1
- * @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
+
/**
- * @brief Get the TIM Clock Division value on runtime
+ * @brief Get the TIM Clock Division value on runtime.
* @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
* @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1208,9 +1402,9 @@ mode.
} while(0)
/**
- * @brief Get the TIM Input Capture prescaler on runtime
+ * @brief Get the TIM Input Capture prescaler on runtime.
* @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
@@ -1224,9 +1418,119 @@ mode.
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@@ -1241,32 +1545,377 @@ mode.
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
* @retval None
*/
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
-
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
-/* Include TIM HAL Extension module */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_OR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || \
+ ((__BASE__) == TIM_DMABASE_AF1) || \
+ ((__BASE__) == TIM_DMABASE_AF2))
+#else
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_OR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6))
+#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
+ ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \
+ ((__CHANNEL__) == TIM_CHANNEL_6) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
+ ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
+ ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
+ ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
+ ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
+ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
#include "stm32f7xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @addtogroup TIM_Exported_Functions_Group1
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
* @{
*/
-
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
@@ -1285,10 +1934,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group2
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
* @{
*/
-/* Timer Output Compare functions **********************************************/
+/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
@@ -1302,20 +1952,19 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group3
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
* @{
*/
-/* Timer PWM functions *********************************************************/
+/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -1325,15 +1974,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group4
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
* @{
*/
-/* Timer Input Capture functions ***********************************************/
+/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
@@ -1347,15 +1996,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group5
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
* @{
*/
-/* Timer One Pulse functions ***************************************************/
+/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
@@ -1363,24 +2012,23 @@ void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group6
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
* @{
*/
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
@@ -1389,56 +2037,60 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group7
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
* @{
*/
-/* Interrupt Handler functions **********************************************/
+/* Interrupt Handler functions ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group8
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
* @{
*/
/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group9
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
* @{
*/
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/
@@ -1451,309 +2103,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group10
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
* @{
*/
-/* Peripheral State functions **************************************************/
+/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
- * @{
- */
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
- ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTSTATE_ENABLE))
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
- ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))
-
-
-#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
- ((__IT__) == TIM_IT_CC1) || \
- ((__IT__) == TIM_IT_CC2) || \
- ((__IT__) == TIM_IT_CC3) || \
- ((__IT__) == TIM_IT_CC4) || \
- ((__IT__) == TIM_IT_COM) || \
- ((__IT__) == TIM_IT_TRIGGER) || \
- ((__IT__) == TIM_IT_BREAK))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
- ((__FLAG__) == TIM_FLAG_CC1) || \
- ((__FLAG__) == TIM_FLAG_CC2) || \
- ((__FLAG__) == TIM_FLAG_CC3) || \
- ((__FLAG__) == TIM_FLAG_CC4) || \
- ((__FLAG__) == TIM_FLAG_COM) || \
- ((__FLAG__) == TIM_FLAG_TRIGGER) || \
- ((__FLAG__) == TIM_FLAG_BREAK) || \
- ((__FLAG__) == TIM_FLAG_BREAK2) || \
- ((__FLAG__) == TIM_FLAG_CC1OF) || \
- ((__FLAG__) == TIM_FLAG_CC2OF) || \
- ((__FLAG__) == TIM_FLAG_CC3OF) || \
- ((__FLAG__) == TIM_FLAG_CC4OF))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
- ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
- ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
- ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
- ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_DCR) || \
- ((__BASE__) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_ICPRESCALER TIM Private macros to SET/RESET TIM Input capture value
- * @{
- */
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-/**
- * @}
- */
-
-/** @defgroup TIM_CAPTUREPOLARITY TIM Private macros to SET/RESET TIM capture polarity value
- * @{
- */
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
/**
* @}
*/
@@ -1761,32 +2121,32 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/* End of private macros -----------------------------------------------------*/
+/* End of exported functions -------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
+* @{
+*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
- * @}
- */
+* @}
+*/
/* End of private functions --------------------------------------------------*/
/**
@@ -1801,6 +2161,6 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
}
#endif
-#endif /* __STM32F7xx_HAL_TIM_H */
+#endif /* STM32F7xx_HAL_TIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim_ex.h
index 404c24962feb4399fcc84af95d1bbd7e3bd6b2ae..f0434c255e038eee1ada5cd8a97d5f5ad146adfe 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_tim_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.h
* @author MCD Application Team
- * @brief Header file of TIM HAL Extension module.
+ * @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_TIM_EX_H
-#define __STM32F7xx_HAL_TIM_EX_H
+#ifndef STM32F7xx_HAL_TIM_EX_H
+#define STM32F7xx_HAL_TIM_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -53,7 +37,7 @@
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Exported Types
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
@@ -63,67 +47,25 @@
typedef struct
{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
- This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
+ * @brief TIM Break/Break2 input configuration
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level.
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Break2State; /*!< TIM Break2 State
- This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity
- This parameter can be a value of @ref TIMEx_Break2_Polarity */
- uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/**
- * @brief TIM Break/Break2 input configuration
- */
-typedef struct {
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
@@ -131,55 +73,21 @@ typedef struct {
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-} TIMEx_BreakInputConfigTypeDef;
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Channel TIMEx Channel
- * @{
- */
-
-#define TIM_CHANNEL_1 ((uint32_t)0x0000U)
-#define TIM_CHANNEL_2 ((uint32_t)0x0004U)
-#define TIM_CHANNEL_3 ((uint32_t)0x0008U)
-#define TIM_CHANNEL_4 ((uint32_t)0x000CU)
-#define TIM_CHANNEL_5 ((uint32_t)0x0010U)
-#define TIM_CHANNEL_6 ((uint32_t)0x0014U)
-#define TIM_CHANNEL_ALL ((uint32_t)0x003CU)
+}
+TIMEx_BreakInputConfigTypeDef;
+#endif /* TIM_BREAK_INPUT_SUPPORT */
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
-/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
-#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
-#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
-
-#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
-#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
-/**
- * @}
- */
-/** @defgroup TIMEx_Remap TIMEx Remap
+/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM2_TIM8_TRGO (0x00000000U)
@@ -194,455 +102,240 @@ typedef struct {
#define TIM_TIM11_SPDIFRX (0x00000001U)
#define TIM_TIM11_HSE (0x00000002U)
#define TIM_TIM11_MCO1 (0x00000003U)
-/**
- * @}
- */
-
-/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
-#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
/**
* @}
*/
+#if defined(TIM_BREAK_INPUT_SUPPORT)
-/** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
-#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)
-#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
+#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
/**
* @}
*/
-/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
-#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)
-#define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)
+#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
/**
* @}
*/
-/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3
- * @{
- */
-#define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
-#define TIM_TRGO2_RESET ((uint32_t)0x00000000U)
-#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
-#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
-#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
-#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
-#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
/**
* @}
*/
-/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
-#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
-#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
-#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
-#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
-/**
- * @}
- */
-#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/** @defgroup TIMEx_Break_Input TIM Extended Break input
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
-#define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */
-#define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
/**
* @}
*/
+#endif /* TIM_BREAK_INPUT_SUPPORT */
-/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
/**
* @}
*/
+/* End of exported constants -------------------------------------------------*/
-/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
-#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */
-/**
- * @}
- */
-/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
- * @{
- */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
/**
* @}
*/
+/* End of exported macro -----------------------------------------------------*/
-/**
- * @}
- */
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
+#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
+ ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\
+ ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
+ ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
+ ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\
+ ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\
+ ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\
+ ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\
+ ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\
+ ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\
+ ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\
+ ((__TIM_REMAP__) == TIM_TIM11_MCO1))
+#if defined(TIM_BREAK_INPUT_SUPPORT)
-/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval None
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
- ((__HANDLE__)->Instance->CCR6))
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
-/**
- * @brief Sets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-/**
- * @brief Resets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+#endif /* TIM_BREAK_INPUT_SUPPORT */
/**
* @}
*/
+/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
-/** @addtogroup TIMEx_Exported_Functions_Group1
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
-/* Extension Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group6
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
* @{
*/
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group7
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
* @{
*/
-/* Extension Peripheral State functions **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
-/**
- * @}
- */
-
+/* Extended Peripheral State functions ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIMEx Private Macros
- * @{
- */
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_5) || \
- ((CHANNEL) == TIM_CHANNEL_6) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2) || \
- ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
- ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
- ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
- ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
- ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
- ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
- ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
- ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
- ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
- ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
- ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
- ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
- ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
- ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
- ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
- ((__TIM_REMAP__) == TIM_TIM11_MCO1))
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
-#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
-#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
-#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
- ((STATE) == TIM_BREAK2_DISABLE))
-#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
-#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
-#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
- ((SOURCE) == TIM_TRGO2_ENABLE) || \
- ((SOURCE) == TIM_TRGO2_UPDATE) || \
- ((SOURCE) == TIM_TRGO2_OC1) || \
- ((SOURCE) == TIM_TRGO2_OC1REF) || \
- ((SOURCE) == TIM_TRGO2_OC2REF) || \
- ((SOURCE) == TIM_TRGO2_OC3REF) || \
- ((SOURCE) == TIM_TRGO2_OC3REF) || \
- ((SOURCE) == TIM_TRGO2_OC4REF) || \
- ((SOURCE) == TIM_TRGO2_OC5REF) || \
- ((SOURCE) == TIM_TRGO2_OC6REF) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
- ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
- ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
- ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
- ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
- ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
- ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
-
-#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
- ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
-
-#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
- ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
-#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
-
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
-
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
+/* End of private functions --------------------------------------------------*/
/**
* @}
@@ -656,6 +349,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
}
#endif
-#endif /* __STM32F7xx_HAL_TIM_EX_H */
+
+#endif /* STM32F7xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart.h
index 24cec7dbb00847dd87dcec404e71d21f6f326e53..689092d36c85aa633fa4fac02ab84694a3f6bf93 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_UART_H
-#define __STM32F7xx_HAL_UART_H
+#ifndef STM32F7xx_HAL_UART_H
+#define STM32F7xx_HAL_UART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -65,17 +49,18 @@ typedef struct
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate register is computed using the following formula:
- If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+ Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate)))
- If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
+ Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck is the UART input clock */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length */
+ This parameter can be a value of @ref UARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits */
+ This parameter can be a value of @ref UART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@@ -85,19 +70,21 @@ typedef struct
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode */
+ This parameter can be a value of @ref UART_Mode. */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control */
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling */
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling */
-}UART_InitTypeDef;
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+
+} UART_InitTypeDef;
/**
* @brief UART Advanced Features initialization structure definition
@@ -106,43 +93,43 @@ typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
- This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref UART_Tx_Inv */
+ This parameter can be a value of @ref UART_Tx_Inv. */
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref UART_Rx_Inv */
+ This parameter can be a value of @ref UART_Rx_Inv. */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
- This parameter can be a value of @ref UART_Data_Inv */
+ This parameter can be a value of @ref UART_Data_Inv. */
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref UART_Rx_Tx_Swap */
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref UART_Overrun_Disable */
+ This parameter can be a value of @ref UART_Overrun_Disable. */
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
- This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
detection is carried out.
- This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref UART_MSB_First */
+ This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
+ * @brief HAL UART State definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -151,14 +138,14 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -168,9 +155,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -179,26 +166,7 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
+typedef uint32_t HAL_UART_StateTypeDef;
/**
* @brief UART clock sources definition
@@ -211,49 +179,97 @@ typedef enum
UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
+} UART_ClockSourceTypeDef;
/**
* @brief UART handle Structure definition
*/
-typedef struct
+typedef struct __UART_HandleTypeDef
{
- USART_TypeDef *Instance; /*!< UART registers base address */
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
- UART_InitTypeDef Init; /*!< UART communication parameters */
- UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
- uint16_t Mask; /*!< UART Rx RDR register mask */
+ __IO uint32_t ErrorCode; /*!< UART Error code */
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- HAL_LockTypeDef Lock; /*!< Locking object */
+} UART_HandleTypeDef;
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
- __IO uint32_t ErrorCode; /*!< UART Error code */
+} HAL_UART_CallbackIDTypeDef;
-}UART_HandleTypeDef;
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@@ -263,23 +279,54 @@ typedef struct
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
+
+/** @defgroup UART_State_Definition UART State Code Definition
+ * @{
+ */
+#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
-#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
+
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
-#define UART_STOPBITS_1 ((uint32_t)0x00000000U)
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
/**
* @}
*/
@@ -287,9 +334,9 @@ typedef struct
/** @defgroup UART_Parity UART Parity
* @{
*/
-#define UART_PARITY_NONE ((uint32_t)0x00000000U)
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
@@ -297,10 +344,10 @@ typedef struct
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
-#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U)
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
/**
* @}
*/
@@ -308,18 +355,18 @@ typedef struct
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
- /** @defgroup UART_State UART State
+/** @defgroup UART_State UART State
* @{
*/
-#define UART_STATE_DISABLE ((uint32_t)0x00000000U)
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
/**
* @}
*/
@@ -327,8 +374,8 @@ typedef struct
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
-#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U)
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
@@ -336,8 +383,8 @@ typedef struct
/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
* @{
*/
-#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
-#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
+#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */
/**
* @}
*/
@@ -345,10 +392,10 @@ typedef struct
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
/**
* @}
*/
@@ -356,8 +403,8 @@ typedef struct
/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
* @{
*/
-#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
-#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */
/**
* @}
*/
@@ -365,8 +412,8 @@ typedef struct
/** @defgroup UART_LIN UART Local Interconnection Network mode
* @{
*/
-#define UART_LIN_DISABLE ((uint32_t)0x00000000U)
-#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
+#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */
/**
* @}
*/
@@ -374,8 +421,8 @@ typedef struct
/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
* @{
*/
-#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U)
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */
/**
* @}
*/
@@ -383,8 +430,8 @@ typedef struct
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
-#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U)
-#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
/**
* @}
*/
@@ -392,8 +439,8 @@ typedef struct
/** @defgroup UART_DMA_Rx UART DMA Rx
* @{
*/
-#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U)
-#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
/**
* @}
*/
@@ -401,8 +448,8 @@ typedef struct
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
*/
-#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U)
-#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */
/**
* @}
*/
@@ -410,8 +457,8 @@ typedef struct
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
* @{
*/
-#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U)
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */
/**
* @}
*/
@@ -419,11 +466,11 @@ typedef struct
/** @defgroup UART_Request_Parameters UART Request Parameters
* @{
*/
-#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
@@ -431,15 +478,15 @@ typedef struct
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
* @{
*/
-#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
-#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
-#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
-#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U)
-#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
+#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -447,8 +494,8 @@ typedef struct
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -456,8 +503,8 @@ typedef struct
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
@@ -465,8 +512,8 @@ typedef struct
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
* @{
*/
-#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
@@ -474,8 +521,8 @@ typedef struct
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
* @{
*/
-#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
@@ -483,8 +530,8 @@ typedef struct
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
* @{
*/
-#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
@@ -492,8 +539,8 @@ typedef struct
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
/**
* @}
*/
@@ -501,8 +548,8 @@ typedef struct
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
@@ -510,8 +557,8 @@ typedef struct
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
-#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
/**
* @}
*/
@@ -519,8 +566,8 @@ typedef struct
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
*/
-#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U)
-#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
+#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */
/**
* @}
*/
@@ -528,7 +575,7 @@ typedef struct
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
-#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U)
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
@@ -536,8 +583,8 @@ typedef struct
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
*/
-#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U)
-#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
+#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */
/**
* @}
*/
@@ -545,7 +592,7 @@ typedef struct
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U)
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -553,7 +600,7 @@ typedef struct
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U)
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -561,7 +608,7 @@ typedef struct
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
* @{
*/
-#define UART_IT_MASK ((uint32_t)0x001FU)
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
/**
* @}
*/
@@ -569,7 +616,7 @@ typedef struct
/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
* @{
*/
-#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
/**
* @}
*/
@@ -579,63 +626,60 @@ typedef struct
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define UART_FLAG_TEACK ((uint32_t)0x00200000U)
-#define UART_FLAG_SBKF ((uint32_t)0x00040000U)
-#define UART_FLAG_CMF ((uint32_t)0x00020000U)
-#define UART_FLAG_BUSY ((uint32_t)0x00010000U)
-#define UART_FLAG_ABRF ((uint32_t)0x00008000U)
-#define UART_FLAG_ABRE ((uint32_t)0x00004000U)
-#define UART_FLAG_EOBF ((uint32_t)0x00001000U)
-#define UART_FLAG_RTOF ((uint32_t)0x00000800U)
-#define UART_FLAG_CTS ((uint32_t)0x00000400U)
-#define UART_FLAG_CTSIF ((uint32_t)0x00000200U)
-#define UART_FLAG_LBDF ((uint32_t)0x00000100U)
-#define UART_FLAG_TXE ((uint32_t)0x00000080U)
-#define UART_FLAG_TC ((uint32_t)0x00000040U)
-#define UART_FLAG_RXNE ((uint32_t)0x00000020U)
-#define UART_FLAG_IDLE ((uint32_t)0x00000010U)
-#define UART_FLAG_ORE ((uint32_t)0x00000008U)
-#define UART_FLAG_NE ((uint32_t)0x00000004U)
-#define UART_FLAG_FE ((uint32_t)0x00000002U)
-#define UART_FLAG_PE ((uint32_t)0x00000001U)
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
+#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */
+#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
+#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
+#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
+#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
+#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
+#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
/**
* @}
*/
/** @defgroup UART_Interrupt_definition UART Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-#define UART_IT_PE ((uint32_t)0x0028U)
-#define UART_IT_TXE ((uint32_t)0x0727U)
-#define UART_IT_TC ((uint32_t)0x0626U)
-#define UART_IT_RXNE ((uint32_t)0x0525U)
-#define UART_IT_IDLE ((uint32_t)0x0424U)
-#define UART_IT_LBD ((uint32_t)0x0846U)
-#define UART_IT_CTS ((uint32_t)0x096AU)
-#define UART_IT_CM ((uint32_t)0x112EU)
-
-/** Elements values convention: 000000000XXYYYYYb
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * Elements values convention: 000000000XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- */
-#define UART_IT_ERR ((uint32_t)0x0060U)
-
-/** Elements values convention: 0000ZZZZ00000000b
+ * Elements values convention: 0000ZZZZ00000000b
* - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
*/
-#define UART_IT_ORE ((uint32_t)0x0300U)
-#define UART_IT_NE ((uint32_t)0x0200U)
-#define UART_IT_FE ((uint32_t)0x0100U)
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */
+
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
/**
* @}
*/
@@ -643,17 +687,15 @@ typedef struct
/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
* @{
*/
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
/**
* @}
*/
@@ -668,294 +710,308 @@ typedef struct
* @{
*/
-/** @brief Reset UART handle state
+/** @brief Reset UART handle states.
* @param __HANDLE__ UART handle.
* @retval None
*/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0)
+ } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-/** @brief Flush the UART Data registers
+/** @brief Flush the UART Data registers.
* @param __HANDLE__ specifies the UART Handle.
+ * @retval None
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
-/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
+/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * @param __FLAG__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
- * This parameter can be one of the following values:
- * @arg UART_CLEAR_PEF: Parity Error Clear Flag
- * @arg UART_CLEAR_FEF: Framing Error Clear Flag
- * @arg UART_CLEAR_NEF: Noise detected Clear Flag
- * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
- * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
- * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg UART_CLEAR_EOBF: End Of Block Clear Flag
- * @arg UART_CLEAR_CMF: Character Match Clear Flag
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
* @retval None
*/
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the UART PE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
/** @brief Clear the UART FE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
/** @brief Clear the UART NE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
/** @brief Clear the UART ORE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
/** @brief Clear the UART IDLE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
-/** @brief Checks whether the specified UART flag is set or not.
+/** @brief Check whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg UART_FLAG_REACK: Receive enable acknowledge flag
- * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg UART_FLAG_WUF: Wake up from stop mode flag
- * @arg UART_FLAG_RWU: Receiver wake up flag (is the UART in mute mode)
- * @arg UART_FLAG_SBKF: Send Break flag
- * @arg UART_FLAG_CMF: Character match flag
- * @arg UART_FLAG_BUSY: Busy flag
- * @arg UART_FLAG_ABRF: Auto Baud rate detection flag
- * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg UART_FLAG_EOBF: End of block flag
- * @arg UART_FLAG_RTOF: Receiver timeout flag
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TXE: Transmit data register empty flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_RXNE: Receive data register not empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
- * @arg UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-/** @brief Enables the specified UART interrupt.
+/** @brief Enable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-/** @brief Disables the specified UART interrupt.
+/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-/** @brief Checks whether the specified UART interrupt has occurred or not.
+/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt to check.
+ * @param __INTERRUPT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Checks whether the specified UART interrupt source is enabled.
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt source to check.
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific UART request flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
- * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg UART_SENDBREAK_REQUEST: Send Break Request
- * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
- * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-/** @brief Enables the UART one bit sample method
+/** @brief Enable the UART one bit sample method.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-/** @brief Disables the UART one bit sample method
+/** @brief Disable the UART one bit sample method.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
-/** @brief Enable UART
+/** @brief Enable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable UART
+/** @brief Disable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/** @brief Enable CTS flow control
- * This macro allows to enable CTS hardware flow control for a given UART instance,
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0)
+ } while(0U)
-/** @brief Disable CTS flow control
- * This macro allows to disable CTS hardware flow control for a given UART instance,
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0)
+ } while(0U)
-/** @brief Enable RTS flow control
- * This macro allows to enable RTS hardware flow control for a given UART instance,
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0)
+ } while(0U)
-/** @brief Disable RTS flow control
- * This macro allows to disable RTS hardware flow control for a given UART instance,
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0)
-
+ } while(0U)
/**
* @}
*/
@@ -964,148 +1020,286 @@ typedef struct
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
-/** @brief BRR division operation to set BRR register with LPUART
- * @param _PCLK_ LPUART clock
- * @param _BAUD_ Baud rate set by the user
- * @retval Division result
- */
-#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))
-/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
- * @param _PCLK_ UART clock
- * @param _BAUD_ Baud rate set by the user
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
* @retval Division result
*/
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
-/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
- * @param _PCLK_ UART clock
- * @param _BAUD_ Baud rate set by the user
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
* @retval Division result
*/
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
-/** @brief Check UART Baud rate
- * @param BAUDRATE Baudrate specified by the user
+
+/** @brief Check UART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval Test result (TRUE or FALSE).
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 27000001U)
-/** @brief Check UART assertion time
- * @param TIME 5-bit value assertion time
+/** @brief Check UART assertion time.
+ * @param __TIME__ 5-bit value assertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
-/** @brief Check UART deassertion time
- * @param TIME 5-bit value deassertion time
+/** @brief Check UART deassertion time.
+ * @param __TIME__ 5-bit value deassertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__ UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__ UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__ UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__ UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__ UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__ UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
-#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \
- ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__ UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__ UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
-#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \
- ((LIN) == UART_LIN_ENABLE))
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__ UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
-#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \
- ((DMATX) == UART_DMA_TX_ENABLE))
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__ UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
-#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \
- ((DMARX) == UART_DMA_RX_ENABLE))
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__ UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
-#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
- ((HDSEL) == UART_HALF_DUPLEX_ENABLE))
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__ UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
- ((PARAM) == UART_SENDBREAK_REQUEST) || \
- ((PARAM) == UART_MUTE_MODE_REQUEST) || \
- ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == UART_TXDATA_FLUSH_REQUEST))
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
- UART_ADVFEATURE_TXINVERT_INIT | \
- UART_ADVFEATURE_RXINVERT_INIT | \
- UART_ADVFEATURE_DATAINVERT_INIT | \
- UART_ADVFEATURE_SWAP_INIT | \
- UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
- UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__ UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
UART_ADVFEATURE_MSBFIRST_INIT))
-#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
- ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__ UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
-#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
- ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__ UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
-#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
- ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__ UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
-#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
- ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
-#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
- ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__ UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
-#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
-#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__ UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__ UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
-#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
- ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__ UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
-#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \
- ((POLARITY) == UART_DE_POLARITY_LOW))
/**
* @}
*/
-/* Include UART HAL Extension module */
+
+/* Include UART HAL Extended module */
#include "stm32f7xx_hal_uart_ex.h"
+
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1120,11 +1314,16 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1143,6 +1342,13 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
@@ -1150,6 +1356,9 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
/**
* @}
@@ -1161,7 +1370,6 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
@@ -1178,7 +1386,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/* Peripheral State and Errors functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
@@ -1192,7 +1400,9 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
-
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
@@ -1214,6 +1424,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
}
#endif
-#endif /* __STM32F7xx_HAL_UART_H */
+#endif /* STM32F7xx_HAL_UART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart_ex.h
index 61895693060198502ba1a5937b8422db8d09a85f..3917016caeedca674d54ffc7c6d52f2d0442edcc 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_uart_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_uart_ex.h
* @author MCD Application Team
- * @brief Header file of UART HAL Extension module.
+ * @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_UART_EX_H
-#define __STM32F7xx_HAL_UART_EX_H
+#ifndef STM32F7xx_HAL_UART_EX_H
+#define STM32F7xx_HAL_UART_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -53,6 +37,15 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
@@ -61,25 +54,18 @@
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
-#define UART_WORDLENGTH_8B ((uint32_t)0x0000U)
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
-#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
- ((__LENGTH__) == UART_WORDLENGTH_8B) || \
- ((__LENGTH__) == UART_WORDLENGTH_9B))
-#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
-
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
-#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)
-#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
- ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
@@ -89,15 +75,55 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
-/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
-/** @brief Reports the UART clock source.
- * @param __HANDLE__ specifies the UART Handle
- * @param __CLOCKSOURCE__ output variable
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -119,6 +145,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -139,6 +166,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -159,6 +187,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -179,6 +208,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -199,6 +229,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -219,6 +250,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -239,9 +271,10 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
- } \
+ } \
else if ((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
@@ -259,93 +292,90 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
- } \
- } while(0)
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
-/** @brief Reports the UART mask to apply to retrieve the received data
+/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * If PCE = 1, the parity bit is not included in the data extracted
+ * @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
- * @param __HANDLE__ specifies the UART Handle
- * @retval mask to apply to UART RDR register value.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#define UART_MASK_COMPUTATION(__HANDLE__) \
+#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU ; \
} \
} \
-} while(0)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup UARTEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+} while(0U)
/**
- * @}
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__ UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
/**
- * @}
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
- * @{
+ * @brief Ensure that UART wake-up address length is valid.
+ * @param __ADDRESS__ UART wake-up address length.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
/**
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+
/**
* @}
*/
@@ -358,6 +388,6 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua
}
#endif
-#endif /* __STM32F7xx_HAL_UART_EX_H */
+#endif /* STM32F7xx_HAL_UART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart.h
index 64fca4f457167415249550aac39369c1b0cbc5c4..9f615f39625d2c273e5877ed55a4e67cf55a9e49 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_USART_H
-#define __STM32F7xx_HAL_USART_H
+#ifndef STM32F7xx_HAL_USART_H
+#define STM32F7xx_HAL_USART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -64,13 +48,17 @@ typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */
+ Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency
+ @note Oversampling by 8 is systematically applied to achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USARTEx_Word_Length */
+ This parameter can be a value of @ref USARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
+ This parameter can be a value of @ref USART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@@ -80,86 +68,126 @@ typedef struct
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref USART_Over_Sampling */
+ This parameter can be a value of @ref USART_Mode. */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
+ This parameter can be a value of @ref USART_Clock_Polarity. */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
+ This parameter can be a value of @ref USART_Clock_Phase. */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
+ This parameter can be a value of @ref USART_Last_Bit. */
+
+} USART_InitTypeDef;
/**
* @brief HAL USART State structures definition
*/
typedef enum
{
- HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
-
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
+} HAL_USART_StateTypeDef;
/**
* @brief USART clock sources definitions
*/
typedef enum
{
- USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
- USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}USART_ClockSourceTypeDef;
-
+} USART_ClockSourceTypeDef;
/**
* @brief USART handle Structure definition
*/
-typedef struct
+typedef struct __USART_HandleTypeDef
{
- USART_TypeDef *Instance; /*!< USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< USART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
- USART_InitTypeDef Init; /*!< USART communication parameters */
+ uint16_t Mask; /*!< USART Rx RDR register mask */
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+ void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
- uint16_t TxXferSize; /*!< USART Tx Transfer size */
+ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
- __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
- uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
- uint16_t RxXferSize; /*!< USART Rx Transfer size */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
- uint16_t Mask; /*!< USART Rx RDR register mask */
+ __IO uint32_t ErrorCode; /*!< USART Error code */
- DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
+ void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
+ void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
+ void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
- DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+ void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
+ void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
- HAL_LockTypeDef Lock; /*!< Locking object */
+} USART_HandleTypeDef;
- HAL_USART_StateTypeDef State; /*!< USART communication state */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL USART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
+ HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
+ HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
+ HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
+ HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
+ HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
+ HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
- __IO uint32_t ErrorCode; /*!< USART Error code */
+ HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
+ HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
+
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL USART Callback pointer definition
+ */
+typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}USART_HandleTypeDef;
/**
* @}
*/
@@ -169,16 +197,18 @@ typedef struct
* @{
*/
-/** @defgroup USART_Error_Code USART Error Code
- * @brief USART Error Code
+/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -186,9 +216,10 @@ typedef struct
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#define USART_STOPBITS_1 ((uint32_t)0x0000U)
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
+#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
+#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
/**
* @}
*/
@@ -196,9 +227,9 @@ typedef struct
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE ((uint32_t)0x0000U)
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define USART_PARITY_NONE 0x00000000U /*!< No parity */
+#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
@@ -206,9 +237,9 @@ typedef struct
/** @defgroup USART_Mode USART Mode
* @{
*/
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
@@ -216,16 +247,17 @@ typedef struct
/** @defgroup USART_Over_Sampling USART Over Sampling
* @{
*/
-#define USART_OVERSAMPLING_16 ((uint32_t)0x0000U)
-#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
+
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE ((uint32_t)0x0000U)
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
+#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
+#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
/**
* @}
*/
@@ -233,8 +265,8 @@ typedef struct
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW ((uint32_t)0x0000U)
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
+#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
/**
* @}
*/
@@ -242,8 +274,8 @@ typedef struct
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE ((uint32_t)0x0000U)
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
/**
* @}
*/
@@ -251,17 +283,18 @@ typedef struct
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE ((uint32_t)0x0000U)
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
+
/** @defgroup USART_Request_Parameters USART Request Parameters
* @{
*/
-#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
@@ -271,20 +304,16 @@ typedef struct
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define USART_FLAG_REACK ((uint32_t)0x00400000U)
-#define USART_FLAG_TEACK ((uint32_t)0x00200000U)
-#define USART_FLAG_BUSY ((uint32_t)0x00010000U)
-#define USART_FLAG_CTS ((uint32_t)0x00000400U)
-#define USART_FLAG_CTSIF ((uint32_t)0x00000200U)
-#define USART_FLAG_LBDF ((uint32_t)0x00000100U)
-#define USART_FLAG_TXE ((uint32_t)0x00000080U)
-#define USART_FLAG_TC ((uint32_t)0x00000040U)
-#define USART_FLAG_RXNE ((uint32_t)0x00000020U)
-#define USART_FLAG_IDLE ((uint32_t)0x00000010U)
-#define USART_FLAG_ORE ((uint32_t)0x00000008U)
-#define USART_FLAG_NE ((uint32_t)0x00000004U)
-#define USART_FLAG_FE ((uint32_t)0x00000002U)
-#define USART_FLAG_PE ((uint32_t)0x00000001U)
+#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
+#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
+#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
+#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
+#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
+#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
+#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
+#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
+#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
/**
* @}
*/
@@ -300,16 +329,16 @@ typedef struct
* @{
*/
-#define USART_IT_PE ((uint16_t)0x0028U)
-#define USART_IT_TXE ((uint16_t)0x0727U)
-#define USART_IT_TC ((uint16_t)0x0626U)
-#define USART_IT_RXNE ((uint16_t)0x0525U)
-#define USART_IT_IDLE ((uint16_t)0x0424U)
-#define USART_IT_ERR ((uint16_t)0x0060U)
+#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
+#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
+#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
+#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
+#define USART_IT_ERR 0x0060U /*!< USART error interruption */
+#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
+#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
+#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
-#define USART_IT_ORE ((uint16_t)0x0300U)
-#define USART_IT_NE ((uint16_t)0x0200U)
-#define USART_IT_FE ((uint16_t)0x0100U)
/**
* @}
*/
@@ -317,13 +346,24 @@ typedef struct
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
-#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
+ * @{
+ */
+#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
+#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
+#define USART_CR_POS 5U /*!< USART control register position */
+#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
+#define USART_ISR_POS 8U /*!< USART ISR register position */
/**
* @}
*/
@@ -337,230 +377,224 @@ typedef struct
* @{
*/
-/** @brief Reset USART handle state
+/** @brief Reset USART handle state.
* @param __HANDLE__ USART handle.
* @retval None
*/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-/** @brief Checks whether the specified USART flag is set or not.
+/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive enable acknowledge flag
- * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg USART_FLAG_BUSY: Busy flag
- * @arg USART_FLAG_CTS: CTS Change flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
+ * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref USART_FLAG_BUSY Busy flag
+ * @arg @ref USART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref USART_FLAG_TC Transmission Complete flag
+ * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref USART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref USART_FLAG_ORE OverRun Error flag
+ * @arg @ref USART_FLAG_NE Noise Error flag
+ * @arg @ref USART_FLAG_FE Framing Error flag
+ * @arg @ref USART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+/** @brief Clear the specified USART pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-/** @brief Enables the specified USART interrupt.
- * @param __HANDLE__ specifies the USART Handle
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+
+
+/** @brief Enable the specified USART interrupt.
+ * @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-/** @brief Disables the specified USART interrupt.
+/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__ specifies the USART Handle
- * @param __IT__ specifies the USART interrupt source to check.
+/** @brief Check whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-
-/** @brief Checks whether the specified USART interrupt source is enabled.
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
- * @param __IT__ specifies the USART interrupt source to check.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
- (((uint16_t)(__IT__)) & USART_IT_MASK)))
-
-
-/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
+
+
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
+ * to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
* @param __HANDLE__ specifies the USART Handle.
- * @param __REQ__ specifies the request flag to set
+ * @param __REQ__ specifies the request flag to set.
* This parameter can be one of the following values:
- * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-/** @brief Enable USART
+/** @brief Enable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-/** @brief Disable USART
+/** @brief Disable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
-/**
- * @}
- */
-/* Include UART HAL Extension module */
-#include "stm32f7xx_hal_usart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
-/**
- * @}
+/** @brief Enable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
*/
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @addtogroup USART_Exported_Functions_Group2
- * @{
+/** @brief Disable USART.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None
*/
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
-/** @addtogroup USART_Exported_Functions_Group3
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
-/* Peripheral State functions ************************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-/**
- * @}
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ USART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
*/
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
- * @{
- */
-/** @brief USART interruptions flag mask
- *
- */
-#define USART_IT_MASK ((uint16_t)0x001FU)
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-/** @brief Reports the USART clock source.
- * @param __HANDLE__ specifies the USART Handle
- * @param __CLOCKSOURCE__ output variable
+/** @brief Report the USART clock source.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
-#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\
+#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -579,6 +613,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -599,6 +634,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -619,6 +655,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
@@ -639,40 +676,173 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
- } while(0)
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+/** @brief Check USART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
-#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
+/**
+ * @brief Ensure that USART frame number of stop bits is valid.
+ * @param __STOPBITS__ USART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_1_5) || \
((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+ * @brief Ensure that USART frame parity is valid.
+ * @param __PARITY__ USART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
((__PARITY__) == USART_PARITY_EVEN) || \
((__PARITY__) == USART_PARITY_ODD))
-#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
+
+/**
+ * @brief Ensure that USART communication mode is valid.
+ * @param __MODE__ USART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that USART oversampling is valid.
+ * @param __SAMPLING__ USART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
((__SAMPLING__) == USART_OVERSAMPLING_8))
-#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__)== USART_CLOCK_DISABLE) || \
- ((__CLOCK__)== USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART clock state is valid.
+ * @param __CLOCK__ USART clock state.
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+ */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+ ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART frame polarity is valid.
+ * @param __CPOL__ USART frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that USART frame phase is valid.
+ * @param __CPHA__ USART frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ USART frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__ USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
+/* Include USART HAL Extended module */
+#include "stm32f7xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
* @{
*/
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -689,6 +859,6 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
}
#endif
-#endif /* __STM32F7xx_HAL_USART_H */
+#endif /* STM32F7xx_HAL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart_ex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart_ex.h
index adf8f444d67ee6905850533452049ee882b15ac2..e8dc9a9c568aa4c50c3f9d675c4bb8bd9e0e699e 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart_ex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_usart_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f7xx_hal_usart_ex.h
* @author MCD Application Team
- * @brief Header file of USART HAL Extension module.
+ * @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_USART_EX_H
-#define __STM32F7xx_HAL_USART_EX_H
+#ifndef STM32F7xx_HAL_USART_EX_H
+#define STM32F7xx_HAL_USART_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -61,83 +45,117 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
+
+
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
-/** @brief Computes the USART mask to apply to retrieve the received data
+/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * If PCE = 1, the parity bit is not included in the data extracted
+ * @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
- * @param __HANDLE__ specifies the USART Handle
- * @retval none
+ * @param __HANDLE__ specifies the USART Handle.
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
+#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU; \
} \
} \
-} while(0)
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+} while(0U)
+
+/**
+ * @brief Ensure that USART frame length is valid.
+ * @param __LENGTH__ USART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
+
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization methods **********************************/
-/* IO operation methods *******************************************************/
-/* Peripheral Control methods ************************************************/
-/* Peripheral State methods **************************************************/
+/** @addtogroup USARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -151,6 +169,6 @@
}
#endif
-#endif /* __STM32F7xx_HAL_USART_EX_H */
+#endif /* STM32F7xx_HAL_USART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_wwdg.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_wwdg.h
index 2a58295d23451b01771e6b06e2024e7db6f5f28b..f6ccb4ee116f0b773a740467beefd55ec7a2a725 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_wwdg.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_hal_wwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_WWDG_H
-#define __STM32F7xx_HAL_WWDG_H
+#ifndef STM32F7xx_HAL_WWDG_H
+#define STM32F7xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
@@ -75,18 +59,44 @@ typedef struct
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
-}WWDG_InitTypeDef;
+} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
typedef struct
+#endif
{
- WWDG_TypeDef *Instance; /*!< Register base address */
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif
+} WWDG_HandleTypeDef;
-}WWDG_HandleTypeDef;
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL WWDG common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+}HAL_WWDG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL WWDG Callback pointer definition
+ */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+
+#endif
/**
* @}
*/
@@ -117,10 +127,10 @@ typedef struct
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -143,9 +153,9 @@ typedef struct
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
@@ -174,7 +184,7 @@ typedef struct
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -247,6 +257,12 @@ typedef struct
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif
+
/**
* @}
*/
@@ -257,7 +273,7 @@ void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_adc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_adc.h
index 5d2ff02a687cae20c3d0ebf815e5373b863458e5..3216dfb3ca0267edc217ed0155b48eabfe188811 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_adc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_adc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -271,11 +255,11 @@ extern "C" {
#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF07A4A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF07A4C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF07A4E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
@@ -309,7 +293,7 @@ extern "C" {
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
/**
* @}
@@ -2471,7 +2455,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -2564,7 +2548,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
return (uint32_t) (READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -3129,7 +3113,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_JOFR1_JOFFSET1,
@@ -3156,7 +3140,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JOFR1_JOFFSET1)
@@ -3253,7 +3237,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
@@ -3326,7 +3310,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
@@ -3563,7 +3547,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
MODIFY_REG(*preg,
ADC_HTR_HT,
@@ -3586,7 +3570,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
}
@@ -4121,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4148,7 +4132,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4175,7 +4159,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4202,7 +4186,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4229,7 +4213,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_bus.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_bus.h
index fe5272fb57fe04d9ca2ba8323f46815dd66ce1fb..dc9c0db9aa79f28e0f4e182e852bdc90e571e356 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_bus.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_bus.h
@@ -23,29 +23,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_cortex.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_cortex.h
index 37e3fa7986d52f2b6209993c2763ff440a7c4b88..9a8d2109727dc129a34e6528b117ae07cfbeecad 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_cortex.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_cortex.h
@@ -21,29 +21,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_crc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_crc.h
index 7d2b7efd27885f7a1dd1d20a92345a1e3be8b312..fbb10711a41d7283f8a8af9d68087e0578b6852a 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_crc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_crc.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_CRC_H
-#define __STM32F7xx_LL_CRC_H
+#ifndef STM32F7xx_LL_CRC_H
+#define STM32F7xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
@@ -134,7 +118,7 @@ extern "C" {
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
@@ -352,7 +336,10 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
- *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+ __IO uint16_t *pReg;
+
+ pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = InData;
}
/**
@@ -431,7 +418,7 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
@@ -472,6 +459,6 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
}
#endif
-#endif /* __STM32F7xx_LL_CRC_H */
+#endif /* STM32F7xx_LL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dac.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dac.h
index 3a1ba1e520921286dbb85fea816e263af1a9c603..4127807992b74cd242ccf14097ead0889e38b2ca 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dac.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dac.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -125,7 +109,7 @@ extern "C" {
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
@@ -454,7 +438,7 @@ typedef struct
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma.h
index fa038a387053e85c2afcdf42688a48a31d56f8e7..fa4b634a918f640446e5daba50b44ca74cada506 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma2d.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma2d.h
index c33f2a63099395035659f3f77bec2b1d0394d42d..f8e1f1131154cfdaeb9df7c84485a652712c4082 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma2d.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_dma2d.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_DMA2D_H
-#define __STM32F7xx_LL_DMA2D_H
+#ifndef STM32F7xx_LL_DMA2D_H
+#define STM32F7xx_LL_DMA2D_H
#ifdef __cplusplus
extern "C" {
@@ -133,7 +117,9 @@ typedef struct
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
- uint32_t LineOffset; /*!< Specifies the output line offset value.
+
+
+ uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
@@ -148,7 +134,7 @@ typedef struct
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
@@ -174,7 +160,7 @@ typedef struct
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
- @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
- uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
+ uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using unitary functions
@@ -260,6 +246,7 @@ typedef struct
- @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
} LL_DMA2D_LayerCfgTypeDef;
/**
@@ -354,10 +341,10 @@ typedef struct
/** @defgroup DMA2D_LL_EC_MODE Mode
* @{
*/
-#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
-#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
-#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
+#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
@@ -403,7 +390,8 @@ typedef struct
* @}
*/
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
* @{
*/
@@ -423,6 +411,8 @@ typedef struct
*/
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+
/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
* @{
*/
@@ -432,6 +422,7 @@ typedef struct
* @}
*/
+
/**
* @}
*/
@@ -452,7 +443,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in DMA2D register.
@@ -460,7 +451,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -497,7 +488,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
}
/**
@@ -534,7 +525,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
}
/**
@@ -559,7 +550,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
}
/**
@@ -626,7 +617,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
}
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/**
* @brief Set DMA2D output Red Blue swap mode.
* @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
@@ -683,6 +674,8 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+
/**
* @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll OOR LO LL_DMA2D_SetLineOffset
@@ -889,7 +882,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
+ return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
}
/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
@@ -938,7 +931,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
+ return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
}
/**
@@ -1038,7 +1031,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
}
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/**
* @brief Set DMA2D foreground Red Blue swap mode.
* @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
@@ -1327,7 +1320,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
+ return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
}
/**
@@ -1427,7 +1420,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
}
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/**
* @brief Set DMA2D background Red Blue swap mode.
* @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
@@ -1687,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
}
/**
@@ -1698,7 +1691,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
}
/**
@@ -1709,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
}
/**
@@ -1720,7 +1713,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
}
/**
@@ -1731,7 +1724,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
}
/**
@@ -1742,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
}
/**
@@ -1959,7 +1952,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
}
/**
@@ -1970,7 +1963,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
}
/**
@@ -1981,7 +1974,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
}
/**
@@ -1992,7 +1985,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
}
/**
@@ -2003,7 +1996,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
}
/**
@@ -2014,7 +2007,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
}
@@ -2063,6 +2056,6 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
}
#endif
-#endif /* __STM32F7xx_LL_DMA2D_H */
+#endif /* STM32F7xx_LL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_exti.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_exti.h
index 0c0c30b2bee5e99e7f069abe1b45c6aba3fdace8..b40dc3228459c58c352606117f491b468a8c843e 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_exti.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_exti.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_fmc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_fmc.h
index 7fd9340b5251b6c8299913036dc7d3ba3c53d825..a217ffe70dbee3a6ef97a0acc29f7f8d37363524 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_fmc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_fmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_gpio.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_gpio.h
index 92c6ae1b21e0e8fccc306a92f9f64f68b612c872..bff720a7bc1e5603f16a5fa606a87bdb0a491450 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_gpio.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_gpio.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_i2c.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_i2c.h
index f90cb6213b5050b49f9f9a217576e4bb8ce19a77..cb56430deb2fc69926759cce3fbcc100bbe6f800 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_i2c.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_i2c.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_I2C_H
-#define __STM32F7xx_LL_I2C_H
+#ifndef STM32F7xx_LL_I2C_H
+#define STM32F7xx_LL_I2C_H
#ifdef __cplusplus
extern "C" {
@@ -431,7 +415,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
/**
@@ -513,7 +497,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
/**
@@ -546,7 +530,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -579,7 +563,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -594,7 +578,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
- register uint32_t data_reg_addr = 0U;
+ register uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
@@ -642,7 +626,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
/**
@@ -675,7 +659,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
@@ -711,7 +695,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
/**
@@ -788,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+ return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
/**
@@ -844,7 +828,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+ return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
/**
@@ -999,7 +983,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
/**
@@ -1038,7 +1022,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
/**
@@ -1203,7 +1187,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
- return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
}
/**
@@ -1244,7 +1228,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
/**
@@ -1277,7 +1261,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
/**
@@ -1310,7 +1294,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
/**
@@ -1343,7 +1327,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
/**
@@ -1376,7 +1360,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
/**
@@ -1415,7 +1399,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
/**
@@ -1466,7 +1450,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
/**
@@ -1487,7 +1471,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
/**
@@ -1500,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
/**
@@ -1513,7 +1497,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -1526,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
/**
@@ -1539,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
/**
@@ -1552,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
/**
@@ -1565,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
/**
@@ -1578,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
/**
@@ -1591,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
/**
@@ -1604,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
/**
@@ -1617,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
/**
@@ -1632,7 +1616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
/**
@@ -1647,7 +1631,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
/**
@@ -1663,7 +1647,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
/**
@@ -1676,7 +1660,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
/**
@@ -1837,7 +1821,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
/**
@@ -1872,7 +1856,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
/**
@@ -1971,7 +1955,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
/**
@@ -2069,7 +2053,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+ SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
/**
@@ -2124,7 +2108,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
/**
@@ -2172,8 +2156,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
* @{
*/
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
@@ -2200,6 +2184,6 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
}
#endif
-#endif /* __STM32F7xx_LL_I2C_H */
+#endif /* STM32F7xx_LL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_iwdg.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_iwdg.h
index fcbe80c47a054319e4aa7e44a53be5d7e9b2165e..50412ac08f500de8be3146b1a2b6b28a222ac077 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_iwdg.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_iwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_IWDG_H
-#define __STM32F7xx_LL_IWDG_H
+#ifndef STM32F7xx_LL_IWDG_H
+#define STM32F7xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
@@ -61,12 +45,10 @@ extern "C" {
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
-
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
/**
* @}
*/
@@ -86,7 +68,6 @@ extern "C" {
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
-
/**
* @}
*/
@@ -160,7 +141,7 @@ extern "C" {
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
@@ -171,7 +152,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
@@ -182,7 +163,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
@@ -193,7 +174,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
@@ -230,7 +211,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->PR));
+ return (READ_REG(IWDGx->PR));
}
/**
@@ -253,7 +234,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->RLR));
+ return (READ_REG(IWDGx->RLR));
}
/**
@@ -276,7 +257,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->WINR));
+ return (READ_REG(IWDGx->WINR));
}
/**
@@ -295,7 +276,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
@@ -306,7 +287,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
@@ -317,7 +298,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
@@ -330,7 +311,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
/**
@@ -346,7 +327,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
* @}
*/
-#endif /* IWDG) */
+#endif /* IWDG */
/**
* @}
@@ -356,6 +337,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
}
#endif
-#endif /* __STM32F7xx_LL_IWDG_H */
+#endif /* STM32F7xx_LL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_lptim.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_lptim.h
index f125a782c79e4fd9cf6f3ad33687240620309faa..b58fa2e25f06623795878a315f15287c7403077d 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_lptim.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_lptim.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -981,7 +965,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
}
/**
- * @brief Inform application whether a autoreload match interrupt has occured.
+ * @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_pwr.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_pwr.h
index 6ceda976a547bb6bfe36fdcd9f917863933510a6..3592ad2514aeee8da9f9a78f4b5b6d09f9f634bd 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_pwr.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_pwr.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rcc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rcc.h
index 7e76fddcfc4ab9724eac3772459f104661250e24..e0a1db7c4199a5d0e409428ae93018eba7452730 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rcc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -137,6 +121,14 @@ typedef struct
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
#endif /* EXTERNAL_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rng.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rng.h
index a7e684f923473100275efdd0193c0e1ed82cb8f7..21406a5027bebb06050283c09045187e36d39428 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rng.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rng.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_RNG_H
-#define __STM32F7xx_LL_RNG_H
+#ifndef STM32F7xx_LL_RNG_H
+#define STM32F7xx_LL_RNG_H
#ifdef __cplusplus
extern "C" {
@@ -48,7 +32,7 @@ extern "C" {
* @{
*/
-#if defined(RNG)
+#if defined (RNG)
/** @defgroup RNG_LL RNG
* @{
@@ -65,6 +49,7 @@ extern "C" {
* @{
*/
+
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
@@ -163,7 +148,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
+ return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
/**
@@ -182,7 +167,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
+ return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
/**
@@ -193,7 +178,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
/**
@@ -204,7 +189,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
/**
@@ -215,7 +200,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
/**
@@ -226,7 +211,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
/**
@@ -292,7 +277,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
+ return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
/**
@@ -322,7 +307,6 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
/**
@@ -338,7 +322,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
* @}
*/
-#endif /* defined(RNG) */
+#endif /* RNG */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rtc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rtc.h
index 9a55fa68aeaa7b55b08f582315981270d6769823..be862e68ffeb42494f64cba408b83c6ad761a051 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rtc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_rtc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1110,10 +1094,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
- return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
}
/**
@@ -1148,10 +1129,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
- return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos);
}
/**
@@ -1186,10 +1164,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
}
/**
@@ -1382,10 +1357,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
}
/**
@@ -1478,10 +1450,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
- return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos);
}
/**
@@ -1511,10 +1480,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
- return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
}
/**
@@ -1711,10 +1677,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
- return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
}
/**
@@ -1806,10 +1769,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
- return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
+ return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
}
/**
@@ -1837,10 +1797,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
- return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
}
/**
@@ -1868,10 +1825,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
}
/**
@@ -2089,10 +2043,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
- return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
+ return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
}
/**
@@ -2184,10 +2135,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
- return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
}
/**
@@ -2215,10 +2163,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
- return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
}
/**
@@ -2246,10 +2191,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
- return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_sdmmc.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_sdmmc.h
index edcd158249bbafa7e88746dfe4cf9fa3c13788f4..43fd0d7b5a6fa9dbbbc27f9927dc1c4140f8dfa8 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_sdmmc.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_sdmmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h
index 423ce133a0d2815b0d4f29d5f66a87416c81cda0..1a0ac48668bbd5e8f40b4cfdad6ffb3a5342533a 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_spi.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_SPI_H
-#define __STM32F7xx_LL_SPI_H
+#ifndef STM32F7xx_LL_SPI_H
+#define STM32F7xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
@@ -48,7 +32,7 @@ extern "C" {
* @{
*/
-#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
/** @defgroup SPI_LL SPI
* @{
@@ -397,7 +381,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
@@ -738,7 +722,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
/**
@@ -902,7 +886,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
}
/**
@@ -921,7 +905,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -932,7 +916,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
/**
@@ -943,7 +927,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
/**
@@ -954,7 +938,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
@@ -965,7 +949,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
@@ -983,7 +967,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
/**
@@ -994,7 +978,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
}
/**
@@ -1048,11 +1032,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void) tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
@@ -1170,7 +1153,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
/**
@@ -1181,7 +1164,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
/**
@@ -1192,7 +1175,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
/**
@@ -1233,7 +1216,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1266,7 +1249,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1373,7 +1356,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif
}
/**
@@ -1385,7 +1373,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
SPIx->DR = TxData;
+#endif
}
/**
@@ -1665,7 +1658,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
/**
@@ -1874,7 +1867,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
#if defined(SPI_I2SCFGR_ASTRTEN)
@@ -1908,7 +1901,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
}
#endif /* SPI_I2SCFGR_ASTRTEN */
@@ -1972,7 +1965,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
@@ -1997,7 +1990,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
/**
@@ -2276,7 +2269,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
* @}
*/
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
/**
* @}
@@ -2286,6 +2279,6 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
}
#endif
-#endif /* __STM32F7xx_LL_SPI_H */
+#endif /* STM32F7xx_LL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_system.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_system.h
index 665445bc40cc5ed3b57c599eb1af6c8e8d0f903c..8818ebdf24c818e2be25cdc572f1ad47be3e4894 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_system.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_system.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_tim.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_tim.h
index 5185647415711cb4c63d935e1ddc9bb30fe03ea5..6e8df2832712cdeef643416cf88bfe99833ec674 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_tim.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_tim.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -127,7 +111,6 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @}
*/
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{
@@ -135,20 +118,20 @@ static const uint8_t SHIFT_TAB_OISx[] =
#if defined(TIM_BREAK_INPUT_SUPPORT)
/* Defines used for the bit position in the register and perform offsets */
-#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source)
+#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */
#if defined(DFSDM1_Channel0)
#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */
#endif /* DFSDM1_Channel0 */
-#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
+#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
/* Generic bit definitions for TIMx_AF2 register */
#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */
#if defined(DFSDM1_Channel0)
#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */
#endif /* DFSDM1_Channel0 */
-#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
+#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
#endif /* TIM_BREAK_INPUT_SUPPORT */
/* Remap mask definitions */
@@ -159,16 +142,16 @@ static const uint8_t SHIFT_TAB_OISx[] =
#define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7FU)
-#define DT_DELAY_2 ((uint8_t)0x3FU)
-#define DT_DELAY_3 ((uint8_t)0x1FU)
-#define DT_DELAY_4 ((uint8_t)0x1FU)
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00U)
-#define DT_RANGE_2 ((uint8_t)0x80U)
-#define DT_RANGE_3 ((uint8_t)0xC0U)
-#define DT_RANGE_4 ((uint8_t)0xE0U)
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
/**
@@ -696,7 +679,7 @@ typedef struct
#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!TIMx_CCRy else active.*/
#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/
@@ -752,7 +735,7 @@ typedef struct
/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
* @{
*/
-#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
@@ -797,7 +780,7 @@ typedef struct
* @{
*/
#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
/**
* @}
@@ -806,9 +789,9 @@ typedef struct
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{
*/
-#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
/**
* @}
*/
@@ -866,14 +849,14 @@ typedef struct
/** @defgroup TIM_LL_EC_TS Trigger Selection
* @{
*/
-#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
/**
* @}
*/
@@ -1026,7 +1009,7 @@ typedef struct
/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
* @{
*/
-#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
/**
* @}
@@ -1054,13 +1037,14 @@ typedef struct
#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-
+#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
+#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+#endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
/**
* @}
*/
@@ -1128,7 +1112,6 @@ typedef struct
* @}
*/
-
/**
* @}
*/
@@ -1148,7 +1131,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in TIM register.
@@ -1156,7 +1139,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -1164,6 +1147,7 @@ typedef struct
/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
+
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@@ -1188,9 +1172,9 @@ typedef struct
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
@@ -1201,7 +1185,7 @@ typedef struct
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -1212,7 +1196,7 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -1300,7 +1284,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
/**
@@ -1329,11 +1313,11 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
* @brief Indicates whether update event generation is enabled.
* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
* @param TIMx Timer instance
- * @retval State of bit (1 or 0).
+ * @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
/**
@@ -1402,6 +1386,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
@@ -1415,7 +1402,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
- MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
}
/**
@@ -1457,7 +1444,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+ CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
}
/**
@@ -1468,7 +1455,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
/**
@@ -1835,7 +1822,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
- return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
/**
@@ -1881,7 +1868,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -1926,7 +1913,7 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -1965,7 +1952,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2125,7 +2112,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2151,7 +2138,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2177,9 +2164,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
@@ -2203,7 +2190,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2228,7 +2215,7 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2253,9 +2240,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
@@ -2282,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2309,7 +2296,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2338,13 +2325,13 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@@ -2437,7 +2424,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
- WRITE_REG(TIMx->CCR5, CompareValue);
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
}
/**
@@ -2528,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
{
- return (uint32_t)(READ_REG(TIMx->CCR5));
+ return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
}
/**
@@ -2552,7 +2539,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
* @param TIMx Timer instance
- * @param GroupCH5 This parameter can be one of the following values:
+ * @param GroupCH5 This parameter can be a combination of the following values:
* @arg @ref LL_TIM_GROUPCH5_NONE
* @arg @ref LL_TIM_GROUPCH5_OC1REFC
* @arg @ref LL_TIM_GROUPCH5_OC2REFC
@@ -2561,7 +2548,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
{
- MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
+ MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
}
/**
@@ -2609,7 +2596,7 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2637,7 +2624,7 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2661,7 +2648,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2687,7 +2674,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2712,7 +2699,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2750,7 +2737,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2787,7 +2774,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2884,7 +2871,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
/**
@@ -2995,7 +2982,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
/**
@@ -3175,7 +3162,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
/**
@@ -3402,7 +3389,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
/**
@@ -3445,7 +3432,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
#if defined(TIM_BREAK_INPUT_SUPPORT)
@@ -3468,8 +3455,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
- SET_BIT(*pReg , Source);
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ SET_BIT(*pReg, Source);
}
/**
@@ -3491,7 +3478,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3518,8 +3505,8 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
- MODIFY_REG(*pReg, (TIMx_AF1_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
#endif /* TIM_BREAK_INPUT_SUPPORT */
/**
@@ -3555,12 +3542,13 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
- * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*)
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*)
+ * (*) value not defined in all devices
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
@@ -3584,7 +3572,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
*/
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
- MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
}
/**
@@ -3641,7 +3629,6 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
* @}
*/
-
/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
* @{
*/
@@ -3664,7 +3651,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
/**
@@ -3686,7 +3673,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
/**
@@ -3708,7 +3695,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
/**
@@ -3730,7 +3717,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
/**
@@ -3752,7 +3739,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
/**
@@ -3774,7 +3761,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
}
/**
@@ -3796,7 +3783,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
}
/**
@@ -3818,7 +3805,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
/**
@@ -3840,7 +3827,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
/**
@@ -3862,7 +3849,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
/**
@@ -3884,7 +3871,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
}
/**
@@ -3906,7 +3893,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
/**
@@ -3928,7 +3915,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
/**
@@ -3950,7 +3937,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
/**
@@ -3972,7 +3959,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
/**
@@ -3994,7 +3981,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
}
/**
@@ -4034,7 +4021,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
/**
@@ -4067,7 +4054,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
/**
@@ -4100,7 +4087,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
/**
@@ -4133,7 +4120,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
/**
@@ -4166,7 +4153,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
/**
@@ -4199,7 +4186,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
/**
@@ -4232,7 +4219,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
/**
@@ -4265,7 +4252,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
/**
@@ -4305,7 +4292,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
/**
@@ -4338,7 +4325,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
@@ -4371,7 +4358,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
@@ -4404,7 +4391,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
/**
@@ -4437,7 +4424,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
/**
@@ -4470,7 +4457,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
/**
@@ -4503,7 +4490,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usart.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usart.h
index de906f0a794d10cbc86fd97064bf48adec7b54d3..df5db5ea4a5075eb7cf5a6439ab4659141af3ab5 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usart.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usart.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_USART_H
-#define __STM32F7xx_LL_USART_H
+#ifndef STM32F7xx_LL_USART_H
+#define STM32F7xx_LL_USART_H
#ifdef __cplusplus
extern "C" {
@@ -86,6 +70,7 @@ extern "C" {
*/
typedef struct
{
+
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
@@ -171,7 +156,7 @@ typedef struct
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
+#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
@@ -415,7 +400,6 @@ typedef struct
* @}
*/
-
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
*/
@@ -496,7 +480,7 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -505,7 +489,7 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -558,10 +542,9 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
-
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
@@ -762,7 +745,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
@@ -950,7 +933,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
/**
@@ -1195,7 +1178,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
/**
@@ -1263,7 +1246,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
/**
@@ -1442,7 +1425,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
/**
@@ -1475,10 +1458,9 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+ return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
-
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
@@ -1498,8 +1480,8 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
uint32_t BaudRate)
{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrtemp = 0x0U;
+ register uint32_t usartdiv;
+ register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
{
@@ -1529,16 +1511,20 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{
- register uint32_t usartdiv = 0x0U;
+ register uint32_t usartdiv;
register uint32_t brrresult = 0x0U;
usartdiv = USARTx->BRR;
- if (OverSampling == LL_USART_OVERSAMPLING_8)
+ if (usartdiv == 0U)
+ {
+ /* Do not perform a division by 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
- if ((usartdiv & 0xFFF7U) != 0U)
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ if (usartdiv != 0U)
{
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
brrresult = (PeriphClk * 2U) / usartdiv;
}
}
@@ -1642,7 +1628,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
/**
@@ -1688,7 +1674,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -1749,7 +1735,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
/**
@@ -1788,7 +1774,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
/**
@@ -1835,7 +1821,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -1864,7 +1850,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
@@ -1925,7 +1911,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
@@ -2003,7 +1989,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
/**
@@ -2104,7 +2090,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
@@ -2431,7 +2417,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
@@ -2442,18 +2428,18 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll ISR NF LL_USART_IsActiveFlag_NE
+ * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
@@ -2464,7 +2450,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
@@ -2475,7 +2461,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/**
@@ -2486,7 +2472,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -2497,7 +2483,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/**
@@ -2508,7 +2494,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
}
/**
@@ -2521,7 +2507,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
/**
@@ -2534,7 +2520,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
@@ -2547,7 +2533,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
@@ -2558,7 +2544,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
/**
@@ -2571,7 +2557,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
/**
@@ -2584,7 +2570,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
/**
@@ -2597,7 +2583,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
/**
@@ -2608,7 +2594,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
@@ -2619,7 +2605,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
@@ -2630,7 +2616,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
@@ -2641,10 +2627,9 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
-
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
@@ -2653,10 +2638,9 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
-
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -2667,7 +2651,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
#endif
@@ -2694,7 +2678,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
}
/**
- * @brief Clear Noise detected Flag
+ * @brief Clear Noise Error detected Flag
* @rmtoll ICR NCF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
@@ -2812,7 +2796,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
-
/**
* @}
*/
@@ -2952,7 +2935,6 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
-
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -3100,7 +3082,6 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
-
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -3125,7 +3106,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/**
@@ -3136,7 +3117,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
}
/**
@@ -3147,7 +3128,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/**
@@ -3158,7 +3139,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
}
/**
@@ -3169,7 +3150,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
@@ -3180,7 +3161,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
@@ -3191,7 +3172,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
/**
@@ -3204,7 +3185,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
/**
@@ -3217,7 +3198,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
/**
@@ -3228,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
@@ -3241,10 +3222,9 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
-
#if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */
/**
@@ -3257,7 +3237,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
#endif
@@ -3299,7 +3279,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
@@ -3332,7 +3312,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
@@ -3365,7 +3345,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
@@ -3380,17 +3360,17 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr = 0U;
+ register uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
- data_reg_addr = (uint32_t) &(USARTx->TDR);
+ data_reg_addr = (uint32_t) & (USARTx->TDR);
}
else
{
/* return address of RDR register */
- data_reg_addr = (uint32_t) &(USARTx->RDR);
+ data_reg_addr = (uint32_t) & (USARTx->RDR);
}
return data_reg_addr;
@@ -3447,7 +3427,7 @@ __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value
*/
__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{
- USARTx->TDR = Value & 0x1FFU;
+ USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
}
/**
@@ -3468,7 +3448,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu
*/
__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
}
/**
@@ -3479,7 +3459,7 @@ __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
@@ -3490,18 +3470,20 @@ __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data flush
+ * @note Allows to discard the received data without reading them, and avoid an overrun
+ * condition.
* @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
/**
@@ -3514,7 +3496,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
}
/**
@@ -3553,6 +3535,6 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS
}
#endif
-#endif /* __STM32F7xx_LL_USART_H */
+#endif /* STM32F7xx_LL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usb.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usb.h
index 94c13802b60074a8d593b6beb397d7250dd4dadc..d53f10ccc3638a87417487a4c54e1321b99ffc9e 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usb.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_usb.h
@@ -6,44 +6,29 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_USB_H
-#define __STM32F7xx_LL_USB_H
+#ifndef STM32F7xx_LL_USB_H
+#define STM32F7xx_LL_USB_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -57,30 +42,33 @@
/**
* @brief USB Mode definition
*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
typedef enum
{
- USB_DEVICE_MODE = 0,
- USB_HOST_MODE = 1,
- USB_DRD_MODE = 2
-}USB_OTG_ModeTypeDef;
+ USB_DEVICE_MODE = 0,
+ USB_HOST_MODE = 1,
+ USB_DRD_MODE = 2
+} USB_OTG_ModeTypeDef;
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief URB States definition
*/
-typedef enum {
+typedef enum
+{
URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
-}USB_OTG_URBStateTypeDef;
+} USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
-typedef enum {
+typedef enum
+{
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
@@ -90,135 +78,134 @@ typedef enum {
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
-}USB_OTG_HCStateTypeDef;
+} USB_OTG_HCStateTypeDef;
/**
* @brief USB OTG Initialization Structure definition
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t Host_channels; /*!< Host Channels number.
- This parameter Depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
- uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS_ */
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY_ */
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY_ */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
-}USB_OTG_CfgTypeDef;
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+} USB_OTG_CfgTypeDef;
typedef struct
{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type_ */
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t even_odd_frame; /*!< IFrame parity
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint16_t tx_fifo_num; /*!< Transmission FIFO number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
- uint32_t xfer_len; /*!< Current transfer length */
+ uint32_t xfer_len; /*!< Current transfer length */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-}USB_OTG_EPTypeDef;
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+} USB_OTG_EPTypeDef;
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
- This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+ uint8_t dev_addr ; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
- uint8_t ch_num; /*!< Host channel number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t ep_num; /*!< Endpoint number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t ep_is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint8_t speed; /*!< USB Host speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
- uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
- uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_EP_Type_ */
- uint16_t max_packet; /*!< Endpoint Max packet size.
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t data_pid; /*!< Initial data PID.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
- uint32_t xfer_len; /*!< Current transfer length. */
+ uint32_t xfer_len; /*!< Current transfer length. */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
- uint8_t toggle_in; /*!< IN transfer current toggle flag.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t toggle_out; /*!< OUT transfer current toggle flag
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
- uint32_t ErrCnt; /*!< Host channel error count.*/
+ uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
- This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
-}USB_OTG_HCTypeDef;
-#endif /* defined USB_OTG_FS || USB_OTG_HS */
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Exported constants --------------------------------------------------------*/
@@ -228,6 +215,15 @@ typedef struct
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+ * @{
+ */
+#define USB_OTG_CORE_ID_300A 0x4F54300AU
+#define USB_OTG_CORE_ID_310A 0x4F54310AU
+/**
+ * @}
+ */
+
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
@@ -243,7 +239,6 @@ typedef struct
*/
#define USB_OTG_SPEED_HIGH 0U
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
-#define USB_OTG_SPEED_LOW 2U
#define USB_OTG_SPEED_FULL 3U
/**
* @}
@@ -257,12 +252,26 @@ typedef struct
#define USB_OTG_HS_EMBEDDED_PHY 3U
#if !defined (USB_HS_PHYC_TUNE_VALUE)
- #define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
+#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
#endif /* USB_HS_PHYC_TUNE_VALUE */
/**
* @}
*/
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+ * @{
+ */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+ * @}
+ */
+
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
@@ -386,8 +395,9 @@ typedef struct
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@@ -402,7 +412,7 @@ typedef struct
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
@@ -412,45 +422,46 @@ typedef struct
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
@@ -459,17 +470,18 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
+
/**
* @}
*/
@@ -481,12 +493,13 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
/**
* @}
*/
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_LL_USB_H */
+#endif /* STM32F7xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_utils.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_utils.h
index a5defcf2e5f422899bab727f1f6eb3a0235efbf0..4a9d36899cb4c0a6e7cb40a12311d454594a46a8 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_utils.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_utils.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_wwdg.h b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_wwdg.h
index 2e95a63c8d2038ea9ad0d329160b169e5e97b141..620a524374a899a448ec2876239a6bf9130b27b1 100644
--- a/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_wwdg.h
+++ b/stm32cube/stm32f7xx/drivers/include/stm32f7xx_ll_wwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_LL_WWDG_H
-#define __STM32F7xx_LL_WWDG_H
+#ifndef STM32F7xx_LL_WWDG_H
+#define STM32F7xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
@@ -56,23 +40,19 @@ extern "C" {
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-
/* Private constants ---------------------------------------------------------*/
-
/* Private macros ------------------------------------------------------------*/
-
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
-
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
@@ -80,10 +60,10 @@ extern "C" {
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
-#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -119,7 +99,6 @@ extern "C" {
* @}
*/
-
/**
* @}
*/
@@ -155,7 +134,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+ return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
@@ -182,7 +161,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+ return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
@@ -196,7 +175,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
- * @retval None
+* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@@ -215,7 +194,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
@@ -247,7 +226,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
@@ -268,7 +247,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+ return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
@@ -310,7 +289,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+ return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/Legacy/stm32f7xx_hal_can.c b/stm32cube/stm32f7xx/drivers/src/Legacy/stm32f7xx_hal_can.c
index 8ad7876e169f80de4c8436a44a192c795a64c747..68e71178183590a68421747cc2bd17e81924d370 100644
--- a/stm32cube/stm32f7xx/drivers/src/Legacy/stm32f7xx_hal_can.c
+++ b/stm32cube/stm32f7xx/drivers/src/Legacy/stm32f7xx_hal_can.c
@@ -83,29 +83,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -130,9 +114,7 @@
#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f7xx_hal_conf.h file'
#endif /* HAL_CAN_MODULE_ENABLED */
-#if 0 /* Disable systematic warning message */
#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
-#endif
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -387,7 +369,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
#if defined (CAN3)
/* Check the CAN instance */
if(hcan->Instance == CAN3)
- {
+ {
can_ip = CAN3;
}
else
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal.c
index eabf6b1a22bb226776bf0dbbcc097d4ac7d1e8e4..44e336f36bf17db0bef5da806ba8d1c31a561e72 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal.c
@@ -21,29 +21,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -66,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F7xx HAL Driver version number V1.2.6
+ * @brief STM32F7xx HAL Driver version number V1.2.7
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -83,8 +67,8 @@
*/
/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Private_Variables
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
* @{
*/
__IO uint32_t uwTick;
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc.c
index 5e8bc23f6f47ced56b9bc074ee0113a475923689..fba4af894c67409e599475c180a198488651ea55 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc.c
@@ -129,7 +129,14 @@
(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
- [..]
+ *** Callback functions ***
+ ==============================
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
(@) You can refer to the ADC HAL driver header file for more useful macros
*** Deinitialization of ADC ***
@@ -158,33 +165,90 @@
(++) Deinitialize the DMA using function HAL_DMA_DeInit().
(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+ *** Callback registration ***
+ ==============================================================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -284,13 +348,30 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
if(hadc->State == HAL_ADC_STATE_RESET)
{
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
}
/* Configuration of ADC parameters if previous preliminary actions are */
@@ -355,8 +436,18 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
/* correctly completed. */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -402,6 +493,209 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/
}
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
@@ -516,6 +810,18 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
+
+ /* if dual mode is selected, ADC3 works independently. */
+ /* check if the mode selected is not triple */
+ if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+ {
+ /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
}
}
@@ -810,6 +1116,18 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
+
+ /* if dual mode is selected, ADC3 works independently. */
+ /* check if the mode selected is not triple */
+ if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+ {
+ /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
}
}
@@ -911,7 +1229,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
}
/* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
@@ -953,7 +1275,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
}
/* Conversion complete callback */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
@@ -970,7 +1296,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/* Clear the ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
@@ -993,7 +1324,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
- HAL_ADC_ErrorCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
@@ -1114,6 +1449,17 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
+ /* if dual mode is selected, ADC3 works independently. */
+ /* check if the mode selected is not triple */
+ if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
+ {
+ /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
}
}
@@ -1551,7 +1897,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
- hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
@@ -1576,7 +1922,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
- hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
@@ -1627,12 +1973,28 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
}
/* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
- else
+ else /* DMA and-or internal error occurred */
{
- /* Call DMA error callback */
- hadc->DMA_Handle->XferErrorCallback(hdma);
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
}
}
@@ -1645,8 +2007,12 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
@@ -1661,7 +2027,12 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc_ex.c
index 21c3d9946ac31c63190f6bad8bc6d7fd5b60e826..0cf31b9a7fe86fcbef62eabed8237fd906b7894d 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_adc_ex.c
@@ -84,29 +84,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_can.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_can.c
index 8ff325c23dbc5f261f0c7a71dadc79d98a7c60ba..a45b2a521f887444a74598bf7f8b78306dbfe4e2 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_can.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_can.c
@@ -126,33 +126,85 @@
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
if automatic wake up mode is enabled.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+
+ By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ example @ref HAL_CAN_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()
+ or @ref HAL_CAN_Init() function.
+
+ When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -221,7 +273,7 @@
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
@@ -243,11 +295,40 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Reset callbacks to legacy functions */
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
+ hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcan->MspInitCallback == NULL)
+ {
+ hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ hcan->MspInitCallback(hcan);
+ }
+
+#else
if (hcan->State == HAL_CAN_STATE_RESET)
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -256,7 +337,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Check Sleep mode leave acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -277,7 +358,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait initialisation acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -387,10 +468,21 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
/* Stop the CAN module */
- HAL_CAN_Stop(hcan);
+ (void)HAL_CAN_Stop(hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->MspDeInitCallback == NULL)
+ {
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
+ }
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hcan->MspDeInitCallback(hcan);
+
+#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -437,6 +529,284 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
*/
}
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a CAN CallBack.
+ * To be used instead of the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = pCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = pCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a CAN CallBack.
+ * CAN callabck is redirected to the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = HAL_CAN_SleepCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
@@ -467,11 +837,12 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
- uint32_t filternbrbitpos = 0U;
+ uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check the parameters */
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
@@ -481,7 +852,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
#if defined(CAN3)
/* Check the CAN instance */
@@ -536,7 +907,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
#endif
/* Convert filter number into bit position */
- filternbrbitpos = (1U) << sFilterConfig->FilterBank;
+ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
@@ -601,7 +972,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
}
/* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
+ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
}
@@ -660,7 +1031,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
{
@@ -674,7 +1045,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
@@ -712,7 +1083,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_LISTENING)
{
@@ -723,7 +1094,7 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
@@ -767,8 +1138,10 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
{
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Request Sleep mode */
SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -798,9 +1171,10 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Wake up request */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -808,8 +1182,11 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
/* Wait sleep mode is exited */
do
{
+ /* Increment counter */
+ count++;
+
/* Check if timeout is reached */
- if (++count > timeout)
+ if (count > timeout)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
@@ -817,7 +1194,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
return HAL_ERROR;
}
}
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -842,12 +1219,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
{
uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Sleep mode */
- if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
status = 1U;
}
@@ -872,6 +1250,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+ uint32_t tsr = READ_REG(hcan->Instance->TSR);
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(pHeader->IDE));
@@ -887,19 +1267,28 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
- if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||
- ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||
- ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))
+ if (((tsr & CAN_TSR_TME0) != 0U) ||
+ ((tsr & CAN_TSR_TME1) != 0U) ||
+ ((tsr & CAN_TSR_TME2) != 0U))
{
/* Select an empty transmit mailbox */
- transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Check transmit mailbox value */
+ if (transmitmailbox > 2U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
/* Store the Tx mailbox */
- *pTxMailbox = 1U << transmitmailbox;
+ *pTxMailbox = (uint32_t)1 << transmitmailbox;
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
@@ -968,28 +1357,30 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
*/
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 */
- if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
{
/* Add cancellation request for Tx Mailbox 0 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
}
/* Check Tx Mailbox 1 */
- if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
{
/* Add cancellation request for Tx Mailbox 1 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
}
/* Check Tx Mailbox 2 */
- if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
{
/* Add cancellation request for Tx Mailbox 2 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
@@ -1016,24 +1407,25 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
{
uint32_t freelevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 1 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 2 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
{
freelevel++;
}
@@ -1058,12 +1450,13 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check pending transmission request on the selected Tx Mailboxes */
if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
@@ -1090,12 +1483,13 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
{
uint32_t timestamp = 0U;
uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Select the Tx mailbox */
transmitmailbox = POSITION_VAL(TxMailbox);
@@ -1121,16 +1515,18 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
assert_param(IS_CAN_RX_FIFO(RxFifo));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
{
/* Check that the Rx FIFO 0 is not empty */
- if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
@@ -1138,10 +1534,10 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
return HAL_ERROR;
}
}
- else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
- if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
@@ -1166,14 +1562,14 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
/* Get the data */
- aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;
- aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;
- aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;
- aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;
- aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;
- aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;
- aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;
- aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;
+ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+ aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+ aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+ aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+ aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+ aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+ aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+ aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
@@ -1181,7 +1577,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
}
- else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
@@ -1210,12 +1606,13 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
uint32_t filllevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_RX_FIFO(RxFifo));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
if (RxFifo == CAN_RX_FIFO0)
{
@@ -1261,11 +1658,13 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
@@ -1292,11 +1691,13 @@ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t
*/
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_IT(InactiveITs));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Disable the selected interrupts */
__HAL_CAN_DISABLE_IT(hcan, InactiveITs);
@@ -1330,28 +1731,33 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
/* Transmit Mailbox empty interrupt management *****************************/
- if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
{
/* Transmit Mailbox 0 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP0) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP0) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
- if ((tsrflags & CAN_TSR_TXOK0) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK0) != 0U)
{
/* Transmission Mailbox 0 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST0) != RESET)
+ if ((tsrflags & CAN_TSR_ALST0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
}
- else if ((tsrflags & CAN_TSR_TERR0) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
@@ -1359,32 +1765,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 0 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 1 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP1) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP1) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
- if ((tsrflags & CAN_TSR_TXOK1) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK1) != 0U)
{
/* Transmission Mailbox 1 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST1) != RESET)
+ if ((tsrflags & CAN_TSR_ALST1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
}
- else if ((tsrflags & CAN_TSR_TERR1) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
@@ -1392,32 +1808,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 1 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 2 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP2) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP2) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
- if ((tsrflags & CAN_TSR_TXOK2) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK2) != 0U)
{
/* Transmission Mailbox 2 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST2) != RESET)
+ if ((tsrflags & CAN_TSR_ALST2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
}
- else if ((tsrflags & CAN_TSR_TERR2) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
@@ -1425,17 +1851,22 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 2 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
- if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
{
- if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)
+ if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
@@ -1446,35 +1877,45 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Receive FIFO 0 full interrupt management ********************************/
- if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
{
- if ((rf0rflags & CAN_RF0R_FULL0) != RESET)
+ if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
/* Receive FIFO 0 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
- if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
- if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
{
/* Receive FIFO 0 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
- if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
{
- if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)
+ if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
@@ -1485,67 +1926,87 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Receive FIFO 1 full interrupt management ********************************/
- if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
{
- if ((rf1rflags & CAN_RF1R_FULL1) != RESET)
+ if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
/* Receive FIFO 1 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
- if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
- if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
{
/* Receive FIFO 1 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
- if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)
+ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
{
- if ((msrflags & CAN_MSR_SLAKI) != RESET)
+ if ((msrflags & CAN_MSR_SLAKI) != 0U)
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
/* Sleep Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->SleepCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
- if ((interrupts & CAN_IT_WAKEUP) != RESET)
+ if ((interrupts & CAN_IT_WAKEUP) != 0U)
{
- if ((msrflags & CAN_MSR_WKUI) != RESET)
+ if ((msrflags & CAN_MSR_WKUI) != 0U)
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
/* WakeUp Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->WakeUpFromRxMsgCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
- if ((interrupts & CAN_IT_ERROR) != RESET)
+ if ((interrupts & CAN_IT_ERROR) != 0U)
{
- if ((msrflags & CAN_MSR_ERRI) != RESET)
+ if ((msrflags & CAN_MSR_ERRI) != 0U)
{
/* Check Error Warning Flag */
- if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&
- ((esrflags & CAN_ESR_EWGF) != RESET))
+ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+ ((esrflags & CAN_ESR_EWGF) != 0U))
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
@@ -1554,8 +2015,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Error Passive Flag */
- if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&
- ((esrflags & CAN_ESR_EPVF) != RESET))
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+ ((esrflags & CAN_ESR_EPVF) != 0U))
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
@@ -1564,8 +2025,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Bus-off Flag */
- if (((interrupts & CAN_IT_BUSOFF) != RESET) &&
- ((esrflags & CAN_ESR_BOFF) != RESET))
+ if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+ ((esrflags & CAN_ESR_BOFF) != 0U))
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
@@ -1574,8 +2035,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Last Error Code Flag */
- if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&
- ((esrflags & CAN_ESR_LEC) != RESET))
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+ ((esrflags & CAN_ESR_LEC) != 0U))
{
switch (esrflags & CAN_ESR_LEC)
{
@@ -1623,8 +2084,13 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
hcan->ErrorCode |= errorcode;
/* Call Error callback function */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->ErrorCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1909,21 +2375,25 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check sleep mode acknowledge flag */
- if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
/* Sleep mode is active */
state = HAL_CAN_STATE_SLEEP_ACTIVE;
}
/* Check sleep mode request flag */
- else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
{
/* Sleep mode request is pending */
state = HAL_CAN_STATE_SLEEP_PENDING;
}
+ else
+ {
+ /* Neither sleep mode request nor sleep mode acknowledge */
+ }
}
/* Return CAN state */
@@ -1951,9 +2421,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
{
HAL_StatusTypeDef status = HAL_OK;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Reset CAN error code */
hcan->ErrorCode = 0U;
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cec.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cec.c
index 5b7a171abb583f77019417cd9f39e44d319db6cc..3f3802ed07870e8d51036463ce09d2914f9d11e1 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cec.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cec.c
@@ -42,34 +42,69 @@
[..]
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
-
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
+ @ref HAL_CEC_RegisterRxCpltCallback().
+
+ Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+
+ For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
+ @ref HAL_CEC_UnRegisterRxCpltCallback().
+
+ By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
+ or @ref HAL_CEC_Init() function.
+
+ When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -146,7 +181,7 @@
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
+ if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
@@ -163,40 +198,62 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
- if(hcec->gState == HAL_CEC_STATE_RESET)
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcec->MspInitCallback == NULL)
+ {
+ hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hcec->MspInitCallback(hcec);
+ }
+#else
+ if (hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
- hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
- hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
/* Enable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
@@ -216,7 +273,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if(hcec == NULL)
+ if (hcec == NULL)
{
return HAL_ERROR;
}
@@ -226,31 +283,43 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
hcec->gState = HAL_CEC_STATE_BUSY;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->MspDeInitCallback == NULL)
+ {
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hcec->MspDeInitCallback(hcec);
+
+#else
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Clear Flags */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
/* Disable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
@@ -283,9 +352,9 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
- hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
}
else
{
@@ -314,7 +383,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -328,7 +397,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -336,6 +405,244 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
the HAL_CEC_MspDeInit can be implemented in the user file
*/
}
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User CEC Callback
+ * To be used instead of the weak predefined callback
+ * @param hcec CEC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CEC Callback
+ * CEC callabck is redirected to the weak predefined callback
+ * @param hcec uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Register CEC RX complete Callback
+ * To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @param pCallback pointer to the Rx transfer compelete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+
+/**
+ * @brief UnRegister CEC RX complete Callback
+ * CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -386,13 +693,14 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size)
{
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (hcec->gState == HAL_CEC_STATE_READY)
{
- if((pData == NULL ) && (Size > 0))
+ if ((pData == NULL) && (Size > 0U))
{
return HAL_ERROR;
}
@@ -408,20 +716,22 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = (uint16_t)Size;
/* in case of no payload (Size = 0), sender is only pinging the system;
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
- if (Size == 0)
+ if (Size == 0U)
{
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
+
/* send header block */
- hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
+ hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
+
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcec);
@@ -451,7 +761,7 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
{
hcec->Init.RxBuffer = Rxbuffer;
}
@@ -465,13 +775,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
/* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg = 0;
+ uint32_t reg;
reg = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if((reg & CEC_FLAG_ARBLST) != RESET)
+ if ((reg & CEC_FLAG_ARBLST) != 0U)
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -479,18 +789,19 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXBR) != RESET)
+ if ((reg & CEC_FLAG_RXBR) != 0U)
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
hcec->RxXferSize++;
/* read received byte */
- *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+ *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
+ hcec->Init.RxBuffer++;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXEND) != RESET)
+ if ((reg & CEC_FLAG_RXEND) != 0U)
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -498,33 +809,39 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* Rx process is completed, restore hcec->RxState to Ready */
hcec->RxState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->RxCpltCallback(hcec, hcec->RxXferSize);
+#else
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
- hcec->RxXferSize = 0;
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+ hcec->RxXferSize = 0U;
}
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXBR) != RESET)
+ if ((reg & CEC_FLAG_TXBR) != 0U)
{
- if (hcec->TxXferCount == 0)
+ if (hcec->TxXferCount == 0U)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
}
else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
hcec->TxXferCount--;
}
/* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXEND) != RESET)
- {
+ if ((reg & CEC_FLAG_TXEND) != 0U)
+ {
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
/* Tx process is ended, restore hcec->gState to Ready */
@@ -533,32 +850,48 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->TxCpltCallback(hcec);
+#else
HAL_CEC_TxCpltCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
+ CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = reg;
- __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
+ HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
- if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- hcec->RxXferSize = 0;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
- else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
- {
+ else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+ {
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
- }
-
+ }
+ else
+ {
+ /* Nothing todo*/
+ }
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->ErrorCallback(hcec);
+#else
/* Error Call Back */
HAL_CEC_ErrorCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing todo*/
}
-
}
/**
@@ -566,7 +899,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -596,7 +929,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -618,7 +951,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
[..]
This subsection provides a set of functions allowing to control the CEC.
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
@@ -630,7 +963,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
+ uint32_t temp1, temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
@@ -638,11 +971,11 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
}
/**
-* @brief Return the CEC error code
-* @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * @brief Return the CEC error code
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
-* @retval CEC Error Code
-*/
+ * @retval CEC Error Code
+ */
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
{
return hcec->ErrorCode;
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cortex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cortex.c
index a5cc574c7d33c9cab66ecf0ff16725fba2f53279..5bafc217a5fe2bf8575f4907db48d8f114aaa69a 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cortex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cortex.c
@@ -68,29 +68,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc.c
index ee87f6d7370455f895a104269864b475604646dd..1ba51ada52e9b0fae00507b34283f242aa3b6dee 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc.c
@@ -11,53 +11,33 @@
*
@verbatim
===============================================================================
- ##### CRC How to use this driver #####
+ ##### How to use this driver #####
===============================================================================
[..]
-
- (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-
- (#) Initialize CRC calculator
- (++) specify generating polynomial (IP default or non-default one)
- (++) specify initialization value (IP default or non-default one)
- (++) specify input data format
- (++) specify input or output data inversion mode if any
-
- (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
- input data buffer starting with the previously computed CRC as
- initialization value
-
- (#) Use HAL_CRC_Calculate() function to compute the CRC value of the
- input data buffer starting with the defined initialization value
- (default or non-default) to initiate CRC calculation
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++) specify generating polynomial (peripheral default or non-default one)
+ (++) specify initialization value (peripheral default or non-default one)
+ (++) specify input data format
+ (++) specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -81,17 +61,24 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
-/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -100,8 +87,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
- (+) Initialize the CRC MSP
- (+) DeInitialize CRC MSP
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
@endverbatim
* @{
@@ -116,7 +103,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
@@ -124,7 +111,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
- if(hcrc->State == HAL_CRC_STATE_RESET)
+ if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
@@ -132,22 +119,21 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
HAL_CRC_MspInit(hcrc);
}
- /* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
- if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
- /* initialize IP with default generating polynomial */
+ /* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
- /* initialize CRC IP with generating polynomial defined by user */
- if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ /* initialize CRC peripheral with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -156,7 +142,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
- if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
@@ -193,7 +179,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
@@ -202,7 +188,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
- if(hcrc->State == HAL_CRC_STATE_BUSY)
+ if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
@@ -230,7 +216,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
}
/**
- * @brief Initialize the CRC MSP.
+ * @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
@@ -263,20 +249,20 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
* @}
*/
-/** @defgroup HAL_CRC_Group2 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
@verbatim
- ==============================================================================
+ ===============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
- (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
- or
+ [..] or
- (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
@@ -300,11 +286,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
@@ -313,7 +296,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@@ -321,11 +304,11 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
break;
case CRC_INPUTDATA_FORMAT_BYTES:
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
@@ -334,9 +317,6 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
/* Return the CRC computed value */
return temp;
}
@@ -358,11 +338,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
@@ -375,7 +352,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@@ -384,13 +361,14 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
+
default:
break;
}
@@ -398,13 +376,51 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
/* Return the CRC computed value */
return temp;
}
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRC handle state.
+ * @param hcrc CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ /* Return CRC handle state */
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
@@ -415,32 +431,42 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0; /* input data buffer index */
-
- /* Processing time optimization: 4 bytes are entered in a row with a single word write,
- * last bytes must be carefully fed to the CRC calculator to ensure a correct type
- * handling by the IP */
- for(i = 0; i < (BufferLength/4); i++)
- {
- hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
- }
- /* last bytes specific handling */
- if((BufferLength%4) != 0)
- {
- if(BufferLength%4 == 1)
- {
- *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
- }
- if(BufferLength%4 == 2)
- {
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
- }
- if(BufferLength%4 == 3)
- {
- *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
- *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
- }
- }
+ uint32_t i; /* input data buffer index */
+ uint16_t data;
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 4U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+ ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+ ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
+ (uint32_t)pBuffer[(4U * i) + 3U];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength % 4U) != 0U)
+ {
+ if ((BufferLength % 4U) == 1U)
+ {
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
+ }
+ if ((BufferLength % 4U) == 2U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+ }
+ if ((BufferLength % 4U) == 3U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
+ }
+ }
/* Return the CRC computed value */
return hcrc->Instance->DR;
@@ -456,57 +482,26 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0; /* input data buffer index */
+ uint32_t i; /* input data buffer index */
+ __IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
- * a correct type handling by the IP */
- for(i = 0; i < (BufferLength/2); i++)
+ * a correct type handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 2U); i++)
{
- hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
- if((BufferLength%2) != 0)
+ if ((BufferLength % 2U) != 0U)
{
- *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = pBuffer[2U * i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the CRC state.
- * @param hcrc CRC handle
- * @retval HAL state
- */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
- return hcrc->State;
-}
-
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc_ex.c
index 16d0cac8e6f6049db410f1822247b956c4dc6f2b..004cb3ae67108a72bb7e253b0b34658bd05ead1d 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_crc_ex.c
@@ -3,47 +3,28 @@
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the CRC peripheral:
- * + Initialization/de-initialization functions
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
*
@verbatim
- ==============================================================================
- ##### CRC specific features #####
- ==============================================================================
- [..]
- (#) Polynomial configuration.
- (#) Input data reverse mode.
- (#) Output data reverse mode.
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -55,7 +36,7 @@
* @{
*/
-/** @addtogroup CRCEx
+/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
@@ -67,22 +48,23 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRCEx_Exported_Functions
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
-/** @addtogroup CRCEx_Exported_Functions_Group1
- * @brief Extended CRC features functions
- *
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ *
@verbatim
===============================================================================
- ##### CRC Extended features functions #####
+ ##### Extended configuration functions #####
===============================================================================
- [..]
-This subsection provides function allowing to:
- (+) Set CRC polynomial if different from default one.
+ [..] This section provides functions allowing to:
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
@endverbatim
* @{
@@ -90,23 +72,24 @@ This subsection provides function allowing to:
/**
- * @brief Initializes the CRC polynomial if different from default one.
+ * @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
- * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long)
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
- * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
- * @param PolyLength CRC polynomial length
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
- * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
- * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
- * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
- * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
+ * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
+ * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
+ * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+ * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
- uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
@@ -118,7 +101,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
@@ -127,47 +110,50 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
break;
+
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
- default:
+ default:
+ status = HAL_ERROR;
break;
}
+ if (status == HAL_OK)
+ {
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
- /* set generating polynomial */
- WRITE_REG(hcrc->Instance->POL, Pol);
-
- /* set generating polynomial size */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
-
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
- * @param InputReverseMode Input Data inversion mode
+ * @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
- * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
- * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
+ * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
@@ -190,10 +176,10 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
- * @param OutputReverseMode Output Data inversion mode
+ * @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
- * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
- * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
@@ -237,4 +223,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp.c
index ee149fbf53030da5dee69a60bda9bc0dd9606e6b..e175801472c2462f07d6498303d28a6b09c012c6 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp.c
@@ -5,10 +5,8 @@
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
- * + Initialization and de-initialization functions
- * + AES processing functions
- * + DES processing functions
- * + TDES processing functions
+ * + Initialization, de-initialization, set config and get config functions
+ * + DES/TDES, AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -18,16 +16,16 @@
##### How to use this driver #####
==============================================================================
[..]
- The CRYP HAL driver can be used as follows:
+ The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
- (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
+ (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
+ (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
@@ -37,60 +35,215 @@
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
- (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
- (##) The encryption/decryption key. It's size depends on the algorithm
- used for encryption/decryption
- (##) The initialization vector (counter). It is not used ECB mode.
+ (#)Initialize the CRYP according to the specified parameters :
+ (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+ (##) The key size: 128, 192 or 256.
+ (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
+ (##) The initialization vector (counter). It is not used in ECB mode.
+ (##) The key buffer used for encryption/decryption.
+ (##) The Header used only in AES GCM and CCM Algorithm for authentication.
+ (##) The HeaderSize The size of header buffer in word.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
i.e. they process the data and wait till the processing is finished,
- e.g. HAL_CRYP_AESCBC_Encrypt()
+ e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
i.e. they process the data under interrupt,
- e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+ e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
(##) DMA mode: encryption and decryption APIs are not blocking functions
i.e. the data transfer is ensured by DMA,
- e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+ e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
(#)When the processing function is called at first time after HAL_CRYP_Init()
- the CRYP peripheral is initialized and processes the buffer in input.
- At second call, the processing function performs an append of the already
- processed buffer.
- When a new data block is to be processed, call HAL_CRYP_Init() then the
- processing function.
+ the CRYP peripheral is configured and processes the buffer in input.
+ At second call, no need to Initialize the CRYP, user have to get current configuration via
+ HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
+ new parametres, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ [..]
+ The cryptographic processor supports following standards:
+ (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
+ (##)64-bit data block processing
+ (##) chaining modes supported :
+ (+++) Electronic Code Book(ECB)
+ (+++) Cipher Block Chaining (CBC)
+ (##) keys length supported :64-bit, 128-bit and 192-bit.
+ (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
+ (##)128-bit data block processing
+ (##) chaining modes supported :
+ (+++) Electronic Code Book(ECB)
+ (+++) Cipher Block Chaining (CBC)
+ (+++) Counter mode (CTR)
+ (+++) Galois/counter mode (GCM/GMAC)
+ (+++) Counter with Cipher Block Chaining-Message(CCM)
+ (##) keys length Supported :
+ (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
+ (+++) for TinyAES IP: 128-bit and 256-bit
+
+ [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
+ (#) Algorithm supported :
+ (##) Galois/counter mode (GCM)
+ (##) Galois message authentication code (GMAC) :is exactly the same as
+ GCM algorithm composed only by an header.
+ (#) Four phases are performed in GCM :
+ (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+ (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+ computation only.
+ (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+ encryption + data XORing. It works in a similar way for ciphertext (C).
+ (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+ (#) structure of message construction in GCM is defined as below :
+ (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
+ (##) The authenticated header A (also knows as Additional Authentication Data AAD)
+ this part of the message is only authenticated, not encrypted.
+ (##) The plaintext message P is both authenticated and encrypted as ciphertext.
+ GCM standard specifies that ciphertext has same bit length as the plaintext.
+ (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
+ (on 64 bits)
+
+ [..] This section describe The AES Counter with Cipher Block Chaining-Message
+ Authentication Code (CCM) supported by both CRYP1 IP:
+ (#) Specific parameters for CCM :
+
+ (##) B0 block : According to NIST Special Publication 800-38C,
+ The first block B0 is formatted as follows, where l(m) is encoded in
+ most-significant-byte first order(see below table 3)
+
+ (+++) Q: a bit string representation of the octet length of P (plaintext)
+ (+++) q The octet length of the binary representation of the octet length of the payload
+ (+++) A nonce (N), n The octet length of the where n+q=15.
+ (+++) Flags: most significant octet containing four flags for control information,
+ (+++) t The octet length of the MAC.
+ (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
+ the associated data length expressed in bytes (a) defined as below:
+ (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
+ (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
+ (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+ (##) CTRx block : control blocks
+ (+++) Generation of CTR1 from first block B0 information :
+ equal to B0 with first 5 bits zeroed and most significant bits storing octet
+ length of P also zeroed, then incremented by one ( see below Table 4)
+ (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
+
+ (#) Four phases are performed in CCM for CRYP1 IP:
+ (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+ (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+ computation only.
+ (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+ encryption + data XORing. It works in a similar way for ciphertext (C).
+ (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+
+ By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
+ or @ref HAL_CRYP_Init() function.
+
+ When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ Table 1. Initial Counter Block (ICB)
+ +-------------------------------------------------------+
+ | Initialization vector (IV) | Counter |
+ |----------------|----------------|-----------|---------|
+ 127 95 63 31 0
+
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
+
+ Table 2. GCM last block definition
+
+ +-------------------------------------------------------------------+
+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
+ |-----------|--------------------|-----------|----------------------|
+ | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
+ |-----------|--------------------|-----------|----------------------|
+
+ Table 3. B0 block
+ Octet Number Contents
+ ------------ ---------
+ 0 Flags
+ 1 ... 15-q Nonce N
+ 16-q ... 15 Q
+
+ the Flags field is formatted as follows:
+
+ Bit Number Contents
+ ---------- ----------------------
+ 7 Reserved (always zero)
+ 6 Adata
+ 5 ... 3 (t-2)/2
+ 2 ... 0 [q-1]3
+
+ Table 4. CTRx block
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
+ bit 0 that is set to 1
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -98,592 +251,428 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-#if defined (CRYP)
-
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+
+#if defined (AES) || defined (CRYP)
+
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYP_Private_define
+/** @addtogroup CRYP_Private_Defines
* @{
*/
-#define CRYP_TIMEOUT_VALUE 1
+#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
+
+#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
+#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
+
+#if defined(AES)
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#else /* CRYP */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
+#endif /* End CRYP or AES */
+
+ /* CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0 0x07FFFFFFU
+#define CRYP_CCM_CTR1_1 0xFFFFFF00U
+#define CRYP_CCM_CTR1_2 0x00000001U
+
+
/**
* @}
*/
+
/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions_prototypes
+/** @addtogroup CRYP_Private_Macros
* @{
*/
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+
+#if defined(CRYP)
+
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+
+#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+
+#else /*AES*/
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+#endif /* End AES or CRYP*/
+
+
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions
+/* Private struct -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions_prototypes
* @{
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
+#if defined (CRYP)
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
- /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#else /*AES*/
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#endif /* End CRYP or AES */
/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @}
*/
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+/* Exported functions ---------------------------------------------------------*/
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+ * @{
+ */
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ========================================================================================
+ ##### Initialization, de-initialization and Set and Get configuration functions #####
+ ========================================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP
+ (+) DeInitialize the CRYP
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize the CRYP MSP
+ (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
+ Parameters which are configured in This section are :
+ (+) Key size
+ (+) Data Type : 32,16, 8 or 1bit
+ (+) AlgoMode :
+ - for CRYP1 IP :
+ ECB and CBC in DES/TDES Standard
+ ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+ - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
+ (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key Pointer to Key buffer
- * @param KeySize Size of Key
- * @retval None
+@endverbatim
+ * @{
*/
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param InitVector Pointer to InitVector/InitCounter buffer
- * @param IVSize Size of the InitVector/InitCounter
- * @retval None
+ * @retval HAL status
*/
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
- uint32_t ivaddr = (uint32_t)InitVector;
-
- switch(IVSize)
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
{
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
- break;
- /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- default:
- break;
+ return HAL_ERROR;
}
-}
-
-/**
- * @brief Process Data: Writes Input data in polling mode and read the output data
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer
- * @param Ilength Length of the Input buffer, must be a multiple of 16.
- * @param Output Pointer to the returned buffer
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+ assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
- for(i=0; (i < Ilength); i+=16)
+ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
{
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
- /* Get tick */
- tickstart = HAL_GetTick();
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ if(hcryp->MspInitCallback == NULL)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Init the low level hardware */
+ hcryp->MspInitCallback(hcryp);
+ }
+#else
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
}
- /* Return function status */
- return HAL_OK;
-}
+ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-/**
- * @brief Process Data: Write Input data in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer
- * @param Ilength Length of the Input buffer, must be a multiple of 8
- * @param Output Pointer to the returned buffer
- * @param Timeout Specify Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
+ /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type and Algorithm */
+#if defined (CRYP)
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
- for(i=0; (i < Ilength); i+=8)
- {
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
+#else /*AES*/
- /* Get tick */
- tickstart = HAL_GetTick();
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+#endif /* End AES or CRYP*/
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief De-Initializes the CRYP peripheral.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param inputaddr address of the Input buffer
- * @param Size Size of the Input buffer, must be a multiple of 16.
- * @param outputaddr address of the Output buffer
- * @retval None
- */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+ hcryp->CrypHeaderCount =0;
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable In DMA request */
- hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
+ if(hcryp->MspDeInitCallback == NULL)
+ {
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
+ }
+ /* DeInit the low level hardware */
+ hcryp->MspDeInitCallback(hcryp);
- /* Enable Out DMA request */
- hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+#else
-}
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
-/**
- * @brief Sets the CRYP peripheral in DES ECB mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- /* Set the key */
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Sets the CRYP peripheral in DES CBC mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Configure the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
* the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
+ * @retval HAL status
*/
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Check the CRYP handle allocation */
+ if((hcryp == NULL)|| (pConf == NULL) )
{
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
+ return HAL_ERROR;
+ }
- /* Set the key */
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
+ assert_param(IS_CRYP_DATATYPE(pConf->DataType));
+ assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
+ /* Set CRYP parameters */
+ hcryp->Init.DataType = pConf->DataType;
+ hcryp->Init.pKey = pConf->pKey;
+ hcryp->Init.Algorithm = pConf->Algorithm;
+ hcryp->Init.KeySize = pConf->KeySize;
+ hcryp->Init.pInitVect = pConf->pInitVect;
+ hcryp->Init.Header = pConf->Header;
+ hcryp->Init.HeaderSize = pConf->HeaderSize;
+ hcryp->Init.B0 = pConf->B0;
+ hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+
+ /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
+#if defined (CRYP)
-/**
- * @brief Sets the CRYP peripheral in TDES ECB mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+#else /*AES*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /*clear error flags*/
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
+#endif /* End AES or CRYP */
-/**
- * @brief Sets the CRYP peripheral in TDES CBC mode
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Return function status */
+ return HAL_OK;
}
-}
-
-/**
- * @}
- */
-
- /* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions
- * @{
- */
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP according to the specified parameters
- in the CRYP_InitTypeDef and creates the associated handle
- (+) DeInitialize the CRYP peripheral
- (+) Initialize the CRYP MSP
- (+) DeInitialize CRYP MSP
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CRYP according to the specified
- * parameters in the CRYP_InitTypeDef and creates the associated handle.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ else
{
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
- if(hcryp->State == HAL_CRYP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcryp->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
}
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the key size and data type*/
- CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @brief DeInitializes the CRYP peripheral.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Get CRYP Configuration parameters in associated handle.
+ * @param pConf: pointer to a CRYP_ConfigTypeDef structure
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
{
/* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ if((hcryp == NULL)|| (pConf == NULL) )
{
return HAL_ERROR;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE(hcryp);
+ /* Get CRYP parameters */
+ pConf->DataType = hcryp->Init.DataType;
+ pConf->pKey = hcryp->Init.pKey;
+ pConf->Algorithm = hcryp->Init.Algorithm;
+ pConf->KeySize = hcryp->Init.KeySize ;
+ pConf->pInitVect = hcryp->Init.pInitVect;
+ pConf->Header = hcryp->Init.Header ;
+ pConf->HeaderSize = hcryp->Init.HeaderSize;
+ pConf->B0 = hcryp->Init.B0;
+ pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Return function status */
- return HAL_OK;
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
}
-
/**
* @brief Initializes the CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
@@ -699,7 +688,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
/**
* @brief DeInitializes CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
@@ -713,2033 +702,2892 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
*/
}
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User CRYP Callback
+ * To be used instead of the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcryp);
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CRYP Callback
+ * CRYP callback is redirected to the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcryp);
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
* @brief processing functions.
*
@verbatim
==============================================================================
- ##### AES processing functions #####
+ ##### Encrypt Decrypt functions #####
==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES-128/192/256 using chaining modes
- (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
+ [..] This section provides API allowing to Encrypt/Decrypt Data following
+ Standard DES/TDES or AES, and Algorithm configured by the user:
+ (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
+ - Electronic Code Book(ECB)
+ - Cipher Block Chaining (CBC)
+ (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
+ - Electronic Code Book(ECB)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Galois/counter mode (GCM)
+ - Counter with Cipher Block Chaining-Message(CCM)
[..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+ (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+ (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(ciphertext)
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ uint32_t algo;
+ HAL_StatusTypeDef status;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+#if defined (CRYP)
+ /* Set Encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch(algo)
{
- return HAL_TIMEOUT;
- }
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Statrt DES/TDES encryption process */
+ status = CRYP_TDES_Process(hcryp,Timeout);
+ break;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+ case CRYP_AES_GCM:
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ break;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ case CRYP_AES_CCM:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp,Timeout);
+ break;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#else /*AES*/
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ switch(algo)
+ {
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ case CRYP_AES_GCM_GMAC:
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process (hcryp,Timeout) ;
+ break;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ case CRYP_AES_CCM:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp,Timeout);
+ break;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
}
+#endif /*end AES or CRYP */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
}
-
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(plaintext)
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ HAL_StatusTypeDef status;
+ uint32_t algo;
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+#if defined (CRYP)
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch(algo)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
}
- }
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Start DES/TDES decryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ break;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
- /* Return function status */
- return HAL_OK;
-}
+ case CRYP_AES_GCM:
-/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process (hcryp, Timeout) ;
+ break;
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ case CRYP_AES_CCM:
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+#else /*AES*/
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ switch(algo)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ case CRYP_AES_GCM_GMAC:
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process (hcryp, Timeout) ;
+ break;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ case CRYP_AES_CCM:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
}
+#endif /* End AES or CRYP */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in interrupt mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word
+ * @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Change the CRYP state */
+ /* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* algo get algorithm selected */
+ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ switch(algo)
{
- return HAL_TIMEOUT;
- }
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Return function status */
- return HAL_OK;
-}
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Enable CRYP to start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+ break;
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ case CRYP_AES_GCM:
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+ case CRYP_AES_CCM:
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+#else /* AES */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /*end AES or CRYP*/
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in itnterrupt mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ hcryp->Size = Size;
+ }
+
+#if defined (CRYP)
+
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP and start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCMdecryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+#else /*AES*/
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in DMA mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ hcryp->Size = Size;
+ }
+
+#if defined (CRYP)
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+#else /*AES*/
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ }
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in DMA mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word
+ * @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t tickstart = 0;
-
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
- /* Change the CRYP state */
+ /* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#if defined (CRYP)
+
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- return HAL_TIMEOUT;
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
}
- }
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+#else /*AES*/
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYP IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYP IRQ handler and callback functions.
+ (+) HAL_CRYP_IRQHandler CRYP interrupt request
+ (+) HAL_CRYP_InCpltCallback input data transfer complete callback
+ (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
+ (+) HAL_CRYP_ErrorCallback CRYP error callback
+ (+) HAL_CRYP_GetState return the CRYP state
+ (+) HAL_CRYP_GetError return the CRYP error code
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles cryptographic interrupt request.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
+#if defined (CRYP)
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U))
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ CRYP_TDES_IT(hcryp); /* DES or TDES*/
+ }
+ else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ {
+ CRYP_AES_IT(hcryp); /*AES*/
+ }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
{
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ else
+ {
+ /* Nothing to do */
+ }
+ }
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+#else /*AES*/
+ if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U))
+ {
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
}
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ else if(hcryp->Init.Algorithm == CRYP_AES_CCM)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* if header phase */
+ if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount )
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else /* AES Algorithm ECB,CBC or CTR*/
+ {
+ CRYP_AES_IT(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ /* Check if error occurred */
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ /* If write Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
+ }
+ /* If read Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
+#endif /* End AES or CRYP */
+}
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief Return the CRYP error code.
+ * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for the CRYP IP
+ * @retval CRYP error code
+ */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->ErrorCode;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
+ * @brief Returns the CRYP state.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval HAL state
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ return hcryp->State;
+}
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+/**
+ * @brief Input FIFO transfer completed callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_InCpltCallback could be implemented in the user file
+ */
+}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+/**
+ * @brief Output FIFO transfer completed callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ */
+}
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+/**
+ * @brief CRYP error callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ #if defined (CRYP)
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+/**
+ * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout: specify Timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t temp; /* Temporary CrypOutBuff */
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
+ /*Start processing*/
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Temporary CrypInCount Value */
+ incount = hcryp->CrypInCount;
+ /* Write plain data and get cipher data */
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
+
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & errorCode*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
}
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
}
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
+ * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval none
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t temp; /* Temporary CrypOutBuff */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Write input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
}
else
{
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
+#endif /* CRYP */
+
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Write plain Ddta and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ if(hcryp->Size != 0U)
+ {
+#if defined (AES)
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+#else /* CRYP */
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+#endif /* End AES or CRYP */
}
else
{
- return HAL_ERROR;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pPlainData Pointer to the plaintext buffer
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & Key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Wait for BUSY flag to be raised */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_TIMEOUT;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#endif /* End AES or CRYP */
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Return function status */
- return HAL_OK;
- }
- else
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
{
- return HAL_ERROR;
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
}
-}
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ count-- ;
+ if(count == 0U)
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ /* Set decryption & key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Wait for BUSY flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
+ }
- /* Return function status */
- return HAL_OK;
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+ if(hcryp->Size != 0U)
+ {
+
+#if defined (AES)
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+#else /* CRYP */
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#endif /* End AES or CRYP */
}
else
{
- return HAL_ERROR;
+ /* Process locked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
}
-}
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Wait for BUSY flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
- /* Return function status */
- return HAL_OK;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if(hcryp->Size != 0U)
+ {
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
else
{
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @}
+ * @brief DMA CRYP input data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### DES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using DES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using ECB or CBC chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+#if defined (CRYP)
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-@endverbatim
- * @{
- */
+#else /* AES */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
+ if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+#endif /* End AES or CRYP */
+
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @brief DMA CRYP output data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Disable the DMA transfer for output FIFO request by resetting
+ the DOEN bit in the DMACR register */
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+ if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
+ {
+ /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_DISABLE(hcryp);
+ }
+#else /* AES */
+
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
+
+ if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
{
- return HAL_TIMEOUT;
+ /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_DISABLE(hcryp);
}
+#endif /* End AES or CRYP */
- /* Change the CRYP state */
+ /* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
+ /* Call output data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Change the CRYP peripheral state */
+ hcryp->State= HAL_CRYP_STATE_READY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+#if defined (AES)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* AES */
- /* Return function status */
- return HAL_OK;
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @param inputaddr: address of the input buffer
+ * @param Size: size of the input buffer, must be a multiple of 16.
+ * @param outputaddr: address of the output buffer
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+
+ /* Set the DMA output error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0);
+#if defined (CRYP)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Enable the input DMA Stream */
+ if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
{
- return HAL_TIMEOUT;
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+ /* Enable the output DMA Stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable In/Out DMA request */
+ hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#else /* AES */
- /* Return function status */
- return HAL_OK;
+ if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ {
+ /* Enable CRYP (not allowed in GCM & CCM)*/
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable the DMA output stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Enable In and Out DMA requests */
+ if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
+ /* Enable only In DMA requests for CCM*/
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN ));
+ }
+ else
+ {
+ /* Enable In and Out DMA requests */
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+ }
+#endif /* End AES or CRYP */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Process Data: Write Input data in polling mode and used in AES functions.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @param Timeout: Specify Timeout value
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ uint32_t temp; /* Temporary CrypOutBuff */
+#if defined (CRYP)
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /*Temporary CrypOutCount Value*/
+ incount = hcryp->CrypInCount;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
{
- return HAL_TIMEOUT;
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Return function status */
- return HAL_OK;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ }
+
+#else /* AES */
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+
+#endif /* End AES or CRYP */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @brief Handle CRYP block input/output data handling under interruption.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t temp; /* Temporary CrypOutBuff */
+#if defined (CRYP)
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (CRYP)
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /*Temporary CrypOutCount Value*/
+ incount = hcryp->CrypInCount;
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0);
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
+#else /*AES*/
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+
+ if(hcryp->CrypOutCount == (hcryp->Size/4U))
{
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable Computation Complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- }
+ else
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ if(hcryp->CrypInCount == (hcryp->Size/4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+#endif /* End AES or CRYP */
- /* Return function status */
- return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Writes Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
+ * @param KeySize: Size of Key
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0);
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
+#if defined (CRYP)
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ switch(KeySize)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ break;
+ default:
+ break;
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+#else /*AES*/
+ switch(KeySize)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5);
+ hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6);
+ hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ break;
+ default:
+ break;
}
-
- /* Return function status */
- return HAL_OK;
+#endif /* End AES or CRYP */
}
+
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart;
+ uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /****************************** Init phase **********************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+#if defined(CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+
+#else /* AES */
+ /* Workaround 1 : only AES.
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Return function status */
- return HAL_OK;
-}
+#endif /* End AES or CRYP */
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /************************ Header phase *************************************/
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ return HAL_ERROR;
+ }
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /*************************Payload phase ************************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#if defined(CRYP)
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Return function status */
- return HAL_OK;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+#endif /* End AES or CRYP */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ /* Write input data and get output Data */
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
+ 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp,Timeout);
}
/* Return function status */
@@ -2747,2416 +3595,2624 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif /* AES */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount =0U;
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /******************************* Init phase *********************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_ERROR;
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
-}
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+#else /* AES */
+
+ /* Workaround 1 : only AES
+ Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0);
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+#endif /* End AES or CRYP */
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /***************************** Header phase *********************************/
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
+#if defined(CRYP)
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+#else /* AES */
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Return function status */
- return HAL_OK;
- }
- else
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
{
- return HAL_ERROR;
- }
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Write the payload Input block in the IN FIFO */
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(hcryp->CrypInCount == ( hcryp->Size/4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Workaround not implemented*/
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U- (uint32_t)(hcryp->Size);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((hcryp->Init.HeaderSize) < 4U)
+ {
+ for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Return function status */
- return HAL_OK;
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else if ((hcryp->Init.HeaderSize) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
}
else
{
- return HAL_ERROR;
+ /* Nothing to do */
}
-}
-/**
- * @}
- */
+#endif /* End AES or CRYP */
-/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### TDES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
- (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Return function status */
+ return HAL_OK;
+}
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ __IO uint32_t count = 0U;
+ uint32_t wordsize;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0);
+ /*************************** Init phase ************************************/
- /* Enable CRYP */
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Return function status */
- return HAL_OK;
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#else /* AES */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /*Workaround 1 : only AES
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Enable CRYP */
+ /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Cypher Data and Get Plain Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0);
+#endif /* End AES or CRYP */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /************************ Header phase *************************************/
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /************************ Payload phase ************************************/
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#endif /* CRYP */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Write Cypher Data and Get Plain Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(hcryp->Size != 0U)
{
- return HAL_TIMEOUT;
- }
+ /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
+ {
+ wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ }
+ else
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
/* Return function status */
return HAL_OK;
}
+
/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption processing in polling mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart;
+ uint32_t wordsize= (uint32_t)(hcryp->Size)/4U;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+#endif /* AES */
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /********************** Init phase ******************************************/
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0);
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Return function status */
- return HAL_OK;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
+ /*Wait for the CRYPEN bit to be cleared*/
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+#else /* AES */
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+
+ /* wait until the end of computation */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call the Output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->Init.HeaderSize != 0U)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ /* Then the payload: cleartext payload (not the ciphertext payload).
+ Write input Data, no output Data to get */
+ if (hcryp->Size != 0U)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
+ }
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
}
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
+ if ((hcryp->Size % 16U) != 0U)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ loopcounter++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
}
}
+#endif /* End AES or CRYP */
- /* Return function status */
- return HAL_OK;
-}
+#if defined(CRYP)
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /************************* Header phase *************************************/
+ /* Header block(B1) : associated data length expressed in bytes concatenated
+ with Associated Data (A)*/
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ return HAL_ERROR;
+ }
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /********************** Payload phase ***************************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ /* Write input data and get output data */
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
+ 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp,Timeout);
}
+#endif /* CRYP */
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption process in interrupt mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+#if defined(CRYP)
+ __IO uint32_t count = 0U;
+#endif /* CRYP */
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /************ Init phase ************/
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Return function status */
- return HAL_OK;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
- hcryp->pCrypInBuffPtr += 8;
- hcryp->CrypInCount -= 8;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
- hcryp->pCrypOutBuffPtr += 8;
- hcryp->CrypOutCount -= 8;
- if(hcryp->CrypOutCount == 0)
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ }
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
+ /* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
}
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
- /* Return function status */
- return HAL_OK;
-}
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+#else /* AES */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0);
+ /* configured mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+#endif /* End AES or CRYP */
+
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption process in DMA mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t wordsize;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /************************** Init phase **************************************/
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0);
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Return function status */
- return HAL_OK;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
}
else
{
- return HAL_ERROR;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
}
-}
-
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+#else /* AES */
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* configured CCM chaining mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+
+ /* wait until the end of computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ count-- ;
+ if(count == 0U)
+{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+}
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+#endif /* AES */
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /********************* Header phase *****************************************/
- /* Return function status */
- return HAL_OK;
- }
- else
+ if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
-}
-/**
- * @}
- */
+ /******************** Payload phase *****************************************/
-/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
- * @brief DMA callback functions.
- *
-@verbatim
- ==============================================================================
- ##### DMA callback functions #####
- ==============================================================================
- [..] This section provides DMA callback functions:
- (+) DMA Input data transfer complete
- (+) DMA Output data transfer complete
- (+) DMA error
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-@endverbatim
- * @{
- */
+#if defined(CRYP)
-/**
- * @brief Input FIFO transfer completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
- */
-}
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-/**
- * @brief Output FIFO transfer completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+#endif /* CRYP */
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
- */
+ if(hcryp->Size != 0U)
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else
+ {
+ wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ }
+ else /*Size = 0*/
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief CRYP error callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Sets the payload phase in iterrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @retval None
+ * @retval state
*/
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ uint32_t loopcounter;
+ uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ #if defined(AES)
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif /* AES */
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
- */
-}
+ /***************************** Payload phase *******************************/
-/**
- * @}
- */
+#if defined(CRYP)
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
-/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
- * @brief CRYP IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### CRYP IRQ handler management #####
- ==============================================================================
-[..] This section provides CRYP IRQ handler function.
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
-@endverbatim
- * @{
- */
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
-/**
- * @brief This function handles CRYP interrupt request.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+ else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
{
- case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
- HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
- HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ if(hcryp->CrypOutCount < (hcryp->Size/4U))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
- HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
- HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
- HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
- HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else if ((hcryp->Size %16U )!= 0U)
+ {
+ /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
- case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
- HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
- case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
- HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
- case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
- HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
- HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer */
+ temp= hcryp->Instance->DOUT;
- case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
- HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /*get CrypOutBuff from temporary buffer */
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
+ hcryp->CrypOutCount++;
+ }
+ }
+ if(hcryp->CrypOutCount >= (hcryp->Size/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
- case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
- HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
- HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
- HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- default:
- break;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CRYP state.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL state
- */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
- return hcryp->State;
-}
-
-/**
- * @}
- */
+ else
+ {
+ /* Nothing to do */
+ }
+#else /* AES */
-/**
- * @}
- */
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* CRYP */
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
-#if defined (AES)
+ if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) )
+ {
+ /* Disable computation complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/** @addtogroup STM32F7xx_HAL_Driver
- * @{
- */
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
-/** @defgroup AES AES
- * @brief AES HAL module driver.
- * @{
- */
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Last block of payload < 128bit*/
+ {
+ /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
+ generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private functions --------------------------------------------------------*/
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+#endif /* AES */
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
+}
-static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
/**
- * @}
+ * @brief Sets the header phase in polling mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @param Timeout: Timeout value
+ * @retval state
*/
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t loopcounter;
-/* Exported functions ---------------------------------------------------------*/
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
+ if((hcryp->Init.HeaderSize != 0U))
+ {
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and deinitialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP according to the specified parameters
- in the CRYP_InitTypeDef and creates the associated handle
- (+) DeInitialize the CRYP peripheral
- (+) Initialize the CRYP MSP (MCU Specific Package)
- (+) De-Initialize the CRYP MSP
+#if defined(CRYP)
- [..]
- (@) Specific care must be taken to format the key and the Initialization Vector IV!
-
- [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
- b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
- (+) as a sequence of words where the MSB word comes first (occupies the
- lowest memory address)
- (+) where each word is byte-swapped:
- (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
- (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
- (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
- (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24
- [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
- The 4 32-bit words that make the key must be stored as follows in MCU memory:
- (+) address n+0 : 0x B12 B13 B14 B15
- (+) address n+4 : 0x B8 B9 B10 B11
- (+) address n+8 : 0x B4 B5 B6 B7
- (+) address n+C : 0x B0 B1 B2 B3
- [..] which leads to the expected setting
- (+) AES_KEYR3 = 0x B15 B14 B13 B12
- (+) AES_KEYR2 = 0x B11 B10 B9 B8
- (+) AES_KEYR1 = 0x B7 B6 B5 B4
- (+) AES_KEYR0 = 0x B3 B2 B1 B0
-
- [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
- The 8 32-bit words that make the key must be stored as follows in MCU memory:
- (+) address n+00 : 0x B28 B29 B30 B31
- (+) address n+04 : 0x B24 B25 B26 B27
- (+) address n+08 : 0x B20 B21 B22 B23
- (+) address n+0C : 0x B16 B17 B18 B19
- (+) address n+10 : 0x B12 B13 B14 B15
- (+) address n+14 : 0x B8 B9 B10 B11
- (+) address n+18 : 0x B4 B5 B6 B7
- (+) address n+1C : 0x B0 B1 B2 B3
- [..] which leads to the expected setting
- (+) AES_KEYR7 = 0x B31 B30 B29 B28
- (+) AES_KEYR6 = 0x B27 B26 B25 B24
- (+) AES_KEYR5 = 0x B23 B22 B21 B20
- (+) AES_KEYR4 = 0x B19 B18 B17 B16
- (+) AES_KEYR3 = 0x B15 B14 B13 B12
- (+) AES_KEYR2 = 0x B11 B10 B9 B8
- (+) AES_KEYR1 = 0x B7 B6 B5 B4
- (+) AES_KEYR0 = 0x B3 B2 B1 B0
-
- [..] Initialization Vector IV (4 32-bit words) format must follow the same as
- that of a 128-bit long key.
-
- [..]
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-@endverbatim
- * @{
- */
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
-/**
- * @brief Initialize the CRYP according to the specified
- * parameters in the CRYP_InitTypeDef and initialize the associated handle.
- * @note Specific care must be taken to format the key and the Initialization Vector IV
- * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations
- * hereabove.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Check the instance */
- assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Check the parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
- assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));
- /* ChainingMode parameter is irrelevant when mode is set to Key derivation */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));
- }
- assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));
-
- /*========================================================*/
- /* Check the proper operating/chaining modes combinations */
- /*========================================================*/
- /* Check the proper chaining when the operating mode is key derivation and decryption */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
- ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)))
-#else
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
- ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
-#endif
- {
- return HAL_ERROR;
- }
- /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
- {
- return HAL_ERROR;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /*================*/
- /* Initialization */
- /*================*/
- /* Initialization start */
- if(hcryp->State == HAL_CRYP_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcryp->Lock = HAL_UNLOCKED;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for CCF IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
- }
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Wait until the complete message has been processed */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /*=============================================================*/
- /* AES initialization common to all operating modes */
- /*=============================================================*/
- /* Set the Key size selection */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
- /* Set the default CRYP phase when this parameter is not used.
- Phase is updated below in case of GCM/GMAC/CMAC(/CCM) setting. */
- hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
+#else /* AES */
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /*=============================================================*/
- /* Carry on the initialization based on the AES operating mode */
- /*=============================================================*/
- /* Key derivation */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Configure the Key registers */
- if (CRYP_SetKey(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
- else
- /* Encryption / Decryption (with or without key derivation) / authentication */
- {
- /* Set data type, operating and chaining modes.
- In case of GCM or GMAC, data type is forced to 0b00 */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
}
- else
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
{
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
- }
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Specify the encryption/decryption phase in case of Galois counter mode (GCM),
- Galois message authentication code (GMAC), cipher message authentication code (CMAC)
- or Counter with Cipher Mode (CCM) when applicable */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
- hcryp->Phase = HAL_CRYP_PHASE_START;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
}
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Configure the Key registers if no need to bypass this step */
- if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)
- {
- if (CRYP_SetKey(hcryp) != HAL_OK)
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
{
- return HAL_ERROR;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /*Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
}
- }
- /* If applicable, configure the Initialization Vector */
- if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)
- {
- if (CRYP_SetInitVector(hcryp) != HAL_OK)
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
+#endif /* End AES or CRYP */
}
+ else
+ {
+#if defined(AES)
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-#if defined(AES_CR_NPBLB)
- /* Clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
-
- /* Reset ErrorCode field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
- /* Reset Mode suspension request */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+#endif /* AES */
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief DeInitialize the CRYP peripheral.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
+ * @brief Sets the header phase when using DMA in process
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0;
- hcryp->CrypOutCount = 0;
-
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE();
+ __IO uint32_t count = 0U;
+ uint32_t loopcounter;
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if((hcryp->Init.HeaderSize != 0U))
+ {
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
+#if defined(CRYP)
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Return function status */
- return HAL_OK;
-}
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
-/**
- * @brief Initialize the CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitialize CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
- * @brief Processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES algorithm in different chaining modes
- (+) Decrypt cyphertext using AES algorithm in different chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-@endverbatim
- * @{
- */
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ /* Wait until the complete message has been processed */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+#else /* AES */
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-/**
- * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-/**
- * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else
{
- return HAL_ERROR;
- }
+#if defined(AES)
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
-}
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+#endif /* AES */
}
-
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
+ * @brief Sets the header phase in interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
-}
+ uint32_t loopcounter;
+#if defined(AES)
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif
+ /***************************** Header phase *********************************/
-/**
- * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+#if defined(CRYP)
+ if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer.
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
+ else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
-
-/**
- * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ { /* HeaderSize %4, no padding */
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else
{
- return HAL_ERROR;
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
}
+#else /* AES */
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
-
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
- return HAL_ERROR;
- }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
+ /* Payload phase not supported in CCM AES2 */
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+ }
+ if(hcryp->Init.Algorithm == CRYP_AES_CCM)
+ {
+ /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-/**
- * @brief Encrypt pPlainData in AES ECB encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U))
+ {
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 4 words : first block is the last block*/
+ {
+ /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
+ generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
-/**
- * @brief Encrypt pPlainData in AES CBC encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
{
- return HAL_ERROR;
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
{
- return HAL_ERROR;
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
-
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+#endif /* End AES or CRYP */
}
+
/**
- * @brief Encrypt pPlainData in AES CTR encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Workaround used for GCM/CCM mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer.
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
+ * @param Timeout: specify Timeout value
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#if defined(CRYP)
+ uint32_t iv1temp;
+ uint32_t temp[4] = {0};
+ uint32_t temp2[4]= {0};
+#endif /* CRYP */
+ uint32_t intermediate_data[4]={0};
+ uint32_t index;
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ { lastwordsize = (16U-npblb)/4U;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ else
+ {lastwordsize = ((16U-npblb)/4U) +1U;
}
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+#if defined(CRYP)
-/**
- * @brief Decrypt pCypherData in AES CBC decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ /* Workaround 2, case GCM encryption */
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM)
{
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {/*Workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+ /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
+ by 1 and reinsert the result in CRYP_IV1R register*/
+ hcryp->Instance->IV1RR = 0x5U;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Enable CRYP to start the final phase */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(index=0; index < lastwordsize; index ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(index < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0U;
+ index++;
+ }
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for(index=0U; index< 4U;index++)
+ {
+ /* Read the output block from the output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUT;
-/**
- * @}
- */
+ /* Intermediate data buffer to be used in for the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+ }
-/** @defgroup CRYP_Exported_Functions_Group3 Callback functions
- * @brief Callback functions.
- *
-@verbatim
- ==============================================================================
- ##### Callback functions #####
- ==============================================================================
- [..] This section provides Interruption and DMA callback functions:
- (+) DMA Input data transfer complete
- (+) DMA Output data transfer complete
- (+) DMA or Interrupt error
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /*workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
+ /* Change the AES mode to GCM mode and Select Final phase */
+ /* configured CHMOD GCM */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
-@endverbatim
- * @{
- */
+ /* configured final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-/**
- * @brief CRYP error callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ for (index=0U; index < lastwordsize; index ++)
+ {
+ /*Write the intermediate_data in the IN FIFO */
+ hcryp->Instance->DIN=intermediate_data[index];
+ }
+ while(index < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ index++;
+ }
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_ErrorCallback can be implemented in the user file
- */
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Input DMA transfer complete callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_InCpltCallback can be implemented in the user file
- */
-}
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for( index=0U; index< 4U;index++)
+ {
+ intermediate_data[index]=hcryp->Instance->DOUT;
+ }
+ }
+ }
+ } /* End of GCM encryption */
+ else{ /* Workaround 2, case CCM decryption, in order to properly compute
+ authentication tags while doing a CCM decryption with the last block
+ of payload size inferior to 128 bits*/
-/**
- * @brief Output DMA transfer complete callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ iv1temp = hcryp->Instance->CSGCMCCM7R;
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_OutCpltCallback can be implemented in the user file
- */
-}
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @}
- */
+ temp[0]= hcryp->Instance->CSGCMCCM0R;
+ temp[1]= hcryp->Instance->CSGCMCCM1R;
+ temp[2]= hcryp->Instance->CSGCMCCM2R;
+ temp[3]= hcryp->Instance->CSGCMCCM3R;
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
- * @brief AES IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### AES IRQ handler management #####
- ==============================================================================
-[..] This section provides AES IRQ handler function.
+ hcryp->Instance->IV1RR= iv1temp;
-@endverbatim
- * @{
- */
+ /* Configured CHMOD CTR */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-/**
- * @brief Handle AES interrupt request.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- /* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)
- {
- /* If Write Error occurred */
- if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)
+ /* Enable CRYP to start the final phase */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(index=0; index < lastwordsize; index ++)
{
- hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- /* If Read Error occurred */
- if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)
+ while(index < 4U)
{
- hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0U;
+ index++;
}
-
- /* If an error has been reported */
- if (hcryp->State == HAL_CRYP_STATE_ERROR)
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
{
- /* Disable Error and Computation Complete Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Clear all Interrupt flags */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-
- return;
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- }
- /* Check if computation complete interrupt is enabled
- and if the computation complete flag is raised */
- if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))
- {
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
{
- /* To ensure proper suspension requests management, CCF flag
- is reset in CRYP_AES_Auth_IT() according to the current
- phase under handling */
- CRYP_AES_Auth_IT(hcryp);
- }
- else
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- CRYP_AES_IT(hcryp);
+ for(index=0U; index< 4U;index++)
+ {
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUT;
+
+ /*intermediate data buffer to be used in for the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
}
- }
-}
-/**
- * @}
- */
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ temp2[0]= hcryp->Instance->CSGCMCCM0R;
+ temp2[1]= hcryp->Instance->CSGCMCCM1R;
+ temp2[2]= hcryp->Instance->CSGCMCCM2R;
+ temp2[3]= hcryp->Instance->CSGCMCCM3R;
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ /* configured CHMOD CCM */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
-@endverbatim
- * @{
- */
+ /* configured Header phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
-/**
- * @brief Return the CRYP handle state.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL state
- */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
- /* Return CRYP handle state */
- return hcryp->State;
-}
+ /*set to zero the bits corresponding to the padded bits*/
+ for(index = lastwordsize; index<4U; index ++)
+ {
+ intermediate_data[index] =0U;
+ }
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ }
+ for(index=0U; index < 4U ; index ++)
+ {
+ intermediate_data[index] ^= temp[index];
+ intermediate_data[index] ^= temp2[index];
+ }
+ for(index = 0U; index < 4U; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DIN = intermediate_data[index] ;
+ }
-/**
- * @brief Return the CRYP peripheral error.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @note The returned error is a bit-map combination of possible errors
- * @retval Error bit-map
- */
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
-{
- return hcryp->ErrorCode;
-}
+ /* Wait for BUSY flag to be raised */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @}
- */
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @}
- */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ } /* End of CCM WKA*/
-/** @addtogroup CRYP_Private_Functions
- * @{
- */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#else /* AES */
-/**
- * @brief Write the Key in KeyRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t keyaddr = 0x0;
+ /*Workaround 2: case GCM encryption, during payload phase and before inserting
+ the last block of paylaod, which size is inferior to 128 bits */
- if ((uint32_t)(hcryp->Init.pKey == NULL))
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
- return HAL_ERROR;
+ /* configured CHMOD CTR */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
+ }
+ /* last block optionally pad the data with zeros*/
+ for(index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- keyaddr = (uint32_t)(hcryp->Init.pKey);
-
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ for(index = 0U; index< 4U;index++)
{
- hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+
+ /*intermediate data buffer to be used in the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
+ hcryp->CrypOutCount++;
}
- hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /* configured CHMOD GCM */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
+
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- return HAL_OK;
+ /*Write the intermediate_data in the IN FIFO */
+ for(index = 0U; index < lastwordsize; index ++)
+ {
+ hcryp->Instance->DINR = intermediate_data[index];
+ }
+ while(index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ for( index = 0U; index< 4U;index++)
+ {
+ intermediate_data[index]=hcryp->Instance->DOUTR;
+ }
+ }/*End of Workaround 2*/
+
+#endif /* End AES or CRYP */
}
+#if defined (CRYP)
+
/**
- * @brief Write the InitVector/InitCounter in IVRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
+ * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t ivaddr = 0x0;
+ uint32_t tickstart;
-#if !defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- hcryp->Instance->IVR3 = 0;
- hcryp->Instance->IVR2 = 0;
- hcryp->Instance->IVR1 = 0;
- hcryp->Instance->IVR0 = 0;
- }
- else
-#endif
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
- if (hcryp->Init.pInitVect == NULL)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- return HAL_ERROR;
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ return HAL_ERROR;
+ }
}
-
- ivaddr = (uint32_t)(hcryp->Init.pInitVect);
-
- hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
}
return HAL_OK;
}
-
-
/**
- * @brief Handle CRYP block input/output data handling under interruption.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by HAL_CRYPEx_AES_IT().
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr = 0;
- uint32_t outputaddr = 0;
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* Get the output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ uint32_t tickstart;
- /* Read the last available output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- }
- else
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Read the derived key from the Key registers */
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
- outputaddr+=4;
+ return HAL_ERROR;
}
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
}
+ }
+ return HAL_OK;
+}
- /* In case of ciphering or deciphering, check if all output text has been retrieved;
- In case of key derivation, stop right there */
- if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
- {
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* reset ModeSuspend */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
-
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ return HAL_ERROR;
+ }
}
- else /* Process the rest of input data */
- {
- /* Get the Intput data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ }
+ return HAL_OK;
+}
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
+#else /* AES */
+
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
- /* Write the next input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- return HAL_OK;
- }
- }
- else
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
- return HAL_BUSY;
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) )
+ {
+ return HAL_ERROR;
+ }
+ }
}
+ return HAL_OK;
}
-
+#endif /* End AES or CRYP */
/**
@@ -5173,8 +6229,15 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
* @}
*/
-#endif /* AES */
-
#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* TinyAES or CRYP*/
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp_ex.c
index 79ef150cf54635bbb279c724f6b0411bd352f06a..bf146dd1265a4df0d1cf2260d89cdb1fc3ebe560 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_cryp_ex.c
@@ -12,84 +12,23 @@
##### How to use this driver #####
==============================================================================
[..]
- The CRYP Extension HAL driver can be used as follows:
- (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
- (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
- (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable two DMA streams one for managing data transfer from
- memory to peripheral (input stream) and another stream for managing data
- transfer from peripheral to memory (output stream)
- (+++) Associate the initialized DMA handle to the CRYP DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
- (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
- (##) The encryption/decryption key. Its size depends on the algorithm
- used for encryption/decryption
- (##) The initialization vector (counter). It is not used ECB mode.
- (#)Three processing (encryption/decryption) functions are available:
- (##) Polling mode: encryption and decryption APIs are blocking functions
- i.e. they process the data and wait till the processing is finished
- e.g. HAL_CRYPEx_AESGCM_Encrypt()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
- (##) DMA mode: encryption and decryption APIs are not blocking functions
- i.e. the data transfer is ensured by DMA
- e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
- (#)When the processing function is called at first time after HAL_CRYP_Init()
- the CRYP peripheral is initialized and processes the buffer in input.
- At second call, the processing function performs an append of the already
- processed buffer.
- When a new data block is to be processed, call HAL_CRYP_Init() then the
- processing function.
- (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
- which provide authentication messages.
- HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
- authentication messages.
- Call those functions after the processing ones (polling, interrupt or DMA).
- e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
- then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
- -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
- -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
- (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
- (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ The CRYP extension HAL driver can be used as follows:
+ (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
+ to get the authentication messages :
+ (##) HAL_CRYPEx_AESGCM_GenerateAuthTAG
+ (##) HAL_CRYPEx_AESCCM_GenerateAuthTAG
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -100,6 +39,8 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+#if defined (AES) || defined (CRYP)
+
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
@@ -108,14 +49,41 @@
#ifdef HAL_CRYP_MODULE_ENABLED
-#if defined (CRYP)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_define
+/** @addtogroup CRYPEx_Private_Defines
* @{
*/
-#define CRYPEx_TIMEOUT_VALUE 1
+#if defined(AES)
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */
+
+#else /* CRYP */
+
+#define CRYP_PHASE_INIT 0x00000000U
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
+#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
+#endif /* End AES or CRYP */
+
+#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
+#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+
+ /* CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0 0x07FFFFFFU
+#define CRYP_CCM_CTR0_3 0xFFFFFF00U
+
+
/**
* @}
*/
@@ -123,5909 +91,578 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes
- * @{
- */
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
-static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
-static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_Functions
+
+
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to generate the authentication
+ TAG in Polling mode
+ (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
+ (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
+ they should be used after Encrypt/Decrypt operation.
- /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+@endverbatim
+ * @{
+ */
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief generate the GCM authentication TAG.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param AuthTag: Pointer to the authentication buffer
+ * @param Timeout: Timeout duration
+ * @retval HAL status
*/
-static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart;
+ uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
+ uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
+ uint32_t tagaddr = (uint32_t)AuthTag;
- /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
+ }
+ else /* Initialization phase has not been performed*/
+ {
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key Pointer to Key buffer
- * @param KeySize Size of Key
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
+#if defined(CRYP)
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param InitVector Pointer to InitVector/InitCounter buffer
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
-}
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-/**
- * @brief Process Data: Writes Input data in polling mode and read the Output data.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer, must be a multiple of 16
- * @param Output Pointer to the returned buffer
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t i = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ /*ALGODIR bit must be set to ‘0’.*/
+ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
- for(i=0; (i < Ilength); i+=16)
- {
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Write the number of bits in header (64 bits) followed by the number of bits
+ in the payload */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = (uint32_t)(headerlength);
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = (uint32_t)(inputlength);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ /* Wait for OFNE flag to be raised */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- /* Read the Output block from the OUT FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the header phase
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer, must be a multiple of 16
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t loopcounter = 0;
- uint32_t headeraddr = (uint32_t)Input;
-
- /***************************** Header phase *********************************/
- if(hcryp->Init.HeaderSize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+#else /* AES*/
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- return HAL_TIMEOUT;
- }
- }
- }
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
+ /* Write the number of bits in header (64 bits) followed by the number of bits
+ in the payload */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength));
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength));
}
-
- /* Wait until the complete message has been processed */
-
- /* Get tick */
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __REV((uint32_t)(headerlength));
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U);
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ /* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the DMA configuration and start the DMA transfer.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param inputaddr Address of the Input buffer
- * @param Size Size of the Input buffer, must be a multiple of 16
- * @param outputaddr Address of the Output buffer
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
+#endif /* End AES or CRYP */
- /* Enable In DMA request */
- hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable Out DMA request */
- hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @}
- */
-
-/* Exported functions---------------------------------------------------------*/
-/** @addtogroup CRYPEx_Exported_Functions
- * @{
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### Extended AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
- (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
- (+) Finish the processing. This function is available only for GCM and CCM
- [..] Three processing methods are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode then
- * encrypt pPlainData. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM Authentication TAG generation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
+ * @param AuthTag: Pointer to the authentication buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- uint32_t tickstart = 0;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
+ uint32_t tagaddr = (uint32_t)AuthTag;
+ uint32_t ctr0 [4]={0};
+ uint32_t ctr0addr = (uint32_t)ctr0;
+ uint32_t tickstart;
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *********************/
- if(headersize != 0)
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFF;
- hcryp->Init.pScratch[bufferidx++] = 0xFE;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
}
- /*********************** Formatting the block B0 **************************/
- if(headersize != 0)
+ else /* Initialization phase has not been performed*/
{
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /************************* Formatting the initial counter *****************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
- are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+#if defined(CRYP)
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ /* Select final phase & ALGODIR bit must be set to ‘0’. */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Write the counter block in the IN FIFO, CTR0 information from B0
+ data has to be swapped according to the DATATYPE*/
+ ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1]=hcryp->Init.B0[1];
+ ctr0[2]=hcryp->Init.B0[2];
+ ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ }
+ /* Wait for OFNE flag to be raised */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- /***************************** Header phase *******************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Read the Auth TAG in the IN FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
+#else /* AES */
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Write the counter block in the IN FIFO, CTR0 information from B0
+ data has to be swapped according to the DATATYPE*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
+ ctr0[1]=__REV(hcryp->Init.B0[1]);
+ ctr0[2]=__REV(hcryp->Init.B0[2]);
+ ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode then
- * encrypt pPlainData. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode then
- * decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Computes the authentication TAG.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Size Total length of the plain/cyphertext buffer
- * @param AuthTag Pointer to the authentication buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
- uint64_t inputlength = Size * 8; /* input length in bits */
- uint32_t tagaddr = (uint32_t)AuthTag;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL;
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the number of bits in header (64 bits) followed by the number of bits
- in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DR = __RBIT(headerlength >> 32);
- hcryp->Instance->DR = __RBIT(headerlength);
- hcryp->Instance->DR = __RBIT(inputlength >> 32);
- hcryp->Instance->DR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DR = __REV(headerlength >> 32);
- hcryp->Instance->DR = __REV(headerlength);
- hcryp->Instance->DR = __REV(inputlength >> 32);
- hcryp->Instance->DR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);
- hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);
- hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);
- hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DR = (uint32_t)(headerlength >> 32);
- hcryp->Instance->DR = (uint32_t)(headerlength);
- hcryp->Instance->DR = (uint32_t)(inputlength >> 32);
- hcryp->Instance->DR = (uint32_t)(inputlength);
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Computes the authentication TAG for AES CCM mode.
- * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param AuthTag Pointer to the authentication buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t tagaddr = (uint32_t)AuthTag;
- uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
- uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */
- uint32_t loopcounter;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL;
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the counter block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the Auth TAG in the IN FIFO */
- temptag[0] = hcryp->Instance->DOUT;
- temptag[1] = hcryp->Instance->DOUT;
- temptag[2] = hcryp->Instance->DOUT;
- temptag[3] = hcryp->Instance->DOUT;
- }
-
- /* Copy temporary authentication TAG in user TAG buffer */
- for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)
- {
- /* Set the authentication TAG buffer */
- *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode then
- * decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *********************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 **************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
-
- /************************* Formatting the initial counter *****************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /***************************** Header phase *******************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
-
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
-
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call Input transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
- * then decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t tickstart = 0;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- if(hcryp->CrypInCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- if(hcryp->CrypOutCount == 0)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t headersize;
- uint32_t headeraddr;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- headersize = hcryp->Init.HeaderSize;
- headeraddr = (uint32_t)hcryp->Init.Header;
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer.
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
- * then decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0;
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t headersize;
- uint32_t headeraddr;
- uint32_t loopcounter = 0;
- uint32_t bufferidx = 0;
- uint8_t blockb0[16] = {0};/* Block B0 */
- uint8_t ctr[16] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- headersize = hcryp->Init.HeaderSize;
- headeraddr = (uint32_t)hcryp->Init.Header;
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
- headersize += 2;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16) != 0)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16) + 1) * 16;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0)
- {
- blockb0[0] = 0x40;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
- blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13; loopcounter++)
- {
- blockb0[loopcounter+1] = 0;
- }
-
- blockb0[14] = (Size >> 8);
- blockb0[15] = (Size & 0xFF);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0] = blockb0[0] & 0x07;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15] |= 0x01;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
-
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
-
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0; (loopcounter < 16); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15] &= 0xfe;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
- * @brief CRYPEx IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### CRYPEx IRQ handler management #####
- ==============================================================================
-[..] This section provides CRYPEx IRQ handler function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles CRYPEx interrupt request.
- * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
- {
- case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
- HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
- HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
- HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
- HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* CRYP */
-
-#if defined (AES)
-
-/** @defgroup AESEx AESEx
- * @brief CRYP Extended HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
- * @{
- */
-#define CRYP_CCF_TIMEOUTVALUE 22000 /*!< CCF flag raising time-out value */
-#define CRYP_BUSY_TIMEOUTVALUE 22000 /*!< BUSY flag reset time-out value */
-
-#define CRYP_POLLING_OFF 0x0 /*!< No polling when padding */
-#define CRYP_POLLING_ON 0x1 /*!< Polling when padding */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
- * @{
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
- * @{
- */
-
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function
- * @brief Extended callback functions.
- *
-@verbatim
- ===============================================================================
- ##### Extended callback functions #####
- ===============================================================================
- [..] This section provides callback function:
- (+) Computation completed.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Computation completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES extended processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
- Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
- based on the processing type. Three processing types are available:
- (++) Polling mode
- (++) Interrupt mode
- (++) DMA mode
- (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES
- algorithm in different chaining modes.
- Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase
- so that steps can be skipped if so required. Functions are only differentiated based on the processing type.
- Three processing types are available:
- (++) Polling mode
- (++) Interrupt mode
- (++) DMA mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Carry out in polling mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
- * chaining modes ECB, CBC and CTR are managed by this function in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * Parameter is meaningless in case of key derivation.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * Parameter is meaningless in case of key derivation.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption, or pointer to the derivative keys in
- * case of key derivation only.
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
-{
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Call CRYP_ReadKey() API if the operating mode is set to
- key derivation, CRYP_ProcessData() otherwise */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- else
- {
- if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If the state has not been set to SUSPENDED, set it to
- READY, otherwise keep it as it is */
- if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-/**
- * @brief Carry out in interrupt mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
- * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * Parameter is meaningless in case of key derivation.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * Parameter is meaningless in case of key derivation.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption, or pointer to the derivative keys in
- * case of key derivation only.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* If operating mode is not limited to key derivation only,
- get the buffers addresses and sizes */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pInputData;
- hcryp->pCrypOutBuffPtr = pOutputData;
- hcryp->CrypOutCount = Size;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Enable Computation Complete Flag and Error Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
-
- /* If operating mode is key derivation only, the input data have
- already been entered during the initialization process. For
- the other operating modes, they are fed to the CRYP hardware
- block at this point. */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* Initiate the processing under interrupt in entering
- the first input data */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- /* Write the first input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-
-/**
- * @brief Carry out in DMA mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption.
- * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.
- * @note Supported operating modes are encryption, decryption and key derivation with decryption.
- * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx
- * registers must be done by software.
- * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx
- * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
- * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0;
- uint32_t outputaddr = 0;
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* no DMA channel is provided for key derivation operating mode,
- access to AES_KEYRx registers must be done by software */
- return HAL_ERROR;
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-
-
-/**
- * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B0 block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @param Timeout Specify Timeout value
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
-{
- uint32_t index = 0;
- uint32_t inputaddr = 0;
- uint32_t outputaddr = 0;
- uint32_t tagaddr = 0;
- uint64_t headerlength = 0;
- uint64_t inputlength = 0;
- uint64_t payloadlength = 0;
- uint32_t difflength = 0;
- uint32_t addhoc_process = 0;
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC (or CCM) header phase resumption, we can have pInputData = NULL and Size = 0 */
- if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. Therefore, the
- API just waits for the CCF flag to be set. */
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
- }
-
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
-
-#if !defined(AES_CR_NPBLB)
- /* in case of CMAC, enter B0 block in header phase, before the header itself. */
- /* If Size = 0 (possible case of resumption after CMAC header phase suspension),
- skip these steps and go directly to header buffer feeding to the HW */
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0))
- {
- inputaddr = (uint32_t)pInputData;
-
- for(index=0; (index < Size); index += 16)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size))
- {
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the total number of bytes (B blocks + header) that remain to be
- processed at this point */
- hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- } /* for(index=0; (index < Size); index += 16) */
- }
-#endif /* !defined(AES_CR_NPBLB) */
-
- /* Enter header */
- inputaddr = (uint32_t)hcryp->Init.Header;
- /* Local variable headerlength is a number of bytes multiple of 128 bits,
- remaining header data (if any) are handled after this loop */
- headerlength = (((hcryp->Init.HeaderSize)/16)*16) ;
- if ((hcryp->Init.HeaderSize % 16) != 0)
- {
- difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);
- }
- for(index=0; index < headerlength; index += 16)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength))
- {
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the total number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- }
-
- /* Case header length is not a multiple of 16 bytes */
- if (difflength != 0)
- {
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
- }
-
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
-
- /* if the header phase has been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Enter payload */
- /* Specific handling to manage payload last block size less than 128 bits */
- if ((Size % 16) != 0)
- {
- payloadlength = (Size/16) * 16;
- difflength = (uint32_t) (Size - payloadlength);
- addhoc_process = 1;
- }
- else
- {
- payloadlength = Size;
- addhoc_process = 0;
- }
-
- /* Feed payload */
- for(index=0; index < payloadlength; index += 16)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Retrieve output data: read the output block
- from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength))
- {
- /* no flag waiting under IRQ handling */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Ensure that Busy flag is reset */
- if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- }
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = Size - (index+16);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
-
- }
-
- /* Additional processing to manage GCM(/CCM) encryption and decryption cases when
- payload last block size less than 128 bits */
- if (addhoc_process == 1)
- {
-
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
-
- } /* (addhoc_process == 1) */
-
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- tagaddr = (uint32_t)pOutputData;
-
-#if defined(AES_CR_NPBLB)
- /* By default, clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
- inputlength = Size * 8; /* input length in bits */
-
-
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(headerlength, 16);
- hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(inputlength, 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
-#endif
-
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Read the Auth TAG in the Data Out register */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the final phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-/**
- * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B0 block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
-{
-
- uint32_t inputaddr = 0;
- uint64_t headerlength = 0;
- uint64_t inputlength = 0;
- uint32_t index = 0;
- uint32_t addhoc_process = 0;
- uint32_t difflength = 0;
- uint32_t difflengthmod4 = 0;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
-
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC header phase resumption, we can have pInputData = NULL and Size = 0 */
- if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Enable Computation Complete Flag and Error Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
-
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. Therefore, the
- software just waits for the CCF interrupt to be raised and which will
- be handled by CRYP_AES_Auth_IT() API. */
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
-
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC, B blocks are first entered, before the header.
- Therefore, B blocks and the header are entered back-to-back
- as if it was only one single block.
- However, in case of resumption after suspension, if all the
- B blocks have been entered (in that case, Size = 0), only the
- remainder of the non-processed header bytes are entered. */
- if (Size != 0)
- {
- hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = pInputData;
- }
- else
- {
- hcryp->CrypInCount = hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
- else
- {
- /* Get the header addresses and sizes */
- hcryp->CrypInCount = hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
-
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
- }
-
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
-
- /* Increment/decrement instance pointer/counter */
- if (hcryp->CrypInCount == 0)
- {
- /* Case of no header */
- hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_OK;
- }
- else if (hcryp->CrypInCount < 16)
- {
- hcryp->CrypInCount = 0;
- addhoc_process = 1;
- difflength = (uint32_t) (hcryp->Init.HeaderSize);
- difflengthmod4 = difflength%4;
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- }
-
-
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
- {
- /* All B blocks will have been entered after the next
- four DINR writing, so point at header buffer for
- the next iteration */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
-
- /* Enter header first block to initiate the process
- in the Data Input register */
- if (addhoc_process == 0)
- {
- /* Header has size equal or larger than 128 bits */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- else
- {
- /* Header has size less than 128 bits */
- /* Enter complete words when possible */
- for(index=0; index < (difflength/4); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- hcryp->Instance->DINR = 0;
- }
-
- }
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pInputData;
- hcryp->pCrypOutBuffPtr = pOutputData;
- hcryp->CrypOutCount = Size;
-
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
-
- /* if the header phase has been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- /* Specific handling to manage payload size less than 128 bits */
- if (Size < 16)
- {
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
- {
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);
- }
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
-
- /* Set hcryp->CrypInCount to 0 (no more data to enter) */
- hcryp->CrypInCount = 0;
-
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes,
- to have a complete block of 128 bits */
- difflength = (uint32_t) (Size);
- difflengthmod4 = difflength%4;
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
- to have a complete block of 128 bits */
- for(index=0; index < (difflength/4); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
- /* If required, manage input data size not multiple of 32 bits */
- if (difflengthmod4 != 0)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Wrap-up in padding with zero-words if applicable */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- hcryp->Instance->DINR = 0;
- }
- }
- else
- {
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
-
- /* Enter payload first block to initiate the process
- in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- hcryp->pCrypOutBuffPtr = pOutputData;
-
-#if defined(AES_CR_NPBLB)
- /* By default, clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
- inputlength = Size * 8; /* Input length in bits */
- /* Write the number of bits in the header on 64 bits followed by the number
- of bits in the payload on 64 bits as well */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(headerlength, 16);
- hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(inputlength, 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
-#endif
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-/**
- * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0;
- uint32_t outputaddr = 0;
- uint32_t tagaddr = 0;
- uint64_t headerlength = 0;
- uint64_t inputlength = 0;
- uint64_t payloadlength = 0;
-
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if ((pInputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. No DMA transfer is
- required at that point therefore, the software just waits for the CCF flag
- to be raised. */
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- /*===============================*/
- /* GCM/GMAC or CMAC header phase */
- /*===============================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
- {
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
- }
-
-#if !defined(AES_CR_NPBLB)
- /* enter first B0 block in polling mode (no DMA transfer for B0) */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- inputaddr = (uint32_t)pInputData;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- }
-#endif
-
- /* No header case */
- if (hcryp->Init.Header == NULL)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
-
- inputaddr = (uint32_t)hcryp->Init.Header;
- if ((hcryp->Init.HeaderSize % 16) != 0)
- {
-
- if (hcryp->Init.HeaderSize < 16)
- {
- CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);
-
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
-
- /* CCF flag indicating header phase AES processing completion
- will be checked at the start of the next phase:
- - payload phase (GCM / CCM when applicable)
- - final phase (GMAC or CMAC). */
- }
- else
- {
- /* Local variable headerlength is a number of bytes multiple of 128 bits,
- remaining header data (if any) are handled after this loop */
- headerlength = (((hcryp->Init.HeaderSize)/16)*16) ;
- /* Store the ending transfer point */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;
- hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */
-
- /* Set the input and output addresses and start DMA transfer */
- /* (incomplete DMA transfer, will be wrapped up after completion of
- the first one (initiated here) with data padding */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0);
- }
- }
- else
- {
- hcryp->CrypInCount = 0;
- /* Set the input address and start DMA transfer */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0);
- }
-
-
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- /* Coming from header phase, wait for CCF flag to be raised
- if header present and fed to the IP in the previous phase */
- if (hcryp->Init.Header != NULL)
- {
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- }
- else
- {
- /* Enable the Peripheral since wasn't in header phase (no header case) */
- __HAL_CRYP_ENABLE();
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
-
- /* Specific handling to manage payload size less than 128 bits */
- if ((Size % 16) != 0)
- {
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
- if (Size < 16)
- {
- /* Block is now entered in polling mode, no actual gain in resorting to DMA */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
-
- CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON);
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- else
- {
- payloadlength = (Size/16) * 16;
-
- /* Store the ending transfer points */
- hcryp->pCrypInBuffPtr = pInputData + payloadlength;
- hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;
- hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */
-
- /* Set the input and output addresses and start DMA transfer */
- /* (incomplete DMA transfer, will be wrapped up with data padding
- after completion of the one initiated here) */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);
- }
- }
- else
- {
- hcryp->CrypInCount = 0;
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Set the input and output addresses and start DMA transfer */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
- }
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- /* If coming from header phase (GMAC or CMAC case),
- wait for CCF flag to be raised */
- if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE)
- {
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- }
-
- tagaddr = (uint32_t)pOutputData;
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
- inputlength = Size * 8; /* input length in bits */
- /* Write the number of bits in the header on 64 bits followed by the number
- of bits in the payload on 64 bits as well */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(headerlength, 16);
- hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);
- hcryp->Instance->DINR = __ROR(inputlength, 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
-#endif
-
- /* No DMA transfer is required at that point therefore, the software
- just waits for the CCF flag to be raised. */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
- /* Mark that the final phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES extended suspension and resumption functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) save in memory the Initialization Vector, the Key registers, the Control register or
- the Suspend registers when a process is suspended by a higher priority message
- (+) write back in CRYP hardware block the saved values listed above when the suspended
- lower priority message processing is resumed.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief In case of message processing suspension, read the Initialization Vector.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Initialization Vector.
- * @note This value has to be stored for reuse by writing the AES_IVRx registers
- * as soon as the interrupted processing has to be resumed.
- * Applicable to all chaining modes.
- * @note AES must be disabled when reading or resetting the IV values.
- * @retval None
- */
-void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);
-}
-
-/**
- * @brief In case of message processing resumption, rewrite the Initialization
- * Vector in the AES_IVRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved Initialization Vector to
- * write back in the CRYP hardware block.
- * @note Applicable to all chaining modes.
- * @note AES must be disabled when reading or resetting the IV values.
- * @retval None
- */
-void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- uint32_t ivaddr = (uint32_t)Input;
-
- hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Suspend Registers.
- * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- /* In case of GCM payload phase encryption, check that suspension can be carried out */
- if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))
- {
- /* Ensure that Busy flag is reset */
- if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- HAL_CRYP_ErrorCallback(hcryp);
- return ;
- }
- }
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend
- * Registers in the AES_SUSPxR registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved suspend registers to
- * write back in the CRYP hardware block.
- * @retval None
- */
-void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- uint32_t ivaddr = (uint32_t)Input;
-
- hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4;
- hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Key Registers.
- * @param KeySize Indicates the key size (128 or 256 bits).
- * @note These values have to be stored for reuse by writing back the AES_KEYRx registers
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Output;
-
- if (KeySize == CRYP_KEYSIZE_256B)
- {
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);
- keyaddr+=4;
- }
-
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);
- keyaddr+=4;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0);
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key
- * Registers in the AES_KEYRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved key registers to
- * write back in the CRYP hardware block.
- * @param KeySize Indicates the key size (128 or 256 bits)
- * @retval None
- */
-void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Input;
-
- if (KeySize == CRYP_KEYSIZE_256B)
- {
- hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- }
-
- hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4;
- hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Control Register.
- * @note This values has to be stored for reuse by writing back the AES_CR register
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- *(uint32_t*)(Output) = hcryp->Instance->CR;
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control
- * Registers in the AES_CR register.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved Control Register to
- * write back in the CRYP hardware block.
- * @retval None
- */
-void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- hcryp->Instance->CR = *(uint32_t*)(Input);
- /* At the same time, set handle state back to READY to be able to resume the AES calculations
- without the processing APIs returning HAL_BUSY when called. */
- hcryp->State = HAL_CRYP_STATE_READY;
-}
-
-/**
- * @brief Request CRYP processing suspension when in polling or interruption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @note Set the handle field SuspendRequest to the appropriate value so that
- * the on-going CRYP processing is suspended as soon as the required
- * conditions are met.
- * @note It is advised not to suspend the CRYP processing when the DMA controller
- * is managing the data transfer
- * @retval None
- */
-void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
-{
- /* Set Handle Suspend Request field */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA CRYP Input Data process complete callback
- * for GCM, GMAC or CMAC chainging modes.
- * @note Specific setting of hcryp fields are required only
- * in the case of header phase where no output data DMA
- * transfer is on-going (only input data transfer is enabled
- * in such a case).
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- uint32_t difflength = 0;
-
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
-
- if (hcryp->CrypInCount != 0)
- {
- /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0;
-
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);
- }
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- }
- /* CCF flag indicating header phase AES processing completion
- will be checked at the start of the next phase:
- - payload phase (GCM or CCM when applicable)
- - final phase (GMAC or CMAC).
- This allows to avoid the Wait on Flag within the IRQ handling. */
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback
- * for GCM, GMAC or CMAC chainging modes.
- * @note This callback is called only in the payload phase.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- uint32_t difflength = 0;
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Initiate additional transfer to wrap-up data feeding to the IP */
- if (hcryp->CrypInCount != 0)
- {
- /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0;
-
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback
- * for GCM, GMAC or CMAC chainging modes.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hcryp->State= HAL_CRYP_STATE_ERROR;
- hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
- HAL_CRYP_ErrorCallback(hcryp);
- /* Clear Error Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
-}
-
-
-
-/**
- * @brief Handle CRYP block input/output data handling under interruption
- * for GCM, GMAC or CMAC chaining modes.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t inputaddr = 0x0;
- uint32_t outputaddr = 0x0;
- uint32_t index = 0x0;
- uint32_t addhoc_process = 0;
- uint32_t difflength = 0;
- uint32_t difflengthmod4 = 0;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
- uint32_t intermediate_data[4] = {0};
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- /*===========================*/
- /* GCM/GMAC(/CCM) init phase */
- /*===========================*/
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- return HAL_OK;
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- /* Check if all input header data have been entered */
- if (hcryp->CrypInCount == 0)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
-
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
- {
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else /* Carry on feeding input data to the CRYP hardware block */
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last Input data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- /* Increment/decrement instance pointer/counter */
- if (hcryp->CrypInCount < 16)
- {
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0;
- addhoc_process = 1;
- difflengthmod4 = difflength%4;
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
- }
-
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
- {
- /* All B blocks will have been entered after the next
- four DINR writing, so point at header buffer for
- the next iteration */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
-
- /* Write the Input block in the Data Input register */
- if (addhoc_process == 0)
- {
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- else
- {
- /* Header remainder has size less than 128 bits */
- /* Enter complete words when possible */
- for(index=0; index < (difflength/4); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- hcryp->Instance->DINR = 0;
- }
- }
-
- return HAL_OK;
- }
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
}
- /*=======================*/
- /* GCM/CCM payload phase */
- /*=======================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- /* Get the last output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-
- /* Specific handling to manage payload size less than 128 bits
- when GCM (or CCM when applicable) encryption or decryption is selected.
- Check here if the last block output data are read */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->CrypOutCount < 16) && \
- (hcryp->CrypOutCount > 0))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
- (hcryp->CrypOutCount < 16) && \
- (hcryp->CrypOutCount > 0))
-#endif
- {
- addhoc_process = 1;
- difflength = hcryp->CrypOutCount;
- difflengthmod4 = difflength%4;
- hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */
- /* Retrieve intermediate data */
- for(index=0; index < 4; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- /* Retrieve last words of cyphered data */
- /* First, retrieve complete output words */
- for(index=0; index < (difflength/4); index ++)
- {
- *(uint32_t*)(outputaddr) = intermediate_data[index];
- outputaddr+=4;
- }
- /* Next, retrieve partial output word if applicable;
- at the same time, start masking intermediate data
- with a mask of zeros of same size than the padding
- applied to the last block of payload */
- if (difflengthmod4 != 0)
- {
- intermediate_data[difflength/4] &= mask[difflengthmod4-1];
- *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
- }
-
-#if !defined(AES_CR_NPBLB)
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change again CHMOD configuration to GCM mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
-
- /* Select FINAL phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
-
- /* Before inserting the intermediate data, carry on masking operation
- with a mask of zeros of same size than the padding applied to the last block of payload */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- intermediate_data[(difflength+3)/4+index] = 0;
- }
-
- /* Insert intermediate data to trigger an additional DOUTR reading round */
- /* Clear Computation Complete Flag before entering new block */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- for(index=0; index < 4; index ++)
- {
- hcryp->Instance->DINR = intermediate_data[index];
- }
- }
- else
-#endif
- {
- /* Payload phase is now over */
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+ ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
+ ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U);
+ ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U);
+ ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
+
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
+ ctr0[1]=__RBIT(hcryp->Init.B0[1]);
+ ctr0[2]=__RBIT(hcryp->Init.B0[2]);
+ ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ }
+ else
+ {
+ ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1]=hcryp->Init.B0[1];
+ ctr0[2]=hcryp->Init.B0[2];
+ ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ }
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- }
- return HAL_OK;
- }
- else
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- if (hcryp->CrypOutCount != 0)
- {
- /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */
- /* Retrieve the last block available from the CRYP hardware block:
- read the output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypOutBuffPtr += 16;
- hcryp->CrypOutCount -= 16;
- }
-#if !defined(AES_CR_NPBLB)
- else
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
- /* Software work-around: additional DOUTR reading round to discard the data */
- for(index=0; index < 4; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- }
-#endif
- }
+ /* Disable the CRYP peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Check if all output text has been retrieved */
- if (hcryp->CrypOutCount == 0)
- {
-#if !defined(AES_CR_NPBLB)
- /* Make sure that software-work around is not running before disabling
- the interruptions (indeed, if software work-around is running, the
- interruptions must not be disabled to allow the additional DOUTR
- reading round */
- if (addhoc_process == 0)
-#endif
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- }
-
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
- {
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else /* Output data are still expected, carry on feeding the CRYP
- hardware block with input data */
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last Input data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- /* Usual input data feeding case */
- if (hcryp->CrypInCount < 16)
- {
- difflength = (uint32_t) (hcryp->CrypInCount);
- difflengthmod4 = difflength%4;
- hcryp->CrypInCount = 0;
-
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
- to have a complete block of 128 bits */
- for(index=0; index < (difflength/4); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
- /* If required, manage input data size not multiple of 32 bits */
- if (difflengthmod4 != 0)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Wrap-up in padding with zero-words if applicable */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- hcryp->Instance->DINR = 0;
- }
-
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16;
- hcryp->CrypInCount -= 16;
-
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ return HAL_ERROR;
}
-
-
- return HAL_OK;
}
}
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- /* Retrieve the last expected data from the CRYP hardware block:
- read the output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+#endif /* End of AES || CRYP */
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- return HAL_OK;
- }
- else
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
}
else
{
- return HAL_BUSY;
- }
-}
-
-
-
-/**
- * @brief Set the DMA configuration and start the DMA transfer
- * for GCM, GMAC or CMAC chainging modes.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param inputaddr Address of the Input buffer.
- * @param Size Size of the Input buffer un bytes, must be a multiple of 16.
- * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream
- * has to be configured.
- * @retval None
- */
-static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
-
- /* Set the input CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError;
-
- if (outputaddr != 0)
- {
- /* Set the output CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError;
- }
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- /* Enable the DMA input stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
-
- /* Enable the DMA input request */
- SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
-
- if (outputaddr != 0)
- {
- /* Enable the DMA output stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
-
- /* Enable the DMA output request */
- SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
- }
-}
-
-
-
-/**
- * @brief Write/read input/output data in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16.
- * @param Output Pointer to the returned buffer.
- * @param Timeout Specify Timeout value.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t index = 0;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
-
- for(index=0; (index < Ilength); index += 16)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Read the Output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4;
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength))
- {
- /* Reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = Ilength - (index+16);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
-
- return HAL_OK;
- }
-
-
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
-
}
-
-
-
-
/**
- * @brief Read derivative key in polling mode when CRYP hardware block is set
- * in key derivation operating mode (mode 2).
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the returned buffer.
- * @param Timeout Specify Timeout value.
- * @retval HAL status
+ * @}
*/
-static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR);
-
- /* Read the derivative key from the AES_KEYRx registers */
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
- {
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
- outputaddr+=4;
- }
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
-
- /* Return function status */
- return HAL_OK;
-}
+#if defined (AES)
+/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions
+ * @brief AutoKeyDerivation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Key Derivation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to Enable or Disable the
+ the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
+ These function are allowed only in TinyAES IP.
-/**
- * @brief Set the DMA configuration and start the DMA transfer.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param inputaddr Address of the Input buffer.
- * @param Size Size of the Input buffer in bytes, must be a multiple of 16.
- * @param outputaddr Address of the Output buffer.
- * @retval None
+@endverbatim
+ * @{
*/
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
- /* Enable the DMA input stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
-
- /* Enable the DMA output stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
-
- /* Enable In and Out DMA requests */
- SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-}
-
/**
- * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout Timeout duration.
- * @retval HAL status
+ * @brief AES enable key derivation functions
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure.
+ * @retval None
*/
-static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- return HAL_TIMEOUT;
- }
- }
+ hcryp->AutoKeyDerivation = ENABLE;
}
- return HAL_OK;
-}
-
-/**
- * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))
+ else
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- return HAL_TIMEOUT;
- }
- }
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
}
- return HAL_OK;
-}
-
-
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE();
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hcryp->State= HAL_CRYP_STATE_ERROR;
- hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
- HAL_CRYP_ErrorCallback(hcryp);
- /* Clear Error Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
}
-
/**
- * @brief Last header or payload block padding when size is not a multiple of 128 bits.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param difflength size remainder after having fed all complete 128-bit blocks.
- * @param polling specifies whether or not polling on CCF must be done after having
- * entered a complete block.
+ * @brief AES disable key derivation functions
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure.
* @retval None
*/
-static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
+void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- uint32_t index = 0;
- uint32_t difflengthmod4 = difflength%4;
- uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
- uint32_t intermediate_data[4] = {0};
-
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
- {
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);
- }
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) &&
- (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
- /* Wrap-up entering header or payload data */
- /* Enter complete words when possible */
- for(index=0; index < (difflength/4); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- hcryp->Instance->DINR = 0;
+ hcryp->AutoKeyDerivation = DISABLE;
}
-
- if (polling == CRYP_POLLING_ON)
+ else
{
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
}
-
- /* if payload */
- if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
- {
-
- /* Retrieve intermediate data */
- for(index=0; index < 4; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- /* Retrieve last words of cyphered data */
- /* First, retrieve complete output words */
- for(index=0; index < (difflength/4); index ++)
- {
- *(uint32_t*)(outputaddr) = intermediate_data[index];
- outputaddr+=4;
- }
- /* Next, retrieve partial output word if applicable;
- at the same time, start masking intermediate data
- with a mask of zeros of same size than the padding
- applied to the last block of payload */
- if (difflengthmod4 != 0)
- {
- intermediate_data[difflength/4] &= mask[difflengthmod4-1];
- *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
- }
-
-
-#if !defined(AES_CR_NPBLB)
- /* Software workaround applied to GCM encryption only,
- applicable for AES IP v2 version (where NPBLB is not defined) */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change again CHMOD configuration to GCM mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
-
- /* Select FINAL phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
-
- /* Before inserting the intermediate data, carry on masking operation
- with a mask of zeros of same size than the padding applied to the last block of payload */
- for(index=0; index < (4 - ((difflength+3)/4)); index ++)
- {
- intermediate_data[(difflength+3)/4+index] = 0;
- }
- /* Insert intermediate data */
- for(index=0; index < 4; index ++)
- {
- hcryp->Instance->DINR = intermediate_data[index];
- }
-
- /* Wait for completion, and read data on DOUT. This data is to discard. */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- /* Read data to discard */
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- for(index=0; index < 4; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
-
- } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */
-#endif /* !defined(AES_CR_NPBLB) */
- } /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */
-
}
-/**
- * @}
- */
-
/**
* @}
*/
#endif /* AES */
-
#endif /* HAL_CRYP_MODULE_ENABLED */
+/**
+ * @}
+ */
+#endif /* TinyAES or CRYP*/
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac.c
index bdd9ff01c2b5cb9d88bd0a2fae5b9b0ef6b11116..38c0979824215b26d4a6bced07bd6d8a276ebe95 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac.c
@@ -123,6 +123,61 @@
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ (+) All Callbacks
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+ and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+ or @ref HAL_DAC_Init function.
+
+ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@@ -141,29 +196,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -221,7 +260,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @brief Initializes the DAC peripheral according to the specified parameters
* in the DAC_InitStruct.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
@@ -237,10 +276,32 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
if(hdac->State == HAL_DAC_STATE_RESET)
{
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the DAC Callback settings */
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+ if(hdac->MspInitCallback == NULL)
+ {
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the low level hardware */
+ hdac->MspInitCallback(hdac);
+#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
@@ -258,7 +319,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
@@ -276,8 +337,17 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ if(hdac->MspDeInitCallback == NULL)
+ {
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdac->MspDeInitCallback(hdac);
+#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
@@ -294,7 +364,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/**
* @brief Initializes the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -310,7 +380,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
/**
* @brief DeInitializes the DAC MSP.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -348,9 +418,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -407,9 +477,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -432,15 +502,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData The Source memory Buffer address.
- * @param Length The length of data to be transferred from memory to DAC peripheral
- * @param Alignment Specifies the data alignment for DAC channel.
+ * @param pData: The Source memory Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -558,9 +628,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/**
* @brief Disables DAC and stop conversion of channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -608,9 +678,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -634,7 +704,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Handles DAC interrupt request
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -656,7 +726,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
/* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh1(hdac);
+#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
@@ -674,13 +748,17 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
/* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh2(hdac);
+#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
/**
* @brief Conversion complete callback in non blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -696,7 +774,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -712,7 +790,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/**
* @brief Error DAC callback for Channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -728,7 +806,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
/**
* @brief DMA underrun DAC callback for channel1.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -763,10 +841,10 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
/**
* @brief Configures the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param sConfig DAC configuration structure.
- * @param Channel The selected DAC channel.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
@@ -814,18 +892,18 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/**
* @brief Set the specified data holding register value for DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Alignment Specifies the data alignment.
+ * @param Alignment: Specifies the data alignment.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data Data to be loaded in the selected data holding register.
+ * @param Data: Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
@@ -876,7 +954,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
/**
* @brief return the DAC state
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
@@ -889,7 +967,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
/**
* @brief Return the DAC error code
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
@@ -902,9 +980,253 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DAC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ *
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if(hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+
+/**
+ * @brief Unregister a User DAC Callback
+ * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if(hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ break;
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ case HAL_DAC_ALL_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
/**
* @brief DMA conversion complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -912,14 +1234,18 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh1(hdac);
+#else
HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -927,12 +1253,16 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh1(hdac);
+#else
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -943,7 +1273,11 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh1(hdac);
+#else
HAL_DAC_ErrorCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac_ex.c
index d467d9dea5b7c912697967f0b6f87ace198c9cac..b96fc94e80ad0f85f600afb7820bd8db3ee5613c 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dac_ex.c
@@ -23,29 +23,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -97,7 +81,7 @@
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
@@ -115,13 +99,13 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
/**
* @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude Select max triangle amplitude.
+ * @param Amplitude: Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -164,13 +148,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
/**
* @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
@@ -213,15 +197,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
/**
* @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Alignment Specifies the data alignment for dual channel DAC.
+ * @param Alignment: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval HAL status
@@ -261,7 +245,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
/**
* @brief Conversion complete callback in non blocking mode for Channel2
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -277,7 +261,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -293,7 +277,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/**
* @brief Error DAC callback for Channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -309,7 +293,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA underrun DAC callback for channel2.
- * @param hdac pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -325,7 +309,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -333,14 +317,18 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -348,12 +336,16 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -364,7 +356,11 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh2(hdac);
+#else
HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi.c
index 5fcbac866d6ac6dfd17a38e89776214b598729a3..7a5e772b8af84c8a345edff5f50b90db95abfc8e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi.c
@@ -56,34 +56,68 @@
[..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
-
+
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
+
+ Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
+ (+) FrameEventCallback : DCMI Frame Event.
+ (+) VsyncEventCallback : DCMI Vsync Event.
+ (+) LineEventCallback : DCMI Line Event.
+ (+) ErrorCallback : DCMI error.
+ (+) MspInitCallback : DCMI MspInit.
+ (+) MspDeInitCallback : DCMI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ This function allows to reset following callbacks:
+ (+) FrameEventCallback : DCMI Frame Event.
+ (+) VsyncEventCallback : DCMI Vsync Event.
+ (+) LineEventCallback : DCMI Line Event.
+ (+) ErrorCallback : DCMI error.
+ (+) MspInitCallback : DCMI MspInit.
+ (+) MspDeInitCallback : DCMI MspDeInit.
+
+ By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
+ and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
+ or @ref HAL_DCMI_Init function.
+
+ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -165,8 +199,24 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
- /* Init the low level hardware */
+ /* Init the DCMI Callback settings */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if(hdcmi->MspInitCallback == NULL)
+ {
+ /* Legacy weak MspInit Callback */
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ }
+ /* Initialize the low level hardware (MSP) */
+ hdcmi->MspInitCallback(hdcmi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
}
/* Change the DCMI state */
@@ -215,8 +265,17 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
- /* DeInit the low level hardware */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ if(hdcmi->MspDeInitCallback == NULL)
+ {
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ }
+ /* De-Initialize the low level hardware (MSP) */
+ hdcmi->MspDeInitCallback(hdcmi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspDeInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@@ -546,7 +605,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI line event callback*/
+ hdcmi->LineEventCallback(hdcmi);
+#else
HAL_DCMI_LineEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
@@ -555,7 +619,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI vsync event callback*/
+ hdcmi->VsyncEventCallback(hdcmi);
+#else
HAL_DCMI_VsyncEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
@@ -574,7 +643,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* Frame Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI frame event callback*/
+ hdcmi->FrameEventCallback(hdcmi);
+#else
HAL_DCMI_FrameEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
}
@@ -790,6 +864,172 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
return hdcmi->ErrorCode;
}
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief DCMI Callback registering
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param CallbackID dcmi Callback ID
+ * @param pCallback pointer to DCMI_CallbackTypeDef structure
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DCMI Callback Unregistering
+ * @param hdcmi dcmi handle
+ * @param CallbackID dcmi Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -874,7 +1114,13 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
}
/* DCMI error Callback */
- HAL_DCMI_ErrorCallback(hdcmi);
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI error callback*/
+ hdcmi->ErrorCallback(hdcmi);
+#else
+ HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi_ex.c
index b505903cfbb892e7675062d805e04291f58b7751..b852675c44d393dd7c4aceff4f5292278997bb37 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dcmi_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dfsdm.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dfsdm.c
index 4e963d3f889f2825a1db794c77bf696e9e450a72..2a8e053fa6b8b7312be93eb2013366e7cfd34e21 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dfsdm.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dfsdm.c
@@ -155,33 +155,96 @@
[..]
(#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
+ @ref HAL_DFSDM_Filter_RegisterCallback() or
+ @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+
+ Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+ following callbacks:
+ (+) CkabCallback : DFSDM channel clock absence detection callback.
+ (+) ScdCallback : DFSDM channel short circuit detection callback.
+ (+) MspInitCallback : DFSDM channel MSP init callback.
+ (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+ following callbacks:
+ (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
+ (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
+ (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback.
+ (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
+ (+) ErrorCallback : DFSDM filter error callback.
+ (+) MspInitCallback : DFSDM filter MSP init callback.
+ (+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific DFSDM filter analog watchdog callback use dedicated register callback:
+ @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+
+ Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
+ @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+ weak function.
+
+ @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) CkabCallback : DFSDM channel clock absence detection callback.
+ (+) ScdCallback : DFSDM channel short circuit detection callback.
+ (+) MspInitCallback : DFSDM channel MSP init callback.
+ (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+
+ @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
+ (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
+ (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback.
+ (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
+ (+) ErrorCallback : DFSDM filter error callback.
+ (+) MspInitCallback : DFSDM filter MSP init callback.
+ (+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+
+ For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
+ @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+
+ By default, after the call of init function and if the state is RESET
+ all callbacks are reset to the corresponding legacy weak functions:
+ examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak functions in the init and de-init only when these
+ callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the init and de-init keep and use
+ the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the init/de-init.
+ In that case first register the MspInit/MspDeInit user callbacks using
+ @ref HAL_DFSDM_Channel_RegisterCallback() or
+ @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+
+ When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -297,8 +360,21 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
return HAL_ERROR;
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+
+ /* Call MSP init function */
+ if(hdfsdm_channel->MspInitCallback == NULL)
+ {
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ }
+ hdfsdm_channel->MspInitCallback(hdfsdm_channel);
+#else
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+#endif
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
@@ -394,7 +470,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
}
/* Call MSP deinit function */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ if(hdfsdm_channel->MspDeInitCallback == NULL)
+ {
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ }
+ hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
+#else
HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+#endif
/* Set DFSDM Channel in reset state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
@@ -434,6 +518,143 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann
the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
*/
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user DFSDM channel callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
+ pDFSDM_Channel_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
+ hdfsdm_channel->CkabCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_SCD_CB_ID :
+ hdfsdm_channel->ScdCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM channel callback.
+ * DFSDM channel callback is redirected to the weak predefined callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_SCD_CB_ID :
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
/**
* @}
@@ -789,7 +1010,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
}
/* Clear short circuit detection flag */
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Return function status */
return HAL_OK;
@@ -822,7 +1043,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
}
/* Return function status */
return status;
@@ -914,7 +1135,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Disable short circuit detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
@@ -1051,8 +1272,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
hdfsdm_filter->InjConvRemaining = 1;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
+ hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
+ hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
+ hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
+ hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
+ hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
+
+ /* Call MSP init function */
+ if(hdfsdm_filter->MspInitCallback == NULL)
+ {
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ }
+ hdfsdm_filter->MspInitCallback(hdfsdm_filter);
+#else
/* Call MSP init function */
HAL_DFSDM_FilterMspInit(hdfsdm_filter);
+#endif
/* Set regular parameters */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
@@ -1142,7 +1380,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
/* Call MSP deinit function */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ if(hdfsdm_filter->MspDeInitCallback == NULL)
+ {
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ }
+ hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
+#endif
/* Set DFSDM filter in reset state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
@@ -1180,6 +1426,242 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
*/
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user DFSDM filter callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
+ pDFSDM_Filter_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->RegConvCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->InjConvCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_ERROR_CB_ID :
+ hdfsdm_filter->ErrorCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM filter callback.
+ * DFSDM filter callback is redirected to the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_ERROR_CB_ID :
+ hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Register a user DFSDM filter analog watchdog callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pCallback pointer to the DFSDM filter analog watchdog callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ pDFSDM_Filter_AwdCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ hdfsdm_filter->AwdCallback = pCallback;
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM filter analog watchdog callback.
+ * DFSDM filter AWD callback is redirected to the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1390,7 +1872,11 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
/* Clear regular overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
@@ -1794,7 +2280,11 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
/* Clear injected overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
@@ -2385,7 +2875,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/* Check if overrun occurs during injected conversion */
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
@@ -2398,14 +2892,22 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/* Check if end of regular conversion */
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
{
/* Call regular conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+#endif
/* End of conversion if mode is not continuous and software trigger */
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
@@ -2424,7 +2926,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
{
/* Call injected conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+#endif
/* Update remaining injected conversions */
hdfsdm_filter->InjConvRemaining--;
@@ -2471,7 +2977,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
(1 << channel);
/* Call analog watchdog callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
+#else
HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
+#endif
}
/* Check if clock absence occurs */
else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
@@ -2495,7 +3005,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
+#endif
}
}
channel++;
@@ -2519,10 +3033,14 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Call short circuit detection callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
+#endif
}
}
@@ -2689,7 +3207,11 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular half conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -2703,7 +3225,11 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -2717,7 +3243,11 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected half conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -2731,7 +3261,11 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -2748,7 +3282,11 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma.c
index de138e18c7585debaf2f84bfdc2af0f7fa1951f9..83c3d114fa238313942dbd4a511006bfad100ea2 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma.c
@@ -84,29 +84,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma2d.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma2d.c
index e5aec3d5615f759d923472b9c9093a38fd87f1c6..c08a4b9a626a58296d3c81de14c5aace2ead1d3c 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma2d.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma2d.c
@@ -41,7 +41,7 @@
(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback (member
of DMA2D handle structure).
- (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
+ (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
XferErrorCallback.
-@- In Register-to-Memory transfer mode, pdata parameter is the register
@@ -59,7 +59,7 @@
(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
- (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
+ (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
@@ -89,6 +89,59 @@
(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+
+ (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+ and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
+ as weak (surcharged) functions. They must be defined by the user to be resorted to.
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
+ or @ref HAL_DMA2D_Init function.
+
+ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -96,29 +149,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -126,6 +163,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -135,9 +175,6 @@
* @{
*/
-#ifdef HAL_DMA2D_MODULE_ENABLED
-#if defined (DMA2D)
-
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
@@ -147,8 +184,8 @@
/** @defgroup DMA2D_TimeOut DMA2D Time Out
* @{
*/
-#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
-#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
+#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
+#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
/**
* @}
*/
@@ -161,7 +198,7 @@
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup DMA2D_Private_Functions_Prototypes
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
@@ -210,7 +247,26 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+ assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
+ assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+ {
+ /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ if(hdma2d->MspInitCallback == NULL)
+ {
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hdma2d->MspInitCallback(hdma2d);
+ }
+#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -218,6 +274,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
}
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
@@ -230,15 +287,10 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
-
-#if defined (DMA2D_OPFCCR_AI)
- /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos));
-#endif /* DMA2D_OPFCCR_AI */
-
-#if defined (DMA2D_OPFCCR_RBS)
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos));
-#endif /* DMA2D_OPFCCR_RBS */
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+ /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
+ MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Update error code */
@@ -285,7 +337,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
/* Abort background CLUT loading if any */
if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
{
- if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
{
/* Issue when aborting background CLUT loading */
return HAL_ERROR;
@@ -296,7 +348,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
/* Abort foreground CLUT loading if any */
if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
{
- if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
+ if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
{
/* Issue when aborting foreground CLUT loading */
return HAL_ERROR;
@@ -306,17 +358,29 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
}
}
+ /* Reset DMA2D control registers*/
+ hdma2d->Instance->CR = 0U;
+ hdma2d->Instance->IFCR = 0x3FU;
+ hdma2d->Instance->FGOR = 0U;
+ hdma2d->Instance->BGOR = 0U;
+ hdma2d->Instance->FGPFCCR = 0U;
+ hdma2d->Instance->BGPFCCR = 0U;
+ hdma2d->Instance->OPFCCR = 0U;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+
+ if(hdma2d->MspDeInitCallback == NULL)
+ {
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hdma2d->MspDeInitCallback(hdma2d);
+#else
/* Carry on with de-initialization of low level hardware */
HAL_DMA2D_MspDeInit(hdma2d);
-
- /* Reset DMA2D control registers*/
- hdma2d->Instance->CR = 0;
- hdma2d->Instance->FGOR = 0;
- hdma2d->Instance->BGOR = 0;
- hdma2d->Instance->FGPFCCR = 0;
- hdma2d->Instance->BGPFCCR = 0;
- hdma2d->Instance->OPFCCR = 0;
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
@@ -362,6 +426,197 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
*/
}
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DMA2D Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+
+/**
+ * @brief Unregister a DMA2D Callback
+ * DMA2D Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
+{
+HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -554,7 +809,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
*/
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Abort the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
@@ -566,7 +821,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively disabled */
- while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
{
@@ -603,7 +858,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
*/
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Suspend the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
@@ -615,8 +870,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
+ while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
{
@@ -631,7 +885,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
@@ -676,7 +930,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
@@ -690,7 +944,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Enable the background CLUT loading */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -713,7 +967,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
* @retval HAL status
*/
@@ -731,7 +985,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
@@ -751,7 +1005,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -768,7 +1022,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -785,7 +1039,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
@@ -808,7 +1062,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
@@ -826,19 +1080,19 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- uint32_t tickstart = 0;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ uint32_t tickstart;
+ const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Abort the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1)
+ if(LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -848,7 +1102,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3
tickstart = HAL_GetTick();
/* Check if the CLUT loading is aborted */
- while((*reg & DMA2D_BGPFCCR_START) != RESET)
+ while((*reg & DMA2D_BGPFCCR_START) != 0U)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
{
@@ -883,19 +1137,20 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- uint32_t tickstart = 0;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ uint32_t tickstart;
+ uint32_t loadsuspended;
+ const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Suspend the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1)
+ if(LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -904,8 +1159,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
tickstart = HAL_GetTick();
/* Check if the CLUT loading is suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ while (loadsuspended == 0UL)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
{
@@ -917,10 +1173,12 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
return HAL_TIMEOUT;
}
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((*reg & DMA2D_BGPFCCR_START) != RESET)
+ if ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
@@ -940,32 +1198,36 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the SUSP and START bits for background or foreground CLUT loading */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Background CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
+ if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ {
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
+ }
else
{
/* Foreground CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+ {
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
+ }
/* Resume the CLUT loading */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
@@ -984,25 +1246,26 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
- uint32_t tickstart = 0;
- __IO uint32_t isrflags = 0x0;
+ uint32_t tickstart;
+ uint32_t layer_start;
+ __IO uint32_t isrflags = 0x0U;
/* Polling for DMA2D transfer */
- if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
{
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
@@ -1020,7 +1283,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1037,26 +1300,27 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
}
}
/* Polling for CLUT loading (foreground or background) */
- if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
- ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
+ layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
+ layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
+ if (layer_start != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
{
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
}
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
@@ -1074,7 +1338,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1114,9 +1378,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
/* Transfer Error Interrupt management ***************************************/
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
- if ((crflags & DMA2D_IT_TE) != RESET)
+ if ((crflags & DMA2D_IT_TE) != 0U)
{
/* Disable the transfer Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
@@ -1141,9 +1405,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* Configuration Error Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
- if ((crflags & DMA2D_IT_CE) != RESET)
+ if ((crflags & DMA2D_IT_CE) != 0U)
{
/* Disable the Configuration Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
@@ -1168,9 +1432,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* CLUT access Error Interrupt management ***********************************/
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
- if ((crflags & DMA2D_IT_CAE) != RESET)
+ if ((crflags & DMA2D_IT_CAE) != 0U)
{
/* Disable the CLUT access error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
@@ -1195,9 +1459,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* Transfer watermark Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_TW) != RESET)
+ if ((isrflags & DMA2D_FLAG_TW) != 0U)
{
- if ((crflags & DMA2D_IT_TW) != RESET)
+ if ((crflags & DMA2D_IT_TW) != 0U)
{
/* Disable the transfer watermark interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
@@ -1206,13 +1470,18 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
/* Transfer watermark Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->LineEventCallback(hdma2d);
+#else
HAL_DMA2D_LineEventCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
}
}
/* Transfer Complete Interrupt management ************************************/
- if ((isrflags & DMA2D_FLAG_TC) != RESET)
+ if ((isrflags & DMA2D_FLAG_TC) != 0U)
{
- if ((crflags & DMA2D_IT_TC) != RESET)
+ if ((crflags & DMA2D_IT_TC) != 0U)
{
/* Disable the transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
@@ -1237,9 +1506,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* CLUT Transfer Complete Interrupt management ******************************/
- if ((isrflags & DMA2D_FLAG_CTC) != RESET)
+ if ((isrflags & DMA2D_FLAG_CTC) != 0U)
{
- if ((crflags & DMA2D_IT_CTC) != RESET)
+ if ((crflags & DMA2D_IT_CTC) != 0U)
{
/* Disable the CLUT transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
@@ -1257,7 +1526,11 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
__HAL_UNLOCK(hdma2d);
/* CLUT Transfer complete Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->CLUTLoadingCpltCallback(hdma2d);
+#else
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
@@ -1320,31 +1593,34 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
/**
* @brief Configure the DMA2D Layer according to the specified
- * parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * parameters in the DMA2D_HandleTypeDef.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
-
- uint32_t regMask = 0, regValue = 0;
+ DMA2D_LayerCfgTypeDef *pLayerCfg;
+ uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
+ assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
{
- assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
if(hdma2d->Init.Mode != DMA2D_M2M)
{
- assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
+ assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
}
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+ assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
+ assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Process locked */
__HAL_LOCK(hdma2d);
@@ -1352,21 +1628,18 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- /* DMA2D BGPFCR register configuration -----------------------------------*/
- /* Prepare the value to be written to the BGPFCCR register */
+ pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+ /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
+ (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
+ regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
+#else
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
+#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
-#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
- regValue |= (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos);
- regMask |= DMA2D_BGPFCCR_AI;
-#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
-
-#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
- regValue |= (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
- regMask |= DMA2D_BGPFCCR_RBS;
-#endif
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
@@ -1378,7 +1651,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
}
/* Configure the background DMA2D layer */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
@@ -1395,6 +1668,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
/* Configure the foreground DMA2D layer */
else
{
+
+
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
@@ -1424,7 +1699,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -1441,7 +1716,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
@@ -1458,7 +1733,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
/* Set the DMA2D state to Ready*/
@@ -1599,7 +1874,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection provides functions allowing to :
+ This subsection provides functions allowing to:
(+) Get the DMA2D state
(+) Get the DMA2D error code
@@ -1654,11 +1929,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
- uint32_t tmp = 0;
- uint32_t tmp1 = 0;
- uint32_t tmp2 = 0;
- uint32_t tmp3 = 0;
- uint32_t tmp4 = 0;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t tmp3;
+ uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
@@ -1685,26 +1960,26 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
{
- tmp2 = (tmp2 >> 19);
- tmp3 = (tmp3 >> 10);
- tmp4 = (tmp4 >> 3 );
- tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 10U);
+ tmp4 = (tmp4 >> 3U );
+ tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
{
- tmp1 = (tmp1 >> 31);
- tmp2 = (tmp2 >> 19);
- tmp3 = (tmp3 >> 11);
- tmp4 = (tmp4 >> 3 );
- tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
+ tmp1 = (tmp1 >> 31U);
+ tmp2 = (tmp2 >> 19U);
+ tmp3 = (tmp3 >> 11U);
+ tmp4 = (tmp4 >> 3U );
+ tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
- tmp1 = (tmp1 >> 28);
- tmp2 = (tmp2 >> 20);
- tmp3 = (tmp3 >> 12);
- tmp4 = (tmp4 >> 4 );
- tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
+ tmp1 = (tmp1 >> 28U);
+ tmp2 = (tmp2 >> 20U);
+ tmp3 = (tmp3 >> 12U);
+ tmp4 = (tmp4 >> 4U );
+ tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
@@ -1719,8 +1994,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/**
* @}
*/
-#endif /* DMA2D */
-#endif /* HAL_DMA2D_MODULE_ENABLED */
+
/**
* @}
*/
@@ -1728,5 +2002,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/**
* @}
*/
+#endif /* DMA2D */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma_ex.c
index b84369d399b9231ef983ed4a65794d2bf0d99056..e694fbca4a0b88d2f0b15b052ac8e3a3ae550b7f 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dma_ex.c
@@ -25,29 +25,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dsi.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dsi.c
index ffeef1f51dfb7055a019bcf2bb799cbca1933b26..a01a6defd3d5f005bf44be68f129d3409e53516e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dsi.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_dsi.c
@@ -9,32 +9,120 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
+ PLL parameters, number of lanes and TX Escape clock divider.
+ (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
+ command mode.
+ (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
+ (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
+ (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
+ (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
+ Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
+ to write DSI short packets, long packets and to read DSI packets.
+
+ (#) The DSI Host Offers two Low power modes :
+ (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
+ It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
+ and @ref HAL_DSI_ExitULPMData()
+
+ (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
+ It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
+ and @ref HAL_DSI_ExitULPM()
+
+ (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
+ When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
+ the error code by calling function @ref HAL_DSI_GetError()
+
+ (#) To control DSI state you can use the following function: HAL_DSI_GetState()
+
+ *** DSI HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DSI HAL driver.
+
+ (+) __HAL_DSI_ENABLE: Enable the DSI Host.
+ (+) __HAL_DSI_DISABLE: Disable the DSI Host.
+ (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
+ (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
+ (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
+ (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
+ (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
+ (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
+ (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
+ (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
+ (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
+ (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
+ (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
+
+
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
+
+ Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+
+ By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
+ or HAL_DSI_Init function.
+
+ When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the DSI HAL driver header file for more useful macros
+
+ @endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -45,20 +133,21 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-/** @addtogroup DSI
- * @{
- */
#ifdef HAL_DSI_MODULE_ENABLED
-#if defined (STM32F769xx) || defined (STM32F779xx)
+#if defined(DSI)
+
+/** @addtogroup DSI
+ * @{
+ */
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup DSI_Private_Constants
* @{
*/
-#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
@@ -81,21 +170,28 @@
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
+ uint32_t Data1);
+
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
/* Private functions ---------------------------------------------------------*/
/**
* @brief Generic DSI packet header configuration
- * @param DSIx Pointer to DSI register base
+ * @param DSIx Pointer to DSI register base
* @param ChannelID Virtual channel ID of the header packet
- * @param DataType Packet data type of the header packet
+ * @param DataType Packet data type of the header packet
* This parameter can be any value of :
* @ref DSI_SHORT_WRITE_PKT_Data_Type
* or @ref DSI_LONG_WRITE_PKT_Data_Type
* or @ref DSI_SHORT_READ_PKT_Data_Type
* or DSI_MAX_RETURN_PKT_SIZE
- * @param Data0 Word count LSB
- * @param Data1 Word count MSB
+ * @param Data0 Word count LSB
+ * @param Data1 Word count MSB
* @retval None
*/
static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
@@ -105,7 +201,48 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
uint32_t Data1)
{
/* Update the DSI packet header with new information */
- DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));
+ DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
+}
+
+/**
+ * @brief write short DCS or short Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI short packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * @param Param1 DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code.
+ * @param Param2 DSC parameter or second generic parameter.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2)
+{
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the packet to send a short DCS command with 0 or 1 parameter */
+ /* Update the DSI packet header with new information */
+ hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
+
+ return HAL_OK;
}
/* Exported functions --------------------------------------------------------*/
@@ -114,8 +251,8 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
*/
/** @defgroup DSI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -131,20 +268,20 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
/**
* @brief Initializes the DSI according to the specified
* parameters in the DSI_InitTypeDef and create the associated handle.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
- * the PLL Clock structure definition for the DSI.
+ * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
+ * the PLL Clock structure definition for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
{
- uint32_t tickstart = 0;
- uint32_t unitIntervalx4 = 0;
- uint32_t tempIDF = 0;
+ uint32_t tickstart;
+ uint32_t unitIntervalx4;
+ uint32_t tempIDF;
/* Check the DSI handle allocation */
- if(hdsi == NULL)
+ if (hdsi == NULL)
{
return HAL_ERROR;
}
@@ -156,91 +293,108 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
- if(hdsi->State == HAL_DSI_STATE_RESET)
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ /* Reset the DSI callback to the legacy weak callbacks */
+ hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+ hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
+ hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hdsi->MspInitCallback == NULL)
+ {
+ hdsi->MspInitCallback = HAL_DSI_MspInit;
+ }
+ /* Initialize the low level hardware */
+ hdsi->MspInitCallback(hdsi);
+ }
+#else
+ if (hdsi->State == HAL_DSI_STATE_RESET)
{
/* Initialize the low level hardware */
HAL_DSI_MspInit(hdsi);
}
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
/**************** Turn on the regulator and enable the DSI PLL ****************/
- /* Enable the regulator */
- __HAL_DSI_REG_ENABLE(hdsi);
+ /* Enable the regulator */
+ __HAL_DSI_REG_ENABLE(hdsi);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the regulator is ready */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the regulator is ready */
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
+ }
- /* Set the PLL division factors */
- hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));
+ /* Set the PLL division factors */
+ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
- /* Enable the DSI PLL */
- __HAL_DSI_PLL_ENABLE(hdsi);
+ /* Enable the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for the lock of the PLL */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
+ }
/*************************** Set the PHY parameters ***************************/
- /* D-PHY clock and digital enable*/
- hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+ /* D-PHY clock and digital enable*/
+ hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
- /* Clock lane configuration */
- hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
- hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
- /* Configure the number of active data lanes */
- hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
- hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
+ /* Configure the number of active data lanes */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
+ hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
/************************ Set the DSI clock parameters ************************/
- /* Set the TX escape clock division factor */
- hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
- hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
+ /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
+ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
+ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
+ tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
+ unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
- /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
- /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
- /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
- tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;
- unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);
-
- /* Set the bit period in high-speed mode */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;
- hdsi->Instance->WPCR[0] |= unitIntervalx4;
+ /* Set the bit period in high-speed mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
+ hdsi->Instance->WPCR[0U] |= unitIntervalx4;
/****************************** Error management *****************************/
- /* Disable all error interrupts and reset the Error Mask */
- hdsi->Instance->IER[0] = 0;
- hdsi->Instance->IER[1] = 0;
- hdsi->ErrorMsk = 0;
+ /* Disable all error interrupts and reset the Error Mask */
+ hdsi->Instance->IER[0U] = 0U;
+ hdsi->Instance->IER[1U] = 0U;
+ hdsi->ErrorMsk = 0U;
- /* Initialise the error code */
- hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
hdsi->State = HAL_DSI_STATE_READY;
@@ -251,14 +405,14 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
/**
* @brief De-initializes the DSI peripheral registers to their default reset
* values.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
{
/* Check the DSI handle allocation */
- if(hdsi == NULL)
+ if (hdsi == NULL)
{
return HAL_ERROR;
}
@@ -281,8 +435,17 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
/* Disable the regulator */
__HAL_DSI_REG_DISABLE(hdsi);
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ if (hdsi->MspDeInitCallback == NULL)
+ {
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdsi->MspDeInitCallback(hdsi);
+#else
/* DeInit the low level hardware */
HAL_DSI_MspDeInit(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Initialise the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
@@ -296,23 +459,11 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
return HAL_OK;
}
-/**
- * @brief Return the DSI error code
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @retval DSI Error Code
- */
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
-{
- /* Get the error code */
- return hdsi->ErrorCode;
-}
-
/**
* @brief Enable the error monitor flags
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ActiveErrors indicates which error interrupts will be enabled.
+ * @param ActiveErrors indicates which error interrupts will be enabled.
* This parameter can be any combination of @ref DSI_Error_Data_Type.
* @retval HAL status
*/
@@ -321,70 +472,70 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A
/* Process locked */
__HAL_LOCK(hdsi);
- hdsi->Instance->IER[0] = 0;
- hdsi->Instance->IER[1] = 0;
+ hdsi->Instance->IER[0U] = 0U;
+ hdsi->Instance->IER[1U] = 0U;
/* Store active errors to the handle */
hdsi->ErrorMsk = ActiveErrors;
- if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;
+ hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;
+ hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
{
/* Enable the interrupt generation on selected errors */
- hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;
+ hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
}
/* Process Unlocked */
@@ -395,15 +546,14 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A
/**
* @brief Initializes the DSI MSP.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
-__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_MspInit could be implemented in the user file
*/
@@ -411,27 +561,209 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
/**
* @brief De-initializes the DSI MSP.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
-__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DSI Callback
+ * To be used instead of the weak predefined callback
+ * @param hdsi dsi handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+ pDSI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ if (hdsi->State == HAL_DSI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_TEARING_EFFECT_CB_ID :
+ hdsi->TearingEffectCallback = pCallback;
+ break;
+
+ case HAL_DSI_ENDOF_REFRESH_CB_ID :
+ hdsi->EndOfRefreshCallback = pCallback;
+ break;
+
+ case HAL_DSI_ERROR_CB_ID :
+ hdsi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a DSI Callback
+ * DSI callabck is redirected to the weak predefined callback
+ * @param hdsi dsi handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ if (hdsi->State == HAL_DSI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_TEARING_EFFECT_CB_ID :
+ hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+ break;
+
+ case HAL_DSI_ENDOF_REFRESH_CB_ID :
+ hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
+ break;
+
+ case HAL_DSI_ERROR_CB_ID :
+ hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return status;
+}
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup DSI_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -444,7 +776,7 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
*/
/**
* @brief Handles DSI interrupt request.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -453,101 +785,119 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
uint32_t ErrorStatus0, ErrorStatus1;
/* Tearing Effect Interrupt management ***************************************/
- if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
+ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
{
- if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
+ if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
{
/* Clear the Tearing Effect Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
/* Tearing Effect Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered Tearing Effect callback */
+ hdsi->TearingEffectCallback(hdsi);
+#else
+ /*Call legacy Tearing Effect callback*/
HAL_DSI_TearingEffectCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* End of Refresh Interrupt management ***************************************/
- if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
+ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
{
- if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
+ if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
{
/* Clear the End of Refresh Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
/* End of Refresh Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered End of refresh callback */
+ hdsi->EndOfRefreshCallback(hdsi);
+#else
+ /*Call Legacy End of refresh callback */
HAL_DSI_EndOfRefreshCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* Error Interrupts management ***********************************************/
- if(hdsi->ErrorMsk != 0)
+ if (hdsi->ErrorMsk != 0U)
{
- ErrorStatus0 = hdsi->Instance->ISR[0];
- ErrorStatus0 &= hdsi->Instance->IER[0];
- ErrorStatus1 = hdsi->Instance->ISR[1];
- ErrorStatus1 &= hdsi->Instance->IER[1];
+ ErrorStatus0 = hdsi->Instance->ISR[0U];
+ ErrorStatus0 &= hdsi->Instance->IER[0U];
+ ErrorStatus1 = hdsi->Instance->ISR[1U];
+ ErrorStatus1 &= hdsi->Instance->IER[1U];
- if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
+ if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
}
- if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
+ if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
}
- if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
}
- if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
}
- if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
}
- if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
}
- if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
}
- if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
}
- if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
}
- if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
}
/* Check only selected errors */
- if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
+ if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
{
- /* DSI error interrupt user callback */
+ /* DSI error interrupt callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered Error callback */
+ hdsi->ErrorCallback(hdsi);
+#else
+ /*Call Legacy Error callback */
HAL_DSI_ErrorCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Tearing Effect DSI callback.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -555,7 +905,6 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_TearingEffectCallback could be implemented in the user file
*/
@@ -563,7 +912,7 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
/**
* @brief End of Refresh DSI callback.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -571,7 +920,6 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
*/
@@ -579,7 +927,7 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
/**
* @brief Operation Error DSI callback.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -587,7 +935,6 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_ErrorCallback could be implemented in the user file
*/
@@ -598,12 +945,40 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
*/
/** @defgroup DSI_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the Generic interface read-back Virtual Channel ID
+ (+) Select video mode and configure the corresponding parameters
+ (+) Configure command transmission mode: High-speed or Low-power
+ (+) Configure the flow control
+ (+) Configure the DSI PHY timer
+ (+) Configure the DSI HOST timeout
+ (+) Configure the DSI HOST timeout
+ (+) Start/Stop the DSI module
+ (+) Refresh the display in command mode
+ (+) Controls the display color mode in Video mode
+ (+) Control the display shutdown in Video mode
+ (+) write short DCS or short Generic command
+ (+) write long DCS or long Generic command
+ (+) Read command (DCS or generic)
+ (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
+ (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
+ (+) Start/Stop test pattern generation
+ (+) Slew-Rate And Delay Tuning
+ (+) Low-Power Reception Filter Tuning
+ (+) Activate an additional current path on all lanes to meet the SDDTx parameter
+ (+) Custom lane pins configuration
+ (+) Set custom timing for the PHY
+ (+) Force the Clock/Data Lane in TX Stop Mode
+ (+) Force LP Receiver in Low-Power Mode
+ (+) Force Data Lanes in RX Mode after a BTA
+ (+) Enable a pull-down on the lanes to prevent from floating states when unused
+ (+) Switch off the contention detection on data lanes
@endverbatim
* @{
@@ -611,9 +986,9 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
/**
* @brief Configure the Generic interface read-back Virtual Channel ID.
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param VirtualChannelID Virtual channel ID
+ * @param VirtualChannelID Virtual channel ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
@@ -633,10 +1008,10 @@ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t Virtu
/**
* @brief Select video mode and configure the corresponding parameters
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
- * the DSI video mode configuration parameters
+ * the DSI video mode configuration parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
@@ -659,7 +1034,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
/* Check the LooselyPacked variant only in 18-bit mode */
- if(VidCfg->ColorCoding == DSI_RGB666)
+ if (VidCfg->ColorCoding == DSI_RGB666)
{
assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
}
@@ -698,10 +1073,10 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
- hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);
+ hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
/* Enable/disable the loosely packed variant to 18-bit configuration */
- if(VidCfg->ColorCoding == DSI_RGB666)
+ if (VidCfg->ColorCoding == DSI_RGB666)
{
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
@@ -741,7 +1116,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
/* Low power largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
- hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);
+ hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
/* Low power VACT largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
@@ -783,9 +1158,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
/**
* @brief Select adapted command mode and configure the corresponding parameters
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
+ * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @retval HAL status
*/
@@ -824,7 +1199,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
- hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);
+ hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
/* Configure the maximum allowed size for write memory command */
hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
@@ -832,7 +1207,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_
/* Configure the tearing effect source and polarity and select the refresh mode */
hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
- hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
+ hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
+ CmdCfg->VSyncPol);
/* Configure the tearing effect acknowledge request */
hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
@@ -853,9 +1229,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_
/**
* @brief Configure command transmission mode: High-speed or Low-power
* and enable/disable acknowledge request after packet transmission
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
+ * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
* the DSI command transmission mode configuration parameters
* @retval HAL status
*/
@@ -879,29 +1255,29 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe
assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
/* Select High-speed or Low-power for command transmission */
- hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
- DSI_CMCR_GSW1TX |\
- DSI_CMCR_GSW2TX |\
- DSI_CMCR_GSR0TX |\
- DSI_CMCR_GSR1TX |\
- DSI_CMCR_GSR2TX |\
- DSI_CMCR_GLWTX |\
- DSI_CMCR_DSW0TX |\
- DSI_CMCR_DSW1TX |\
- DSI_CMCR_DSR0TX |\
- DSI_CMCR_DLWTX |\
+ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
+ DSI_CMCR_GSW1TX | \
+ DSI_CMCR_GSW2TX | \
+ DSI_CMCR_GSR0TX | \
+ DSI_CMCR_GSR1TX | \
+ DSI_CMCR_GSR2TX | \
+ DSI_CMCR_GLWTX | \
+ DSI_CMCR_DSW0TX | \
+ DSI_CMCR_DSW1TX | \
+ DSI_CMCR_DSR0TX | \
+ DSI_CMCR_DLWTX | \
DSI_CMCR_MRDPS);
- hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
- LPCmd->LPGenShortWriteOneP |\
- LPCmd->LPGenShortWriteTwoP |\
- LPCmd->LPGenShortReadNoP |\
- LPCmd->LPGenShortReadOneP |\
- LPCmd->LPGenShortReadTwoP |\
- LPCmd->LPGenLongWrite |\
- LPCmd->LPDcsShortWriteNoP |\
- LPCmd->LPDcsShortWriteOneP |\
- LPCmd->LPDcsShortReadNoP |\
- LPCmd->LPDcsLongWrite |\
+ hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \
+ LPCmd->LPGenShortWriteOneP | \
+ LPCmd->LPGenShortWriteTwoP | \
+ LPCmd->LPGenShortReadNoP | \
+ LPCmd->LPGenShortReadOneP | \
+ LPCmd->LPGenShortReadTwoP | \
+ LPCmd->LPGenLongWrite | \
+ LPCmd->LPDcsShortWriteNoP | \
+ LPCmd->LPDcsShortWriteOneP | \
+ LPCmd->LPDcsShortReadNoP | \
+ LPCmd->LPDcsLongWrite | \
LPCmd->LPMaxReadPacket);
/* Configure the acknowledge request after each packet transmission */
@@ -916,9 +1292,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe
/**
* @brief Configure the flow control parameters
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param FlowControl flow control feature(s) to be enabled.
+ * @param FlowControl flow control feature(s) to be enabled.
* This parameter can be any combination of @ref DSI_FlowControl.
* @retval HAL status
*/
@@ -942,9 +1318,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t Fl
/**
* @brief Configure the DSI PHY timer parameters
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
+ * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
* the DSI PHY timing parameters
* @retval HAL status
*/
@@ -954,7 +1330,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
/* Process locked */
__HAL_LOCK(hdsi);
- maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
+ maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
+ PhyTimers->ClockLaneHS2LPTime;
/* Clock lane timer configuration */
@@ -966,17 +1343,18 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
- */
+ */
hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
- hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));
+ hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
/* Data lane timer configuration */
hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
- hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));
+ hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
+ PhyTimers->DataLaneHS2LPTime) << 24U));
/* Configure the wait period to request HS transmission after a stop state */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
- hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);
+ hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -986,9 +1364,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
/**
* @brief Configure the DSI HOST timeout parameters
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
+ * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
* the DSI host timeout parameters
* @retval HAL status
*/
@@ -999,39 +1377,39 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T
/* Set the timeout clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
- hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8);
+ hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
/* High-speed transmission timeout */
- hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
- hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);
+ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
+ hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
/* Low-power reception timeout */
- hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;
- hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;
+ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
+ hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
/* High-speed read timeout */
- hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;
- hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;
+ hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
+ hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
/* Low-power read timeout */
- hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;
- hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;
+ hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
+ hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
/* High-speed write timeout */
- hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;
- hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;
+ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
+ hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
/* High-speed write presp mode */
- hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;
- hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;
+ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
+ hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
/* Low-speed write timeout */
- hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;
- hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;
+ hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
+ hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
/* BTA timeout */
- hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;
- hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;
+ hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
+ hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1041,7 +1419,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T
/**
* @brief Start the DSI module
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1064,7 +1442,7 @@ HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
/**
* @brief Stop the DSI module
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1087,7 +1465,7 @@ HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
/**
* @brief Refresh the display in command mode
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1107,9 +1485,9 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
/**
* @brief Controls the display color mode in Video mode
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ColorMode Color mode (full or 8-colors).
+ * @param ColorMode Color mode (full or 8-colors).
* This parameter can be any value of @ref DSI_Color_Mode
* @retval HAL status
*/
@@ -1133,9 +1511,9 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
/**
* @brief Control the display shutdown in Video mode
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Shutdown Shut-down (Display-ON or Display-OFF).
+ * @param Shutdown Shut-down (Display-ON or Display-OFF).
* This parameter can be any value of @ref DSI_ShutDown
* @retval HAL status
*/
@@ -1158,16 +1536,16 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
}
/**
- * @brief DCS or Generic short write command
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @brief write short DCS or short Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelID Virtual channel ID.
- * @param Mode DSI short packet data type.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI short packet data type.
* This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
- * @param Param1 DSC command or first generic parameter.
+ * @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @ref DSI_DCS_Command or a
* generic command code.
- * @param Param2 DSC parameter or second generic parameter.
+ * @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
@@ -1176,55 +1554,33 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
uint32_t Param1,
uint32_t Param2)
{
- uint32_t tickstart = 0;
-
- /* Process locked */
- __HAL_LOCK(hdsi);
-
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdsi);
-
- return HAL_TIMEOUT;
- }
- }
+ /* Process locked */
+ __HAL_LOCK(hdsi);
- /* Configure the packet to send a short DCS command with 0 or 1 parameter */
- DSI_ConfigPacketHeader(hdsi->Instance,
- ChannelID,
- Mode,
- Param1,
- Param2);
+ status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
- return HAL_OK;
+ return status;
}
/**
- * @brief DCS or Generic long write command
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @brief write long DCS or long Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelID Virtual channel ID.
- * @param Mode DSI long packet data type.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI long packet data type.
* This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
- * @param NbParams Number of parameters.
- * @param Param1 DSC command or first generic parameter.
+ * @param NbParams Number of parameters.
+ * @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @ref DSI_DCS_Command or a
* generic command code
- * @param ParametersTable Pointer to parameter values table.
+ * @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
@@ -1232,10 +1588,12 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t* ParametersTable)
+ uint8_t *ParametersTable)
{
- uint32_t uicounter = 0;
- uint32_t tickstart = 0;
+ uint32_t uicounter, nbBytes, count;
+ uint32_t tickstart;
+ uint32_t fifoword;
+ uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1247,10 +1605,10 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
+ while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1259,33 +1617,39 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
}
}
- /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
- while(uicounter < NbParams)
+ /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
+ fifoword = Param1;
+ nbBytes = (NbParams < 3U) ? NbParams : 3U;
+
+ for (count = 0U; count < nbBytes; count++)
{
- if(uicounter == 0x00)
- {
- hdsi->Instance->GPDR=(Param1 | \
- ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \
- ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \
- ((uint32_t)(*(ParametersTable + uicounter+2))<<24));
- uicounter += 3;
- }
- else
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
+ }
+ hdsi->Instance->GPDR = fifoword;
+
+ uicounter = NbParams - nbBytes;
+ pparams += nbBytes;
+ /* Set the Next parameters on the write FIFO command*/
+ while (uicounter != 0U)
+ {
+ nbBytes = (uicounter < 4U) ? uicounter : 4U;
+ fifoword = 0U;
+ for (count = 0U; count < nbBytes; count++)
{
- hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \
- ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \
- ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \
- ((uint32_t)(*(ParametersTable + uicounter+3)) << 24));
- uicounter+=4;
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
}
+ hdsi->Instance->GPDR = fifoword;
+
+ uicounter -= nbBytes;
+ pparams += nbBytes;
}
/* Configure the packet to send a long DCS command */
DSI_ConfigPacketHeader(hdsi->Instance,
ChannelID,
Mode,
- ((NbParams+1)&0x00FF),
- (((NbParams+1)&0xFF00)>>8));
+ ((NbParams + 1U) & 0x00FFU),
+ (((NbParams + 1U) & 0xFF00U) >> 8U));
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1295,26 +1659,31 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
/**
* @brief Read command (DCS or generic)
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelNbr Virtual channel ID
+ * @param ChannelNbr Virtual channel ID
* @param Array pointer to a buffer to store the payload of a read back operation.
- * @param Size Data size to be read (in byte).
- * @param Mode DSI read packet data type.
+ * @param Size Data size to be read (in byte).
+ * @param Mode DSI read packet data type.
* This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
- * @param DCSCmd DCS get/read command.
- * @param ParametersTable Pointer to parameter values table.
+ * @param DCSCmd DCS get/read command.
+ * @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
- uint8_t* Array,
+ uint8_t *Array,
uint32_t Size,
uint32_t Mode,
uint32_t DCSCmd,
- uint8_t* ParametersTable)
+ uint8_t *ParametersTable)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
+ uint8_t *pdata = Array;
+ uint32_t datasize = Size;
+ uint32_t fifoword;
+ uint32_t nbbytes;
+ uint32_t count;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1322,28 +1691,35 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
/* Check the parameters */
assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
- if(Size > 2)
+ if (datasize > 2U)
{
/* set max return packet size */
- HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));
+ if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
+ (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
}
/* Configure the packet to read command */
if (Mode == DSI_DCS_SHORT_PKT_READ)
{
- DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
{
- DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
{
- DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
{
- DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);
+ DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
}
else
{
@@ -1356,49 +1732,24 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
/* Get tick */
tickstart = HAL_GetTick();
- /* Check that the payload read FIFO is not empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
+ /* If DSI fifo is not empty, read requested bytes */
+ while (((int32_t)(datasize)) > 0)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdsi);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Get the first byte */
- *((uint32_t *)Array) = (hdsi->Instance->GPDR);
- if (Size > 4)
- {
- Size -= 4;
- Array += 4;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
-
- return HAL_OK;
- }
+ fifoword = hdsi->Instance->GPDR;
+ nbbytes = (datasize < 4U) ? datasize : 4U;
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Get the remaining bytes if any */
- while(((int)(Size)) > 0)
- {
- if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)
- {
- *((uint32_t *)Array) = (hdsi->Instance->GPDR);
- Size -= 4;
- Array += 4;
+ for (count = 0U; count < nbbytes; count++)
+ {
+ *pdata = (uint8_t)(fifoword >> (8U * count));
+ pdata++;
+ datasize--;
+ }
}
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1416,13 +1767,13 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1434,12 +1785,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until the D-PHY active lanes enter into ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
+ while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1450,10 +1801,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1462,6 +1813,13 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
}
}
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1472,13 +1830,13 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1490,12 +1848,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+ while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1506,10 +1864,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1518,9 +1876,19 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
}
}
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* wait for 1 ms*/
+ HAL_Delay(1U);
/* De-assert the ULPM requests and the ULPM exit bits */
- hdsi->Instance->PUCR = 0;
+ hdsi->Instance->PUCR = 0U;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1531,13 +1899,13 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1555,12 +1923,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1571,10 +1939,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1583,6 +1951,13 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
}
}
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
/* Turn off the DSI PLL */
__HAL_DSI_PLL_DISABLE(hdsi);
@@ -1596,13 +1971,13 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1614,10 +1989,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1633,12 +2008,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1649,10 +2024,11 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
+ DSI_PSR_UANC))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1661,9 +2037,19 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
}
}
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* wait for 1 ms */
+ HAL_Delay(1U);
/* De-assert the ULPM requests and the ULPM exit bits */
- hdsi->Instance->PUCR = 0;
+ hdsi->Instance->PUCR = 0U;
/* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
@@ -1679,13 +2065,13 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
/**
* @brief Start test pattern generation
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Mode Pattern generator mode
+ * @param Mode Pattern generator mode
* This parameter can be one of the following values:
* 0 : Color bars (horizontal or vertical)
* 1 : BER pattern (vertical only)
- * @param Orientation Pattern generator orientation
+ * @param Orientation Pattern generator orientation
* This parameter can be one of the following values:
* 0 : Vertical color bars
* 1 : Horizontal color bars
@@ -1698,7 +2084,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_
/* Configure pattern generator mode and orientation */
hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
- hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));
+ hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
/* Enable pattern generator by setting PGE bit */
hdsi->Instance->VMCR |= DSI_VMCR_PGE;
@@ -1711,7 +2097,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_
/**
* @brief Stop test pattern generation
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1731,16 +2117,17 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
/**
* @brief Set Slew-Rate And Delay Tuning
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CommDelay Communication delay to be adjusted.
+ * @param CommDelay Communication delay to be adjusted.
* This parameter can be any value of @ref DSI_Communication_Delay
- * @param Lane select between clock or data lanes.
+ * @param Lane select between clock or data lanes.
* This parameter can be any value of @ref DSI_Lane_Group
- * @param Value Custom value of the slew-rate or delay
+ * @param Value Custom value of the slew-rate or delay
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+ uint32_t Value)
{
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1749,52 +2136,73 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin
assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
assert_param(IS_DSI_LANE_GROUP(Lane));
- switch(CommDelay)
+ switch (CommDelay)
{
- case DSI_SLEW_RATE_HSTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Slew Rate Control on Clock Lane */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;
- hdsi->Instance->WPCR[1] |= Value<<16;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* High-Speed Transmission Slew Rate Control on Data Lanes */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;
- hdsi->Instance->WPCR[1] |= Value<<18;
- }
- break;
- case DSI_SLEW_RATE_LPTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Low-Power transmission Slew Rate Compensation on Clock Lane */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;
- hdsi->Instance->WPCR[1] |= Value<<6;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* Low-Power transmission Slew Rate Compensation on Data Lanes */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;
- hdsi->Instance->WPCR[1] |= Value<<8;
- }
- break;
- case DSI_HS_DELAY:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Delay on Clock Lane */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;
- hdsi->Instance->WPCR[1] |= Value;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* High-Speed Transmission Delay on Data Lanes */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;
- hdsi->Instance->WPCR[1] |= Value<<2;
- }
- break;
- default:
- break;
+ case DSI_SLEW_RATE_HSTX:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Slew Rate Control on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value << 16U;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Slew Rate Control on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value << 18U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_SLEW_RATE_LPTX:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value << 6U;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value << 8U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_HS_DELAY:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Delay on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
+ hdsi->Instance->WPCR[1U] |= Value;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Delay on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
+ hdsi->Instance->WPCR[1U] |= Value << 2U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -1805,9 +2213,9 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin
/**
* @brief Low-Power Reception Filter Tuning
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
+ * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
@@ -1816,8 +2224,8 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t
__HAL_LOCK(hdsi);
/* Low-Power RX low-pass Filtering Tuning */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;
- hdsi->Instance->WPCR[1] |= Frequency<<25;
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
+ hdsi->Instance->WPCR[1U] |= Frequency << 25U;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1828,9 +2236,9 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t
/**
* @brief Activate an additional current path on all lanes to meet the SDDTx parameter
* defined in the MIPI D-PHY specification
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
@@ -1842,8 +2250,8 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
assert_param(IS_FUNCTIONAL_STATE(State));
/* Activate/Disactivate additional current path on all lanes */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;
- hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12);
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
+ hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1853,16 +2261,17 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
/**
* @brief Custom lane pins configuration
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CustomLane Function to be applyed on selected lane.
+ * @param CustomLane Function to be applyed on selected lane.
* This parameter can be any value of @ref DSI_CustomLane
- * @param Lane select between clock or data lane 0 or data lane 1.
+ * @param Lane select between clock or data lane 0 or data lane 1.
* This parameter can be any value of @ref DSI_Lane_Select
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+ FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1872,50 +2281,64 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
assert_param(IS_DSI_LANE(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
- switch(CustomLane)
+ switch (CustomLane)
{
- case DSI_SWAP_LANE_PINS:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Swap pins on clock lane */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Swap pins on data lane 0 */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7);
- }
- else if(Lane == DSI_DATA_LANE1)
- {
- /* Swap pins on data lane 1 */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8);
- }
- break;
- case DSI_INVERT_HS_SIGNAL:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Invert HS signal on clock lane */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Invert HS signal on data lane 0 */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10);
- }
- else if(Lane == DSI_DATA_LANE1)
- {
- /* Invert HS signal on data lane 1 */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11);
- }
- break;
- default:
- break;
+ case DSI_SWAP_LANE_PINS:
+ if (Lane == DSI_CLK_LANE)
+ {
+ /* Swap pins on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
+ }
+ else if (Lane == DSI_DATA_LANE0)
+ {
+ /* Swap pins on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
+ }
+ else if (Lane == DSI_DATA_LANE1)
+ {
+ /* Swap pins on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_INVERT_HS_SIGNAL:
+ if (Lane == DSI_CLK_LANE)
+ {
+ /* Invert HS signal on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
+ }
+ else if (Lane == DSI_DATA_LANE0)
+ {
+ /* Invert HS signal on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
+ }
+ else if (Lane == DSI_DATA_LANE1)
+ {
+ /* Invert HS signal on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -1926,12 +2349,12 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
/**
* @brief Set custom timing for the PHY
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Timing PHY timing to be adjusted.
+ * @param Timing PHY timing to be adjusted.
* This parameter can be any value of @ref DSI_PHY_Timing
- * @param State ENABLE or DISABLE
- * @param Value Custom value of the timing
+ * @param State ENABLE or DISABLE
+ * @param Value Custom value of the timing
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
@@ -1943,127 +2366,127 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
assert_param(IS_DSI_PHY_TIMING(Timing));
assert_param(IS_FUNCTIONAL_STATE(State));
- switch(Timing)
+ switch (Timing)
{
- case DSI_TCLK_POST:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27);
+ case DSI_TCLK_POST:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;
- hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
+ hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
+ }
- break;
- case DSI_TLPX_CLK:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26);
+ break;
+ case DSI_TLPX_CLK:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;
- hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
+ hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
+ }
- break;
- case DSI_THS_EXIT:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25);
+ break;
+ case DSI_THS_EXIT:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;
- hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
+ hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
+ }
- break;
- case DSI_TLPX_DATA:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24);
+ break;
+ case DSI_TLPX_DATA:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;
- hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
+ hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
+ }
- break;
- case DSI_THS_ZERO:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23);
+ break;
+ case DSI_THS_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;
- hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
+ hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
+ }
- break;
- case DSI_THS_TRAIL:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22);
+ break;
+ case DSI_THS_TRAIL:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;
- hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
+ hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
+ }
- break;
- case DSI_THS_PREPARE:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21);
+ break;
+ case DSI_THS_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;
- hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
+ hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
+ }
- break;
- case DSI_TCLK_ZERO:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20);
+ break;
+ case DSI_TCLK_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;
- hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
+ hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
+ }
- break;
- case DSI_TCLK_PREPARE:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19);
+ break;
+ case DSI_TCLK_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
- if(State)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;
- hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
+ hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
+ }
- break;
- default:
- break;
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -2074,11 +2497,11 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
/**
* @brief Force the Clock/Data Lane in TX Stop Mode
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Lane select between clock or data lanes.
+ * @param Lane select between clock or data lanes.
* This parameter can be any value of @ref DSI_Lane_Group
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
@@ -2090,17 +2513,24 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane
assert_param(IS_DSI_LANE_GROUP(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
- if(Lane == DSI_CLOCK_LANE)
+ if (Lane == DSI_CLOCK_LANE)
{
/* Force/Unforce the Clock Lane in TX Stop Mode */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12);
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
}
- else if(Lane == DSI_DATA_LANES)
+ else if (Lane == DSI_DATA_LANES)
{
/* Force/Unforce the Data Lanes in TX Stop Mode */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13);
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
}
/* Process unlocked */
@@ -2110,10 +2540,10 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane
}
/**
- * @brief Forces LP Receiver in Low-Power Mode
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @brief Force LP Receiver in Low-Power Mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
@@ -2125,8 +2555,8 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta
assert_param(IS_FUNCTIONAL_STATE(State));
/* Force/Unforce LP Receiver in Low-Power Mode */
- hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;
- hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22);
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
+ hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -2136,9 +2566,9 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta
/**
* @brief Force Data Lanes in RX Mode after a BTA
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
@@ -2150,8 +2580,8 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional
assert_param(IS_FUNCTIONAL_STATE(State));
/* Force Data Lanes in RX Mode */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16);
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -2161,9 +2591,9 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional
/**
* @brief Enable a pull-down on the lanes to prevent from floating states when unused
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
@@ -2175,8 +2605,8 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S
assert_param(IS_FUNCTIONAL_STATE(State));
/* Enable/Disable pull-down on lanes */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18);
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -2186,9 +2616,9 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S
/**
* @brief Switch off the contention detection on data lanes
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
@@ -2200,8 +2630,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
assert_param(IS_FUNCTIONAL_STATE(State));
/* Contention Detection on Data Lanes OFF */
- hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;
- hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14);
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -2214,8 +2644,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
*/
/** @defgroup DSI_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -2231,7 +2661,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
/**
* @brief Return the DSI state
- * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL state
*/
@@ -2240,6 +2670,18 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
return hdsi->State;
}
+/**
+ * @brief Return the DSI error code
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval DSI Error Code
+ */
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+{
+ /* Get the error code */
+ return hdsi->ErrorCode;
+}
+
/**
* @}
*/
@@ -2247,12 +2689,15 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
/**
* @}
*/
-#endif /*STM32F769xx | STM32F779xx */
-#endif /* HAL_DSI_MODULE_ENABLED */
+
/**
* @}
*/
+#endif /* DSI */
+
+#endif /* HAL_DSI_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
index 17418d555420d6bf2b9f345d7ba16874305919ca..2b9039ae464e6bbf923e6b6c2318f26aabf91773 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
@@ -62,33 +62,66 @@
(#) Configure the Ethernet DMA after ETH peripheral initialization
HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
+*** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+ or HAL_ETH_Init function.
+
+ When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -137,6 +170,9 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
@@ -192,8 +228,20 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ ETH_InitCallbacksToDefault(heth);
+
+ if(heth->MspInitCallback == NULL)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ }
+ heth->MspInitCallback(heth);
+
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Enable SYSCFG Clock */
@@ -447,8 +495,17 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ if(heth->MspDeInitCallback == NULL)
+ {
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ }
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+ heth->MspDeInitCallback(heth);
+#else
/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspDeInit(heth);
+#endif
/* Set ETH HAL state to Disabled */
heth->State= HAL_ETH_STATE_RESET;
@@ -629,6 +686,173 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
*/
}
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ETH Callback
+ * To be used instead of the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->State == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an ETH Callback
+ * ETH callabck is redirected to the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->State == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -946,8 +1170,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Receive complete callback*/
+ heth->RxCpltCallback(heth);
+#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
@@ -962,8 +1191,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call resgistered Transfer complete callback*/
+ heth->TxCpltCallback(heth);
+#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
@@ -981,8 +1215,12 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ heth->DMAErrorCallback(heth);
+#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
@@ -1023,7 +1261,7 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
+ the HAL_ETH_RxCpltCallback could be implemented in the user file
*/
}
@@ -1039,7 +1277,7 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
+ the HAL_ETH_ErrorCallback could be implemented in the user file
*/
}
@@ -2026,6 +2264,16 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
(heth->Instance)->DMAOMR = tmpreg;
}
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+ /* Init the ETH Callback settings */
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_exti.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_exti.c
new file mode 100644
index 0000000000000000000000000000000000000000..869b8a90a7c4843119bd0189d74d8e6165ba3ecd
--- /dev/null
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_exti.c
@@ -0,0 +1,451 @@
+/**
+ ******************************************************************************
+ * @file stm32F7xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two different
+ interrupts pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+#include "stm32f7xx_hal_exti.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ uint32_t regval;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~pExtiConfig->Line;
+ EXTI->EMR &= ~pExtiConfig->Line;
+
+ /* Select the Mode for the selected external interrupts */
+ regval = (uint32_t)EXTI_BASE;
+ regval += pExtiConfig->Mode;
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~pExtiConfig->Line;
+ EXTI->FTSR &= ~pExtiConfig->Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= pExtiConfig->Line;
+ EXTI->FTSR |= pExtiConfig->Line;
+ }
+ else
+ {
+ regval = (uint32_t)EXTI_BASE;
+ regval += pExtiConfig->Trigger;
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configuration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* Get EXTI mode to configiguration structure */
+ if ((EXTI->IMR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ }
+ else if ((EXTI->EMR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Mode = EXTI_MODE_EVENT;
+ }
+ else
+ {
+ /* No MODE selected */
+ pExtiConfig->Mode = 0x0Bu;
+ }
+
+ /* Get EXTI Trigger to configiguration structure */
+ if ((EXTI->RTSR & hexti->Line) == hexti->Line)
+ {
+ if ((EXTI->FTSR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
+ }
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+ }
+ else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
+ }
+ else
+ {
+ /* No Trigger selected */
+ pExtiConfig->Trigger = 0x00u;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* 1] Clear interrupt mode */
+ EXTI->IMR = (EXTI->IMR & ~hexti->Line);
+
+ /* 2] Clear event mode */
+ EXTI->EMR = (EXTI->EMR & ~hexti->Line);
+
+ /* 3] Clear triggers */
+ EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
+ EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Register callback for a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->PendingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+
+ /* Get pending bit */
+ regaddr = (&EXTI->PR);
+ regval = (*regaddr & hexti->Line);
+
+ if (regval != 0x00u)
+ {
+ /* Clear pending bit */
+ *regaddr = hexti->Line;
+
+ /* Call callback */
+ if (hexti->PendingCallback != NULL)
+ {
+ hexti->PendingCallback();
+ }
+ }
+}
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* Get pending bit */
+ regaddr = &EXTI->PR;
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
+
+ return regval;
+}
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* Clear Pending bit */
+ EXTI->PR = hexti->Line;
+}
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ EXTI->SWIER = hexti->Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash.c
index 36f29d6e3be65d446781c9379725f560b2dc940d..29dc54e481ece4d143815fb99e415657b35e92a1 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash.c
@@ -70,29 +70,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash_ex.c
index 3acd6dd082cfb166ab1476680a64eb4ab68947c4..675814150b37028c0d80583589693578ebffee4b 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_flash_ex.c
@@ -42,29 +42,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_gpio.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_gpio.c
index 89e59b307859fc333315f52184e1a449250d09d5..8fc358313578a36408afb4de4932d56972309a44 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_gpio.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_gpio.c
@@ -93,29 +93,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -327,22 +311,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
if(iocurrent == ioposition)
{
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floating Mode */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
@@ -359,7 +327,22 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
- }
+ }
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floating Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
}
}
}
@@ -448,7 +431,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- GPIOx->ODR ^= GPIO_Pin;
+ if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ }
+ else
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash.c
index a1a5b0957305e6bf7cf125f6d9ed6e1bce3f18b2..bb335409456e3e10ca5a4d729c5c2a673f180459 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash.c
@@ -5,90 +5,160 @@
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
- * + Initialization and de-initialization functions
- * + HASH/HMAC Processing functions by algorithm using polling mode
- * + HASH/HMAC functions by algorithm using interrupt mode
- * + HASH/HMAC functions by algorithm using DMA mode
- * + Peripheral State functions
+ * + Initialization and de-initialization methods
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * + Peripheral State methods
+ * + HASH or HMAC processing suspension/resumption
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
[..]
The HASH HAL driver can be used as follows:
+
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
- (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
+ (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream one for managing data transfer from
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+ (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
+ (+++) Enable the DMAx interface clock using
+ __DMAx_CLK_ENABLE()
+ (+++) Configure and enable one DMA stream to manage data transfer from
memory to peripheral (input stream). Managing data transfer from
- peripheral to memory can be performed only using CPU
+ peripheral to memory can be performed only using CPU.
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
- (##) For HMAC, the encryption key.
- (##) For HMAC, the key size used for encryption.
- (#)Three processing functions are available:
+ interrupt on the DMA Stream: use
+ HAL_NVIC_SetPriority() and
+ HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+ (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+ (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
+
+ (#)Three processing schemes are available:
(##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished
- e.g. HAL_HASH_SHA1_Start()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_HASH_SHA1_Start_IT()
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
(##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA
- e.g. HAL_HASH_SHA1_Start_DMA()
- (#)When the processing function is called at first time after HAL_HASH_Init()
- the HASH peripheral is initialized and processes the buffer in input.
- After that, the digest computation is started.
- When processing multi-buffer use the accumulate function to write the
- data in the peripheral without starting the digest computation. In last
- buffer use the start function to input the last buffer ans start the digest
- computation.
- (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
- (##) write (n-1)th data buffer in the peripheral without starting the digest computation
- (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
- (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
- (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
- After that, call the finish function in order to get the digest value
- e.g. HAL_HASH_SHA1_Finish()
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
+ for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
+ is then required to retrieve the digest.
+
+ (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
+ initialized and processes the buffer fed in input. When the input data have all been
+ fed to the IP, the digest computation can start.
+
+ (#)Multi-buffer processing is possible in polling and DMA mode.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASH_xxx_Finish().
+ (+++) HMAC processing (requires to resort to extended functions):
+ after initialization, the key and the first input buffer are entered
+ in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
+
+
+ (#)Context swapping.
+ (##) Two APIs are available to suspend HASH or HMAC processing:
+ (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
+ (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
+
+ (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
+ to save in memory the IP context. This context can be restored afterwards
+ to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
+
+ (##) Once the HASH IP has been restored to the same configuration as that at suspension
+ time, processing can be restarted with the same API call (same API, same handle,
+ same parameters) as done before the suspension. Relevant parameters to restart at
+ the proper location are internally saved in the HASH handle.
+
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+
+ (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
+ and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
+ or @ref HAL_HASH_Init function.
+
+ When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -96,226 +166,86 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+#if defined (HASH)
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
-
-/** @defgroup HASH HASH
+/** @defgroup HASH HASH
* @brief HASH HAL module driver.
* @{
*/
+
#ifdef HAL_HASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/** @defgroup HASH_Private_Constants HASH Private Constants
* @{
*/
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
+
+/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
+ * @{
+ */
+#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
+#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup HASH_Private_Functions
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
* @{
*/
-
+#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */
/**
- * @brief DMA HASH Input Data complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @}
*/
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0;
- uint32_t buffersize = 0;
-
- if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* Increment Interrupt counter */
- hhash->HashInCount++;
- /* Disable the DMA transfer before starting the next transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- if(hhash->HashInCount <= 2)
- {
- /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
- if(hhash->HashInCount == 1)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- buffersize = hhash->HashBuffSize;
- }
- /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
- else if(hhash->HashInCount == 2)
- {
- inputaddr = (uint32_t)hhash->Init.pKey;
- buffersize = hhash->Init.KeySize;
- }
- /* Configure the number of valid bits in last word of the message */
- MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
-
- /* Set the HASH DMA transfer complete */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
- }
- else
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Reset the InCount */
- hhash->HashInCount = 0;
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-}
+/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
+ * @{
+ */
+#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */
/**
- * @brief DMA HASH communication error callback.
- * @param hdma DMA handle
- * @retval None
+ * @}
*/
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hhash->State= HAL_HASH_STATE_READY;
- HAL_HASH_ErrorCallback(hhash);
-}
+/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
+ * @{
+ */
+#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */
/**
- * @brief Writes the input buffer in data register.
- * @param pInBuffer Pointer to input buffer
- * @param Size The size of input buffer
- * @retval None
+ * @}
*/
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t buffercounter;
- uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
-}
/**
- * @brief Provides the message digest result.
- * @param pMsgDigest Pointer to the message digest
- * @param Size The size of the message digest in bytes
- * @retval None
+ * @}
*/
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- case 16:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
- case 20:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- case 28:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- break;
- case 32:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
- break;
- default:
- break;
- }
-}
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HASH_Exported_Functions
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
-
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization, configuration and call-back functions.
*
@verbatim
===============================================================================
@@ -323,67 +253,108 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the HASH according to the specified parameters
- in the HASH_InitTypeDef and creates the associated handle.
- (+) DeInitialize the HASH peripheral.
- (+) Initialize the HASH MSP.
- (+) DeInitialize HASH MSP.
+ in the HASH_InitTypeDef and create the associated handle
+ (+) DeInitialize the HASH peripheral
+ (+) Initialize the HASH MCU Specific Package (MSP)
+ (+) DeInitialize the HASH MSP
+
+ [..] This section provides as well call back functions definitions for user
+ code to manage:
+ (+) Input data transfer to IP completion
+ (+) Calculated digest retrieval completion
+ (+) Error management
+
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the HASH according to the specified parameters in the
- HASH_HandleTypeDef and creates the associated handle.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Initialize the HASH according to the specified parameters in the
+ HASH_HandleTypeDef and create the associated handle.
+ * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+ * other configuration bits are set by HASH or HMAC processing APIs.
+ * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
+ * multi-buffer HASH processing, user needs to resort to
+ * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
+ * relevant APIs manage themselves the MDMAT bit.
+ * @param hhash: HASH handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+
/* Check the hash handle allocation */
if(hhash == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if (hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+
+ /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ if(hhash->MspInitCallback == NULL)
+ {
+ hhash->MspInitCallback = HAL_HASH_MspInit;
+ }
+ /* Init the low level hardware */
+ hhash->MspInitCallback(hhash);
+ }
+#else
if(hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_HASH_MspInit(hhash);
}
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+ /* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
- /* Reset HashInCount, HashBuffSize and HashITCounter */
+ /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
hhash->HashInCount = 0;
hhash->HashBuffSize = 0;
hhash->HashITCounter = 0;
+ hhash->NbWordsAlreadyPushed = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+ /* Set phase to READY */
+ hhash->Phase = HAL_HASH_PHASE_READY;
- /* Set the data type */
- HASH->CR |= (uint32_t) (hhash->Init.DataType);
+ /* Set the data type bit */
+ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
+ /* Reset MDMAT bit */
+__HAL_HASH_RESET_MDMAT();
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
- /* Change the HASH state */
+ /* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_READY;
- /* Set the default HASH phase */
- hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
- * @brief DeInitializes the HASH peripheral.
- * @note This API must be called before starting a new processing.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief DeInitialize the HASH peripheral.
+ * @param hhash: HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -400,28 +371,43 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
/* Set the default HASH phase */
hhash->Phase = HAL_HASH_PHASE_READY;
- /* Reset HashInCount, HashBuffSize and HashITCounter */
+ /* Reset HashInCount, HashITCounter and HashBuffSize */
hhash->HashInCount = 0;
hhash->HashBuffSize = 0;
hhash->HashITCounter = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if(hhash->MspDeInitCallback == NULL)
+ {
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+ }
- /* DeInit the low level hardware */
+ /* DeInit the low level hardware */
+ hhash->MspDeInitCallback(hhash);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
HAL_HASH_MspDeInit(hhash);
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
+
+ /* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hhash);
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the HASH MSP.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Initialize the HASH MSP.
+ * @param hhash: HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@@ -429,15 +415,14 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspInit() can be implemented in the user file.
*/
}
/**
- * @brief DeInitializes HASH MSP.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief DeInitialize the HASH MSP.
+ * @param hhash: HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@@ -445,258 +430,1375 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspDeInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspDeInit() can be implemented in the user file.
*/
}
/**
- * @brief Input data transfer complete callback.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Input data transfer complete call back.
+ * @note HAL_HASH_InCpltCallback() is called when the complete input message
+ * has been fed to the IP. This API is invoked only when input data are
+ * entered under interruption or thru DMA.
+ * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
+ * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
+ * to the IP.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_InCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_InCpltCallback() can be implemented in the user file.
*/
}
/**
- * @brief Data transfer Error callback.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Digest computation complete call back.
+ * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
+ * relevant with DMA.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_ErrorCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_DgstCpltCallback() can be implemented in the user file.
*/
}
/**
- * @brief Digest computation complete callback. It is used only with interrupt.
- * @note This callback is not relevant with DMA.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Error callback.
+ * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+ * to retrieve the error type.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_DgstCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_ErrorCallback() can be implemented in the user file.
*/
}
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
- * @brief processing functions using polling mode
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using polling mode functions#####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
+ * @brief Register a User HASH Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
{
- uint32_t tickstart = 0;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
__HAL_LOCK(hhash);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(HAL_HASH_STATE_READY == hhash->State)
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
}
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ else if(HAL_HASH_STATE_RESET == hhash->State)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ switch (CallbackID)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
+ else
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
+ /* Release Lock */
__HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @retval HAL status
+ * @brief Unregister a HASH Callback
+ * HASH Callback is redirected to the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @retval status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
+HAL_StatusTypeDef status = HAL_OK;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Process locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(HAL_HASH_STATE_READY == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_HASH_STATE_RESET == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+ return status;
+}
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+/**
+ * @}
+ */
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @brief HASH processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start()
+ (++) HAL_HASH_MD5_Accumulate()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start()
+ (++) HAL_HASH_SHA1_Accumulate()
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the IP), the user can resort to successive calls
+ to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASH_xxx_Start().
- /* Return function status */
- return HAL_OK;
-}
+@endverbatim
+ * @{
+ */
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ * @brief HASH processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interruption mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_IT()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_IT()
+
+ [..] API HAL_HASH_IRQHandler() manages each HASH interruption.
+
+ [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+ HMAC processing mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief Handle HASH interrupt request.
+ * @param hhash: HASH handle.
+ * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
+ * @note In case of error reported during the HASH interruption processing,
+ * HAL_HASH_ErrorCallback() API is called so that user code can
+ * manage the error. The error type is available in hhash->Status field.
+ * @retval None
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ hhash->Status = HASH_IT(hhash);
+ if (hhash->Status != HAL_OK)
+ {
+ hhash->ErrorCode |= HAL_HASH_ERROR_IT;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ * @brief HASH processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_DMA()
+ (++) HAL_HASH_MD5_Finish()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_DMA()
+ (++) HAL_HASH_SHA1_Finish()
+
+ [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASH_xxx_Finish().
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Return the computed digest in MD5 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
+ * HMAC MD5 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @brief Return the computed digest in SHA1 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA1 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ * @brief HMAC processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start()
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ * @brief HMAC processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupt mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_IT()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_IT()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @brief HMAC processing functions using DMA modes.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_DMA()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State methods #####
+ ===============================================================================
+ [..]
+ This section permits to get in run-time the state and the peripheral handle
+ status of the peripheral:
+ (+) HAL_HASH_GetState()
+ (+) HAL_HASH_GetStatus()
+
+ [..]
+ Additionally, this subsection provides functions allowing to save and restore
+ the HASH or HMAC processing context in case of calculation suspension:
+ (+) HAL_HASH_ContextSaving()
+ (+) HAL_HASH_ContextRestoring()
+
+ [..]
+ This subsection provides functions allowing to suspend the HASH processing
+ (+) when input are fed to the IP by software
+ (++) HAL_HASH_SwFeed_ProcessSuspend()
+ (+) when input are fed to the IP by DMA
+ (++) HAL_HASH_DMAFeed_ProcessSuspend()
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HASH handle state.
+ * @note The API yields the current state of the handle (BUSY, READY,...).
+ * @param hhash: HASH handle.
+ * @retval HAL HASH state
+ */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+ return hhash->State;
+}
+
+
+/**
+ * @brief Return the HASH HAL status.
+ * @note The API yields the HAL status of the handle: it is the result of the
+ * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
+ * @param hhash: HASH handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+{
+ return hhash->Status;
+}
+
+/**
+ * @brief Save the HASH context in case of processing suspension.
+ * @param hhash: HASH handle.
+ * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * is saved.
+ * @note The IMR, STR, CR then all the CSR registers are saved
+ * in that order. Only the r/w bits are read to be restored later on.
+ * @note By default, all the context swap registers (there are
+ * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
+ * @note pMemBuffer points to a buffer allocated by the user. The buffer size
+ * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
+ * @retval None
+ */
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Save IMR register content */
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
+ mem_ptr+=4U;
+ /* Save STR register content */
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
+ mem_ptr+=4U;
+ /* Save CR register content */
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
+ mem_ptr+=4U;
+ /* By default, save all CSRs registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ {
+ *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
+ mem_ptr+=4U;
+ csr_ptr+=4U;
+ }
+}
+
+
+/**
+ * @brief Restore the HASH context in case of processing resumption.
+ * @param hhash: HASH handle.
+ * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * is stored.
+ * @note The IMR, STR, CR then all the CSR registers are restored
+ * in that order. Only the r/w bits are restored.
+ * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+ * of those) are restored (all of them have been saved by default
+ * beforehand).
+ * @retval None
+ */
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Restore IMR register content */
+ WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ /* Restore STR register content */
+ WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ /* Restore CR register content */
+ WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+
+ /* Reset the HASH processor before restoring the Context
+ Swap Registers (CSR) */
+ __HAL_HASH_INIT();
+
+ /* By default, restore all CSR registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ {
+ WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ csr_ptr+=4U;
+ }
+}
+
+
+/**
+ * @brief Initiate HASH processing suspension when in polling or interruption mode.
+ * @param hhash: HASH handle.
+ * @note Set the handle field SuspendRequest to the appropriate value so that
+ * the on-going HASH processing is suspended as soon as the required
+ * conditions are met. Note that the actual suspension is carried out
+ * by the functions HASH_WriteData() in polling mode and HASH_IT() in
+ * interruption mode.
+ * @retval None
+ */
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ /* Set Handle Suspend Request field */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND;
+}
+
+/**
+ * @brief Suspend the HASH processing when in DMA mode.
+ * @param hhash: HASH handle.
+ * @note When suspension attempt occurs at the very end of a DMA transfer and
+ * all the data have already been entered in the IP, hhash->State is
+ * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
+ * recommended to wrap-up the processing in reading the digest as usual.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ uint32_t tmp_remaining_DMATransferSize_inWords;
+ uint32_t tmp_initial_DMATransferSize_inWords;
+ uint32_t tmp_words_already_pushed;
+
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Make sure there is enough time to suspend the processing */
+ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+ if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
+ {
+ /* No suspension attempted since almost to the end of the transferred data. */
+ /* Best option for user code is to wrap up low priority message hashing */
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be reset */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable DMA channel */
+ if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK)
+ {
+ /*
+ Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ }
+
+ /* Clear DMAE bit */
+ CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* At this point, DMA interface is disabled and no transfer is on-going */
+ /* Retrieve from the DMA handle how many words remain to be written */
+ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+ if (tmp_remaining_DMATransferSize_inWords == 0U)
+ {
+ /* All the DMA transfer is actually done. Suspension occurred at the very end
+ of the transfer. Either the digest computation is about to start (HASH case)
+ or processing is about to move from one step to another (HMAC case).
+ In both cases, the processing can't be suspended at this point. It is
+ safer to
+ - retrieve the low priority block digest before starting the high
+ priority block processing (HASH case)
+ - re-attempt a new suspension (HMAC case)
+ */
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Compute how many words were supposed to be transferred by DMA */
+ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+
+ /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
+ by HASH IP, correct it */
+ /* tmp_words_already_pushed reflects the number of words that were already pushed before
+ the start of DMA transfer (multi-buffer processing case) */
+ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
+ if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED())
+ {
+ tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
+ }
+
+ /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+
+ /* And store in HashInCount the remaining size to transfer (in bytes) */
+ hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
+
+ }
+
+ /* Set State as suspended */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+
+ }
+}
+
+/**
+ * @brief Return the HASH handle error code.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure.
+ * @retval HASH Error Code
+*/
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+{
+ /* Return HASH Error Code */
+ return hhash->ErrorCode;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA HASH Input Data transfer completion callback.
+ * @param hdma: DMA handle.
+ * @note In case of HMAC processing, HASH_DMAXferCplt() initiates
+ * the next DMA transfer for the following HMAC step.
+ * @retval None
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t inputaddr;
+ uint32_t buffersize;
+ HAL_StatusTypeDef status ;
+
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+
+ /* Disable the DMA transfer */
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+ if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
+ {
+ /* If no HMAC processing, input data transfer is now over */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ }
+ else
+ {
+ /* HMAC processing: depending on the current HMAC step and whether or
+ not multi-buffer processing is on-going, the next step is initiated
+ and MDMAT bit is set. */
+
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+ {
+ /* This is the end of HMAC processing */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back
+ (note that the last DMA transfer was that of the key
+ for the outer HASH operation). */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ return;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
+ buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+ /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
+ no digest calculation will be triggered at the end of the input buffer feeding to the IP */
+ __HAL_HASH_SET_MDMAT();
+ }
+ }
+ else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
+ {
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+ (case of multi-buffer HMAC processing):
+ DCAL must not be set.
+ Phase remains in Step 2, MDMAT remains set at this point.
+ Change the HASH state to ready and call Input data transfer complete call back. */
+ hhash->State = HAL_HASH_STATE_READY;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ return ;
+ }
+ else
+ {
+ /* Digest calculation is not disabled (case of single buffer input or last buffer
+ of multi-buffer HMAC processing) */
+ inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */
+ buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+ }
+ }
+
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(buffersize);
+
+ /* Set the HASH DMA transfert completion call back */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hhash->State = HAL_HASH_STATE_READY;
+ }
+ }
+ }
+
+ return;
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma: DMA handle.
+ * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
+ * can contain user code to manage the error.
+ * @retval None
+ */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+ /* Set HASH state to ready to prevent any blocking issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State= HAL_HASH_STATE_READY;
+ /* Set HASH handle status to error */
+ hhash->Status = HAL_ERROR;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+
}
+}
+
+/**
+ * @brief Feed the input buffer to the HASH IP.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to input buffer.
+ * @param Size: the size of input buffer in bytes.
+ * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the IP feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+
+ for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+ {
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+ {
+ /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
+ in the input buffer */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Depending whether the key or the input data were fed to the IP, the feeding point
+ reached at suspension time is not saved in the same handle fields */
+ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashInCount = Size - (buffercounter + 4U);
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashKeyCount = Size - (buffercounter + 4U);
+ }
+ else
+ {
+ /* Unexpected phase: unlock process and report error */
+ hhash->State = HAL_HASH_STATE_READY;
+ __HAL_UNLOCK(hhash);
+ return HAL_ERROR;
+ }
+
+ /* Set the HASH state to Suspended and exit to stop entering data */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ return HAL_OK;
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
+ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ /* At this point, all the data have been entered to the IP: exit */
+ return HAL_OK;
+}
+
+/**
+ * @brief Retrieve the message digest.
+ * @param pMsgDigest: pointer to the computed digest.
+ * @param Size: message digest size in bytes.
+ * @retval None
+ */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+ switch(Size)
+ {
+ /* Read the message digest */
+ case 16: /* MD5 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ break;
+ case 20: /* SHA1 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28: /* SHA224 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ break;
+ case 32: /* SHA256 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+ break;
+ default:
+ break;
+ }
+}
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief Handle HASH processing Timeout.
+ * @param hhash: HASH handle.
+ * @param Flag: specifies the HASH flag to check.
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_HASH_GET_FLAG(Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hhash);
@@ -705,1159 +1807,1239 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
}
}
}
+ }
+ else
+ {
+ while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Return function status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
+ * @brief HASH processing in interruption mode.
+ * @param hhash: HASH handle.
+ * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the IP feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
{
- /* Check the parameters */
- assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ if (hhash->State == HAL_HASH_STATE_BUSY)
+ {
+ /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
+ if(hhash->HashITCounter == 0U)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ /* HASH state set back to Ready to prevent any issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (hhash->HashITCounter == 1U)
+ {
+ /* This is the first call to HASH_IT, the first input data are about to be
+ entered in the IP. A specific processing is carried out at this point to
+ start-up the processing. */
+ hhash->HashITCounter = 2U;
+ }
+ else
+ {
+ /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
+ the HASH processing or the end of the current step for HMAC processing. */
+ hhash->HashITCounter = 3U;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* If digest is ready */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
- }
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->DgstCpltCallback(hhash);
+#else
+ HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ return HAL_OK;
+ }
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ /* If IP ready to accept new data */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
- /* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+ }
-/**
- * @}
- */
+ /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+ check whether the digest calculation has been triggered */
+ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
+ {
+ /* Call Input data transfer complete call back
+ (called at the end of each step for HMAC) */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /* Wait until IP is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
+ hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Wait until IP is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
+ hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
-/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using interrupt mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @brief Write a block of data in HASH IP in interruption mode.
+ * @param hhash: HASH handle.
+ * @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
{
uint32_t inputaddr;
- uint32_t outputaddr;
uint32_t buffercounter;
uint32_t inputcounter;
+ uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* If there are more than 64 bytes remaining to be entered */
+ if(hhash->HashInCount > 64U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register
+ (16 32-bit words, or 64 bytes are entered) */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* If this is the start of input data entering, an additional word
+ must be entered to start up the HASH processing */
+ if(hhash->HashITCounter == 2U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ if(hhash->HashInCount >= 68U)
+ {
+ /* There are still data waiting to be entered in the IP.
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round. */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ /* All the input buffer has been fed to the HW. */
+ hhash->HashInCount = 0U;
+ }
+ }
+ else
+ {
+ /* 64 bytes have been entered and there are still some remaining:
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round.*/
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* 64 or less bytes remain to be entered. This is the last
+ data entering round. */
+
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Return indication that digest calculation has started:
+ this return value triggers the call to Input data transfer
+ complete call back as well as the proper transition from
+ one step to another in HMAC mode. */
+ ret = HASH_DIGEST_CALCULATION_STARTED;
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
- if(hhash->State == HAL_HASH_STATE_READY)
+ /* Return whether or digest calculation has started */
+ return ret;
+}
+
+/**
+ * @brief HMAC processing in polling mode.
+ * @param hhash: HASH handle.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+{
+ /* Ensure first that Phase is correct */
+ if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ hhash->State = HAL_HASH_STATE_READY;
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* HMAC Step 1 processing */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /************************** STEP 1 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
{
- /* Select the SHA1 mode */
- HASH->CR |= HASH_ALGOSELECTION_MD5;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
+ return hhash->Status;
}
- /* Reset interrupt counter */
- hhash->HashITCounter = 0;
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 1 to Step 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
- /* Return function status */
- return HAL_OK;
}
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+
+ /* HMAC Step 2 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 2 processing was suspended previously
+ - or fall through from the Step 1 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
-
- if(hhash->HashInCount == 0)
+ /************************** STEP 2 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
+ if (hhash->Status != HAL_OK)
{
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
+ return hhash->Status;
+ }
+ /* Check whether or not data entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
/* Process Unlocked */
__HAL_UNLOCK(hhash);
- /* Return function status */
+ /* Stop right there and return function status */
return HAL_OK;
}
+
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 2 to Step 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+ /* In case Step 1 phase was suspended then resumed,
+ set again Key input buffers and size before moving to
+ next step */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+ hhash->HashKeyCount = hhash->Init.KeySize;
}
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+
+ /* HMAC Step 3 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 3 processing was suspended previously
+ - or fall through from the Step 2 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
- if(hhash->HashInCount >= 68)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
+ /************************** STEP 3 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount = 0;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
}
- else
+
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
- else if ((inputcounter < 4) && (inputcounter != 0))
- {
- inputcounter = 4;
- }
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
+ /* No processing suspension at this point: start the Digest calculation. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
}
+
+ /* Read the message digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
}
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
- /* Return function status */
- return HAL_OK;
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Process Locked */
- __HAL_LOCK(hhash);
- if(hhash->State == HAL_HASH_STATE_READY)
+ /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
+ /* Check if initialization phase has not been already performed */
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- /* Select the SHA1 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA1;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Reset interrupt counter */
- hhash->HashITCounter = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
- outputaddr+=4;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
- if(hhash->HashInCount == 0)
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
- /* Disable Interrupts */
- HASH->IMR = 0;
+ /* if the IP has already been initialized, two cases are possible */
+
+ /* Process resumption time ... */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr;
+ Size_tmp = hhash->HashInCount;
+ }
+ /* ... or multi-buffer HASH processing end */
+ else
+ {
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer;
+ Size_tmp = Size;
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+ }
/* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Phase error */
hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
- return HAL_OK;
+ return HAL_ERROR;
}
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount = 0;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
}
- else
+
+ /* If the process has not been suspended, carry on to digest calculation */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
- else if ((inputcounter < 4) && (inputcounter != 0))
- {
- inputcounter = 4;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
+ return HAL_TIMEOUT;
}
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
- /* Return function status */
- return HAL_OK;
-}
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
-/**
- * @brief This function handles HASH interrupt request.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
-{
- switch(HASH->CR & HASH_CR_ALGO)
- {
- case HASH_ALGOSELECTION_MD5:
- HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
- break;
+ }
- case HASH_ALGOSELECTION_SHA1:
- HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
- break;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- default:
- break;
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
}
}
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
- control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
- /* Return function status */
- return HAL_OK;
-}
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
-/**
- * @brief Returns the computed digest in MD5 mode
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ }
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* Get tick */
- tickstart = HAL_GetTick();
+ }
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ return hhash->Status;
+ }
- return HAL_TIMEOUT;
- }
+ /* If the process has not been suspended, move the state to Ready */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
}
- }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1;
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Returns the computed digest in SHA1 mode.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
+ hhash->HashInCount = Size; /* Counter used to keep track of number of data
+ to be fed to the IP */
+ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
- /* Process Locked */
- __HAL_LOCK(hhash);
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ }
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* Get tick */
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- return HAL_TIMEOUT;
- }
- }
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
}
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using polling mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
+ (case of multi-buffer HASH processing) */
+ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ( (pInBuffer == NULL ) || (Size == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or PROCESS (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* If not a resumption case */
+ if (hhash->State == HAL_HASH_STATE_READY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Check if initialization phase has already been performed.
+ If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+ API is processing a new input data message in case of multi-buffer HASH
+ computation. */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- return HAL_TIMEOUT;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */
+ inputSize = Size; /* DMA transfer size (in bytes) */
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* In case of suspension request, save the starting parameters */
+ hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */
+ hhash->HashInCount = Size; /* DMA transfer size (in bytes) */
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ }
+ /* If resumption case */
+ else
{
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Resumption case, inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
+ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
- return HAL_TIMEOUT;
- }
}
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Set the HASH DMA transfert complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- return HAL_TIMEOUT;
- }
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
}
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Return the computed digest.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(hhash->State == HAL_HASH_STATE_READY)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
+ /* Check parameter */
+ if (pOutBuffer == NULL)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ return HAL_ERROR;
}
- }
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Change the HASH state to busy */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Return function status */
+ return HAL_OK;
- return HAL_TIMEOUT;
- }
- }
}
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+}
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
+ * @param Algorithm: HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
}
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- if((HAL_GetTick() - tickstart ) > Timeout)
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if(hhash->Init.KeySize > 64U)
{
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ /* Resort to hhash internal fields to feed the IP.
+ Parameters will be updated in case of suspension to contain the proper
+ information at resumption time. */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */
+ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */
+ hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
+ hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */
}
- }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Carry out HMAC processing */
+ return HMAC_Processing(hhash, Timeout);
- /* Return function status */
- return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- uint32_t inputaddr = 0;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if(hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+
+ /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
+ to feed the IP whatever the HMAC step.
+ Lines below are set to start HMAC Step 1 processing where key is entered first. */
+ hhash->HashInCount = hhash->Init.KeySize; /* Key size */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
+
+ /* Store input and output parameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */
+ hhash->HashBuffSize = Size; /* Input message size (in bytes) */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
+
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Restart IT-based HASH processing after Step 2 suspension */
+
}
else
{
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ /* Error report as phase incorrect */
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
}
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+}
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
-}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
+ * be a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * Only the length of the last buffer of the thread doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t inputaddr = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+ is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+ /* If State is ready or suspended, start or resume DMA-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or one of HMAC PROCESS steps (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
+ /* If not a case of resumption after suspension */
+ if (hhash->State == HAL_HASH_STATE_READY)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
+ /* Check whether or not initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+ At the same time, ensure MDMAT bit is cleared. */
+ if(hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ /* Store input aparameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
+ hhash->HashBuffSize = Size; /* input data size (in bytes) */
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
+ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Process a new input data message in case of multi-buffer HMAC processing
+ (this is not a resumption case) */
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Save input parameters to be able to manage possible suspension/resumption */
+ hhash->HashInCount = Size; /* Input message address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
- /* Return function status */
- return HAL_OK;
-}
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)pInBuffer; /* Input message address */
+ inputSize = Size; /* Input message size in bytes */
-/**
- * @}
- */
+ if (hhash->DigestCalculationDisable == RESET)
+ {
+ /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+ __HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ }
+ }
+ else
+ {
+ /* Phase not aligned with handle READY state */
+ __HAL_UNLOCK(hhash);
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Resumption case (phase may be Step 1, 2 or 3) */
-/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set DMA input parameters at resumption location;
+ inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended. */
+ inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */
+ inputSize = hhash->HashInCount; /* Input message size in bytes */
+ }
-@endverbatim
- * @{
- */
-/**
- * @brief return the HASH state
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval HAL state
- */
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
-{
- return hhash->State;
-}
+ /* Set the HASH DMA transfert complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
-/**
- * @}
- */
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ }
+ /* Return function status */
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
/**
* @}
*/
@@ -1867,10 +3049,11 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
+#endif /* HASH*/
/**
* @}
*/
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash_ex.c
index e1f1db4c53e1661be3cdff356fa53d1c48af7136..e666d0a1ce766966b2b696653de075e0854a92c0 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hash_ex.c
@@ -2,90 +2,76 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
- * @brief HASH HAL Extension module driver.
+ * @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of HASH peripheral:
- * + Extended HASH processing functions based on SHA224 Algorithm
- * + Extended HASH processing functions based on SHA256 Algorithm
+ * functionalities of the HASH peripheral for SHA-224 and SHA-256
+ * alogrithms:
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * Additionally, this file provides functions to manage HMAC
+ * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
+ * and SHA-256.
+ *
*
@verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
+ ##### HASH peripheral extended features #####
+ ===============================================================================
[..]
- The HASH HAL driver can be used as follows:
- (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
- (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
- (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream one for managing data transfer from
- memory to peripheral (input stream). Managing data transfer from
- peripheral to memory can be performed only using CPU
- (+++) Associate the initialized DMA handle to the HASH DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
- (##) For HMAC, the encryption key.
- (##) For HMAC, the key size used for encryption.
- (#)Three processing functions are available:
+ The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
+ the same way as for SHA-1 or MD-5 algorithms.
+ (#) Three modes are available.
(##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished
- e.g. HAL_HASHEx_SHA224_Start()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_HASHEx_SHA224_Start_IT()
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASHEx_xxx_Start()
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASHEx_xxx_Start_IT()
(##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA
- e.g. HAL_HASHEx_SHA224_Start_DMA()
- (#)When the processing function is called at first time after HAL_HASH_Init()
- the HASH peripheral is initialized and processes the buffer in input.
- After that, the digest computation is started.
- When processing multi-buffer use the accumulate function to write the
- data in the peripheral without starting the digest computation. In last
- buffer use the start function to input the last buffer ans start the digest
- computation.
- (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
- (##) write (n-1)th data buffer in the peripheral without starting the digest computation
- (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
- (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
- (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
- After that, call the finish function in order to get the digest value
- e.g. HAL_HASHEx_SHA224_Finish()
- (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
+ HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
+
+ (#)Multi-buffer processing is possible in polling and DMA mode.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASHEx_xxx_Finish().
+
+ (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
+ extended functions): after initialization, the key and the first input buffer are entered
+ in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
+ MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -93,1530 +79,825 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+
+
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined (STM32F750xx)
+#if defined (HASH)
/** @defgroup HASHEx HASHEx
- * @brief HASH Extension HAL module driver.
+ * @brief HASH HAL extended module driver.
* @{
*/
-
#ifdef HAL_HASH_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup HASHEx_Private_Functions
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
-static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
-static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
+ * @brief HASH extended processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start()
+ (++) HAL_HASHEx_SHA224_Accumulate()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start()
+ (++) HAL_HASHEx_SHA256_Accumulate()
+
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
-/** @addtogroup HASHEx_Private_Functions
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the IP), the user can resort to successive calls
+ to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASHEx_xxx_Start().
+
+@endverbatim
* @{
*/
+
/**
- * @brief Writes the input buffer in data register.
- * @param pInBuffer Pointer to input buffer
- * @param Size The size of input buffer
- * @retval None
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
*/
-static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t buffercounter;
- uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Provides the message digest result.
- * @param pMsgDigest Pointer to the message digest
- * @param Size The size of the message digest in bytes
- * @retval None
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
*/
-static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- case 16:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
- case 20:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- case 28:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- break;
- case 32:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- msgdigest+=4;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
- break;
- default:
- break;
- }
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief DMA HASH Input Data complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
*/
-static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0;
- uint32_t buffersize = 0;
-
- if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* Increment Interrupt counter */
- hhash->HashInCount++;
- /* Disable the DMA transfer before starting the next transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- if(hhash->HashInCount <= 2)
- {
- /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
- if(hhash->HashInCount == 1)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- buffersize = hhash->HashBuffSize;
- }
- /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
- else if(hhash->HashInCount == 2)
- {
- inputaddr = (uint32_t)hhash->Init.pKey;
- buffersize = hhash->Init.KeySize;
- }
- /* Configure the number of valid bits in last word of the message */
- MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
-
- /* Set the HASH DMA transfer complete */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
- }
- else
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Reset the InCount */
- hhash->HashInCount = 0;
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
- * @brief DMA HASH communication error callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
*/
-static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hhash->State= HAL_HASH_STATE_READY;
- HAL_HASH_ErrorCallback(hhash);
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
- /**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HASHEx_Exported_Functions
- * @{
+/**
+ * @}
*/
-/** @defgroup HASHEx_Group1 HASH processing functions
- * @brief processing functions using polling mode
+/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
+ * @brief HASH extended processing functions using interrupt mode.
*
@verbatim
===============================================================================
- ##### HASH processing using polling mode functions #####
+ ##### Interruption mode HASH extended processing functions #####
===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
+ [..] This section provides functions allowing to calculate in interrupt mode
the hash value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_IT()
(+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_IT()
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout Specify Timeout value
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout Specify Timeout value
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+}
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+/**
+ * @}
+ */
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
+/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
+ * @brief HASH extended processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH extended processing functionss #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_DMA()
+ (++) HAL_HASHEx_SHA224_Finish()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_DMA()
+ (++) HAL_HASHEx_SHA256_Finish()
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASHEx_xxx_Finish().
- /* Get tick */
- tickstart = HAL_GetTick();
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASHEx_xxx_Finish().
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
+@endverbatim
+ * @{
+ */
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
-
/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Return the computed digest in SHA224 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA224 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
-
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
+/**
+ * @brief Return the computed digest in SHA256 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA256 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
/**
* @}
*/
-/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
+/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
+ * @brief HMAC extended processing functions using polling mode.
*
@verbatim
===============================================================================
- ##### HMAC processing using polling mode functions #####
+ ##### Polling mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start()
@endverbatim
* @{
*/
+
+
/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
-/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
+
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
+ * @brief HMAC extended processing functions using interruption mode.
*
@verbatim
===============================================================================
- ##### HASH processing using interrupt functions #####
+ ##### Interrupt mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
+ the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_IT()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_IT()
@endverbatim
* @{
*/
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA224;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
- /* Reset interrupt counter */
- hhash->HashITCounter = 0;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount = 0;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
- else if ((inputcounter < 4) && (inputcounter != 0))
- {
- inputcounter = 4;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA256;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Reset interrupt counter */
- hhash->HashITCounter = 0;
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
- if(hhash->HashInCount == 0)
- {
- /* Disable Interrupts */
- HASH->IMR = 0;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- if(hhash->HashITCounter == 0)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68;
- hhash->pHashInBuffPtr+= 68;
- }
- else
- {
- hhash->HashInCount = 0;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64;
- hhash->pHashInBuffPtr+= 64;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4) && (inputcounter%4))
- {
- inputcounter = (inputcounter+4-inputcounter%4);
- }
- else if ((inputcounter < 4) && (inputcounter != 0))
- {
- inputcounter = 4;
- }
-
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief This function handles HASH interrupt request.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
*/
-void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- switch(HASH->CR & HASH_CR_ALGO)
- {
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}
- case HASH_ALGOSELECTION_SHA224:
- HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);
- break;
- case HASH_ALGOSELECTION_SHA256:
- HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);
- break;
- default:
- break;
- }
-}
/**
* @}
*/
-/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions using DMA mode.
*
@verbatim
===============================================================================
- ##### HASH processing using DMA functions #####
+ ##### DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
+ the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_DMA()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASHEx_xxx_Finish().
+
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Process Locked */
- __HAL_LOCK(hhash);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+/**
+ * @}
+ */
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
+/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions in multi-buffer DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Multi-buffer DMA mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions to manage HMAC multi-buffer
+ DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
+ (+) MD5
+ (++) HAL_HMACEx_MD5_Step1_2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_3_DMA()
+ (+) SHA1
+ (++) HAL_HMACEx_SHA1_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_3_DMA()
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ (+) SHA256
+ (++) HAL_HMACEx_SHA224_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_3_DMA()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_3_DMA()
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ [..] User must first start-up the multi-buffer DMA-based HMAC computation in
+ calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ intiates step 2 with the first input buffer.
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+ [..] The following buffers are next fed to the IP with a call to the API
+ HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
+ to this API.
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+ [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
+ HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
+ buffer to the IP then carries out step 3.
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
+ SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ [..] If only two buffers need to be consecutively processed, a call to
+ HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
+ is sufficient.
- /* Return function status */
- return HAL_OK;
-}
+@endverbatim
+ * @{
+ */
/**
- * @brief Returns the computed digest in SHA224
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout Timeout value
+ * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief MD5 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ return HAL_ERROR;
}
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
- * @brief Returns the computed digest in SHA256.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout Timeout value
+ * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+/**
+ * @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
+ return HAL_ERROR;
}
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
-
/**
- * @}
+ * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
*/
-/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
-@endverbatim
- * @{
+/**
+ * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
+ return HAL_ERROR;
}
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0;
+/**
+ * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+/**
+ * @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
+ return HAL_ERROR;
}
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
+
/**
* @}
*/
@@ -1625,10 +906,11 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
+#endif /* HASH*/
/**
* @}
*/
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hcd.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hcd.c
index 690c4e0b02815aa0743d25f412f33bcedb07c6b3..92a6277ed153fa75f1572f747823f8090d06f057 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hcd.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_hcd.c
@@ -44,27 +44,15 @@
*
* © COPYRIGHT(c) 2017 STMicroelectronics
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * @attention
+ *
+ * © Copyright (c) YYYY STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -76,13 +64,15 @@
* @{
*/
+#ifdef HAL_HCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
-#ifdef HAL_HCD_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -125,7 +115,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
- if(hhcd == NULL)
+ if (hhcd == NULL)
{
return HAL_ERROR;
}
@@ -133,13 +123,30 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
- if(hhcd->State == HAL_HCD_STATE_RESET)
+ if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhcd->Lock = HAL_UNLOCKED;
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+ if (hhcd->MspInitCallback == NULL)
+ {
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hhcd->MspInitCallback(hhcd);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
}
hhcd->State = HAL_HCD_STATE_BUSY;
@@ -156,7 +163,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Init Host */
(void)USB_HostInit(hhcd->Instance, hhcd->Init);
- hhcd->State= HAL_HCD_STATE_READY;
+ hhcd->State = HAL_HCD_STATE_READY;
return HAL_OK;
}
@@ -252,15 +259,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
- if(hhcd == NULL)
+ if (hhcd == NULL)
{
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_BUSY;
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ if (hhcd->MspDeInitCallback == NULL)
+ {
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
/* DeInit the low level hardware */
+ hhcd->MspDeInitCallback(hhcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_DISABLE(hhcd);
@@ -346,7 +363,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t direction,
uint8_t ep_type,
uint8_t token,
- uint8_t* pbuff,
+ uint8_t *pbuff,
uint16_t length,
uint8_t do_ping)
{
@@ -355,7 +372,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
- if(token == 0U)
+ if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
}
@@ -365,86 +382,93 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
/* Manage Data Toggle */
- switch(ep_type)
+ switch (ep_type)
{
- case EP_TYPE_CTRL:
- if((token == 1U) && (direction == 0U)) /*send data */
- {
- if (length == 0U)
- { /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1U;
- }
+ case EP_TYPE_CTRL:
+ if ((token == 1U) && (direction == 0U)) /*send data */
+ {
+ if (length == 0U)
+ {
+ /* For Status OUT stage, Length==0, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1U;
+ }
- /* Set the Data Toggle bit as per the Flag */
- if (hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- break;
+ break;
- case EP_TYPE_BULK:
- if(direction == 0U)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0U)
+ case EP_TYPE_BULK:
+ if (direction == 0U)
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
else
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- break;
- case EP_TYPE_INTR:
- if(direction == 0U)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0U)
+ break;
+ case EP_TYPE_INTR:
+ if (direction == 0U)
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
else
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- break;
+ break;
- case EP_TYPE_ISOC:
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
+ case EP_TYPE_ISOC:
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ break;
- default:
- break;
+ default:
+ break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
@@ -472,64 +496,74 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
/* Avoid spurious interrupt */
- if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle Host Disconnect Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
/* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
- /* Handle Host Port Interrupts */
+ /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->DisconnectCallback(hhcd);
+#else
HAL_HCD_Disconnect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
/* Handle Host Port Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
{
- HCD_Port_IRQHandler (hhcd);
+ HCD_Port_IRQHandler(hhcd);
}
- /* Handle Host SOF Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+ /* Handle Host SOF Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
{
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback(hhcd);
+#else
HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
- /* Handle Host channel Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+ /* Handle Host channel Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
for (i = 0U; i < hhcd->Init.Host_channels; i++)
@@ -542,7 +576,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
}
else
{
- HCD_HC_OUT_IRQHandler (hhcd, (uint8_t)i);
+ HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
}
}
}
@@ -550,11 +584,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
}
/* Handle Rx Queue Level Interrupts */
- if((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- HCD_RXQLVL_IRQHandler (hhcd);
+ HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
@@ -663,6 +697,282 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
*/
}
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB HCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB HCD Callback
+ * USB HCD callabck is redirected to the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Register USB HCD Host Channel Notify URB Change Callback
+ * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback
+ * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -841,7 +1151,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
* This parameter can be a value from 1 to 15
* @retval none
*/
-static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -890,25 +1200,30 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
if (hhcd->Init.dma_enable != 0U)
{
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
- (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[ch_num].state = HC_XFRC;
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
- if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
- else if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
@@ -921,7 +1236,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
__HAL_HCD_MASK_HALT_HC_INT(ch_num);
- if(hhcd->hc[ch_num].state == HC_XFRC)
+ if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
}
@@ -929,11 +1244,11 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
}
- else if((hhcd->hc[ch_num].state == HC_XACTERR) ||
- (hhcd->hc[ch_num].state == HC_DATATGLERR))
+ else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
- if(hhcd->hc[ch_num].ErrCnt > 3U)
+ if (hhcd->hc[ch_num].ErrCnt > 3U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
@@ -975,22 +1290,22 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
- if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+ if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
- else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||
+ else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
- hhcd->hc[ch_num].ErrCnt = 0U;
- if (hhcd->Init.dma_enable == 0U)
- {
- hhcd->hc[ch_num].state = HC_NAK;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- }
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].state = HC_NAK;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
}
else
{
@@ -1011,7 +1326,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
* This parameter can be a value from 1 to 15
* @retval none
*/
-static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1027,7 +1342,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
- if( hhcd->hc[ch_num].do_ping == 1U)
+ if (hhcd->hc[ch_num].do_ping == 1U)
{
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
@@ -1039,7 +1354,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
- hhcd->hc[ch_num].ErrCnt= 0U;
+ hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
@@ -1087,7 +1402,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[ch_num].state = HC_XACTERR;
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
@@ -1104,7 +1419,8 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
- if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}
@@ -1122,7 +1438,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
- (hhcd->hc[ch_num].state == HC_DATATGLERR))
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 3U)
@@ -1151,7 +1467,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
else
{
- /* ... */
+ /* ... */
}
}
@@ -1160,7 +1476,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
* @param hhcd HCD handle
* @retval none
*/
-static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1177,35 +1493,35 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
switch (pktsts)
{
- case GRXSTS_PKTSTS_IN:
- /* Read the data into the host buffer. */
- if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
- {
- (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+ case GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
+ {
+ (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
- /*manage multiple Xfer */
- hhcd->hc[ch_num].xfer_buff += pktcnt;
- hhcd->hc[ch_num].xfer_count += pktcnt;
+ /*manage multiple Xfer */
+ hhcd->hc[ch_num].xfer_buff += pktcnt;
+ hhcd->hc[ch_num].xfer_count += pktcnt;
- if((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
- {
- /* re-activate the channel when more packets are expected */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
- hhcd->hc[ch_num].toggle_in ^= 1U;
+ if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
+ {
+ /* re-activate the channel when more packets are expected */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
}
- }
- break;
+ break;
- case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
- break;
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ break;
- case GRXSTS_PKTSTS_IN_XFER_COMP:
- case GRXSTS_PKTSTS_CH_HALTED:
- default:
- break;
+ case GRXSTS_PKTSTS_IN_XFER_COMP:
+ case GRXSTS_PKTSTS_CH_HALTED:
+ default:
+ break;
}
}
@@ -1214,7 +1530,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
* @param hhcd HCD handle
* @retval None
*/
-static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1224,28 +1540,33 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
hprt0 = USBx_HPRT0;
hprt0_dup = USBx_HPRT0;
- hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
/* Check whether Port Connect detected */
- if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+ if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
{
- if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+ if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->ConnectCallback(hhcd);
+#else
HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
}
/* Check whether Port Enable Changed */
- if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+ if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
- if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+ if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
- if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
+ if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{
@@ -1258,29 +1579,38 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
}
else
{
- if(hhcd->Init.speed == HCD_SPEED_FULL)
+ if (hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = 60000U;
}
}
-
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortEnabledCallback(hhcd);
+ hhcd->ConnectCallback(hhcd);
+#else
HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
}
else
{
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortDisabledCallback(hhcd);
+#else
HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}
/* Check for an overcurrent */
- if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+ if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
}
@@ -1297,7 +1627,9 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
* @}
*/
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_HCD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c.c
index 15e7e6e8935674c52b4d9844c0e6a22dca1c3d72..d74bb1dd4afdf1fe59cc59fca50df57d723eaca1 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c.c
@@ -19,7 +19,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -39,54 +39,54 @@
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
- *** Interrupt mode IO sequential operation ***
- ==============================================
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
@@ -98,7 +98,8 @@
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
+ several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
@@ -107,94 +108,104 @@
if no direction change and with a final stop condition in both cases
(++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
- Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+ or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+ or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ @ref HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ @ref HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ @ref HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ @ref HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ @ref HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ @ref HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ @ref HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ @ref HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -202,13 +213,78 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+
+ Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+
+ By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+ or @ref HAL_I2C_Init() function.
+
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -217,29 +293,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -280,14 +340,14 @@
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
@@ -306,10 +366,6 @@
*/
/* Private macro -------------------------------------------------------------*/
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -326,8 +382,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
@@ -351,14 +407,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-/* Private functions to flush TXDR register */
+/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-/* Private functions to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/* Private function to handle start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
@@ -430,8 +489,30 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ /* Init the I2C Callback settings */
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hi2c->MspInitCallback == NULL)
+ {
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hi2c->MspInitCallback(hi2c);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
@@ -510,8 +591,18 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ if (hi2c->MspDeInitCallback == NULL)
+ {
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hi2c->MspDeInitCallback(hi2c);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_RESET;
@@ -556,6 +647,328 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
*/
}
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User I2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2C Callback
+ * I2C callback is redirected to the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match I2C Callback
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match I2C Callback
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -597,6 +1010,13 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Slave_Receive_IT()
(++) HAL_I2C_Mem_Write_IT()
(++) HAL_I2C_Mem_Read_IT()
+ (++) HAL_I2C_Master_Seq_Transmit_IT()
+ (++) HAL_I2C_Master_Seq_Receive_IT()
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()
+ (++) HAL_I2C_Slave_Seq_Receive_IT()
+ (++) HAL_I2C_EnableListen_IT()
+ (++) HAL_I2C_DisableListen_IT()
+ (++) HAL_I2C_Master_Abort_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2C_Master_Transmit_DMA()
@@ -605,15 +1025,22 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Slave_Receive_DMA()
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()
+ (++) HAL_I2C_Master_Seq_Receive_DMA()
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
(++) HAL_I2C_MasterRxCpltCallback()
(++) HAL_I2C_SlaveTxCpltCallback()
(++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_AddrCallback()
+ (++) HAL_I2C_ListenCpltCallback()
(++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
@endverbatim
* @{
@@ -623,7 +1050,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -632,7 +1059,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -644,7 +1071,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
@@ -661,12 +1088,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
@@ -674,37 +1101,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -713,14 +1137,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -747,7 +1164,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -756,7 +1173,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -768,7 +1185,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
@@ -785,12 +1202,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
@@ -798,38 +1215,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -838,14 +1252,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -879,12 +1286,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -910,7 +1318,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -924,7 +1332,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -936,7 +1344,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
@@ -946,19 +1354,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
@@ -976,7 +1380,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
else
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -988,7 +1392,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1019,12 +1423,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1050,7 +1455,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -1061,7 +1466,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
@@ -1076,22 +1481,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
- if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
@@ -1100,15 +1506,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1119,7 +1517,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1143,7 +1541,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1151,7 +1549,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1186,7 +1584,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1212,7 +1610,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1220,7 +1618,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1255,7 +1653,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1379,7 +1777,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1387,7 +1785,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1422,37 +1821,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1461,7 +1894,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1487,7 +1920,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1495,7 +1928,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1530,37 +1964,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1569,7 +2037,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1582,6 +2050,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
+
return HAL_OK;
}
else
@@ -1600,10 +2069,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1620,33 +2092,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1666,10 +2172,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1686,33 +2195,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1725,7 +2268,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -1736,7 +2279,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1745,6 +2288,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1756,7 +2300,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
@@ -1771,30 +2315,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
do
@@ -1802,38 +2337,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
@@ -1844,14 +2376,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -1878,7 +2403,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -1889,7 +2414,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1898,6 +2423,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1909,7 +2435,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
@@ -1924,18 +2450,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Send Slave Address */
@@ -1943,12 +2460,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
do
@@ -1956,31 +2473,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -1990,14 +2511,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2023,7 +2537,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2033,8 +2547,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2043,6 +2557,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2081,22 +2596,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2122,7 +2628,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2132,8 +2638,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2142,6 +2648,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2180,22 +2687,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2220,7 +2718,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2230,8 +2728,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2240,6 +2739,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2278,51 +2778,77 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2336,7 +2862,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2346,8 +2872,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2356,6 +2883,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2394,50 +2922,75 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2452,7 +3005,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
@@ -2460,9 +3013,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- __IO uint32_t I2C_Trials = 0U;
+ __IO uint32_t I2C_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -2485,19 +3041,31 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- /* Device is ready */
+ /* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
@@ -2506,7 +3074,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2525,7 +3093,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear NACK Flag */
@@ -2536,7 +3104,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
/* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials++ == Trials)
+ if (I2C_Trials == Trials)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@@ -2544,21 +3112,28 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
+
+ /* Increment Trials */
+ I2C_Trials++;
}
while (I2C_Trials < Trials);
+ /* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
else
{
@@ -2571,16 +3146,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
/* Check the parameters */
@@ -2601,7 +3176,92 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_IT;
- /* If size > MAX_NBYTE_SIZE, use reload mode */
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -2613,107 +3273,642 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Abort DMA Xfer if any */
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
- xferrequest = I2C_NO_STARTSTOP;
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
- /* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
}
/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
- * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = I2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hi2c->State == HAL_I2C_STATE_READY)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
- /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = hi2c->XferOptions;
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
}
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ if (dmaxferstatus == HAL_OK)
{
- xferrequest = I2C_NO_STARTSTOP;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
}
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
}
/**
- * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -2722,33 +3917,54 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
}
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2762,7 +3978,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -2776,7 +3992,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
- I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
@@ -2787,7 +4003,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
}
/**
- * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -2796,15 +4012,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2820,6 +4039,52 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
@@ -2834,7 +4099,60 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
- hi2c->XferISR = I2C_Slave_ISR_IT;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
@@ -2852,6 +4170,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
return HAL_OK;
}
else
@@ -2919,7 +4240,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
@@ -2996,9 +4317,10 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
- if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -3007,7 +4329,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -3016,7 +4338,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -3024,10 +4346,13 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
}
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
/* Call the Error Callback in case of Error detected */
- if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
- I2C_ITError(hi2c, hi2c->ErrorCode);
+ I2C_ITError(hi2c, tmperror);
}
}
@@ -3237,7 +4562,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Return the I2C error code.
+* @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
@@ -3269,12 +4594,13 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
*/
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
+ uint16_t devaddress;
+ uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3287,41 +4613,52 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -3331,7 +4668,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
+ I2C_ITMasterSeqCplt(hi2c);
}
else
{
@@ -3341,7 +4678,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
}
}
}
- else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -3356,7 +4693,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
else
{
/* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
+ I2C_ITMasterSeqCplt(hi2c);
}
}
}
@@ -3367,11 +4704,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
@@ -3390,10 +4731,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
*/
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t tmpITFlags = ITFlags;
+
/* Process locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -3401,13 +4745,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
+ I2C_ITListenCplt(hi2c, tmpITFlags);
}
- else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3417,7 +4760,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
else
{
@@ -3433,30 +4776,43 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
}
}
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
if ((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
}
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
- I2C_ITAddrCplt(hi2c, ITFlags);
+ I2C_ITAddrCplt(hi2c, tmpITFlags);
}
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@@ -3465,26 +4821,34 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
if (hi2c->XferCount > 0U)
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
}
else
{
- if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if STOPF is set */
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
@@ -3503,13 +4867,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
*/
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
- uint32_t xfermode = 0U;
+ uint16_t devaddress;
+ uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3525,7 +4889,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
@@ -3533,7 +4897,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
if (hi2c->XferCount != 0U)
{
/* Recover Slave address */
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
@@ -3544,11 +4908,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ else
+ {
+ xfermode = I2C_AUTOEND_MODE;
+ }
}
/* Set the new XferSize in Nbytes register */
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -3565,16 +4936,55 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
}
else
{
- /* Wrong size Status regarding TCR flag event */
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3592,40 +5002,105 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
*/
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t treatdmanack = 0U;
+
/* Process locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
{
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Split check of hdmarx, for MISRA compliance */
+ if (hi2c->hdmarx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ /* Split check of hdmatx, for MISRA compliance */
+ if (hi2c->hdmatx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ if (treatdmanack == 1U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
}
else
{
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
+ /* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3637,7 +5112,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -3647,19 +5122,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3677,14 +5145,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3694,7 +5155,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3704,7 +5165,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -3714,19 +5175,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3744,14 +5198,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3761,7 +5208,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3775,16 +5222,16 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
*/
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
- uint8_t transferdirection = 0U;
- uint16_t slaveaddrcode = 0U;
- uint16_t ownadd1code = 0U;
- uint16_t ownadd2code = 0U;
+ uint8_t transferdirection;
+ uint16_t slaveaddrcode;
+ uint16_t ownadd1code;
+ uint16_t ownadd2code;
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
transferdirection = I2C_GET_DIR(hi2c);
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
@@ -3810,7 +5257,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
@@ -3824,7 +5275,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* else 7 bits addressing mode is selected */
@@ -3837,7 +5292,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* Else clear address flag only */
@@ -3856,7 +5315,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
* @param hi2c I2C handle.
* @retval None
*/
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -3876,7 +5335,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
else
@@ -3892,7 +5355,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -3901,7 +5368,7 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
* @param hi2c I2C handle.
* @retval None
*/
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -3918,8 +5385,12 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
@@ -3934,8 +5405,16 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
@@ -3947,6 +5426,8 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
*/
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
+ uint32_t tmperror;
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -3958,7 +5439,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if ((ITFlags & I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3973,8 +5454,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
@@ -3992,7 +5476,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4002,7 +5490,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
@@ -4017,7 +5509,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4026,9 +5523,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
@@ -4039,12 +5545,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
*/
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmpITFlags = ITFlags;
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
@@ -4058,35 +5564,51 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C_Flush_TXDR(hi2c);
/* If a DMA is ongoing, Update handle size context */
- if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
- hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
}
-
- /* All data are not transferred, so set error code accordingly */
- if (hi2c->XferCount != 0U)
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ /* Do nothing */
}
/* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
+ /* All data are not transferred, so set error code accordingly */
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -4100,11 +5622,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
+ I2C_ITListenCplt(hi2c, tmpITFlags);
}
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ I2C_ITSlaveSeqCplt(hi2c);
+
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4112,7 +5637,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
@@ -4122,8 +5651,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Slave Rx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4132,8 +5665,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Slave Tx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4153,10 +5690,13 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferISR = NULL;
/* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
if ((hi2c->XferSize > 0U))
{
@@ -4178,7 +5718,11 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/**
@@ -4189,6 +5733,8 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
*/
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -4198,9 +5744,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
@@ -4231,18 +5777,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- /* Set the I2C DMA Abort callback :
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
}
}
/* Abort DMA RX transfer if any */
@@ -4250,18 +5799,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
}
}
else if (hi2c->State == HAL_I2C_STATE_ABORT)
@@ -4272,7 +5824,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4280,7 +5836,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4312,7 +5872,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -4340,10 +5900,16 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
}
/* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4354,12 +5920,24 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4369,7 +5947,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -4397,10 +5975,16 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
}
/* Enable the DMA stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4411,12 +5995,24 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hi2c->XferOptions;
+
+ if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4426,13 +6022,34 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t treatdmaerror = 0U;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ if (hi2c->hdmatx != NULL)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ {
+ treatdmaerror = 1U;
+ }
+ }
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ if (hi2c->hdmarx != NULL)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ {
+ treatdmaerror = 1U;
+ }
+ }
+
+ /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+ if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
}
/**
@@ -4443,10 +6060,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hi2c->hdmatx->XferAbortCallback = NULL;
@@ -4458,12 +6072,20 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
hi2c->State = HAL_I2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4484,14 +6106,15 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4519,7 +6142,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4528,7 +6151,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4554,7 +6177,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4563,7 +6186,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4618,7 +6241,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4626,7 +6249,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4651,14 +6274,16 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
}
@@ -4675,7 +6300,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -4706,7 +6331,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@@ -4723,9 +6348,9 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4787,8 +6412,6 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
}
/**
@@ -4796,9 +6419,9 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4807,7 +6430,7 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
@@ -4819,7 +6442,7 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
@@ -4854,8 +6477,34 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
- return HAL_OK;
+/**
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+ /* if user set XferOptions to I2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to I2C_FIRST_FRAME */
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c_ex.c
index f8f48aa9c83235d0dd68c1a60ed719c104e3f91e..1a14aa6603ed8285e7535a2f24dc5f3e33f4207c 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2c_ex.c
@@ -31,29 +31,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -151,7 +135,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2s.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2s.c
index 13da6bcebb49eab48e701f88a0a945155a3d75ea..aa955fc4b27060f902c5f18531bb2d1cbeb58b00 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2s.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_i2s.c
@@ -13,7 +13,7 @@
##### How to use this driver #####
===============================================================================
[..]
- The I2S HAL driver can be used as follows:
+ The I2S HAL driver can be used as follow:
(#) Declare a I2S_HandleTypeDef handle structure.
(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
@@ -27,13 +27,13 @@
(+++) Enable the NVIC I2S IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Channel.
+ (+++) Configure the DMA Tx/Rx Stream/Channel.
(+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Channel.
+ DMA Tx/Rx Stream/Channel.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
@@ -42,11 +42,11 @@
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-@- Make sure that either:
- (+@) I2S clock is configured based on SYSCLK or
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
+ (+@) I2S clock is configured based on SYSCLK or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.
- (#) Three mode of operations are available within this driver :
+ (#) Three mode of operations are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -90,7 +90,7 @@
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
*** I2S HAL driver macros list ***
- =============================================
+ ===================================
[..]
Below the list of most used macros in I2S HAL driver.
@@ -103,33 +103,72 @@
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : I2S Tx Completed callback
+ (+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) ErrorCallback : I2S Error callback
+ (+) MspInitCallback : I2S Msp Init callback
+ (+) MspDeInitCallback : I2S Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : I2S Tx Completed callback
+ (+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) ErrorCallback : I2S Error callback
+ (+) MspInitCallback : I2S Msp Init callback
+ (+) MspDeInitCallback : I2S Msp DeInit callback
+
+ By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+ or HAL_I2S_Init() function.
+
+ When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -137,6 +176,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#ifdef HAL_I2S_MODULE_ENABLED
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -146,8 +187,6 @@
* @{
*/
-#ifdef HAL_I2S_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -156,15 +195,16 @@
/** @defgroup I2S_Private_Functions I2S Private Functions
* @{
*/
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout);
/**
* @}
*/
@@ -196,16 +236,15 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
(++) MCLK Output
(++) Audio frequency
(++) Polarity
- (++) Full duplex mode
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
of the selected I2Sx peripheral.
-@endverbatim
+ @endverbatim
* @{
*/
/**
- * @brief Initializes the I2S according to the specified parameters
+ * @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -213,16 +252,19 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
+ uint32_t i2sdiv;
+ uint32_t i2sodd;
+ uint32_t packetlength;
+ uint32_t tmp;
+ uint32_t i2sclk;
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
@@ -232,52 +274,67 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
- if(hi2s->State == HAL_I2S_STATE_RESET)
+ if (hi2s->State == HAL_I2S_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2s->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ /* Init the I2S Callback settings */
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hi2s->MspInitCallback == NULL)
+ {
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hi2s->MspInitCallback(hi2s);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
hi2s->State = HAL_I2S_STATE_BUSY;
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- hi2s->Instance->I2SPR = 0x0002;
+ CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002U;
- /* Get the I2SCFGR register value */
- tmpreg = hi2s->Instance->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
+ /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
/* If the requested audio frequency is not the default, compute the prescaler */
- else
+ if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
- /* Check the frame length (For the Prescaler computing) *******************/
- if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ /* Check the frame length (For the Prescaler computing) ********************/
+ if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
- packetlength = 1;
+ packetlength = 16U;
}
else
{
/* Packet length is 32 bits */
- packetlength = 2;
+ packetlength = 32U;
}
- /* Get I2S source Clock frequency ****************************************/
+ /* I2S standard */
+ if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet lenght is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f3xx_conf.h file */
- if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ if (hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
{
/* Set the I2S clock to the external clock value */
i2sclk = EXTERNAL_CLOCK_VALUE;
@@ -285,55 +342,80 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
else
{
/* Get the I2S source clock value */
- i2sclk = I2S_GetClockFreq(hi2s);
+ i2sclk = I2S_GetClockFreq(hi2s);
}
/* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
}
else
{
/* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
- tmp = tmp / 10;
+ tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+ i2sodd = (uint32_t)(tmp & (uint32_t)1U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
+ i2sodd = (uint32_t)(i2sodd << 8U);
+ }
+ else
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ return HAL_ERROR;
}
- /* Write to SPIx I2SPR register the computed value */
- hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
- /* Configure the I2S with the I2S_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
- (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
- /* Write to SPIx I2SCFGR */
- hi2s->Instance->I2SCFGR = tmpreg;
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
+ {
+ /* Write to SPIx I2SCFGR */
+ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+ }
+#endif
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
return HAL_OK;
}
@@ -347,7 +429,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
@@ -357,11 +439,24 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_BUSY;
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ if (hi2s->MspDeInitCallback == NULL)
+ {
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hi2s->MspDeInitCallback(hi2s);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
+ hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hi2s);
@@ -375,7 +470,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
@@ -391,7 +486,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
@@ -401,11 +496,202 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
}
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User I2S Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2S Callback
+ * I2S callback is redirected to the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -448,505 +734,538 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
/**
- * @brief Transmit an amount of data in blocking mode
+ * @brief Transmit an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
* @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- while(hi2s->TxXferCount > 0)
- {
- hi2s->Instance->DR = (*pData++);
- hi2s->TxXferCount--;
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
- /* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- return HAL_ERROR;
- }
- }
+ while (hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
- /* Check if Slave mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
{
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- return HAL_OK;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
}
- else
+
+ /* Check if Slave mode is selected */
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
- return HAL_BUSY;
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
}
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Receive data */
- while(hi2s->RxXferCount > 0)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
- return HAL_ERROR;
- }
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
- (*pData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
+ /* Receive data */
+ while (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
- hi2s->State = HAL_I2S_STATE_READY;
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
}
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ uint32_t tmpreg_cfgr;
- hi2s->pTxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- return HAL_OK;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
- return HAL_BUSY;
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
* between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
- hi2s->pRxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- return HAL_OK;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
- return HAL_BUSY;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Transmit data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t *tmp;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Set the I2S TxDMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Enable the Tx DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
- /* Enable Tx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- return HAL_OK;
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
- else
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
{
- return HAL_BUSY;
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with DMA
+ * @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t *tmp;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- hi2s->pRxBuffPtr = pData;
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
- /* Enable the Rx DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
- /* Enable Rx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- return HAL_OK;
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
- else
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
{
- return HAL_BUSY;
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Pauses the audio stream playing from the Media.
+ * @brief Pauses the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -956,28 +1275,19 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ else
{
- if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
- {
- /* Disable the I2S DMA Tx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
- else
- {
- /* Disable the I2S DMA Rx request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- }
+ /* nothing to do */
}
/* Process Unlocked */
@@ -987,7 +1297,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Resumes the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -997,19 +1307,23 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
+ else
+ {
+ /* nothing to do */
+ }
/* If the I2S peripheral is still not enabled, enable it */
- if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
@@ -1022,33 +1336,44 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Stops the audio stream playing from the Media.
+ * @brief Stops the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ */
/* Disable the I2S Tx/Rx DMA requests */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- /* Abort the I2S DMA Channel tx */
- if(hi2s->hdmatx != NULL)
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmatx);
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
- /* Abort the I2S DMA Channel rx */
- if(hi2s->hdmarx != NULL)
+
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmarx);
- HAL_DMA_Abort(hi2s->hdmarx);
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Disable I2S peripheral */
@@ -1056,155 +1381,77 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
+ return errorcode;
}
/**
* @brief This function handles I2S interrupt request.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @retval HAL status
+ * @retval None
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
- __IO uint32_t i2ssr = hi2s->Instance->SR;
+ uint32_t itsource = hi2s->Instance->CR2;
+ uint32_t itflag = hi2s->Instance->SR;
- if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
+ (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
{
- /* I2S in mode Receiver ----------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- I2S_Receive_IT(hi2s);
- }
+ I2S_Receive_IT(hi2s);
+ return;
+ }
- /* I2S Overrun error interrupt occurred -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ return;
+ }
+
+ /* I2S interrupt error -------------------------------------------------*/
+ if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
+ {
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* I2S in mode Transmitter ---------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
}
- /* I2S Underrun error interrupt occurred ------------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(State == RESET)
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
}
- }
- else
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
- }
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
- return HAL_OK;
}
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
/**
- * @brief Tx Transfer Half completed callbacks
+ * @brief Tx Transfer Half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
@@ -1215,12 +1462,12 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
}
/**
- * @brief Tx Transfer completed callbacks
+ * @brief Tx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
@@ -1231,7 +1478,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
}
/**
- * @brief Rx Transfer half completed callbacks
+ * @brief Rx Transfer half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1242,12 +1489,12 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks
+ * @brief Rx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1263,12 +1510,12 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief I2S error callbacks
+ * @brief I2S error callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
@@ -1326,30 +1573,33 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
* @}
*/
- /**
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
* @brief Get I2S Input Clock based on I2S source clock selection
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module.
* @retval I2S Clock Input
*/
static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg;
/* This variable used to store the VCO Input (value in Hz) */
- uint32_t vcoinput = 0;
+ uint32_t vcoinput;
/* This variable used to store the I2S_CK_x (value in Hz) */
- uint32_t i2sclocksource = 0;
+ uint32_t i2sclocksource;
/* Configure I2S Clock based on I2S source clock selection */
/* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
- switch(hi2s->Init.ClockSource)
+ switch (hi2s->Init.ClockSource)
{
case I2S_CLOCK_PLL :
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
- if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -1362,8 +1612,8 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
- tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
- i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
+ i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
break;
}
@@ -1374,6 +1624,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
}
default :
{
+ i2sclocksource = 0U;
break;
}
}
@@ -1382,122 +1633,124 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
return i2sclocksource;
}
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
/**
- * @brief DMA I2S transmit process complete callback
+ * @brief DMA I2S transmit process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
- hi2s->TxXferCount = 0;
-
/* Disable Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->RxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S transmit process half complete callback
+ * @brief DMA I2S transmit process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxHalfCpltCallback(hi2s);
+#else
HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process complete callback
+ * @brief DMA I2S receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Rx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-
- hi2s->RxXferCount = 0;
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- if(hi2s->TxXferCount == 0)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
- }
- else
- {
- hi2s->State = HAL_I2S_STATE_READY;
- }
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
}
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process half complete callback
+ * @brief DMA I2S receive process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxHalfCpltCallback(hi2s);
+#else
HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S communication error callback
+ * @brief DMA I2S communication error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Disable Rx and Tx DMA Request */
- hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0;
- hi2s->RxXferCount = 0;
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1505,44 +1758,93 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma)
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if (hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s I2S handle
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
/* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
- if(hi2s->RxXferCount == 0)
+ if (hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set to status*/
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
+ return HAL_OK;
}
+
/**
* @}
*/
-#endif /* HAL_I2S_MODULE_ENABLED */
/**
* @}
*/
@@ -1551,4 +1853,6 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
* @}
*/
+#endif /* HAL_I2S_MODULE_ENABLED */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_irda.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_irda.c
index 1e595fd2ab1581d8ca742e8afee98574f8ca066c..e79476fbc7830cdabe6666c4dc702039ce61d336 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_irda.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_irda.c
@@ -42,8 +42,8 @@
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
- and Mode(Receiver/Transmitter) in the hirda Init structure.
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
@@ -55,78 +55,131 @@
(#) Three operation modes are available within this driver :
- *** Polling mode IO operation ***
- =================================
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ ##### Callback registration #####
+ ==================================
+
[..]
- (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+ The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
- *** Interrupt mode IO operation ***
- ===================================
[..]
- (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
- *** DMA mode IO operation ***
- =============================
+ Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
+ Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
[..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
- *** IRDA HAL driver macros list ***
- ===================================
+ Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+
[..]
- Below the list of most used macros in IRDA HAL driver.
+ By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
+ and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
- (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
- (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
- (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
- (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
+ [..]
+ Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
+ or @ref HAL_IRDA_Init() function.
[..]
- (@) You can refer to the IRDA HAL driver header file for more useful macros
+ When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -150,20 +203,40 @@
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define IRDA_TEACK_REACK_TIMEOUT 1000U
-#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
+#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
+
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ IRDA clock source.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
+ */
+#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
@@ -179,9 +252,9 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
@@ -192,35 +265,52 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
* @{
*/
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in IrDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) BaudRate
- (++) WordLength
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible IRDA frame formats.
- (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- (++) Mode: Receiver/transmitter modes
- (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
- [..]
- The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
- are available in reference manual).
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible IRDA frame formats are listed in the
+ following table.
+
+ Table 1. IRDA frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | IRDA frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
* @{
*/
@@ -234,7 +324,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -242,13 +332,25 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- if(hirda->gState == HAL_IRDA_STATE_RESET)
+ if (hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ IRDA_InitCallbacksToDefault(hirda);
+
+ if (hirda->MspInitCallback == NULL)
+ {
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hirda->MspInitCallback(hirda);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
hirda->gState = HAL_IRDA_STATE_BUSY;
@@ -287,7 +389,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -298,7 +400,16 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
hirda->gState = HAL_IRDA_STATE_BUSY;
/* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ if (hirda->MspDeInitCallback == NULL)
+ {
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hirda->MspDeInitCallback(hirda);
+#else
HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
@@ -306,7 +417,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
hirda->gState = HAL_IRDA_STATE_RESET;
hirda->RxState = HAL_IRDA_STATE_RESET;
- /* Release Lock */
+ /* Process Unlock */
__HAL_UNLOCK(hirda);
return HAL_OK;
@@ -344,6 +455,244 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
*/
}
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IRDA Callback
+ * To be used instead of the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an IRDA callback
+ * IRDA callback is redirected to the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (HAL_IRDA_STATE_READY == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_IRDA_STATE_RESET == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -353,7 +702,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
*
@verbatim
===============================================================================
- ##### IO operation functions #####
+ ##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
@@ -382,21 +731,19 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
- (#) Non-Blocking mode APIs with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
- (++) IRDA_Transmit_IT()
- (++) IRDA_Receive_IT()
- (#) Non-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
(++) HAL_IRDA_DMAPause()
(++) HAL_IRDA_DMAResume()
(++) HAL_IRDA_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
(++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
(++) HAL_IRDA_RxHalfCpltCallback()
@@ -404,26 +751,26 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_IRDA_Abort()
- (++) HAL_IRDA_AbortTransmit()
- (++) HAL_IRDA_AbortReceive()
- (++) HAL_IRDA_Abort_IT()
- (++) HAL_IRDA_AbortTransmit_IT()
- (++) HAL_IRDA_AbortReceive_IT()
+ (+) HAL_IRDA_Abort()
+ (+) HAL_IRDA_AbortTransmit()
+ (+) HAL_IRDA_AbortReceive()
+ (+) HAL_IRDA_Abort_IT()
+ (+) HAL_IRDA_AbortTransmit_IT()
+ (+) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_IRDA_AbortCpltCallback()
- (++) HAL_IRDA_AbortTransmitCpltCallback()
- (++) HAL_IRDA_AbortReceiveCpltCallback()
+ (+) HAL_IRDA_AbortCpltCallback()
+ (+) HAL_IRDA_AbortTransmitCpltCallback()
+ (+) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@@ -432,23 +779,24 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
*/
/**
- * @brief Send an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Send an amount of data in blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Specify timeout value.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -464,27 +812,40 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0)
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pData += 2;
+ hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
}
else
{
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
}
}
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -504,24 +865,25 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
}
/**
- * @brief Receive an amount of data in blocking mode.
+ * @brief Receive an amount of data in blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @param Timeout Specify timeout value.
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -543,24 +905,36 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
IRDA_MASK_COMPUTATION(hirda);
uhMask = hirda->Mask;
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
/* Check data remaining to be received */
- while(hirda->RxXferCount > 0)
+ while (hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2;
+ *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pdata16bits++;
}
else
{
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
}
}
@@ -579,19 +953,19 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
}
/**
- * @brief Send an amount of data in interrupt mode.
+ * @brief Send an amount of data in interrupt mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -621,19 +995,19 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
}
/**
- * @brief Receive an amount of data in interrupt mode.
+ * @brief Receive an amount of data in interrupt mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -656,7 +1030,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
__HAL_UNLOCK(hirda);
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -670,19 +1044,19 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
}
/**
- * @brief Send an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Send an amount of data in DMA mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -710,19 +1084,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
hirda->hdmatx->XferAbortCallback = NULL;
/* Enable the IRDA transmit DMA channel */
- HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+ if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
- /* Clear the TC flag in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->gState to ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -731,21 +1119,21 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
}
/**
- * @brief Receive an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @brief Receive an amount of data in DMA mode.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -772,22 +1160,36 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+ if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->RxState to ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -797,9 +1199,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/**
- * @brief Pause the DMA Transfer.
+ * @brief Pause the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
@@ -807,21 +1209,25 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
/* Process Locked */
__HAL_LOCK(hirda);
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- /* Disable the IRDA DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
}
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Disable the IRDA DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
}
/* Process Unlocked */
@@ -831,9 +1237,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
}
/**
- * @brief Resume the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
@@ -841,12 +1247,12 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
/* Process Locked */
__HAL_LOCK(hirda);
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
@@ -866,9 +1272,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
@@ -881,33 +1287,55 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
the stream and the corresponding call back is executed. */
/* Stop IRDA DMA Tx request if ongoing */
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
- HAL_DMA_Abort(hirda->hdmatx);
- }
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- IRDA_EndTxTransfer(hirda);
+ /* Abort the IRDA DMA Tx channel */
+ if (hirda->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
}
/* Stop IRDA DMA Rx request if ongoing */
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
- HAL_DMA_Abort(hirda->hdmarx);
- }
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
- IRDA_EndRxTransfer(hirda);
+ IRDA_EndRxTransfer(hirda);
+ }
}
return HAL_OK;
@@ -938,13 +1366,22 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmatx);
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -954,19 +1391,28 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmarx);
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1005,18 +1451,27 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmatx);
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
@@ -1049,18 +1504,27 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmarx);
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1088,7 +1552,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
- uint32_t abortcplt = 1;
+ uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
@@ -1097,11 +1561,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
@@ -1111,11 +1575,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
}
/* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
@@ -1126,25 +1590,25 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
else
{
- abortcplt = 0;
+ abortcplt = 0U;
}
}
}
@@ -1155,30 +1619,30 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1;
+ abortcplt = 1U;
}
else
{
- abortcplt = 0;
+ abortcplt = 0U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1)
+ if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -1191,7 +1655,13 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1223,14 +1693,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
@@ -1239,25 +1709,37 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
else
{
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1290,14 +1772,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1306,7 +1788,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
else
{
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1315,13 +1797,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1330,15 +1818,21 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
- * @brief Handle IRDA interrupt request.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1348,13 +1842,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
uint32_t cr1its = READ_REG(hirda->Instance->CR1);
uint32_t cr3its;
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
return;
@@ -1363,12 +1858,12 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
/* If some errors occur */
cr3its = READ_REG(hirda->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* IRDA parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
@@ -1376,7 +1871,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/* IRDA frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
@@ -1384,7 +1879,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/* IRDA noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
@@ -1392,8 +1887,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
@@ -1401,18 +1896,19 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
- if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ errorcode = hirda->ErrorCode;
+ if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
{
/* Blocking error : transfer is aborted
Set the IRDA state ready to be able to start again the process,
@@ -1425,14 +1921,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1440,21 +1936,37 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
}
}
@@ -1463,14 +1975,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
} /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U))
{
IRDA_Transmit_IT(hirda);
return;
}
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
IRDA_EndTransmit_IT(hirda);
return;
@@ -1529,7 +2041,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
/**
* @brief Rx Half Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -1564,7 +2076,7 @@ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1580,7 +2092,7 @@ __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1596,7 +2108,7 @@ __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1630,24 +2142,24 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
*/
/**
- * @brief Return the IRDA handle state.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
- uint32_t temp1= 0x00, temp2 = 0x00;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
+ uint32_t temp1, temp2;
+ temp1 = (uint32_t)hirda->gState;
+ temp2 = (uint32_t)hirda->RxState;
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
- * @brief Return the IRDA handle error code.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
@@ -1668,17 +2180,38 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
* @{
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
- * @brief Configure the IRDA peripheral.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Initialize the callbacks to their default values.
+ * @param hirda IRDA handle.
+ * @retval none
+ */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+ /* Init the IRDA Callback settings */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval None
+ * @retval HAL status
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
- uint32_t tmpreg = 0x00000000;
- IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t tmpreg;
+ IRDA_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -1700,46 +2233,57 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
/*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ tmpreg = 0U;
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_PCLK2:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
break;
- case IRDA_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hirda->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
return ret;
}
/**
- * @brief Check the IRDA Idle State.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -1748,10 +2292,10 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@@ -1781,12 +2325,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -1846,12 +2390,12 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the IRDA CR3 register */
@@ -1863,7 +2407,13 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Circular mode */
else
{
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
@@ -1876,9 +2426,15 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half complete callback */
+ hirda->TxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -1889,12 +2445,12 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
@@ -1908,7 +2464,13 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hirda->RxState = HAL_IRDA_STATE_READY;
}
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
/**
@@ -1919,39 +2481,55 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ hirda->RxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx Half complete callback */
HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
- * @brief DMA IRDA communication error callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* Stop IRDA DMA Tx request if ongoing */
- if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- hirda->TxXferCount = 0;
- IRDA_EndTxTransfer(hirda);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
}
/* Stop IRDA DMA Rx request if ongoing */
- if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- hirda->RxXferCount = 0;
- IRDA_EndRxTransfer(hirda);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
}
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -1962,11 +2540,17 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
- hirda->RxXferCount = 0;
- hirda->TxXferCount = 0;
-
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+ hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -1979,22 +2563,22 @@ static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- if(hirda->hdmarx->XferAbortCallback != NULL)
+ if (hirda->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -2007,7 +2591,13 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
@@ -2021,22 +2611,22 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- if(hirda->hdmatx->XferAbortCallback != NULL)
+ if (hirda->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0;
- hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -2049,7 +2639,13 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
@@ -2063,15 +2659,21 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2084,9 +2686,9 @@ static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -2095,7 +2697,13 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2104,55 +2712,48 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
* interruptions have been enabled by HAL_IRDA_Transmit_IT().
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
/* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- if(hirda->TxXferCount == 0)
+ if (hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
}
else
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- hirda->pTxBuffPtr += 2;
+ tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ hirda->pTxBuffPtr += 2U;
}
else
{
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
+ hirda->pTxBuffPtr++;
}
hirda->TxXferCount--;
-
- return HAL_OK;
}
}
- else
- {
- return HAL_BUSY;
- }
}
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
@@ -2160,9 +2761,13 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2171,11 +2776,11 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
* interruptions have been enabled by HAL_IRDA_Receive_IT()
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint16_t uhMask = hirda->Mask;
uint16_t uhdata;
@@ -2185,16 +2790,18 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
*tmp = (uint16_t)(uhdata & uhMask);
- hirda->pRxBuffPtr +=2;
+ hirda->pRxBuffPtr += 2U;
}
else
{
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+ *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ hirda->pRxBuffPtr++;
}
- if(--hirda->RxXferCount == 0)
+ hirda->RxXferCount--;
+ if (hirda->RxXferCount == 0U)
{
/* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@@ -2205,19 +2812,19 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
-
- return HAL_OK;
}
else
{
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
}
@@ -2235,4 +2842,3 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_iwdg.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_iwdg.c
index dc5dbcee51a82c6b4b66e99cc908460b44d4a759..70f72687e953fe3bd14e3e53b752895a48e95e66 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_iwdg.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_iwdg.c
@@ -36,7 +36,7 @@
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx
@@ -48,20 +48,20 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
- IWDG_WINR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
+ (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (+) Enable write access to configuration registers:
+ IWDG_PR, IWDG_RLR and IWDG_WINR.
+ (+) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) wait for status flags to be reset
- (++) Depending on window parameter:
- (+++) If Window Init parameter is same as Window register value,
- nothing more is done but reload counter value in order to exit
- function withy exact time base.
- (+++) Else modify Window register. This will automatically reload
- watchdog counter.
+ (+) Wait for status flags to be reset.
+ (+) Depending on window parameter:
+ (++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function with exact time base.
+ (++) Else modify Window register. This will automatically reload
+ watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -79,29 +79,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -172,7 +156,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
uint32_t tickstart;
/* Check the IWDG handle allocation */
- if(hiwdg == NULL)
+ if (hiwdg == NULL)
{
return HAL_ERROR;
}
@@ -183,7 +167,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
- /* Enable IWDG. LSI is turned on automaticaly */
+ /* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
@@ -197,10 +181,10 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
- /* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
+ /* Wait for register to be updated */
+ while (hiwdg->Instance->SR != 0x00u)
{
- if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -208,7 +192,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
/* If window parameter is different than current value, modify window
register */
- if(hiwdg->Instance->WINR != hiwdg->Init.Window)
+ if (hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_jpeg.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_jpeg.c
index 405f17786c95448856809360e81b47916efb8342..282d8f70dc4c5d20472caa5d1ae66afe667370fa 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_jpeg.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_jpeg.c
@@ -26,7 +26,7 @@
(#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
the encoding parameters (mandatory before calling the encoding function).
- the application can change the encoding parameter "ImageQuality" from
+ the application can change the encoding parameter ImageQuality from
1 to 100 to obtain a more or less quality (visual quality vs the original row image),
and inversely more or less jpg file size.
@@ -91,11 +91,11 @@
call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
with the new output buffer location and size to be used to store next data chunk.
if the application is not ready to provide the output chunk location then it can
- call the function HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
+ call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT
to inform the JPEG HAL driver that it shall pause output data. Once the application
is ready to receive the new data chunk (output buffer location free or available) it should call
the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
- with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
+ with the new output chunk buffer location and size, then call HAL_JPEG_Resume
to inform the HAL that it shall resume outputting data in the given output buffer.
(++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
@@ -119,7 +119,7 @@
to the application.
(#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
- the current operation. the application can call the function "HAL_JPEG_GetError"
+ the current operation. the application can call the function HAL_JPEG_GetError()
to retrieve the error codes.
(#) By default the HAL JPEG driver uses the default quantization tables
@@ -144,34 +144,74 @@
(+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt.
(+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled).
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function HAL_JPEG_RegisterCallback() allows to register following callbacks:
+ (+) EncodeCpltCallback : callback for end of encoding operation.
+ (+) DecodeCpltCallback : callback for end of decoding operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : JPEG MspInit.
+ (+) MspDeInitCallback : JPEG MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
+ register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(),
+ HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback().
+
+ Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) EncodeCpltCallback : callback for end of encoding operation.
+ (+) DecodeCpltCallback : callback for end of decoding operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : JPEG MspInit.
+ (+) MspDeInitCallback : JPEG MspDeInit.
+
+ For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
+ unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(),
+ HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback().
+
+ By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit()
+ or HAL_JPEG_Init() function.
+
+ When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -190,45 +230,47 @@
#ifdef HAL_JPEG_MODULE_ENABLED
-#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+#if defined (JPEG)
/* Private define ------------------------------------------------------------*/
/** @addtogroup JPEG_Private_Constants
* @{
*/
-#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
-#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
-#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/
+#define JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */
+#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/
+#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/
#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
-#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
+#define JPEG_FIFO_TH_SIZE ((uint32_t)4U) /* JPEG Input/Output HW FIFO Threshold in words*/
-#define JPEG_DMA_MASK ((uint32_t)0x00001800U) /* JPEG DMA request Mask*/
+#define JPEG_DMA_MASK ((uint32_t)0x00001800) /* JPEG DMA request Mask*/
#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */
#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */
-#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/
-#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/
-#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */
+#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
+
+#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/
+#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/
+#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */
-#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */
-#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */
-#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */
-#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */
+#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */
+#define JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */
+#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */
+#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */
-#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */
+#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */
-#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */
-#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */
+#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */
+#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */
-#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */
+#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */
-#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */
+#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */
-#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */
-#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */
+#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */
+#define JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */
/**
* @}
*/
@@ -250,7 +292,7 @@ typedef struct
uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
-}JPEG_ACHuffTableTypeDef;
+} JPEG_ACHuffTableTypeDef;
typedef struct
{
@@ -260,7 +302,7 @@ typedef struct
uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */
-}JPEG_DCHuffTableTypeDef;
+} JPEG_DCHuffTableTypeDef;
typedef struct
{
@@ -268,7 +310,7 @@ typedef struct
uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */
-}JPEG_AC_HuffCodeTableTypeDef;
+} JPEG_AC_HuffCodeTableTypeDef;
typedef struct
{
@@ -276,7 +318,7 @@ typedef struct
uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */
-}JPEG_DC_HuffCodeTableTypeDef;
+} JPEG_DC_HuffCodeTableTypeDef;
/**
* @}
*/
@@ -288,12 +330,11 @@ typedef struct
#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK))
/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
located in the same DMA request enable register (CR register). */
-#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0)
+#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0UL)
/**
* @}
*/
-
/* Private variables ---------------------------------------------------------*/
/** @addtogroup JPEG_Private_Variables
* @{
@@ -318,86 +359,63 @@ static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =
{
{ 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/
- { 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */
- 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
- 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
- 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
- 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
- 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
- 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
- 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
- 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
- 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
- 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
- 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
- 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
- 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
- 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
- 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
- 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
- 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
- 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
- 0xf9, 0xfa }
+ {
+ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */
+ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
+ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
+ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
+ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
+ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
+ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
+ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
+ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
+ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
+ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
+ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+ 0xf9, 0xfa
+ }
};
static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =
{
{ 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/
- { 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */
- 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
- 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
- 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
- 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
- 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
- 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
- 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
- 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
- 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
- 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
- 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
- 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
- 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
- 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
- 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
- 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
- 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
- 0xf9, 0xfa }
-};
-
-
-/*
- These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1.
-*/
-static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
-{
- 16, 11, 10, 16, 24, 40, 51, 61,
- 12, 12, 14, 19, 26, 58, 60, 55,
- 14, 13, 16, 24, 40, 57, 69, 56,
- 14, 17, 22, 29, 51, 87, 80, 62,
- 18, 22, 37, 56, 68, 109, 103, 77,
- 24, 35, 55, 64, 81, 104, 113, 92,
- 49, 64, 78, 87, 103, 121, 120, 101,
- 72, 92, 95, 98, 112, 100, 103, 99
-};
-static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
-{
- 17, 18, 24, 47, 99, 99, 99, 99,
- 18, 21, 26, 66, 99, 99, 99, 99,
- 24, 26, 56, 99, 99, 99, 99, 99,
- 47, 66, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99,
- 99, 99, 99, 99, 99, 99, 99, 99
+ {
+ 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */
+ 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+ 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
+ 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
+ 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
+ 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
+ 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
+ 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
+ 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
+ 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+ 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
+ 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+ 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
+ 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
+ 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
+ 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
+ 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
+ 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
+ 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
+ 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+ 0xf9, 0xfa
+ }
};
static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
{
- 0, 1, 8, 16, 9, 2, 3, 10,
+ 0, 1, 8, 16, 9, 2, 3, 10,
17, 24, 32, 25, 18, 11, 4, 5,
12, 19, 26, 33, 40, 48, 41, 34,
27, 20, 13, 6, 7, 14, 21, 28,
@@ -416,13 +434,18 @@ static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
*/
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);
-static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
-static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
-static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress);
-static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress);
-static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
-static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);
-static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress);
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
+ JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
+ JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
+ const __IO uint32_t *DCTableAddress);
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
+ const __IO uint32_t *ACTableAddress);
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg);
+static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
+ __IO uint32_t *QTableAddress);
static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);
static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);
static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);
@@ -434,13 +457,14 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);
static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
-static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
-static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma);
static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma);
static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma);
static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ;
+
/**
* @}
*/
@@ -450,8 +474,8 @@ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ;
*/
/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions.
- *
+ * @brief Initialization and de-initialization functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -473,20 +497,59 @@ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ;
*/
HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
{
- /*Note : these intermediate variables are used to avoid MISRA warning
- regarding rule 11.5 */
- uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable);
- uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable);
- uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable);
- uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable);
+ /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */
+ static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
+ {
+ 16, 11, 10, 16, 24, 40, 51, 61,
+ 12, 12, 14, 19, 26, 58, 60, 55,
+ 14, 13, 16, 24, 40, 57, 69, 56,
+ 14, 17, 22, 29, 51, 87, 80, 62,
+ 18, 22, 37, 56, 68, 109, 103, 77,
+ 24, 35, 55, 64, 81, 104, 113, 92,
+ 49, 64, 78, 87, 103, 121, 120, 101,
+ 72, 92, 95, 98, 112, 100, 103, 99
+ };
+ static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
+ {
+ 17, 18, 24, 47, 99, 99, 99, 99,
+ 18, 21, 26, 66, 99, 99, 99, 99,
+ 24, 26, 56, 99, 99, 99, 99, 99,
+ 47, 66, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99,
+ 99, 99, 99, 99, 99, 99, 99, 99
+ };
/* Check the JPEG handle allocation */
- if(hjpeg == NULL)
+ if (hjpeg == NULL)
{
return HAL_ERROR;
}
- if(hjpeg->State == HAL_JPEG_STATE_RESET)
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ if (hjpeg->State == HAL_JPEG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hjpeg->Lock = HAL_UNLOCKED;
+
+ hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */
+ hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */
+ hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */
+ hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */
+ hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */
+ hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */
+
+ if (hjpeg->MspInitCallback == NULL)
+ {
+ hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hjpeg->MspInitCallback(hjpeg);
+ }
+#else
+ if (hjpeg->State == HAL_JPEG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hjpeg->Lock = HAL_UNLOCKED;
@@ -494,6 +557,7 @@ HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
/* Init the low level hardware : GPIO, CLOCK */
HAL_JPEG_MspInit(hjpeg);
}
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/* Change the JPEG state */
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -505,25 +569,26 @@ HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
/* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
/* Disable All DMA requests */
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
/* Flush input and output FIFOs*/
hjpeg->Instance->CR |= JPEG_CR_IFF;
hjpeg->Instance->CR |= JPEG_CR_OFF;
/* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
- hjpeg->QuantTable0 = (uint8_t *)JPEG_LUM_QuantTable;
- hjpeg->QuantTable1 = (uint8_t *)JPEG_CHROM_QuantTable;
+ /* init default quantization tables*/
+ hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable);
+ hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable);
hjpeg->QuantTable2 = NULL;
hjpeg->QuantTable3 = NULL;
/* init the default Huffman tables*/
- if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK)
+ if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK)
{
hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;
@@ -559,13 +624,24 @@ HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)
{
/* Check the JPEG handle allocation */
- if(hjpeg == NULL)
+ if (hjpeg == NULL)
{
return HAL_ERROR;
}
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ if (hjpeg->MspDeInitCallback == NULL)
+ {
+ hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hjpeg->MspDeInitCallback(hjpeg);
+
+#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_JPEG_MspDeInit(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
/* Change the JPEG state */
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -622,13 +698,398 @@ __weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
*/
}
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User JPEG Callback
+ * To be used instead of the weak predefined callback
+ * @param hjpeg JPEG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
+ * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
+ * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
+ pJPEG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_JPEG_ENCODE_CPLT_CB_ID :
+ hjpeg->EncodeCpltCallback = pCallback;
+ break;
+
+ case HAL_JPEG_DECODE_CPLT_CB_ID :
+ hjpeg->DecodeCpltCallback = pCallback;
+ break;
+
+ case HAL_JPEG_ERROR_CB_ID :
+ hjpeg->ErrorCallback = pCallback;
+ break;
+
+ case HAL_JPEG_MSPINIT_CB_ID :
+ hjpeg->MspInitCallback = pCallback;
+ break;
+
+ case HAL_JPEG_MSPDEINIT_CB_ID :
+ hjpeg->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_JPEG_STATE_RESET == hjpeg->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_JPEG_MSPINIT_CB_ID :
+ hjpeg->MspInitCallback = pCallback;
+ break;
+
+ case HAL_JPEG_MSPDEINIT_CB_ID :
+ hjpeg->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief Unregister a JPEG Callback
+ * JPEG callabck is redirected to the weak predefined callback
+ * @param hjpeg JPEG handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
+ * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
+ * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_JPEG_ENCODE_CPLT_CB_ID :
+ hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */
+ break;
+
+ case HAL_JPEG_DECODE_CPLT_CB_ID :
+ hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */
+ break;
+
+ case HAL_JPEG_ERROR_CB_ID :
+ hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_JPEG_MSPINIT_CB_ID :
+ hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_JPEG_MSPDEINIT_CB_ID :
+ hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_JPEG_STATE_RESET == hjpeg->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_JPEG_MSPINIT_CB_ID :
+ hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_JPEG_MSPDEINIT_CB_ID :
+ hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief Register Info Ready JPEG Callback
+ * To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @param pCallback pointer to the Info Ready Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
+ pJPEG_InfoReadyCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->InfoReadyCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Info Ready JPEG Callback
+ * Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief Register Get Data JPEG Callback
+ * To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @param pCallback pointer to the Get Data Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->GetDataCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Get Data JPEG Callback
+ * Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief Register Data Ready JPEG Callback
+ * To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @param pCallback pointer to the Get Data Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
+ pJPEG_DataReadyCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->DataReadyCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Data Ready JPEG Callback
+ * Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback
+ * @param hjpeg JPEG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hjpeg);
+
+ if (HAL_JPEG_STATE_READY == hjpeg->State)
+ {
+ hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hjpeg);
+ return status;
+}
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions
- * @brief JPEG Configuration functions.
- *
+ * @brief JPEG Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -654,11 +1115,11 @@ __weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
*/
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
{
- uint32_t error = HAL_OK;
- uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU;
+ uint32_t error;
+ uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
/* Check the JPEG handle allocation */
- if( (hjpeg == NULL) || (pConf == NULL) )
+ if ((hjpeg == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
@@ -672,7 +1133,7 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -686,63 +1147,65 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;
/* Set Number of color components*/
- if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
+ if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
{
/*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/
hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;
JPEG_SetColorGrayScale(hjpeg);
/* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
}
- else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
+ else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
{
/*
Set the Color Space for YCbCr : 2 quantization tables are used
one for Luminance(Y) and one for both Chrominances (Cb & Cr)
- */
+ */
hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;
JPEG_SetColorYCBCR(hjpeg);
/* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
/*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
- if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
+ if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
{
+ /*Use user customized quantization tables , 1 table per component*/
/* use 3 quantization tables , one for each component*/
hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);
hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
/*Use Quantization 1 table for component 1*/
- hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
+ hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0;
/*Use Quantization 2 table for component 2*/
- hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);
+ hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);
hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1;
}
}
- else if(hjpeg->Conf.ColorSpace == JPEG_CMYK_COLORSPACE)
+ else /* ColorSpace == JPEG_CMYK_COLORSPACE */
{
JPEG_SetColorCMYK(hjpeg);
- /* Set quantization table 0*/
- error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));
+ /* Set quantization table 0*/
+ error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
/*By default quantization table 0 for All components*/
- if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/
+ if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
{
+ /*Use user customized quantization tables , 1 table per component*/
/* use 4 quantization tables , one for each component*/
hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));
- error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (uint32_t *)(hjpeg->Instance->QMEM3));
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
+ error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3));
/*Use Quantization 1 table for component 1*/
hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0;
@@ -755,7 +1218,7 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
}
}
- if(error != HAL_OK)
+ if (error != 0UL)
{
hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;
@@ -768,15 +1231,18 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
return HAL_ERROR;
}
/* Set the image size*/
- MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16)); /* set the number of lines*/
- MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16)); /* set the number of pixels per line*/
+ /* set the number of lines*/
+ MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16));
+ /* set the number of pixels per line*/
+ MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16));
+
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
+ if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
{
hfactor = 16;
vfactor = 16;
}
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
+ else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
{
hfactor = 16;
vfactor = 8;
@@ -788,27 +1254,27 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
}
hMCU = (hjpeg->Conf.ImageWidth / hfactor);
- if((hjpeg->Conf.ImageWidth % hfactor) != 0)
+ if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL)
{
hMCU++; /*+1 for horizontal incomplete MCU */
}
vMCU = (hjpeg->Conf.ImageHeight / vfactor);
- if((hjpeg->Conf.ImageHeight % vfactor) != 0)
+ if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL)
{
vMCU++; /*+1 for vertical incomplete MCU */
}
- numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
+ numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
/* Set the number of MCU*/
- hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);
+ hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);
hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
- /* Set the JPEG State to ready */
+ /* Set the JPEG State to ready */
hjpeg->State = HAL_JPEG_STATE_READY;
/* Return function status */
@@ -838,43 +1304,47 @@ HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *
uint32_t yblockNb, cBblockNb, cRblockNb;
/* Check the JPEG handle allocation */
- if((hjpeg == NULL) || (pInfo == NULL))
+ if ((hjpeg == NULL) || (pInfo == NULL))
{
return HAL_ERROR;
}
/*Read the conf parameters */
- if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
+ if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
{
pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;
}
- else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0)
+ else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL)
{
pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;
}
- else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
+ else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
{
pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;
}
+ else
+ {
+ return HAL_ERROR;
+ }
- pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16;
- pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16;
+ pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16;
+ pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16;
- if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
+ if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
{
yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;
cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;
cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;
- if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0))
+ if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
{
pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/
}
- else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0))
+ else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
{
pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
}
- else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0))
+ else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
{
pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;
}
@@ -905,7 +1375,7 @@ HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
/* Process locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/* Change the JPEG state */
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -941,7 +1411,7 @@ HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
/* Process locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/* Change the JPEG state */
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -971,24 +1441,25 @@ HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for JPEG module
* @param QTable0 pointer to uint8_t , define the user quantification table for color component 1.
- * If NULL assume no need to update the table and no error return
+ * If NULL assume no need to update the table and no error return
* @param QTable1 pointer to uint8_t , define the user quantification table for color component 2.
- * If NULL assume no need to update the table and no error return.
+ * If NULL assume no need to update the table and no error return.
* @param QTable2 pointer to uint8_t , define the user quantification table for color component 3,
- * If NULL assume no need to update the table and no error return.
+ * If NULL assume no need to update the table and no error return.
* @param QTable3 pointer to uint8_t , define the user quantification table for color component 4.
- * If NULL assume no need to update the table and no error return.
+ * If NULL assume no need to update the table and no error return.
*
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)
+HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
+ uint8_t *QTable2, uint8_t *QTable3)
{
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/* Change the DMA state */
hjpeg->State = HAL_JPEG_STATE_BUSY;
@@ -1023,8 +1494,8 @@ HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_
*/
/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions
- * @brief processing functions.
- *
+ * @brief processing functions.
+ *
@verbatim
==============================================================================
##### JPEG processing functions #####
@@ -1057,24 +1528,24 @@ HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
+HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State != HAL_JPEG_STATE_READY)
+ if (hjpeg->State != HAL_JPEG_STATE_READY)
{
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
@@ -1082,9 +1553,9 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
return HAL_BUSY;
}
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
+ if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
@@ -1095,15 +1566,12 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
/* Get tick */
tickstart = HAL_GetTick();
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
/*Store In/out buffers pointers and size*/
hjpeg->pJpegInBuffPtr = pDataInMCU;
hjpeg->pJpegOutBuffPtr = pDataOut;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
+ hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /* In Data length must be multiple of 4 Bytes (1 word)*/
+ hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple of 4 Bytes (1 word)*/
/*Reset In/out data counter */
hjpeg->JpegInCount = 0;
@@ -1113,11 +1581,11 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
JPEG_Init_Process(hjpeg);
/*JPEG data processing : In/Out FIFO transfer*/
- while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
+ while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* Update error code */
@@ -1126,8 +1594,8 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
- /*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
+ /*Change JPEG state*/
+ hjpeg->State = HAL_JPEG_STATE_READY;
return HAL_TIMEOUT;
}
@@ -1138,9 +1606,10 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
__HAL_UNLOCK(hjpeg);
/*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
+ hjpeg->State = HAL_JPEG_STATE_READY;
- }else
+ }
+ else
{
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
@@ -1163,17 +1632,17 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout)
+HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
{
return HAL_ERROR;
}
@@ -1184,7 +1653,7 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
/* Get tick */
tickstart = HAL_GetTick();
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
@@ -1194,15 +1663,11 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
/*Store In/out buffers pointers and size*/
hjpeg->pJpegInBuffPtr = pDataIn;
hjpeg->pJpegOutBuffPtr = pDataOutMCU;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
+ hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/
+ hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
/*Reset In/out data counter */
hjpeg->JpegInCount = 0;
@@ -1212,11 +1677,11 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
JPEG_Init_Process(hjpeg);
/*JPEG data processing : In/Out FIFO transfer*/
- while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
+ while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* Update error code */
@@ -1226,7 +1691,7 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
__HAL_UNLOCK(hjpeg);
/*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
+ hjpeg->State = HAL_JPEG_STATE_READY;
return HAL_TIMEOUT;
}
@@ -1237,9 +1702,10 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
__HAL_UNLOCK(hjpeg);
/*Change JPEG state*/
- hjpeg->State= HAL_JPEG_STATE_READY;
+ hjpeg->State = HAL_JPEG_STATE_READY;
- }else
+ }
+ else
{
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
@@ -1260,15 +1726,15 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,
* @param OutDataLength size in bytes of the Output buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
+HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength)
{
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
{
return HAL_ERROR;
}
@@ -1276,7 +1742,7 @@ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataI
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State != HAL_JPEG_STATE_READY)
+ if (hjpeg->State != HAL_JPEG_STATE_READY)
{
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
@@ -1285,7 +1751,7 @@ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataI
}
else
{
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
+ if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
@@ -1294,15 +1760,11 @@ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataI
hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
/*Store In/out buffers pointers and size*/
hjpeg->pJpegInBuffPtr = pDataInMCU;
hjpeg->pJpegOutBuffPtr = pDataOut;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
+ hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/
+ hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
/*Reset In/out data counter */
hjpeg->JpegInCount = 0;
@@ -1334,15 +1796,15 @@ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataI
* @param OutDataLength size in bytes of the Output buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
+HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength)
{
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
{
return HAL_ERROR;
}
@@ -1350,7 +1812,7 @@ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataI
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
@@ -1359,15 +1821,11 @@ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataI
hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);
- /*In/Out Data length must be multiple of 4 Bytes (1 word)*/
- InDataLength = InDataLength - (InDataLength % 4);
- OutDataLength = OutDataLength - (OutDataLength % 4);
-
/*Store In/out buffers pointers and size*/
hjpeg->pJpegInBuffPtr = pDataIn;
hjpeg->pJpegOutBuffPtr = pDataOutMCU;
- hjpeg->InDataLength = InDataLength;
- hjpeg->OutDataLength = OutDataLength;
+ hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/
+ hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/
/*Reset In/out data counter */
hjpeg->JpegInCount = 0;
@@ -1398,15 +1856,15 @@ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataI
* @param OutDataLength size in bytes of the Output buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)
+HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+ uint8_t *pDataOut, uint32_t OutDataLength)
{
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
{
return HAL_ERROR;
}
@@ -1414,7 +1872,7 @@ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pData
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State != HAL_JPEG_STATE_READY)
+ if (hjpeg->State != HAL_JPEG_STATE_READY)
{
/* Process Unlocked */
__HAL_UNLOCK(hjpeg);
@@ -1423,7 +1881,7 @@ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pData
}
else
{
- if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )
+ if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
@@ -1446,7 +1904,15 @@ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pData
JPEG_Init_Process(hjpeg);
/* JPEG encoding process using DMA */
- JPEG_DMA_StartProcess(hjpeg);
+ if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
+ {
+ /* Update State */
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+
+ return HAL_ERROR;
+ }
}
else
@@ -1471,15 +1937,15 @@ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pData
* @param OutDataLength size in bytes of the Output buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)
+HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+ uint8_t *pDataOutMCU, uint32_t OutDataLength)
{
/* Check the parameters */
- assert_param((InDataLength >= 4));
- assert_param((OutDataLength >= 4));
+ assert_param((InDataLength >= 4UL));
+ assert_param((OutDataLength >= 4UL));
/* Check In/out buffer allocation and size */
- if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \
- (InDataLength == 0) || (OutDataLength == 0))
+ if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
{
return HAL_ERROR;
}
@@ -1487,7 +1953,7 @@ HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pData
/* Process Locked */
__HAL_LOCK(hjpeg);
- if(hjpeg->State == HAL_JPEG_STATE_READY)
+ if (hjpeg->State == HAL_JPEG_STATE_READY)
{
/*Change JPEG state*/
hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
@@ -1510,8 +1976,15 @@ HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pData
JPEG_Init_Process(hjpeg);
/* JPEG decoding process using DMA */
- JPEG_DMA_StartProcess(hjpeg);
+ if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
+ {
+ /* Update State */
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+ return HAL_ERROR;
+ }
}
else
{
@@ -1540,37 +2013,41 @@ HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelect
assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+ if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
{
hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
mask |= JPEG_DMA_IDMA;
}
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
{
hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
mask |= JPEG_DMA_ODMA;
}
- JPEG_DISABLE_DMA(hjpeg,mask);
+ JPEG_DISABLE_DMA(hjpeg, mask);
}
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+ else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
{
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
{
hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
}
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
{
hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
- mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
+ mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
}
- __HAL_JPEG_DISABLE_IT(hjpeg,mask);
+ __HAL_JPEG_DISABLE_IT(hjpeg, mask);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Return function status */
return HAL_OK;
@@ -1592,66 +2069,81 @@ HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelec
assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
- if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0))
+ if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL)
{
/* if nothing paused to resume return error*/
return HAL_ERROR;
}
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+ if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
{
hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
mask |= JPEG_DMA_IDMA;
/*JPEG Input DMA transfer data number must be multiple of DMA buffer size
as the destination is a 32 bits register */
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
- if(hjpeg->InDataLength > 0)
+ if (hjpeg->InDataLength > 0UL)
{
/* Start DMA FIFO In transfer */
- HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);
+ if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+ hjpeg->InDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ return HAL_ERROR;
+ }
}
-
}
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
{
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
- if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
+ if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
{
JPEG_DMA_PollResidualData(hjpeg);
}
else
{
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
mask |= JPEG_DMA_ODMA;
/* Start DMA FIFO Out transfer */
- HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);
+ if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+ hjpeg->OutDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ return HAL_ERROR;
+ }
}
}
- JPEG_ENABLE_DMA(hjpeg,mask);
+ JPEG_ENABLE_DMA(hjpeg, mask);
}
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+ else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
{
- if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
{
hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
}
- if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+ if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
{
hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
- mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
+ mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
}
- __HAL_JPEG_ENABLE_IT(hjpeg,mask);
+ __HAL_JPEG_ENABLE_IT(hjpeg, mask);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Return function status */
return HAL_OK;
@@ -1694,17 +2186,29 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
{
uint32_t tickstart, tmpContext;
-
tmpContext = hjpeg->Context;
/*Reset the Context operation and method*/
hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);
- if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+ if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
/* Stop the DMA In/out Xfer*/
- HAL_DMA_Abort(hjpeg->hdmaout);
- HAL_DMA_Abort(hjpeg->hdmain);
+ if (HAL_DMA_Abort(hjpeg->hdmaout) != HAL_OK)
+ {
+ if (hjpeg->hdmaout->ErrorCode == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ }
+ }
+ if (HAL_DMA_Abort(hjpeg->hdmain) != HAL_OK)
+ {
+ if (hjpeg->hdmain->ErrorCode == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ }
+ }
+
}
/* Stop the JPEG encoding/decoding process*/
@@ -1714,36 +2218,32 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
tickstart = HAL_GetTick();
/* Check if the JPEG Codec is effectively disabled */
- while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET)
+ while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE)
{
/* Update error code */
hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
/* Change the DMA state */
- hjpeg->State = HAL_JPEG_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
-
- return HAL_TIMEOUT;
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ break;
}
}
/* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
/* Disable All DMA requests */
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
/* Flush input and output FIFOs*/
hjpeg->Instance->CR |= JPEG_CR_IFF;
hjpeg->Instance->CR |= JPEG_CR_OFF;
/* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
/* Reset JpegInCount and JpegOutCount */
hjpeg->JpegInCount = 0;
@@ -1753,13 +2253,23 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);
/* Change the DMA state*/
- hjpeg->State = HAL_JPEG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
+ if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE)
+ {
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ hjpeg->State = HAL_JPEG_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+ /* Return function status */
+ return HAL_OK;
+ }
- /* Return function status */
- return HAL_OK;
}
@@ -1768,8 +2278,8 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
*/
/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions
- * @brief JPEG process callback functions.
- *
+ * @brief JPEG process callback functions.
+ *
@verbatim
==============================================================================
##### JPEG Decode and Encode callback functions #####
@@ -1794,7 +2304,7 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
* The JPEG decoded header informations
* @retval None
*/
-__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo)
+__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hjpeg);
@@ -1843,7 +2353,7 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
* the configuration information for JPEG module
* @retval None
*/
- __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
+__weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hjpeg);
@@ -1860,7 +2370,7 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
* @param NbDecodedData Number of consummed data in the previous chunk in bytes
* @retval None
*/
- __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
+__weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hjpeg);
@@ -1879,7 +2389,7 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
* @param OutDataLength number in bytes of data available in the specified output buffer
* @retval None
*/
-__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
+__weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hjpeg);
@@ -1897,8 +2407,8 @@ __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDat
/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management
- * @brief JPEG IRQ handler.
- *
+ * @brief JPEG IRQ handler.
+ *
@verbatim
==============================================================================
##### JPEG IRQ handler management #####
@@ -1918,22 +2428,24 @@ __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDat
*/
void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
{
- switch(hjpeg->State)
+ switch (hjpeg->State)
{
case HAL_JPEG_STATE_BUSY_ENCODING:
case HAL_JPEG_STATE_BUSY_DECODING:
/* continue JPEG data encoding/Decoding*/
/* JPEG data processing : In/Out FIFO transfer*/
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+ if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
{
- JPEG_Process(hjpeg);
+ (void) JPEG_Process(hjpeg);
}
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+ else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
JPEG_DMA_ContinueProcess(hjpeg);
-
}
-
+ else
+ {
+ /* Nothing to do */
+ }
break;
default:
@@ -1946,8 +2458,8 @@ void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
*/
/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -1972,11 +2484,11 @@ HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)
}
/**
-* @brief Return the JPEG error code
-* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+ * @brief Return the JPEG error code
+ * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for the specified JPEG.
-* @retval JPEG Error Code
-*/
+ * @retval JPEG Error Code
+ */
uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
{
return hjpeg->ErrorCode;
@@ -2009,16 +2521,18 @@ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize
/* Figure C.1: Generation of table of Huffman code sizes */
p = 0;
- for (l = 0; l < 16; l++)
+ for (l = 0; l < 16UL; l++)
{
i = (uint32_t)Bits[l];
- if ( (p + i) > 256)
- { /* check for table overflow */
+ if ((p + i) > 256UL)
+ {
+ /* check for table overflow */
return HAL_ERROR;
}
- while (i != 0)
+ while (i != 0UL)
{
- Huffsize[p++] = (uint8_t) l+1;
+ Huffsize[p] = (uint8_t) l + 1U;
+ p++;
i--;
}
}
@@ -2029,14 +2543,19 @@ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize
code = 0;
si = Huffsize[0];
p = 0;
- while (Huffsize[p] != 0)
+ while (Huffsize[p] != 0U)
{
while (((uint32_t) Huffsize[p]) == si)
{
- Huffcode[p++] = code;
+ Huffcode[p] = code;
+ p++;
code++;
}
/* code must fit in "size" bits (si), no code is allowed to be all ones*/
+ if(si > 31UL)
+ {
+ return HAL_ERROR;
+ }
if (((uint32_t) code) >= (((uint32_t) 1) << si))
{
return HAL_ERROR;
@@ -2055,49 +2574,50 @@ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize
* @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table
* @retval HAL status
*/
-static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
+ JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
{
HAL_StatusTypeDef error;
uint8_t huffsize[257];
uint32_t huffcode[257];
uint32_t k;
- uint32_t l,lsb, msb;
+ uint32_t l, lsb, msb;
uint32_t lastK;
error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
- if(error != HAL_OK)
+ if (error != HAL_OK)
{
return error;
}
/* Figure C.3: Ordering procedure for encoding procedure code tables */
- k=0;
+ k = 0;
- while(k < lastK)
+ while (k < lastK)
{
l = AC_BitsValsTable->HuffVal[k];
- if(l == 0)
+ if (l == 0UL)
{
l = 160; /*l = 0x00 EOB code*/
}
- else if(l == 0xF0)/* l = 0xF0 ZRL code*/
+ else if (l == 0xF0UL) /* l = 0xF0 ZRL code*/
{
l = 161;
}
else
{
- msb = (l & 0xF0) >> 4;
- lsb = (l & 0x0F);
- l = (msb * 10) + lsb - 1;
+ msb = (l & 0xF0UL) >> 4;
+ lsb = (l & 0x0FUL);
+ l = (msb * 10UL) + lsb - 1UL;
}
- if(l >= JPEG_AC_HUFF_TABLE_SIZE)
+ if (l >= JPEG_AC_HUFF_TABLE_SIZE)
{
return HAL_ERROR; /* Huffman Table overflow error*/
}
else
{
AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
- AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
+ AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U;
k++;
}
}
@@ -2113,7 +2633,8 @@ static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeD
* @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table
* @retval HAL status
*/
-static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
+ JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
{
HAL_StatusTypeDef error;
@@ -2123,24 +2644,24 @@ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeD
uint8_t huffsize[257];
uint32_t huffcode[257];
error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
- if(error != HAL_OK)
+ if (error != HAL_OK)
{
return error;
}
/* Figure C.3: ordering procedure for encoding procedure code tables */
- k=0;
+ k = 0;
- while(k < lastK)
+ while (k < lastK)
{
l = DC_BitsValsTable->HuffVal[k];
- if(l >= JPEG_DC_HUFF_TABLE_SIZE)
+ if (l >= JPEG_DC_HUFF_TABLE_SIZE)
{
return HAL_ERROR; /* Huffman Table overflow error*/
}
else
{
DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];
- DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;
+ DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U;
k++;
}
}
@@ -2157,30 +2678,31 @@ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeD
* @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
* @retval HAL status
*/
-static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress)
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
+ const __IO uint32_t *DCTableAddress)
{
- HAL_StatusTypeDef error = HAL_OK;
+ HAL_StatusTypeDef error;
JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
uint32_t i, lsb, msb;
__IO uint32_t *address, *addressDef;
- if(DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC0))
+ if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
{
- address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2));
+ address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
}
- else if (DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC1))
+ else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1))
{
- address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2));
+ address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
}
else
{
return HAL_ERROR;
}
- if(HuffTableDC != NULL)
+ if (HuffTableDC != NULL)
{
error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);
- if(error != HAL_OK)
+ if (error != HAL_OK)
{
return error;
}
@@ -2190,13 +2712,15 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH
*addressDef = 0x0FFF0FFF;
i = JPEG_DC_HUFF_TABLE_SIZE;
- while(i>0)
+ while (i > 1UL)
{
i--;
address --;
- msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
+ msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] &
+ 0xFFUL);
i--;
- lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);
+ lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] &
+ 0xFFUL);
*address = lsb | (msb << 16);
}
@@ -2214,30 +2738,31 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH
* @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
* @retval HAL status
*/
-static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress)
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
+ const __IO uint32_t *ACTableAddress)
{
- HAL_StatusTypeDef error = HAL_OK;
+ HAL_StatusTypeDef error;
JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;
uint32_t i, lsb, msb;
__IO uint32_t *address, *addressDef;
- if(ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC0))
+ if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0))
{
- address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2));
+ address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
}
- else if (ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC1))
+ else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1))
{
- address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2));
+ address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
}
else
{
return HAL_ERROR;
}
- if(HuffTableAC != NULL)
+ if (HuffTableAC != NULL)
{
error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);
- if(error != HAL_OK)
+ if (error != HAL_OK)
{
return error;
}
@@ -2245,7 +2770,7 @@ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACH
/* Locations 162:175 of each AC table contain information used internally by the core */
addressDef = address;
- for(i=0; i<3; i++)
+ for (i = 0; i < 3UL; i++)
{
*addressDef = 0x0FFF0FFF;
addressDef++;
@@ -2261,13 +2786,15 @@ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACH
i = JPEG_AC_HUFF_TABLE_SIZE;
- while (i > 0)
+ while (i > 1UL)
{
i--;
address--;
- msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
+ msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] &
+ 0xFFUL);
i--;
- lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);
+ lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] &
+ 0xFFUL);
*address = lsb | (msb << 16);
}
@@ -2282,52 +2809,39 @@ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACH
* the encdoing operation
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for JPEG module
- * @param HuffTableAC0 AC0 huffman table
- * @param HuffTableDC0 DC0 huffman table
- * @param HuffTableAC1 AC1 huffman table
- * @param HuffTableDC1 DC1 huffman table
* @retval None
*/
-static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg)
{
- HAL_StatusTypeDef error = HAL_OK;
-
- JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1);
+ HAL_StatusTypeDef error;
- if(HuffTableAC0 != NULL)
+ JPEG_Set_Huff_DHTMem(hjpeg);
+ error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable,
+ (hjpeg->Instance->HUFFENC_AC0));
+ if (error != HAL_OK)
{
- error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (uint32_t *)(hjpeg->Instance->HUFFENC_AC0));
- if(error != HAL_OK)
- {
- return error;
- }
+ return error;
}
- if(HuffTableAC1 != NULL)
+ error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable,
+ (hjpeg->Instance->HUFFENC_AC1));
+ if (error != HAL_OK)
{
- error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (uint32_t *)(hjpeg->Instance->HUFFENC_AC1));
- if(error != HAL_OK)
- {
- return error;
- }
+ return error;
}
- if(HuffTableDC0 != NULL)
+ error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable,
+ hjpeg->Instance->HUFFENC_DC0);
+ if (error != HAL_OK)
{
- error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, (uint32_t *)hjpeg->Instance->HUFFENC_DC0);
- if(error != HAL_OK)
- {
- return error;
- }
+ return error;
}
- if(HuffTableDC1 != NULL)
+ error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable,
+ hjpeg->Instance->HUFFENC_DC1);
+ if (error != HAL_OK)
{
- error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, (uint32_t *)hjpeg->Instance->HUFFENC_DC1);
- if(error != HAL_OK)
- {
- return error;
- }
+ return error;
}
/* Return function status */
return HAL_OK;
@@ -2338,196 +2852,188 @@ static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_AC
* file header (used for encoding only)
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for JPEG module
- * @param HuffTableAC0 AC0 huffman table
- * @param HuffTableDC0 DC0 huffman table
- * @param HuffTableAC1 AC1 huffman table
- * @param HuffTableDC1 DC1 huffman table
* @retval None
*/
-static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)
+static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg)
{
+ JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable;
+ JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable;
+ JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable;
+ JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable;
uint32_t value, index;
__IO uint32_t *address;
- if(HuffTableDC0 != NULL)
+
+ /* DC0 Huffman Table : BITS*/
+ /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
+ address = (hjpeg->Instance->DHTMEM + 3);
+ index = 16;
+ while (index > 3UL)
{
- /* DC0 Huffman Table : BITS*/
- /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
- address = (hjpeg->Instance->DHTMEM + 3);
- index = 16;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF);
- address--;
- index -=4;
+ *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL);
+ address--;
+ index -= 4UL;
- }
- /* DC0 Huffman Table : Val*/
- /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
- address = (hjpeg->Instance->DHTMEM + 6);
- index = 12;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF);
- address--;
- index -=4;
- }
}
-
- if(HuffTableAC0 != NULL)
+ /* DC0 Huffman Table : Val*/
+ /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
+ address = (hjpeg->Instance->DHTMEM + 6);
+ index = 12;
+ while (index > 3UL)
{
- /* AC0 Huffman Table : BITS*/
- /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
- address = (hjpeg->Instance->DHTMEM + 10);
- index = 16;
- while(index > 0)
- {
-
- *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF);
- address--;
- index -=4;
-
- }
- /* AC0 Huffman Table : Val*/
- /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
- address = (hjpeg->Instance->DHTMEM + 51);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF);
- *address = value;
-
- /*continue setting 160 AC0 huffman values */
- address--; /* address = hjpeg->Instance->DHTMEM + 50*/
- index = 160;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF);
- address--;
- index -=4;
- }
+ *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL);
+ address--;
+ index -= 4UL;
}
- if(HuffTableDC1 != NULL)
+ /* AC0 Huffman Table : BITS*/
+ /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
+ address = (hjpeg->Instance->DHTMEM + 10UL);
+ index = 16;
+ while (index > 3UL)
{
- /* DC1 Huffman Table : BITS*/
- /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 51);
- value = *address & 0x0000FFFFU;
- value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16);
- *address = value;
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 55);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF);
- *address = value;
-
- /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
+ *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL);
address--;
- index = 12;
- while(index > 0)
- {
+ index -= 4UL;
- *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF);
- address--;
- index -=4;
+ }
+ /* AC0 Huffman Table : Val*/
+ /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
+ address = (hjpeg->Instance->DHTMEM + 51);
+ value = *address & 0xFFFF0000U;
+ value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL);
+ *address = value;
+
+ /*continue setting 160 AC0 huffman values */
+ address--; /* address = hjpeg->Instance->DHTMEM + 50*/
+ index = 160;
+ while (index > 3UL)
+ {
+ *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL);
+ address--;
+ index -= 4UL;
+ }
- }
- /* DC1 Huffman Table : Val*/
- /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
- address = (hjpeg->Instance->DHTMEM + 55);
- value = *address & 0x0000FFFF;
- value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16);
- *address = value;
+ /* DC1 Huffman Table : BITS*/
+ /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
+ address = (hjpeg->Instance->DHTMEM + 51);
+ value = *address & 0x0000FFFFU;
+ value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16);
+ *address = value;
+
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
+ address = (hjpeg->Instance->DHTMEM + 55);
+ value = *address & 0xFFFF0000U;
+ value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL);
+ *address = value;
+
+ /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
+ address--;
+ index = 12;
+ while (index > 3UL)
+ {
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
- address = (hjpeg->Instance->DHTMEM + 58);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF);
- *address = value;
+ *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL);
+ address--;
+ index -= 4UL;
- /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
+ }
+ /* DC1 Huffman Table : Val*/
+ /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
+ address = (hjpeg->Instance->DHTMEM + 55);
+ value = *address & 0x0000FFFFUL;
+ value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) <<
+ 16);
+ *address = value;
+
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
+ address = (hjpeg->Instance->DHTMEM + 58);
+ value = *address & 0xFFFF0000UL;
+ value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL);
+ *address = value;
+
+ /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
+ address--;
+ index = 8;
+ while (index > 3UL)
+ {
+ *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL);
address--;
- index = 8;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF);
- address--;
- index -=4;
- }
+ index -= 4UL;
}
- if(HuffTableAC1 != NULL)
+ /* AC1 Huffman Table : BITS*/
+ /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
+ address = (hjpeg->Instance->DHTMEM + 58);
+ value = *address & 0x0000FFFFU;
+ value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16);
+ *address = value;
+
+ /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
+ address = (hjpeg->Instance->DHTMEM + 62);
+ value = *address & 0xFFFF0000U;
+ value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL);
+ *address = value;
+
+ /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
+ address--;
+ index = 12;
+ while (index > 3UL)
{
- /* AC1 Huffman Table : BITS*/
- /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
- address = (hjpeg->Instance->DHTMEM + 58);
- value = *address & 0x0000FFFFU;
- value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16);
- *address = value;
-
- /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
- address = (hjpeg->Instance->DHTMEM + 62);
- value = *address & 0xFFFF0000U;
- value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF);
- *address = value;
- /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
+ *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL);
address--;
- index = 12;
- while(index > 0)
- {
+ index -= 4UL;
- *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF);
- address--;
- index -=4;
-
- }
- /* AC1 Huffman Table : Val*/
- /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
- /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
- address = (hjpeg->Instance->DHTMEM + 62);
- value = *address & 0x0000FFFF;
- value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16);
- *address = value;
-
- /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
- address = (hjpeg->Instance->DHTMEM + 102);
- index = 160;
- while(index > 0)
- {
- *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)|
- (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)|
- (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) |
- ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF);
- address--;
- index -=4;
- }
}
+ /* AC1 Huffman Table : Val*/
+ /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
+ /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
+ address = (hjpeg->Instance->DHTMEM + 62);
+ value = *address & 0x0000FFFFUL;
+ value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) <<
+ 16);
+ *address = value;
+
+ /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
+ address = (hjpeg->Instance->DHTMEM + 102);
+ index = 160;
+ while (index > 3UL)
+ {
+ *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
+ (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) |
+ (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
+ ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL);
+ address--;
+ index -= 4UL;
+ }
+
}
/**
@@ -2537,66 +3043,62 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableType
* @param QTable pointer to an array of 64 bytes giving the quantization table
* @param QTableAddress destination quantization address in the JPEG peripheral
* it could be QMEM0, QMEM1, QMEM2 or QMEM3
- * @retval None
+ * @retval 0 if no error, 1 if error
*/
-static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress)
+static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
+ __IO uint32_t *QTableAddress)
{
- uint32_t i, j, *tableAddress, quantRow, quantVal, ScaleFactor;
+ uint32_t i, j, quantRow, quantVal, ScaleFactor;
+ __IO uint32_t *tableAddress;
- if((QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM0))) ||
- (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM1))) ||
- (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM2))) ||
- (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM3))))
- {
- tableAddress = QTableAddress;
- }
- else
- {
- return HAL_ERROR;
- }
+ tableAddress = QTableAddress;
- if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100))
+ if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL))
{
- ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2);
+ ScaleFactor = 200UL - (hjpeg->Conf.ImageQuality * 2UL);
}
- else if (hjpeg->Conf.ImageQuality > 0)
+ else if (hjpeg->Conf.ImageQuality > 0UL)
{
ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);
}
else
{
- return HAL_ERROR;
+ return 1UL;
}
/*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/
i = 0;
- while( i < JPEG_QUANT_TABLE_SIZE)
+ while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
{
quantRow = 0;
- for(j=0; j<4; j++)
+ for (j = 0; j < 4UL; j++)
{
/* Note that the quantization coefficients must be specified in the table in zigzag order */
- quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100;
+ quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL;
- if(quantVal == 0)
+ if (quantVal == 0UL)
{
- quantVal = 1;
+ quantVal = 1UL;
}
- else if (quantVal > 255)
+ else if (quantVal > 255UL)
{
- quantVal = 255;
+ quantVal = 255UL;
+ }
+ else
+ {
+ /* Nothing to do, keep same value of quantVal */
}
- quantRow |= ((quantVal & 0xFF) << (8 * j));
+ quantRow |= ((quantVal & 0xFFUL) << (8UL * j));
}
- i += 4;
+ i += 4UL;
*tableAddress = quantRow;
tableAddress ++;
}
/* Return function status */
- return HAL_OK;
+ return 0UL;
}
/**
@@ -2616,14 +3118,14 @@ static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1;
/* compute MCU block size and Y, Cb ,Cr sampling factors*/
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
+ if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
{
ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/
yblockNb = 0x30; /* 4 blocks of 8x8*/
}
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
+ else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
{
ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
@@ -2639,24 +3141,24 @@ static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
}
hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
- hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
+ hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
/*Reset CONFR4 register*/
hjpeg->Instance->CONFR4 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
- hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
+ hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
/*Reset CONFR5 register*/
hjpeg->Instance->CONFR5 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
- hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);
+ hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);
/*Reset CONFR6 register*/
hjpeg->Instance->CONFR6 = 0;
/*Set Horizental and Vertical sampling factor and number of blocks for component 2*/
/* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */
/* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */
- hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);
+ hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);
}
@@ -2696,14 +3198,14 @@ static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);
/* compute MCU block size and Y, Cb ,Cr sampling factors*/
- if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
+ if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
{
ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/
yblockNb = 0x30; /* 4 blocks of 8x8*/
}
- else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
+ else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
{
ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/
ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/
@@ -2721,22 +3223,22 @@ static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
/*Reset CONFR4 register*/
hjpeg->Instance->CONFR4 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/
- hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );
+ hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
/*Reset CONFR5 register*/
hjpeg->Instance->CONFR5 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/
- hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
+ hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
/*Reset CONFR6 register*/
hjpeg->Instance->CONFR6 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/
- hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
+ hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
/*Reset CONFR7 register*/
hjpeg->Instance->CONFR7 = 0;
/*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/
- hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
+ hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
}
/**
@@ -2750,12 +3252,12 @@ static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
/*Reset pause*/
hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));
- if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
/*Set JPEG Codec to Decoding mode */
hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;
}
- else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
+ else /* JPEG_CONTEXT_ENCODE */
{
/*Set JPEG Codec to Encoding mode */
hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;
@@ -2765,32 +3267,35 @@ static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
/* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
/* Disable All DMA requests */
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);
-
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
/* Flush input and output FIFOs*/
hjpeg->Instance->CR |= JPEG_CR_IFF;
hjpeg->Instance->CR |= JPEG_CR_OFF;
/* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
/*Start Encoding/Decoding*/
hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START;
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+ if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
{
/*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/
- __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD);
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD);
}
- else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+ else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
/*Enable End Of Conversation, and End Of Header parsing interruptions*/
- __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD);
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
@@ -2804,79 +3309,99 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
uint32_t tmpContext;
/*End of header processing flag rised*/
- if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
+ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
- /*Call Header parsing complet callback */
- HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
- /* Reset the ImageQuality */
- hjpeg->Conf.ImageQuality = 0;
- /* Note : the image quality is only available at the end of the decoding operation */
- /* at the current stage the calculated image quality is not correct so reset it */
-
- /*Call Info Ready callback */
- HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
-
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
-
- /* Clear header processing done flag */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
+ {
+ /*Call Header parsing complet callback */
+ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
+ /* Reset the ImageQuality */
+ hjpeg->Conf.ImageQuality = 0;
+ /* Note : the image quality is only available at the end of the decoding operation */
+ /* at the current stage the calculated image quality is not correct so reset it */
+
+ /*Call Info Ready callback */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#else
+ HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
+
+ /* Clear header processing done flag */
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
+ }
}
/*Input FIFO status handling*/
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0)
+ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL)
{
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL)
{
/*Input FIFO threshold flag rised*/
- /*4 words (16 bytes) can be written in */
- JPEG_ReadInputData(hjpeg,4);
+ /*JPEG_FIFO_TH_SIZE words can be written in */
+ JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE);
}
- else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET)
+ else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL)
{
/*Input FIFO Not Full flag rised*/
/*32-bit value can be written in */
- JPEG_ReadInputData(hjpeg,1);
+ JPEG_ReadInputData(hjpeg, 1);
+ }
+ else
+ {
+ /* Nothing to do */
}
}
/*Output FIFO flag handling*/
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
+ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
{
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL)
{
/*Output FIFO threshold flag rised*/
- /*4 words (16 bytes) can be read out */
- JPEG_StoreOutputData(hjpeg, 4);
+ /*JPEG_FIFO_TH_SIZE words can be read out */
+ JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
}
- else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET)
+ else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
{
/*Output FIFO Not Empty flag rised*/
/*32-bit value can be read out */
JPEG_StoreOutputData(hjpeg, 1);
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)
{
/*Stop Encoding/Decoding*/
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
- if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+ if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
{
/* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
}
/* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
/*Call End of conversion callback */
- if(hjpeg->JpegOutCount > 0)
+ if (hjpeg->JpegOutCount > 0UL)
{
/*Output Buffer is not empty, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
hjpeg->JpegOutCount = 0;
}
@@ -2892,13 +3417,21 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
hjpeg->State = HAL_JPEG_STATE_READY;
/*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+ if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DecodeCpltCallback(hjpeg);
+#else
HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
}
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
+ else /* JPEG_CONTEXT_ENCODE */
{
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->EncodeCpltCallback(hjpeg);
+#else
HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif
}
return JPEG_PROCESS_DONE;
@@ -2919,63 +3452,84 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
{
- uint32_t index, nBwords, nbBytes , dataword, *pOutData;
+ uint32_t index, nBwords, nbBytes, dataword;
- pOutData = (uint32_t *)(((uint32_t *)hjpeg->pJpegOutBuffPtr) + (hjpeg->JpegOutCount/4));
-
- if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4)))
+ if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
{
- for(index = 0; index < nbOutputWords; index++)
+ for (index = 0; index < nbOutputWords; index++)
{
/*Transfer 32 bits from the JPEG output FIFO*/
- *pOutData = hjpeg->Instance->DOR;
- pOutData++;
- hjpeg->JpegOutCount += 4;
+ dataword = hjpeg->Instance->DOR;
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
+ hjpeg->JpegOutCount += 4UL;
}
- if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
+ if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
{
/*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
hjpeg->JpegOutCount = 0;
}
}
- else if(hjpeg->OutDataLength > hjpeg->JpegOutCount)
+ else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
{
- nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4;
- for(index = 0; index < nBwords; index++)
+ nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
+ for (index = 0; index < nBwords; index++)
{
/*Transfer 32 bits from the JPEG output FIFO*/
- *pOutData = hjpeg->Instance->DOR;
- pOutData++;
- hjpeg->JpegOutCount += 4;
+ dataword = hjpeg->Instance->DOR;
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
+ hjpeg->JpegOutCount += 4UL;
}
- if(hjpeg->OutDataLength == hjpeg->JpegOutCount)
+ if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
{
/*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
hjpeg->JpegOutCount = 0;
}
else
{
nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
dataword = hjpeg->Instance->DOR;
- for(index = 0; index < nbBytes; index++)
+ for (index = 0; index < nbBytes; index++)
{
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
hjpeg->JpegOutCount++;
}
/*Output Buffer is full, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
hjpeg->JpegOutCount = 0;
- nbBytes = 4 - nbBytes;
- for(index = nbBytes; index < 4; index++)
+ nbBytes = 4UL - nbBytes;
+ for (index = nbBytes; index < 4UL; index++)
{
- hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
hjpeg->JpegOutCount++;
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
@@ -2989,58 +3543,75 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
*/
static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
{
- uint32_t nbBytes = 0, nBwords, index, Dataword;
+ uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
- if((hjpeg->InDataLength == 0) || (nbRequestWords == 0))
+ if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
{
/* No more Input data : nothing to do*/
- HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
+ (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
}
- else if(hjpeg->InDataLength > hjpeg->JpegInCount)
+ else if (hjpeg->InDataLength > hjpeg->JpegInCount)
{
nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
}
- else if(hjpeg->InDataLength == hjpeg->JpegInCount)
+ else if (hjpeg->InDataLength == hjpeg->JpegInCount)
{
/*Call HAL_JPEG_GetDataCallback to get new data */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#else
HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
- if(hjpeg->InDataLength > 4)
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
+
+ if (hjpeg->InDataLength > 4UL)
{
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
}
hjpeg->JpegInCount = 0;
nbBytes = hjpeg->InDataLength;
}
- if((nbBytes > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0))
+ else
{
- nBwords = nbBytes / 4;
- if(nBwords >= nbRequestWords)
+ /* Nothing to do */
+ }
+ if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
+ {
+ nBwords = nbBytes / 4UL;
+ if (nBwords >= nbRequestWords)
{
- for(index = 0; index < nbRequestWords; index++)
+ for (index = 0; index < nbRequestWords; index++)
{
- hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));
+ inputCount = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
- hjpeg->JpegInCount += 4;
+ hjpeg->JpegInCount += 4UL;
}
}
else /*nBwords < nbRequestWords*/
{
- if(nBwords > 0)
+ if (nBwords > 0UL)
{
- for(index = 0; index < nBwords; index++)
+ for (index = 0; index < nBwords; index++)
{
- hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));
+ inputCount = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
- hjpeg->JpegInCount += 4;
+ hjpeg->JpegInCount += 4UL;
}
}
else
{
/* end of file*/
Dataword = 0;
- for(index=0; index< nbBytes; index++)
+ for (index = 0; index < nbBytes; index++)
{
- Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index);
+ Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
hjpeg->JpegInCount++;
}
hjpeg->Instance->DIR = Dataword;
@@ -3057,7 +3628,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
*/
static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
{
- if((hjpeg->InDataLength < 4) || (hjpeg->OutDataLength < 4))
+ if ((hjpeg->InDataLength < 4UL) || (hjpeg->OutDataLength < 4UL))
{
return HAL_ERROR;
}
@@ -3065,7 +3636,7 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA;
/* Disable DMA In/Out Request*/
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA);
/* Set the JPEG DMA In transfer complete callback */
hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback;
@@ -3080,19 +3651,29 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback;
/*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
/*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/
- hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4);
+ hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL);
/* Start DMA FIFO In transfer */
- HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);
+ if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+ hjpeg->InDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ return HAL_ERROR;
+ }
/* Start DMA FIFO Out transfer */
- HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);
+ if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+ hjpeg->OutDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ return HAL_ERROR;
+ }
/* Enable JPEG In/Out DMA requests*/
- JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA | JPEG_DMA_ODMA);
+ JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA | JPEG_DMA_ODMA);
return HAL_OK;
}
@@ -3103,62 +3684,69 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
* the configuration information for JPEG module
* @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
*/
-static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
+static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
{
/*End of header processing flag rises*/
- if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))
+ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
- /*Call Header parsing complete callback */
- HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
+ {
+ /*Call Header parsing complete callback */
+ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
- /* Reset the ImageQuality */
- hjpeg->Conf.ImageQuality = 0;
- /* Note : the image quality is only available at the end of the decoding operation */
- /* at the current stage the calculated image quality is not correct so reset it */
+ /* Reset the ImageQuality */
+ hjpeg->Conf.ImageQuality = 0;
+ /* Note : the image quality is only available at the end of the decoding operation */
+ /* at the current stage the calculated image quality is not correct so reset it */
- /*Call Info Ready callback */
- HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
+ /*Call Info Ready callback */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#else
+ HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
- /* Clear header processing done flag */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);
+ /* Clear header processing done flag */
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
+ }
}
/*End of Conversion handling*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL)
{
/*Disabkle JPEG In/Out DMA Requests*/
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA);
hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;
/*Stop Encoding/Decoding*/
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
/* Clear all flags */
- __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);
+ __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
- if(hjpeg->hdmain->State == HAL_DMA_STATE_BUSY)
+ if (hjpeg->hdmain->State == HAL_DMA_STATE_BUSY)
{
/* Stop the DMA In Xfer*/
- HAL_DMA_Abort_IT(hjpeg->hdmain);
+ (void) HAL_DMA_Abort_IT(hjpeg->hdmain);
}
- if(hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY)
+ if (hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY)
{
/* Stop the DMA out Xfer*/
- HAL_DMA_Abort_IT(hjpeg->hdmaout);
+ (void) HAL_DMA_Abort_IT(hjpeg->hdmaout);
}
else
{
- return JPEG_DMA_EndProcess(hjpeg);
+ JPEG_DMA_EndProcess(hjpeg);
}
}
- return JPEG_PROCESS_ONGOING;
+
}
/**
@@ -3167,21 +3755,38 @@ static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
* the configuration information for JPEG module
* @retval JPEG_PROCESS_DONE
*/
-static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
+static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
{
uint32_t tmpContext;
hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2);
/*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
+ if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
{
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
hjpeg->JpegOutCount = 0;
}
/*Check if remaining data in the output FIFO*/
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL)
{
+ if (hjpeg->JpegOutCount > 0UL)
+ {
+ /*Output Buffer is not empty, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+ hjpeg->JpegOutCount = 0;
+ }
+
/*Stop Encoding/Decoding*/
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
@@ -3196,23 +3801,32 @@ static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
hjpeg->State = HAL_JPEG_STATE_READY;
/*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+ if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DecodeCpltCallback(hjpeg);
+#else
HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
}
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
+ else /* JPEG_CONTEXT_ENCODE */
{
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->EncodeCpltCallback(hjpeg);
+#else
HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
}
}
- else if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
+ else if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
{
JPEG_DMA_PollResidualData(hjpeg);
-
- return JPEG_PROCESS_DONE;
+ }
+ else
+ {
+ /* Nothing to do */
}
- return JPEG_PROCESS_ONGOING;
}
/**
@@ -3223,53 +3837,83 @@ static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut;
- pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount);
+ uint32_t tmpContext, count, dataOut;
- while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0))
+ for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
{
- count--;
-
- *pDataOut = hjpeg->Instance->DOR;
- pDataOut++;
- hjpeg->JpegOutCount += 4;
-
- if(hjpeg->JpegOutCount == hjpeg->OutDataLength)
+ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
{
- /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
+ {
+ dataOut = hjpeg->Instance->DOR;
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16);
+ hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24);
+ hjpeg->JpegOutCount += 4UL;
+
+ if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
+ {
+ /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+ hjpeg->JpegOutCount = 0;
+ }
+
+ }
}
}
- /*Stop Encoding/Decoding*/
- hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
+ tmpContext = hjpeg->Context;
- if(hjpeg->JpegOutCount > 0)
+ if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL))
{
- /*Output Buffer is not empty, call DecodedDataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
- hjpeg->JpegOutCount = 0;
- }
+ /*Stop Encoding/Decoding*/
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
- tmpContext = hjpeg->Context;
- /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
- hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
+ if (hjpeg->JpegOutCount > 0UL)
+ {
+ /*Output Buffer is not empty, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
- /* Process Unlocked */
- __HAL_UNLOCK(hjpeg);
+ hjpeg->JpegOutCount = 0;
+ }
- /* Change the JPEG state */
- hjpeg->State = HAL_JPEG_STATE_READY;
+ tmpContext = hjpeg->Context;
+ /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
- /*Call End of Encoding/Decoding callback */
- if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
- {
- HAL_JPEG_DecodeCpltCallback(hjpeg);
- }
- else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
- {
- HAL_JPEG_EncodeCpltCallback(hjpeg);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+
+ /* Change the JPEG state */
+ hjpeg->State = HAL_JPEG_STATE_READY;
+
+ /*Call End of Encoding/Decoding callback */
+ if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+ {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DecodeCpltCallback(hjpeg);
+#else
+ HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+ }
+ else /* JPEG_CONTEXT_ENCODE */
+ {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->EncodeCpltCallback(hjpeg);
+#else
+ HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+ }
}
}
@@ -3280,41 +3924,57 @@ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma)
{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
- if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
+ if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) ==
+ JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */
{
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_IDMA);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_IDMA);
hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);
/*Call HAL_JPEG_GetDataCallback to get new data */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#else
HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
- if(hjpeg->InDataLength >= 4)
+ if (hjpeg->InDataLength >= 4UL)
{
/*JPEG Input DMA transfer data number must be multiple of 32 bits word
as the destination is a 32 bits (4 bytes) register */
- hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);
+ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
}
- else if(hjpeg->InDataLength > 0)
+ else if (hjpeg->InDataLength > 0UL)
{
/*Transfer last data word (i.e last 4 bytes)*/
hjpeg->InDataLength = 4;
}
- if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0))
+ if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL))
{
/* Start DMA FIFO In transfer */
- HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);
- JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA);
+ if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+ hjpeg->InDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->ErrorCallback(hjpeg);
+#else
+ HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+ return;
+ }
+ JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA);
}
/* JPEG Conversion still on going : Enable the JPEG IT */
- __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
}
}
@@ -3325,34 +3985,51 @@ static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma)
*/
static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma)
{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
- if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))
+ if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) ==
+ JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */
{
- if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0)
+ if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL)
{
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA);
hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);
/*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
- HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+ HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
- if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
+ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
{
/* Start DMA FIFO Out transfer */
- HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);
- JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_ODMA);
+ if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+ hjpeg->OutDataLength >> 2) != HAL_OK)
+ {
+ hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+ hjpeg->State = HAL_JPEG_STATE_ERROR;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->ErrorCallback(hjpeg);
+#else
+ HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+ return;
+ }
+ JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_ODMA);
}
}
/* JPEG Conversion still on going : Enable the JPEG IT */
- __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);
+ __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
}
}
+
/**
* @brief DMA Transfer error callback
* @param hdma pointer to a DMA_HandleTypeDef structure.
@@ -3360,23 +4037,27 @@ static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma)
*/
static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma)
{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* if DMA error is FIFO error ignore it */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+ if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
/*Stop Encoding/Decoding*/
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
/* Disable All Interrupts */
- __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);
+ __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
/* Disable All DMA requests */
- JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);
+ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
- hjpeg->State= HAL_JPEG_STATE_READY;
+ hjpeg->State = HAL_JPEG_STATE_READY;
hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+ hjpeg->ErrorCallback(hjpeg);
+#else
HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
}
}
@@ -3387,14 +4068,15 @@ static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma)
*/
static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)
{
- JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
+ if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
{
JPEG_DMA_EndProcess(hjpeg);
}
}
+
/**
* @brief Calculate the decoded image quality (from 1 to 100)
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
@@ -3404,48 +4086,48 @@ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)
static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
{
uint32_t quality = 0;
- uint32_t quantRow, quantVal,scale, i, j;
- uint32_t *tableAddress = (uint32_t *)hjpeg->Instance->QMEM0;
+ uint32_t quantRow, quantVal, scale, i, j;
+ __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0;
i = 0;
- while( i < JPEG_QUANT_TABLE_SIZE)
+ while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
{
quantRow = *tableAddress;
- for(j=0; j<4; j++)
+ for (j = 0; j < 4UL; j++)
{
- quantVal = (quantRow >> (8 * j)) & 0xFF;
- if(quantVal == 1)
+ quantVal = (quantRow >> (8UL * j)) & 0xFFUL;
+ if (quantVal == 1UL)
{
/* if Quantization value = 1 then quality is 100%*/
- quality += 100;
+ quality += 100UL;
}
else
{
/* Note that the quantization coefficients must be specified in the table in zigzag order */
- scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]);
+ scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]);
- if(scale <= 100)
+ if (scale <= 100UL)
{
- quality += (200 - scale)/2;
+ quality += (200UL - scale) / 2UL;
}
else
{
- quality += 5000/scale;
+ quality += 5000UL / scale;
}
}
}
- i += 4;
+ i += 4UL;
tableAddress ++;
}
- return (quality/((uint32_t)64));
+ return (quality / 64UL);
}
/**
* @}
*/
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* JPEG */
#endif /* HAL_JPEG_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_lptim.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_lptim.c
index 8442cfb0a9643cfb5d82a6d6ace5b3a19f4c7d85..1decaa97d4c4b27870acea60cb1bdcdca5c7ca2e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_lptim.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_lptim.c
@@ -138,29 +138,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc.c
index bc6b37ab4bb38d3aea38cf8a20d7491aa9a02972..50671bfa3860b3d7ff4aa730e32f4f8e4f244df6 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc.c
@@ -40,18 +40,18 @@
value, the window size, the window position and the layer start address
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
- HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
+ HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
- (#) Variant functions with "_NoReload" post fix allows to set the LTDC configuration/settings without immediate reload.
+ (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
- then applying(reload) these settings in one shot by calling the function "HAL_LTDC_Reload"
-
- After calling the "_NoReload" functions to set different color/format/layer settings,
- the program can call the function "HAL_LTDC_Reload" To apply(Reload) these settings.
- Function "HAL_LTDC_Reload" can be called with the parameter "ReloadType"
- set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
- Function "HAL_LTDC_Reload" can be called with the parameter "ReloadType"
- set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
+ then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
+
+ After calling the _NoReload functions to set different color/format/layer settings,
+ the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
+ Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
+ an immediate reload is required.
+ Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
+ the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
@@ -64,15 +64,64 @@
(+) __HAL_LTDC_ENABLE: Enable the LTDC.
(+) __HAL_LTDC_DISABLE: Disable the LTDC.
- (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
- (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
- (+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration.
+ (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
+ (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
+ (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration.
(+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
(+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
(+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
(+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
(+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_LTDC_RegisterCallback() to register a callback.
+
+ Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback.
+ (+) ReloadEventCallback : LTDC Reload Event Callback.
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit.
+ (+) MspDeInitCallback : LTDC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback.
+ (+) ReloadEventCallback : LTDC Reload Event Callback.
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit.
+ (+) MspDeInitCallback : LTDC MspDeInit.
+
+ By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit
+ or HAL_LTDC_Init function.
+
+ When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
@@ -80,29 +129,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -110,17 +143,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#ifdef HAL_LTDC_MODULE_ENABLED
+#if defined (LTDC)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
-#ifdef HAL_LTDC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -135,8 +168,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
*/
/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -150,18 +183,17 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
*/
/**
- * @brief Initializes the LTDC according to the specified
- * parameters in the LTDC_InitTypeDef and create the associated handle.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
- uint32_t tmp = 0, tmp1 = 0;
+ uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
- if(hltdc == NULL)
+ if (hltdc == NULL)
{
return HAL_ERROR;
}
@@ -181,53 +213,70 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
- if(hltdc->State == HAL_LTDC_STATE_RESET)
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hltdc->Lock = HAL_UNLOCKED;
+
+ /* Reset the LTDC callback to the legacy weak callbacks */
+ hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
+ hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
+ hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hltdc->MspInitCallback == NULL)
+ {
+ hltdc->MspInitCallback = HAL_LTDC_MspInit;
+ }
+ /* Init the low level hardware */
+ hltdc->MspInitCallback(hltdc);
+ }
+#else
+ if (hltdc->State == HAL_LTDC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Configures the HS, VS, DE and PC polarity */
+ /* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
- hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
- hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+ hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+ hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
- /* Sets Synchronization size */
+ /* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
- tmp = (hltdc->Init.HorizontalSync << 16);
+ tmp = (hltdc->Init.HorizontalSync << 16U);
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
- /* Sets Accumulated Back porch */
+ /* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
- tmp = (hltdc->Init.AccumulatedHBP << 16);
+ tmp = (hltdc->Init.AccumulatedHBP << 16U);
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
- /* Sets Accumulated Active Width */
+ /* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
- tmp = (hltdc->Init.AccumulatedActiveW << 16);
+ tmp = (hltdc->Init.AccumulatedActiveW << 16U);
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
- /* Sets Total Width */
+ /* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
- tmp = (hltdc->Init.TotalWidth << 16);
+ tmp = (hltdc->Init.TotalWidth << 16U);
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
- /* Sets the background color value */
- tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);
- tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
+ /* Set the background color value */
+ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
+ tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
- /* Enable the transfer Error interrupt */
- __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);
-
- /* Enable the FIFO underrun interrupt */
- __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);
+ /* Enable the Transfer Error and FIFO underrun interrupts */
+ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
@@ -242,17 +291,25 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
}
/**
- * @brief Deinitializes the LTDC peripheral registers to their default reset
- * values.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief De-initialize the LTDC peripheral.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
{
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ if (hltdc->MspDeInitCallback == NULL)
+ {
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hltdc->MspDeInitCallback(hltdc);
+#else
/* DeInit the low level hardware */
HAL_LTDC_MspDeInit(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
@@ -267,44 +324,226 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
}
/**
- * @brief Initializes the LTDC MSP.
+ * @brief Initialize the LTDC MSP.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes the LTDC MSP.
+ * @brief De-initialize the LTDC MSP.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User LTDC Callback
+ * To be used instead of the weak predefined callback
+ * @param hltdc ltdc handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+ * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+ * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ if (hltdc->State == HAL_LTDC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_LINE_EVENT_CB_ID :
+ hltdc->LineEventCallback = pCallback;
+ break;
+
+ case HAL_LTDC_RELOAD_EVENT_CB_ID :
+ hltdc->ReloadEventCallback = pCallback;
+ break;
+
+ case HAL_LTDC_ERROR_CB_ID :
+ hltdc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hltdc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an LTDC Callback
+ * LTDC callabck is redirected to the weak predefined callback
+ * @param hltdc ltdc handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+ * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+ * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ if (hltdc->State == HAL_LTDC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_LINE_EVENT_CB_ID :
+ hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_LTDC_RELOAD_EVENT_CB_ID :
+ hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
+ break;
+
+ case HAL_LTDC_ERROR_CB_ID :
+ hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hltdc);
+
+ return status;
+}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -316,108 +555,126 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
* @{
*/
/**
- * @brief Handles LTDC interrupt request.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Handle LTDC interrupt request.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
+ uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
+ uint32_t itsources = READ_REG(hltdc->Instance->IER);
+
/* Transfer Error Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
+ if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
{
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
- {
- /* Disable the transfer Error interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
+ /* Disable the transfer Error interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
- /* Clear the transfer error flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
+ /* Clear the transfer error flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
- /* Update error code */
- hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
+ /* Update error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_ERROR;
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
- /* Transfer error Callback */
- HAL_LTDC_ErrorCallback(hltdc);
- }
+ /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hltdc->ErrorCallback(hltdc);
+#else
+ /* Call legacy error callback*/
+ HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
+
/* FIFO underrun Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
+ if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
{
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
- {
- /* Disable the FIFO underrun interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+ /* Disable the FIFO underrun interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
- /* Clear the FIFO underrun flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+ /* Clear the FIFO underrun flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
- /* Update error code */
- hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+ /* Update error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_ERROR;
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
- /* Transfer error Callback */
- HAL_LTDC_ErrorCallback(hltdc);
- }
+ /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hltdc->ErrorCallback(hltdc);
+#else
+ /* Call legacy error callback*/
+ HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
+
/* Line Interrupt management ************************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
+ if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
{
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
- {
- /* Disable the Line interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
-
- /* Clear the Line interrupt flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Line interrupt Callback */
- HAL_LTDC_LineEventCallback(hltdc);
- }
+ /* Disable the Line interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+ /* Clear the Line interrupt flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Line interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered Line Event callback */
+ hltdc->LineEventCallback(hltdc);
+#else
+ /*Call Legacy Line Event callback */
+ HAL_LTDC_LineEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
+
/* Register reload Interrupt management ***************************************/
- if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)
+ if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
{
- if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)
- {
- /* Disable the register reload interrupt */
- __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
-
- /* Clear the register reload flag */
- __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
-
- /* Change LTDC state */
- hltdc->State = HAL_LTDC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hltdc);
-
- /* Register reload interrupt Callback */
- HAL_LTDC_ReloadEventCallback(hltdc);
- }
+ /* Disable the register reload interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
+
+ /* Clear the register reload flag */
+ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
+
+ /* Change LTDC state */
+ hltdc->State = HAL_LTDC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hltdc);
+
+ /* Reload interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered reload Event callback */
+ hltdc->ReloadEventCallback(hltdc);
+#else
+ /*Call Legacy Reload Event callback */
+ HAL_LTDC_ReloadEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
/**
* @brief Error LTDC callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -426,14 +683,14 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Line Event callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -442,14 +699,14 @@ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
/**
* @brief Reload Event callback.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -458,7 +715,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
@@ -468,8 +725,8 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
*/
/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -494,43 +751,44 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
/**
* @brief Configure the LTDC Layer according to the specified
* parameters in the LTDC_InitTypeDef and create the associated handle.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
- assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
- assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Initialize the LTDC state*/
@@ -544,30 +802,30 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT
/**
* @brief Configure the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param RGBValue the color key value
+ * @param RGBValue the color key value
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Configures the default color values */
+ /* Configure the default color values */
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -581,20 +839,22 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t
/**
* @brief Load the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pCLUT pointer to the color lookup table address.
- * @param CLUTSize the color lookup table size.
+ * @param pCLUT pointer to the color lookup table address.
+ * @param CLUTSize the color lookup table size.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
{
- uint32_t tmp = 0;
- uint32_t counter = 0;
- uint32_t pcounter = 0;
+ uint32_t tmp;
+ uint32_t counter;
+ uint32_t *pcolorlut = pCLUT;
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -602,21 +862,18 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- for(counter = 0; (counter < CLUTSize); counter++)
+ for (counter = 0U; (counter < CLUTSize); counter++)
{
- if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+ if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
{
- tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+ tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
else
{
- tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+ tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
- pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
- pCLUT = (uint32_t *)pcounter;
+
+ pcolorlut++;
/* Specifies the C-LUT address and RGB value */
LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
@@ -633,28 +890,28 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT
/**
* @brief Enable the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -668,28 +925,28 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t
/**
* @brief Disable the color keying.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -703,15 +960,17 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_
/**
* @brief Enable the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -719,13 +978,10 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Disable LTDC color lookup table by setting CLUTEN bit */
+ /* Enable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -739,15 +995,17 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI
/**
* @brief Disable the color lookup table.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -755,13 +1013,10 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -774,8 +1029,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer
}
/**
- * @brief Enables Dither.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Enable Dither.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -801,8 +1056,8 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
}
/**
- * @brief Disables Dither.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Disable Dither.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -829,19 +1084,24 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
/**
* @brief Set the LTDC window size.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param XSize LTDC Pixel per line
- * @param YSize LTDC Line number
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters (Layers parameters)*/
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(XSize));
+ assert_param(IS_LTDC_CFBLNBR(YSize));
+
/* Process locked */
__HAL_LOCK(hltdc);
@@ -851,21 +1111,10 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
- /* Check the parameters (Layers parameters)*/
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
- assert_param(IS_LTDC_CFBLL(XSize));
- assert_param(IS_LTDC_CFBLNBR(YSize));
-
- /* update horizontal start/stop */
- pLayerCfg->WindowX0 = 0;
+ /* update horizontal stop */
pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
- /* update vertical start/stop */
- pLayerCfg->WindowY0 = 0;
+ /* update vertical stop */
pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
/* Reconfigures the color frame buffer pitch in byte */
@@ -877,7 +1126,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -891,19 +1140,24 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi
/**
* @brief Set the LTDC window position.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param X0 LTDC window X offset
- * @param Y0 LTDC window Y offset
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(X0));
+ assert_param(IS_LTDC_CFBLNBR(Y0));
+
/* Process locked */
__HAL_LOCK(hltdc);
@@ -913,13 +1167,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
-
/* update horizontal start/stop */
pLayerCfg->WindowX0 = X0;
pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
@@ -931,7 +1178,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -945,28 +1192,28 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
/**
* @brief Reconfigure the pixel format.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Pixelformat new pixel format value.
- * @param LayerIdx LTDC Layer index.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1.
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -976,7 +1223,7 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -990,28 +1237,28 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi
/**
* @brief Reconfigure the layer alpha value.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Alpha new alpha value.
+ * @param Alpha new alpha value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_ALPHA(Alpha));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_ALPHA(Alpha));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -1021,7 +1268,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -1034,27 +1281,27 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u
}
/**
* @brief Reconfigure the frame buffer Address.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Address new address value.
- * @param LayerIdx LTDC Layer index.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1.
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -1064,7 +1311,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Sets the Reload type */
+ /* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -1081,19 +1328,22 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
* larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
* want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
* will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
- uint32_t tmp = 0;
- uint32_t pitchUpdate = 0;
- uint32_t pixelFormat = 0;
+ uint32_t tmp;
+ uint32_t pitchUpdate;
+ uint32_t pixelFormat;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1101,44 +1351,41 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
- tmp = 4;
+ tmp = 4U;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
- tmp = 3;
+ tmp = 3U;
}
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
- tmp = 2;
+ tmp = 2U;
}
else
{
- tmp = 1;
+ tmp = 1U;
}
- pitchUpdate = ((LinePitchInPixels * tmp) << 16);
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
- /* Sets the Reload type as immediate update of LTDC pitch configured above */
+ /* Set the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
- /* Sets the Reload type as immediate update of LTDC pitch configured above */
+ /* Set the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Change the LTDC state*/
@@ -1152,28 +1399,32 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc
/**
* @brief Define the position of the line interrupt.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param Line Line Interrupt Position.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param Line Line Interrupt Position.
+ * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LIPOS(Line));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LIPOS(Line));
+ /* Disable the Line interrupt */
+ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+ /* Set the Line Interrupt position */
+ LTDC->LIPCR = (uint32_t)Line;
/* Enable the Line interrupt */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
- /* Sets the Line Interrupt position */
- LTDC->LIPCR = (uint32_t)Line;
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1184,17 +1435,19 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
}
/**
- * @brief LTDC configuration reload.
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param ReloadType This parameter can be one of the following values :
- * LTDC_RELOAD_IMMEDIATE : Immediate Reload
- * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
+ * @brief Reload LTDC Layers configuration.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param ReloadType This parameter can be one of the following values :
+ * LTDC_RELOAD_IMMEDIATE : Immediate Reload
+ * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
+ * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
{
- assert_param(IS_LTDC_RELAOD(ReloadType));
+ /* Check the parameters */
+ assert_param(IS_LTDC_RELOAD(ReloadType));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1220,45 +1473,44 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp
/**
* @brief Configure the LTDC Layer according to the specified without reloading
* parameters in the LTDC_InitTypeDef and create the associated handle.
- * Variant of the function HAL_LTDC_ConfigLayer without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
- * @param LayerIdx LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
- /* Process locked */
- __HAL_LOCK(hltdc);
-
- /* Change LTDC peripheral state */
- hltdc->State = HAL_LTDC_STATE_BUSY;
-
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
- assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
- assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+ assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+ assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+ assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ /* Change LTDC peripheral state */
+ hltdc->State = HAL_LTDC_STATE_BUSY;
+
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1270,20 +1522,25 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_
/**
* @brief Set the LTDC window size without reloading.
- * Variant of the function HAL_LTDC_SetWindowSize without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param XSize LTDC Pixel per line
- * @param YSize LTDC Line number
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters (Layers parameters)*/
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(XSize));
+ assert_param(IS_LTDC_CFBLNBR(YSize));
+
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1293,21 +1550,10 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
- /* Check the parameters (Layers parameters)*/
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
- assert_param(IS_LTDC_CFBLL(XSize));
- assert_param(IS_LTDC_CFBLNBR(YSize));
-
- /* update horizontal start/stop */
- pLayerCfg->WindowX0 = 0;
+ /* update horizontal stop */
pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
- /* update vertical start/stop */
- pLayerCfg->WindowY0 = 0;
+ /* update vertical stop */
pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
/* Reconfigures the color frame buffer pitch in byte */
@@ -1319,8 +1565,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1332,20 +1576,25 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
/**
* @brief Set the LTDC window position without reloading.
- * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param X0 LTDC window X offset
- * @param Y0 LTDC window Y offset
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+ assert_param(IS_LTDC_CFBLL(X0));
+ assert_param(IS_LTDC_CFBLNBR(Y0));
+
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1355,13 +1604,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc,
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
- assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
- assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
- assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
-
/* update horizontal start/stop */
pLayerCfg->WindowX0 = X0;
pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
@@ -1373,8 +1615,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc,
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1386,29 +1626,29 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc,
/**
* @brief Reconfigure the pixel format without reloading.
- * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
+ * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
* the configuration information for the LTDC.
- * @param Pixelformat new pixel format value.
- * @param LayerIdx LTDC Layer index.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1.
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
- assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -1418,8 +1658,6 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1431,29 +1669,29 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui
/**
* @brief Reconfigure the layer alpha value without reloading.
- * Variant of the function HAL_LTDC_SetAlpha without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_SetAlpha without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Alpha new alpha value.
+ * @param Alpha new alpha value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_ALPHA(Alpha));
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_ALPHA(Alpha));
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -1463,8 +1701,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1476,28 +1712,28 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/**
* @brief Reconfigure the frame buffer Address without reloading.
- * Variant of the function HAL_LTDC_SetAddress without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_SetAddress without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Address new address value.
- * @param LayerIdx LTDC Layer index.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1.
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
@@ -1507,8 +1743,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1523,20 +1757,23 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
* larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
* want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
* will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
- * Variant of the function HAL_LTDC_SetPitch without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
+ * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * Variant of the function HAL_LTDC_SetPitch without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
- uint32_t tmp = 0;
- uint32_t pitchUpdate = 0;
- uint32_t pixelFormat = 0;
+ uint32_t tmp;
+ uint32_t pitchUpdate;
+ uint32_t pixelFormat;
+
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1544,33 +1781,30 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
- tmp = 4;
+ tmp = 4U;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
- tmp = 3;
+ tmp = 3U;
}
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
- tmp = 2;
+ tmp = 2U;
}
else
{
- tmp = 1;
+ tmp = 1U;
}
- pitchUpdate = ((LinePitchInPixels * tmp) << 16);
+ pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
@@ -1578,8 +1812,6 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1592,32 +1824,30 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/**
* @brief Configure the color keying without reloading.
- * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param RGBValue the color key value
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
- /* Configures the default color values */
+ /* Configure the default color values */
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1629,30 +1859,28 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc,
/**
* @brief Enable the color keying without reloading.
- * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1664,30 +1892,28 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc,
/**
* @brief Disable the color keying without reloading.
- * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
+
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1699,16 +1925,18 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc
/**
* @brief Enable the color lookup table without reloading.
- * Variant of the function HAL_LTDC_EnableCLUT without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1716,14 +1944,9 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1735,16 +1958,18 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32
/**
* @brief Disable the color lookup table without reloading.
- * Variant of the function HAL_LTDC_DisableCLUT without immediate reload
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
- * 0 or 1
+ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
+ /* Check the parameters */
+ assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
@@ -1752,14 +1977,9 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- /* Check the parameters */
- assert_param(IS_LTDC_LAYER(LayerIdx));
-
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
- /* Do not Sets the Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1774,24 +1994,24 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
*/
/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
- (+) Check the LTDC state.
- (+) Get error code.
+ (+) Check the LTDC handle state.
+ (+) Get the LTDC handle error code.
@endverbatim
* @{
*/
/**
- * @brief Return the LTDC state
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Return the LTDC handle state.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
@@ -1801,11 +2021,11 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
}
/**
-* @brief Return the LTDC error code
-* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * @brief Return the LTDC handle error code.
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
-* @retval LTDC Error Code
-*/
+ * @retval LTDC Error Code
+ */
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
{
return hltdc->ErrorCode;
@@ -1816,38 +2036,46 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
*/
/**
- * @brief Configures the LTDC peripheral
+ * @}
+ */
+
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the LTDC peripheral
* @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg Pointer LTDC Layer Configuration structure
* @param LayerIdx LTDC Layer index.
- * This parameter can be one of the following values: 0 or 1
+ * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
- uint32_t tmp = 0;
- uint32_t tmp1 = 0;
- uint32_t tmp2 = 0;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
- /* Configures the horizontal start and stop position */
- tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
+ /* Configure the horizontal start and stop position */
+ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
- /* Configures the vertical start and stop position */
- tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
+ /* Configure the vertical start and stop position */
+ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
- LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);
+ LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
- /* Configures the default color values */
- tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
- tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
- tmp2 = (pLayerCfg->Alpha0 << 24);
+ /* Configure the default color values */
+ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
+ tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
+ tmp2 = (pLayerCfg->Alpha0 << 24U);
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
@@ -1859,35 +2087,34 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
- /* Configures the color frame buffer start address */
+ /* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
- if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
- tmp = 4;
+ tmp = 4U;
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
- tmp = 3;
+ tmp = 3U;
}
- else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
- tmp = 2;
+ tmp = 2U;
}
else
{
- tmp = 1;
+ tmp = 1U;
}
- /* Configures the color frame buffer pitch in byte */
+ /* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3));
-
- /* Configures the frame buffer line number */
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
+ /* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
@@ -1899,15 +2126,17 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
* @}
*/
-#endif /* HAL_LTDC_MODULE_ENABLED */
/**
* @}
*/
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
/**
* @}
*/
+#endif /* LTDC */
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc_ex.c
index a8fc6d94041a281ae688e1f4352d424f648c56a8..79c6a24f732942a80d72a73f51469ebfacff87a3 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_ltdc_ex.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -39,12 +23,15 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+
+#if defined (LTDC) && defined (DSI)
+
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
-#ifdef HAL_LTDC_MODULE_ENABLED
+#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -58,8 +45,8 @@
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -70,18 +57,18 @@
@endverbatim
* @{
*/
-#if defined (STM32F769xx) || defined (STM32F779xx)
+
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
@@ -99,32 +86,32 @@ HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc,
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
- hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1;
- hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;
- hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;
- hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;
+ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
+ hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
+ hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
+ hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
- * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
- * the configuration information for the LTDC.
- * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
+ * the configuration information for the LTDC.
+ * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
- LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
- LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+ LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+ LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
@@ -138,7 +125,6 @@ HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef
return HAL_OK;
}
-#endif /*STM32F769xx | STM32F779xx */
/**
* @}
@@ -148,11 +134,14 @@ HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef
* @}
*/
-#endif /* HAL_LTCD_MODULE_ENABLED */
+#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
+
/**
* @}
*/
+#endif /* LTDC && DSI */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mdios.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mdios.c
index cee198181a789d90a827d92448384df434cd5ad1..58dc313050b3245ca932ffbf67fd0d848023399a 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mdios.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mdios.c
@@ -58,34 +58,69 @@
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
(GPIO, Clocks, NVIC configuration ...)
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks:
+ (+) WriteCpltCallback : Write Complete Callback.
+ (+) ReadCpltCallback : Read Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) WakeUpCallback : Wake UP Callback
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback : MspDeInit Callback.
+
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) WriteCpltCallback : Write Complete Callback.
+ (+) ReadCpltCallback : Read Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) WakeUpCallback : Wake UP Callback
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback : MspDeInit Callback.
+
+ By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit
+ or HAL_MDIOS_Init function.
+
+ When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -117,6 +152,9 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
@@ -167,8 +205,23 @@ HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+ MDIOS_InitCallbacksToDefault(hmdios);
+
+ if(hmdios->MspInitCallback == NULL)
+ {
+ hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+ }
+
/* Init the low level hardware */
+ hmdios->MspInitCallback(hmdios);
+
+#else
+ /* Init the low level hardware */
HAL_MDIOS_MspInit(hmdios);
+
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
/* Change the MDIOS state */
@@ -221,9 +274,22 @@ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
/* Disable the Peripheral */
__HAL_MDIOS_DISABLE(hmdios);
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+ if(hmdios->MspDeInitCallback == NULL)
+ {
+ hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hmdios->MspDeInitCallback(hmdios);
+
+#else
+
/* DeInit the low level hardware */
HAL_MDIOS_MspDeInit(hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_RESET;
@@ -263,6 +329,194 @@ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
the HAL_MDIOS_MspDeInit can be implemented in the user file
*/
}
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/**
+* @brief Register a User MDIOS Callback
+* To be used instead of the weak predefined callback
+* @param hmdios mdios handle
+* @param CallbackID ID of the callback to be registered
+* This parameter can be one of the following values:
+* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
+* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
+* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID
+* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
+* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
+* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
+* @param pCallback pointer to the Callback function
+* @retval status
+*/
+HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hmdios);
+
+ if(hmdios->State == HAL_MDIOS_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
+ hmdios->WriteCpltCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_READ_COMPLETE_CB_ID :
+ hmdios->ReadCpltCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_ERROR_CB_ID :
+ hmdios->ErrorCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_WAKEUP_CB_ID :
+ hmdios->WakeUpCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_MSPINIT_CB_ID :
+ hmdios->MspInitCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_MSPDEINIT_CB_ID :
+ hmdios->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hmdios->State == HAL_MDIOS_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDIOS_MSPINIT_CB_ID :
+ hmdios->MspInitCallback = pCallback;
+ break;
+
+ case HAL_MDIOS_MSPDEINIT_CB_ID :
+ hmdios->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmdios);
+
+ return status;
+}
+
+/**
+* @brief Unregister an MDIOS Callback
+* MDIOS callabck is redirected to the weak predefined callback
+* @param hmdios mdios handle
+* @param CallbackID ID of the callback to be unregistered
+* This parameter can be one of the following values:
+* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
+* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
+* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID
+* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
+* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
+* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
+* @retval status
+*/
+HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hmdios);
+
+ if(hmdios->State == HAL_MDIOS_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
+ hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback;
+ break;
+
+ case HAL_MDIOS_READ_COMPLETE_CB_ID :
+ hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback;
+ break;
+
+ case HAL_MDIOS_ERROR_CB_ID :
+ hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback;
+ break;
+
+ case HAL_MDIOS_WAKEUP_CB_ID :
+ hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback;
+ break;
+
+ case HAL_MDIOS_MSPINIT_CB_ID :
+ hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+ break;
+
+ case HAL_MDIOS_MSPDEINIT_CB_ID :
+ hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hmdios->State == HAL_MDIOS_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDIOS_MSPINIT_CB_ID :
+ hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+ break;
+
+ case HAL_MDIOS_MSPDEINIT_CB_ID :
+ hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmdios);
+
+ return status;
+}
+
+static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
+{
+ /* Init the MDIOS Callback settings */
+ hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; /* Legacy weak WriteCpltCallback */
+ hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; /* Legacy weak ReadCpltCallback */
+ hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; /* Legacy weak WakeUpCallback */
+}
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -456,8 +710,13 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
/* Write register flag */
if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)
{
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+ /* Call registered Write complete callback */
+ hmdios->WriteCpltCallback(hmdios);
+#else
/* Write callback function */
HAL_MDIOS_WriteCpltCallback(hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear write register flag */
HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
@@ -470,8 +729,13 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
/* Read register flag */
if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)
{
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+ /* Call registered Read complete callback */
+ hmdios->ReadCpltCallback(hmdios);
+#else
/* Read callback function */
HAL_MDIOS_ReadCpltCallback(hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear read register flag */
HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
@@ -484,8 +748,13 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
/* All Errors Flag */
if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)
{
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hmdios->ErrorCallback(hmdios);
+#else
/* Error Callback */
HAL_MDIOS_ErrorCallback(hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear errors flag */
__HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
@@ -495,8 +764,13 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET)
{
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+ /* Call registered WakeUp callback */
+ hmdios->WakeUpCallback(hmdios);
+#else
/* MDIOS WAKEUP interrupt user callback */
HAL_MDIOS_WakeUpCallback(hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG();
@@ -577,7 +851,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
[..]
This subsection provides a set of functions allowing to control the MDIOS.
(+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
- (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
+ (+) HAL_MDIOS_GetError() API, returns the errors occurred during data transfer.
@endverbatim
* @{
@@ -586,7 +860,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
/**
* @brief Gets MDIOS error flags
* @param hmdios mdios handle
- * @retval bit map of occured errors
+ * @retval bit map of occurred errors
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
{
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mmc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mmc.c
index 0a980df119da85c717c2cac02a0f0175a63b47e4..5d4fcdf60a139624f09c07b6b2232365aebedb9a 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mmc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_mmc.c
@@ -186,33 +186,63 @@
[..]
(@) You can refer to the MMC HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
+ and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL__RegisterCallback before calling @ref HAL_MMC_DeInit
+ or @ref HAL_MMC_Init function.
+
+ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -310,8 +340,24 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+
+ if(hmmc->MspInitCallback == NULL)
+ {
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hmmc->MspInitCallback(hmmc);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
+#endif
}
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -408,8 +454,18 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
/* Set MMC power state to off */
MMC_PowerOFF(hmmc);
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ if(hmmc->MspDeInitCallback == NULL)
+ {
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hmmc->MspDeInitCallback(hmmc);
+#else
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
+#endif
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
@@ -1379,7 +1435,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
@@ -1389,11 +1449,19 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
hmmc->State = HAL_MMC_STATE_READY;
if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->RxCpltCallback(hmmc);
+#else
HAL_MMC_RxCpltCallback(hmmc);
+#endif
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->TxCpltCallback(hmmc);
+#else
HAL_MMC_TxCpltCallback(hmmc);
+#endif
}
}
else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
@@ -1404,7 +1472,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
@@ -1415,7 +1487,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->TxCpltCallback(hmmc);
+#else
HAL_MMC_TxCpltCallback(hmmc);
+#endif
}
}
}
@@ -1488,14 +1564,22 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
}
else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
}
@@ -1547,7 +1631,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
+ the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
}
@@ -1581,6 +1665,180 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
*/
}
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User MMC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackID : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = pCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+
+/**
+ * @brief Unregister a User MMC Callback
+ * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackID : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+#endif
+
/**
* @}
@@ -2129,7 +2387,11 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
@@ -2142,7 +2404,11 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->RxCpltCallback(hmmc);
+#else
HAL_MMC_RxCpltCallback(hmmc);
+#endif
}
/**
@@ -2177,8 +2443,13 @@ static void MMC_DMAError(DMA_HandleTypeDef *hdma)
hmmc->State= HAL_MMC_STATE_READY;
}
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
+
}
/**
@@ -2212,7 +2483,11 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
}
@@ -2249,7 +2524,11 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
}
@@ -2485,7 +2764,7 @@ static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
* @}
*/
-#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_msp_template.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_msp_template.c
index 3bd3746c11588d67717e5755ce846b529d932eb5..c2949c052c6d75609904c714acb702bbb8a45c57 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_msp_template.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_msp_template.c
@@ -16,29 +16,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nand.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nand.c
index f40975eeda50627dc6f52f2777786509719eff69..d3c8ae320cd76df7cac63a7ef41dee70074e60ee 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nand.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nand.c
@@ -52,33 +52,56 @@
If a NAND flash device contains different operations and/or implementations,
it should be implemented separately.
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
+ and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
+ or @ref HAL_NAND_Init function.
+
+ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -144,8 +167,20 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if(hnand->MspInitCallback == NULL)
+ {
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ }
+ hnand->ItCallback = HAL_NAND_ITCallback;
+
+ /* Init the low level hardware */
+ hnand->MspInitCallback(hnand);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
+#endif
}
/* Initialize NAND control Interface */
@@ -174,8 +209,18 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if(hnand->MspDeInitCallback == NULL)
+ {
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnand->MspDeInitCallback(hnand);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
+#endif
/* Configure the NAND registers with their reset values */
FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
@@ -234,7 +279,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
@@ -244,7 +293,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
@@ -254,7 +307,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
@@ -264,7 +321,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
@@ -1670,6 +1731,143 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
return (status);
}
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NAND Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if(hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NAND Callback
+ * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if(hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nor.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nor.c
index 751c2cffebe098b3e8fae9c54817c6f62cfbba9a..1483f3bfff3e430db02a8d90f6972b819a3c4724 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nor.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_nor.c
@@ -49,33 +49,56 @@
(+) NOR_WRITE : NOR memory write data to specified address
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
+ and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
+ or @ref HAL_NOR_Init function.
+
+ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -186,8 +209,19 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
{
/* Allocate lock resource and initialize it */
hnor->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if(hnor->MspInitCallback == NULL)
+ {
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hnor->MspInitCallback(hnor);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
}
/* Initialize NOR control Interface */
@@ -226,8 +260,18 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if(hnor->MspDeInitCallback == NULL)
+ {
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnor->MspDeInitCallback(hnor);
+#else
/* De-Initialize the low level hardware (MSP) */
HAL_NOR_MspDeInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/* Configure the NOR registers with their reset values */
FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
@@ -859,6 +903,105 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
return HAL_OK;
}
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NOR Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NOR Callback
+ * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd.c
index b9f0df14c35e25e0c2fcd9ce726bb721212cd8ef..c089e7e52d9796193d685285dfcdae485336cf8a 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd.c
@@ -43,29 +43,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -77,24 +61,18 @@
* @{
*/
-/** @defgroup PCD
+/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/**
- * USB_OTG_CORE VERSION ID
- */
-#define USB_OTG_CORE_ID_300A 0x4F54300AU
-#define USB_OTG_CORE_ID_310A 0x4F54310AU
-#define USB_OTG_CORE_ID_320A 0x4F54320AU
-#endif /* USB_OTG_FS || USB_OTG_HS */
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
@@ -111,7 +89,9 @@
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-#endif /* USB_OTG_FS || USB_OTG_HS */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
@@ -145,7 +125,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
uint8_t i;
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
@@ -153,13 +133,35 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
- if(hpcd->State == HAL_PCD_STATE_RESET)
+ if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+
+ if (hpcd->MspInitCallback == NULL)
+ {
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hpcd->MspInitCallback(hpcd);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
@@ -168,13 +170,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
__HAL_PCD_DISABLE(hpcd);
/*Init the Core (common init.) */
- (void)USB_CoreInit(hpcd->Instance, hpcd->Init);
+ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Force Device Mode*/
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
/* Init endpoints structures */
- for (i = 0U; i < 15U; i++)
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
@@ -187,7 +193,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[i].xfer_len = 0U;
}
- for (i = 0U; i < 15U; i++)
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
@@ -199,7 +205,11 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
}
/* Init Device */
- (void)USB_DevInit(hpcd->Instance, hpcd->Init);
+ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
@@ -210,7 +220,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
- (void)USB_DevDisconnect (hpcd->Instance);
+ (void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
}
@@ -223,7 +233,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
@@ -233,8 +243,18 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
/* Stop Device */
(void)HAL_PCD_Stop(hpcd);
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ if (hpcd->MspDeInitCallback == NULL)
+ {
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
/* DeInit the low level hardware */
+ hpcd->MspDeInitCallback(hpcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
hpcd->State = HAL_PCD_STATE_RESET;
@@ -271,11 +291,599 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
*/
}
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB PCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = pCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = pCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB PCD Callback
+ * USB PCD callabck is redirected to the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data OUT Stage Callback
+ * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data OUT Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data IN Stage Callback
+ * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data IN Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data IN Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso OUT incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso OUT incomplete Callback
+ * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso IN incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso IN incomplete Callback
+ * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD LPM Callback
+ * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD LPM Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD LPM Callback
+ * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
@@ -298,7 +906,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
- (void)USB_DevConnect (hpcd->Instance);
+ (void)USB_DevConnect(hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -313,9 +921,16 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
- (void)USB_StopDevice(hpcd->Instance);
+
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ {
+ __HAL_UNLOCK(hpcd);
+ return HAL_ERROR;
+ }
+
(void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
@@ -328,29 +943,26 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t TempReg = USBx_BASE + 0x40U;
- uint32_t gSNPSiD = *(uint32_t *) TempReg;
uint32_t i, ep_intr, epint, epnum = 0U;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
- uint32_t hclk;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
- if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
@@ -366,97 +978,43 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
- if (gSNPSiD > USB_OTG_CORE_ID_300A)
- {
- /* setup/out transaction management for Core ID >= 310A */
- if (hpcd->Init.dma_enable == 1U)
- {
- if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
- {
- CLEAR_OUT_EP_INTR(epnum, (1U << 15));
- }
- }
- }
-
- if(hpcd->Init.dma_enable == 1U)
- {
- hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
- hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
- }
-
- if (gSNPSiD == USB_OTG_CORE_ID_310A)
- {
- if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
- {
- CLEAR_OUT_EP_INTR(epnum, (1U << 15));
- }
- else
- {
- HAL_PCD_DataOutStageCallback(hpcd, epnum);
- }
- }
- else
- {
- HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
- }
-
- if(hpcd->Init.dma_enable == 1U)
- {
- if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
- {
- /* this is ZLP, so prepare EP0 for next setup */
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- }
- }
+ (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
- if (gSNPSiD == USB_OTG_CORE_ID_310A)
- {
- if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
- {
- CLEAR_OUT_EP_INTR(epnum, (1U << 15));
- }
- }
-
- if (gSNPSiD > USB_OTG_CORE_ID_300A)
- {
- /* setup/out transaction management for Core ID >= 310A */
- if (hpcd->Init.dma_enable == 1U)
- {
- if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
- {
- CLEAR_OUT_EP_INTR(epnum, (1U << 15));
- }
- }
- }
-
- /* Inform the upper layer that a setup packet is available */
- HAL_PCD_SetupStageCallback(hpcd);
+ /* Class B setup phase done for previous decoded setup */
+ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
- if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+ if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
-#ifdef USB_OTG_DOEPINT_OTEPSPR
/* Clear Status Phase Received interrupt */
- if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
+
+ /* Clear OUT NAK interrupt */
+ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+ }
}
epnum++;
ep_intr >>= 1U;
}
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
@@ -471,7 +1029,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
- fifoemptymsk = (uint32_t)(0x1UL << (epnum & 0xFU));
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@@ -481,7 +1039,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
}
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if (hpcd->Init.dma_enable == 1U)
{
@@ -520,53 +1082,75 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/* Handle Resume Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
- if(hpcd->LPM_State == LPM_L1)
+ if (hpcd->LPM_State == LPM_L1)
{
hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResumeCallback(hpcd);
+#else
HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
-
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
/* Handle LPM Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
- if( hpcd->LPM_State == LPM_L0)
+
+ if (hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Handle Reset Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
@@ -582,121 +1166,67 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (hpcd->Init.use_dedicated_ep1 != 0U)
{
- USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM;
+
+ USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
}
else
{
-#ifdef USB_OTG_DOEPINT_OTEPSPR
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
-#else
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
- USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM |
+ USB_OTG_DOEPMSK_OTEPSPRM |
+ USB_OTG_DOEPMSK_NAKM;
+
+ USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
/* setup EP0 to receive SETUP packets */
- (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+ (uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
/* Handle Enumeration done Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
- hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
- if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
+ if (USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
{
- hpcd->Init.speed = USB_OTG_SPEED_HIGH;
- hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
+ hpcd->Init.speed = USB_OTG_SPEED_HIGH;
}
else
{
- hpcd->Init.speed = USB_OTG_SPEED_FULL;
- hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE;
-
- /* The USBTRD is configured according to the tables below, depending on AHB frequency
- used by application. In the low AHB frequency range it is used to stretch enough the USB response
- time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
- latency to the Data FIFO */
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- if((hclk >= 14200000U) && (hclk < 15000000U))
- {
- /* hclk Clock Range between 14.2-15 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 15000000U) && (hclk < 16000000U))
- {
- /* hclk Clock Range between 15-16 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 16000000U) && (hclk < 17200000U))
- {
- /* hclk Clock Range between 16-17.2 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 17200000U) && (hclk < 18500000U))
- {
- /* hclk Clock Range between 17.2-18.5 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 18500000U) && (hclk < 20000000U))
- {
- /* hclk Clock Range between 18.5-20 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 20000000U) && (hclk < 21800000U))
- {
- /* hclk Clock Range between 20-21.8 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 21800000U) && (hclk < 24000000U))
- {
- /* hclk Clock Range between 21.8-24 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 24000000U) && (hclk < 27700000U))
- {
- /* hclk Clock Range between 24-27.7 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 27700000U) && (hclk < 32000000U))
- {
- /* hclk Clock Range between 27.7-32 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else /* if(hclk >= 32000000) */
- {
- /* hclk Clock Range between 32-200 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT);
- }
+ hpcd->Init.speed = USB_OTG_SPEED_FULL;
}
+ /* Set USB Turnaround time */
+ (void)USB_SetTurnaroundTime(hpcd->Instance,
+ HAL_RCC_GetHCLKFreq(),
+ (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResetCallback(hpcd);
+#else
HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle RxQLevel Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@@ -704,11 +1234,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
- if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
- if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
- (void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+ (void)USB_ReadPacket(USBx, ep->xfer_buff,
+ (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
@@ -720,53 +1252,77 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
else
{
- /* ... */
+ /* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle SOF Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback(hpcd);
+#else
HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Incomplete ISO IN Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
/* Handle Incomplete ISO OUT Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
/* Handle Connection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ConnectCallback(hpcd);
+#else
HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
}
/* Handle Disconnection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
temp = hpcd->Instance->GOTGINT;
- if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DisconnectCallback(hpcd);
+#else
HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= temp;
}
}
}
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
@@ -1015,16 +1571,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0xFU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0xFU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->type = ep_type;
@@ -1058,18 +1614,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0xFU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0xFU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
- (void)USB_DeactivateEndpoint(hpcd->Instance , ep);
+ (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1087,21 +1643,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
PCD_EPTypeDef *ep;
- ep = &hpcd->OUT_ep[ep_addr & 0xFU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
- if ((ep_addr & 0xFU) == 0U)
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
@@ -1119,9 +1675,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- return (uint16_t)hpcd->OUT_ep[ep_addr & 0xFU].xfer_count;
+ return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
/**
* @brief Send an amount of data
@@ -1135,21 +1691,21 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
{
PCD_EPTypeDef *ep;
- ep = &hpcd->IN_ep[ep_addr & 0xFU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
- if ((ep_addr & 0xFU) == 0U)
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
@@ -1171,14 +1727,14 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
- if (((uint32_t)ep_addr & 0xFU) > hpcd->Init.dev_endpoints)
+ if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
{
return HAL_ERROR;
}
if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0xFU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
@@ -1188,12 +1744,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
ep->is_stall = 1U;
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
- if((ep_addr & 0xFU) == 0U)
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
@@ -1219,17 +1775,17 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0xFU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr &0xFU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->is_stall = 0U;
- ep->num = ep_addr & 0xFU;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPClearStall(hpcd->Instance, ep);
@@ -1250,7 +1806,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
if ((ep_addr & 0x80U) == 0x80U)
{
- (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & 0xFU);
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
}
else
{
@@ -1269,7 +1825,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- return(USB_ActivateRemoteWakeup(hpcd->Instance));
+ return (USB_ActivateRemoteWakeup(hpcd->Instance));
}
/**
@@ -1279,7 +1835,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- return(USB_DeActivateRemoteWakeup(hpcd->Instance));
+ return (USB_DeActivateRemoteWakeup(hpcd->Instance));
}
/**
@@ -1340,6 +1896,12 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
+
+ if (ep->xfer_count > ep->xfer_len)
+ {
+ return HAL_ERROR;
+ }
+
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
@@ -1349,8 +1911,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
len32b = (len + 3U) / 4U;
- while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&
- (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
+ while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+ (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
@@ -1361,27 +1923,185 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
}
len32b = (len + 3U) / 4U;
- (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable);
+ (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+ (uint8_t)hpcd->Init.dma_enable);
ep->xfer_buff += len;
ep->xfer_count += len;
}
- if(len <= 0U)
+ if (ep->xfer_len <= ep->xfer_count)
{
- fifoemptymsk = (uint32_t)(0x1UL << epnum);
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
}
return HAL_OK;
}
-#endif /* USB_OTG_FS || USB_OTG_HS */
/**
- * @}
+ * @brief process EP OUT transfer complete interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
*/
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+
+ /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+ }
+ else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+ else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ /* out data packet received over EP0 */
+ hpcd->OUT_ep[epnum].xfer_count =
+ hpcd->OUT_ep[epnum].maxpacket -
+ (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ }
+ }
+ else
+ {
+ /* ... */
+ }
+ }
+ else
+ {
+ if (gSNPSiD == USB_OTG_CORE_ID_310A)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief process EP OUT setup packet received interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ /* StupPktRcvd = 1 pending setup packet int */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ }
+ else
+ {
+ if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ }
+
+ /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+
+ return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd_ex.c
index cee1bb058317e420683986735291615d919bf538..168d963959303ea03452ed3c531393e26dca840b 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pcd_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -51,6 +35,7 @@
#ifdef HAL_PCD_MODULE_ENABLED
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -100,7 +85,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
Tx_Offset = hpcd->Instance->GRXFSIZ;
- if(fifo == 0U)
+ if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
@@ -164,8 +149,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
return HAL_OK;
}
-#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Send LPM message to user layer callback.
@@ -208,7 +193,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
/**
* @}
*/
-
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr.c
index 71cd61d8732203c73304f9b6ae13c8d6c6f8e76e..70849df009fc51e7026a006055518d7c1ba2d1d5 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr.c
@@ -11,29 +11,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr_ex.c
index b2d576d1b1b73ad8029f9a6790f19d70a22df835..ce546b48c89c78bea3a2934a4321c4065284d9d6 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_pwr_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_qspi.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_qspi.c
index 1af847cc70c84e59f7bfa23cf3f49705d1e72678..5947f4c4d5473a5b1863c02c09bd1bec40a8d4ab 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_qspi.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_qspi.c
@@ -126,6 +126,65 @@
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : QSPI MspInit.
+ (+) MspDeInitCallback : QSPI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : QSPI MspInit.
+ (+) MspDeInitCallback : QSPI MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
+ and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
+ or @ref HAL_QSPI_Init function.
+
+ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
*** Workarounds linked to Silicon Limitation ***
====================================================
[..]
@@ -136,29 +195,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -280,8 +323,30 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
+ hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+ hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+ hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+ hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+ hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+ hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+ hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+ hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+ hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+ hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+
+ if(hqspi->MspInitCallback == NULL)
+ {
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hqspi->MspInitCallback(hqspi);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
+#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
@@ -339,8 +404,18 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ if(hqspi->MspDeInitCallback == NULL)
+ {
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hqspi->MspDeInitCallback(hqspi);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_QSPI_MspDeInit(hqspi);
+#endif
/* Set QSPI error code to none */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
@@ -466,7 +541,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* FIFO Threshold callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->FifoThresholdCallback(hqspi);
+#else
HAL_QSPI_FifoThresholdCallback(hqspi);
+#endif
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
@@ -499,7 +578,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* TX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TxCpltCallback(hqspi);
+#else
HAL_QSPI_TxCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
@@ -538,7 +621,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* RX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->RxCpltCallback(hqspi);
+#else
HAL_QSPI_RxCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY)
{
@@ -546,7 +633,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* Command Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->CmdCpltCallback(hqspi);
+#else
HAL_QSPI_CmdCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_ABORT)
{
@@ -558,14 +649,22 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Abort called by the user */
/* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
}
else
{
/* Abort due to an error (eg : DMA error) */
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
}
@@ -587,7 +686,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* Status match callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->StatusMatchCallback(hqspi);
+#else
HAL_QSPI_StatusMatchCallback(hqspi);
+#endif
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
@@ -609,7 +712,21 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Disable the DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_DMA_Abort_IT(hqspi->hdma);
+ if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
+ HAL_QSPI_ErrorCallback(hqspi);
+#endif
+ }
}
else
{
@@ -617,7 +734,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
@@ -628,7 +749,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
/* Time out callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TimeOutCallback(hqspi);
+#else
HAL_QSPI_TimeOutCallback(hqspi);
+#endif
}
}
@@ -1833,6 +1958,227 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
the HAL_QSPI_TimeOutCallback could be implemented in the user file
*/
}
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User QSPI Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hqspi : QSPI handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
+ * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
+ * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
+ * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
+ * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
+ * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_ERROR_CB_ID :
+ hqspi->ErrorCallback = pCallback;
+ break;
+ case HAL_QSPI_ABORT_CB_ID :
+ hqspi->AbortCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+ hqspi->FifoThresholdCallback = pCallback;
+ break;
+ case HAL_QSPI_CMD_CPLT_CB_ID :
+ hqspi->CmdCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_RX_CPLT_CB_ID :
+ hqspi->RxCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_TX_CPLT_CB_ID :
+ hqspi->TxCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+ hqspi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+ hqspi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_STATUS_MATCH_CB_ID :
+ hqspi->StatusMatchCallback = pCallback;
+ break;
+ case HAL_QSPI_TIMEOUT_CB_ID :
+ hqspi->TimeOutCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+ return status;
+}
+
+/**
+ * @brief Unregister a User QSPI Callback
+ * QSPI Callback is redirected to the weak (surcharged) predefined callback
+ * @param hqspi : QSPI handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
+ * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
+ * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
+ * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
+ * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
+ * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_ERROR_CB_ID :
+ hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+ break;
+ case HAL_QSPI_ABORT_CB_ID :
+ hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+ break;
+ case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+ hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+ break;
+ case HAL_QSPI_CMD_CPLT_CB_ID :
+ hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+ break;
+ case HAL_QSPI_RX_CPLT_CB_ID :
+ hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+ break;
+ case HAL_QSPI_TX_CPLT_CB_ID :
+ hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+ break;
+ case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+ hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+ break;
+ case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+ hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+ break;
+ case HAL_QSPI_STATUS_MATCH_CB_ID :
+ hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+ break;
+ case HAL_QSPI_TIMEOUT_CB_ID :
+ hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+ break;
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+ return status;
+}
+#endif
/**
* @}
@@ -1957,7 +2303,18 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
/* Abort DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_DMA_Abort_IT(hqspi->hdma);
+ if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
+ HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+ }
}
else
{
@@ -2070,7 +2427,11 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->RxHalfCpltCallback(hqspi);
+#else
HAL_QSPI_RxHalfCpltCallback(hqspi);
+#endif
}
/**
@@ -2082,7 +2443,11 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TxHalfCpltCallback(hqspi);
+#else
HAL_QSPI_TxHalfCpltCallback(hqspi);
+#endif
}
/**
@@ -2140,7 +2505,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
hqspi->State = HAL_QSPI_STATE_READY;
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc.c
index bde6077939bd675d2c520b263c95df617076e28a..c8290a82a6b60a2f4c90dfc103c7d533e39cf821 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc.c
@@ -54,29 +54,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc_ex.c
index 6b7a153e5645811f621c57fe81d6832b545ba5a6..ee0900391e70b514d94babd9e5c33e9154806212 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rcc_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rng.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rng.c
index ff25aed70e806c51f0150a02f749606033ffccb2..3e073e291dd36f31acdb6875e31199510bc3dc9c 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rng.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rng.c
@@ -5,7 +5,7 @@
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization/de-initialization functions
+ * + Initialization and configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -23,33 +23,71 @@
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
+ Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+
+ [..]
+ For specific callback ReadyDataCallback, use dedicated register callbacks:
+ respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+
+ [..]
+ By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ example @ref HAL_RNG_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
+ and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
+ or @ref HAL_RNG_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -61,7 +99,10 @@
* @{
*/
+#if defined (RNG)
+
/** @addtogroup RNG
+ * @brief RNG HAL module driver.
* @{
*/
@@ -71,7 +112,7 @@
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
+/** @defgroup RNG_Private_Constants RNG Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -88,11 +129,11 @@
*/
/** @addtogroup RNG_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and configuration functions
*
@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the RNG according to the specified parameters
@@ -114,28 +155,54 @@
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
- if(hrng == NULL)
+ if (hrng == NULL)
{
return HAL_ERROR;
}
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->State == HAL_RNG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hrng->MspInitCallback == NULL)
+ {
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ }
- if(hrng->State == HAL_RNG_STATE_RESET)
+ /* Init the low level hardware */
+ hrng->MspInitCallback(hrng);
+ }
+#else
+ if (hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
+
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
/* Return function status */
return HAL_OK;
}
@@ -149,22 +216,36 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
- if(hrng == NULL)
+ if (hrng == NULL)
{
return HAL_ERROR;
}
+
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->MspDeInitCallback == NULL)
+ {
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hrng->MspDeInitCallback(hrng);
+#else
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_RESET;
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
/* Release Lock */
__HAL_UNLOCK(hrng);
@@ -202,6 +283,233 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
*/
}
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RNG Callback
+ * To be used instead of the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Unregister an RNG Callback
+ * RNG callabck is redirected to the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Register Data Ready RNG Callback
+ * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @param pCallback pointer to the Data Ready Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Data Ready RNG Callback
+ * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -234,14 +542,14 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
+ if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@@ -250,16 +558,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
- while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_ERROR;
-
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -271,6 +578,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
}
else
{
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
@@ -294,14 +602,11 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
+ if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
}
@@ -310,12 +615,59 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
/* Process Unlocked */
__HAL_UNLOCK(hrng);
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
+/**
+ * @brief Returns generated random number in polling mode (Obsolete)
+ * Use HAL_RNG_GenerateRandomNumber() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval Random value
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ {
+ return hrng->RandomNumber;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+/**
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval 32-bit random number
+ */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ uint32_t random32bit = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get a 32bit Random number */
+ random32bit = hrng->Instance->DR;
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+
+ /* Return the 32 bit random number */
+ return random32bit;
+}
+
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
@@ -339,21 +691,45 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
+ uint32_t rngclockerror = 0U;
+
/* RNG clock error interrupt occurred */
- if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ rngclockerror = 1U;
+ }
+ else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+ rngclockerror = 1U;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (rngclockerror == 1U)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Clear the clock error flag */
- __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
}
/* Check RNG data ready interrupt occurred */
- if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -361,63 +737,24 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
- if(hrng->State != HAL_RNG_STATE_ERROR)
+ if (hrng->State != HAL_RNG_STATE_ERROR)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
-
- /* Data Ready callback */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Data Ready callback */
+ hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+ /* Call legacy weak Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
}
}
}
-/**
- * @brief Returns generated random number in polling mode (Obsolete)
- * Use HAL_RNG_GenerateRandomNumber() API instead.
- * @param hrng pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval Random value
- */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
- if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
- {
- return hrng->RandomNumber;
- }
- else
- {
- return 0U;
- }
-}
-
-/**
- * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
- * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
- * @param hrng pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval 32-bit random number
- */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
- uint32_t random32bit = 0U;
-
- /* Process locked */
- __HAL_LOCK(hrng);
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Get a 32bit Random number */
- random32bit = hrng->Instance->DR;
-
- /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
- __HAL_RNG_ENABLE_IT(hrng);
-
- /* Return the 32 bit random number */
- return random32bit;
-}
-
/**
* @brief Read latest generated random number.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
@@ -426,7 +763,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
*/
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
- return(hrng->RandomNumber);
+ return (hrng->RandomNumber);
}
/**
@@ -491,6 +828,16 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
return hrng->State;
}
+/**
+ * @brief Return the RNG handle error code.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval RNG Error Code
+*/
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+{
+ /* Return RNG Error Code */
+ return hrng->ErrorCode;
+}
/**
* @}
*/
@@ -499,12 +846,14 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
* @}
*/
-#endif /* HAL_RNG_MODULE_ENABLED */
+#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
*/
+#endif /* RNG */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc.c
index 4991ce1eee0fadbf3c0e97c86833545dea1c8b28..de5a34aad14bafd4f4e2efc785075c895dddd652 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc.c
@@ -92,44 +92,84 @@
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+ Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+
+ By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions :
+ examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+ Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+ in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+ or @ref HAL_RTC_Init() function.
+
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -153,7 +193,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
@@ -182,7 +222,7 @@
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
+ initialization, calendar update or after wake-up from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
@@ -216,13 +256,42 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
if(hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
+
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+
+ if(hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if(hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+ }
+#else
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
@@ -363,8 +432,19 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if(hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+
+#else
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
hrtc->State = HAL_RTC_STATE_RESET;
@@ -374,6 +454,214 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
return HAL_OK;
}
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RTC Callback
+ * To be used instead of the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if(HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an RTC Callback
+ * RTC callabck is redirected to the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if(HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ break;
+
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @brief Initializes the RTC MSP.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
@@ -473,8 +761,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sTime->Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
@@ -648,8 +935,8 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- assert_param(IS_RTC_MONTH(sDate->Month));
- assert_param(IS_RTC_DATE(sDate->Date));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
(((uint32_t)sDate->Month) << 8) | \
@@ -834,8 +1121,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
@@ -849,13 +1135,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
@@ -1022,8 +1306,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
@@ -1037,13 +1320,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
@@ -1146,7 +1427,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
/**
- * @brief Deactive the specified RTC Alarm
+ * @brief Deactivate the specified RTC Alarm
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm Specifies the Alarm.
@@ -1311,7 +1592,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
{
/* AlarmA callback */
+ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback(hrtc);
+ #else
HAL_RTC_AlarmAEventCallback(hrtc);
+ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
@@ -1324,7 +1609,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
{
/* AlarmB callback */
+ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmBEventCallback(hrtc);
+ #else
HAL_RTCEx_AlarmBEventCallback(hrtc);
+ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
@@ -1349,7 +1638,7 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
@@ -1414,7 +1703,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
+ * initialization, calendar update or after wake-up from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc_ex.c
index 1a0b84292bacde295208cc187944070ea413ad47..c98f0af74892384c575a7085c5b24d97e26c2707 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_rtc_ex.c
@@ -68,29 +68,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -114,7 +98,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
@@ -677,8 +661,12 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
{
- /* TIMESTAMP callback */
- HAL_RTCEx_TimeStampEventCallback(hrtc);
+ /* TIMESTAMP callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->TimeStampEventCallback(hrtc);
+#else
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the TIMESTAMP interrupt pending bit */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
@@ -693,7 +681,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
{
/* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper1EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
@@ -708,7 +700,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
{
/* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper2EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
@@ -723,7 +719,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
{
/* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper3EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
@@ -815,7 +815,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
tickstart = HAL_GetTick();
while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
- {
+ {
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
@@ -825,7 +825,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
}
}
}
-
+
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
/* Clear the TIMESTAMP OverRun Flag */
@@ -836,7 +836,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
return HAL_ERROR;
}
-
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1223,7 +1223,11 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
{
/* WAKEUPTIMER callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->WakeUpTimerEventCallback(hrtc);
+#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai.c
index 8c3ae101ab0d0959f47d12da8f50903ff72444af..3c2cddee7a053284664f41bfee133d08c06c9187 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai.c
@@ -130,33 +130,69 @@
enabled or disabled
(+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+
+ Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ This function allows to reset following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+
+ By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
+ and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
+ or @ref HAL_SAI_Init function.
+
+ When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -176,7 +212,6 @@
#ifdef HAL_SAI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-
/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
* @{
*/
@@ -366,8 +401,24 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
/* Allocate lock resource and initialize it */
hsai->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ if (hsai->MspInitCallback == NULL)
+ {
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ }
+ hsai->MspInitCallback(hsai);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
hsai->State = HAL_SAI_STATE_BUSY;
@@ -540,7 +591,15 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ if (hsai->MspDeInitCallback == NULL)
+ {
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ }
+ hsai->MspDeInitCallback(hsai);
+#else
HAL_SAI_MspDeInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/* Initialize the error code */
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
@@ -586,13 +645,189 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
*/
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user SAI callback
+ * to be used instead of the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = pCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user SAI callback.
+ * SAI callback is redirected to the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -1358,7 +1593,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
uint32_t cr1config = hsai->Instance->CR1;
uint32_t tmperror;
- /* SAI Fifo request interrupt occured ------------------------------------*/
+ /* SAI Fifo request interrupt occurred ------------------------------------*/
if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
{
hsai->InterruptServiceRoutine(hsai);
@@ -1373,7 +1608,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
/* Change the SAI error code */
hsai->ErrorCode |= tmperror;
/* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/* SAI mutedet interrupt occurred ----------------------------------*/
else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
@@ -1418,7 +1657,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
HAL_SAI_Abort(hsai);
/* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI LFSDET interrupt occurred ----------------------------------*/
@@ -1452,7 +1695,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
HAL_SAI_Abort(hsai);
/* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI WCKCFG interrupt occurred ----------------------------------*/
@@ -1489,7 +1736,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->XferCount = 0U;
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI CNRDY interrupt occurred ----------------------------------*/
@@ -1500,7 +1751,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
/* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1593,10 +1848,9 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
* @}
*/
-
/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1621,8 +1875,8 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
}
/**
-* @brief Return the SAI error code.
-* @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * @brief Return the SAI error code.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for the specified SAI Block.
* @retval SAI Error Code
*/
@@ -1630,6 +1884,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
{
return hsai->ErrorCode;
}
+
/**
* @}
*/
@@ -1639,7 +1894,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
*/
/** @addtogroup SAI_Private_Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
@@ -1915,7 +2170,11 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1939,7 +2198,11 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1964,7 +2227,11 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1997,7 +2264,11 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
@@ -2024,9 +2295,14 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
+
/**
* @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
* @param hsai pointer to a SAI_HandleTypeDef structure that contains
@@ -2050,7 +2326,11 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
@@ -2076,7 +2356,11 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
hsai->State= HAL_SAI_STATE_READY;
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2089,7 +2373,11 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxHalfCpltCallback(hsai);
+#else
HAL_SAI_TxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2101,7 +2389,8 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
@@ -2112,7 +2401,11 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
hsai->State = HAL_SAI_STATE_READY;
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2125,8 +2418,13 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxHalfCpltCallback(hsai);
+#else
HAL_SAI_RxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
+
/**
* @brief DMA SAI communication error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -2155,7 +2453,11 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma)
hsai->XferCount = 0U;
}
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2190,7 +2492,11 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
hsai->XferCount = 0U;
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai_ex.c
index 0f2353f7f42af279ed79b1bdc88715e083c98bf8..f9eb86234eeafb51a73df55427c6bd401c37e3fc 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sai_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sd.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sd.c
index 85f70a56132ec6725ef709b34cb95346f29d8dd1..ecef3963a1094663bb76f1e5eb144795324ee620 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sd.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sd.c
@@ -192,33 +192,64 @@
[..]
(@) You can refer to the SD HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ or @ref HAL_SD_Init function.
+
+ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -319,8 +350,24 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+
+ if(hsd->MspInitCallback == NULL)
+ {
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsd->MspInitCallback(hsd);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
+#endif
}
hsd->State = HAL_SD_STATE_BUSY;
@@ -417,8 +464,18 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
/* Set SD power state to off */
SD_PowerOFF(hsd);
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ if(hsd->MspDeInitCallback == NULL)
+ {
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsd->MspDeInitCallback(hsd);
+#else
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
+#endif
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
@@ -1392,7 +1449,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
@@ -1402,11 +1463,19 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
hsd->State = HAL_SD_STATE_READY;
if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->RxCpltCallback(hsd);
+#else
HAL_SD_RxCpltCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->TxCpltCallback(hsd);
+#else
HAL_SD_TxCpltCallback(hsd);
+#endif
}
}
else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
@@ -1417,7 +1486,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
@@ -1428,7 +1501,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->TxCpltCallback(hsd);
+#else
HAL_SD_TxCpltCallback(hsd);
+#endif
}
}
}
@@ -1501,14 +1578,22 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
}
else if((hsd->Context & SD_CONTEXT_IT) != RESET)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
}
@@ -1594,6 +1679,179 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
*/
}
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SD Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackId : Id of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = pCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = pCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = pCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = pCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SD Callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackId : Id of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+#endif
/**
* @}
@@ -2156,7 +2414,11 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
}
@@ -2206,7 +2468,11 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
@@ -2219,7 +2485,11 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->RxCpltCallback(hsd);
+#else
HAL_SD_RxCpltCallback(hsd);
+#endif
}
/**
@@ -2253,7 +2523,12 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma)
hsd->State= HAL_SD_STATE_READY;
}
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
@@ -2284,11 +2559,19 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
}
@@ -2321,11 +2604,19 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sdram.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sdram.c
index bfc92c139d70175348c2883e53e999f359b9b634..b2880b60473156a9c2a227af7f5af7cd38e991cc 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sdram.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sdram.c
@@ -57,33 +57,56 @@
(#) You can continuously monitor the SDRAM device HAL state by calling the function
HAL_SDRAM_GetState()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : SDRAM MspInit.
+ (+) MspDeInitCallback : SDRAM MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : SDRAM MspInit.
+ (+) MspDeInitCallback : SDRAM MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
+ and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
+ or @ref HAL_SDRAM_Init function.
+
+ When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -145,8 +168,21 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ if(hsdram->MspInitCallback == NULL)
+ {
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ }
+ hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+ hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+ /* Init the low level hardware */
+ hsdram->MspInitCallback(hsdram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
+#endif
}
/* Initialize the SDRAM controller state */
@@ -172,8 +208,18 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
*/
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
{
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ if(hsdram->MspDeInitCallback == NULL)
+ {
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsdram->MspDeInitCallback(hsdram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspDeInit(hsdram);
+#endif
/* Configure the SDRAM registers with their reset values */
FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
@@ -231,7 +277,11 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
{
/* SDRAM refresh error interrupt callback */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ hsdram->RefreshErrorCallback(hsdram);
+#else
HAL_SDRAM_RefreshErrorCallback(hsdram);
+#endif
/* Clear SDRAM refresh error interrupt pending bit */
__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
@@ -635,6 +685,204 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
return HAL_OK;
}
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SDRAM Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
+ * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
+ * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+/**
+ * @brief Unregister a User SDRAM Callback
+ * SDRAM Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
+ * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
+ * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+
+/**
+ * @brief Register a User SDRAM Callback for DMA transfers
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+#endif
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard.c
index f9f2749fb209accfc7bc0b88a36d281c589174bf..e4759851600491cda36d0cf17556131c569d9e10 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard.c
@@ -12,7 +12,7 @@
*
@verbatim
==============================================================================
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
[..]
The SMARTCARD HAL driver can be used as follows:
@@ -20,25 +20,22 @@
(#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
(#) Associate a USART to the SMARTCARD handle hsmartcard.
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) SMARTCARD pins configuration:
- (+++) Enable the clock for the SMARTCARD GPIOs.
- (+++) Configure these SMARTCARD pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (+++) The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
- (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -102,33 +99,78 @@
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
+ and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
+ or @ref HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -152,13 +194,21 @@
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U
-#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
+ USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -169,6 +219,9 @@
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -183,9 +236,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
@@ -197,7 +250,7 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
*/
/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
@@ -254,7 +307,7 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
+ if (hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -262,13 +315,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
/* Check the USART associated to the SMARTCARD handle */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsmartcard->Lock = HAL_UNLOCKED;
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+ if (hsmartcard->MspInitCallback == NULL)
+ {
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsmartcard->MspInitCallback(hsmartcard);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
}
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
@@ -315,7 +380,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
+ if (hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -328,14 +393,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
/* Disable the Peripheral */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- WRITE_REG(hsmartcard->Instance->CR1, 0x0);
- WRITE_REG(hsmartcard->Instance->CR2, 0x0);
- WRITE_REG(hsmartcard->Instance->CR3, 0x0);
- WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
- WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
/* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsmartcard->MspDeInitCallback == NULL)
+ {
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsmartcard->MspDeInitCallback(hsmartcard);
+#else
HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
@@ -379,12 +453,233 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
*/
}
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = pCallback;
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
+ * @brief SMARTCARD Transmit and Receive functions
*
@verbatim
==============================================================================
@@ -394,14 +689,14 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
- (#) Smartcard is a single wire half duplex communication protocol.
+ Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- (#) The USART should be configured as:
- (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
- (#) There are two modes of transfer:
+ [..]
+ (+) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
@@ -415,47 +710,47 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (#) Blocking mode APIs are :
+ (+) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
- (#) Non Blocking mode APIs with Interrupt are :
+ (+) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (#) Non Blocking mode functions with DMA are :
+ (+) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_SMARTCARD_Abort()
- (++) HAL_SMARTCARD_AbortTransmit()
- (++) HAL_SMARTCARD_AbortReceive()
- (++) HAL_SMARTCARD_Abort_IT()
- (++) HAL_SMARTCARD_AbortTransmit_IT()
- (++) HAL_SMARTCARD_AbortReceive_IT()
+ (+) HAL_SMARTCARD_Abort()
+ (+) HAL_SMARTCARD_AbortTransmit()
+ (+) HAL_SMARTCARD_AbortReceive()
+ (+) HAL_SMARTCARD_Abort_IT()
+ (+) HAL_SMARTCARD_AbortTransmit_IT()
+ (+) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_SMARTCARD_AbortCpltCallback()
- (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (+) HAL_SMARTCARD_AbortCpltCallback()
+ (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -472,12 +767,13 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((ptmpdata == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -487,7 +783,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Disable the Peripheral first to update mode for TX master */
@@ -495,7 +791,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
@@ -505,21 +801,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
- while(hsmartcard->TxXferCount > 0)
+ while (hsmartcard->TxXferCount > 0U)
{
hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+ ptmpdata++;
}
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -553,12 +850,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((ptmpdata == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -569,22 +867,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
/* Check the remain data to be received */
- while(hsmartcard->RxXferCount > 0)
+ while (hsmartcard->RxXferCount > 0U)
{
hsmartcard->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ ptmpdata++;
}
/* At end of Rx process, restore hsmartcard->RxState to Ready */
@@ -614,7 +913,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -625,21 +924,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
+ hsmartcard->TxISR = NULL;
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Configure Tx interrupt processing */
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@@ -668,9 +972,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -685,11 +989,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
+ /* Configure Rx interrupt processing */
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
/* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -715,7 +1023,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -735,7 +1043,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
@@ -751,22 +1059,36 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+ if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
- /* Clear the TC flag in the ICR register */
- CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- return HAL_OK;
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -787,9 +1109,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -813,22 +1135,36 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+ if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -848,7 +1184,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -861,13 +1197,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmatx);
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -877,19 +1222,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmarx);
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
@@ -916,14 +1270,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -935,18 +1289,27 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmatx);
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -969,14 +1332,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -988,18 +1352,27 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmarx);
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
+ hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
@@ -1024,10 +1397,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t abortcplt = 1;
+ uint32_t abortcplt = 1U;
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
@@ -1036,11 +1409,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
}
@@ -1050,11 +1423,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
}
}
/* DMA Rx Handle is valid */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
{
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
}
@@ -1065,25 +1438,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* SMARTCARD Tx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
hsmartcard->hdmatx->XferAbortCallback = NULL;
}
else
{
- abortcplt = 0;
+ abortcplt = 0U;
}
}
}
@@ -1094,30 +1467,34 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* SMARTCARD Rx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
hsmartcard->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1;
+ abortcplt = 1U;
}
else
{
- abortcplt = 0;
+ abortcplt = 0U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if (abortcplt == 1)
+ if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
/* Reset errorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
@@ -1130,7 +1507,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1150,14 +1533,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -1169,14 +1552,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
@@ -1185,19 +1568,31 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart
else
{
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
/* Restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -1206,7 +1601,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1231,9 +1632,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -1245,14 +1647,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
@@ -1261,7 +1663,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
else
{
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
@@ -1270,13 +1675,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
@@ -1285,15 +1699,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
- * @brief Handle SMARTCARD interrupt requests.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -1301,30 +1721,33 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
- uint32_t cr3its;
+ uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3);
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- SMARTCARD_Receive_IT(hsmartcard);
- /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
return;
}
}
/* If some errors occur */
- cr3its = READ_REG(hsmartcard->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* SMARTCARD parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
@@ -1332,7 +1755,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* SMARTCARD frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -1340,7 +1763,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* SMARTCARD noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
@@ -1348,8 +1771,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U)
+ || ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
@@ -1357,7 +1781,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
@@ -1365,12 +1789,16 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
/* Call SMARTCARD Error Call back function if need be --------------------------*/
- if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- SMARTCARD_Receive_IT(hsmartcard);
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
}
/* If Error is to be considered as blocking :
@@ -1378,8 +1806,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
- if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
- || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+ errorcode = hsmartcard->ErrorCode;
+ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
{
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
@@ -1392,14 +1821,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
@@ -1407,20 +1836,31 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
/* other error type to be considered as blocking :
- Frame error in Transmission
*/
- else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
{
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
@@ -1433,14 +1873,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
@@ -1448,21 +1888,37 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
}
}
@@ -1471,30 +1927,44 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
} /* End if some error occurs */
/* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
- if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+ if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
{
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
__HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
/* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
- * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ to be available during HAL_SMARTCARD_RxCpltCallback() processing */
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
return;
}
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
- SMARTCARD_Transmit_IT(hsmartcard);
+ if (hsmartcard->TxISR != NULL)
+ {
+ hsmartcard->TxISR(hsmartcard);
+ }
return;
}
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
+ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
- SMARTCARD_EndTransmit_IT(hsmartcard);
- return;
+ if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
}
+
}
/**
@@ -1551,7 +2021,7 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1567,7 +2037,7 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1583,7 +2053,7 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1598,7 +2068,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm
*/
/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
+ * @brief SMARTCARD State and Errors functions
*
@verbatim
==============================================================================
@@ -1625,9 +2095,9 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
- uint32_t temp1= 0x00, temp2 = 0x00;
- temp1 = hsmartcard->gState;
- temp2 = hsmartcard->RxState;
+ uint32_t temp1, temp2;
+ temp1 = (uint32_t)hsmartcard->gState;
+ temp2 = (uint32_t)hsmartcard->RxState;
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
@@ -1637,7 +2107,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
-*/
+ */
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->ErrorCode;
@@ -1655,17 +2125,36 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
* @{
*/
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
- * @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Initialize the callbacks to their default values.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @retval None
+ * @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tmpreg = 0x00000000;
- SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t tmpreg;
+ SMARTCARD_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@@ -1688,8 +2177,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -1706,49 +2194,66 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
* according to hsmartcard->Init.OneBitSampling
* - NACK transmission in case of parity error according
* to hsmartcard->Init.NACKEnable
- * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
- tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
- tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
- MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
/*-------------------------- USART GTPR Configuration ----------------------*/
- tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
/*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ tmpreg = 0U;
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
- hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
- case SMARTCARD_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hsmartcard->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
return ret;
}
@@ -1756,7 +2261,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
/**
* @brief Configure the SMARTCARD associated USART peripheral advanced features.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1818,24 +2323,24 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @brief Check the SMARTCARD Idle State.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Initialize the SMARTCARD ErrorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@@ -1855,7 +2360,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
/**
* @brief Handle SMARTCARD Communication Timeout.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @param Flag Specifies the SMARTCARD flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Tickstart Tick start value
@@ -1865,12 +2370,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -1892,7 +2397,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/**
* @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1909,7 +2414,7 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1931,8 +2436,8 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->TxXferCount = 0;
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the SMARTCARD associated USART CR3 register */
@@ -1950,8 +2455,8 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0;
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
@@ -1964,7 +2469,13 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* At end of Rx process, restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1975,26 +2486,36 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
/* Stop SMARTCARD DMA Tx request if ongoing */
- if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- hsmartcard->TxXferCount = 0;
- SMARTCARD_EndTxTransfer(hsmartcard);
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
}
/* Stop SMARTCARD DMA Rx request if ongoing */
- if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- hsmartcard->RxXferCount = 0;
- SMARTCARD_EndRxTransfer(hsmartcard);
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
}
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2005,11 +2526,17 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
- hsmartcard->RxXferCount = 0;
- hsmartcard->TxXferCount = 0;
-
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2022,22 +2549,22 @@ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+ if (hsmartcard->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
/* Reset errorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
@@ -2049,8 +2576,13 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
@@ -2064,22 +2596,22 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+ if (hsmartcard->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsmartcard->TxXferCount = 0;
- hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
/* Reset errorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
@@ -2091,8 +2623,13 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
@@ -2106,9 +2643,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
- hsmartcard->TxXferCount = 0;
+ hsmartcard->TxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -2116,8 +2653,13 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/* Restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2130,9 +2672,9 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
- hsmartcard->RxXferCount = 0;
+ hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
@@ -2140,67 +2682,65 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT().
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check that a Tx process is ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- if(hsmartcard->TxXferCount == 0)
+ if (hsmartcard->TxXferCount == 0U)
{
/* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
/* Enable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
-
- return HAL_OK;
}
else
{
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
hsmartcard->TxXferCount--;
-
- return HAL_OK;
}
}
- else
- {
- return HAL_BUSY;
- }
}
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -2212,32 +2752,41 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+ /* Clear TxISR function pointer */
+ hsmartcard->TxISR = NULL;
- return HAL_OK;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsmartcard->TxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
* interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
- * @retval HAL status
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check that a Rx process is ongoing */
if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
- if(--hsmartcard->RxXferCount == 0)
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
{
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
/* Check if a transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -2248,19 +2797,22 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
- return HAL_OK;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
-
- return HAL_OK;
}
else
{
/* Clear RXNE interrupt flag */
__HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard_ex.c
index 6e4bd53a9a255c89022cf0e9a3ac34c8fde3729b..a5881e2b45f6bd8fe0c2835fb1933465bce77cb0 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smartcard_ex.c
@@ -3,49 +3,32 @@
* @file stm32f7xx_hal_smartcard_ex.c
* @author MCD Application Team
* @brief SMARTCARD HAL module driver.
- *
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
* + Initialization and de-initialization functions
* + Peripheral Control functions
+ *
@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The Extended SMARTCARD HAL driver can be used as follow:
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
- then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
- auto-retry counter,...) in the hsc AdvancedInit structure.
-
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -65,24 +48,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
* @{
*/
-/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended control functions
*
@verbatim
- ===============================================================================
+ ===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
(+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
(+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
@@ -92,85 +74,141 @@
* @{
*/
-/**
- * @brief Update on the fly the SMARTCARD block length in RTOR register
- * @param hsc SMARTCARD handle
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @param BlockLength SMARTCARD block length (8-bit long at most)
* @retval None
*/
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
{
- MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
}
-/**
- * @brief Update on the fly the receiver timeout value in RTOR register
- * @param hsc SMARTCARD handle
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
{
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
- MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
}
-/**
- * @brief Enable the SMARTCARD receiver timeout feature
- * @param hsc SMARTCARD handle
+/** @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Process Locked */
- __HAL_LOCK(hsc);
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
- /* Set the USART RTOEN bit */
- hsc->Instance->CR2 |= USART_CR2_RTOEN;
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
- hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
-/**
- * @brief Disable the SMARTCARD receiver timeout feature
- * @param hsc SMARTCARD handle
+/** @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Process Locked */
- __HAL_LOCK(hsc);
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
- /* Clear the USART RTOEN bit */
- hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
- hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
* @}
*/
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+@endverbatim
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
+ * @brief SMARTCARD control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions
+ * @{
+ */
+
/**
* @}
*/
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smbus.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smbus.c
index 6f14d8a305448b7c4be8b2997ebcf5ea54d3334c..f23105d9edf0ddf37fbe306a28e0ef6fe4bf0e2d 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smbus.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_smbus.c
@@ -20,7 +20,7 @@
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
SMBUS_HandleTypeDef hsmbus;
- (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
(##) Enable the SMBUSx interface clock
(##) SMBUS pins configuration
(+++) Enable the clock for the SMBUS GPIOs
@@ -33,91 +33,133 @@
Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
- (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
(++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+ by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
- (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
(#) For SMBUS IO operations, only one mode of operations is available within this driver
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
(++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+ using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
- (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Error Code using function HAL_SMBUS_GetError()
+ (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
+ (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function @ref HAL_SMBUS_GetError()
*** SMBUS HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SMBUS HAL driver.
- (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
- (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
- (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
- (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+
+ Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+
+ By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
+ or @ref HAL_SMBUS_Init() function.
+
+ When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the SMBUS HAL driver header file for more useful macros
-
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -141,7 +183,7 @@
/** @defgroup SMBUS_Private_Define SMBUS Private Constants
* @{
*/
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */
#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
@@ -161,18 +203,18 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -255,8 +297,26 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
/* Allocate lock resource and initialize it */
hsmbus->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hsmbus->MspInitCallback == NULL)
+ {
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hsmbus->MspInitCallback(hsmbus);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
hsmbus->State = HAL_SMBUS_STATE_BUSY;
@@ -278,7 +338,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
/* Configure SMBUSx: Own Address1 and ack own address1 mode */
hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if (hsmbus->Init.OwnAddress1 != 0U)
+ if (hsmbus->Init.OwnAddress1 != 0UL)
{
if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
{
@@ -347,8 +407,18 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
/* Disable the SMBUS Peripheral Clock */
__HAL_SMBUS_DISABLE(hsmbus);
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ if (hsmbus->MspDeInitCallback == NULL)
+ {
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hsmbus->MspDeInitCallback(hsmbus);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
@@ -447,7 +517,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint
*/
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -490,6 +560,299 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
}
}
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an SMBUS Callback
+ * SMBUS callback is redirected to the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match SMBUS Callback
+ * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match SMBUS Callback
+ * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -541,7 +904,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
* @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address which contain device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -550,6 +913,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ uint32_t tmp;
+
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -583,17 +948,21 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+
+ /* Store current volatile XferOptions, misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -602,12 +971,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -634,7 +1003,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
* @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address which contain device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -643,6 +1012,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ uint32_t tmp;
+
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -677,17 +1048,21 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+
+ /* Store current volatile XferOptions, Misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -696,7 +1071,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
}
}
@@ -721,7 +1096,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
* @note This abort can be called only if state is ready
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address which contain device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
@@ -752,7 +1127,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_
/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -768,6 +1143,10 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
}
+ else
+ {
+ /* Nothing to do */
+ }
return HAL_OK;
}
@@ -791,11 +1170,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- if ((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0UL))
{
- return HAL_ERROR;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -804,7 +1184,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
/* Process Locked */
__HAL_LOCK(hsmbus);
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
/* Set SBC bit to manage Acknowledge at each bit */
@@ -831,18 +1211,18 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
}
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -866,7 +1246,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
}
else
{
- return HAL_ERROR;
+ return HAL_BUSY;
}
}
@@ -884,11 +1264,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- if ((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0UL))
{
- return HAL_ERROR;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -897,7 +1278,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* Process Locked */
__HAL_LOCK(hsmbus);
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
/* Set SBC bit to manage Acknowledge at each bit */
@@ -920,13 +1301,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
{
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else
{
- SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
}
/* Clear ADDR flag after prepare the transfer parameters */
@@ -946,7 +1327,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
}
else
{
- return HAL_ERROR;
+ return HAL_BUSY;
}
}
@@ -1030,7 +1411,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
* @brief Check if target device is ready for communication.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address which contain device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
@@ -1038,9 +1419,12 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
*/
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+
+ __IO uint32_t SMBUS_Trials = 0UL;
- __IO uint32_t SMBUS_Trials = 0U;
+ FlagStatus tmp1;
+ FlagStatus tmp2;
if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
@@ -1063,20 +1447,30 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
@@ -1085,7 +1479,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -1104,7 +1498,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear NACK Flag */
@@ -1115,7 +1509,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
}
/* Check if the maximum allowed number of trials has been reached */
- if (SMBUS_Trials++ == Trials)
+ if (SMBUS_Trials == Trials)
{
/* Generate Stop */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
@@ -1123,21 +1517,27 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
}
+
+ /* Increment Trials */
+ SMBUS_Trials++;
}
while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
else
{
@@ -1160,49 +1560,55 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
*/
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
- uint32_t tmpisrvalue = 0U;
-
/* Use a local variable to store the current ISR flags */
/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
- tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+ uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
+ uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
/* Master mode selected */
else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
- SMBUS_Master_ISR(hsmbus);
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
}
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
/* Master mode selected */
else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
- SMBUS_Master_ISR(hsmbus);
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
}
}
/* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
}
}
@@ -1392,16 +1798,17 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint16_t DevAddress;
/* Process Locked */
__HAL_LOCK(hsmbus);
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1414,9 +1821,13 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
__HAL_UNLOCK(hsmbus);
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
{
/* Check and treat errors if errors occurs during STOP process */
SMBUS_ITErrorHandler(hsmbus);
@@ -1446,15 +1857,23 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* REenable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
/* Store Last receive data if any */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
if ((hsmbus->XferSize > 0U))
{
@@ -1478,28 +1897,47 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
{
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
{
- DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+ DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
@@ -1509,17 +1947,17 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
}
- else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
+ else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
{
/* Call TxCpltCallback() if no stop mode is set */
if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
@@ -1535,7 +1973,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
@@ -1546,12 +1989,25 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
{
if (hsmbus->XferCount == 0U)
{
@@ -1578,7 +2034,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
@@ -1589,11 +2050,28 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1604,17 +2082,18 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
- uint8_t TransferDirection = 0U;
- uint16_t SlaveAddrCode = 0U;
+ uint8_t TransferDirection;
+ uint16_t SlaveAddrCode;
/* Process Locked */
__HAL_LOCK(hsmbus);
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
{
/* Check that SMBUS transfer finished */
/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
@@ -1650,13 +2129,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
__HAL_UNLOCK(hsmbus);
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
{
- TransferDirection = SMBUS_GET_DIR(hsmbus);
- SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+ TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
+ SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
/* Other ADDRInterrupt will be treat in next Listen usecase */
@@ -1666,14 +2149,22 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
__HAL_UNLOCK(hsmbus);
/* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
{
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1683,7 +2174,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else if (hsmbus->XferCount == 0U)
{
@@ -1697,13 +2188,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else
{
/* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -1711,20 +2206,20 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
}
else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1732,8 +2227,12 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@@ -1742,7 +2241,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
if (hsmbus->XferCount > 0U)
{
/* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
hsmbus->XferCount--;
hsmbus->XferSize--;
}
@@ -1758,13 +2261,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if STOPF is set */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
{
if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
@@ -1772,7 +2283,10 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
if ((hsmbus->XferSize > 0U))
{
@@ -1799,7 +2313,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Clear ADDR flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
- hsmbus->XferOptions = 0U;
+ hsmbus->XferOptions = 0;
hsmbus->PreviousState = hsmbus->State;
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1807,7 +2321,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
__HAL_UNLOCK(hsmbus);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
@@ -1823,9 +2341,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
- uint32_t tmpisr = 0U;
+ uint32_t tmpisr = 0UL;
if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
{
@@ -1855,8 +2373,6 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* to avoid the risk of SMBUS interrupt handle execution before */
/* all interrupts requested done */
__HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
}
/**
* @brief Manage the disabling of Interrupts.
@@ -1865,11 +2381,12 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
- uint32_t tmpisr = 0U;
+ uint32_t tmpisr = 0UL;
+ uint32_t tmpstate = hsmbus->State;
- if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
+ if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1877,48 +2394,48 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
- /* Disable TC, STOP, NACK, TXI interrupt */
+ /* Disable TC, STOP, NACK and TXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
- /* Disable STOPI, NACKI */
+ /* Disable STOP and NACK interrupt */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
- /* Disable TC, STOP, NACK, RXI interrupt */
+ /* Disable TC, STOP, NACK and RXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
- /* Disable STOPI, NACKI */
+ /* Disable STOP and NACK interrupt */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
- /* Enable ADDR, STOP interrupt */
+ /* Disable ADDR, STOP and NACK interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1929,8 +2446,6 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
}
/**
@@ -1938,13 +2453,15 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
{
uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+ uint32_t tmpstate;
+ uint32_t tmperror;
/* SMBUS Bus error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
@@ -1953,7 +2470,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
@@ -1962,7 +2479,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
@@ -1971,7 +2488,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
@@ -1980,7 +2497,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
@@ -1989,7 +2506,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
@@ -1997,14 +2514,20 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
+ /* Store current volatile hsmbus->State, misra rule */
+ tmperror = hsmbus->ErrorCode;
+
/* Call the Error Callback in case of Error detected */
- if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
{
/* Do not Reset the HAL state in case of ALERT error */
- if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
{
- if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ /* Store current volatile hsmbus->State, misra rule */
+ tmpstate = hsmbus->State;
+
+ if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
{
/* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
/* keep HAL_SMBUS_STATE_LISTEN if set */
@@ -2014,7 +2537,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
}
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
@@ -2027,51 +2554,32 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
- if (Status == RESET)
+ while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
{
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
}
}
+
return HAL_OK;
}
@@ -2095,7 +2603,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2103,7 +2611,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
/* update CR2 register */
- MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
@@ -2112,7 +2620,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
{
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
@@ -2144,6 +2652,10 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spdifrx.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spdifrx.c
index 50c5eab1a8ed71100b8e06930d12a9feb916658c..15c03ac3f9526b006a9e089406020d37400d6700 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spdifrx.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spdifrx.c
@@ -47,13 +47,13 @@
================================================================
[..]
(+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
- (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
*** Interrupt mode for reception operation ***
=========================================
[..]
(+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
- (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
+ (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT()
(+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
(+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
@@ -65,7 +65,7 @@
========================================
[..]
(+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
- (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
+ (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA()
(+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
(+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
@@ -77,7 +77,7 @@
*** SPDIFRX HAL driver macros list ***
=============================================
[..]
- Below the list of most used macros in USART HAL driver.
+ Below the list of most used macros in SPDIFRX HAL driver.
(+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
(+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
(+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
@@ -85,36 +85,73 @@
(+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
(+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
- [..]
+ [..]
(@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.
+
+ The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
+ (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
+ (+) RxCpltCallback : SPDIFRX Data flow completed callback.
+ (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback.
+ (+) CxCpltCallback : SPDIFRX Control flow completed callback.
+ (+) ErrorCallback : SPDIFRX error callback.
+ (+) MspInitCallback : SPDIFRX MspInit.
+ (+) MspDeInitCallback : SPDIFRX MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default
+ weak function.
+ The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset the following callbacks:
+ (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
+ (+) RxCpltCallback : SPDIFRX Data flow completed callback.
+ (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback.
+ (+) CxCpltCallback : SPDIFRX Control flow completed callback.
+ (+) ErrorCallback : SPDIFRX error callback.
+ (+) MspInitCallback : SPDIFRX MspInit.
+ (+) MspDeInitCallback : SPDIFRX MspDeInit.
+
+ By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(),
+ HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback()
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when
+ these callbacks pointers are NULL (not registered beforehand).
+ If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit()
+ or HAL_SPDIFRX_Init() function.
+
+ When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -125,17 +162,18 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
+
/** @defgroup SPDIFRX SPDIFRX
-* @brief SPDIFRX HAL module driver
-* @{
-*/
+ * @brief SPDIFRX HAL module driver
+ * @{
+ */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#if defined (SPDIFRX)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define SPDIFRX_TIMEOUT_VALUE 0xFFFF
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -168,13 +206,13 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPDIFRX peripheral:
+ de-initialize the SPDIFRX peripheral:
(+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
- the selected configuration:
+ the selected configuration:
(++) Input Selection (IN0, IN1,...)
(++) Maximum allowed re-tries during synchronization phase
(++) Wait for activity on SPDIF selected input
@@ -184,7 +222,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
(++) User bits masking (PT,C,U,V,...)
(+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
- of the selected SPDIFRXx peripheral.
+ of the selected SPDIFRXx peripheral.
@endverbatim
* @{
*/
@@ -197,7 +235,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
*/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
@@ -217,6 +255,27 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspdif->Lock = HAL_UNLOCKED;
+
+ hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */
+ hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */
+ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if(hspdif->MspInitCallback == NULL)
+ {
+ hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hspdif->MspInitCallback(hspdif);
+ }
+#else
if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -224,8 +283,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SPDIFRX_MspInit(hspdif);
}
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
- /* SPDIFRX peripheral state is BUSY*/
+ /* SPDIFRX peripheral state is BUSY */
hspdif->State = HAL_SPDIFRX_STATE_BUSY;
/* Disable SPDIFRX interface (IDLE State) */
@@ -234,12 +294,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
/* Reset the old SPDIFRX CR configuration */
tmpreg = hspdif->Instance->CR;
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
- SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL);
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+ SPDIFRX_CR_INSEL);
/* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
+ tmpreg |= (hspdif->Init.StereoMode |
hspdif->Init.InputSelection |
hspdif->Init.Retries |
hspdif->Init.WaitForActivity |
@@ -248,7 +309,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
hspdif->Init.PreambleTypeMask |
hspdif->Init.ChannelStatusMask |
hspdif->Init.ValidityBitMask |
- hspdif->Init.ParityErrorMask);
+ hspdif->Init.ParityErrorMask
+ );
+
hspdif->Instance->CR = tmpreg;
@@ -281,8 +344,18 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
/* Disable SPDIFRX interface (IDLE state) */
__HAL_SPDIFRX_IDLE(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ if(hspdif->MspDeInitCallback == NULL)
+ {
+ hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hspdif->MspDeInitCallback(hspdif);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPDIFRX_MspDeInit(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
@@ -325,16 +398,207 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
*/
}
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
/**
- * @brief Sets the SPDIFRX dtat format according to the specified parameters
- * in the SPDIFRX_InitTypeDef.
+ * @brief Register a User SPDIFRX Callback
+ * To be used instead of the weak predefined callback
+ * @param hspdif SPDIFRX handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
+ * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspdif);
+
+ if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_RX_HALF_CB_ID :
+ hspdif->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_RX_CPLT_CB_ID :
+ hspdif->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_HALF_CB_ID :
+ hspdif->CxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_CPLT_CB_ID :
+ hspdif->CxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_ERROR_CB_ID :
+ hspdif->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+ return status;
+}
+
+/**
+ * @brief Unregister a SPDIFRX Callback
+ * SPDIFRX callabck is redirected to the weak predefined callback
+ * @param hspdif SPDIFRX handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
+ * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
+{
+HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspdif);
+
+ if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_RX_HALF_CB_ID :
+ hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_RX_CPLT_CB_ID :
+ hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_HALF_CB_ID :
+ hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_CPLT_CB_ID :
+ hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_ERROR_CB_ID :
+ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+ return status;
+}
+
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+/**
+ * @brief Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.
* @param hspdif SPDIFRX handle
* @param sDataFormat SPDIFRX data format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
@@ -360,11 +624,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
return HAL_ERROR;
}
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
- /* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) sDataFormat.StereoMode |
+ /* Configure the new data format */
+ tmpreg |= (sDataFormat.StereoMode |
sDataFormat.DataFormat |
sDataFormat.PreambleTypeMask |
sDataFormat.ChannelStatusMask |
@@ -416,13 +680,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
(++) HAL_SPDIFRX_RxCpltCallback()
- (++) HAL_SPDIFRX_ErrorCallback()
+ (++) HAL_SPDIFRX_CxCpltCallback()
@endverbatim
* @{
*/
-
/**
* @brief Receives an amount of data (Data Flow) in blocking mode.
* @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains
@@ -434,7 +697,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+ uint16_t sizeCounter = Size;
+ uint32_t *pTmpBuf = pData;
if((pData == NULL ) || (Size == 0U))
{
@@ -464,7 +729,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
__HAL_SPDIFRX_RCV(hspdif);
/* Receive data flow */
- while(Size > 0U)
+ while(sizeCounter > 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
@@ -475,8 +740,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
return HAL_TIMEOUT;
}
- (*pData++) = hspdif->Instance->DR;
- Size--;
+ (*pTmpBuf) = hspdif->Instance->DR;
+ pTmpBuf++;
+ sizeCounter--;
}
/* SPDIFRX ready */
@@ -504,7 +770,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+ uint16_t sizeCounter = Size;
+ uint32_t *pTmpBuf = pData;
if((pData == NULL ) || (Size == 0U))
{
@@ -534,7 +802,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_RCV(hspdif);
/* Receive control flow */
- while(Size > 0U)
+ while(sizeCounter > 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
@@ -545,8 +813,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
return HAL_TIMEOUT;
}
- (*pData++) = hspdif->Instance->CSR;
- Size--;
+ (*pTmpBuf) = hspdif->Instance->CSR;
+ pTmpBuf++;
+ sizeCounter--;
}
/* SPDIFRX ready */
@@ -572,9 +841,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
if((pData == NULL) || (Size == 0U))
{
@@ -593,37 +864,51 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
/* Check if a receive process is ongoing or not */
hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
-
/* Enable the SPDIFRX PE Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
/* Enable the SPDIFRX OVR Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
/* Enable the SPDIFRX RXNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
+ do
{
- return HAL_TIMEOUT;
- }
+ if (count == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
return HAL_OK;
}
else
@@ -636,14 +921,16 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
* @brief Receive an amount of data (Control Flow) with Interrupt
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data sample (Control Flow) to be received :
+ * @param Size number of data sample (Control Flow) to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
if((pData == NULL ) || (Size == 0U))
{
@@ -662,37 +949,51 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
/* Check if a receive process is ongoing or not */
hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
-
/* Enable the SPDIFRX PE Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
/* Enable the SPDIFRX OVR Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
/* Enable the SPDIFRX CSRNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
+ do
{
- return HAL_TIMEOUT;
- }
+ if (count == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
return HAL_OK;
}
else
@@ -705,27 +1006,29 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
* @brief Receive an amount of data (Data Flow) mode with DMA
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be received :
+ * @param Size number of data sample to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
hspdif->pRxBuffPtr = pData;
hspdif->RxXferSize = Size;
hspdif->RxXferCount = Size;
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
@@ -739,24 +1042,51 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
+ if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set SPDIFRX error */
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+ /* Set SPDIFRX state */
+ hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_ERROR;
+ }
/* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
+ do
{
- return HAL_TIMEOUT;
- }
+ if (count == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
@@ -777,19 +1107,21 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
* @brief Receive an amount of data (Control Flow) with DMA
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data (Control Flow) sample to be received :
+ * @param Size number of data (Control Flow) sample to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
hspdif->pCsBuffPtr = pData;
hspdif->CsXferSize = Size;
@@ -811,24 +1143,51 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd
hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
+ if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
+ {
+ /* Set SPDIFRX error */
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+ /* Set SPDIFRX state */
+ hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_ERROR;
+ }
/* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
- if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
+ do
{
- return HAL_TIMEOUT;
- }
+ if (count == 0U)
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_TIMEOUT;
+ }
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
@@ -881,24 +1240,27 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
*/
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
{
- /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
+ uint32_t itFlag = hspdif->Instance->SR;
+ uint32_t itSource = hspdif->Instance->IMR;
+
+ /* SPDIFRX in mode Data Flow Reception */
+ if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
SPDIFRX_ReceiveDataFlow_IT(hspdif);
}
- /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
+ /* SPDIFRX in mode Control Flow Reception */
+ if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
SPDIFRX_ReceiveControlFlow_IT(hspdif);
}
- /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
+ /* SPDIFRX Overrun error interrupt occurred */
+ if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
{
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
/* Change the SPDIFRX error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
@@ -907,10 +1269,10 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
HAL_SPDIFRX_ErrorCallback(hspdif);
}
- /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
+ /* SPDIFRX Parity error interrupt occurred */
+ if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
{
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
/* Change the SPDIFRX error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
@@ -931,7 +1293,7 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
UNUSED(hspdif);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
*/
}
@@ -946,7 +1308,7 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
UNUSED(hspdif);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
*/
}
@@ -961,7 +1323,7 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
UNUSED(hspdif);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
*/
}
@@ -976,7 +1338,7 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
UNUSED(hspdif);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+ the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
*/
}
@@ -991,7 +1353,7 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
UNUSED(hspdif);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+ the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
*/
}
@@ -1016,20 +1378,20 @@ and the data flow.
/**
* @brief Return the SPDIFRX state
- * @param hspdif SPDIFRX handle
+ * @param hspdif SPDIFRX handle
* @retval HAL state
*/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif)
{
return hspdif->State;
}
/**
* @brief Return the SPDIFRX error code
- * @param hspdif SPDIFRX handle
+ * @param hspdif SPDIFRX handle
* @retval SPDIFRX Error Code
*/
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
{
return hspdif->ErrorCode;
}
@@ -1040,7 +1402,7 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
/**
* @brief DMA SPDIFRX receive process (Data flow) complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -1048,31 +1410,39 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Disable Rx DMA Request */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if(hdma->Init.Mode != DMA_CIRCULAR)
{
hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
hspdif->RxXferCount = 0;
hspdif->State = HAL_SPDIFRX_STATE_READY;
}
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxCpltCallback(hspdif);
+#else
HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX receive process (Data flow) half complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxHalfCpltCallback(hspdif);
+#else
HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX receive process (Control flow) complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
@@ -1084,24 +1454,32 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
hspdif->CsXferCount = 0;
hspdif->State = HAL_SPDIFRX_STATE_READY;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxCpltCallback(hspdif);
+#else
HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX receive process (Control flow) half complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
{
SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxHalfCpltCallback(hspdif);
+#else
HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX communication error callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
@@ -1116,7 +1494,14 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
/* Set the error code and execute error callback*/
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ /* The transfer is not stopped */
+ hspdif->ErrorCallback(hspdif);
+#else
+ /* The transfer is not stopped */
HAL_SPDIFRX_ErrorCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
@@ -1127,10 +1512,11 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
{
/* Receive data */
- (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+ (*hspdif->pRxBuffPtr) = hspdif->Instance->DR;
+ hspdif->pRxBuffPtr++;
hspdif->RxXferCount--;
- if(hspdif->RxXferCount == 0)
+ if(hspdif->RxXferCount == 0U)
{
/* Disable RXNE/PE and OVR interrupts */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
@@ -1140,7 +1526,11 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
- HAL_SPDIFRX_RxCpltCallback(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxCpltCallback(hspdif);
+#else
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1152,10 +1542,11 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
{
/* Receive data */
- (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+ (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR;
+ hspdif->pCsBuffPtr++;
hspdif->CsXferCount--;
- if(hspdif->CsXferCount == 0)
+ if(hspdif->CsXferCount == 0U)
{
/* Disable CSRNE interrupt */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
@@ -1165,7 +1556,11 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
- HAL_SPDIFRX_CxCpltCallback(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxCpltCallback(hspdif);
+#else
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1181,68 +1576,40 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
{
/* Wait until flag is set */
- if(Status == RESET)
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
{
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
- else
- {
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
return HAL_OK;
}
/**
-* @}
-*/
+ * @}
+ */
+
+
#endif /* SPDIFRX */
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi.c
index 974a0047141848bc47bba64c9670f98212105b88..2e14cea07ea5efcb4dfb607a4cb3f1cfc9f732a9 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi.c
@@ -33,7 +33,7 @@
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
@@ -50,20 +50,80 @@
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
[..]
- (@) The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- (@)
- (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+ Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
@endverbatim
- Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
- the following table resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+ Additional table :
DataSize = SPI_DATASIZE_8BIT:
+----------------------------------------------------------------------------------------------+
@@ -114,33 +174,23 @@
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -184,7 +234,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart);
@@ -301,8 +351,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
@@ -343,7 +413,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit, CRC calculation state */
+ Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
@@ -355,8 +425,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
}
#endif /* USE_SPI_CRC */
- /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
#if (USE_SPI_CRC != 0U)
@@ -401,8 +471,18 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
@@ -445,6 +525,221 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
*/
}
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -493,8 +788,9 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -504,6 +800,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
+ initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
@@ -555,20 +852,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -579,6 +882,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 8 Bit mode */
else
{
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr ++;
+ hspi->TxXferCount--;
+ }
+ }
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
@@ -587,20 +906,21 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -651,10 +971,7 @@ error:
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -709,12 +1026,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Set the Rx Fifo threshold */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -741,14 +1058,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
- (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
- pData += sizeof(uint8_t);
+ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -764,14 +1081,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- *((uint16_t *)pData) = hspi->Instance->DR;
- pData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -798,12 +1115,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Receive last data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- *((uint16_t *)pData) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
- (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
}
/* Wait the CRC data */
@@ -817,28 +1134,25 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Read CRC to Flush DR and RXNE flag */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -883,14 +1197,19 @@ error :
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
+ uint32_t spi_cr1;
+ uint32_t spi_cr2;
#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
+
/* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -901,11 +1220,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+#if (USE_SPI_CRC != 0U)
+ spi_cr1 = READ_REG(hspi->Instance->CR1);
+ spi_cr2 = READ_REG(hspi->Instance->CR2);
+#endif /* USE_SPI_CRC */
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -945,14 +1271,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -966,19 +1292,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
@@ -988,7 +1314,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
@@ -998,15 +1324,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Check RXNE flag */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -1016,26 +1342,36 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Transmit and Receive data in 8 Bit mode */
else
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);
- pTxData += sizeof(uint8_t);
- hspi->TxXferCount--;
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
+ hspi->TxXferCount--;
+ }
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
- /* check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1046,7 +1382,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
@@ -1056,28 +1392,29 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Wait until RXNE flag is reset */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
if (hspi->RxXferCount > 1U)
{
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount -= 2U;
if (hspi->RxXferCount <= 1U)
{
- /* set fiforxthreshold before to switch on 8 bit data size */
+ /* Set RX Fifo threshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
}
else
{
- (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
}
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -1100,15 +1437,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Read CRC */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -1119,9 +1454,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
errorcode = HAL_TIMEOUT;
goto error;
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -1139,13 +1473,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
error :
@@ -1284,16 +1614,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
hspi->TxXferCount = 0U;
hspi->TxISR = NULL;
- /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+ /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data length: 16 bit */
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- /* set fiforxthreshold according the reception data length: 8 bit */
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_8BIT;
}
@@ -1352,8 +1682,9 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1361,11 +1692,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -1421,15 +1753,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
}
#endif /* USE_SPI_CRC */
- /* check if packing mode is enabled and if there is more than 2 data to receive */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+ /* Check if packing mode is enabled and if there is more than 2 data to receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
{
- /* set fiforxthreshold according the reception data length: 16 bit */
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8 bit */
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -1461,6 +1793,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -1520,7 +1855,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
hspi->hdmatx->XferAbortCallback = NULL;
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- /* packing mode is enabled only if the DMA setting is HALWORD */
+ /* Packing mode is enabled only if the DMA setting is HALWORD */
if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Check the even/odd of the data size + crc if enabled */
@@ -1537,7 +1872,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
}
/* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1560,6 +1903,7 @@ error :
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
@@ -1571,9 +1915,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
@@ -1620,24 +1971,34 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
#endif /* USE_SPI_CRC */
- /* packing mode management is enabled by the DMA settings */
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
- {
- /* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
- goto error;
- }
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* Set RX Fifo threshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
}
/* Set the SPI RxDMA Half transfer complete callback */
@@ -1653,7 +2014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1687,19 +2056,26 @@ error:
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
- if (!((tmp == HAL_SPI_STATE_READY) ||
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -1741,15 +2117,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
- /* the packing mode management is enabled by the DMA settings according the spi data size */
+ /* The packing mode management is enabled by the DMA settings according the spi data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
@@ -1768,7 +2144,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if ((hspi->RxXferCount & 0x1U) == 0x0U)
@@ -1805,7 +2181,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
@@ -1818,7 +2202,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1854,38 +2246,55 @@ error :
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
- uint32_t tickstart = 0U;
+ __IO uint32_t count, resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
- }
-
- while (hspi->State != HAL_SPI_STATE_ABORT)
- {
- if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY)
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
{
- return HAL_TIMEOUT;
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
}
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmatx != NULL)
@@ -1917,6 +2326,11 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
}
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmarx != NULL)
{
@@ -1993,38 +2407,55 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
- uint32_t tickstart = 0U;
uint32_t abortcplt ;
+ __IO uint32_t count, resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
- }
-
- while (hspi->State != HAL_SPI_STATE_ABORT)
- {
- if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY)
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
{
- return HAL_TIMEOUT;
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
}
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -2056,41 +2487,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel */
@@ -2108,7 +2505,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
/* Abort the SPI DMA Rx Stream/Channel */
@@ -2153,7 +2550,11 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
hspi->State = HAL_SPI_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
return errorcode;
@@ -2200,13 +2601,14 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
@@ -2216,18 +2618,26 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
/* Abort the SPI DMA tx Stream/Channel */
if (hspi->hdmatx != NULL)
{
- HAL_DMA_Abort(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Abort the SPI DMA rx Stream/Channel */
if (hspi->hdmarx != NULL)
{
- HAL_DMA_Abort(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
+ return errorcode;
}
/**
@@ -2242,25 +2652,25 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
- if (((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
/* SPI in mode Transmitter -------------------------------------------------*/
- if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
/* SPI in Error Treatment --------------------------------------------------*/
- if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
- if ((itflag & SPI_FLAG_OVR) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
{
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
@@ -2275,14 +2685,14 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
- if ((itflag & SPI_FLAG_MODF) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
/* SPI Frame error interrupt occurred ------------------------------------*/
- if ((itflag & SPI_FLAG_FRE) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
@@ -2305,7 +2715,10 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
@@ -2313,13 +2726,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
@@ -2327,7 +2747,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Tx Transfer completed callback.
+ * @brief Tx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2343,7 +2763,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Rx Transfer completed callback.
+ * @brief Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2359,7 +2779,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Tx and Rx Transfer completed callback.
+ * @brief Tx and Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2375,7 +2795,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Tx Half Transfer completed callback.
+ * @brief Tx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2391,7 +2811,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Rx Half Transfer completed callback.
+ * @brief Rx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2407,7 +2827,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Tx and Rx Half Transfer callback.
+ * @brief Tx and Rx Half Transfer callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2423,7 +2843,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @brief SPI error callback.
+ * @brief SPI error callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2513,17 +2933,17 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
/**
- * @brief DMA SPI transmit process complete callback.
+ * @brief DMA SPI transmit process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
@@ -2552,26 +2972,33 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
- * @brief DMA SPI receive process complete callback.
+ * @brief DMA SPI receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -2587,7 +3014,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
@@ -2595,26 +3022,23 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* Read CRC */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -2643,11 +3067,21 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2658,11 +3092,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -2685,9 +3117,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
else
{
@@ -2697,9 +3127,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(hspi->Instance->DR);
}
}
#endif /* USE_SPI_CRC */
@@ -2728,11 +3156,21 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2743,9 +3181,14 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2756,9 +3199,14 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxHalfCpltCallback(hspi);
+#else
HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2769,9 +3217,14 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2782,14 +3235,19 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2800,11 +3258,16 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2817,7 +3280,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
hspi->hdmatx->XferAbortCallback = NULL;
@@ -2866,7 +3329,11 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2879,7 +3346,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -2929,7 +3396,11 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2943,23 +3414,24 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Receive data in packing mode */
if (hspi->RxXferCount > 1U)
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount -= 2U;
if (hspi->RxXferCount == 1U)
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
}
/* Receive data in 8 Bit mode */
else
{
- *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
}
- /* check end of the reception */
+ /* Check end of the reception */
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
@@ -2990,17 +3462,12 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Regsiter */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
- /* check end of the reception */
+ /* Check end of the reception */
if (hspi->CRCSize == 0U)
{
/* Disable RXNE and ERR interrupt */
@@ -3032,11 +3499,12 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Transmit data in 8 Bit mode */
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
- /* check the end of the transmission */
+ /* Check the end of the transmission */
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
@@ -3069,7 +3537,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
@@ -3102,14 +3570,8 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- /* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Regsiter */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3164,13 +3626,8 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
@@ -3189,7 +3646,8 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
@@ -3222,13 +3680,8 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Register */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -3245,7 +3698,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
@@ -3278,7 +3731,8 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
if (hspi->TxXferCount == 0U)
@@ -3321,23 +3775,23 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
}
/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
- while ((hspi->Instance->SR & Flag) != State)
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -3373,32 +3827,29 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
}
/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Fifo Fifo to check
- * @param State Fifo state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
- __IO uint8_t tmpreg;
-
while ((hspi->Instance->SR & Fifo) != State)
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
}
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -3439,7 +3890,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
* the configuration information for SPI module.
* @param Timeout Timeout duration
* @param Tickstart tick start value
- * @retval None.
+ * @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
@@ -3471,10 +3922,11 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
}
/**
- * @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi SPI handle
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
@@ -3484,18 +3936,21 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
/* Control if the RX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
return HAL_OK;
}
@@ -3507,7 +3962,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -3528,7 +3983,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
hspi->State = HAL_SPI_STATE_READY;
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
@@ -3538,18 +3998,33 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
else
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
@@ -3580,18 +4055,33 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
@@ -3606,7 +4096,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3629,11 +4119,21 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
hspi->State = HAL_SPI_STATE_READY;
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
@@ -3645,24 +4145,27 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
*/
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ __IO uint32_t count;
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do
{
- if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY)
+ if (count == 0U)
{
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
}
+ count--;
}
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@@ -3687,21 +4190,24 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
*/
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ __IO uint32_t count;
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+ /* Disable TXEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ /* Check TXEIE is disabled */
+ do
{
- if ((HAL_GetTick() - tickstart) >= HAL_MAX_DELAY)
+ if (count == 0U)
{
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
}
+ count--;
}
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
@@ -3717,6 +4223,36 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
+ /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
hspi->State = HAL_SPI_STATE_ABORT;
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi_ex.c
new file mode 100644
index 0000000000000000000000000000000000000000..d34cb45e9e310abf314d40069eb0dcacdc829c34
--- /dev/null
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_spi_ex.c
@@ -0,0 +1,115 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0U;
+ while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if (count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sram.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sram.c
index fa31f4c72b268f06ff10295b6614ba265e1837cd..07f9c57a51a400bc3bef5549fd0f7f397119b6ff 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sram.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_sram.c
@@ -58,33 +58,56 @@
(#) You can continuously monitor the SRAM device HAL state by calling the function
HAL_SRAM_GetState()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
+ and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
+ or @ref HAL_SRAM_Init function.
+
+ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -146,8 +169,21 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if(hsram->MspInitCallback == NULL)
+ {
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ }
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Init the low level hardware */
+ hsram->MspInitCallback(hsram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
+#endif
}
/* Initialize SRAM control Interface */
@@ -171,10 +207,20 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
* the configuration information for SRAM module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if(hsram->MspDeInitCallback == NULL)
+ {
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsram->MspDeInitCallback(hsram);
+#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
+#endif
/* Configure the SRAM registers with their reset values */
FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
@@ -571,6 +617,181 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
return HAL_OK;
}
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SRAM Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SRAM Callback
+ * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(state == HAL_SRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Register a User SRAM Callback for DMA transfers
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim.c
index 44c637292b2afdf4ac051e2c9a2c6fd3acc508f0..46809f4c8cb1474f4396abe2a01c11b7e53c2056 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim.c
@@ -5,30 +5,30 @@
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
* + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
@verbatim
==============================================================================
##### TIMER Generic features #####
@@ -42,12 +42,15 @@
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
+ depending on the selected feature:
(++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
@@ -59,7 +62,7 @@
(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -68,17 +71,17 @@
any start function.
(#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
@@ -108,74 +111,66 @@
and the Callback ID.
These functions allow to register/unregister following callbacks:
- (+) Base_MspInitCallback : TIM Base Msp Init Callback.
- (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
- (+) IC_MspInitCallback : TIM IC Msp Init Callback.
- (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
- (+) OC_MspInitCallback : TIM OC Msp Init Callback.
- (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
- (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
- (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
- (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
- (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
- (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
- (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
- (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
- (+) TriggerCallback : TIM Trigger Callback.
- (+) IC_CaptureCallback : TIM Input Capture Callback.
- (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
- (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
- (+) ErrorCallback : TIM Error Callback.
- (+) CommutationCallback : TIM Commutation Callback.
- (+) BreakCallback : TIM Break Callback.
-
- By default, after the Init and when the state is HAL_TIM_STATE_RESET
- all interrupt callbacks are set to the corresponding weak functions:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+ (+) Break2Callback : TIM Break2 Callback.
+
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
- functionalities in the Init/DeInit only when these callbacks are null
- (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in HAL_TIM_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
- When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -198,35 +193,40 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
* @{
*/
-/* Private function prototypes -----------------------------------------------*/
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
-
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
*
@verbatim
@@ -249,15 +249,18 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/
/**
* @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -268,16 +271,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->Base_MspInitCallback == NULL)
+ if (htim->Base_MspInitCallback == NULL)
{
htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
}
@@ -288,22 +291,22 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
HAL_TIM_Base_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -317,7 +320,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->Base_MspDeInitCallback == NULL)
+ if (htim->Base_MspDeInitCallback == NULL)
{
htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
}
@@ -339,8 +342,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Base MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -348,15 +350,14 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -364,30 +365,36 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
}
+
/**
* @brief Starts the TIM Base generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -395,8 +402,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -405,13 +411,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -419,20 +425,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -440,8 +451,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -460,24 +470,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0 ) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -486,20 +497,33 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Set the DMA Period elapsed callback */
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -507,8 +531,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -519,6 +542,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -533,38 +558,41 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
*
@verbatim
==============================================================================
- ##### Time Output Compare functions #####
+ ##### TIM Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
- (+) Start the Time Output Compare.
- (+) Stop the Time Output Compare.
- (+) Start the Time Output Compare and enable interrupt.
- (+) Stop the Time Output Compare and disable interrupt.
- (+) Start the Time Output Compare and enable DMA transfer.
- (+) Stop the Time Output Compare and disable DMA transfer.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -575,18 +603,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->OC_MspInitCallback == NULL)
+ if (htim->OC_MspInitCallback == NULL)
{
- htim->OC_MspInitCallback = HAL_TIM_OC_MspDeInit;
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OC_MspInitCallback(htim);
@@ -595,22 +623,22 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
HAL_TIM_OC_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -618,13 +646,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->OC_MspDeInitCallback == NULL)
+ if (htim->OC_MspDeInitCallback == NULL)
{
htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
}
@@ -646,8 +674,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -655,15 +682,14 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -671,39 +697,46 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -711,14 +744,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -729,7 +763,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -744,9 +778,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -756,6 +789,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -765,45 +800,49 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -811,9 +850,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -832,38 +870,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -878,9 +916,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -892,16 +929,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -910,87 +949,110 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -998,9 +1060,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1019,38 +1080,42 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1070,38 +1135,41 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
*
@verbatim
==============================================================================
- ##### Time PWM functions #####
+ ##### TIM PWM functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
+ (+) Initialize and configure the TIM PWM.
(+) De-initialize the TIM PWM.
- (+) Start the Time PWM.
- (+) Stop the Time PWM.
- (+) Start the Time PWM and enable interrupt.
- (+) Stop the Time PWM and disable interrupt.
- (+) Start the Time PWM and enable DMA transfer.
- (+) Stop the Time PWM and disable DMA transfer.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1112,16 +1180,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->PWM_MspInitCallback == NULL)
+ if (htim->PWM_MspInitCallback == NULL)
{
htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
}
@@ -1132,22 +1200,22 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
HAL_TIM_PWM_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1161,7 +1229,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->PWM_MspDeInitCallback == NULL)
+ if (htim->PWM_MspDeInitCallback == NULL)
{
htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
}
@@ -1183,8 +1251,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1192,15 +1259,14 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1208,39 +1274,46 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the PWM signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1248,14 +1321,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the PWM signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1266,7 +1340,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1284,9 +1358,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1296,6 +1369,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1305,45 +1379,49 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1351,9 +1429,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1361,7 +1438,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1372,38 +1449,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1418,9 +1495,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1432,16 +1508,18 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1450,87 +1528,109 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1538,9 +1638,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1559,38 +1658,42 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1610,38 +1713,41 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
*
@verbatim
==============================================================================
- ##### Time Input Capture functions #####
+ ##### TIM Input Capture functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
- (+) Start the Time Input Capture.
- (+) Stop the Time Input Capture.
- (+) Start the Time Input Capture and enable interrupt.
- (+) Stop the Time Input Capture and disable interrupt.
- (+) Start the Time Input Capture and enable DMA transfer.
- (+) Stop the Time Input Capture and disable DMA transfer.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1652,16 +1758,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->IC_MspInitCallback == NULL)
+ if (htim->IC_MspInitCallback == NULL)
{
htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
}
@@ -1674,21 +1780,20 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1702,7 +1807,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->IC_MspDeInitCallback == NULL)
+ if (htim->IC_MspDeInitCallback == NULL)
{
htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
}
@@ -1723,9 +1828,8 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
}
/**
- * @brief Initializes the TIM INput Capture MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1733,15 +1837,14 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1749,16 +1852,15 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Input Capture measurement.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1766,16 +1868,22 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1783,9 +1891,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1810,9 +1917,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1820,8 +1926,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1831,38 +1939,42 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1870,9 +1982,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1891,32 +2002,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -1930,10 +2041,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
}
/**
- * @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1945,17 +2055,19 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0 ) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1964,92 +2076,111 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2069,32 +2200,36 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -2113,32 +2248,35 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
*
@verbatim
==============================================================================
- ##### Time One Pulse functions #####
+ ##### TIM One Pulse functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
- (+) Start the Time One Pulse.
- (+) Stop the Time One Pulse.
- (+) Start the Time One Pulse and enable interrupt.
- (+) Stop the Time One Pulse and disable interrupt.
- (+) Start the Time One Pulse and enable DMA transfer.
- (+) Stop the Time One Pulse and disable DMA transfer.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
@@ -2148,7 +2286,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -2160,21 +2298,21 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->OnePulse_MspDeInitCallback == NULL)
+ if (htim->OnePulse_MspInitCallback == NULL)
{
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspInit;
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->OnePulse_MspDeInitCallback(htim);
+ htim->OnePulse_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
@@ -2182,7 +2320,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2194,15 +2332,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
htim->Instance->CR1 |= OnePulseMode;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -2216,7 +2353,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->OnePulse_MspDeInitCallback == NULL)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
{
htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
}
@@ -2238,8 +2375,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2247,15 +2383,14 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2263,16 +2398,15 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2295,7 +2429,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2307,9 +2441,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be disable.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2329,7 +2462,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -2344,9 +2477,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2354,6 +2486,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2363,9 +2498,6 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -2375,7 +2507,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2387,9 +2519,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2414,14 +2545,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
@@ -2431,51 +2562,57 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
*
@verbatim
==============================================================================
- ##### Time Encoder functions #####
+ ##### TIM Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
- (+) Start the Time Encoder.
- (+) Stop the Time Encoder.
- (+) Start the Time Encoder and enable interrupt.
- (+) Stop the Time Encoder and disable interrupt.
- (+) Start the Time Encoder and enable DMA transfer.
- (+) Stop the Time Encoder and disable DMA transfer.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
@endverbatim
* @{
*/
/**
- * @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2486,16 +2623,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- /* Reset interrupt callbacks to legacy week callbacks */
+ /* Reset interrupt callbacks to legacy weak callbacks */
TIM_ResetCallback(htim);
- if(htim->Encoder_MspInitCallback == NULL)
+ if (htim->Encoder_MspInitCallback == NULL)
{
htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
}
@@ -2508,10 +2645,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2530,18 +2667,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
- tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
@@ -2553,15 +2690,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
htim->Instance->CCER = tmpccer;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
+
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2575,7 +2712,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->Encoder_MspDeInitCallback == NULL)
+ if (htim->Encoder_MspDeInitCallback == NULL)
{
htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
}
@@ -2597,8 +2734,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2606,15 +2742,14 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2622,16 +2757,15 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2651,16 +2785,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
}
/* Enable the Peripheral */
@@ -2672,9 +2808,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2684,9 +2819,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1 and 2
+ /* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
@@ -2695,18 +2830,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
}
}
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -2716,9 +2854,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2740,19 +2877,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
}
@@ -2765,9 +2904,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2781,19 +2919,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
else
{
@@ -2817,9 +2955,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2834,13 +2971,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -2849,20 +2986,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
@@ -2871,19 +3015,22 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
@@ -2892,30 +3039,37 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_ALL:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the Peripheral */
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
@@ -2926,11 +3080,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Return function status */
return HAL_OK;
@@ -2938,9 +3092,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2954,19 +3107,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
else
{
@@ -2976,6 +3131,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
/* Disable the Peripheral */
@@ -2992,7 +3149,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
+ * @brief TIM IRQ handler management
*
@verbatim
==============================================================================
@@ -3006,23 +3163,22 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
/* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
@@ -3046,14 +3202,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
@@ -3076,14 +3232,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
@@ -3106,14 +3262,14 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
@@ -3136,9 +3292,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3149,9 +3305,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3159,28 +3315,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
#else
HAL_TIMEx_BreakCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
}
}
-
- /* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ /* TIM Break2 input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
+ htim->Break2Callback(htim);
#else
- HAL_TIMEx_BreakCallback(htim);
+ HAL_TIMEx_Break2Callback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
-
/* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3191,15 +3344,15 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
- HAL_TIMEx_CommutationCallback(htim);
+ HAL_TIMEx_CommutCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
@@ -3209,8 +3362,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
*
@verbatim
==============================================================================
@@ -3218,11 +3371,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
==============================================================================
[..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
@endverbatim
* @{
@@ -3231,25 +3384,28 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channels to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- /* Check input state */
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3258,39 +3414,68 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
default:
- break;
+ break;
}
+
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -3301,10 +3486,9 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM IC handle
* @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3312,7 +3496,7 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -3321,6 +3505,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3329,9 +3514,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
{
/* TI1 Configuration */
TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -3353,7 +3538,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
/* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
}
else if (Channel == TIM_CHANNEL_3)
{
@@ -3361,9 +3546,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC3PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
@@ -3377,15 +3562,15 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC4PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
htim->State = HAL_TIM_STATE_READY;
@@ -3398,34 +3583,40 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channels to be configured
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
- __HAL_LOCK(htim);
-
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
htim->State = HAL_TIM_STATE_BUSY;
switch (Channel)
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
@@ -3435,12 +3626,14 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
@@ -3449,42 +3642,80 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
case TIM_CHANNEL_3:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 6 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3497,20 +3728,19 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM Channels to be enabled.
+ * @param OutputChannel TIM output channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM Channels to be enabled.
+ * @param InputChannel TIM input Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@@ -3518,8 +3748,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
- if(OutputChannel != InputChannel)
+ if (OutputChannel != InputChannel)
{
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3539,18 +3770,19 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
}
- break;
default:
- break;
+ break;
}
+
switch (InputChannel)
{
case TIM_CHANNEL_1:
@@ -3558,7 +3790,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ sConfig->ICSelection, sConfig->ICFilter);
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -3570,14 +3802,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
}
- break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ sConfig->ICSelection, sConfig->ICFilter);
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
@@ -3589,11 +3821,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3610,10 +3842,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
- * This parameters can be on of the following values:
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
@@ -3632,9 +3863,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources.
- * This parameters can be on of the following values:
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1 (*)
+ * @arg TIM_DMABASE_AF2 (*)
+ * (*) value not defined in all devices
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3644,11 +3881,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
- * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength)
+ uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -3656,13 +3894,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3671,102 +3909,134 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -3774,71 +4044,73 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ /* Abort the DMA transfer (at least disable the DMA stream) */
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
- * This parameters can be on of the following values:
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
@@ -3857,9 +4129,15 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources.
- * This parameters can be on of the following values:
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1 (*)
+ * @arg TIM_DMABASE_AF2 (*)
+ * (*) value not defined in all devices
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3869,7 +4147,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
- * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3881,13 +4160,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3896,98 +4175,130 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture/compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@@ -4000,69 +4311,71 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Stop the DMA burst reading
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ /* Abort the DMA transfer (at least disable the DMA stream) */
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @brief Generate a software event
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param EventSource specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
@@ -4074,8 +4387,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+ * only for timer instances supporting break input(s).
* @retval HAL status
*/
@@ -4105,23 +4420,25 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
/**
* @brief Configures the OCRef clear feature
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel.
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
/* Process Locked */
@@ -4129,81 +4446,129 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C
htim->State = HAL_TIM_STATE_BUSY;
- if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+ switch (sClearInputConfig->ClearInputSource)
{
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ break;
+ }
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
+ default:
+ break;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
}
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
}
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
}
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
}
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -4215,15 +4580,14 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C
/**
* @brief Configures the clock source to be used
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
@@ -4244,38 +4608,41 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_INTERNAL:
{
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ break;
}
- break;
case TIM_CLOCKSOURCE_ETRMODE1:
{
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+
/* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
+ break;
}
- break;
case TIM_CLOCKSOURCE_ETRMODE2:
{
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
@@ -4285,11 +4652,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
}
- break;
case TIM_CLOCKSOURCE_TI1:
{
+ /* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
@@ -4297,65 +4665,58 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_TI2:
{
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
- /* Check TI1 input conditioning related parameters */
+ /* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_TI1ED:
{
+ /* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_ITR0:
- {
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
- }
- break;
case TIM_CLOCKSOURCE_ITR1:
- {
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
case TIM_CLOCKSOURCE_ITR2:
- {
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
case TIM_CLOCKSOURCE_ITR3:
{
+ /* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -4367,11 +4728,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param TI1_Selection Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
* pins are connected to the TI1 input (XOR combination)
@@ -4379,7 +4739,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
@@ -4402,20 +4762,15 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
/**
* @brief Configures the TIM in Slave mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
-
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
@@ -4425,121 +4780,18 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
htim->State = HAL_TIM_STATE_BUSY;
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
- }
- break;
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
- default:
- break;
- }
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
htim->State = HAL_TIM_STATE_READY;
@@ -4553,12 +4805,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
* @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4569,7 +4821,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY;
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
@@ -4586,9 +4843,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4598,9 +4854,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpreg = 0;
-
- __HAL_LOCK(htim);
+ uint32_t tmpreg = 0U;
switch (Channel)
{
@@ -4610,7 +4864,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
+ tmpreg = htim->Instance->CCR1;
break;
}
@@ -4620,7 +4874,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
+ tmpreg = htim->Instance->CCR2;
break;
}
@@ -4631,7 +4885,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
+ tmpreg = htim->Instance->CCR3;
break;
}
@@ -4642,16 +4896,15 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
+ tmpreg = htim->Instance->CCR4;
break;
}
default:
- break;
+ break;
}
- __HAL_UNLOCK(htim);
return tmpreg;
}
@@ -4668,22 +4921,19 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
==============================================================================
[..]
This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
- (+) Timer_RegisterCallback
- (+) Timer_UnRegisterCallback
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
@endverbatim
* @{
*/
/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4691,15 +4941,29 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
+}
+/**
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+ */
}
+
/**
- * @brief Output Compare callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4707,14 +4971,14 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
+
/**
- * @brief Input Capture callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
@@ -4722,15 +4986,29 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
@@ -4738,15 +5016,29 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
@@ -4754,15 +5046,29 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
/**
- * @brief Timer error callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
@@ -4770,7 +5076,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
}
@@ -4796,189 +5102,219 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @param pCallback pointer to the callback function
- * @retval status
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
*/
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(htim);
- if(htim->State == HAL_TIM_STATE_READY)
+ if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
{
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = pCallback;
- break;
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
- case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = pCallback;
- break;
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
- case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = pCallback;
- break;
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = pCallback;
- break;
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = pCallback;
- break;
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
- case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = pCallback;
- break;
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
- case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = pCallback;
- break;
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
- case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = pCallback;
- break;
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(htim->State == HAL_TIM_STATE_RESET)
+ else if (htim->State == HAL_TIM_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = pCallback;
- break;
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = pCallback;
- break;
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -5014,14 +5350,20 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
- * @retval status
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @retval status
*/
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
{
@@ -5030,168 +5372,192 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
/* Process locked */
__HAL_LOCK(htim);
- if(htim->State == HAL_TIM_STATE_READY)
+ if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
{
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
- break;
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
- break;
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
- break;
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
- break;
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
- break;
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
- break;
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
- break;
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
- break;
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
- break;
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
- break;
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
- break;
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
- break;
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
- break;
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
- break;
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
- case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
- break;
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ break;
- case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
- break;
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ break;
- case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
- break;
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
- case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
- break;
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ break;
- case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
- break;
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ break;
- case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
- break;
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ break;
- case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */
- break;
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ break;
- case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
- break;
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(htim->State == HAL_TIM_STATE_RESET)
+ else if (htim->State == HAL_TIM_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
- break;
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
- case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
- break;
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
- case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
- break;
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
- case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
- break;
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
- case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
- break;
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
- case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
- break;
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
- case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
- break;
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
- case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
- break;
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
- case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
- break;
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
- case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
- break;
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
- case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
- break;
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
- case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
- break;
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
- case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
- break;
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
- case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
- break;
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -5211,14 +5577,14 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
- [..]
+ [..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@@ -5227,9 +5593,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
*/
/**
- * @brief Return the TIM Base state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
@@ -5238,9 +5603,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
}
/**
- * @brief Return the TIM OC state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -5249,9 +5613,8 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
}
/**
- * @brief Return the TIM PWM state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
@@ -5259,10 +5622,9 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
return htim->State;
}
-/**
- * @brief Return the TIM Input Capture state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -5271,9 +5633,8 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
}
/**
- * @brief Return the TIM One Pulse Mode state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -5282,9 +5643,8 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
}
/**
- * @brief Return the TIM Encoder Mode state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
@@ -5296,19 +5656,27 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
* @}
*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+
/**
* @brief TIM DMA error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
- htim->State= HAL_TIM_STATE_READY;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->ErrorCallback(htim);
+ htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -5316,15 +5684,14 @@ void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
@@ -5342,25 +5709,71 @@ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
+
/**
* @brief TIM DMA Capture complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
@@ -5378,26 +5791,72 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
+
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
- htim->State= HAL_TIM_STATE_READY;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -5405,44 +5864,80 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
/**
* @brief TIM DMA Trigger callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
- htim->State= HAL_TIM_STATE_READY;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
- #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief Time Base configuration
* @param TIMx TIM peripheral
- * @param Structure pointer on TIM Time Base required parameters
+ * @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- uint32_t tmpcr1 = 0;
+ uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
- if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
tmpcr1 |= Structure->CounterMode;
}
- if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
@@ -5454,34 +5949,34 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
TIMx->CR1 = tmpcr1;
- /* Set the Auto-reload value */
+ /* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
/* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
+ TIMx->PSC = Structure->Prescaler;
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
}
/* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediately */
+ and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
}
/**
- * @brief Time Output Compare 1 configuration
+ * @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
-void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -5489,7 +5984,7 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
@@ -5505,15 +6000,24 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
{
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
@@ -5523,6 +6027,7 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -5537,16 +6042,16 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 2 configuration
+ * @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5554,7 +6059,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
@@ -5564,32 +6069,41 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
tmpccmrx &= ~TIM_CCMR1_CC2S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
+ tmpccer |= (OC_Config->OCPolarity << 4U);
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
tmpcr2 &= ~TIM_CR2_OIS2N;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -5604,16 +6118,16 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 3 configuration
+ * @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
-void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5621,7 +6135,7 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
@@ -5635,27 +6149,35 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8);
+ tmpccer |= (OC_Config->OCPolarity << 8U);
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8);
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
tmpcr2 &= ~TIM_CR2_OIS3N;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4);
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -5670,16 +6192,16 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 4 configuration
+ * @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
-void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5687,7 +6209,7 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
@@ -5697,22 +6219,25 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
tmpccmrx &= ~TIM_CCMR2_CC4S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12);
+ tmpccer |= (OC_Config->OCPolarity << 12U);
- /*if((TIMx == TIM1) || (TIMx == TIM8))*/
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
+ /* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
+
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6);
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -5727,20 +6252,126 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 4 configuration
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sSlaveConfig The slave configuration structure
+ * @brief Timer Output Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
* @retval None
*/
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
- /* Get the TIMx SMCR register value */
+ /* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* Reset the Trigger Selection Bits */
@@ -5759,10 +6390,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
{
- case TIM_TS_ETRF:
+ case TIM_TS_ETRF:
{
/* Check the parameters */
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
@@ -5771,16 +6402,20 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
sSlaveConfig->TriggerPrescaler,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI1F_ED:
+ case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim->Instance->CCER;
htim->Instance->CCER &= ~TIM_CCER_CC1E;
@@ -5788,16 +6423,15 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
htim->Instance->CCER = tmpccer;
-
+ break;
}
- break;
- case TIM_TS_TI1FP1:
+ case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -5808,10 +6442,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_TI1_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI2FP2:
+ case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -5820,57 +6454,40 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_ITR3:
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
}
- break;
- default:
- break;
+ default:
+ break;
}
+ return HAL_OK;
}
/**
* @brief Configure the TI1 as Input.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5881,8 +6498,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -5890,7 +6507,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
tmpccer = TIMx->CCER;
/* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
{
tmpccmr1 &= ~TIM_CCMR1_CC1S;
tmpccmr1 |= TIM_ICSelection;
@@ -5902,7 +6519,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5916,19 +6533,19 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
@@ -5937,7 +6554,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
+ tmpccmr1 |= (TIM_ICFilter << 4U);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5951,16 +6568,16 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/**
* @brief Configure the TI2 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5969,10 +6586,10 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5981,15 +6598,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8);
+ tmpccmr1 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -5999,19 +6616,19 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the Polarity and Filter for TI2.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
-uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -6020,11 +6637,11 @@ uint32_t tmpccmr1 = 0;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
+ tmpccmr1 |= (TIM_ICFilter << 12U);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
+ tmpccer |= (TIM_ICPolarity << 4U);
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -6034,16 +6651,16 @@ uint32_t tmpccmr1 = 0;
/**
* @brief Configure the TI3 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -6052,10 +6669,10 @@ uint32_t tmpccmr1 = 0;
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -6068,11 +6685,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -6082,28 +6699,28 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the TI4 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
- * @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
+ * @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -6112,15 +6729,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8);
+ tmpccmr2 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -6130,7 +6747,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param TIM_ITRx The Input Trigger source.
+ * @param InputTriggerSource The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -6142,41 +6759,40 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
- uint32_t tmpsmcr = 0;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
+ uint32_t tmpsmcr;
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
* This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
* @param TIM_ExtTRGPolarity The external Trigger Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
* @param ExtTRGFilter External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
@@ -6184,7 +6800,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
@@ -6195,34 +6811,36 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
- uint32_t tmp = 0;
+ uint32_t tmp;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
- tmp = TIM_CCER_CC1E << Channel;
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
- * @brief Reset interrupt callbacks to the legacy week callbacks.
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
* @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
@@ -6230,16 +6848,23 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
void TIM_ResetCallback(TIM_HandleTypeDef *htim)
{
/* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
- htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim_ex.c
index 67bb4a70a7e285328c0c37d4fea64993ab2fdbc7..8ec1d0fd2c42931a28c042cef914ec3f6c0f8061 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim_ex.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_tim_ex.c
@@ -4,22 +4,20 @@
* @author MCD Application Team
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Timer extension peripheral:
+ * functionalities of the Timer Extended peripheral:
* + Time Hall Sensor Interface Initialization
* + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
+ * + Time Complementary signal break and dead time configuration
* + Time Master and Slave synchronization configuration
* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
- * + Time OCRef clear configuration
* + Timer remapping capabilities configuration
@verbatim
==============================================================================
##### TIMER Extended features #####
==============================================================================
[..]
- The Timer Extension features include:
+ The Timer Extended features include:
(#) Complementary outputs with programmable dead-time for :
- (++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
@@ -29,21 +27,18 @@
(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
positioning purposes
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -51,51 +46,34 @@
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
- (#) Activate the TIM peripheral using one of the start functions:
+ (#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -113,29 +91,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define BDTR_BKF_SHIFT (16)
-#define BDTR_BK2F_SHIFT (20)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions
- * @{
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
+ * @brief Timer Hall Sensor functions
+ *
@verbatim
==============================================================================
##### Timer Hall Sensor functions #####
@@ -155,23 +123,23 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
* @{
*/
/**
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
{
TIM_OC_InitTypeDef OC_Config;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
@@ -179,7 +147,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
@@ -188,7 +156,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
/* Reset interrupt callbacks to legacy week callbacks */
TIM_ResetCallback(htim);
- if(htim->HallSensor_MspInitCallback == NULL)
+ if (htim->HallSensor_MspInitCallback == NULL)
{
htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
}
@@ -201,7 +169,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -242,15 +210,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -264,7 +231,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE(htim);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- if(htim->HallSensor_MspDeInitCallback == NULL)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
{
htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
}
@@ -286,8 +253,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -295,15 +261,14 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -311,28 +276,33 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -340,17 +310,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
@@ -362,24 +331,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -387,17 +361,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
@@ -412,24 +385,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @param pData The destination Buffer address.
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -438,23 +412,34 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ else
+ {
+ /* nothing to do */
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ /* Set the DMA Input Capture 1 Callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream for Capture 1*/
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -462,23 +447,23 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 event */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -491,8 +476,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
*/
/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
+ * @brief Timer Complementary Output Compare functions
+ *
@verbatim
==============================================================================
##### Timer Complementary Output Compare functions #####
@@ -513,9 +498,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -524,17 +508,23 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -543,9 +533,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -557,11 +546,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Disable the Capture compare channel N */
+ /* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -573,9 +562,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -584,6 +572,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -593,32 +583,26 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
@@ -628,10 +612,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -640,9 +628,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -651,8 +638,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
-
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -662,32 +648,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel N */
@@ -695,7 +674,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -713,9 +692,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -726,16 +704,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -744,74 +724,72 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel N */
@@ -820,8 +798,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -830,9 +812,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -850,32 +831,28 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel N */
@@ -899,8 +876,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
+ * @brief Timer Complementary PWM functions
+ *
@verbatim
==============================================================================
##### Timer Complementary PWM functions #####
@@ -930,9 +907,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -941,6 +917,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -950,8 +928,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -959,9 +941,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -989,9 +970,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1000,6 +980,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1009,32 +991,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
@@ -1046,8 +1021,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1056,18 +1035,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1078,32 +1056,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
@@ -1111,7 +1082,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1129,9 +1100,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1142,16 +1112,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1160,84 +1132,85 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1246,9 +1219,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1266,39 +1238,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1315,8 +1283,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
+ * @brief Timer Complementary One Pulse functions
+ *
@verbatim
==============================================================================
##### Timer Complementary One Pulse functions #####
@@ -1333,18 +1301,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * @brief Starts the TIM One Pulse signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
+{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1361,9 +1328,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be disabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1376,10 +1342,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1391,9 +1357,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1418,14 +1383,13 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Return function status */
return HAL_OK;
- }
+}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be disabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1449,7 +1413,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
@@ -1460,24 +1424,26 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure the DMA Burst Mode.
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Enable or disable channel grouping.
@endverbatim
* @{
*/
+
/**
* @brief Configure the TIM commutation event sequence.
* @note This function is mandatory to use the commutation event in order to
@@ -1486,25 +1452,24 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1523,6 +1488,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -1536,25 +1507,24 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1573,7 +1543,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
- /* Enable the Commutation Interrupt Request */
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
__HAL_UNLOCK(htim);
@@ -1589,26 +1562,25 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1629,9 +1601,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@@ -1643,14 +1619,14 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM in master mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
{
uint32_t tmpcr2;
uint32_t tmpsmcr;
@@ -1663,7 +1639,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Check input state */
__HAL_LOCK(htim);
- /* Get the TIMx CR2 register value */
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
/* Get the TIMx SMCR register value */
@@ -1697,24 +1676,27 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
- uint32_t tmpbdtr = 0;
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ uint32_t tmpbdtr = 0U;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@@ -1726,15 +1708,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
- assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
- assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
- assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Check input state */
__HAL_LOCK(htim);
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
@@ -1743,23 +1723,21 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
+ /* Check the parameters */
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
}
-
-
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
@@ -1767,7 +1745,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
return HAL_OK;
}
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
/**
* @brief Configures the break input source.
* @param htim TIM handle.
@@ -1783,101 +1762,111 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{
- uint32_t tmporx = 0;
- uint32_t bkin_enable_mask = 0;
- uint32_t bkin_polarity_mask = 0;
- uint32_t bkin_enable_bitpos = 0;
- uint32_t bkin_polarity_bitpos = 0;
+ uint32_t tmporx;
+ uint32_t bkin_enable_mask = 0U;
+ uint32_t bkin_polarity_mask = 0U;
+ uint32_t bkin_enable_bitpos = 0U;
+ uint32_t bkin_polarity_bitpos = 0U;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+#if defined(DFSDM1_Channel0)
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
{
assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
}
+#else
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+#endif /* DFSDM1_Channel0 */
/* Check input state */
__HAL_LOCK(htim);
- switch(sBreakInputConfig->Source)
+ switch (sBreakInputConfig->Source)
{
- case TIM_BREAKINPUTSOURCE_BKIN:
+ case TIM_BREAKINPUTSOURCE_BKIN:
{
bkin_enable_mask = TIM1_AF1_BKINE;
bkin_enable_bitpos = 0;
bkin_polarity_mask = TIM1_AF1_BKINP;
bkin_polarity_bitpos = 9;
+ break;
}
- break;
- case TIM_BREAKINPUTSOURCE_DFSDM1:
+ case TIM_BREAKINPUTSOURCE_DFSDM1:
{
bkin_enable_mask = TIM1_AF1_BKDF1BKE;
bkin_enable_bitpos = 8;
+ break;
}
- break;
- default:
- break;
+ default:
+ break;
}
- switch(BreakInput)
+ switch (BreakInput)
{
case TIM_BREAKINPUT_BRK:
+ {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+#if defined(DFSDM1_Channel0)
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* DFSDM1_Channel0 */
{
- /* Get the TIMx_AF1 register value */
- tmporx = htim->Instance->AF1;
-
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
- if(sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
- /* Set TIMx_AF1 */
- htim->Instance->AF1 = tmporx;
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
}
- break;
- case TIM_BREAKINPUT_BRK2:
- {
- /* Get the TIMx_AF2 register value */
- tmporx = htim->Instance->AF2;
- /* Enable the break input */
- tmporx &= ~bkin_enable_mask;
- tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
- if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
- /* Set TIMx_AF2 */
- htim->Instance->AF2 = tmporx;
+ /* Set the break input polarity */
+#if defined(DFSDM1_Channel0)
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+#endif /* DFSDM1_Channel0 */
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
}
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ break;
+ }
+ default:
break;
- default:
- break;
}
__HAL_UNLOCK(htim);
return HAL_OK;
}
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /*TIM_BREAK_INPUT_SUPPORT */
/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Remap specifies the TIM input remapping source.
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
* @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
@@ -1892,6 +1881,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
* (HSE divided by a programmable prescaler)
* @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@@ -1915,7 +1905,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
/**
* @brief Group channel 5 and channel 1, 2 or 3
* @param htim TIM handle.
- * @param OCRef specifies the reference signal(s) the OC5REF is combined with.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
* This parameter can be any combination of the following values:
* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
@@ -1923,11 +1913,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
* TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
{
/* Check parameters */
assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_GROUPCH5(OCRef));
+ assert_param(IS_TIM_GROUPCH5(Channels));
/* Process Locked */
__HAL_LOCK(htim);
@@ -1935,30 +1925,32 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe
htim->State = HAL_TIM_STATE_BUSY;
/* Clear GC5Cx bit fields */
- htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
/* Set GC5Cx bit fields */
- htim->Instance->CCR5 |= OCRef;
+ htim->Instance->CCR5 |= Channels;
+ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
+
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
- *
+ *
@verbatim
==============================================================================
- ##### Extension Callbacks functions #####
+ ##### Extended Callbacks functions #####
==============================================================================
[..]
- This section provides Extension TIM callback functions:
+ This section provides Extended TIM callback functions:
(+) Timer Commutation callback
(+) Timer Break callback
@@ -1967,25 +1959,37 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe
*/
/**
- * @brief Hall commutation changed callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Break detection callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
@@ -1993,21 +1997,35 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- *
+ * @brief Extended Peripheral State functions
+ *
@verbatim
==============================================================================
- ##### Extension Peripheral State functions #####
+ ##### Extended Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
@@ -2018,9 +2036,8 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
*/
/**
- * @brief Return the TIM Hall Sensor interface state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -2032,561 +2049,81 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* @}
*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+ * @{
+ */
+
/**
* @brief TIM DMA Commutation callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
- HAL_TIMEx_CommutationCallback(htim);
+ HAL_TIMEx_CommutCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-/**
- * @}
- */
/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @arg TIM_Channel_5: TIM Channel 5
- * @arg TIM_Channel_6: TIM Channel 6
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- uint32_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
- }
- break;
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- case TIM_CHANNEL_5:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
- }
- }
- break;
- case TIM_CHANNEL_6:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
- }
- }
- break;
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM Output Compare handle
- * @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to configure
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 5 in Output Compare */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the TIM Channel 6 in Output Compare */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- default:
- break;
- }
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM PWM handle
- * @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be configured
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef* sConfig,
- uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
- }
- break;
-
- case TIM_CHANNEL_5:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_6:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
* @param ChannelNState specifies the TIM Channel CCxNE bit new state.
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
{
- uint32_t tmp = 0;
+ uint32_t tmp;
- /* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1NE << Channel;
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
+ TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-/**
- * @brief Timer Output Compare 5 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
-
/**
- * @brief Timer Output Compare 6 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
+ * @}
*/
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
#endif /* HAL_TIM_MODULE_ENABLED */
/**
@@ -2596,4 +2133,5 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @}
*/
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_alarm_template.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_alarm_template.c
index baa2c49ee5134388299e404328f652448be596f9..a7d5dd060516403675de8b5d3283473018169027 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_alarm_template.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_alarm_template.c
@@ -32,29 +32,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_wakeup_template.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_wakeup_template.c
index 55559acb56996a05ba0640e34de1f40f05df1cd8..96b912e366686d9f48af9dd12b8c3f8c6f80cda5 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_wakeup_template.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_rtc_wakeup_template.c
@@ -33,29 +33,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_tim_template.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_tim_template.c
index ea70863778d883b6461ac8204deada543524172c..f7a9879c8171742b36e1be1b764094e07934047e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_tim_template.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_timebase_tim_template.c
@@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart.c
index 150d9e8376705395b506550a88b4e4e6d269ed42..9b09bdb46032d505a02e6b518b2d2cde0ef31e87 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart.c
@@ -4,43 +4,48 @@
* @author MCD Application Team
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
- * + Peripheral State and Errors functions
+ *
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
[..]
The UART HAL driver can be used as follows:
- (#) Declare a UART_HandleTypeDef handle structure.
-
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
(#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) UART pins configuration:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
(+++) Configure these UART pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
and HAL_UART_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+ inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
and HAL_UART_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required
- Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the Init structure.
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
(#) For the UART asynchronous mode, initialize the UART registers by calling
the HAL_UART_Init() API.
@@ -48,105 +53,102 @@
(#) For the UART Half duplex mode, initialize the UART registers by calling
the HAL_HalfDuplex_Init() API.
- (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-
- (#) For the Multi-Processor mode, initialize the UART registers by calling
- the HAL_MultiProcessor_Init() API.
-
- [..]
- (@) The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
- and receive process.
-
- [..]
- (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
- low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
- HAL_UART_MspInit() API.
-
- [..]
- Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_UART_DMAPause()
- (+) Resume the DMA Transfer using HAL_UART_DMAResume()
- (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
- *** UART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in UART HAL driver.
-
- (+) __HAL_UART_ENABLE: Enable the UART peripheral
- (+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag
- (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
- (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-
- [..]
- (@) You can refer to the UART HAL driver header file for more useful macros
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+ or @ref HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -170,12 +172,20 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
@@ -189,9 +199,15 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
/**
* @}
*/
@@ -212,41 +228,71 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
- (+) For the asynchronous mode only these parameters can be configured:
+ (+) For the asynchronous mode the parameters below can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
[..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
- follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
- configuration procedures (details for the procedures are available in reference manual (RM0329)).
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ and UART multiprocessor mode configuration procedures (details for the procedures
+ are available in reference manual).
@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
* @{
*/
/**
- * @brief Initializes the UART mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart uart handle
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
/* Check the parameters */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
@@ -257,13 +303,25 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
assert_param(IS_UART_INSTANCE(huart->Instance));
}
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -296,26 +354,41 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
}
/**
- * @brief Initializes the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart UART handle
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
- if(huart->gState == HAL_UART_STATE_RESET)
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -353,9 +426,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/**
* @brief Initialize the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart UART handle.
- * @param BreakDetectLength specifies the LIN break detection length.
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
* @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
@@ -364,23 +437,46 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
- assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));
- if(huart->gState == HAL_UART_STATE_RESET)
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -422,9 +518,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/**
* @brief Initialize the multiprocessor mode according to the specified
* parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @param Address UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod specifies the UART wakeup method.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
* @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
@@ -432,13 +528,15 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
* is useless and ignored by the initialization function.
* @note If the user resorts to address mark wake up, the address length detection
* is configured by default to 4 bits only. For the UART to be able to
- * manage 6-, 7- or 8-bit long addresses detection
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -446,13 +544,25 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Check the wake up method parameter */
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -495,97 +605,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/**
- * @brief Initialize the RS485 Driver enable feature according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @brief DeInitialize the UART peripheral.
* @param huart UART handle.
- * @param Polarity select the driver enable polarity.
- * This parameter can be one of the following values:
- * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
- * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
- * @param AssertionTime Driver Enable assertion time:
- * 5-bit value defining the time between the activation of the DE (Driver Enable)
- * signal and the beginning of the start bit. It is expressed in sample time
- * units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime Driver Enable deassertion time:
- * 5-bit value defining the time between the end of the last stop bit, in a
- * transmitted message, and the de-activation of the DE (Driver Enable) signal.
- * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
- * oversampling rate).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
-{
- uint32_t temp = 0x0;
-
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the Driver Enable UART instance */
- assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
- /* Check the Driver Enable polarity */
- assert_param(IS_UART_DE_POLARITY(Polarity));
-
- /* Check the Driver Enable assertion time */
- assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
- /* Check the Driver Enable deassertion time */
- assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
- /* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
- /* Set the Driver Enable assertion and deassertion times */
- temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-/**
- * @brief DeInitializes the UART peripheral
- * @param huart uart handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -602,12 +629,21 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->Instance->CR2 = 0x0U;
huart->Instance->CR3 = 0x0U;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
@@ -616,8 +652,8 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
}
/**
- * @brief UART MSP Init
- * @param huart uart handle
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
@@ -631,8 +667,8 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
}
/**
- * @brief UART MSP DeInit
- * @param huart uart handle
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
@@ -645,6 +681,255 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
*/
}
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = pCallback;
+ break;
+
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -680,8 +965,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
(+) HAL_UART_Transmit_IT()
(+) HAL_UART_Receive_IT()
(+) HAL_UART_IRQHandler()
- (+) UART_Transmit_IT()
- (+) UART_Receive_IT()
(#) Non-Blocking mode API's with DMA are :
(+) HAL_UART_Transmit_DMA()
@@ -697,6 +980,29 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
(+) HAL_UART_RxCpltCallback()
(+) HAL_UART_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-@- In the Half duplex communication, it is forbidden to run the transmit
and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
@@ -707,21 +1013,22 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
/**
* @brief Send an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -735,27 +1042,41 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- huart->TxXferSize = Size;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0U)
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (huart->TxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2;
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
}
else
{
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
}
+ huart->TxXferCount--;
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -776,22 +1097,23 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -805,31 +1127,43 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- huart->RxXferSize = Size;
+ huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
uhMask = huart->Mask;
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
/* as long as data have to be received */
- while(huart->RxXferCount > 0U)
+ while (huart->RxXferCount > 0U)
{
- huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2U;
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
}
else
{
- *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
}
+ huart->RxXferCount--;
}
/* At end of Rx process, restore huart->RxState to Ready */
@@ -849,16 +1183,16 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
* @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -866,17 +1200,28 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/* Process Locked */
__HAL_LOCK(huart);
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
+ huart->TxISR = NULL;
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
- /* Enable the UART Transmit Data Register Empty Interrupt */
+ /* Enable the Transmit Data Register Empty interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
@@ -890,16 +1235,16 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
* @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -907,9 +1252,10 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/* Process Locked */
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
huart->RxXferCount = Size;
+ huart->RxISR = NULL;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
@@ -917,13 +1263,23 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
return HAL_OK;
@@ -937,18 +1293,16 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
* @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -956,37 +1310,50 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Process Locked */
__HAL_LOCK(huart);
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
- /* Enable the UART transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
+ /* Enable the UART transmit DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
+ return HAL_ERROR;
+ }
+ }
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
@@ -999,21 +1366,19 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/**
* @brief Receive an amount of data in DMA mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1027,22 +1392,35 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- /* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1071,17 +1449,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
/* Process Locked */
__HAL_LOCK(huart);
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
/* Disable the UART DMA Tx request */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
@@ -1107,15 +1488,15 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
/* Process Locked */
__HAL_LOCK(huart);
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
@@ -1125,12 +1506,8 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- /* If the UART peripheral is still not enabled, enable it */
- if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)
- {
- /* Enable UART peripheral */
- __HAL_UART_ENABLE(huart);
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
return HAL_OK;
}
@@ -1149,31 +1526,52 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
/* Stop UART DMA Tx request if ongoing */
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
UART_EndTxTransfer(huart);
}
/* Stop UART DMA Rx request if ongoing */
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
UART_EndRxTransfer(huart);
@@ -1183,336 +1581,728 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
}
/**
- * @brief This function handles UART interrupt request.
- * @param huart uart handle
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- uint32_t errorflags;
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
{
- UART_Receive_IT(huart);
- return;
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
- /* If some errors occur */
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* UART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
- huart->ErrorCode |= HAL_UART_ERROR_PE;
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
+ }
- /* UART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
- /* UART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
+ /* Reset Handle ErrorCode to No Error */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- UART_Receive_IT(huart);
- }
+ return HAL_OK;
+}
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
{
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
}
}
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_UART_ErrorCallback(huart);
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
}
- return;
+ }
- } /* End if some error occurs */
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
- /* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- UART_Transmit_IT(huart);
- return;
- }
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- UART_EndTransmit_IT(huart);
- return;
- }
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ return HAL_OK;
}
/**
- * @brief This function handles UART Communication Timeout.
- * @param huart UART handle
- * @param Flag specifies the UART flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
- /* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
{
- if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
return HAL_OK;
}
/**
- * @brief DMA UART transmit process complete callback
- * @param hdma DMA handle
- * @retval None
- */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t abortcplt = 1U;
- /* DMA Normal mode*/
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
- {
- huart->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
}
- /* DMA Circular mode */
- else
+ /* DMA Rx Handle is valid */
+ if (huart->hdmarx != NULL)
{
- HAL_UART_TxCpltCallback(huart);
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
}
-}
-/**
- * @brief DMA UART transmit process half complete callback
- * @param hdma DMA handle
- * @retval None
- */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- HAL_UART_TxHalfCpltCallback(huart);
-}
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-/**
- * @brief DMA UART receive process complete callback
- * @param hdma DMA handle
- * @retval None
- */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
- /* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- huart->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- }
- HAL_UART_RxCpltCallback(huart);
-}
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-/**
- * @brief DMA UART receive process half complete callback
- * @param hdma DMA handle
- * @retval None
- */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
- HAL_UART_RxHalfCpltCallback(huart);
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
}
/**
- * @brief DMA UART communication error callback
- * @param hdma DMA handle
- * @retval None
- */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
- /* Stop UART DMA Tx request if ongoing */
- if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+ /* Disable interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- UART_EndTxTransfer(huart);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
- /* Stop UART DMA Rx request if ongoing */
- if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- UART_EndRxTransfer(huart);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
- SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);
- HAL_UART_ErrorCallback(huart);
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
}
/**
- * @brief DMA UART communication abort callback, when call by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
* @retval None
*/
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == 0U)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ ((cr3its & USART_CR3_EIE) != 0U)))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & HAL_UART_ERROR_ORE) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
+ {
+ if (huart->TxISR != NULL)
+ {
+ huart->TxISR(huart);
+ }
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
- HAL_UART_ErrorCallback(huart);
}
/**
- * @brief Tx Transfer completed callbacks
- * @param huart uart handle
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
* @retval None
*/
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param huart UART handle
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
* @retval None
*/
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Transfer completed callbacks
- * @param huart uart handle
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1521,13 +2311,13 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Half Transfer completed callbacks.
- * @param huart UART handle
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1536,147 +2326,586 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief UART error callbacks
- * @param huart uart handle
+ * @brief UART error callback.
+ * @param huart UART handle.
* @retval None
*/
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file
+ the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
/**
- * @brief Send an amount of data in interrupt mode
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT()
- * @param huart UART handle
- * @retval HAL status
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
*/
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
- /* Check that a Tx process is ongoing */
- if (huart->gState == HAL_UART_STATE_BUSY_TX)
- {
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
- if(huart->TxXferCount == 0U)
- {
- /* Disable the UART Transmit Data Register Empty Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
- return HAL_OK;
- }
- else
- {
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- huart->pTxBuffPtr += 2U;
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1, temp2;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv = 0x00000000U;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ tmpreg |= huart->Init.OneBitSampling;
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
- huart->TxXferCount--;
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
- return HAL_OK;
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
}
}
- else
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
{
- return HAL_BUSY;
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
}
}
/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
* @retval HAL status
*/
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ uint32_t tickstart;
- /* Tx process is ended, restore huart->gState to Ready */
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
- HAL_UART_TxCpltCallback(huart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
return HAL_OK;
}
/**
- * @brief Receive an amount of data in interrupt mode
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle
+ * @brief Handle UART Communication Timeout.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
-
- /* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
-
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- huart->pRxBuffPtr +=2;
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- }
-
- if(--huart->RxXferCount == 0)
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
- HAL_UART_RxCpltCallback(huart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- return HAL_OK;
+ return HAL_TIMEOUT;
+ }
}
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
+ return HAL_OK;
}
+
/**
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
@@ -1705,456 +2934,526 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
-}
-/**
- * @}
- */
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+}
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the UART.
- (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
- (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) UART_SetConfig() API configures the UART peripheral
- (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
- (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
- (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
- (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
- (+) HAL_LIN_SendBreak() API transmits the break characters
- (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
- detection length to more than 4 bits for multiprocessor address mark wake up.
-@endverbatim
- * @{
- */
/**
- * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
- * @param huart UART handle
- * @retval HAL status
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- /* Enable USART mute mode by setting the MME bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+ /* DMA Normal mode */
+ if (hdma->Init.Mode != DMA_CIRCULAR)
+ {
+ huart->TxXferCount = 0U;
- huart->gState = HAL_UART_STATE_READY;
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- return (UART_CheckIdleState(huart));
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
- * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
- * as it may not have been in mute mode at this very moment).
- * @param huart uart handle
- * @retval HAL status
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(huart);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable USART mute mode by clearing the MME bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
-
- huart->gState = HAL_UART_STATE_READY;
-
- return (UART_CheckIdleState(huart));
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
+ HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief Enter UART mute mode (means UART actually enters mute mode).
- * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
- * @param huart uart handle
- * @retval HAL status
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
*/
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
-}
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* DMA Normal mode */
+ if (hdma->Init.Mode != DMA_CIRCULAR)
+ {
+ huart->RxXferCount = 0U;
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-/**
- * @brief return the UART state
- * @param huart uart handle
- * @retval HAL state
- */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = huart->gState;
- temp2 = huart->RxState;
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ }
-/**
-* @brief Return the UART error code
-* @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
-* @retval UART Error Code
-*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
- return huart->ErrorCode;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief Configure the UART peripheral
- * @param huart uart handle
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
* @retval None
*/
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- uint32_t tmpreg = 0x00000000U;
- UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
-
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
- MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check UART Over Sampling to set Baud Rate Register */
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- }
- else
- {
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_PCLK2:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
- }
-
- return ret;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
-
/**
- * @brief Configure the UART peripheral advanced features
- * @param huart uart handle
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
* @retval None
*/
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- /* if required, configure TX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- }
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
- /* if required, configure RX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
}
- /* if required, configure data inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
}
- /* if required, configure RX/TX pins swap */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
- /* if required, configure RX overrun detection disabling */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
- /* if required, configure DMA disabling on reception error */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- }
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
- /* if required, configure auto Baud rate detection scheme */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmarx != NULL)
{
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- /* set auto Baudrate detection parameters if detection is enabled */
- if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ if (huart->hdmarx->XferAbortCallback != NULL)
{
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ return;
}
}
- /* if required, configure MSB first on communication line */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- }
-}
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
/**
- * @brief Check the UART Idle State
- * @param huart uart handle
- * @retval HAL status
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
*/
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- uint32_t tickstart = 0U;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ huart->hdmarx->XferAbortCallback = NULL;
- /* Check if the Transmitter is enabled */
- if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmatx != NULL)
{
- /* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ if (huart->hdmatx->XferAbortCallback != NULL)
{
- /* Timeout Occurred */
- return HAL_TIMEOUT;
+ return;
}
}
- /* Initialize the UART State */
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
- return HAL_OK;
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+
/**
- * @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart UART handle
- * @retval HAL status
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
* @retval None
*/
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+ huart->TxXferCount = 0U;
- huart->gState= HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- return HAL_OK;
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart UART handle
- * @retval HAL status
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- /* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+ huart->RxXferCount = 0U;
- huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
- return HAL_OK;
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+/**
+ * @brief TX interrrupt handler for 7 or 8 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ }
+}
/**
- * @brief Transmits break characters.
- * @param huart UART handle
- * @retval HAL status
+ * @brief TX interrrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
+ uint16_t *tmp;
- /* Process Locked */
- __HAL_LOCK(huart);
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
- huart->gState = HAL_UART_STATE_BUSY;
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
- /* Send break characters */
- SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
- return HAL_OK;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection;
- * this API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long).
- * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
- * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
- * @param AddressLength this parameter can be one of the following values:
- * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
- * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
- * @retval HAL status
+ * @retval None
*/
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
- /* Check the address length parameter */
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
- huart->gState = HAL_UART_STATE_BUSY;
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Set the address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
- /* TEACK and/or REACK to check before moving huart->gState to Ready */
- return (UART_CheckIdleState(huart));
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
}
/**
- * @}
+ * @brief RX interrrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
*/
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart_ex.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart_ex.c
new file mode 100644
index 0000000000000000000000000000000000000000..254fe252f8527d2ae3ca366f9d74b24a9b8f264d
--- /dev/null
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_uart_ex.c
@@ -0,0 +1,330 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+ uint32_t temp;
+
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+
+@endverbatim
+ * @{
+ */
+
+
+
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_usart.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_usart.c
index 609d4b95debdeed6883ca718425e2839c959217d..a8969dabea0a4591e96c365731d9baa094fe2a6d 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_usart.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_usart.c
@@ -9,70 +9,124 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
+ * + Peripheral State and Error functions
*
@verbatim
- ===============================================================================
+ ===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The USART HAL driver can be used as follows:
- (#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
- (##) Enable the USARTx interface clock.
- (##) USART pins configuration:
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
(+++) Configure these USART pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (+++) The specific USART interrupts (Transmission complete interrupt,
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
- (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the husart Init structure.
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
+ (Receiver/Transmitter) in the husart handle Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
+ Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
+ and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
+ or @ref HAL_USART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -93,40 +147,49 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup USART_Private_Constants
+/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
-#define DUMMY_DATA ((uint16_t) 0xFFFFU)
-#define TEACK_REACK_TIMEOUT ((uint32_t) 1000U)
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
- USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
+#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
/** @addtogroup USART_Private_Functions
* @{
*/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
+
/**
* @}
@@ -138,8 +201,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
* @{
*/
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -165,31 +228,40 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
@endverbatim
- Depending on the frame length defined by the M1 and M0 bits (7-bit,
- 8-bit or 9-bit), the possible USART frame formats are as listed in the
- following table:
-
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible USART formats are listed in the
+ following table.
+
+ Table 1. USART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | USART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
* @{
*/
/**
- * @brief Initializes the USART mode according to the specified
- * parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart USART handle
+ * @brief Initialize the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == NULL)
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -197,12 +269,25 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
- if(husart->State == HAL_USART_STATE_RESET)
+ if (husart->State == HAL_USART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ USART_InitCallbacksToDefault(husart);
+
+ if (husart->MspInitCallback == NULL)
+ {
+ husart->MspInitCallback = HAL_USART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ husart->MspInitCallback(husart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
husart->State = HAL_USART_STATE_BUSY;
@@ -219,25 +304,25 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
- /* TEACK and/or REACK to check before moving husart->State to Ready */
+ /* TEACK to check before moving husart->State to Ready */
return (USART_CheckIdleState(husart));
}
/**
- * @brief DeInitializes the USART peripheral
- * @param husart USART handle
+ * @brief DeInitialize the USART peripheral.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
- /* Check the USART handle allocation */
- if(husart == NULL)
+ /* Check the USART handle allocation */
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -251,8 +336,17 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
husart->Instance->CR2 = 0x0U;
husart->Instance->CR3 = 0x0U;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ if (husart->MspDeInitCallback == NULL)
+ {
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ husart->MspDeInitCallback(husart);
+#else
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_RESET;
@@ -264,11 +358,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
}
/**
- * @brief USART MSP Init
- * @param husart USART handle
+ * @brief Initialize the USART MSP.
+ * @param husart USART handle.
* @retval None
*/
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -279,11 +373,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
}
/**
- * @brief USART MSP DeInit
- * @param husart USART handle
+ * @brief DeInitialize the USART MSP.
+ * @param husart USART handle.
* @retval None
*/
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -293,56 +387,289 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
*/
}
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User USART Callback
+ * To be used instead of the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
++ */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = pCallback;
+ break;
+
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param husart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (HAL_USART_STATE_READY == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_USART_STATE_RESET == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+ * @brief USART Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- This subsection provides a set of functions allowing to manage the USART synchronous
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
data transfers.
[..] The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
- (#) There are two mode of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+ [..]
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
- (++) HAL_USART_Transmit()in simplex mode
+ (++) HAL_USART_Transmit() in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
(#) Non-Blocking mode API's with Interrupt are :
- (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Transmit_IT() in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
(++) HAL_USART_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_USART_Transmit_DMA()in simplex mode
+ (#) No-Blocking mode API's with DMA are :
+ (++) HAL_USART_Transmit_DMA() in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_TxHalfCpltCallback()
@@ -350,26 +677,45 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
- * @brief Simplex Send an amount of data in blocking mode
- * @param husart USART handle
- * @param pTxData pointer to data buffer
- * @param Size amount of data to be sent
- * @param Timeout Timeout duration
+ * @brief Simplex send an amount of data in blocking mode.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -386,31 +732,53 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
husart->TxXferSize = Size;
husart->TxXferCount = Size;
+ /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ }
+ else
+ {
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ }
+
/* Check the remaining data to be sent */
- while(husart->TxXferCount > 0U)
+ while (husart->TxXferCount > 0U)
{
- husart->TxXferCount--;
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
{
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pTxData += 2;
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
+ ptxdata16bits++;
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
+ ptxdata8bits++;
}
+
+ husart->TxXferCount--;
}
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
+ /* Clear Transmission Complete Flag */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+
+ /* At end of Tx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -425,75 +793,94 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
}
/**
- * @brief Receive an amount of data in blocking mode
- * @note To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart USART handle
- * @param pRxData pointer to data buffer
- * @param Size amount of data to be received
- * @param Timeout Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
- /* as long as data have to be received */
- while(husart->RxXferCount > 0U)
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- husart->RxXferCount--;
+ prxdata8bits = NULL;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ prxdata16bits = NULL;
+ }
- /* Wait until TC flag is set to send dummy byte in order to generate the
- * clock for the slave to send data.
- * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
- * can be written for all the cases. */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ /* as long as data have to be received */
+ while (husart->RxXferCount > 0U)
+ {
{
- return HAL_TIMEOUT;
+ /* Wait until TXE flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
}
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU);
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if (prxdata8bits == NULL)
{
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
}
else
{
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
}
+
+ husart->RxXferCount--;
+
}
+
+ /* At end of Rx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -508,33 +895,38 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in blocking mode
- * @param husart USART handle
- * @param pTxData pointer to TX data buffer
- * @param pRxData pointer to RX data buffer
- * @param Size amount of data to be sent (same amount to be received)
- * @param Timeout Timeout duration
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0U;
+ uint16_t rxdatacount;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -543,49 +935,97 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
husart->RxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
- /* Check the remain data to be sent */
- while(husart->TxXferCount > 0)
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- husart->TxXferCount--;
- husart->RxXferCount--;
+ prxdata8bits = NULL;
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ prxdata16bits = NULL;
+ }
- /* Wait until TC flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (husart->TxXferCount == 0x01U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if (ptxdata8bits == NULL)
{
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2;
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
}
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ husart->TxXferCount--;
+ }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ /* Check the remain data to be sent */
+ /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ rxdatacount = husart->RxXferCount;
+ while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
+ {
+ if (husart->TxXferCount > 0U)
{
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
}
- else
+
+ if (husart->RxXferCount > 0U)
{
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
}
+ rxdatacount = husart->RxXferCount;
}
+ /* At end of TxRx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -600,17 +1040,17 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param husart USART handle
- * @param pTxData pointer to data buffer
- * @param Size amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL ) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -618,12 +1058,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/* Process Locked */
__HAL_LOCK(husart);
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
husart->TxXferCount = Size;
+ husart->TxISR = NULL;
husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
+ husart->State = HAL_USART_STATE_BUSY_TX;
/* The USART Error Interrupts: (Frame error, noise error, overrun error)
are not managed by the USART Transmit Process to avoid the overrun interrupt
@@ -631,11 +1072,23 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
to benefit for the frame error and noise interrupts the usart mode should be
configured only for transmit "USART_MODE_TX" */
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ }
return HAL_OK;
}
@@ -646,51 +1099,63 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
}
/**
- * @brief Receive an amount of data in blocking mode
- * To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart USART handle
- * @param pRxData pointer to data buffer
- * @param Size amount of data to be received
+ * @brief Receive an amount of data in interrupt mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL ) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
husart->RxXferCount = Size;
+ husart->RxISR = NULL;
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Enable the USART Parity Error and Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Send dummy byte in order to generate the clock for the Slave to send the next data */
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU);
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
- else
+
{
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);
+ /* Send dummy data in order to generate the clock for the Slave to send the next data.
+ */
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
}
return HAL_OK;
@@ -702,22 +1167,23 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in interrupt mode
- * @param husart USART handle
- * @param pTxData pointer to TX data buffer
- * @param pRxData pointer to RX data buffer
- * @param Size amount of data to be sent (same amount to be received)
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -729,25 +1195,35 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
husart->TxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
- /* Enable the USART Data Register not empty Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ husart->RxISR = USART_RxISR_8BIT;
+ }
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+ }
return HAL_OK;
}
@@ -758,22 +1234,24 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
}
/**
- * @brief Send an amount of data in DMA mode
- * @param husart USART handle
- * @param pTxData pointer to data buffer
- * @param Size amount of data to be sent
+ * @brief Send an amount of data in DMA mode.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL ) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -784,34 +1262,49 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Set the USART DMA transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -820,22 +1313,24 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
}
/**
- * @brief Receive an amount of data in DMA mode
- * @param husart USART handle
- * @param pRxData pointer to data buffer
- * @param Size amount of data to be received
+ * @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
* @retval HAL status
- * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp = (uint32_t *)&pRxData;
- if(husart->State == HAL_USART_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL ) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -851,58 +1346,78 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
- /* Set the DMA abort callback */
- husart->hdmatx->XferAbortCallback = NULL;
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+ }
- /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- husart->hdmatx->XferHalfCpltCallback = NULL;
- husart->hdmatx->XferCpltCallback = NULL;
+ {
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ if (husart->hdmatx != NULL)
+ {
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Enable the USART transmit DMA channel: the transmit stream is used in order
- to generate in the non-blocking mode the clock to the slave device,
- this mode isn't a simplex receive mode but a full-duplex receive mode */
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* No need to check on error code */
+ UNUSED(status);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- return HAL_OK;
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -911,24 +1426,26 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
- * @param husart USART handle
- * @param pTxData pointer to TX data buffer
- * @param pRxData pointer to RX data buffer
- * @param Size amount of data to be received/sent
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be received/sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ HAL_StatusTypeDef status;
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -940,57 +1457,87 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+ if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
- /* Set the USART DMA Tx transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
- /* Set the USART DMA Tx transfer error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t *)&pRxData;
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* Enable the USART transmit DMA channel */
+ if (status == HAL_OK)
+ {
+ tmp = (uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
- return HAL_OK;
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -999,34 +1546,44 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
}
/**
- * @brief Pauses the DMA Transfer.
- * @param husart USART handle
- * @retval None
+ * @brief Pause the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
+ const HAL_USART_StateTypeDef state = husart->State;
+
/* Process Locked */
__HAL_LOCK(husart);
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
+ (state == HAL_USART_STATE_BUSY_TX))
{
/* Disable the USART DMA Tx request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Disable the USART DMA Rx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Rx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
}
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ else
{
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* Disable the USART DMA Rx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Nothing to do */
}
/* Process Unlocked */
@@ -1036,43 +1593,42 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
}
/**
- * @brief Resumes the DMA Transfer.
- * @param husart USART handle
- * @retval None
+ * @brief Resume the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
+ const HAL_USART_StateTypeDef state = husart->State;
+
/* Process Locked */
__HAL_LOCK(husart);
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (state == HAL_USART_STATE_BUSY_TX)
{
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
/* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
- /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART DMA Rx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- }
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
-
/* Enable the USART DMA Rx request before the DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1081,9 +1637,9 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
}
/**
- * @brief Stops the DMA Transfer.
- * @param husart USART handle
- * @retval None
+ * @brief Stop the DMA Transfer.
+ * @param husart USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
@@ -1094,138 +1650,384 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
- /* Stop USART DMA Tx request if ongoing */
- if ((husart->State == HAL_USART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
+ /* Disable the USART Tx/Rx DMA requests */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA tx channel */
+ if (husart->hdmatx != NULL)
{
- USART_EndTxTransfer(husart);
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
- /* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Abort the USART DMA rx channel */
+ if (husart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
{
- HAL_DMA_Abort(husart->hdmatx);
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
}
+ }
+
+ USART_EndTransfer(husart);
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Disable the USART Tx DMA request */
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t abortcplt = 1U;
+
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
}
- /* Stop USART DMA Rx request if ongoing */
- if ((husart->State == HAL_USART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
- USART_EndRxTransfer(husart);
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmatx != NULL)
{
- HAL_DMA_Abort(husart->hdmarx);
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
}
+ }
- /* Disable the USART Rx DMA request */
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
return HAL_OK;
}
/**
- * @brief This function handles USART interrupt request.
- * @param husart USART handle
+ * @brief Handle USART interrupt request.
+ * @param husart USART handle.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
{
- uint32_t isrflags = READ_REG(husart->Instance->ISR);
- uint32_t cr1its = READ_REG(husart->Instance->CR1);
- uint32_t cr3its = READ_REG(husart->Instance->CR3);
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
- /* USART in mode Receiver --------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
+ if (husart->RxISR != NULL)
{
- USART_TransmitReceive_IT(husart);
+ husart->RxISR(husart);
}
+ return;
}
}
/* If some errors occur */
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
-
- /* USART parity error interrupt occurred ------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ /* USART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
husart->ErrorCode |= HAL_USART_ERROR_PE;
}
- /* USART frame error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ /* USART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
husart->ErrorCode |= HAL_USART_ERROR_FE;
}
- /* USART noise error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ /* USART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
husart->ErrorCode |= HAL_USART_ERROR_NE;
}
- /* USART Over-Run interrupt occurred ----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ /* USART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+
/* Call USART Error Call back function if need be --------------------------*/
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)
{
/* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- USART_Receive_IT(husart);
+ if (husart->RxISR != NULL)
+ {
+ husart->RxISR(husart);
+ }
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+ consider error as blocking */
+ errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
+ (errorcode != 0U))
{
/* Blocking error : transfer is aborted
- Set the USART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- USART_EndRxTransfer(husart);
+ Set the USART state ready to be able to start again the process,
+ Disable Interrupts, and disable DMA requests, if ongoing */
+ USART_EndTransfer(husart);
/* Disable the USART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+ /* Abort the USART DMA Tx channel */
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART Tx DMA Abort callback to NULL : no callback
+ executed at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA TX */
+ (void)HAL_DMA_Abort_IT(husart->hdmatx);
+ }
/* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- /* Set the USART DMA Abort callback :
- will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ /* Set the USART Rx DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
/* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
husart->hdmarx->XferAbortCallback(husart->hdmarx);
@@ -1234,20 +2036,38 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
/* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
+ Error is notified to user through user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
}
}
@@ -1255,31 +2075,30 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
} /* End if some error occurs */
- /* USART in mode Transmitter -----------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+
+ /* USART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- USART_Transmit_IT(husart);
- }
- else
+ if (husart->TxISR != NULL)
{
- USART_TransmitReceive_IT(husart);
+ husart->TxISR(husart);
}
return;
}
/* USART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
USART_EndTransmit_IT(husart);
return;
}
+
}
/**
- * @brief Tx Transfer completed callbacks
- * @param husart USART handle
+ * @brief Tx Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1288,28 +2107,28 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback can be implemented in the user file
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param husart USART handle
+ * @brief Tx Half Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback can be implemented in the user file
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Transfer completed callbacks.
- * @param husart USART handle
+ * @brief Rx Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1318,13 +2137,13 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback can be implemented in the user file
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Half Transfer completed callbacks
- * @param husart usart handle
+ * @brief Rx Half Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1338,8 +2157,8 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
}
/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process
- * @param husart USART handle
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1353,8 +2172,8 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
}
/**
- * @brief USART error callbacks
- * @param husart USART handle
+ * @brief USART error callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1363,37 +2182,51 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback can be implemented in the user file
+ the HAL_USART_ErrorCallback can be implemented in the user file.
*/
}
/**
- * @}
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
*/
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief USART State and Errors functions
- *
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
@verbatim
==============================================================================
- ##### Peripheral State and Errors functions #####
+ ##### Peripheral State and Error functions #####
==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of
- USART communication
- process, return Peripheral Errors occurred during communication process
- (+) HAL_USART_GetState() API can be helpful to check in run-time the state
- of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occurred during
- communication.
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
@endverbatim
* @{
*/
+
/**
- * @brief return the USART state
- * @param husart USART handle
- * @retval HAL state
+ * @brief Return the USART handle state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
{
@@ -1401,10 +2234,10 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
}
/**
- * @brief Return the USART error code
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Return the USART error code.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
- * @retval USART Error Code
+ * @retval USART handle Error Code
*/
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
{
@@ -1415,454 +2248,383 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
* @}
*/
-
-/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Transmit_IT().
- * @param husart USART handle
- * @retval HAL status
- * @note The USART errors are not managed to avoid the overrun error.
- */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
-
- if(husart->TxXferCount == 0U)
- {
- /* Disable the USART Transmit data register empty interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
- }
-
- husart->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
/**
- * @brief Wraps up transmission in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
+ * @}
*/
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
- /* Disable the USART Transmit Complete Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
-}
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Receive_IT()
- * @param husart USART handle
- * @retval HAL status
+ * @brief Initialize the callbacks to their default values.
+ * @param husart USART handle.
+ * @retval none
*/
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
{
- uint16_t* tmp;
- uint16_t uhMask = husart->Mask;
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
-
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);
-
- if(--husart->RxXferCount == 0U)
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the USART Parity Error Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_RxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
+ /* Init the USART Callback settings */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT()
- * @param husart USART handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
- uint16_t uhMask = husart->Mask;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- if(husart->TxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
- }
- husart->TxXferCount--;
-
- /* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
- }
- }
- }
-
- if(husart->RxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- husart->RxXferCount--;
- }
- }
-
- /* Check the latest data received */
- if(husart->RxXferCount == 0U)
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the USART Parity Error Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxRxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles USART Communication Timeout.
- * @param husart USART handle
- * @param Flag specifies the USART flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+ * @param husart USART handle.
+ * @retval None
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
{
- /* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout))
- {
- /* Disable the USART Transmit Complete Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
- /* Disable the USART RXNE Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the USART Parity Error Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
+ /* At end of process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
}
-
/**
- * @brief DMA USART transmit process complete callback
- * @param hdma DMA handle
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
husart->TxXferCount = 0U;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Enable the USART Transmit Complete Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
/* DMA Circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
- HAL_USART_TxCpltCallback(husart);
- }
- }
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ }
}
-
/**
- * @brief DMA USART transmit process half complete callback
- * @param hdma DMA handle
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half Complete Callback */
+ husart->TxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Half Complete Callback */
HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief DMA USART receive process complete callback
- * @param hdma DMA handle
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
husart->RxXferCount = 0U;
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
- in USART CR3 register */
+ in USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* similarly, disable the DMA TX transfer that was started to provide the
clock to the slave device */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- husart->State= HAL_USART_STATE_READY;
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ husart->State = HAL_USART_STATE_READY;
}
/* DMA circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief DMA USART receive process half complete callback
- * @param hdma DMA handle
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Half Complete Callback */
+ husart->RxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Half Complete Callback */
HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief DMA USART communication error callback
- * @param hdma DMA handle
+ * @brief DMA USART communication error callback.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
-
- /* Stop USART DMA Tx request if ongoing */
- if((husart->State == HAL_USART_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
- {
- USART_EndTxTransfer(husart);
- }
-
- /* Stop USART DMA Rx request if ongoing */
- if((husart->State == HAL_USART_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
- {
- USART_EndRxTransfer(husart);
- }
+ USART_EndTransfer(husart);
husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief DMA USART communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma DMA handle.
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
- * @param husart USART handle.
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
* @retval None
*/
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- /* At end of Tx process, restore husart->State to Ready */
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmarx != NULL)
+ {
+ if (husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
}
+
/**
- * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
- * @param husart USART handle.
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
* @retval None
*/
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- /* At end of Rx process, restore husart->RxState to Ready */
- husart->State = HAL_USART_STATE_READY;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
- /* Disable RXNE, PE and ERR interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (husart->hdmatx != NULL)
+ {
+ if (husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
+ HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout.
+ * @param husart USART handle.
+ * @param Flag Specifies the USART flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
}
/**
- * @brief Configure the USART peripheral
- * @param husart USART handle
- * @retval None
+ * @brief Configure the USART peripheral.
+ * @param husart USART handle.
+ * @retval HAL status
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
- uint32_t tmpreg = 0x0U;
- USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+ uint32_t tmpreg;
+ USART_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
+ uint16_t brrtemp;
+ uint32_t usartdiv = 0x00000000;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -1873,16 +2635,14 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
assert_param(IS_USART_PARITY(husart->Init.Parity));
assert_param(IS_USART_MODE(husart->Init.Mode));
- assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));
-
/*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity, Mode and OverSampling:
- * set the M bits according to husart->Init.WordLength value
- * set PCE and PS bits according to husart->Init.Parity value
- * set TE and RE bits according to husart->Init.Mode value
- * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
@@ -1890,77 +2650,89 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= (uint32_t)husart->Init.CLKLastBit;
tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
- tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+ tmpreg |= (uint32_t)husart->Init.StopBits;
MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* no CR3 register configuration */
/*-------------------------- USART BRR Configuration -----------------------*/
/* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
USART_GETCLOCKSOURCE(husart, clocksource);
+
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate));
break;
- case USART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- husart->Instance->BRR = brrtemp;
+ /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
+ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ husart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+
+ /* Clear ISR function pointers */
+ husart->RxISR = NULL;
+ husart->TxISR = NULL;
return ret;
}
/**
- * @brief Check the USART Idle State
- * @param husart USART handle
+ * @brief Check the USART Idle State.
+ * @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- /* Initialize the USART ErrorCode */
+ /* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
- if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
- husart->State= HAL_USART_STATE_TIMEOUT;
+ /* Timeout occurred */
return HAL_TIMEOUT;
}
}
/* Initialize the USART state*/
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1968,6 +2740,293 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
return HAL_OK;
}
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when data word length is less than 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+
+ /* Check that a Tx process is ongoing */
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t *tmp;
+
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ tmp = (uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non-blocking mode.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ /* Clear TxISR function pointer */
+ husart->TxISR = NULL;
+
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+ /* Tx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if (husart->RxXferCount == 0U)
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when data word length is less than 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t uhMask = husart->Mask;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
+ */
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t *tmp;
+ uint16_t uhMask = husart->Mask;
+
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
+ {
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
+
+ if (husart->RxXferCount == 0U)
+ {
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
+
+ /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ txdatacount = husart->TxXferCount;
+
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+}
+
+
/**
* @}
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_wwdg.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_wwdg.c
index 9d1c3d1f88d994a28486c506779a331623302661..b1fcde238712e44adcfc8054746e11459f0db20e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_wwdg.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_wwdg.c
@@ -5,118 +5,110 @@
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and Configuration function
+ * + Initialization and Configuration functions
* + IO operation functions
@verbatim
==============================================================================
- ##### WWDG specific features #####
+ ##### WWDG Specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
+ value rolls down from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
-
(+) Once enabled the WWDG cannot be disabled except by a system reset.
-
- (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
- occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
-
- (+) The WWDG downcounter input clock is derived from the APB clock divided
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
-
- (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
-
- (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
- where T[5;0] are the lowest 6 bits of downcounter.
-
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
- (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
-
- (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: ~73.14µs
+ (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: ~599.18ms
+ ==============================================================================
##### How to use this driver #####
==============================================================================
[..]
+ *** Common driver usage ***
+ ===========================
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
+ (+) Set the WWDG prescaler, refresh window and counter value
+ using HAL_WWDG_Init() function.
+ (+) Start the WWDG using HAL_WWDG_Start() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
+ generated when the counter reaches 0x40, and then start the WWDG using
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
+ add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
+ the counter is lower than the refresh window value already programmed.
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
-
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+ [..]
+ *** Callback registration ***
+ =============================
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ @ref HAL_WWDG_RegisterCallback() to register a user callback.
+
+ (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -172,7 +164,7 @@
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
- if(hwwdg == NULL)
+ if (hwwdg == NULL)
{
return HAL_ERROR;
}
@@ -184,8 +176,24 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if(hwwdg->EwiCallback == NULL)
+ {
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ }
+
+ if(hwwdg->MspInitCallback == NULL)
+ {
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hwwdg->MspInitCallback(hwwdg);
+#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
+#endif
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -217,6 +225,82 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
*/
}
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User WWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch(CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = pCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a WWDG Callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch(CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif
+
/**
* @}
*/
@@ -269,16 +353,21 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hwwdg->EwiCallback(hwwdg);
+#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif
}
}
}
@@ -290,7 +379,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
* the configuration information for the specified WWDG module.
* @retval None
*/
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_adc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_adc.c
index 4c0ec47e659e361a9a853bab22745c235e7784de..277063018e693fb771d29208fdf06594a59fd554 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_adc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_adc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_crc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_crc.c
index 50efc31ae022eb79a8474c3f7caa7cdee1ceefd8..d0b266b415e46ee3e0e0d47fc31963ef800e1c15 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_crc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_crc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dac.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dac.c
index 3d481c6f5ea5487a033eb942cc27868bad4b418f..d2c8ef849412bfa36d7042a7c77cd9e3c24b186b 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dac.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dac.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma.c
index 03a18006397780f6880ca80f92f946cfdebe44d8..e9c2a38524e6fb52e9aa6079ec719893ac39e7c5 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma2d.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma2d.c
index 9b6f8be0b20024e253243bc883e7fd3d0372a505..9e3ae778c62bdfb24335bac9cdb3e82776d1d525 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma2d.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_dma2d.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -87,19 +71,21 @@
#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
-#define IS_LL_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= LL_DMA2D_OFFSET_MAX)
+
+#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
-
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \
@@ -120,6 +106,8 @@
#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \
((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+
+
/**
* @}
*/
@@ -170,7 +158,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
* @note DMA2D transfers must be disabled to set initialization bits in configuration registers,
* otherwise ERROR result is returned.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
+ * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
* that contains the configuration information for the specified DMA2D peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
@@ -180,20 +168,21 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
{
ErrorStatus status = ERROR;
LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
- uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U;
+ uint32_t tmp, tmp1, tmp2;
+ uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
+ assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
+ assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
- assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
- assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
-#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
+#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
@@ -208,13 +197,18 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
+ regMask = DMA2D_OPFCCR_CM;
+ regValue = DMA2D_InitStruct->ColorMode;
+
+
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
- MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \
- (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode));
-#else
- MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, DMA2D_InitStruct->ColorMode);
+ regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI);
+ regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode);
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
+ MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue);
+
/* DMA2D OOR register configuration ------------------------------------------*/
LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
@@ -241,7 +235,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
/**
* @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
- * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
+ * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -250,14 +244,14 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
/* Set DMA2D_InitStruct fields to default values */
DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M;
DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888;
+ DMA2D_InitStruct->NbrOfLines = 0x0U;
+ DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
DMA2D_InitStruct->LineOffset = 0x0U;
DMA2D_InitStruct->OutputBlue = 0x0U;
DMA2D_InitStruct->OutputGreen = 0x0U;
DMA2D_InitStruct->OutputRed = 0x0U;
DMA2D_InitStruct->OutputAlpha = 0x0U;
DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
- DMA2D_InitStruct->NbrOfLines = 0x0U;
- DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR;
@@ -268,9 +262,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
* @brief Configure the foreground or background according to the specified parameters
* in the LL_DMA2D_LayerCfgTypeDef structure.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+ * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
* the configuration information for the specified layer.
- * @param LayerIdx DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval None
@@ -292,6 +286,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D
assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
+
if (LayerIdx == 0U)
{
/* Configure the background memory address */
@@ -362,7 +357,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D
/**
* @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
- * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+ * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -390,15 +385,15 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
* @brief Initialize DMA2D output color register according to the specified parameters
* in DMA2D_ColorStruct.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
+ * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
* the color configuration information for the specified DMA2D peripheral.
* @retval None
*/
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
{
- uint32_t outgreen = 0U;
- uint32_t outred = 0U;
- uint32_t outalpha = 0U;
+ uint32_t outgreen;
+ uint32_t outred;
+ uint32_t outalpha;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -455,7 +450,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM
*/
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -499,7 +494,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -543,7 +538,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -587,7 +582,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_exti.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_exti.c
index 4d58695e10a805cbe7e0dc8d4129a4cff0471134..5663874a11f27d5a7bfff1070fa74b77b7262809 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_exti.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_exti.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_fmc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_fmc.c
index 45bf8c8ffb3ee4f155721c21fc171ae4ee5794f3..cdde47521d513b1884f69da0617f95b09450d231 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_fmc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_fmc.c
@@ -44,29 +44,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_gpio.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_gpio.c
index 40080dbe222770cc76303b097dc7299ad25ae11a..ba55800b00900a60633eda069356bc767b1cc466 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_gpio.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_gpio.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_i2c.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_i2c.c
index ef295570c60f39d97370e34efe76a043f961531e..a2eb5d54e742bdf46a61f31ea502f8d75c8ab7b2 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_i2c.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_i2c.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -100,7 +84,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -158,7 +142,7 @@ uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_lptim.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_lptim.c
index ecc7e76716960b69cb5ef67bfb5dfc9e684e8ab4..137335d1baf11c258e4b86f087a83c979fa5d193 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_lptim.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_lptim.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -61,10 +45,10 @@
/** @addtogroup LPTIM_LL_Private_Macros
* @{
*/
-#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
-#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
+#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
@@ -73,10 +57,10 @@
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
-#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
-#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
@@ -167,10 +151,10 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
- assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
- assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+ assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
/* Set CKSEL bitfield according to ClockSource value */
/* Set PRESC bitfield according to Prescaler value */
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_pwr.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_pwr.c
index 905bb11b2eaf0b4f2bc6ee7b7cdeeee45486bb01..1404ad4c58ddd55ec12c78385ab46354b254b7cd 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_pwr.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_pwr.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rcc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rcc.c
index 43aed1fabbfa8b0290923ff315a97a123f4536d5..9c03d565721fc857b27e99b632aee96e6d947b5e 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rcc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rcc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -771,7 +755,6 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
* @arg @ref LL_RCC_SAI2_CLKSOURCE
* @retval SAI clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
- * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
*/
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
{
@@ -821,8 +804,10 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
break;
#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
+ sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
+
default:
- sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
break;
}
}
@@ -869,9 +854,11 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
break;
#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
- default:
- sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
break;
+
+ default:
+ break;
}
}
}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rng.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rng.c
index 1572a9e86cbcde5202695a4a6e363baa0d05d4aa..5b9fe66f57abe4fa3178324e20617715b519a8d7 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rng.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rng.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -80,13 +64,11 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
-
/* Enable RNG reset state */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
/* Release RNG from reset state */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
-
return (SUCCESS);
}
@@ -102,7 +84,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
* @}
*/
-#endif /* defined (RNG) */
+#endif /* RNG */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rtc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rtc.c
index dd3b12bb0c1ff837d230d0308bf97eeaf5d0416f..a333075ef029920e4e26b8feef92f8016daad703 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rtc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_rtc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_sdmmc.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_sdmmc.c
index 01e8c434f1909d888801327d91a46afb7e4a4195..a225e1d25f142c925439967ffe9e6f1937b4bac9 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_sdmmc.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_sdmmc.c
@@ -145,29 +145,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_spi.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_spi.c
index 8e94fee2c6656f2872d5ce1ae6c96c18dd502dff..60494951cc4c742a30960b0b10dc2d7ab7ffb750 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_spi.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_spi.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -49,7 +33,7 @@
* @{
*/
-#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
/** @addtogroup SPI_LL
* @{
@@ -233,7 +217,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -419,7 +403,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -428,9 +412,9 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- uint32_t sourceclock = 0U;
+ uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp;
+ uint32_t sourceclock;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
@@ -488,25 +472,25 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
/* Remove the floating point */
tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+ i2sodd = (tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+ i2sdiv = ((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
+ i2sodd = (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
@@ -576,7 +560,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_
* @}
*/
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
/**
* @}
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_tim.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_tim.c
index 7f1c9e081c218e236f52f06434a6ab8c4f47b4a2..8bd622a6603188a9913eed275e3485af05f4e648 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_tim.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_tim.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -170,24 +154,24 @@
|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
|| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
@@ -348,11 +332,11 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
{
/* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
}
/**
@@ -365,7 +349,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
*/
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
{
- uint32_t tmpcr1 = 0U;
+ uint32_t tmpcr1;
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(TIMx));
@@ -555,8 +539,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct
*/
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
@@ -646,10 +630,10 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI
*/
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
@@ -728,7 +712,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
@@ -824,9 +808,9 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
*/
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
@@ -903,9 +887,9 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
@@ -982,9 +966,9 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
@@ -1061,9 +1045,9 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
@@ -1131,8 +1115,8 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr3 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(TIMx));
@@ -1192,8 +1176,8 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr3 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr3;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(TIMx));
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usart.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usart.c
index de96f7fcf928f74b7f9fd047acf5b1252c460f0f..028c7049184eae00ae09ed3001edd06f63936d06 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usart.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usart.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -65,7 +49,6 @@
* @}
*/
-
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@@ -172,14 +155,6 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
}
- else if (USARTx == USART6)
- {
- /* Force reset of USART clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
-
- /* Release reset of USART clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
- }
else if (USARTx == UART4)
{
/* Force reset of UART clock */
@@ -196,6 +171,14 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
}
+ else if (USARTx == USART6)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+ }
else if (USARTx == UART7)
{
/* Force reset of UART clock */
@@ -224,7 +207,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -293,10 +276,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
}
- else if (USARTx == USART6)
- {
- periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
- }
else if (USARTx == UART4)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
@@ -305,6 +284,10 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
}
+ else if (USARTx == USART6)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
+ }
else if (USARTx == UART7)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
@@ -334,7 +317,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
- /* Check BRR is greater than or equal to 16d */
+ /* Check BRR is lower than or equal to 0xFFFF */
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
@@ -346,7 +329,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
+ * whose fields will be set to default values.
* @retval None
*/
@@ -366,7 +349,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
@@ -430,7 +413,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
+ * whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usb.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usb.c
index 6717783ec517c181c729341bb62ad3e27fa96649..19c5604bd22cffa255fc3fbd18cd176ebf315f1b 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usb.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_usb.c
@@ -26,29 +26,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -61,7 +45,7 @@
*/
#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -101,6 +85,8 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx);
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ HAL_StatusTypeDef ret;
+
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -110,12 +96,12 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
- if(cfg.use_external_vbus == 1U)
+ if (cfg.use_external_vbus == 1U)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
/* Reset after a PHY select */
- (void)USB_CoreReset(USBx);
+ ret = USB_CoreReset(USBx);
}
#ifdef USB_HS_PHYC
else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
@@ -133,15 +119,17 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
/* Enables control of a High Speed USB PHY */
- USB_HS_PHYCInit(USBx);
+ if (USB_HS_PHYCInit(USBx) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- if(cfg.use_external_vbus == 1)
+ if (cfg.use_external_vbus == 1U)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
/* Reset after a PHY select */
- USB_CoreReset(USBx);
-
+ ret = USB_CoreReset(USBx);
}
#endif
else /* FS interface (embedded Phy) */
@@ -150,18 +138,102 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
/* Reset after a PHY select and set Host mode */
- (void)USB_CoreReset(USBx);
+ ret = USB_CoreReset(USBx);
- /* Deactivate the power down*/
- USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+ /* Activate the USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
- if(cfg.dma_enable == 1U)
+ if (cfg.dma_enable == 1U)
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
}
+ return ret;
+}
+
+
+/**
+ * @brief Set the USB turnaround time
+ * @param USBx USB Instance
+ * @param hclk: AHB clock frequency
+ * @retval USB turnaround time In PHY Clocks number
+ */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+ uint32_t hclk, uint8_t speed)
+{
+ uint32_t UsbTrd;
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ latency to the Data FIFO */
+ if (speed == USB_OTG_SPEED_FULL)
+ {
+ if ((hclk >= 14200000U) && (hclk < 15000000U))
+ {
+ /* hclk Clock Range between 14.2-15 MHz */
+ UsbTrd = 0xFU;
+ }
+ else if ((hclk >= 15000000U) && (hclk < 16000000U))
+ {
+ /* hclk Clock Range between 15-16 MHz */
+ UsbTrd = 0xEU;
+ }
+ else if ((hclk >= 16000000U) && (hclk < 17200000U))
+ {
+ /* hclk Clock Range between 16-17.2 MHz */
+ UsbTrd = 0xDU;
+ }
+ else if ((hclk >= 17200000U) && (hclk < 18500000U))
+ {
+ /* hclk Clock Range between 17.2-18.5 MHz */
+ UsbTrd = 0xCU;
+ }
+ else if ((hclk >= 18500000U) && (hclk < 20000000U))
+ {
+ /* hclk Clock Range between 18.5-20 MHz */
+ UsbTrd = 0xBU;
+ }
+ else if ((hclk >= 20000000U) && (hclk < 21800000U))
+ {
+ /* hclk Clock Range between 20-21.8 MHz */
+ UsbTrd = 0xAU;
+ }
+ else if ((hclk >= 21800000U) && (hclk < 24000000U))
+ {
+ /* hclk Clock Range between 21.8-24 MHz */
+ UsbTrd = 0x9U;
+ }
+ else if ((hclk >= 24000000U) && (hclk < 27700000U))
+ {
+ /* hclk Clock Range between 24-27.7 MHz */
+ UsbTrd = 0x8U;
+ }
+ else if ((hclk >= 27700000U) && (hclk < 32000000U))
+ {
+ /* hclk Clock Range between 27.7-32 MHz */
+ UsbTrd = 0x7U;
+ }
+ else /* if(hclk >= 32000000) */
+ {
+ /* hclk Clock Range between 32-200 MHz */
+ UsbTrd = 0x6U;
+ }
+ }
+ else if (speed == USB_OTG_SPEED_HIGH)
+ {
+ UsbTrd = USBD_HS_TRDT_VALUE;
+ }
+ else
+ {
+ UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+ }
+
+ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+ USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
return HAL_OK;
}
@@ -199,7 +271,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_DRD_MODE: Dual Role Device mode
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
@@ -228,8 +300,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
@@ -238,18 +311,21 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->DIEPTXF[i] = 0U;
}
- /*Activate VBUS Sensing B */
- USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
+ /* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
- /* B-peripheral session valid override enable*/
+ /* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
}
+ else
+ {
+ /* Enable HW VBUS sensing */
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+ }
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
@@ -257,41 +333,48 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Device mode configuration */
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
- if(cfg.phy_itface == USB_OTG_ULPI_PHY)
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
- if(cfg.speed == USB_OTG_SPEED_HIGH)
+ if (cfg.speed == USB_OTG_SPEED_HIGH)
{
/* Set High speed phy */
- (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH);
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
/* set High speed phy in Full speed mode */
- (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
- else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
+ else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
{
- if(cfg.speed == USB_OTG_SPEED_HIGH)
+ if (cfg.speed == USB_OTG_SPEED_HIGH)
{
/* Set High speed phy */
- (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH);
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
/* set High speed phy in Full speed mode */
- (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else
{
/* Set Full speed phy */
- (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_FULL);
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
}
/* Flush the FIFOs */
- (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
- (void)USB_FlushRxFifo(USBx);
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
@@ -370,10 +453,10 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
- USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
- if(cfg.Sof_enable != 0U)
+ if (cfg.Sof_enable != 0U)
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
}
@@ -383,7 +466,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
}
- return HAL_OK;
+ return ret;
}
/**
@@ -394,7 +477,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
15 means Flush all Tx FIFOs
* @retval HAL status
*/
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
uint32_t count = 0U;
@@ -436,7 +519,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
}
/**
- * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
+ * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
* depending the PHY type and the enumeration speed of the device.
* @param USBx Selected device
* @param speed device speed
@@ -444,10 +527,9 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -456,13 +538,12 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
}
/**
- * @brief USB_GetDevSpeed :Return the Dev Speed
+ * @brief USB_GetDevSpeed Return the Dev Speed
* @param USBx Selected device
- * @retval speed : device speed
+ * @retval speed device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@@ -470,19 +551,15 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
uint8_t speed;
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
- if(DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+ if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
{
speed = USB_OTG_SPEED_HIGH;
}
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
- (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+ (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
speed = USB_OTG_SPEED_FULL;
}
- else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- speed = USB_OTG_SPEED_LOW;
- }
else
{
speed = 0U;
@@ -504,26 +581,26 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
if (ep->is_in == 1U)
{
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
{
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
- ((uint32_t)ep->type << 18) | (epnum << 22) |
- USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
- USB_OTG_DIEPCTL_USBAEP;
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
}
}
else
{
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
{
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)ep->type << 18) |
- USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
- USB_OTG_DOEPCTL_USBAEP;
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DOEPCTL_USBAEP;
}
}
return HAL_OK;
@@ -547,11 +624,11 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
{
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
((uint32_t)ep->type << 18) | (epnum << 22) |
- USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
- USB_OTG_DIEPCTL_USBAEP;
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
}
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
}
else
{
@@ -559,10 +636,10 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
{
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)ep->type << 18) | (epnum << 22) |
- USB_OTG_DOEPCTL_USBAEP;
+ USB_OTG_DOEPCTL_USBAEP;
}
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
}
return HAL_OK;
@@ -582,8 +659,8 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
USB_OTG_DIEPCTL_MPSIZ |
USB_OTG_DIEPCTL_TXFNUM |
@@ -592,8 +669,8 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
USB_OTG_DOEPCTL_MPSIZ |
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
@@ -617,13 +694,13 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
- USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));
+ USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
- USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
return HAL_OK;
@@ -639,7 +716,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -676,7 +753,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
if (dma == 1U)
{
- USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
}
else
{
@@ -685,7 +765,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
}
@@ -733,7 +813,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
if (dma == 1U)
{
- USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)ep->xfer_buff;
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
}
if (ep->type == EP_TYPE_ISOC)
@@ -764,7 +847,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -789,7 +872,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- if(ep->xfer_len > ep->maxpacket)
+ if (ep->xfer_len > ep->maxpacket)
{
ep->xfer_len = ep->maxpacket;
}
@@ -799,14 +882,17 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
if (dma == 1U)
{
- USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
}
else
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
@@ -832,7 +918,10 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
if (dma == 1U)
{
- USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
}
/* EP enable */
@@ -863,7 +952,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
if (dma == 0U)
{
- count32b = ((uint32_t)len + 3U) / 4U;
+ count32b = ((uint32_t)len + 3U) / 4U;
for (i = 0U; i < count32b; i++)
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
@@ -908,7 +997,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -949,7 +1038,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
{
- USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
}
}
else
@@ -970,6 +1059,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
*/
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
{
+ HAL_StatusTypeDef ret;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
@@ -986,10 +1076,19 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
USBx_DEVICE->DAINTMSK = 0U;
/* Flush the FIFO */
- (void)USB_FlushRxFifo(USBx);
- (void)USB_FlushTxFifo(USBx , 0x10U);
+ ret = USB_FlushRxFifo(USBx);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
- return HAL_OK;
+ ret = USB_FlushTxFifo(USBx, 0x10U);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
+
+ return ret;
}
/**
@@ -999,11 +1098,11 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
+ USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
return HAL_OK;
@@ -1014,7 +1113,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1029,7 +1128,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1044,7 +1143,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t tmpreg;
@@ -1059,7 +1158,7 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1075,7 +1174,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1093,7 +1192,7 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1111,14 +1210,14 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg, msk, emp;
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
- msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7;
+ msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
return tmpreg;
@@ -1130,7 +1229,7 @@ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
* @param interrupt interrupt flag
* @retval None
*/
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
{
USBx->GINTSTS |= interrupt;
}
@@ -1145,7 +1244,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
*/
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
{
- return ((USBx->GINTSTS ) & 0x1U);
+ return ((USBx->GINTSTS) & 0x1U);
}
/**
@@ -1153,14 +1252,14 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
/* Set the MPS of the IN EP based on the enumeration speed */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
{
USBx_INEP(0U)->DIEPCTL |= 3U;
}
@@ -1182,6 +1281,15 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
{
uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+ if (gSNPSiD > USB_OTG_CORE_ID_300A)
+ {
+ if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ return HAL_OK;
+ }
+ }
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
@@ -1192,7 +1300,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin
{
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
/* EP enable */
- USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;
+ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
}
return HAL_OK;
@@ -1242,13 +1350,14 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
*/
static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
{
+ UNUSED(USBx);
uint32_t count = 0U;
/* Enable LDO */
USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
/* wait for LDO Ready */
- while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET)
+ while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U)
{
if (++count > 200000U)
{
@@ -1281,6 +1390,10 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
{
USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);
}
+ else
+ {
+ /* ... */
+ }
/* Control the tuning interface of the High Speed PHY */
USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
@@ -1289,7 +1402,7 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
/* 2ms Delay required to get internal phy clock stable */
- HAL_Delay(2);
+ HAL_Delay(2U);
return HAL_OK;
}
@@ -1303,7 +1416,7 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
@@ -1314,13 +1427,22 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Disable VBUS sensing */
USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
- /* Disable the FS/LS support mode only */
- if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS))
+ if ((USBx->CID & (0x1U << 8)) != 0U)
{
- USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ if (cfg.speed == USB_OTG_SPEED_FULL)
+ {
+ /* Force Device Enumeration to FS/LS mode only */
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ }
+ else
+ {
+ /* Set default Max speed support */
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ }
}
else
{
+ /* Set default Max speed support */
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
}
@@ -1346,19 +1468,19 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFFU;
- if(USBx == USB_OTG_FS)
+ if ((USBx->CID & (0x1U << 8)) != 0U)
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = 0x80U;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
- USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+ USBx->GRXFSIZ = 0x200U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+ USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
}
else
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = 0x200U;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
- USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+ USBx->GRXFSIZ = 0x80U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+ USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
}
/* Enable the common interrupts */
@@ -1368,8 +1490,8 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
}
/* Enable interrupts matching to the Host mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
- USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT|\
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
+ USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
return HAL_OK;
@@ -1385,7 +1507,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1402,7 +1524,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq
}
else
{
- /* ... */
+ /* ... */
}
return HAL_OK;
@@ -1427,9 +1549,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
- HAL_Delay (100U); /* See Note #1 */
+ HAL_Delay(100U); /* See Note #1 */
USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
- HAL_Delay (10U);
+ HAL_Delay(10U);
return HAL_OK;
}
@@ -1442,7 +1564,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* 1 : VBUS Inactive
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1472,7 +1594,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
*/
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1486,7 +1608,7 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval current frame number
*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1535,59 +1657,59 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
/* Enable channel interrupts required for this transfer. */
switch (ep_type)
{
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
- USB_OTG_HCINTMSK_STALLM |
- USB_OTG_HCINTMSK_TXERRM |
- USB_OTG_HCINTMSK_DTERRM |
- USB_OTG_HCINTMSK_AHBERR |
- USB_OTG_HCINTMSK_NAKM;
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_NAKM;
- if ((epnum & 0x80U) == 0x80U)
- {
- USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- else
- {
- if(USBx != USB_OTG_FS)
+ if ((epnum & 0x80U) == 0x80U)
{
- USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+ else
+ {
+ if ((USBx->CID & (0x1U << 8)) != 0U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ }
+ }
+ break;
+
+ case EP_TYPE_INTR:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_NAKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
}
- }
- break;
-
- case EP_TYPE_INTR:
- USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
- USB_OTG_HCINTMSK_STALLM |
- USB_OTG_HCINTMSK_TXERRM |
- USB_OTG_HCINTMSK_DTERRM |
- USB_OTG_HCINTMSK_NAKM |
- USB_OTG_HCINTMSK_AHBERR |
- USB_OTG_HCINTMSK_FRMORM;
-
- if ((epnum & 0x80U) == 0x80U)
- {
- USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- break;
+ break;
- case EP_TYPE_ISOC:
- USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
- USB_OTG_HCINTMSK_ACKM |
- USB_OTG_HCINTMSK_AHBERR |
- USB_OTG_HCINTMSK_FRMORM;
+ case EP_TYPE_ISOC:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
- if ((epnum & 0x80U) == 0x80U)
- {
- USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
- }
- break;
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+ }
+ break;
- default:
- ret = HAL_ERROR;
- break;
+ default:
+ ret = HAL_ERROR;
+ break;
}
/* Enable the top level host channel interrupt. */
@@ -1597,7 +1719,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
/* Program the HCCHAR register */
- if((epnum & 0x80U) == 0x80U)
+ if ((epnum & 0x80U) == 0x80U)
{
HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
}
@@ -1606,7 +1728,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
HCcharEpDir = 0U;
}
- if(speed == HPRT0_PRTSPD_LOW_SPEED)
+ if (speed == HPRT0_PRTSPD_LOW_SPEED)
{
HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
}
@@ -1616,9 +1738,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
}
USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
- ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
- (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
- ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+ ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+ (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+ ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
if (ep_type == EP_TYPE_INTR)
{
@@ -1648,14 +1770,14 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t num_packets;
uint16_t max_hc_pkt_count = 256U;
- if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
+ if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USB_OTG_SPEED_HIGH))
{
- if((dma == 0U) && (hc->do_ping == 1U))
+ if ((dma == 0U) && (hc->do_ping == 1U))
{
(void)USB_DoPing(USBx, hc->ch_num);
return HAL_OK;
}
- else if(dma == 1U)
+ else if (dma == 1U)
{
USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
hc->do_ping = 0U;
@@ -1688,8 +1810,8 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
/* Initialize the HCTSIZn register */
USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
- (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
- (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+ (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+ (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
if (dma != 0U)
{
@@ -1712,45 +1834,45 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
}
else
{
- tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+ tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
}
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
if (dma == 0U) /* Slave mode */
{
- if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
{
- switch(hc->ep_type)
+ switch (hc->ep_type)
{
/* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
- len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx->HNPTXSTS & 0xFFFFU))
- {
- /* need to process data in nptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
- }
- break;
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+ {
+ /* need to process data in nptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+ }
+ break;
/* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
- }
- break;
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+ {
+ /* need to process data in ptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ }
+ break;
- default:
- break;
+ default:
+ break;
}
/* Write packet into the Tx FIFO. */
@@ -1766,7 +1888,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1780,7 +1902,7 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
@@ -1831,7 +1953,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
}
else
{
- USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
}
@@ -1845,7 +1967,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t chnum = (uint32_t)ch_num;
@@ -1853,7 +1975,7 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
uint32_t tmpreg;
USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
- USB_OTG_HCTSIZ_DOPING;
+ USB_OTG_HCTSIZ_DOPING;
/* Set host channel enable */
tmpreg = USBx_HC(chnum)->HCCHAR;
@@ -1879,7 +2001,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
(void)USB_DisableGlobalInt(USBx);
- /* Flush FIFO */
+ /* Flush FIFO */
(void)USB_FlushTxFifo(USBx, 0x10U);
(void)USB_FlushRxFifo(USBx);
@@ -1929,7 +2051,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
/* active Remote wakeup signalling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
@@ -1948,20 +2070,21 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
uint32_t USBx_BASE = (uint32_t)USBx;
/* active Remote wakeup signalling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
-#endif /* defined USB_OTG_FS || defined USB_OTG_HS */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
+
/**
* @}
*/
-
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
/**
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_utils.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_utils.c
index f59d006e5f3f14e48ece557d8b9a84b0c799cf37..302b1c747c8d23197875b3e6c46fb6b1d01e4fba 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_utils.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_ll_utils.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f7xx/soc/stm32f722xx.h b/stm32cube/stm32f7xx/soc/stm32f722xx.h
index eed5ceff81fc777c4833efded99809c1659e6db2..e1d01929fd708fbf07432bb84a28ce5925b1ed34 100644
--- a/stm32cube/stm32f7xx/soc/stm32f722xx.h
+++ b/stm32cube/stm32f7xx/soc/stm32f722xx.h
@@ -828,12 +828,11 @@ typedef struct
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ uint32_t Reserved7; /*!< Reserved 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
} USB_OTG_GlobalTypeDef;
@@ -933,148 +932,148 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
-#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
-#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
-#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
-#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
-#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
-#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
-#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
-#define SRAM1_BASE 0x20010000U /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
-#define SRAM2_BASE 0x2003C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
-#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
-#define FLASH_OTP_BASE 0x1FF07800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
-#define FLASH_OTP_END 0x1FF07A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */
+#define SRAM1_BASE 0x20010000UL /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
+#define SRAM2_BASE 0x2003C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
+#define FLASH_END 0x0807FFFFUL /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FF07800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FF07A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
/* Legacy define */
#define FLASH_BASE FLASHAXI_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
-#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE 0x1FF07A10U /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE 0x1FF07A22U /*!< FLASH Size register base address */
-#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
+#define UID_BASE 0x1FF07A10UL /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FF07A22UL /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FF07BF0UL /*!< Package size register base address */
/* Legacy define */
#define PACKAGESIZE_BASE PACKAGE_BASE
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
/*!< AHB2 peripherals */
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
/* Debug MCU registers base address */
-#define DBGMCU_BASE 0xE0042000U
+#define DBGMCU_BASE 0xE0042000UL
/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE 0x40040000U
-#define USB_OTG_FS_PERIPH_BASE 0x50000000U
-
-#define USB_OTG_GLOBAL_BASE 0x000U
-#define USB_OTG_DEVICE_BASE 0x800U
-#define USB_OTG_IN_ENDPOINT_BASE 0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
-#define USB_OTG_EP_REG_SIZE 0x20U
-#define USB_OTG_HOST_BASE 0x400U
-#define USB_OTG_HOST_PORT_BASE 0x440U
-#define USB_OTG_HOST_CHANNEL_BASE 0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
-#define USB_OTG_PCGCCTL_BASE 0xE00U
-#define USB_OTG_FIFO_BASE 0x1000U
-#define USB_OTG_FIFO_SIZE 0x1000U
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE 0x0000UL
+#define USB_OTG_DEVICE_BASE 0x0800UL
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
+#define USB_OTG_EP_REG_SIZE 0x0020UL
+#define USB_OTG_HOST_BASE 0x0400UL
+#define USB_OTG_HOST_PORT_BASE 0x0440UL
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL
+#define USB_OTG_FIFO_BASE 0x1000UL
+#define USB_OTG_FIFO_SIZE 0x1000UL
/**
* @}
@@ -1199,455 +1198,455 @@ typedef struct
/******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
-#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
#define ADC_SR_AWD ADC_SR_AWD_Msk /*!