Commit ca7ae024 authored by Francois Ramu's avatar Francois Ramu Committed by Kumar Gala
Browse files

stm32cube: update stm32l5 to version V1.4.0 

Update Cube version for STM32FL5xx series
on https://github.com/STMicroelectronics


from version v1.3.1
to version v1.4.0

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent e5090a6f

stm32cube/stm32l5xx/CMakeLists.txt

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD_EX drivers/src/stm32l5xx_ha 
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32l5xx_hal_smartcard.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32l5xx_hal_smartcard_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32l5xx_hal_smbus.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS_EX drivers/src/stm32l5xx_hal_smbus_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32l5xx_hal_spi.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32l5xx_hal_spi_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SRAM drivers/src/stm32l5xx_hal_sram.c)
@@ -81,6 +82,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_EXTI drivers/src/stm32l5xx_ll_e 
zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_FMC drivers/src/stm32l5xx_ll_fmc.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_GPIO drivers/src/stm32l5xx_ll_gpio.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_I2C drivers/src/stm32l5xx_ll_i2c.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_ICACHE drivers/src/stm32l5xx_ll_icache.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPTIM drivers/src/stm32l5xx_ll_lptim.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPUART drivers/src/stm32l5xx_ll_lpuart.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_OPAMP drivers/src/stm32l5xx_ll_opamp.c)

stm32cube/stm32l5xx/README

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubel5.html



Status:

   version v1.3.1

   version v1.4.0



Purpose:

   ST Microelectronics official MCU package for STM32L5 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeL5



Commit:

   c9a55ef9a841f24549e424a2338496681754332b

   1a04696d5732626c678dea940eda2f33b320ab15



Maintained-by:

   External

stm32cube/stm32l5xx/drivers/include/Legacy/stm32_hal_legacy.h

+71 −101
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR



/**

  * @}

  */
@@ -383,7 +382,6 @@ 
#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT



#endif /* STM32H7 */



/**

  * @}

  */
@@ -774,49 +772,6 @@ 
#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)



/** @brief Constants defining the events that can be selected to configure the

  *        set/reset crossbar of a timer output

  */

#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)



#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)



/** @brief Constants defining the event filtering applied to external events

  *        by a timer

  */

#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)



/** @brief Constants defining the DLL calibration periods (in micro seconds)

  */

#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
@@ -896,7 +851,6 @@ 
#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS



/**

  * @}

  */
@@ -969,6 +923,11 @@ 
#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

#endif



#if defined(STM32L4) || defined(STM32L5)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER

#elif defined(STM32G4)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED

#endif



/**

  * @}
@@ -1459,7 +1418,7 @@ 
#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY



#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)

#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)



#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
@@ -1481,7 +1440,7 @@ 
#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT



#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */

#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */

/**

  * @}

  */
@@ -1495,7 +1454,8 @@ 
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode

#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode

#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\

                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect

#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())

#if defined(STM32L0)
@@ -1503,7 +1463,8 @@ 
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())

#endif

#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\

                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
@@ -1538,7 +1499,8 @@ 
#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter

#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter



#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))

#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\

                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))



#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)

#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
@@ -2284,7 +2246,8 @@ 
#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI



#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\

                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())



#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE

#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
@@ -3252,7 +3215,7 @@ 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2



#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)

#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)

#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

#else

#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3381,7 +3344,7 @@ 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)

#else

#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

#endif
@@ -3597,6 +3560,13 @@ 
#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE

#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE



#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)

#define USART_OVERSAMPLING_16               0x00000000U

#define USART_OVERSAMPLING_8                USART_CR1_OVER8



#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \

                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

#endif /* STM32F0 || STM32F3 || STM32F7 */

/**

  * @}

  */

stm32cube/stm32l5xx/drivers/include/stm32l5xx_hal.h

+10 −9
Original line number Diff line number Diff line
@@ -459,7 +459,8 @@ typedef enum 
  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing

  * @retval The new state of __FLAG__ (TRUE or FALSE).

  */

#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)

#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\

                                                & (__FLAG__))!= 0U) ? 1U : 0U)



/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.

  */

stm32cube/stm32l5xx/drivers/include/stm32l5xx_hal_cortex.h

+209 −1
Original line number Diff line number Diff line
@@ -37,6 +37,57 @@ 
  */



/* Exported types ------------------------------------------------------------*/

/** @defgroup CORTEX_Exported_Types CORTEX Exported Types

  * @{

  */



#if (__MPU_PRESENT == 1)

/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition

  * @{

  */

typedef struct

{

  uint8_t                Enable;                /*!< Specifies the status of the region.

                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */

  uint8_t                Number;                /*!< Specifies the number of the region to protect.

                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */

  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */

  uint32_t               LimitAddress;          /*!< Specifies the limit address of the region to protect.                          */

  uint8_t                AttributesIndex;       /*!< Specifies the memory attributes index.

                                                     This parameter can be a value of @ref CORTEX_MPU_Attributes_Number             */

  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.

                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */

  uint8_t                DisableExec;           /*!< Specifies the instruction access status.

                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */

  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.

                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */

} MPU_Region_InitTypeDef;

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition

  * @{

  */

typedef struct

{

  uint8_t                Number;                /*!< Specifies the number of the memory attributes to configure.

                                                     This parameter can be a value of @ref CORTEX_MPU_Attributes_Number              */



  uint8_t                Attributes;            /*!< Specifies the memory attributes vue.

                                                     This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF    */



} MPU_Attributes_InitTypeDef;

/**

  * @}

  */



#endif /* __MPU_PRESENT */



/**

  * @}

  */



/* Exported constants --------------------------------------------------------*/



/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
@@ -67,6 +118,115 @@ 
  * @}

  */



#if (__MPU_PRESENT == 1)

/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control

  * @{

  */

#define  MPU_HFNMI_PRIVDEF_NONE          0U

#define  MPU_HARDFAULT_NMI               2U

#define  MPU_PRIVILEGED_DEFAULT          4U

#define  MPU_HFNMI_PRIVDEF               6U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable

  * @{

  */

#define  MPU_REGION_ENABLE               1U

#define  MPU_REGION_DISABLE              0U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access

  * @{

  */

#define  MPU_INSTRUCTION_ACCESS_ENABLE   0U

#define  MPU_INSTRUCTION_ACCESS_DISABLE  1U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable

  * @{

  */

#define  MPU_ACCESS_NOT_SHAREABLE        0U

#define  MPU_ACCESS_OUTER_SHAREABLE      1U

#define  MPU_ACCESS_INNER_SHAREABLE      3U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes

  * @{

  */

#define  MPU_REGION_PRIV_RW              0U

#define  MPU_REGION_ALL_RW               1U

#define  MPU_REGION_PRIV_RO              2U

#define  MPU_REGION_ALL_RO               3U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number

  * @{

  */

#define  MPU_REGION_NUMBER0              0U

#define  MPU_REGION_NUMBER1              1U

#define  MPU_REGION_NUMBER2              2U

#define  MPU_REGION_NUMBER3              3U

#define  MPU_REGION_NUMBER4              4U

#define  MPU_REGION_NUMBER5              5U

#define  MPU_REGION_NUMBER6              6U

#define  MPU_REGION_NUMBER7              7U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number

  * @{

  */

#define  MPU_ATTRIBUTES_NUMBER0          0U

#define  MPU_ATTRIBUTES_NUMBER1          1U

#define  MPU_ATTRIBUTES_NUMBER2          2U

#define  MPU_ATTRIBUTES_NUMBER3          3U

#define  MPU_ATTRIBUTES_NUMBER4          4U

#define  MPU_ATTRIBUTES_NUMBER5          5U

#define  MPU_ATTRIBUTES_NUMBER6          6U

#define  MPU_ATTRIBUTES_NUMBER7          7U

/**

  * @}

  */



/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes

  * @{

  */

#define  MPU_DEVICE_nGnRnE          0x0U  /* Device, noGather, noReorder, noEarly acknowledge. */

#define  MPU_DEVICE_nGnRE           0x4U  /* Device, noGather, noReorder, Early acknowledge.   */

#define  MPU_DEVICE_nGRE            0x8U  /* Device, noGather, Reorder, Early acknowledge.     */

#define  MPU_DEVICE_GRE             0xCU  /* Device, Gather, Reorder, Early acknowledge.       */



#define  MPU_WRITE_THROUGH          0x0U  /* Normal memory, write-through. */

#define  MPU_NOT_CACHEABLE          0x4U  /* Normal memory, non-cacheable. */

#define  MPU_WRITE_BACK             0x4U  /* Normal memory, write-back.    */



#define  MPU_TRANSIENT              0x0U  /* Normal memory, transient.     */

#define  MPU_NON_TRANSIENT          0x8U  /* Normal memory, non-transient. */



#define  MPU_NO_ALLOCATE            0x0U  /* Normal memory, no allocate.         */

#define  MPU_W_ALLOCATE             0x1U  /* Normal memory, write allocate.      */

#define  MPU_R_ALLOCATE             0x2U  /* Normal memory, read allocate.       */

#define  MPU_RW_ALLOCATE            0x3U  /* Normal memory, read/write allocate. */



#define OUTER(__ATTR__)        ((__ATTR__) << 4U)

#define INNER_OUTER(__ATTR__)  ((__ATTR__) | ((__ATTR__) << 4U))

/**

  * @}

  */



#endif /* __MPU_PRESENT */



/**

  * @}

  */
@@ -96,7 +256,6 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);

void HAL_NVIC_SystemReset(void);

uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);



/**

  * @}

  */
@@ -115,6 +274,19 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);

void HAL_SYSTICK_IRQHandler(void);

void HAL_SYSTICK_Callback(void);



#if (__MPU_PRESENT == 1)

void HAL_MPU_Enable(uint32_t MPU_Control);

void HAL_MPU_Disable(void);

void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit);

void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit);

#ifdef MPU_NS

void HAL_MPU_Enable_NS(uint32_t MPU_Control);

void HAL_MPU_Disable_NS(void);

void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit);

void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit);

#endif /* MPU_NS */

#endif /* __MPU_PRESENT */

/**

  * @}

  */
@@ -144,6 +316,42 @@ void HAL_SYSTICK_Callback(void); 
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \

                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))



#if (__MPU_PRESENT == 1)

#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \

                                     ((STATE) == MPU_REGION_DISABLE))



#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \

                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))



#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \

                                          ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \

                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))



#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \

                                                  ((TYPE) == MPU_REGION_ALL_RW)  || \

                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \

                                                  ((TYPE) == MPU_REGION_ALL_RO))



#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \

                                         ((NUMBER) == MPU_REGION_NUMBER1) || \

                                         ((NUMBER) == MPU_REGION_NUMBER2) || \

                                         ((NUMBER) == MPU_REGION_NUMBER3) || \

                                         ((NUMBER) == MPU_REGION_NUMBER4) || \

                                         ((NUMBER) == MPU_REGION_NUMBER5) || \

                                         ((NUMBER) == MPU_REGION_NUMBER6) || \

                                         ((NUMBER) == MPU_REGION_NUMBER7))



#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER)  (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \

                                           ((NUMBER) == MPU_ATTRIBUTES_NUMBER7))



#endif /* __MPU_PRESENT */



/**

  * @}

  */

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