Commit 85995391 authored by Francois Ramu's avatar Francois Ramu Committed by Kumar Gala
Browse files

stm32cube: update stm32g4 to version V1.4.0 

Update Cube version for STM32G4xx series
on https://github.com/STMicroelectronics


from version v1.3.0
to version v1.4.0

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent e9cd3edc

stm32cube/stm32g4xx/CMakeLists.txt

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI_EX drivers/src/stm32g4xx_h 
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32g4xx_hal_smartcard.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32g4xx_hal_smartcard_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32g4xx_hal_smbus.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS_EX drivers/src/stm32g4xx_hal_smbus_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32g4xx_hal_spi.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32g4xx_hal_spi_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SRAM drivers/src/stm32g4xx_hal_sram.c)

stm32cube/stm32g4xx/README

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubeg4.html



Status:

   version v1.3.0

   version v1.4.0



Purpose:

   ST Microelectronics official MCU package for STM32G4 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeG4



Commit:

   3e5243a22addb3cd323dba491eaf43c85ff448f3

   e762fe2ce800cf6c18a1868a3aabc7e9351751bd



Maintained-by:

   External

stm32cube/stm32g4xx/drivers/include/Legacy/stm32_hal_legacy.h

+78 −101
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR



/**

  * @}

  */
@@ -315,6 +314,11 @@ 
#if defined(STM32G0)

#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1

#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2

#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM

#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM



#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM

#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM

#endif



#if defined(STM32H7)
@@ -591,12 +595,12 @@ 
#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1



#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)

#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)

#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW

#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM

#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH

#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/



#if defined(STM32L1)

#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
@@ -769,49 +773,6 @@ 
#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)



/** @brief Constants defining the events that can be selected to configure the

  *        set/reset crossbar of a timer output

  */

#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)



#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)



/** @brief Constants defining the event filtering applied to external events

  *        by a timer

  */

#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)



/** @brief Constants defining the DLL calibration periods (in micro seconds)

  */

#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
@@ -964,6 +925,11 @@ 
#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

#endif



#if defined(STM32L4) || defined(STM32L5)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER

#elif defined(STM32G4)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED

#endif



/**

  * @}
@@ -1454,7 +1420,7 @@ 
#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY



#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)

#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)



#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
@@ -1476,7 +1442,7 @@ 
#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT



#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */

#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */

/**

  * @}

  */
@@ -1490,7 +1456,8 @@ 
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode

#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode

#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\

                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect

#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())

#if defined(STM32L0)
@@ -1498,7 +1465,8 @@ 
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())

#endif

#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\

                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
@@ -1533,7 +1501,8 @@ 
#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter

#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter



#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))

#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\

                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))



#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)

#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
@@ -2279,7 +2248,8 @@ 
#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI



#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\

                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())



#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE

#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
@@ -3247,7 +3217,7 @@ 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2



#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)

#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)

#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

#else

#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3376,7 +3346,7 @@ 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)

#else

#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

#endif
@@ -3592,6 +3562,13 @@ 
#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE

#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE



#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)

#define USART_OVERSAMPLING_16               0x00000000U

#define USART_OVERSAMPLING_8                USART_CR1_OVER8



#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \

                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

#endif /* STM32F0 || STM32F3 || STM32F7 */

/**

  * @}

  */

stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc.h

+25 −26
Original line number Diff line number Diff line
@@ -384,7 +384,7 @@ typedef struct 
typedef struct __ADC_HandleTypeDef

#else

typedef struct

#endif

#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

{

  ADC_TypeDef                   *Instance;              /*!< Register base address */

  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
@@ -769,7 +769,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
  * @}

  */





/** @defgroup ADC_Event_type ADC Event type

  * @{

  */
@@ -1239,7 +1238,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#else

#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \

  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

#endif

#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */



/**

  * @brief Enable ADC interrupt.
@@ -1667,7 +1666,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
  */

#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \

  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))

#endif

#endif /* ADC_MULTIMODE_SUPPORT */



/**

  * @brief  Helper macro to select the ADC common instance

stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc_ex.h

+8 −6
Original line number Diff line number Diff line
@@ -393,7 +393,7 @@ typedef struct 
                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\

                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\

                             ADC_SMPR1_SMP0)

#endif

#endif /* ADC_SMPR1_SMPPLUS */

/**

  * @}

  */
@@ -482,7 +482,7 @@ typedef struct 
  )

#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)

#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)

#endif

#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */



/**

  * @brief Set the selected injected Channel rank.
@@ -490,7 +490,8 @@ typedef struct 
  * @param __RANKNB__ Rank number.

  * @retval None

  */

#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\

                                                  & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))



/**

  * @brief Configure ADC injected context queue
@@ -658,7 +659,7 @@ typedef struct 
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))

#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)

#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)

#endif

#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */



/**

  * @brief Verify the ADC instance connected to the battery voltage VBAT.
@@ -838,7 +839,7 @@ typedef struct 
                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \

                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \

                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))

#endif

#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */



/**

  * @brief Verify the ADC channel setting in differential mode.
@@ -1360,7 +1361,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 
  * @{

  */

/* Peripheral Control functions ***********************************************/

HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);

HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,

                                                        ADC_InjectionConfTypeDef *sConfigInjected);

#if defined(ADC_MULTIMODE_SUPPORT)

HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);

#endif /* ADC_MULTIMODE_SUPPORT */

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