Commit 1946a197 authored by Erwan Gouriou's avatar Erwan Gouriou
Browse files

stm32cube: update stm32h5 to cube version V1.1.0 

Update Cube version for STM32H5xx series
on https://github.com/STMicroelectronics
from version v1.0.0
to version v1.1.0

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@st.com>
parent 65b64134

stm32cube/stm32h5xx/CMakeLists.txt

+1 −0
Changes for stm32cube/stm32h5xx/CMakeLists.txt: 1 added line, 0 removed lines.
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI drivers/src/stm32h5xx_hal_ 
zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI_EX drivers/src/stm32h5xx_hal_sai_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD drivers/src/stm32h5xx_hal_sd.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD_EX drivers/src/stm32h5xx_hal_sd_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SDRAM drivers/src/stm32h5xx_hal_sdram.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32h5xx_hal_smartcard.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32h5xx_hal_smartcard_ex.c)

zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32h5xx_hal_smbus.c)

stm32cube/stm32h5xx/README

+2 −2
Changes for stm32cube/stm32h5xx/README: 2 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubeh5.html



Status:

   version v1.0.0

   version v1.1.0



Purpose:

   ST Microelectronics official MCU package for STM32H5 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeH5



Commit:



   3d723b2467cdb13c2d780ceaa583b269680b67a4

Maintained-by:

   External

stm32cube/stm32h5xx/drivers/include/Legacy/stm32_hal_legacy.h

+39 −24
Changes for stm32cube/stm32h5xx/drivers/include/Legacy/stm32_hal_legacy.h: 39 added lines, 24 removed lines.
Original line number Diff line number Diff line
@@ -37,16 +37,12 @@ extern "C" { 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR

#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)

#if defined(STM32H7) || defined(STM32MP1)

#define CRYP_DATATYPE_32B               CRYP_NO_SWAP

#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP

#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP

#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP

#if defined(STM32U5)

#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF

#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF

#endif /* STM32U5 */

#endif /* STM32U5 || STM32H7 || STM32MP1 */

#endif /* STM32H7 || STM32MP1 */

/**

  * @}

  */
@@ -143,7 +139,8 @@ extern "C" { 
#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6

#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7

#if defined(STM32L0)

#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */

#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM

                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */

#endif

#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR

#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -242,10 +239,12 @@ extern "C" { 
/** @defgroup CRC_Aliases CRC API aliases

  * @{

  */

#if defined(STM32H5)

#if defined(STM32H5) || defined(STM32C0)

#else

#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */

#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */

#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for

                                                                          inter STM32 series compatibility  */

#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for

                                                                          inter STM32 series compatibility */

#endif

/**

  * @}
@@ -1521,26 +1520,36 @@ extern "C" { 
#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */

#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */

#define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */

#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */

#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */

#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */

#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to

                                                                      the MAC transmitter) */

#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from

                                                                      MAC transmitter */

#define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus

                                                                      or flushing the TxFIFO */

#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status

                                                                   of previous frame or IFG/backoff period to be over */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and

                                                             transmitting a Pause control frame (in full duplex mode) */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input

                                                                      frame for transmission */

#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */

#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control

                                                              de-activate threshold */

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control

                                                              activate threshold */

#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */

#if defined(STM32F1)

#else

#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */

#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */

#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */

#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status

                                                             (or time-stamp) */

#endif

#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */

#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and

                                                              status */

#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */

#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */

#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
@@ -2369,8 +2378,10 @@ extern "C" { 
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose

  * @{

  */

#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */

#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */

#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is

                                                  done into HAL_COMP_Init() */

#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is

                                                  done into HAL_COMP_Init() */

/**

  * @}

  */
@@ -3833,6 +3844,12 @@ extern "C" { 
                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))

#endif   /* STM32F1 */



#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \

    defined (STM32H7) || \

    defined (STM32L0) || defined (STM32L1)

#define __HAL_RTC_TAMPER_GET_IT                   __HAL_RTC_TAMPER_GET_FLAG

#endif



#define IS_ALARM                                  IS_RTC_ALARM

#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK

#define IS_TAMPER                                 IS_RTC_TAMPER
@@ -4227,5 +4244,3 @@ extern "C" { 
#endif



#endif /* STM32_HAL_LEGACY */

stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal.h

+77 −21
Changes for stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal.h: 77 added lines, 21 removed lines.
Original line number Diff line number Diff line
@@ -232,10 +232,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; 
/** @defgroup SBS_NextHDPL_Selection  Next HDPL Selection

  * @{

  */

#define SBS_OBKHDPL_INCR_0                   0x00U

#define SBS_OBKHDPL_INCR_1                   SBS_NEXTHDPLCR_NEXTHDPL_0

#define SBS_OBKHDPL_INCR_2                   SBS_NEXTHDPLCR_NEXTHDPL_1

#define SBS_OBKHDPL_INCR_3                   SBS_NEXTHDPLCR_NEXTHDPL

#define SBS_OBKHDPL_INCR_0                   0x00U                      /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */

#define SBS_OBKHDPL_INCR_1                   SBS_NEXTHDPLCR_NEXTHDPL_0  /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */

#define SBS_OBKHDPL_INCR_2                   SBS_NEXTHDPLCR_NEXTHDPL_1  /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */

#define SBS_OBKHDPL_INCR_3                   SBS_NEXTHDPLCR_NEXTHDPL    /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */

/**

  * @}

  */
@@ -244,14 +244,24 @@ extern HAL_TickFreqTypeDef uwTickFreq; 
/** @defgroup SBS_HDPL_Value  HDPL Value

  * @{

  */

#define SBS_HDPL_VALUE_0                     0x000000B4U

#define SBS_HDPL_VALUE_1                     0x00000051U

#define SBS_HDPL_VALUE_2                     0x0000008AU

#define SBS_HDPL_VALUE_3                     0x0000006FU

#define SBS_HDPL_VALUE_0                     0x000000B4U   /*!< Hide protection level 0 */

#define SBS_HDPL_VALUE_1                     0x00000051U   /*!< Hide protection level 0 */

#define SBS_HDPL_VALUE_2                     0x0000008AU   /*!< Hide protection level 0 */

#define SBS_HDPL_VALUE_3                     0x0000006FU   /*!< Hide protection level 0 */

/**

  * @}

  */



#if defined(SBS_DBGCR_DBG_AUTH_SEC)

/** @defgroup SBS_DEBUG_SEC_Value  Debug sec Value

  * @{

  */

#define SBS_DEBUG_SEC_NSEC                   0x000000B4U   /*!< Debug opening for secure and non-secure */

#define SBS_DEBUG_NSEC                       0x0000003CU   /*!< Debug opening for non-secure only */

/**

  * @}

  */

#endif /* SBS_DBGCR_DBG_AUTH_SEC */



/** @defgroup SBS_Lock_items SBS Lock items

  * @brief SBS items to set lock on
@@ -658,6 +668,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; 
                                         (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8))

#endif /* SBS_FASTMODEPLUS_PB9 */



#define IS_SBS_HDPL(__LEVEL__)          (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \

                                         ((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3))



#define IS_SBS_OBKHDPL_SELECTION(__SELECT__)    (((__SELECT__) == SBS_OBKHDPL_INCR_0)  || \

                                                 ((__SELECT__) == SBS_OBKHDPL_INCR_1)  || \

                                                 ((__SELECT__) == SBS_OBKHDPL_INCR_2)  || \
@@ -765,18 +778,25 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); 
  * @{

  */



/* SBS Control functions  ****************************************************/



/* VREFBUF Control functions  ****************************************************/

#if defined(VREFBUF)

void                 HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);

void                 HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode);

void                 HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

HAL_StatusTypeDef    HAL_EnableVREFBUF(void);

void                 HAL_DisableVREFBUF(void);

#endif /* VREFBUF */



void HAL_SBS_EnableIOAnalogSwitchBooster(void);

void HAL_SBS_DisableIOAnalogSwitchBooster(void);

/**

  * @}

  */



/** @addtogroup HAL_Exported_Functions_Group5

  * @{

  */



/* SBS System Configuration functions  *******************************************/

void                 HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface);

void HAL_SBS_AnalogSwitchSupplyVoltageSelection(uint32_t SBS_BOOSTVDDSEL);

void                 HAL_SBS_EnableVddIO1CompensationCell(void);

void                 HAL_SBS_DisableVddIO1CompensationCell(void);

void                 HAL_SBS_EnableVddIO2CompensationCell(void);
@@ -791,22 +811,59 @@ uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); 
uint32_t             HAL_SBS_GetPMOSVddCompensationValue(void);

uint32_t             HAL_SBS_GetNMOSVddIO2CompensationValue(void);

uint32_t             HAL_SBS_GetPMOSVddIO2CompensationValue(void);

void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection);

uint32_t HAL_SBS_GetEPOCHSelection(void);

void                 HAL_SBS_FLASH_EnableECCNMI(void);

void                 HAL_SBS_FLASH_DisableECCNMI(void);

uint32_t             HAL_SBS_FLASH_ECCNMI_IsDisabled(void);



/**

  * @}

  */



/** @addtogroup HAL_Exported_Functions_Group6

  * @{

  */



/* SBS Boot control functions  ***************************************************/

void                 HAL_SBS_IncrementHDPLValue(void);

uint32_t             HAL_SBS_GetHDPLValue(void);



/**

  * @}

  */



/** @addtogroup HAL_Exported_Functions_Group7

  * @{

  */



/* SBS Hardware secure storage control functions  ********************************/

void                 HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection);

uint32_t             HAL_SBS_GetEPOCHSelection(void);

void                 HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value);

uint32_t             HAL_SBS_GetOBKHDPL(void);

void HAL_SBS_FLASH_EnableECCNMI(void);

void HAL_SBS_FLASH_DisableECCNMI(void);

uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void);



/**

  * @}

  */



/** @addtogroup HAL_Exported_Functions_Group8

  * @{

  */



/** @addtogroup HAL_Exported_Functions_Group5

/* SBS Debug control functions  ***************************************************/

void                 HAL_SBS_OpenAccessPort(void);

void                 HAL_SBS_OpenDebug(void);

HAL_StatusTypeDef    HAL_SBS_ConfigDebugLevel(uint32_t Level);

uint32_t             HAL_SBS_GetDebugLevel(void);

void                 HAL_SBS_LockDebugConfig(void);

void                 HAL_SBS_ConfigDebugSecurity(uint32_t Security);

uint32_t             HAL_SBS_GetDebugSecurity(void);



/**

  * @}

  */





/** @addtogroup HAL_Exported_Functions_Group9

  * @{

  */
@@ -818,7 +875,7 @@ HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); 
  * @}

  */



/** @addtogroup HAL_Exported_Functions_Group6

/** @addtogroup HAL_Exported_Functions_Group10

  * @{

  */
@@ -849,4 +906,3 @@ HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut 
#endif /* __cplusplus */



#endif /* __STM32H5xx_HAL_H */

stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h

+0 −2
Changes for stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h: 0 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -407,5 +407,3 @@ void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const p 
#endif



#endif /* __STM32H5xx_HAL_CORTEX_H */

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